MC-4R512FKK6K-840 [ELPIDA]
512MB 32-bit Direct Rambus DRAM RIMM Module; 512MB 32位直接Rambus的DRAM RIMM模块
| 型号： | MC-4R512FKK6K-840 |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 512MB 32-bit Direct Rambus DRAM RIMM Module |
| 文件： | 总13页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
512MB 32-bit Direct Rambus DRAM RIMM Module
MC-4R512FKK6K (128M words × 16 bits × 2 channels)
Description
Features
The 32-bit Direct Rambus RIMM module is a general-
purpose high-performance lines of memory modules
suitable for use in a broad range of applications
including computer memory, personal computers,
workstations, and other applications where high
bandwidth and latency are required.
• 512MB Direct RDRAM storage and 512 banks total
on module
• 2 independent Direct RDRAM channels, 1 pass
through and 1 terminated on 32-bit RIMM module
• High speed 800MHz Direct RDRAM devices
• 232 edge connector pads with 1mm pad spacing
Module PCB size: 133.35mm × 39.925mm ×
1.27mm
The 32-bit RIMM module consists of 288Mb Direct
Rambus DRAM (Direct RDRAM) devices. These are
extremely high-speed CMOS DRAMs organized as
16M words by 18 bits. The use of Rambus Signaling
Level (RSL) technology permits the use of conventional
system and board design technologies. The 32-bit
RIMM modules support 800MHz transfer rate per pin,
resulting in total module bandwidth of 3.2GB/s.
Gold plated edge connector pads contacts
• Serial Presence Detect (SPD) support
• Operates from a 2.5V (±5%) supply
• Low power and power down self refresh modes
• Separate Row and Column buses for higher
efficiency
The 32-bit RIMM module provides two independent 16
bit memory channels to facilitate compact system
design. The "Thru" Channel enters and exits the
module to support a connection to or from a controller,
memory slot, or termination. The "Term" Channel is
terminated on the module and supports a connection
from a controller or another memory slot.
The RDRAM
sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The
architecture enables the highest
separate control and data buses with independent row
and column control yield over 95% bus efficiency. The
RDRAM device multi-bank architecture supports up to
four simultaneous transactions per device.
Document No. E0267N10 (Ver. 1.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4R512FKK6K
Ordering Information
I/O Freq.
(MHz)
RAS access
time (ns)
Part number
Organization
128M x 16 x 2
Package
Mounted devices
232 edge connector pads
RIMM with heat spreader
Edge connector: Gold plated
16 pieces of µPD488588FF
FBGA (µBGA ) package
MC-4R512FKK6K-840
800
40
Module Pad Names
Pad Signal name
Pad Signal name
Pad
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
Signal name
GND
Pad
Signal name
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
GND
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
SCK_THRU_L
GND
CMD_THRU_L
GND
VTERM
VTERM
GND
VTERM
VTERM
GND
DQA8_THRU_L
GND
DQA7_THRU_L
GND
DQA3_THRU_R
GND
DQA4_THRU_R
GND
DQA6_THRU_L
GND
DQA5_THRU_L
GND
DQA5_THRU_R
GND
DQA6_THRU_R
GND
DQA4_THRU_L
GND
DQA3_THRU_L
GND
DQA7_THRU_R
GND
DQA8_THRU_R
GND
A10 DQA2_THRU_L
A11 GND
B10 DQA1_THRU_L
B11 GND
VDD
VDD
A12 DQA0_THRU_L
A13 GND
B12 CTMN_THRU_L
B13 GND
GND
GND
SCK_THRU_R
GND
CTMN_TERM_L
GND
A14 CFM_THRU_L
A15 GND
B14 CTM_THRU_L
B15 GND
CMD_THRU_R
GND
CTM_TERM_L
GND
A16 CFMN_THRU_L
A17 GND
B16 ROW2_THRU_L
B17 GND
VREF
VCMOS
VDD
A18 ROW1_THRU_L
A19 GND
B18 ROW0_THRU_L
B19 GND
VDD
SVDD
SWP
A20 COL4_THRU_L
A21 GND
B20 COL3_THRU_L
B21 GND
VDD
VDD
SCL
SDA
A22 COL2_THRU_L
A23 GND
B22 COL1_THRU_L
B23 GND
VDD
VDD
SA0
SA1
A24 COL0_THRU_L
A25 GND
B24 DQB0_THRU_L
B25 GND
VDD
VDD
SA2
SIN_TERM
GND
A26 DQB1_THRU_L
A27 GND
B26 DQB2_THRU_L
B27 GND
GND
DQB8_TERM
GND
DQB7_TERM
GND
A28 DQB3_THRU_L
A29 GND
B28 DQB4_THRU_L
B29 GND
DQB6_TERM
GND
DQB5_TERM
GND
A30 DQB5_THRU_L
A31 GND
B30 DQB6_THRU_L
B31 GND
DQB4_TERM
GND
DQB3_TERM
GND
A32 DQB7_THRU_L
A33 GND
B32 DQB8_THRU_L
B33 GND
DQB2_TERM
GND
DQB1_TERM
GND
A34 SOUT_THRU
A35 GND
B34 SIN_THRU
B35 GND
DQB0_TERM
GND
COL0_TERM
GND
A36 DQB8_THRU_R
B36 DQB7_THRU_R
Preliminary Data Sheet E0267N10 (Ver. 1.0)
2
MC-4R512FKK6K
Pad Signal name
A37 GND
Pad Signal name
B37 GND
Pad
A95
A96
A97
A98
A99
Signal name
COL1_TERM
GND
Pad
B95
B96
B97
B98
B99
Signal name
COL2_TERM
GND
A38 DQB6_THRU_R
A39 GND
B38 DQB5_THRU_R
B39 GND
COL3_TERM
GND
COL4_TERM
GND
A40 DQB4_THRU_R
A41 GND
B40 DQB3_THRU_R
B41 GND
ROW0_TERM
ROW1_TERM
A42 DQB2_THRU_R
A43 GND
B42 DQB1_THRU_R
B43 GND
A100 GND
B100 GND
A101 ROW2_TERM
A102 GND
B101 CFMN_TERM
B102 GND
A44 DQB0_THRU_R
A45 GND
B44 COL0_THRU_R
B45 GND
A103 CTM_TERM_R
A104 GND
B103 CFM_TERM
B104 GND
A46 COL1_THRU_R
A47 GND
B46 COL2_THRU_R
B47 GND
A105 CTMN_TERM_R
A106 GND
B105 DQA0_TERM
B106 GND
A48 COL3_THRU_R
A49 GND
B48 COL4_THRU_R
B49 GND
A107 DQA1_TERM
A108 GND
B107 DQA2_TERM
B108 GND
A50 ROW0_THRU_R
A51 GND
B50 ROW1_THRU_R
B51 GND
A109 DQA3_TERM
A110 GND
B109 DQA4_TERM
B110 GND
A52 ROW2_THRU_R
A53 GND
B52 CFMN_THRU_R
B53 GND
A111 DQA5_TERM
A112 GND
B111 DQA6_TERM
B112 GND
A54 CTM_THRU_R
A55 GND
B54 CFM_THRU_R
B55 GND
A113 DQA7_TERM
A114 GND
B113 DQA8_TERM
B114 GND
A56 CTMN_THRU_R
A57 GND
B56 DQA0_THRU_R
B57 GND
A115 CMD_TERM
A116 GND
B115 SCK_TERM
B116 GND
A58 DQA1_THRU_R
B58 DQA2_THRU_R
Preliminary Data Sheet E0267N10 (Ver. 1.0)
3
MC-4R512FKK6K
Module Connector Pad Description
Module
Signal
connector pads
A14
I/O
I
Type
RSL
Description
Clock From Master. Connects to left RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Positive polarity.
CFM_THRU_L
Clock From Master. Connects to right RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Positive polarity.
Clock From Master. Connects to left RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Negative polarity.
CFM_THRU_R
CFMN_THRU_L
CFMN_THRU_R
CMD_THRU_L
CMD_THRU_R
B54
A16
B52
B2
I
I
I
I
I
I
I
I
I
I
I
RSL
RSL
Clock From Master. Connects to right RDRAM device on
"Thru" Channel. Interface clock used for receiving RSL
signals from the controller. Negative polarity.
Serial Command Input used to read from and write to the
control registers. Also used for power management.
Connects to left RDRAM device on "Thru" Channel.
RSL
VCMOS
VCMOS
RSL
Serial Command Input used to read from and write to the
control registers. Also used for power management.
Connects to right RDRAM device on "Thru" Channel.
"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to left
RDRAM device on "Thru" Channel.
A73
COL4_THRU_L..
COL0_THRU_L
A20, B20, A22, B22,
A24
"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Thru" Channel.
Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.
COL4_THRU_R..
COL0_THRU_R
B48, A48, B46, A46,
B44
RSL
CTM_THRU_L
CTM_THRU_R
CTMN_THRU_L
CTMN_THRU_R
B14
A54
B12
A56
RSL
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.
Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.
RSL
RSL
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.
RSL
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Thru” Channel. Connects to left RDRAM device on "Thru"
Channel. DQA8_THRU_L is non-functional on modules.
DQA8_THRU_L..
DQA0_THRU_L
A4, B4, A6, B6, A8,
B8, A10, B10, A12
I/O
RSL
RSL
RSL
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Thru” Channel. Connects to right RDRAM device on
"Thru" Channel. DQA8_THRU_R is non-functional on
modules.
B67, A67, B65, A65,
B63, A63, B58, A58, I/O
B56
DQA8_THRU_R..
DQA0_THRU_R
B32, A32, B30, A30,
B28, A28, B26, A26,
B24
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Thru” Channel. Connects to left RDRAM device on "Thru"
Channel. DQB8_THRU_L is non-functional on modules.
DQB8_THRU_L..
DQB0_THRU_L
I/O
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Thru” Channel. Connects to right RDRAM device on
"Thru" Channel. DQB8_THRU_R is non-functional on
modules.
A36, B36, A38, B38,
A40, B40, A42, B42, I/O
A44
DQB8_THRU_R..
DQB0_THRU_R
RSL
RSL
Row bus. 3-bit bus containing control and address information
for row accesses. Connects to left RDRAM device on "Thru"
Channel.
ROW2_THRU_L..
ROW0_THRU_L
B16, A18, B18
I
Preliminary Data Sheet E0267N10 (Ver. 1.0)
4
MC-4R512FKK6K
Module
Signal
connector pads
I/O
I
Type
RSL
Description
Row bus. 3-bit bus containing control and address information
for row accesses. Connects to right RDRAM device on "Thru"
Channel.
Serial Clock input. Clock source used to read from and write
to "Thru" Channel RDRAM control registers. Connects to left
RDRAM device on "Thru" Channel.
ROW2_THRU_R..
ROW0_THRU_R
A52, B50, A50
A2
SCK_THRU_L
SCK_THRU_R
SIN_THRU
I
VCMOS
VCMOS
VCMOS
VCMOS
RSL
Serial Clock input. Clock source used to read from and write
to "Thru" Channel RDRAM control registers. Connects to right
RDRAM device on "Thru" Channel.
A71
I
"Thru" Channel Serial I/O for reading from and writing to the
control registers. Attaches to SIO0 of right RDRAM device on
"Thru" Channel.
B34
I/O
"Thru" Channel Serial I/O for reading from and writing to the
control registers. Attaches to SIO1 of left RDRAM device on
"Thru" Channel.
SOUT_THRU
CFM_TERM
CFMN_TERM
CMD_TERM
A34
I/O
Clock from master. Connects to right RDRAM device on
"Term" Channel. Interface clock used for receiving RSL
signals from the controller. Positive polarity.
B103
B101
A115
I
I
I
I
I
I
I
I
Clock from master. Connects to right RDRAM device on
"Term" Channel. Interface clock used for receiving RSL
signals from the controller. Negative polarity.
RSL
Serial Command Input used to read from and write to the
control registers. Also used for power management.
Connects to right RDRAM device on "Term" Channel.
VCMOS
RSL
"Term" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Term" Channel.
COL4_TERM..
COL0_TERM
B97, A97, B95, A95,
B93
Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.
CTM_TERM_L
CTM_TERM_R
CTMN_TERM_L
CTMN_TERM_R
B73
RSL
Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Positive polarity.
A103
B71
RSL
Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.
RSL
Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to
the controller. Negative polarity.
A105
RSL
"Term" Channel Data bus A. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Term” Channel. Connects to right RDRAM device on
"Term" Channel. DQA8_TERM is non-functional on modules.
"Term" Channel Data bus B. A 9-bit bus carrying a byte of
read or write data between the controller and RDRAM devices
on “Term” Channel. Connects to right RDRAM device on
"Term" Channel. DQB8_TERM is non-functional on modules.
B113, A113, B111,
A111, B109, A109, I/O
B107, A107, B105
DQA8_TERM..
DQA0_TERM
RSL
RSL
A85, B85, A87, B87,
A89, B89, A91, B91, I/O
A93
DQB8_TERM..
DQB0_TERM
"Term" Channel Row bus. 3-bit bus containing control and
address information for row accesses. Connects to right
RDRAM device on "Term" Channel.
ROW2_TERM..
ROW0_TERM
A101, B99, A99
B115
I
RSL
Serial Clock input. Clock source used to read from and write
to "Term" Channel RDRAM control registers. Connects to
right RDRAM device on "Term" Channel.
SCK_TERM
I
VCMOS
VCMOS
"Term" Channel Serial I/O for reading from and writing to the
control registers. Attaches to SIO0 of left RDRAM device on
"Term" Channel.
SIN_TERM
VTERM
B83
I/O
A60, B60, A61, B61
"Term" Channel Termination voltage.
Preliminary Data Sheet E0267N10 (Ver. 1.0)
5
MC-4R512FKK6K
Module
Signal
connector pads
I/O
Type
Description
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A35, A37, A39, A41, A43,
A45, A47, A49, A51, A53, A55, A57,
A59, A62, A64, A66, A68, A70, A72,
A74, A84, A86, A88, A90, A92, A94,
A96, A98, A100, A102, A104, A106,
A108, A110, A112, A114, A116, B1,
B3, B5, B7, B9, B11, B13, B15, B17,
B19, B21, B23, B25, B27, B29, B31,
B33, B35, B37, B39, B41, B43, B45,
B47, B49, B51, B53, B55, B57, B59,
B62, B64, B66, B68, B70, B72, B74,
B84, B86, B88, B90, B92, B94, B96,
B98, B100, B102, B104, B106,
Ground reference for RDRAM core and
interface.
GND
B108, B110, B112, B114, B116
SA0
SA1
SA2
SCL
A81
B81
A83
A79
I
I
I
I
SVDD
SVDD
SVDD
SVDD
Serial Presence Detect Address 0
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
Serial Presence Detect Data (Open Collector
I/O).
SDA
B79
A77
I/O
SVDD
SPD Voltage. Used for signals SCL, SDA,
SWE, SA0, SA1 and SA2.
SVDD
Serial Presence Detect Write Protect (active
high). When low, the SPD can be written as
well as read.
SWP
B77
B75
I
SVDD
CMOS I/O Voltage. Used for signals CMD,
SCK, SIN, SOUT.
VCMOS
VDD
A69, B69, A76, B76, A78, B78, A80,
B80, A82, B82
Supply voltage for the RDRAM core and
interface logic.
Logic threshold reference voltage for both
"Thru" Channel and "Term" Channel RSL
signals.
VREF
A75
Preliminary Data Sheet E0267N10 (Ver. 1.0)
6
MC-4R512FKK6K
Block Diagram
SIO0
SIO1
SCK
CMD
VREF
Left RDRAM Device of "Thru" Channel
Right RDRAM Device of "Thru" Channel
SIO0
SIO1
SCK
CMD
VREF
CTMN_TERM_L
CTM_TERM_L
VTERM
SIO0
SIO1
SCK
CMD
VREF
Left RDRAM Device of "Term" Channel
Right RDRAM Device of "Term" Channel
SVDD
VCC
U0
SCL
SCL
WP
A0
SDA
A2
SDA
SWP
A1
SA0
SA1
SA2
SIO0
SIO1
SCK
CMD
VREF
Serial PD
Preliminary Data Sheet E0267N10 (Ver. 1.0)
7
MC-4R512FKK6K
Electrical Specifications
Absolute Maximum Ratings
Symbol
VI,ABS
Parameter
MIN.
MAX.
Unit
V
Voltage applied to any RSL or CMOS signal pad with
respect to GND
−0.3
VDD + 0.3
VDD,ABS
TSTORE
Voltage on VDD with respect to GND
Storage temperature
−0.5
−50
VDD + 1.0
+100
V
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Recommended Electrical Conditions
Symbol
VDD
Parameter and conditions
Supply voltageNote
MIN.
MAX.
Unit
V
2.50 − 0.13
2.50 + 0.13
CMOS I/O power supply at pad
2.5V controllers
VCMOS
V
VDD
VDD
1.8V controllers
1.8 − 0.1
1.8 + 0.2
VREF
Reference voltageNote
1.4 − 0.2
2.2
1.4 + 0.2
3.6
V
V
V
SVDD
VTERM
Serial Presence Detector- positive power supply
Termination Voltage
1.89 − 0.09
1.89 + 0.09
Note: See Direct RDRAM datasheet for more details.
Preliminary Data Sheet E0267N10 (Ver. 1.0)
8
MC-4R512FKK6K
AC Electrical Specifications
Symbol
ZL
Parameter and ConditionsNote1
MIN.
25.2
23.8
TYP.
28.0
28.0
MAX.
30.8
32.2
Unit
Ω
Module Impedance of RSL signals
ZUL−CMOS
Module Impedance of SCK and CMD signals
Ω
Average clock delay from finger to finger of all RSL clock
nets (CTM, CTMN,CFM, and CFMN) Note2
TPD
1.36
+21
ns
ps
ps
Propagation delay variation of RSL signals with respect to
TPD Note1, 3
∆TPD
−21
Propagation delay variation of SCK signal with respect to
an average clock delay Note1
∆TPD-CMOS
−250
−200
+250
Propagation delay variation of CMD signal with respect to
SCK signal
∆TPD- SCK,CMD
Vα/VIN
+200
16.0
4.0
ps
%
%
Attenuation Limit
Forward crosstalk coefficient
(300ps input rise time 20% - 80%)
VXF/VIN
Backward crosstalk coefficient
(300ps input rise time 20% - 80%)
VXB/VIN
RDC
2.0
0.8
%
DC Resistance Limit
Ω
Notes 1. Specifications apply per channel.
2. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets
(CTM, CTMN, CFM, and CFMN).
3. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted ∆TPD Specification” table.
Adjusted ∆TPD Specification
Absolute
Symbol Parameter and conditions
Propagation delay variation of RSL signals with
respect to TPD
Adjusted MIN./MAX.
MIN.
MAX.
30
Unit
ps
∆TPD
+/− [17+(18*N*∆Z0)] Note
−30
Note N = Number of RDRAM devices installed on the RIMM module.
∆Z0 = delta Z0% = (MAX. Z0 - MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
Preliminary Data Sheet E0267N10 (Ver. 1.0)
9
MC-4R512FKK6K
RIMM Module Current Profile
IDD
RIMM module power conditions Note1
MAX.
1469
Unit
mA
One RDRAM device per channel in Read Note2
balance in NAP mode
,
,
,
IDD1
One RDRAM device per channel in Read Note2
balance in Standby mode
IDD2
IDD3
IDD4
IDD5
IDD6
2670
3300
1589
2790
3420
mA
mA
mA
mA
mA
One RDRAM device per channel in Read Note2
balance in Active mode
One RDRAM device per channel in Write,
balance in NAP mode
One RDRAM device per channel in Write,
balance in Standby mode
One RDRAM device per channel in Write,
balance in Active mode
Notes 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage
patterns. Please refer to specific RIMM module vendor data sheets for additional information. Power does
not include Refresh Current. Max current computed for x16 256Mb RDRAM components. x18 288Mb
RDRAM components use 8 mA more current per RDRAM device in Read and 60mA more current per
RDRAM device in Write.
2. I/O current is a function of the % of 1’s, to add I/O power for 50 % 1’s for a x16 need to add 257mA for the
following : VDD = 2.5V, VTERM = 1.8V, VREF = 1.4V and VDIL = VREF − 0.5V.
Preliminary Data Sheet E0267N10 (Ver. 1.0)
10
MC-4R512FKK6K
Physical Outline
A
B
E
F
G
C
J
Pad A1
Pad A116
H
K
D
Description
PCB length
Item
A
min.
typ.
max.
Unit
mm
133.22 133.35 133.48
PCB height
B
C
D
E
F
34.795 34.925 35.055
mm
mm
mm
mm
mm
mm
mm
mm
mm
Center-center pad width from pad A1 to A60,
B1 to B60
-
59.00
78.170
17.78
1.27
-
-
Spacing from PCB left edge to connector key notch
-
-
Spacing from contact pad PCB edge
to side edge retainer notch
PCB thickness
-
-
1.17
1.37
3.09
-
Heat spreader thickness from PCB surface (one side) to
heat spreader top surface
G
H
J
-
-
-
-
Center-center pad width from pad A61 to A68,
B61 to B68
7.00
47.00
-
Center-center pad width from pad A69 to A116,
B69 to B116
-
RIMM thickness
K
7.55
ECA-TS2-0063-01
Preliminary Data Sheet E0267N10 (Ver. 1.0)
11
MC-4R512FKK6K
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E0267N10 (Ver. 1.0)
12
MC-4R512FKK6K
Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc.
RIMM, SO-RIMM, RaSer and QRSL are trademarks of Rambus Inc.
µBGA is a registered trademark of Tessera, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0267N10 (Ver. 1.0)
13
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