EKTF5616QN24 [ELAN]
8-Bit Microcontroller;
| 型号： | EKTF5616QN24 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller 微控制器 |
| 文件： | 总170页 (文件大小：5766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Contents
eKTF5616/08
8-Bit
Microcontroller
IC Product
Specification
DOC. VERSION 1.3
ELAN MICROELECTRONICS CORP.
September 2019
IC Product Specification (V1.3) 09.10.2019
iii
Contents
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2019 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Hsinchu Science Park
Hsinchu, TAIWAN 308
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F, World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Elan Information
Technology Group
(U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Fax: +852 2723-7780
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
Room 703, No. 3, Lane88,
Shengrong Road,
Pudong New Area,
Shanghai, China 201203
Tel : 86-21-50803866
elan-sh@elanic.com.cn
8A F, Microprofit Building, 6
Gaoxin Road, Shenzhen Hi-tech
Industrial Park, Nanshan (South
Area), Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
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IC Product Specification (V1.3) 09.10.2019
Contents
Contents
1
2
3
General Description.........................................................................................1
Features ..........................................................................................................1
Pin Assignment................................................................................................2
3.1 Package: SOP 28 .............................................................................................2
3.2 Package: SOP 20 .............................................................................................2
3.3 Package: QFN 24 .............................................................................................3
3.4 Package: SOP 16 .............................................................................................3
3.5 Package: SSOP 20...........................................................................................4
4
5
Pin Description ................................................................................................5
System Overview.............................................................................................8
5.1 Memory Map.....................................................................................................8
5.2 Block Diagram ..................................................................................................9
6
Functional Description................................................................................10
6.1 Operational Registers .....................................................................................10
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
R0: IAR (Indirect Addressing Register) ..........................................................10
R1: BSR (Bank Selection Control Register) ...................................................10
R2: PCL (Program Counter Low) ...................................................................11
R3: SR (Status Register)................................................................................16
R4: RSR (RAM Select Register).....................................................................17
Bank 0 R5 ~ R8: (Port 5 ~ Port 8) ..................................................................17
Bank 0 R9 ~ RA: (Reserved)..........................................................................17
Bank 0 RB~RD: (IOCR5 ~ IOCR7).................................................................17
Bank 0 RE: OMCR (Operating Mode Control Register).................................17
6.1.10 Bank 0 RF: EIESCR (External Interrupt Edge Select Control Register) ........19
6.1.11 Bank 0 R10: WUCR1 (Wake-up Control Register 1)......................................20
6.1.12 Bank 0 R11: WUCR2 (Wake-up Control Register 2)......................................20
6.1.13 Bank 0 R12: WUCR3 (Wake-up Control Register 3)......................................21
6.1.14 Bank 0 R13: (Reserved) .................................................................................21
6.1.15 Bank 0 R14: SFR1 (Status Flag Register 1) ..................................................22
6.1.16 Bank 0 R15: SFR2 (Status Flag Register 2) ..................................................22
6.1.17 Bank 0 R16: SFR3 (Status Flag Register 3) ..................................................22
6.1.18 Bank 0 R17: SFR4 (Status Flag Register 4) ..................................................23
6.1.19 Bank 0 R18: (Reserved) .................................................................................23
6.1.20 Bank 0 R19: SFR6 (Status Flag Register 6)...................................................23
6.1.21 Bank 0 R1A: (Reserved).................................................................................24
6.1.22 Bank 0 R1B: IMR1 (Interrupt Mask Register 1)..............................................24
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6.1.23 Bank 0 R1C: IMR2 (Interrupt Mask Register 2)..............................................25
6.1.24 Bank 0 R1D: IMR3 (Interrupt Mask Register 3)..............................................25
6.1.25 Bank 0 R1E: IMR4 (Interrupt Mask Register 4)..............................................26
6.1.26 Bank 0 R1F: (Reserved).................................................................................27
6.1.27 Bank 0 R20: IMR6 (Interrupt Mask Register 6) ..............................................27
6.1.28 Bank 0 R21: WDTCR (Watchdog Timer Control Register).............................28
6.1.29 Bank 0 R22: TCCCR (TCC Control Register) ................................................28
6.1.30 Bank 0 R23: TCCD (TCC Data Register).......................................................29
6.1.31 Bank 0 R24: TC1CR1 (Timer 1 Control Register 1) .......................................29
6.1.32 Bank 0 R25: TC1CR2 (Timer 1 Control Register 2) .......................................30
6.1.33 Bank 0 R26: TC1DA (Timer/Counter 1 DATA Buffer A) ..................................32
6.1.34 Bank 0 R27: TC1DB (Timer/Counter 1 DATA Buffer B)..................................32
6.1.35 Bank 0 R28 ~ R2F: (Reserved) ......................................................................32
6.1.36 Bank 0 R30: I2CCR1 (I2C Status and Control Register 1) ............................32
6.1.37 Bank 0 R31: I2CCR2 (I2C Status and Control Register 2) ............................33
6.1.38 Bank 0 R32: I2CSA (I2C Slave Address Register).........................................34
6.1.39 Bank 0 R33: I2CDB (I2C Data Buffer Register) .............................................35
6.1.40 Bank 0 R34: I2CDAL (I2C Device Address Register).....................................35
6.1.41 Bank 0 R35: I2CDAH (I2C Device Address Register)....................................35
6.1.42 Bank 0 R36: SPICR (SPI Control Register) ...................................................35
6.1.43 Bank 0 R37: SPIS (SPI Status Register)........................................................36
6.1.44 Bank 0 R38: SPIR (SPI Read Buffer Register) ..............................................37
6.1.45 Bank 0 R39: SPIW (SPI Write Buffer Register)..............................................37
6.1.46 Bank 0 R3A ~ R3D: (Reserved) .....................................................................37
6.1.47 Bank 0 R3E: ADCR1 (ADC Control Register 1) .............................................38
6.1.48 Bank 0 R3F: ADCR2 (ADC Control Register 2) .............................................39
6.1.49 Bank 0 R40: ADISR (Analog to Digital Converter Input Channel Selection
Register) .........................................................................................................40
6.1.50 Bank 0 R41: ADER1 (Analog to Digital Converter Input Control Register 1) .40
6.1.51 Bank 0 R42: (Reserved) .................................................................................41
6.1.52 Bank 0 R43: ADDL (Low Byte of Analog to Digital Converter Data)...............41
6.1.53 Bank 0 R44: ADDH (High Byte of Analog to Digital Converter Data) .............42
6.1.54 Bank 0 R45: ADCVL (Low Byte of Analog to Digital Converter Comparison) 42
6.1.55 Bank 0 R46: ADCVH (High Byte of Analog to Digital Converter Comparison)
........................................................................................................................42
6.1.56 Bank 0 R47~4F: (Reserved)...........................................................................42
6.1.57 Bank 1 R5: IOCR8..........................................................................................42
6.1.58 Bank 1 R6 ~ R7: (Reserved) ..........................................................................42
6.1.59 Bank 1 R8: P5PHCR (Port 5 Pull-high Control Register)...............................43
6.1.60 Bank 1 R9: P6PHCR (Port 6 Pull-high Control Register)...............................43
6.1.61 Bank 1 RA: P78PHCR (Ports 7~8 Pull-high Control Register).......................44
6.1.62 Bank 1 RB: P5PLCR (Port 5 Pull-low Control Register).................................44
6.1.63 Bank 1 RC: P6PLCR (Port 6 Pull-low Control Register) ................................44
6.1.64 Bank 1 RD: P78PLCR (Ports 7~8 Pull-low Control Register) ........................45
6.1.65 Bank 1 RE: P5HDSCR (Port 5 High Drive/Sink Control Register) .................45
6.1.66 Bank 1 RF: P6HDSCR (Port 6 High Drive/Sink Control Register) .................46
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IC Product Specification (V1.3) 09.10.2019
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6.1.67 Bank 1 R10: P78HDSCR (Port 7~8 High Drive/Sink Control Register) .........46
6.1.68 Bank 1 R11: P5ODCR (Port 5 Open-Drain Control Register) ........................46
6.1.69 Bank 1 R12: P6ODCR (Port 6 Open-Drain Control Register)........................47
6.1.70 Bank 1 R13: P78ODCR (Ports 7~8 Open-Drain Control Register)................47
6.1.71 Bank 1 R14 ~ R15: (Reserved) ......................................................................47
6.1.72 Bank 1 R16: PWMSCR (PWM Source Clock Control Register) ....................47
6.1.73 Bank 1 R17: PWMACR (PWMA Control Register).........................................48
6.1.74 Bank 1 R18: PRDAL (Low Byte of PWMA Period) .........................................48
6.1.75 Bank 1 R19: PRDAH (High Byte of PWMA Period)........................................49
6.1.76 Bank 1 R1A: DTAL (Low Byte of PMWA Duty)...............................................49
6.1.77 Bank 1 R1B: DTAH (High Byte of PMWA Duty) .............................................49
6.1.78 Bank 1 R1C: TMRAL (Low Byte of Timer 1)...................................................49
6.1.79 Bank 1 R1D: TMRAH (High Byte of Timer 1) .................................................49
6.1.80 Bank 1 R1E: PWMBCR (PWMB Control Register) ........................................50
6.1.81 Bank 1 R1F: PRDBL (Low Byte of PWMB Period).........................................50
6.1.82 Bank 1 R20: PRDBH (High Byte of PWMB Period) .......................................51
6.1.83 Bank 1 R21: DTBL (Low Byte of PMWB Duty)...............................................51
6.1.84 Bank 1 R22: DTBH (High Byte of PMW2 Duty)..............................................51
6.1.85 Bank 1 R23: TMRBL (Low Byte of Timer B)...................................................51
6.1.86 Bank 1 R24: TMRBH (High Byte of Timer 2)..................................................51
6.1.87 Bank 1 R25 ~ R32: (Reserved) ......................................................................51
6.1.88 Bank 1 R33: URCR (UART Control Register) ................................................52
6.1.89 Bank 1 R34: URS (UART Status Register) ....................................................53
6.1.90 Bank 1 R35: URTD (UART Transmit Data Buffer Register) ...........................53
6.1.91 Bank 1 R36: URRDL (UART Receive Data Low Buffer Register)..................54
6.1.92 Bank 1 R37: URRDH (UART Receive Data High Buffer Register) ................54
6.1.93 Bank 1 R38 ~ R3F: (Reserved) ......................................................................54
6.1.94 Bank 1 R40: EECR1 (EEPROM Control Register 1)......................................54
6.1.95 Bank 1 R41: EECR2 (EEPROM Control Register 2)......................................55
6.1.96 Bank 1 R42: EERA (EEPROM Address) ........................................................55
6.1.97 Bank 1 R43: EERD (EEPROM Data) .............................................................55
6.1.98 Bank 1 R44: FLKR (Flash Key Register for Table write use) .........................55
6.1.99 Bank 1 R45: TBPTL (Table Point Low Register) ............................................56
6.1.100 Bank 1 R46: TBPTH (Table Point High Register)...........................................56
6.1.101 Bank 1 R47: STKMON (Stack Pointer)...........................................................56
6.1.102 Bank 1 R48: PCH (Program Counter High)....................................................56
6.1.103 Bank 1 R49: HLVDCR (High / Low Voltage Detector Control Register).........57
6.1.104 Bank 1 R4A~ R4C: (Reserved) ......................................................................58
6.1.105 Bank 1 R4D: TBWCR (Table Write Control Register).....................................58
6.1.106 Bank 1 R4E: TBWAL (Table Write start Address Low byte) ...........................58
6.1.107 Bank 1 R4F: TBWAH (Table Write start Address High byte)..........................59
6.1.108 Bank 2 R5: TKAPC (Touch Key Group A Pin Control Register) .....................59
6.1.109 Bank 2 R6: TKBPC (Touch Key Group B Pin Control Register).....................60
6.1.110 Bank 2 R7: TKASCR (Touch Key Group A Select Control Register)..............61
6.1.111 Bank 2 R8: TKBSCR (Touch Key Group B Select Control Register) .............62
6.1.112 Bank 2 R9 ~ RC: (Reserved)..........................................................................62
IC Product Specification (V1.3) 09.10.2019
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Contents
6.1.113 Bank 2 RD: TKCR (Touch Key Control Register) ...........................................62
6.1.114 Bank 2 RE: TKCCR (Touch Key Calculate Cycle Register) ...........................63
6.1.115 Bank 2 RF: TKCSR (Touch Key Calculate Step Register) .............................63
6.1.116 Bank 2 R10: TKCTR (Touch Key Calculate Time Register) ...........................63
6.1.117 Bank 2 R11: TKSWR (Touch Key Sensing Window Register) .......................64
6.1.118 Bank 2 R12: TKAH (The Most Significant Byte of A Group Touch Key Buffer)
........................................................................................................................64
6.1.119 Bank 2 R13: TKAL (The Least Significant Byte of A Group Touch Key Buffer)
........................................................................................................................64
6.1.120 Bank 2 R14: TKBH (The Most Significant Byte of B Group Touch Key Buffer)
........................................................................................................................64
6.1.121 Bank 2 R15: TKBL (The Least Significant Byte of B Group Touch Key Buffer)
........................................................................................................................64
6.1.122 Bank 2 R16: TKSCR (Touch Key idle Scan Control Register) .......................65
6.1.123 Bank 2 R17: TKA1WBH (TK Group A idle Scan Wakeup Base High byte
Register 1) ......................................................................................................66
6.1.124 Bank 2 R18: TKA1WBL (TK Group A idle Scan Wakeup Base Low byte
Register 1) ......................................................................................................66
6.1.125 Bank 2 R19: TKA1WR (Touch Key of Group A idle scan Wakeup Range
Register 1) ......................................................................................................66
6.1.126 Bank 2 R1A: TKA2WBH (TK Group A idle Scan Wakeup Base High byte
Register 2) ......................................................................................................66
6.1.127 Bank 2 R1B: TKA2WBL (TK Group A idle Scan Wakeup Base Low byte
Register 2) ......................................................................................................67
6.1.128 Bank 2 R1C: TKA2WR (Touch Key of Group A idle scan Wakeup Range
Register 2) ......................................................................................................67
6.1.129 Bank 2 R1D: TKB1WBH (TK Group B idle Scan Wakeup Base High byte
Register 1) ......................................................................................................67
6.1.130 Bank 2 R1E: TKB1WBL (TK Group B idle Scan Wakeup Base Low byte
Register 1) ......................................................................................................67
6.1.131 Bank 2 R1F: TKB1WR (Touch Key of Group B idle scan Wakeup Range
Register 1) ......................................................................................................68
6.1.132 Bank 2 R20: TKB2WBH (TK Group B idle Scan Wakeup Base High byte
Register 2) ......................................................................................................68
6.1.133 Bank 2 R21: TKB2WBL (TK Group B idle Scan Wakeup Base Low byte
Register 2) ......................................................................................................68
6.1.134 Bank 2 R22: TKB2WR (Touch Key of Group B idle scan Wakeup Range
Register 2) ......................................................................................................68
6.1.135 Bank 2 R23 ~ R46: (Reserved) ......................................................................69
6.1.136 Bank 2 R47: LOCKPR (Lock Page Number Register) ...................................69
6.1.137 Bank 2 R48: LOCKCR (Lock Control Register)..............................................69
6.1.138 Bank 2 R49 ~ R4F: (Reserved) ......................................................................69
6.1.139 R50~R7F, Banks 0~3 R80~RFF.....................................................................69
6.2 TCC/WDT and Prescaler ................................................................................70
6.3 I/O Ports .........................................................................................................71
6.3.1
Usage of Ports 5~8 Input Change Wake-up/Interrupt Function .....................73
6.4 Reset and Wake-up ........................................................................................74
6.4.1 Summary of Wake-up and Interrupt Mode Operation...........................................75
6.4.2
The Status of RST, T, and P of the Status Register .......................................78
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IC Product Specification (V1.3) 09.10.2019
Contents
6.4.3
Summary of Register Initial Values after Reset..............................................79
6.5 Interrupt ..........................................................................................................92
6.6 A/D Converter.................................................................................................94
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
ADC Data Register .........................................................................................95
A/D Sampling Time.........................................................................................95
A/D Conversion Time......................................................................................95
ADC Operation during Sleep Mode................................................................96
Programming Process/Considerations...........................................................96
Programming Process for Detecting Internal VDD.........................................97
6.7 Touch Key Sensor Function ............................................................................98
6.7.1
6.7.2
6.7.3
Touch Key Function Block & Control Register................................................98
Touch Key Operation ....................................................................................102
Touch Key Idle-Scan mode...........................................................................103
6.8 Dual Set of PWM (Pulse Width Modulation)..................................................105
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
Overview.......................................................................................................105
Control Register............................................................................................106
Increment Timer Counter (TMRX: TMRxH/TMRxL) .....................................107
PWM Time Period (PRDX: PRDxL/H) ..........................................................107
PWM Duty Cycle (DTX: DTxH/DT1L)..........................................................107
PWM Programming Process/Steps..............................................................108
6.9 Timer ............................................................................................................109
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
Timer/Counter Mode.....................................................................................109
Window Mode............................................................................................... 111
Capture Mode...............................................................................................112
Programmable Divider Output Mode and Pulse Width Modulation Mode....113
Buzzer Mode.................................................................................................114
6.10 SPI (Serial Peripheral Interface) ................................................................... 115
6.10.1 Overview and Features ................................................................................115
6.10.2 SPI Function Description..............................................................................117
6.10.3 SPI Signal and Pin Description.....................................................................118
6.10.4 SPI Mode Timing ..........................................................................................120
6.11 UART (Universal Asynchronous Receiver/Transmitter).................................121
6.11.1 UART Mode.......................................................................................................122
6.11.2 Transmitting.......................................................................................................123
6.11.3 Receiving...........................................................................................................123
6.11.4 Baud Rate Generator........................................................................................124
6.11.5 UART Timing.....................................................................................................124
6.12 I2C Function .................................................................................................125
6.12.1 7-Bit Slave Address ......................................................................................127
6.12.2 10-Bit Slave Address ....................................................................................128
6.12.3 Master Mode.................................................................................................131
6.13.4 Slave Mode I2C Transmit .............................................................................131
6.13 HLVD (High / Low Voltage Detector)..............................................................132
6.14 Oscillator.......................................................................................................134
IC Product Specification (V1.3) 09.10.2019
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Contents
6.14.1 Oscillator Modes...........................................................................................134
6.14.2 Internal RC Oscillator Mode .........................................................................134
6.15 Power-On Considerations.............................................................................135
6.16 External Power-on Reset Circuit...................................................................135
6.17 Residue-Voltage Protection...........................................................................136
6.18 Code Option .................................................................................................137
6.18.1 Code Option Register (Word 0)....................................................................137
6.18.2 Code Option Register (Word 1)....................................................................139
6.18.3 Code Option Register (Word 2)....................................................................140
6.18.4 Code Option Register (Word 3)....................................................................141
6.19 Instruction Set...............................................................................................142
Absolute Maximum Ratings.........................................................................146
DC Electrical Characteristics .......................................................................146
AC Electrical Characteristics .......................................................................148
7
8
9
APPENDIX
A
B
Package Type..............................................................................................152
Package Information....................................................................................153
B.1 eKTF5616SOP28 .........................................................................................153
B.2 eKTF5616QN24............................................................................................154
B.3 eKTF5616SOP20 .........................................................................................155
B.4 eKTF5608SOP16A.......................................................................................156
B.5 eKTF5616SSOP20A.....................................................................................157
C
D
Ordering and Manufacturing Information.....................................................158
Quality Assurance and Reliability ................................................................160
D.1 Address Trap Detect.....................................................................................160
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IC Product Specification (V1.3) 09.10.2019
Contents
Specification Revision History
Revision Description
Version
Date
2017/05/22
2017/07/27
1.0
Initial Release Version
1.1
1.2
1.3
Delete Internal RC frequency 4MHz information
1. Modify I2C function pin description
2. Modify DC Electrical Characteristics & Add IOH3/IOL3 information
3. Modify feature information
4. Add APPENDIX : D Quality Assurance and Reliability
2018/04/20
2019/09/10
Add eKTF5616SS20A package type
IC Product Specification (V1.3) 09.10.2019
ix
Contents
User Application Note
1. OCDS simulation 12MHz need select other frequency first, then set Bank0 RE bit1~0(RCM1~RCM0)
change to 12MHz
2. When P50//RESET is /RESET pin, P50 must set input.
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IC Product Specification (V1.3) 09.10.2019
eKTF5616/08
8-Bit Microcontroller
1 General Description
The eKTF5616/08 is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. It has a built-in 4K16-bit programmable ROM and is equipped with touch sensors.
The capacitive touch key sensor uses plastic or glass substrate as cover.
The system controller converts fingertip position data into button presses, depending on finger location
and human interface context. The eKTF5616/08 OCD can be used to develop user program for this
microcontroller and several other ELAN Flash type ICs.
2 Features
CPU configuration
Peripheral configuration
8-bit real time clock (TCC) with selective signal
sources, trigger edges, and overflow interrupt
Two Pulse Width Modulation (PWMA, PWMB) with
16-bit resolution shared with Timers A and B
One 8-bit timer TC1 with six modes:
Supports 4K16 bits program ROM
(48+512) bytes general purpose register.
128 bytes in-system programmable EEPROM
16-level stacks for subroutine nesting
3 programmable Level Volt Reset
LVR: 4.2V, 3.6V, 2.5V
Timer/Counter/Capture/Window/Buzzer/PWM/ PDO
(Programmable Divider Output) modes.
1 sets of 16 programmable Level Voltage Detector
LVD: 4.7V, 4.5V, 4.3V, 4.1V, 3.9V, 3.7V, 3.5V, 3.3V,
3.1V, 2.9V, 2.8V, 2.6V, 2.5V, 2.4V, 2.3V, 2.2V
Four CPU operation modes (Normal, Green, Idle, Sleep)
Typically 1 uA, during sleep mode
Touch key function 16 traces for 2 groups
8-channel Analog-to-Digital converter with 12bit
resolution + 1 internal reference for Vref &
1/2VDD(power detector)
I/O port configuration
Serial transmitter/receiver interface (SPI): 3-wire
4 bidirectional I/O ports: P5 ~ P8
4 programmable pin change wake-up ports:
P5~P8
synchronous communication
I2C function with 7/10 bits address and 8 bits data
transmit/receive mode
Universal asynchronous receiver/transmitter (UART)
4 programmable pull-down I/O ports: P5~P8
4 programmable pull-high I/O ports: P5~P8
4 programmable open-drain I/O ports: P5~P8
4 programmable high-sink/drive I/O ports: P5~P8
High-drive 30mA(typically)
available
Power down (Sleep) mode
Idle with scan mode
18 available interrupts: (2 external, 19 internal)
External interrupt: P54, P55
TCC overflow interrupt
Input-port status changed interrupt (wake up from
High-sink 80mA(typically)
Operating voltage range:
2.1V~5.5V at -40 C~85 C (industrial)
sleep mode)
PWMA, PWMB period match completion
Operating frequency range (base on two clocks):
TC1 interrupt
I2C transfer/receive/stop interrupt
SPI interrupt
Main oscillator:
IRC mode:
DC ~ 16 MHz at 3V; DC ~ 8 MHz at 2.1V
UART TX, RX , RX error interrupt
LVD interrupt
System hold interrupt
ADC completion interrupt
TK Scan interrupt
Drift Rate
Internal
Temperature(-40℃~+85℃)
Process
(UWTR:+1%
RC
Total
+ Voltage(2.1V~5.5V)
Frequency
Single instruction cycle commands
Package Type:
NUWTR: +0.5%)
VDD
Internal Vref.
±2%
VDD
Internal Vref.
28 SOP(300mil)
20 SOP(300mil)
16 SOP(150mil)
24 QFN(4*4*0.8mm) : eKTF5616QN24
20 SSOP(150mil) : eKTF5616SS20A
:
:
:
eKTF5616SO28
eKTF5616SO20
eKTF5608SO16A
8MHz
12MHz
16MHz
±9.5%
±9.5%
±9.5%
±1%
±1%
±1%
±10.5%
±10.5%
±10.5%
±3%
±3%
±3%
±2%
±2%
*Internal Vref. : UWTR total ±3%, NUWTR total ±2.5%
Note: These are all Green products which do not contain
hazardous substances.
Sub oscillator:
IRC mode: 16K/32K
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
1
eKTF5616/08
8-Bit Microcontroller
3 Pin Assignment
3.1 Package: SOP 28
1
2
P73/TK12
P72/TK11
P71/TK10
P70/TK9
P67/TK8
P66/TK7
P65/TK6
P64/TK5
P63/TK4
P62/TK3
P61/TK2
28
27
26
25
24
23
P87/AD7
P86/AD6
3
P85/AD5
4
P84/AD4/VREF
P83/AD3/TK16
5
6
P82/AD2/TK15
22 P81/PWMB/AD1/TK14
7
eKTF5616SO28
21
8
P80/PWMA/AD0/TK13
9
20
19
18
17
P55/INT1/SCL1/OSCO/2W_CLK
P54/INT0/SDA1/2W_DATA
P53/SCK/SCL0
10
11
12
P52/SO/SDA0
P60/TC1/TK1
VDD
P51/SI/TX
13
14
16
15
P50//SS/RX//Reset
VSS
Figure 3-1 SOP-28 Pin Assignment
3.2 Package: SOP 20
1
20
19
18
17
16
15
14
13
12
11
P67/TK8
P83/AD3/TK16
2
3
P66/TK7
P65/TK6
P64/TK5
P82/AD2/TK15
P81/PWMB/AD1/TK14
P80/PWMA/AD0/TK13
P55/INT1/SCL1/OSCO/2W_CLK
4
5
eKTF5616SO20
P63/TK4
P62/TK3
P61/TK2
P60/TC1/TK1
VDD
6
P54/INT0/SDA1/2W_DATA
P53/SCK/SCL0
7
8
P52/SO/SDA0
9
P51/SI/TX
VSS
10
P50//SS/RX//Reset
Figure 3-2 SOP-20 Pin Assignment
IC Product Specification (V1.3) 09.10.2019
2
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
3.3 Package: QFN 24
23
24
22
21
20
19
1
2
3
4
5
6
18 P55/INT1/SCL1/OSCO/2W_CLK
P71/TK10
P70/TK9
P67/TK8
P66/TK7
P65/TK6
P64/TK5
17
16
P54/INT0/SDA1/2W_DATA
P53/SCK/SCL0
eKTF5616QN24
15 P52/SO/SDA0
14
P51/SI/TX
13 P50//SS/RX//Reset
10
11
12
7
8
9
Figure 3-3 QFN-24 Pin Assignment
3.4 Package: SOP 16
1
16
15
14
13
12
11
10
9
P64/TK5
P65/TK6
2
3
4
5
6
7
8
P81/PWMB/AD1/TK14
P80/PWMA/AD0/TK13
P55/INT1/SCL1/OSCO/2W_CLK
P63/TK4
P62/TK3
P61/TK2
eKTF5608SO16A
P60/TC1/TK1
VDD
P54/INT0/SDA1/2W_DATA
P53/SCK/SCL0
P52/SO/SDA0
VSS
P51/SI/TX
P50//SS/RX//Reset
Figure 3-4 SOP-16A Pin Assignment
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
3
eKTF5616/08
8-Bit Microcontroller
3.5 Package: SSOP 20
1
2
3
4
5
6
7
8
9
20
19
P65/TK6
P64/TK5
P71/TK10
P72/TK11
P63/TK4
18 P83/AD3/TK16
P62/TK3
17
P82/AD2/TK15
P61/TK2
16
15
14
13
12
11
P81/PWMB/AD1/TK14
eKTF5616SS20A
P60/TC1/TK1
P80/PWMA/AD0/TK13
P55/INT1/SCL1/OSCO/2W_CLK
VSS
VDD
P54/INT0/SDA1/2W_DATA
P53/SCK/SCL0
P50//SS/RX//Reset
P51/SI/TX 10
P52/SO/SDA0
Figure 3-5 SSOP-20A Pin Assignment
4
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
4 Pin Description
Input Output
Name
Function
Description
Type
Type
VDD
VSS
VDD
VSS
Power
Power
Kernel Power
Kernel Ground
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P50
ST
CMOS
/SS
RX
ST
ST
SPI slave mode enable
P50//SS/RX//RESET
UART data receive input (RX)
Internal pull-high reset pin
* When P50//RESET is /RESET pin, P50 must set
input.
/RESET
P51
ST
ST
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
P51/SI/TX
SI
ST
SPI serial data input
TX
CMOS
UART data transmit output (TX)
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P52
ST
CMOS
P52/SO/SDA0
P53/SCK/SCL0
SO
CMOS
CMOS
SPI serial data output
I2C serial data line. It is open-drain
SDA0
ST
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P53
ST
CMOS
SCK
ST
ST
CMOS
CMOS
SPI serial clock input/output
I2C serial clock line. It is open-drain
SCL0
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P54
ST
CMOS
P54/INT0/SDA1/
2W_DATA
INT0
2W_DATA
SDA1
ST
ST
ST
External interrupt pin
CMOS
CMOS
OCD data line
I2C serial data line. It is open-drain
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P55
ST
CMOS
INT1
2W_CLK
SCL1
ST
ST
ST
External interrupt pin
P55/INT1/SCL1/OSCO
2W_CLK
CMOS
CMOS
CMOS
OCD clock line
I2C serial clock line. It is open-drain
Clock output of internal RC oscillator
OSCO
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
P60/TK1/TC1
P60
ST
CMOS
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
5
eKTF5616/08
8-Bit Microcontroller
Input Output
Name
Function
Description
change wake-up
Type
Type
TK1
TC1
AN
ST
TK1 are Touch Key pins
8-bit Timer/Counter 1
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P61
TK2
P62
TK3
P63
TK4
P64
TK5
P65
TK6
P66
TK7
P67
TK8
P70
TK9
P71
TK10
P72
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
CMOS
P61/TK2
P62/TK3
P63/TK4
P64/TK5
P65/TK6
P66/TK7
P67/TK8
P70/TK9
P71/TK10
P72/TK11
TK2 are Touch Key pins
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
TK3 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TK4 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TK5 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TK6 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TK7 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TK8 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TK9 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TK10 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
TK11
P73
AN
ST
TK11 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
P73/TK12
CMOS
6
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Input Output
Name
Function
Description
change wake-up
Type
Type
TK12
P80
AN
ST
TK12 are Touch Key pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
AD0
TK13
AN
AN
Analog to Digital Converter input pins
TK13 are Touch Key pins
PWMA output
P80/TK13/AD0/PWMA
PWMA
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P81
ST
CMOS
TK14
AD1
AN
AN
TK14 are Touch Key pins
Analog to Digital Converter input pins
PWMB output
P81/TK14/AD1/PWMB
PWMB
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P82
ST
CMOS
P82/TK15/AD2
P83/TK16/AD3
P84/VREF/AD4
TK15
AD2
AN
AN
TK15 are Touch Key pins
Analog to Digital Converter input pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P83
ST
CMOS
TK16
AD3
AN
AN
TK16 are Touch Key pins
Analog to Digital Converter input pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P84
ST
CMOS
VREF
AD4
AN
AN
External reference voltage for ADC
Analog to Digital Converter input pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
P85
AD5
P86
AD6
P87
AD7
ST
AN
ST
AN
ST
AN
CMOS
P85/AD5
P86/AD6
P87/AD7
Analog to Digital Converter input pins
CMOS
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
Analog to Digital Converter input pins
Bidirectional I/O pin with programmable
pull-down, pull-high, open-drain, and pin
change wake-up
CMOS
Analog to Digital Converter input pins
Note: OCD: On-Chip Debug system
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
7
eKTF5616/08
8-Bit Microcontroller
5 System Overview
5.1 Memory Map
Flash User Program Area
Registers and Data RAM Memory
0x000
0x00
0x05
Common Registers
OperationalRegisters
Reg. Bank0
Reg. Bank2
4 K x 16bits
0x50
0x80
Common Register
SRAM: (48+512) x 8 bits
Data RAM
(Bank0~3)
0xFF
0xFFF
STACK
Level1
Level2
Level3
Level4
Level5
Level6
Level7
Level8
Level9
Level10
Level11
Level12
Level13
Level14
Level15
Level16
Flash INF Area
EEPROM
0x00
0x00
Code Option
32 x 16 bits
128 x 8 bits
0x7F
Notes:
1. Flash User Program Area is protected when power down occurs, and will not be read, written and erased from the
OCDS.
2. EEPROM can be protected by Code Option Word0<2~0>, and will not be read from the OCDS.
8
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
5.2 Block Diagram
Int. RC
Flash ROM
PC
OscillatorGenerator
16-level
Stack
Instruction
Register
WDT
TCC
TCC
P8
P87
P86
P85
P84
P83
P82
P81
P80
Reset
PWMA
PWMA
Instruction
Decoder
PWMB
TC1
PWMB
TC1
MUX
RAM
P7
HLVD
ALU
P73
P72
P71
P70
R4
LVR
P6
P67
P66
P65
P64
P63
P62
P61
P60
ADC0~ADC7
ADC
Interrupt
Control
Register
Status
Register
ACC
P5
Interrupt
Circuit
P55
P54
UART
TK
I2C
SPI
P53
P52
P51
P50
SO,SI
SCK
Ext INT0, INT1
TK1~TK16
SCL, SDA
TX, RX
Figure 5-1 eKTF5616/08 Functional Block Diagram
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
9
eKTF5616/08
8-Bit Microcontroller
6 Functional Description
6.1 Operational Registers
6.1.1 R0: IAR (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect
addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed
by the RAM Select Register (R4).
6.1.2 R1: BSR (Bank Selection Control Register)
Bit 7
Bit 6
Bit 5
SBS1
R/W
Bit 4
SBS0
R/W
Bit 3
Bit 2
Bit 1
GBS1
R/W
Bit 0
GBS0
R/W
-
-
-
-
0
0
0
0
Bits 7~6: Not used. Set to “0” all the time.
Bits 5~4 (SBS1~SBS0): Special register bank select bit. It is used to select Banks 0/1/2 of
Special Registers R5~R4F.
SBS1
SBS0
Special Register Bank
0
0
1
1
0
1
0
1
0
1
2
X
Bit 3~2: Not used. Set to “0” all the time.
Bits 1~0 (GBS1~GBS0): General register bank select bit. It is used to select
Banks 0~3 of General Registers R80~RFF.
GBS1
GBS0
RAM Bank
0
0
1
1
0
1
0
1
0
1
2
3
10
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
6.1.3 R2: PCL (Program Counter Low)
Bit 7
PC7
R/W
Bit 6
PC6
R/W
Bit 5
PC5
R/W
Bit 4
PC4
R/W
Bit 3
PC3
R/W
Bit 2
PC2
R/W
Bit 1
PC1
R/W
Bit 0
PC0
R/W
Bits 7~0 (PC7~PC0): The low byte of program counter.
Depending on the device type, R2 and hardware stack are 16-bits wide. The structure
is depicted in Figure 6-1 eKTF5616/08 Program Counter Organization.
Generating 4K16 bits on-chip Flash ROM addresses to the relative programming
instruction codes. One program page is 4096 words long.
R2 is set as all "0"s when under RESET condition.
"JMP" instruction allows direct loading of the lower 12 program counter bits. Thus,
"JMP" allows PC to go to any location within a page.
"CALL" instruction loads the lower 12 bits of the PC, and the present PC value will add
1 and is pushed into the stack. Thus, the subroutine entry address can be located
anywhere within a page.
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the
top-level stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth and
above bits of the PC will increase progressively.
"MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of the
PC, and the ninth and above bits of the PC won’t be changed.
Any instruction except “ADD R2,A” that is written to R2 (e.g. "MOV R2, A", "BC R2,
6",“INC R2”,) will cause the ninth bit and the above bits (PC8~PC12) of the PC not
change.
All instructions are single instruction cycle (Fsys/2).
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
11
eKTF5616/08
8-Bit Microcontroller
A 11 ~ A 0
PC
Reset vector
0000h
0002h
0004h
0006h
0008h
000Ch
0010 h
0012h
0014h
INT interrupt vector
Pin change interrupt vector
TCC interrupt vector
LVD interrupt vector
SPI interrupt vector
ADC interrupt vector
TC1 interrupt vector
PWMPA interrupt vector
STACK LEVEL1
STACK LEVEL2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
STACK LEVEL 7
STACK LEVEL 8
STACK LEVEL 9
PWMDA interrupt vector
I2C Tx interrupt vector
I2C Rx interrupt vector
I2Cstop interrupt vector
PWMPB interrupt vector
0016h
001Ah
001Ch
001Eh
0024h
0026h
002Eh
0030h
PWMDB interrupt vector
UART RX error interrupt vector
UART RX interrupt vector
UART TX interrupt vector
0032h
STACK LEVEL10
STACK LEVEL11
STACK LEVEL12
STACK LEVEL13
STACK LEVEL14
STACK LEVEL15
STACK LEVEL16
System hold interrupt vector
003Ah
Touch Key
003Ch
003Eh
0040h
interrupt vector
Touch Key error interrupt vector
Touch Key Idle with scan mode interrupt vector
On- Chip Program memory
FFFh
Figure 6-1 eKTF5616/08 Program Counter Organization
12
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Data Memory Configuration
SBANK 0
Address
0X00
0X01
0X02
0X03
0X04
0X05
0X06
0X07
0X08
0X09
0X0A
0x0B
0X0C
0X0D
0X0E
0X0F
0X10
0X11
0X12
0X13
0X14
0X15
0X16
0X17
0X18
0X19
0X1A
0X1B
0X1C
0X1D
0X1E
0X1F
0X20
0X21
0X22
0X23
SBANK 1
SBANK 2
IAR (Indirect Addressing Reg.)
BSR (Bank Selection Control Reg.)
PCL (Program Counter Low)
SR (Status Reg.)
RSR (RAM Selection Reg.)
IOCR8
TKAPC
TKBPC
Port 5
Port 6
Unused
Unused
TKASCR
TKBSCR
Unused
Port 7
P5PHCR
Port 8
P6PHCR
Unused
Unused
IOCR5
IOCR6
IOCR7
P78PHCR
P5PLCR
Unused
Unused
P6PLCR
Unused
P78PLCR
TKCR
P5HDSCR
P6HDSCR
P789AHDSCR
P5ODCR
TKCCR
OMCR
EIESCR
TKCSR
WUCR1
WUCR2
TKCTR
TKSWR
TKAH
P6ODCR
WUCR3
Unused
P78ODCR
Unused
TKAL
TKBH
SFR1
SFR2
SFR3
SFR4
Unused
TKBL
PWMSCR
TKSCR
PWMACR
TKA1WBH
TKA1WBL
TKA1WR
TKA2WBH
TKA2WBL
TKA2WR
TKB1WBH
TKB1WBL
TKB1WR
TKB2WBH
TKB2WBL
TKB2WR
Unused
PRDAL
Unused
SFR6
PRDAH
Unused
DTAL
DTAH
IMR1
IMR2
IMR3
IMR4
TMRAL
TMRAH
PWMBCR
PRDBL
Unused
IMR6
PRDBH
DTBL
WDTCR
TCCCR
TCCD
DTBH
TMRBL
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
13
eKTF5616/08
8-Bit Microcontroller
Address
0X24
0X25
0X26
0X27
0X28
0X29
0X2A
0x2B
0X2C
0X2D
0X2E
0X2F
0X30
0X31
0X32
0X33
0X34
0X35
0X36
0X37
0X38
0X39
0X3A
0x3B
0X3C
0X3D
0X3E
0X3F
0X40
0X41
0X42
0X43
0X44
0X45
0X46
0X47
0X48
SBANK 0
SBANK 1
SBANK 2
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
LOCKPR
LOCKCR
TMRBH
TC1CR1
Unused
Unused
TC1CR2
TC1DA
Unused
Unused
Unused
Unused
Unused
TC1DB
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
I2CCR1
I2CCR2
I2CSA
Unused
Unused
Unused
Unused
Unused
Unused
Unused
URCR
I2CDB
I2CDAL
I2CDAH
SPICR
SPIS
URS
URTD
URRDL
URRDH
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
EECR1
EECR2
EERA
SPIR
SPIW
Unused
Unused
Unused
Unused
ADCR1
ADCR2
ADISR
ADER1
Unused
ADDL
EERD
ADDH
FLKR
ADCVL
ADCVH
Unused
Unused
TBPTL
TBPTH
STKMON
PCH
14
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Address
0X49
0X4A
0x4B
0X4C
0X4D
0X4E
0X4F
0X50
0X51
.
SBANK 0
Unused
Unused
Unused
Unused
Unused
Unused
Unused
SBANK 1
HLVDCR
Unused
Unused
Unused
TBWCR
TBWAL
TBWAH
SBANK 2
Unused
Unused
Unused
Unused
Unused
Unused
Unused
GENERAL PURPOSE REGISTER
.
0X7F
0X80
0X81
.
.
.
0XFE
0XFF
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
15
eKTF5616/08
8-Bit Microcontroller
6.1.4 R3: SR (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT
F
N
OV
T
P
Z
DC
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7 (INT): Interrupt Enable flag
0: Interrupt masked by DISI or hardware interrupt
1: Interrupt enabled by ENI/RETI instructions
Bit 6 (N): Negative flag.
The negative flag stores the state of the most significant bit of the output result
0: The result of the operation is not negative.
1: The result of the operation is negative.
Bit 5 (OV): Overflow flag.
OV is set when a two’s complement overflows occurs as a result of an operation
0: No overflow occurred.
1: Overflow occurred.
Bit 4 (T): Time-out bit.
Set to 1 with the "SLEP" and "WDTC" commands, or during power up and reset to 0 by
WDT time-out.
Bit 3 (P): Power down bit.
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
Bit 2 (Z): Zero flag.
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry or Borrow flag
C : C is set when a carry occurs and cleared when a borrow occurs during an arithmetic
operation. The Carry Flag bit is set or cleared, depending on the operation that is
performed.
For ADD, ADC, INC, INCA instructions
0: No carry occurs.
1: Carry occurs.
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8-Bit Microcontroller
For SUB, SUBB, DEC, DECA, NEG instructions
0: Borrow occurs.
1: No borrow occurs.
For RLC, RRC, RLCA, RRCA instructions
The Carry flag is used as a link between the least significant bit (LSB) and the most
significant bit (MSB).
6.1.5 R4: RSR (RAM Select Register)
Bit 7
RSR7
R/W
Bit 6
RSR6
R/W
Bit 5
RSR5
R/W
Bit 4
RSR4
R/W
Bit 3
RSR3
R/W
Bit 2
RSR2
R/W
Bit 1
RSR1
R/W
Bit 0
RSR0
R/W
Bits 7~0 (RSR7~RSR0): These bits are used to select registers (Address 00 ~ FF) in
indirect addressing mode. For more details, refer to the table on Data Memory
Configuration in Section 6.1.3, R2: PCL (Program Counter Low).
6.1.6 Bank 0 R5 ~ R8: (Port 5 ~ Port 8)
R5, R6, R7, and R8 are I/O data registers.
6.1.7 Bank 0 R9 ~ RA: (Reserved)
6.1.8 Bank 0 RB~RD: (IOCR5 ~ IOCR7)
These registers are used to control the I/O port direction. They are both
readable and writable.
0: Set the relative I/O pin as output
1: Set the relative I/O pin into high impedance
6.1.9 Bank 0 RE: OMCR (Operating Mode Control Register)
Bit 7
CPUS
R/W
Bit 6
IDLE
R/W
Bit 5
PERCS
R/W
Bit 4
Bit 3
FMSF
R
Bit 2
Bit 1
RCM1
R/W
Bit 0
RCM0
R/W
-
-
-
-
Bit 7 (CPUS): CPU Oscillator Source Select.
0: Fs: sub-oscillator
1: Fm: main-oscillator (default)
When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator
is stopped.
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8-Bit Microcontroller
Bit 6 (IDLE): Idle Mode Enable Bit. This bit will decide SLEP instruction which mode to go.
0: “IDLE=0”+SLEP instruction sleep mode
1: “IDLE=1”+SLEP instruction idle mode (default)
Code option
HLFS=1
RESET
Normal mode
Fm: oscillation
Fs: oscillation
CPU: using Fm
Code option
HLFS=0
wakeup
Interrupt or
wakeup
IDLE=0
+ SLEP
CPUS=1
CPUS=0
IDLE=1
+ SLEP
IDLE=1
+ SLEP
(*)
wakeup
(**)
Sleep mode
Fm: stop
Green mode
Fm: stop
Idle mode
Fm: stop
Fs: stop
CPU: stop
Fs: oscillation
CPU: using Fs
Fs: oscillation
CPU: stop
Interrupt or
wakeup
IDLE=0
+ SLEP
Figure 6-2 CPU Operation Mode
Note
(*)
If Watchdog function is enabled before entering into sleep mode, some circuits, such as timer (Its
clock source is Fs) must stop counting.
If Watchdog function is enabled before entering into sleep mode, some circuits, such as timer (Its
clock source is external pin) can still count and its interrupt flag can be active at matching condition
as corresponding interrupt is enabled. But CPU cannot be woken up by this event.
(**)
Switching Operation Mode at sleep Normal, Green Normal:
If the clock source of the timer is Fm, the timer/counter must stop counting at sleep or green mode.
Then, timer can continue to count until clock source is stable at normal mode. A stable clock source
means CPU starts to work at normal mode.
Switching Operation Mode at Sleep green:
If the clock source of the timer is Fs, the timer must stop counting at sleep mode. Then, the timer can
continue to count until the clock source is stable at green mode. A stable clock source means that
CPU starts to work at green mode.
Switching Operation Mode at Sleep Normal:
If the clock source of the Timer is Fs, the timer must stop counting at sleep mode. Then, the timer can
continue to count until the clock source is stable at normal mode. A stable clock source means that
CPU starts to work at normal mode.
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eKTF5616/08
8-Bit Microcontroller
Waiting time before CPU starting to work
IRC
Frequency
CPU mode switch
POR/LVR
PERCS = 1
PERCS = 0
16ms + WSTO + 32 clocks
(main frequency)
32 clocks
(main frequency)
WSTO + 32 clocks
(main frequency)
12M, 16M
8M
Sleep -> Normal
Idle -> Normal
Green -> Normal
16ms + WSTO + 8/32 clocks
(main frequency)
8/32 clocks
(main frequency)
WSTO + 8/32 clocks (main
frequency)
Sleep -> Green
Idle -> Green
16ms + WSTO + 8 clocks
(sub frequency)
WSTO + 8 clocks
(sub frequency)
WSTO + 8 clocks (sub
frequency)
32KHz
WSTO: Waiting time of Start-to-Oscillation
Bit 5 (PERCS): Periphery Clock Source for Green and Idle modes.
0: Periphery Clock Source is Fs. Fm will be Stop into Green and Idle modes.
(default)
1: Periphery Clock Source is Fm. Fm will be oscillation into Green and Idle
modes.
Bits 4,2: Not used, set to “0” all the time
Bit 3 (FMSF): Fm Stable Flag bit.
0: Indicate that the frequency is unstable.
1: Indicate that the frequency has stabilized.
Bits 1~0 (RCM1~RCM0): Internal RC mode selection bits
*Default value corresponding code option Word1 RCM1~RCM0
*RCM1
*RCM0
Frequency (MHz)
0
0
1
1
0
1
0
1
NA
8
12*
16
*OCDS simulation 12MHz need select other frequency first, then set RCM1~RCM0 change to 12MHz
6.1.10 Bank 0 RF: EIESCR (External Interrupt Edge Select Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EIES1
R/W
Bit 2
EIES0
R/W
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7~4: Not used, set to "0" all the time
Bits 3~2 (EIES1~0): external interrupt edge select bit
0: Falling edge interrupt
1: Rising edge interrupt
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Bits 1~0: Not used, set to "0" all the time
6.1.11 Bank 0 R10: WUCR1 (Wake-up Control Register 1)
Bit 7
Bit 6
Bit 5
LVDWK
R/W
Bit 4
ADWK
R/W
Bit 3
INTWK1
R/W
Bit 2
INTWK0
R/W
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bits 7~6: Not used, set to “0” all the time
Bit 5 (LVDWK): Low Voltage Detect Wake-up Enable Bit
0: Disable Low Voltage Detect wake-up.
1: Enable Low Voltage Detect wake-up.
Bit 4 (ADWK): A/D Converter Wake-up Function Enable Bit
0: Disable AD converter wake-up
1: Enable AD converter wake-up
When the AD Complete status is used to enter interrupt vector or to wake up IC from
sleep/idle with AD conversion running, the ADWK bit must be set to “enable”.
Bits 3~2 (INTWK1~0): External Interrupt (INT pin) Wake-up Function Enable Bit
0: Disable external interrupt wake-up
1: Enable external interrupt wake-up
When the External Interrupt status changed is used to enter interrupt vector or to wake up
IC from Sleep/Idle, the INTWK bits must be set to “enable”.
Bits 1~0: Not used, set to “0” all the time
6.1.12 Bank 0 R11: WUCR2 (Wake-up Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SPIWK
R/W
Bit 2
I2CWK
R/W
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7~4:
Not used. Set to "0" all the time.
Bit 3 (SPIWK): SPI wake-up enable bit. Applicable when SPI works in Slave mode.
0: Disable SPI wake-up
1: Enable SPI wake-up
Bit 2 (I2CWK): I2C wake-up enable bit. Applicable when I2C works in Slave mode.
0: Disable I2C wake-up
1: Enable I2C wake-up
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8-Bit Microcontroller
NOTE
When I2C is in Slave mode, it cannot communicate with the MCU in Green mode. At the
same time, the SCL in on hold and kept at low level when the MCU is in Green mode. SCL
is released when the MCU switches to Normal mode.
Bits 1~0:
Not used. Set to "0" all the time.
6.1.13 Bank 0 R12: WUCR3 (Wake-up Control Register 3)
Bit 7
ICWKP8
R/W
Bit 6
ICWKP7
R/W
Bit 5
ICWKP6 ICWKP5
R/W R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bits 7~4 (ICWKP8~ICWKP5): Pin change Wake-up enable for Ports 8/7/6/5.
0: Disable wake-up function
1: Enable wake-up function
Bits 3~0:
Sleep Mode
DISI
Not used. Set to "0" all the time.
Idle Mode
DISI
Green Mode
Normal Mode
Wake-up Condition
Signal Signal
ENI
ENI
DISI
ENI
DISI
ENI
ICWKPx =
0,
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
PxICIE = 0
ICWKPx =
0,
Interrupt +
Next
Interrupt +
Interrupt
Vector
Next
Interrupt
Instruction
Vector
Instruction
Pin
PxICIE = 1
Change
INT
ICWKPx =
1,
Wake-up +
Interrupt is invalid
Next Instruction
PxICIE = 0
ICWKPx =
1,
Wake-up + Wake-up + Wake-up + Wake-up +
Interrupt +
Next
Interrupt +
Interrupt
Vector
Next
Next
Interrupt
Vector
Next
Interrupt
Vector
Interrupt
Instruction
Vector
Instruction
Instruction
Instruction
PxICIE = 1
NOTE
When the MCU wakes up from Sleep or Idle mode, the ICSF must equal to 1. If ICSF is
equal to 0, it means the pin status does not change or the pin change ICIE is disabled.
Hence the MCU cannot wake-up.
6.1.14 Bank 0 R13: (Reserved)
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6.1.15 Bank 0 R14: SFR1 (Status Flag Register 1)
Bit 7
Bit 6
Bit 5
LVDSF
F
Bit 4
ADSF
F
Bit 3
EXSF1
F
Bit 2
EXSF0
F
Bit 1
Bit 0
TCSF
F
-
-
-
-
-
-
Each corresponding status flag is set to "1" when interrupt condition is triggered.
Bits 7~6, 1: Not used, set to "0" all the time
Bit 5 (LVDSF): Low Voltage Detector status flag
Bit 4 (ADSF): Analog to digital conversion interrupt status flag. Set when AD conversion is
completed. Reset by software.
Bits 3~2 (EXSF1~0): External interrupt status flag.
Bit 0 (TCSF): TCC overflow status flag. Set when TCC overflows, reset by software.
NOTE
If a function is enabled, the corresponding status flag would be active
regardless of whether the interrupt mask is enabled or not.
6.1.16 Bank 0 R15: SFR2 (Status Flag Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
UERRSF
F
URSF
F
UTSF
F
-
-
-
-
TC1SF
F
Bits 7~6: Not used, set to "0" all the time
Bit 5 (UERRSF): UART receiving error status flag, cleared by software or UART disable.
Bit 4 (URSF): UART receive mode data buffer full status flag, cleared by software.
Bit 3 (UTSF): UART transmit mode data buffer empty flag, cleared by software.
Bits 2~1: Not used, set to "0" all the time
Bit 0 (TC1SF): 8-bit timer/counter 1 status flag, cleared by software.
6.1.17 Bank 0 R16: SFR3 (Status Flag Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
PWMBPSF PWMBDSF PWMAPSF PWMADSF
F
F
F
F
Bits 7~4: Not used, set to "0" all the time
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8-Bit Microcontroller
Bit 3 (PWMBPSF): Status flag of period-matching for PWMB (Pulse Width Modulation).
Set when a selected period is reached, reset by software.
Bit 2 (PWMBDSF): Status flag of duty-matching for PWMB (Pulse Width Modulation). Set
when a selected duty is reached, reset by software.
Bit 1 (PWMAPSF): Status flag of period-matching for PWMA (Pulse Width Modulation).
Set when a selected period is reached, reset by software.
Bit 0 (PWMADSF): Status flag of duty-matching for PWMA (Pulse Width Modulation). Set
when a selected duty is reached, reset by software.
NOTE
If a function is enabled, the corresponding status flag would be active whether the
interrupt mask is enabled or not.
6.1.18 Bank 0 R17: SFR4 (Status Flag Register 4)
Bit 7
P8ICSF
F
Bit 6
P7ICSF
F
Bit 5
P6ICSF
F
Bit 4
P5ICSF
F
Bit 3
SPISF
F
Bit 2
Bit 1
Bit 0
I2CTSF
F
I2CSTPSF I2CRSF
F
F
Bits 7~4 (P8ICSF~P5ICSF): Ports 5~8 input status change status flag. Set when
Ports 5~8 input changes. Reset by software.
Bit 3 (SPISF):
SPI mode status flag. Flag is cleared by software.
Bit 2 (I2CSTPSF): I2C stop status flag. Set when I2C stop signal occurs.
Bit 1 (I2CRSF): I2C receive status flag. Set when I2C receives 1byte data and responds
to ACK signal. Reset by firmware or I2C disable.
Bit 0 (I2CTSF): I2C transmit status flag. Set when I2C transmits a 1 byte data and
receives a handshake signal (ACK or NACK). Reset by firmware or I2C
disable.
NOTE
If a function is enabled, the corresponding status flag will be active regardless of whether
the interrupt mask is enabled or not.
6.1.19 Bank 0 R18: (Reserved)
6.1.20 Bank 0 R19: SFR6 (Status Flag Register 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SHSF
F
-
-
-
-
TKTOSF
F
TKCSF
F
TKPESF TKOESF
TKSF
F
F
F
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8-Bit Microcontroller
Bit 7 (SHSF): System hold status flag, Set when system hold occur, reset by software.
Bits 6~5: Not used, set to "0" all the time
Bit 4 (TKTOSF): Touch Key idle with scan mode time out status flag. Set when Touch Key
idle with scan mode threshold compare condition dissatisfied and continued for 16 times,
reset by software.
Bit 3 (TKCSF): Touch Key Compare status flag. Set when Touch Key idle with scan mode
threshold compare conditions are satisfied, reset by software.
Bit 2 (TKPESF): Touch Key period Error status flag. Set when Touch Key period falls early,
reset by software
Bit 1 (TKOESF): Touch Key Counter Overflow Error status flag. Set when Touch Key timer
overflows, reset by software
Bit 0 (TKSF): Status flag for Touch Key Conversion. Set when Touch Key conversion is
completed, reset by software (except idle with scan mode condition)
6.1.21 Bank 0 R1A: (Reserved)
6.1.22 Bank 0 R1B: IMR1 (Interrupt Mask Register 1)
Bit 7
Bit 6
Bit 5
LVDIE
R/W
Bit 4
ADIE
R/W
Bit 3
EXIE1
R/W
Bit 2
EXIE0
R/W
Bit 1
Bit 0
TCIE
R/W
-
-
-
-
-
-
Bits 7~6, 1: Not used, set to "0" all the time.
Bit 5 (LVDIE): LVDSF interrupt enable bit.
0: Disable LVDSF interrupt
1: Enable LVDSF interrupt
Bit 4 (ADIE): ADSF interrupt enable bit.
0: Disable ADSF interrupt
1: Enable ADSF interrupt.
Bit 3 (EXIE1): EXSF1 interrupt enable and /INT1 function enable bit.
0: P55/INT1/SCL1/OSCO is P55/SCL1/OSCO pin, EXSF1 always equals
0.
1: Enable EXSF1 interrupt and P55/INT1/SCL1/OSCO is /INT1 pin
Bit 2 (EXIE0): EXSF0 interrupt enable and /INT0 function enable bit.
0: P54/INT0/SDA1 is P54/SDA1 pin, EXSF0 always equals 0.
1: Enable EXSF0 interrupt and P54/INT0/SDA1 is /INT0 pin
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eKTF5616/08
8-Bit Microcontroller
Bit 0 (TCIE): TCSF interrupt enable bit.
0: Disable TCSF interrupt
1: Enable TCSF interrupt
NOTE
If the interrupt mask and instruction “ENI” are enabled, the program counter will jump into
the corresponding interrupt vector when the corresponding status flag is set.
6.1.23 Bank 0 R1C: IMR2 (Interrupt Mask Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
UERRIE
R/W
URIE
R/W
UTIE
R/W
-
-
-
-
TC1IE
R/W
Bits 7~6: Not used, set to "0" all the time.
Bit 5 (UERRIE): UART receive error interrupt enable bit.
0: Disable UERRSF interrupt
1: Enable UERRSF interrupt
Bit 4 (URIE): UART receive mode Interrupt enable bit.
0: Disable URSF interrupt
1: Enable URSF interrupt
Bit 3 (UTIE): UART transmit mode interrupt enable bit.
0: Disable UTSF interrupt
1: Enable UTSF interrupt
Bits 2~1: Not used, set to "0" all the time.
Bit 0 (TC1IE): Interrupt enable bit.
0: Disable TC1SF interrupt
1: Enable TC1SF interrupt
6.1.24 Bank 0 R1D: IMR3 (Interrupt Mask Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
PWMBPIE PWMBDIE PWMAPIE PWMADIE
R/W R/W R/W R/W
Bits 7~4: Not used, set to "0" all the time.
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eKTF5616/08
8-Bit Microcontroller
Bit 3 (PWMBPIE): PWMBPSF interrupt enable bit.
0: Disable period-matching of PWMB interrupt
1: Enable period-matching of PWMB interrupt
Bit 2 (PWMBDIE): PWMBDSF interrupt enable bit.
0: Disable duty-matching of PWMB interrupt
1: Enable duty-matching of PWMB interrupt
Bit 1 (PWMAPIE): PWMAPSF interrupt enable bit.
0: Disable period-matching of PWMA interrupt
1: Enable period-matching of PWMA interrupt
Bit 0 (PWMADIE): PWMADSF interrupt enable bit.
0: Disable duty-matching of PWMA interrupt
1: Enable duty-matching of PWMA interrupt
NOTE
If the interrupt mask and instruction “ENI” are enabled, the program counter will jump into
the corresponding interrupt vector when the corresponding status flag is set.
6.1.25 Bank 0 R1E: IMR4 (Interrupt Mask Register 4)
Bit 7
P8ICIE
R/W
Bit 6
P7ICIE
R/W
Bit 5
P6ICIE
R/W
Bit 4
P5ICIE
R/W
Bit 3
SPIIE
R/W
Bit 2
I2CSTPIE
R/W
Bit 1
I2CRIE
R/W
Bit 0
I2CTIE
R/W
Bits 7~4 (P8ICIE~P5ICIE): PxICSF interrupt enable bit
0: Disable PxICSF interrupt
1: Enable PxICSF interrupt
Bit 3 (SPIIE): Interrupt enable bit
0: Disable SPSF interrupt
1: Enable SPSF interrupt
Bit 2 (I2CSTPIE): I2C stop interrupt enable bit.
0: Disable interrupt
1: Enable interrupt
Bit 1 (I2CRIE): I2C Interface Rx interrupt enable bit
0: Disable interrupt
1: Enable interrupt
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8-Bit Microcontroller
Bit 0 (I2CTIE): I2C Interface Tx interrupt enable bit
0: Disable interrupt
1: Enable interrupt
NOTE
If the interrupt mask and instruction “ENI” are enabled, the program counter will jump into
the corresponding interrupt vector when the corresponding status flag is set.
6.1.26 Bank 0 R1F: (Reserved)
6.1.27 Bank 0 R20: IMR6 (Interrupt Mask Register 6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SHIE
R/W
-
-
-
-
-
-
TKCIE
R/W
-
-
TKERRIE
R/W
TKIE
R/W
Bit 7 (SHIE): SHSF Interrupt Enable Bit.
0: Disable SHSF interrupt
1: Enable SHSF interrupt
Bits 6~4,2: Not used, set to "0" all the time.
Bit 3 (TKCIE): TKCSF/TKTOSF Interrupt Enable Bit.
0: Disable TKCSF/TKTOSF interrupt
1: Enable TKCSF/TKTOSF interrupt
Bit 1 (TKERRIE): TKPESF /TKOESF Interrupt Enable Bit.
0: Disable TKPESF /TKOESF interrupt
1: Enable TKPESF /TKOESF interrupt
Bit 0 (TKIE): TKIE Interrupt Enable Bit.
0: Disable TKSF interrupt
1: Enable TKSF interrupt
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6.1.28 Bank 0 R21: WDTCR (Watchdog Timer Control Register)
Bit 7
Bit 6
FSSF
R
Bit 5
Bit 4
Bit 3
PSWE
R/W
Bit 2
WPSR2
R/W
Bit 1
WPSR1
R/W
Bit 0
WPSR0
R/W
WDTE
R/W
-
-
-
-
Bit 7 (WDTE): Watchdog Timer enable bit. WDTE is both readable and writable.
0: Disable WDT
1: Enable WDT
Bit 6 (FSSF): Fs Stable Flag bit
1: Indicate that the frequency has stabilized.
0: Indicate that the frequency is unstable.
Bits 5~4: Not used. Set to "0" all the time.
Bit 3 (PSWE): Prescaler enable bit for WDT
0: Prescaler disable bit. WDT rate is 1:1.
1: Prescaler enable bit. The WDT rate is set at Bits 2~0.
Bits 2~0 (WPSR2~WPSR0): WDT Prescaler bits
WPSR2
WPSR1
WPSR0
WDT Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.1.29 Bank 0 R22: TCCCR (TCC Control Register)
Bit 7
Bit 6
TCCS
R/W
Bit 5
Bit 4
Bit 3
PSTE
R/W
Bit 2
TPSR2
R/W
Bit 1
TPSR1
R/W
Bit 0
TPSR0
R/W
-
-
-
-
-
-
Bit 7:
Not used. Set to “0” all the time.
Bit 6 (TCCS): TCC Clock Source select bit
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8-Bit Microcontroller
0: Fs (sub clock)
1: Fm (main clock)
Bits 5~4:
Not used. Set to “0” all the time.
Bit 3 (PSTE): Prescaler enable bit for TCC
0: Prescaler disable bit. TCC rate is 1:1.
1: Prescaler enable bit. TCC rate is set at Bit 2 ~ Bit 0.
Bits 2~0 (TPSR2~TPSR0): TCC Prescaler Bits
TPSR2
TPSR1
TPSR0
TCC Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.1.30 Bank 0 R23: TCCD (TCC Data Register)
Bit 7
TCC7
R/W
Bit 6
TCC6
R/W
Bit 5
TCC5
R/W
Bit 4
TCC4
R/W
Bit 3
TCC3
R/W
Bit 2
TCC2
R/W
Bit 1
TCC1
R/W
Bit 0
TCC0
R/W
Bits 7~0 (TCC7~TCC0): TCC data
Counter is increased by the instruction cycle clock. Writable and readable as
any other registers.
6.1.31 Bank 0 R24: TC1CR1 (Timer 1 Control Register 1)
Bit 7
TC1S
R/W
Bit 6
TC1RC
R/W
Bit 5
TC1SS1
R/W
Bit 4
Bit 3
TC1FF
R/W
Bit 2
TC1MOS
R/W
Bit 1
TC1IS1
R/W
Bit 0
TC1IS0
R/W
-
-
Bit 7 (TC1S): Timer/Counter 1 Start Control Bit
0: Stop and clear counter (default)
1: Start
Bit 6 (TC1RC): Timer 1 Read Control Bit. To load current number of counter into TC1DB
register. It’s useful only in counter mode.
IC Product Specification (V1.3) 09.10.2019
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29
eKTF5616/08
8-Bit Microcontroller
0: Disable function. When using capture mode, this bit must be set to “0”
(default).
1: Enable function. The number of counting are loaded into TC1DB.
Bit 5 (TC1SS1): Timer/Counter 1 Clock Source Select Bit 1
0: Internal clock as count source (Fc)- Fs/Fm (default)
1: External TC1 pin as count source (Fc). It is used only for timer/counter
mode.
Bit 4: Not used, set to “0” all the time.
Bit 3(TC1FF): Inversion for Timer/Counter 1 as PWM or PDO mode
0: Duty is Logic 1 (default)
1: Duty is Logic 0
Bit 2 (TC1MOS): Timer Output Mode Select Bit
0: Repeating mode (default)
1: One–shot mode
NOTE
One-shot mode means the timer only counts a cycle.
Bits 1~0 (TC1IS1~ TC1IS0): Timer 1 Interrupt Type Select Bits. These two bits are
used when the Timer operates in PWM mode.
TC1IS1
TC1IS0
Timer 1 Interrupt Type Select
TC1DA(period) matching
0
0
1
0
1
x
TC1DB(duty) matching
TC1DA and TC1DB matching
6.1.32 Bank 0 R25: TC1CR2 (Timer 1 Control Register 2)
Bit 7
TC1M2
R/W
Bit 6
TC1M1
R/W
Bit 5
TC1M0
R/W
Bit 4
TC1SS0
R/W
Bit 3
TC1CK3
R/W
Bit 2
TC1CK2
R/W
Bit 1
TC1CK1
R/W
Bit 0
TC1CK0
R/W
Bits 7~5 (TC1M2~TC1M0): Timer/Counter 1 operation mode select.
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IC Product Specification (V1.3) 09.10.2019
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eKTF5616/08
8-Bit Microcontroller
TC1M2
TC1M1
TC1M0
Operating Mode Select
Timer/Counter Rising Edge
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Timer/Counter Falling Edge
Capture Mode Rising Edge
Capture Mode Falling Edge
Window mode
Programmable Divider output
Pulse Width Modulation output
Buzzer (output timer/counter clock source.
The duty cycle of clock source must be 50/50)
1
1
1
Bit 4 (TC1SS0): Timer/Counter 1 clock source selection bit
0: The Fs is used as count source (Fc) (default)
1: The Fm is used as count source (Fc)
Bits 3~0 (TC1CK3~TC1CK0): Timer/Counter 1 clock source prescaler select.
Max time
8MHz
Max time
16KHz
Clock
Source
Resolution
8MHZ
Resolution
16KHZ
TC1CK3
TC1CK2
TC1CK1
TC1CK0
Normal
FC
FC=8M
125ns
250ns
500ns
1us
FC=8M
32us
FC=16K
62.5us
125us
250us
500us
FC=16K
16ms
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
FC/2
64us
32ms
FC/22
FC/23
128us
256us
64ms
128ms
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
FC/24
FC/25
FC/26
FC/27
FC/28
FC/29
FC/210
FC/211
FC/212
FC/213
FC/214
FC/215
2us
4us
512us
1024us
1ms
2ms
256ms
512ms
8us
2048us
4ms
1024ms
16us
4096us
8ms
2048ms
32us
8192us
16ms
32ms
64ms
128ms
256ms
512ms
1.024s
2.048s
4096ms
64us
16384us
32768us
65536us
131072us
262144us
524.288ms
1.048s
8192ms
128us
256us
512us
1.024ms
2.048ms
4.096ms
16384ms
32768ms
65536ms
131072ms
262144ms
524288ms
IC Product Specification (V1.3) 09.10.2019
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31
eKTF5616/08
8-Bit Microcontroller
6.1.33 Bank 0 R26: TC1DA (Timer/Counter 1 DATA Buffer A)
Bit 7
Bit 6
TC1DA6
R/W
Bit 5
TC1DA5
R/W
Bit 4
TC1DA4
R/W
Bit 3
TC1DA3
R/W
Bit 2
TC1DA2
R/W
Bit 1
TC1DA1
R/W
Bit 0
TC1DA0
R/W
TC1DA7
R/W
Bits 7~0 (TC1DA7~TC1DA0): Data buffer A of 8 bit Timer/Counter 1
6.1.34 Bank 0 R27: TC1DB (Timer/Counter 1 DATA Buffer B)
Bit 7
TC1DB7
R/W
Bit 6
TC1DB6
R/W
Bit 5
TC1DB5
R/W
Bit 4
TC1DB4
R/W
Bit 3
TC1DB3
R/W
Bit 2
TC1DB2
R/W
Bit 1
TC1DB1
R/W
Bit 0
TC1DB0
R/W
Bits 7~0 (TC1DB7~TC1DB0): Data Buffer B of 8 bit Timer/Counter 1
NOTE
1. When Timer/Counter x is used as PWM mode, the duty value stored at
register TCxDB must be less than or equal to the period value stored at
register TCxDA. i.e., duty ≦ period. And then the PWM waveform is
generated. If duty value is greater than period value, the PWM output
waveform will be kept at high voltage levels.
2. The period value set by users is extra plus 1 in inner circuit.
For example:
The period value is set as 0x4F, the circuit actually processes 0x50 period
length.
The period value is set as 0xFF, the circuit actually processes 0x100 period
length.
6.1.35 Bank 0 R28 ~ R2F: (Reserved)
6.1.36 Bank 0 R30: I2CCR1 (I2C Status and Control Register 1)
Bit 7
Strobe/Pend
R/W
Bit 6
IMS
Bit 5
ISS
Bit 4
STOP SAR_EMPTY
R/W
Bit 3
Bit 2
ACK
R
Bit 1
FULL
R
Bit 0
EMPTY
R
R/W
R/W
R
Bit 7 (Strobe/Pend): In Master mode, it is used as strobe signal to control I2C circuit in
sending SCL clock. Automatically reset after receiving or
transmitting handshake signal (ACK or NACK). In Slave mode, it is
used as pending signal. User should clear it after writing data into
Tx buffer or taking data from Rx buffer to inform Slave I2C circuit to
release SCL signal.
Bit 6 (IMS):
I2C Master/Slave mode select bit
0: Slave (Default)
1: Master
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eKTF5616/08
8-Bit Microcontroller
Bit 5 (ISS):
I2C C Fast/Standard mode select bit (if Fm is 4 MHz and
I2CTS1~0<0,0>)
0: Standard mode (100K bit/s)
1: Fast mode (400K bit/s)
Bit 4 (STOP):
In Master mode, if STOP=1 and R/nW=1, then MCU must return
nACK signal to Slave device before sending STOP signal. If
STOP=1 and R/nW=0, then MCU sends STOP signal after receiving
an ACK signal. MCU resets when it sends STOP signal to Slave
device.
In Slave mode, if STOP=1 and R/nW=0, then MCU must return
nACK signal to Master device.
Bit 3 (SAR_EMPTY): Set when MCU transmits 1 byte data from I2C Slave Address
Register and receive ACK (or nACK) signal. Reset when MCU
writes 1 byte data to I2C Slave Address Register.
Bit 2 (ACK):
The ACK condition bit is set to 1 by hardware when the device
responds with an acknowledge (ACK). Reset when the device
responds with a not-acknowledge (nACK) signal.
Bit 1 (FULL):
Bit 0 (EMPTY):
Set by hardware when I2C Receive Buffer register is full. Reset by
hardware when the MCU reads data from the I2C Receive Buffer
register.
Set by hardware when I2C Transmit Buffer register is empty and
ACK (or nACK) signal is received. Reset by hardware when the
MCU writes new data into the I2C Transmit Buffer register.
6.1.37 Bank 0 R31: I2CCR2 (I2C Status and Control Register 2)
Bit 7
I2CBF
R
Bit 6
GCEN
R/W
Bit 5
I2COPT
R/W
Bit 4
BBF
R
Bit 3
Bit 2
I2CTS1
R/W
Bit 1
I2CTS0
R/W
Bit 0
I2CEN
R/W
-
-
Bit 7 (I2CBF): I2C Busy Flag Bit
0: clear to "0" in Slave mode, if receives a STOP signal or when I2C slave
address does not match.
1: set when I2C communicate with master in slave mode.
*Set when STAR signal, clear when I2C disable or STOP signal for Slave
mode.
Bit 6 (GCEN): I2C General Call Function Enable Bit
0: Disable General Call Function
1: Enable General Call Function
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33
eKTF5616/08
8-Bit Microcontroller
Bit 5 (I2COPT): I2C pin optional bit. It is used to switch the pin position of I2C function.
0: Placed I2C pins in P52 (SDA0) and P53 (SCL0).
1: Placed I2C pins in P54 (SDA1) and P55 (SCL1).
*Default value corresponding code option Word 2 I2COPT
Bit 4 (BBF): Busy Flag Bit. I2C detection is busy in the master mode. Read only.
*Set when STAR signal, clear when STOP signal for Master mode.
Bit 3: Not used, set to “0” all the time.
Bits 2~1 (I2CTS1~I2CTS0): I2C Transmit Clock Select Bits. When using different
operating frequency (Fm), these bits must be set correctly to let SCL clock fill in with
standard/fast mode.
I2CCR1 Bit 5=1, Fast Mode
I2CTS1
I2CTS0
SCL CLK
Fm/10
Operating Fm (MHz)
0
0
1
1
0
1
0
1
4
8
Fm/20
Fm/30
12
16
Fm/40
I2CCR1 Bit 5=0, Standard Mode
I2CTS1
I2CTS0
SCL CLK
Fm/40
Operating Fm (MHz)
0
0
1
1
0
1
0
1
4
8
Fm/80
Fm/120
Fm/160
12
16
Bit 0 (I2CEN): I2C Enable Bit
0: Disable I2C mode (Default)
1: Enable I2C mode
6.1.38 Bank 0 R32: I2CSA (I2C Slave Address Register)
Bit 7
SA6
R/W
Bit 6
SA5
R/W
Bit 5
SA4
R/W
Bit 4
SA3
R/W
Bit 3
SA2
R/W
Bit 2
SA1
R/W
Bit 1
SA0
R/W
Bit 0
IRW
R/W
Bits 7~1 (SA6~SA0): When the MCU is used as Master device for I2C application, these
bits are the Slave Device Address register.
Bit 0 (IRW): When the MCU is used as Master device for I2C application, this bit is
Read/Write transaction control bit.
0: Write
1: Read
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IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
6.1.39 Bank 0 R33: I2CDB (I2C Data Buffer Register)
Bit 7
DB7
R/W
Bit 6
DB6
R/W
Bit 5
DB5
R/W
Bit 4
DB4
R/W
Bit 3
DB3
R/W
Bit 2
DB2
R/W
Bit 1
DB1
R/W
Bit 0
DB0
R/W
Bits 7~0 (DB7~DB0): I2C Receive/Transmit Data Buffer
6.1.40 Bank 0 R34: I2CDAL (I2C Device Address Register)
Bit 7
DA7
R/W
Bit 6
DA6
R/W
Bit 5
DA5
R/W
Bit 4
DA4
R/W
Bit 3
DA3
R/W
Bit 2
DA2
R/W
Bit 1
DA1
R/W
Bit 0
DA0
R/W
Bits 7~0 (DA7~DA0): When the MCU is used as Slave device for I2C application, this
register stores the MCU address. It is used to identify the data on the I2C
bus to extract the message delivered to the MCU.
NOTE
Slave Address 0x77 is reserved for WTR use.
6.1.41 Bank 0 R35: I2CDAH (I2C Device Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DA9
R/W
Bit 0
DA8
R/W
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7~2:
Not used. Set to "0" all the time.
Bits 1~0 (DA9~DA8): Device Address bits
6.1.42 Bank 0 R36: SPICR (SPI Control Register)
Bit 7
CES
R/W
Bit 6
SPIE
R/W
Bit 5
SRO
R
Bit 4
SSE
R/W
Bit 3
SDOC
R/W
Bit 2
SBRS2
R/W
Bit 1
SBRS1
R/W
Bit 0
SBRS0
R/W
Bit 7 (CES): Clock Edge Select bit
0: Data shift out on a rising edge, and shift in on a falling edge. Data is on
hold during a low-level.
1: Data shift out on a falling edge, and shift in on a rising edge. Data is on
hold during a high-level.
Bit 6 (SPIE): SPI Enable bit
0: Disable SPI mode
1: Enable SPI mode
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
35
eKTF5616/08
8-Bit Microcontroller
Bit 5 (SRO): SPI Read Overflow bit
0: No overflow
1: A new data is received while the previous data is still being held in the
SPIR register. Under this condition, the data in the SPIS register is
destroyed. To avoid setting this bit, user should read the SPIR register
although only transmission is implemented. This can only occur in
Slave mode.
Bit 4 (SSE): SPI Shift Enable bit
0: Reset as soon as the shifting is completed, and the next byte is read to
shift.
1: Start to shift, and it remains at "1" while the current byte is still being
transmitted.
Bit 3 (SDOC): SDO Output Status Control bit
0: After serial data output, the SDO remains high
1: After serial data output, the SDO remains low
Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select bits
SBRS2
SBRS1
SBRS0
Mode
Master
Master
Master
Master
Master
Master
Slave
SPI Baud Rate
Fosc/2
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
/SS enable
1
1
1
Slave
/SS disable
6.1.43 Bank 0 R37: SPIS (SPI Status Register)
Bit 7
DORD
R/W
Bit 6
TD1
R/W
Bit 5
TD0
R/W
Bit 4
Bit 3
OD3
R/W
Bit 2
Bit 1
Bit 0
RBF
R
-
-
OD4
R/W
-
-
Bit 7 (DORD): Data shift type control bit
0: Shift left (MSB first)
1: Shift right (LSB first)
Bits 6~5 (TD1~TD0): SDO status output delay time options (Normal mode only). When
the CPU oscillator source uses Fs, it will result in 1 CLK delay time.
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IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
NOTE
TD1~TD0 bits are applicable only to Normal mode Normal mode. If
under Sleep mode Normal mode condition, then Wake-up time is
“Warm up time + 1CLK”.
TD1
0
TD0
0
Delay Time
8 CLK
0
1
16 CLK
24 CLK
32 CLK
1
0
1
1
Bit 4:
Bit 3 (OD3): Open-drain control bit
0: Open-drain disabled for SDO
1: Open-drain enabled for SDO
Bit 2 (OD4): Open-drain control bit
Not used. Set to “0” all the time.
0: Open-drain disabled for SCK
1: Open-drain enabled for SCK
Bit 1:
Not used. Set to “0” all the time.
Bit 0 (RBF): Read Buffer Full flag
0: Receiving is not completed, and SPIR has not fully exchanged data.
1: Receiving is completed, and SPIR has fully exchanged data.
6.1.44 Bank 0 R38: SPIR (SPI Read Buffer Register)
Bit 7
SRB7
R
Bit 6
SRB6
R
Bit 5
SRB5
R
Bit 4
SRB4
R
Bit 3
SRB3
R
Bit 2
SRB2
R
Bit 1
SRB1
R
Bit 0
SRB0
R
Bits 7~0 (SRB7~SRB0): SPI Read Data Buffer
6.1.45 Bank 0 R39: SPIW (SPI Write Buffer Register)
Bit 7
SWB7
R/W
Bit 6
SWB6
R/W
Bit 5
SWB5
R/W
Bit 4
SWB4
R/W
Bit 3
SWB3
R/W
Bit 2
SWB2
R/W
Bit 1
SWB1
R/W
Bit 0
SWB0
R/W
Bits 7~0 (SWB7~SWB0): SPI Write Data Buffer
6.1.46 Bank 0 R3A ~ R3D: (Reserved)
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
37
eKTF5616/08
8-Bit Microcontroller
6.1.47 Bank 0 R3E: ADCR1 (ADC Control Register 1)
Bit 7
CKR2
R/W
Bit 6
CKR1
R/W
Bit 5
CKR0
R/W
Bit 4
ADRUN
R/W
Bit 3
ADP
R/W
Bit 2
ADOM
R/W
Bit 1
SHS1
R/W
Bit 0
SHS0
R/W
Bits 7~5 (CKR2~0): Clock Rate Selection of ADC
Max. System
Clock
Max. System
Operation
Frequency in
2.5~3V
Max. System
Operation
Frequency in
3~5.5V
System
Mode
Operation
Frequency in
2.2~2.5V
CKR2~0
Rate
000
001
010
011
100
101
110
111
FMain/4
FMain/8
-
-
-
-
-
8 MHz
16 MHz
16 MHz
16 MHz
16 MHz
16 MHz
Fs
FMain/16
FMain/32
FMain/64
FMain/128
FMain/256
FSub
-
-
-
8 MHz
12 MHz
16 MHz
16 MHz
Fs
Normal
Mode
-
-
8 MHz
Fs
Green
Mode
Fs
Fs
xxx
FSub
Fs
Bit 4 (ADRUN): ADC Starts to Run
In single mode:
0: Reset on completion of the conversion by hardware, this bit cannot be reset by
software.
1: A/D conversion starts. This bit can be set by software
In continuous mode:
0: ADC is stopped.
1: ADC is running unless this bit is reset by software
Bit 3 (ADP): ADC Power
0: ADC is in power down mode.
1: ADC is operating normally.
Bit 2 (ADOM): ADC Operation Mode Selection
0: ADC operates in single mode.
1: ADC operates in continuous mode.
Bits 1~0 (SHS1~0): Sample and Hold Timing Selection
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IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
SHS[1:0]
Sample and Hold Timing
00
01
10
11
2 x TAD
4 x TAD
8 x TAD
12 x TAD
6.1.48 Bank 0 R3F: ADCR2 (ADC Control Register 2)
Bit 7
Bit 6
VPIS2
R/W
Bit 5
ADIM
R/W
Bit 4
ADCMS
R/W
Bit 3
VPIS1
R/W
Bit 2
VPIS0
R/W
Bit 1
VREFP
R/W
Bit 0
-
-
-
-
Bit 7: Not used, set to "0" all the time.
Bit 5 (ADIM): ADC Interrupt Mode
0: Normal mode. Interrupt occurred after AD conversion is completed.
1: Compare mode. Interrupt occurred when comparison result conforms the
setting of ADCMS bits.
Bit 4 (ADCMS): ADC Comparison Mode Selection.
In compare mode:
0: Interrupt occurred when AD conversion data is greater than data in ADCD
register.
It means when ADD > ADCD, interrupt occurred.
1: Interrupt occurred when AD conversion data is less than data in ADCD
register.
It means when ADD < ADCD, interrupt occurred.
In normal mode:
No effect
Bits 6, 3 ~ 2 (VPIS2~0): Internal Positive Reference Voltage Selection.
VPIS[2]
VPIS[1:0]
Reference Voltage
0
0
0
0
1
00
01
10
11
AVDD
4 V
3 V
2.5 V
2 V
XX
Bit 1 (VREFP): Positive Reference Voltage Selection
0: Internal positive reference voltage. The actual voltage is set by VPIS[1:0] bits
1: From VREF pin.
Bit 0: Not used, set to "0" all the time.
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
39
eKTF5616/08
8-Bit Microcontroller
NOTE
When using internal voltage reference and the code option word2<7> is set to “0”,
users need to wait at least 50us the first time to enable and stabilize the internal
voltage reference circuit. After that, users only need to wait at least 6us whenever
switching voltage references.
6.1.49 Bank 0 R40: ADISR (Analog to Digital Converter Input Channel
Selection Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ADIS3
R/W
Bit 2
ADIS2
R/W
Bit 1
ADIS1
R/W
Bit 0
ADIS0
R/W
-
-
-
-
-
-
-
-
Bits 7~4: Not used, set to "0" all the time.
Bits 3~0 (ADIS4~0): ADC input channel selection bits
ADIS[3:0]
0000
Selected Channel
ADC0
0001
ADC1
0010
ADC2
0011
ADC3
0100
ADC4
0101
ADC5
0110
ADC6
0111
ADC7
1xxx*
1/2 VDD PowerDet.
Note:
*: For internal signal source use. Users only need to set ADIS3=1, these AD input channels
will be active instantly, internal Vref stable time = 4 µs.
6.1.50 Bank 0 R41: ADER1 (Analog to Digital Converter Input Control
Register 1)
Bit 7
ADE7
R/W
Bit 6
ADE6
R/W
Bit 5
ADE5
R/W
Bit 4
ADE4
R/W
Bit 3
ADE3
R/W
Bit 2
ADE2
R/W
Bit 1
ADE1
R/W
Bit 0
ADE0
R/W
Bit 7 (ADE7): AD converter enable bit of P87 pin.
0: Disable ADC7, P87/ADC7 act as I/O pin
1: Enable ADC7, act as analog input pin.
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eKTF5616/08
8-Bit Microcontroller
Bit 6 (ADE6): AD converter enable bit of P86 pin.
0: Disable ADC6, P86/ADC6 act as I/O pin
1: Enable ADC6, act as analog input pin
Bit 5 (ADE5): AD converter enable bit of P85 pin.
0: Disable ADC5, P85/ADC5 act as I/O pin
1: Enable ADC5, act as analog input pin
Bit 4 (ADE4): AD converter enable bit of P84 pin.
0: Disable ADC4, P84/VREF/ADC4 act as I/O or VREF pin
1: Enable ADC4, act as analog input pin
Bit 3 (ADE3): AD converter enable bit of P83 pin.
0: Disable ADC3, P83/TK16/ADC3 act as I/O or TK16 pin
1: Enable ADC3, act as analog input pin
Bit 2 (ADE2): AD converter enable bit of P82 pin.
0: Disable ADC2, P82/TK15/ADC2 act as I/O or TK15 pin
1: Enable ADC2, act as analog input pin
Bit 1 (ADE1): AD converter enable bit of P81 pin.
0: Disable ADC1, P81/TK14/ADC1/PWMB act as I/O or TK14/PWMB pin
1: Enable ADC1, act as analog input pin
Bit 0 (ADE0): AD converter enable bit of P80 pin.
0: Disable ADC0, P80/TK13/ADC0/VREF/PWMA act as I/O or TK13/PWMA
pin
1: Enable ADC0, act as analog input pin
6.1.51 Bank 0 R42: (Reserved)
6.1.52 Bank 0 R43: ADDL (Low Byte of Analog to Digital Converter
Data)
Bit 7
ADD7
R
Bit 6
ADD6
R
Bit 5
ADD5
R
Bit 4
ADD4
R
Bit 3
ADD3
R
Bit 2
ADD2
R
Bit 1
ADD1
R
Bit 0
ADD0
R
Bits 7~0 (ADD7~0): Low Byte of AD Data Buffer
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
41
eKTF5616/08
8-Bit Microcontroller
6.1.53 Bank 0 R44: ADDH (High Byte of Analog to Digital Converter
Data)
Bit 7
Bit 6
ADD10
R
Bit 5
ADD9
R
Bit 4
ADD8
R
Bit 3
ADD7
R
Bit 2
ADD6
R
Bit 1
ADD5
R
Bit 0
ADD4
R
ADD11
R
Bits 7~0 (ADD11~4): High Byte of AD Data Buffer
6.1.54 Bank 0 R45: ADCVL (Low Byte of Analog to Digital Converter
Comparison)
Bit 7
ADCD7
R/W
Bit 6
ADCD6
R/W
Bit 5
ADCD5
R/W
Bit 4
ADCD4
R/W
Bit 3
ADCD3
R/W
Bit 2
ADCD2
R/W
Bit 1
ADCD1
R/W
Bit 0
ADCD0
R/W
Bits 7~0 (ADCD7~0): Low Byte Data for AD Comparison.
User should use the data format the same as ADDH and ADDL register. Otherwise,
inaccurate result will be obtained after AD comparison.
6.1.55 Bank 0 R46: ADCVH (High Byte of Analog to Digital Converter
Comparison)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ADCD11 ADCD10
R/W R/W
Bit 2
Bit 1
ADCD9
R/W
Bit 0
ADCD8
R/W
-
-
-
-
-
-
-
-
Bits 3~0 (ADCD11~8): High Byte Data for AD Comparison
6.1.56 Bank 0 R47~4F: (Reserved)
6.1.57 Bank 1 R5: IOCR8
These registers are used to control I/O port direction. They are both readable and
writable.
1: Put the relative I/O pin into high impedance
0: Put the relative I/O pin as output
6.1.58 Bank 1 R6 ~ R7: (Reserved)
42
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
6.1.59 Bank 1 R8: P5PHCR (Port 5 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
PH55
R/W
Bit 4
PH54
R/W
Bit 3
PH53
R/W
Bit 2
PH52
R/W
Bit 1
PH51
R/W
Bit 0
PH50
R/W
-
-
-
-
Bits 7~6: Not used, set to "0" all the time.
Bit 5 (PH55): Control bit used to enable pull-high of the P55 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 4 (PH54): Control bit used to enable pull-high of the P54 pin
Bit 3 (PH53): Control bit used to enable pull-high of the P53 pin
Bit 2 (PH52): Control bit used to enable pull-high of the P52 pin
Bit 1 (PH51): Control bit used to enable pull-high of the P51 pin
Bit 0 (PH50): Control bit used to enable pull-high of the P50 pin
6.1.60 Bank 1 R9: P6PHCR (Port 6 Pull-high Control Register)
Bit 7
PH67
R/W
Bit 6
PH66
R/W
Bit 5
PH65
R/W
Bit 4
PH64
R/W
Bit 3
PH63
R/W
Bit 2
PH62
R/W
Bit 1
PH61
R/W
Bit 0
PH60
R/W
Bit 7 (PH67): Control bit used to enable pull-high of the P67 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (PH66): Control bit used to enable pull-high of the P66 pin
Bit 5 (PH65): Control bit used to enable pull-high of the P65 pin
Bit 4 (PH64): Control bit used to enable pull-high of the P64 pin
Bit 3 (PH63): Control bit used to enable pull-high of the P63 pin
Bit 2 (PH62): Control bit used to enable pull-high of the P62 pin
Bit 1 (PH61): Control bit used to enable pull-high of the P61 pin
Bit 0 (PH60): Control bit used to enable pull-high of the P60 pin
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
43
eKTF5616/08
8-Bit Microcontroller
6.1.61 Bank 1 RA: P78PHCR (Ports 7~8 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HPH
R/W
Bit 2
P8LPH
R/W
Bit 1
Bit 0
P7LPH
R/W
-
-
-
-
-
-
-
-
-
-
Bits 7~4,1: Not used, set to "0" all the time.
Bit 3 (P8HPH): Control bit used to enable the pull-high of Port 8 high nibble pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 2 (P8LPH): Control bit used to enable the pull-high of Port8 low nibble pin
Bit 0 (P7LPH): Control bit used to enable the pull-high of Port7 low nibble pin
6.1.62 Bank 1 RB: P5PLCR (Port 5 Pull-low Control Register)
Bit 7
Bit 6
Bit 5
PL55
R/W
Bit 4
PL54
R/W
Bit 3
PL53
R/W
Bit 2
PL52
R/W
Bit 1
PL51
R/W
Bit 0
PL50
R/W
-
-
-
-
Bits 7~6: Not used, set to "0" all the time.
Bit 5 (PL55): Control bit used to enable pull-low of the P55 pin
0: Enable internal pull-low
1: Disable internal pull-low
Bit 4 (PL54): Control bit used to enable pull-low of the P54 pin
Bit 3 (PL53): Control bit used to enable pull low of the P53 pin
Bit 2 (PL52): Control bit used to enable pull-low of the P52 pin
Bit 1 (PL51): Control bit used to enable pull-low of the P51 pin
Bit 0 (PL50): Control bit used to enable pull-low of the P50 pin
6.1.63 Bank 1 RC: P6PLCR (Port 6 Pull-low Control Register)
Bit 7
PL67
R/W
Bit 6
PL66
R/W
Bit 5
PL65
R/W
Bit 4
PL64
R/W
Bit 3
PL63
R/W
Bit 2
PL62
R/W
Bit 1
PL61
R/W
Bit 0
PL60
R/W
Bit 7 (PL67): Control bit used to enable the pull-low of P67 pin
0: Enable internal pull-low
1: Disable internal pull-low
44
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Bit 6 (PL66): Control bit used to enable the pull-low of P66 pin
Bit 5 (PL65): Control bit used to enable the pull-low of P65 pin
Bit 4 (PL64): Control bit used to enable the pull-low of P64 pin
Bit 3 (PL63): Control bit used to enable the pull-low of P63 pin
Bit 2 (PL62): Control bit used to enable the pull-low of P62 pin
Bit 1 (PL61): Control bit used to enable the pull-low of P61 pin
Bit 0 (PL60): Control bit used to enable the pull-low of P60 pin
6.1.64 Bank 1 RD: P78PLCR (Ports 7~8 Pull-low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HPL
R/W
Bit 2
P8LPL
R/W
Bit 1
Bit 0
P7LPL
R/W
-
-
-
-
-
-
-
-
-
-
Bits 7~4,1: Not used, set to "0" all the time.
Bit 3 (P8HPL): Control bit used to enable the pull-low of Port 8 high nibble pin
0: Enable internal pull-low
1: Disable internal pull-low
Bit 2 (P8LPL): Control bit used to enable the pull-low of Port 8 low nibble pin
Bit 0 (P7LPL): Control bit used to enable the pull-low of Port 7 low nibble pin
6.1.65 Bank 1 RE: P5HDSCR (Port 5 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
H55
R/W
Bit 4
H54
R/W
Bit 3
H53
R/W
Bit 2
H52
R/W
Bit 1
H51
R/W
Bit 0
H50
R/W
-
-
-
-
Bits 7~6: Not used, set to "0" all the time.
Bits 5~0 (H55~H50): P55~P50 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
45
eKTF5616/08
8-Bit Microcontroller
6.1.66 Bank 1 RF: P6HDSCR (Port 6 High Drive/Sink Control
Register)
Bit 7
H67
R/W
Bit 6
H66
R/W
Bit 5
H65
R/W
Bit 4
H64
R/W
Bit 3
H63
R/W
Bit 2
H62
R/W
Bit 1
H61
R/W
Bit 0
H60
R/W
Bits 7~0 (H67~H60): P67~P60 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
6.1.67 Bank 1 R10: P78HDSCR (Port 7~8 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HHDS P8LHDS
R/W R/W
Bit 2
Bit 1
Bit 0
P7LHDS
R/W
-
-
-
-
-
-
-
-
-
-
Bits 7~4,1: Not used, set to "0" all the time.
Bit 3 (P8HHDS): Control bit used to enable high drive/sink of Port8 high nibble pin
0: Enable high drive/sink
1: Disable high drive/sink
Bit 2 (P8LHDS): Control bit used to enable high drive/sink of Port8 low nibble pin
Bit 0 (P7LHDS): Control bit used to enable high drive/sink of Port7 low nibble pin
6.1.68 Bank 1 R11: P5ODCR (Port 5 Open-Drain Control Register)
Bit 7
Bit 6
Bit 5
OD55
R/W
Bit 4
OD54
R/W
Bit 3
OD53
R/W
Bit 2
OD52
R/W
Bit 1
OD51
R/W
Bit 0
OD50
R/W
-
-
-
-
Bits 7~6: Not used, set to "0" all the time.
Bits 5~0 (OD55~OD50): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
46
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
6.1.69 Bank 1 R12: P6ODCR (Port 6 Open-Drain Control Register)
Bit 7
OD67
R/W
Bit 6
OD66
R/W
Bit 5
OD65
R/W
Bit 4
OD64
R/W
Bit 3
OD63
R/W
Bit 2
OD62
R/W
Bit 1
OD61
R/W
Bit 0
OD60
R/W
Bits 7~0 (OD67~OD60): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.1.70 Bank 1 R13: P78ODCR (Ports 7~8 Open-Drain Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HOD
R/W
Bit 2
P8LOD
R/W
Bit 1
Bit 0
P7LOD
R/W
-
-
-
-
-
-
-
-
-
-
Bits 7~4,1: Not used, set to "0" all the time.
Bit 3 (P8HOD): Control bit used to enable open-drain of Port 8 high nibble pin
0: Disable open-drain function
1: Enable open-drain function
Bit 2 (P8LOD): Control bit used to enable open-drain of Port 8 low nibble pin
Bit 0 (P7LOD): Control bit used to enable open-drain of Port 7 low nibble pin
6.1.71 Bank 1 R14 ~ R15: (Reserved)
6.1.72 Bank 1 R16: PWMSCR (PWM Source Clock Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PWMBS
R/W
Bit 0
PWMAS
R/W
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7~2: Not used, set to "0" all the time.
Bit 1 (PWMBS): Clock selection for PWMB timer
0: Fs (default)
1: Fm
Bit 0 (PWMAS): Clock selection for PWMA timer
0: Fs (default)
1: Fm
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
47
eKTF5616/08
8-Bit Microcontroller
6.1.73 Bank 1 R17: PWMACR (PWMA Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TAEN
R/W
Bit 2
TAP2
R/W
Bit 1
TAP1
R/W
Bit 0
TAP0
R/W
PWMAE
R/W
-
-
-
-
-
-
Bit 7 (PWMAE): PWMA enable bit
0: Disable (default)
1: Enable. The compound pin is used as PWMA pin
Bits 6~4: Not used, set to "0" all the time.
Bit 3 (TAEN): TMRA enable bit. All PWM functions are valid only when this bit is set
0: TMRA is off (default value)
1: TMRA is on
PWMXEN
TXEN
Function description
0
0
1
1
0
1
0
1
Not used as PWM function; I/O pin or other functional pin.
Timer function; I/O pin or other function pin.
PWM function, the waveform keeps at low level.
PWM function, the normal PWM output waveform.
Bits 2~0 (TAP2~TAP0): TMRA clock prescaler option bits
TAP2
TAP1
TAP0
Prescale
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
6.1.74 Bank 1 R18: PRDAL (Low Byte of PWMA Period)
Bit 7
PRDA7
R/W
Bit 6
PRDA6
R/W
Bit 5
PRDA5
R/W
Bit 4
PRDA4
R/W
Bit 3
PRDA3
R/W
Bit 2
PRDA2
R/W
Bit 1
PRDA1
R/W
Bit 0
PRDA0
R/W
Bits 7~0 (PRDA7~0): The contents of the register are low bytes of the PWMA period.
48
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
NOTE
If the PWMA duty/period needs to reload, the PRDAL register must be updated.
6.1.75 Bank 1 R19: PRDAH (High Byte of PWMA Period)
Bit 7
PRDA15 PRDA14 PRDA13 PRDA12 PRDA11 PRDA10
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PRDA9
R/W
Bit 0
PRDA8
R/W
Bits 7~0 (PRDA15~8): The contents of the register are high bytes of PWMA period
6.1.76 Bank 1 R1A: DTAL (Low Byte of PMWA Duty)
Bit 7
DTA7
R/W
Bit 6
DTA6
R/W
Bit 5
DTA5
R/W
Bit 4
DTA4
R/W
Bit 3
DTA3
R/W
Bit 2
DTA2
R/W
Bit 1
DTA1
R/W
Bit 0
DTA0
R/W
Bits 7~0 (DTA7~0): The contents of the register are low bytes of the PWMA duty.
6.1.77 Bank 1 R1B: DTAH (High Byte of PMWA Duty)
Bit 7
DTA15
R/W
Bit 6
DTA14
R/W
Bit 5
DTA13
R/W
Bit 4
DTA12
R/W
Bit 3
DTA11
R/W
Bit 2
DTA10
R/W
Bit 1
DTA9
R/W
Bit 0
DTA8
R/W
Bits 7~0 (DTA15~8): The contents of the register are high bytes of the PWMA duty.
6.1.78 Bank 1 R1C: TMRAL (Low Byte of Timer 1)
Bit 7
TMRA7
R
Bit 6
TMRA6
R
Bit 5
TMRA5
R
Bit 4
TMRA4
R
Bit 3
TMRA3
R
Bit 2
TMRA2
R
Bit 1
TMRA1
R
Bit 0
TMRA0
R
Bits 7~0 (TMRA7~0): The contents of the register are low bytes of the PWMA timer which
is counting. This is read-only.
6.1.79 Bank 1 R1D: TMRAH (High Byte of Timer 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMRA9
R
Bit 0
TMRA8
R
TMRA15 TMRA14 TMRA13 TMRA12 TMRA11 TMRA10
R
R
R
R
R
R
Bits 7~0 (TMRA15~8): The contents of the register are high bytes of the PWMA timer
which is counting. This is read-only
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
49
eKTF5616/08
8-Bit Microcontroller
6.1.80 Bank 1 R1E: PWMBCR (PWMB Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TBEN
R/W
Bit 2
TBP2
R/W
Bit 1
TBP1
R/W
Bit 0
TBP0
R/W
PWMBE
R/W
-
-
-
-
-
-
Bit 7 (PWMBE): PWMB enable bit
0: Disable (default)
1: Enable. The compound pin is used as PWMB pin
Bits 6~4: Not used, set to "0" all the time.
Bit 3 (TBEN): TMRB enable bit. All PWM function is valid only when this bit is set
0: TMRB is off (default value)
1: TMRB is on
Bits 2~0 (TBP2~TBP0): TMRB clock prescaler option bits
TBP2
TBP1
TBP0
Prescale
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
6.1.81 Bank 1 R1F: PRDBL (Low Byte of PWMB Period)
Bit 7
PRDB7
R/W
Bit 6
PRDB6
R/W
Bit 5
PRDB5
R/W
Bit 4
PRDB4
R/W
Bit 3
PRDB3
R/W
Bit 2
PRDB2
R/W
Bit 1
PRDB1
R/W
Bit 0
PRDB0
R/W
Bits 7~0 (PRDB7~0): The contents of the register are low byte of the PWMB period
NOTE
If the PWMB duty/period needs to reload, the PRDBL register must be updated.
50
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eKTF5616/08
8-Bit Microcontroller
6.1.82 Bank 1 R20: PRDBH (High Byte of PWMB Period)
Bit 7
PRDB15 PRDB14 PRDB13 PRDB12 PRDB11 PRDB10
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PRDB9
R/W
Bit 0
PRDB8
R/W
Bits 7~0 (PRDB15~8): The contents of the register are high byte of PWMB period
6.1.83 Bank 1 R21: DTBL (Low Byte of PMWB Duty)
Bit 7
DTB7
R/W
Bit 6
DTB6
R/W
Bit 5
DTB5
R/W
Bit 4
DTB4
R/W
Bit 3
DTB3
R/W
Bit 2
DTB2
R/W
Bit 1
DTB1
R/W
Bit 0
DTB0
R/W
Bits 7~0 (DTB7~0): The contents of the register are low byte of the PWMB duty
6.1.84 Bank 1 R22: DTBH (High Byte of PMW2 Duty)
Bit 7
DTB15
R/W
Bit 6
DTB14
R/W
Bit 5
DTB13
R/W
Bit 4
DTB12
R/W
Bit 3
DTB11
R/W
Bit 2
DTB10
R/W
Bit 1
DTB9
R/W
Bit 0
DTB8
R/W
Bits 7~0 (DTB15~8): The contents of the register are high byte of the PWMB duty
6.1.85 Bank 1 R23: TMRBL (Low Byte of Timer B)
Bit 7
TMRB7
R
Bit 6
TMRB6
R
Bit 5
TMRB5
R
Bit 4
TMRB4
R
Bit 3
TMRB3
R
Bit 2
TMRB2
R
Bit 1
TMRB1
R
Bit 0
TMRB0
R
Bits 7~0 (TMRB7~0): The contents of the register are low byte of the PWMB timer which
is counting. This is read-only
6.1.86 Bank 1 R24: TMRBH (High Byte of Timer 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMRB9
R
Bit 0
TMRB8
R
TMRB15 TMRB14 TMRB13 TMRB12 TMRB11 TMRB10
R
R
R
R
R
R
Bits 7~0 (TMRB15~8): The contents of the register are high byte of the PWMB timer
which is counting. This is read-only
6.1.87 Bank 1 R25 ~ R32: (Reserved)
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
51
eKTF5616/08
8-Bit Microcontroller
6.1.88 Bank 1 R33: URCR (UART Control Register)
Bit 7
UINVEN UMODE1 UMODE0 BRATE2 BRATE1 BRATE0
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
UTBF
R
Bit 0
TXE
R/W
Bit 7 (UINVEN): Enable UART TXD and RXD Port Inverse Output Bit
0: Disable TXD and RXD port inverse output.
1: Enable TXD and RXD port inverse output.
Bits 6~5 (UMODE1~UMODE0): UART mode select bits
UMODE1
UMODE0
UART mode
Mode1: 7-bit
Mode1: 8-bit
Mode1: 9-bit
Reserved
0
0
1
1
0
1
0
1
Bits 4~2 (BRATE2~BRATE0): transmit Baud rate selection
BRATE2 BRATE1 BRATE0
Baud rate
Fc/13
8MHz
38400
19200
9600
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
Fc/26
Fc/52
Fc/104
Fc/208
Fc/416
4800
2400
1200
Reserved
Bit 1 (UTBF): UART transfer buffer empty flag. Set to 1 when transfer buffer is empty.
Reset to 0 automatically when write into URTD register. UTBF bit will be cleared by
hardware when enabling transmission. And UTBF bit is read-only. Therefore, write URTD
register is necessary when starting transmitting shifting.
Bit 0 (TXE): Enable transmission
0: Disable
1: Enable
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eKTF5616/08
8-Bit Microcontroller
6.1.89 Bank 1 R34: URS (UART Status Register)
Bit 7
URTD8
W
Bit 6
EVEN
R/W
Bit 5
PRE
R/W
Bit 4
PRERR
R/W
Bit 3
OVERR
R/W
Bit 2
FMERR
R/W
Bit 1
URBF
R
Bit 0
RXE
R/W
Bit 7 (URTD8): UART transmit data bit 8. Write only.
Bit 6 (EVEN): select parity check
0: Odd parity
1: Even parity
Bit 5 (PRE): enable parity addition
0: Disable
1: Enable
Bit 4 (PRERR): Parity error flag. Set to 1 when parity error happened, and clear to 0 by
software.
Bit 3 (OVERR): Over running error flag. Set to 1 when overrun error happened, and clear
to 0 by software.
Bit 2 (FMERR): Framing error flag. Set to 1 when framing error happen, and clear to 0 by
software.
Bit 1 (URBF): UART read buffer full flag. Set to 1 when one character is received. Reset to
0 automatically when read from URRDL register. URBF will be cleared by hardware when
enabling receiving. And URBF bit is read-only. Therefore, read URRDL register is
necessary to avoid overrun error.
Bit 0 (RXE): Enable receiving
0: Disable
1: Enable
6.1.90 Bank 1 R35: URTD (UART Transmit Data Buffer Register)
Bit 7
URTD7
W
Bit 6
URTD6
W
Bit 5
URTD5
W
Bit 4
URTD4
W
Bit 3
URTD3
W
Bit 2
URTD2
W
Bit 1
URTD1
W
Bit 0
URTD0
W
Bits 7~0 (URTD7~URTD0): UART transmit data buffer. Write only.
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
53
eKTF5616/08
8-Bit Microcontroller
6.1.91 Bank 1 R36: URRDL (UART Receive Data Low Buffer Register)
Bit 7
Bit 6
URRD6
R
Bit 5
URRD5
R
Bit 4
URRD4
R
Bit 3
URRD3
R
Bit 2
URRD2
R
Bit 1
URRD1
R
Bit 0
URRD0
R
URRD7
R
Bits 7~0 (URRD7~URRD0): UART Receive Data Buffer. Read only
6.1.92 Bank 1 R37: URRDH (UART Receive Data High Buffer
Register)
Bit 7
URRD8
R
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URSS
R/W
-
-
-
-
-
-
-
-
-
-
-
-
Bit 7 (URRD8): UART receive data bit 8. Read only.
Bits 6~1: Not used, set to "0" all the time.
Bit 0 (URSS): UART clock source select bit
0: Fc is set to Fs
1: Fc is set to Fm (Default)
6.1.93 Bank 1 R38 ~ R3F: (Reserved)
6.1.94 Bank 1 R40: EECR1 (EEPROM Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RD
Bit 0
WR
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
Bits 7~2: unused bit, set to 0 all the time
Bit 1(RD): Read control bit
0: Don’t execute EEPROM read
1: Read EEPROM content (RD can be set by software. When read instruction
is completed, RD will be cleared by hardware.)
Bit 0 (WR): Write control bit
0: Write cycle to the EEPROM is completed.
1: Initiate a write cycle (WR can be set by software. When write cycle is
completed, WR will be cleared by hardware).
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eKTF5616/08
8-Bit Microcontroller
6.1.95 Bank 1 R41: EECR2 (EEPROM Control Register 2)
Bit 7
EEWE
R/W
Bit 6
EEDF
R/W
Bit 5
EEPC
R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
Bit 7 (EEWE): EEPROM write enable bit
0: Prohibit write to the EEPROM
1: Allow EEPROM write cycles
Bit 6 (EEDF): EEPROM detect flag
0: Write cycle is completed
1: Write cycle is unfinished
Bit 5 (EEPC): EEPROM power down control bit
0: Switch of EEPROM
1: EEPROM is operating
Bits 4~0: unused bit, set to 0 all the time
6.1.96 Bank 1 R42: EERA (EEPROM Address)
Bit 7
Bit 6
EERA6
R/W
Bit 5
EERA5
R/W
Bit 4
EERA4
R/W
Bit 3
EERA3
R/W
Bit 2
EERA2
R/W
Bit 1
EERA1
R/W
Bit 0
EERA0
R/W
-
-
Bits 6~0 (EERA6~EERA0): EEPROM address register
6.1.97 Bank 1 R43: EERD (EEPROM Data)
Bit 7
EERD7
R/W
Bit 6
EERD6
R/W
Bit 5
EERD5
R/W
Bit 4
EERD4
R/W
Bit 3
EERD3
R/W
Bit 2
EERD2
R/W
Bit 1
EERD1
R/W
Bit 0
EERD0
R/W
Bits 7~0 (EERD7~EERD0): EEPROM data register.
6.1.98 Bank 1 R44: FLKR (Flash Key Register for Table write use)
Bit 7
FLK[7]
R/W
Bit 6
FLK[6]
R/W
Bit 5
FLK[5]
R/W
Bit 4
FLK[4]
R/W
Bit 3
FLK[3]
R/W
Bit 2
FLK[2]
R/W
Bit 1
FLK[1]
R/W
Bit 0
FLK[0]
R/W
This FLASHKEY register is used by table write IAP mode operation. The IAP enable signal
is generated when a specific value is written into this register, e.g., 0xB4. The register is
designed to make sure that IAP operation occurs for flash update. Written into register
value 0XC5. The register is designed to make sure that IAP lock.
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
55
eKTF5616/08
8-Bit Microcontroller
6.1.99 Bank 1 R45: TBPTL (Table Point Low Register)
Bit 7
Bit 6
TB6
R/W
Bit 5
TB5
R/W
Bit 4
TB4
R/W
Bit 3
TB3
R/W
Bit 2
TB2
R/W
Bit 1
TB1
R/W
Bit 0
TB0
R/W
TB7
R/W
Bits 7~0 (TB7~TB0): Table Point Address Bits 7~0.
6.1.100 Bank 1 R46: TBPTH (Table Point High Register)
Bit 7
HLB
R/W
Bit 6
Bit 5
Bit 4
Bit 3
TB11
R/W
Bit 2
TB10
R/W
Bit 1
TB9
R/W
Bit 0
TB8
R/W
-
-
-
-
-
-
Bit 7 (HLB): Obtain MLB or LSB at machine code of ROM or Data area.
0: the address of read byte value is Bit7 ~Bit0
1: the address of read byte value is Bit15~Bit8
Bits 6~4: unused bit, set to 0 all the time
Bits 5~0 (TB11~TB8): Table point Address Bits 11~8.
6.1.101 Bank 1 R47: STKMON (Stack Pointer)
Bit 7
STOV
R
Bit 6
Bit 5
Bit 4
Bit 3
STL3
R
Bit 2
STL2
R
Bit 1
STL1
R
Bit 0
STL0
R
-
-
-
-
-
-
Bit 7 (STOV): Stack pointer overflow indicator bit. Read only.
Bits 4~0 (STL3~0): Stack pointer number. Read only.
6.1.102 Bank 1 R48: PCH (Program Counter High)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PC11
R/W
Bit 2
PC10
R/W
Bit 1
PC9
R/W
Bit 0
PC8
R/W
-
-
-
-
-
-
-
-
Bits 7~4:
Not used. Set to “0” all the time.
Bits 3~0 (PC11~PC8): The high byte of program counter
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(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
6.1.103 Bank 1 R49: HLVDCR (High / Low Voltage Detector Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
HLVDS3 HLVDS2 HLVDS1 HLVDS0
R/W R/W R/W R/W
Bit 2
Bit 1
Bit 0
HLVDEN
R/W
IRVSF
R
VDSB
R
VDM
R/W
Bit 7 (HLVDEN): High/Low Voltage Detector Enable Bit
0: Disable low voltage detector (LVD function related setting must be disabled
in HLVDEN)
1: Enable low voltage detector
Bit 6 (IRVSF): Internal Reference Voltage Stable Flag bit
1: Indicate that the voltage detect logic will generate the interrupt flag at the
specified voltage range
0: Indicate that the voltage detect logic will not generate the interrupt flag at the
specified voltage range and the HLVD interrupt should not be enabled
Bit 5 (VDSB): Voltage Detector State Bit. This is a read only bit.
1: VDD > HLVD trip point (HLVDS<3:0>)
0: VDD < HLVD trip point (HLVDS<3:0>)
Bit 4 (VDM): Voltage Direction Magnitude Select bit
1: Event occurs when voltage equals or exceeds trip point (HLVDS<3:0>)
0: Event occurs when voltage equals or falls below trip point (HLVDS<3:0>)
HLVDIE HLVDEN
VDM
IRVSF
VDSB
HLVDSF
Interrupt
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
X
X
1
1
0
0
1
1
1
1
X
0
1
1
1
1
0->1
1->0
0->1
1->0
X
0->1
0
Not happened
Not happened
Not happened
Not happened
Not happened
Not happened
Happened
0
0->1
0
X
0
0->1
1->0
0->1
1->0
0->1
0
Not happened
Not happened
Happened
0
0->1
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
57
eKTF5616/08
8-Bit Microcontroller
Bits 3~0 (HLVDS3~HLVDS0): High/Low Voltage Detector Level Bits
HLVDS3 HLVDS2 HLVDS1 HLVDS0
HLVD Voltage Level
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4.73V
4.53V
4.33V
4.14V
3.94V
3.74V
3.54V
3.34V
3.14V
2.94V
2.84V
2.64V
2.54V
2.44V
2.34V
2.24V
6.1.104 Bank 1 R4A~ R4C: (Reserved)
6.1.105 Bank 1 R4D: TBWCR (Table Write Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IAPEN
R/W
Bit 7~1: not used, fixed to “0” all the time.
Bits 0 (IAPEN): IAP enable bit
0: IAP mode Disable.
1: IAP mode Enable.
6.1.106 Bank 1 R4E: TBWAL (Table Write start Address Low byte)
Bit 7
TBWA[7] TBWA[6] TBWA[5] TBWA[4] TBWA[3] TBWA[2] TBWA[1] TBWA[0]
R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
Bits 7~0(TBWA[7]~TBWA[0]): Table write star address bits 7~0, TBWA[4]~TBWA[0]
always fixed to “0”.
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IC Product Specification (V1.3) 09.10.2019
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eKTF5616/08
8-Bit Microcontroller
6.1.107 Bank 1 R4F: TBWAH (Table Write start Address High byte)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TBWA[11] TBWA[10] TBWA[9] TBWA[8]
R/W R/W R/W R/W
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bits 7~4: Fixed to “0” all the time. (Read only)
Bits 3~0(TBWA[11]~TBWA[8]): Table write address bits 11~8.
※Note:
ROM Code Buffer
(Start)
Table Write ROM Address
(Destination)
BANK3 0x80
BANK3 0x81
BANK3 0x82
BANK3 0x83
[TBWA] Low byte(bits7~0)
[TBWA] High byte(bits14~8)
[TBWA+1] Low byte(bits7~0)
[TBWA+1] High byte(bits14~8)
BANK3 0XBE
BANK3 0XBF
[TBWA+31] Low byte(bits7~0)
[TBWA+31] High byte(bits14~8)
6.1.108 Bank 2 R5: TKAPC (Touch Key Group A Pin Control Register)
Bit 7
TKAEP7 TKAEP6 TKAEP5 TKAEP4 TKAEP3 TKAEP2 TKAEP1 TKAEP0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7 (TKAEP7): Touch Key Enable Pin Control Bits
0: P67/TK8 is P67 pin.
1: Functions as Touch Key pin, TK8 is TK Sensor.
Bits 6 (TKAEP6): Touch Key Enable Pin Control Bits
0: P66/TK7 is P66 pin.
1: Functions as Touch Key pin, TK7 is TK Sensor.
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
59
eKTF5616/08
8-Bit Microcontroller
Bits 5 (TKAEP5): Touch Key Enable Pin Control Bits
0: P65/TK6 is P65 pin.
1: Functions as Touch Key pin, TK6 is TK Sensor.
Bits 4 (TKAEP4): Touch Key Enable Pin Control Bits
0: P64/TK5 is P64 pin.
1: Functions as Touch Key pin, TK5 is TK Sensor.
Bits 3 (TKAEP3): Touch Key Enable Pin Control Bits
0: P63/TK4 is P63 pin.
1: Functions as Touch Key pin, TK4 is TK Sensor.
Bits 2 (TKAEP2): Touch Key Enable Pin Control Bits
0: P62/TK3 is P62 pin.
1: Functions as Touch Key pin, TK3 is TK Sensor.
Bits 1 (TKAEP1): Touch Key Enable Pin Control Bits
0: P61/TK2 is P61 pin.
1: Functions as Touch Key pin, TK2 is TK Sensor.
Bits 0 (TKAEP0): Touch Key Enable Pin Control Bits
0: P60/TK1 is P60 pin.
1: Functions as Touch Key pin, TK1 is TK Sensor.
6.1.109 Bank 2 R6: TKBPC (Touch Key Group B Pin Control Register)
Bit 7
TKBEP7 TKBEP6 TKBEP5 TKBEP4 TKBEP3 TKBEP2 TKBEP1 TKBEP0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7 (TKBEP7): Touch Key Enable Pin Control Bits
0: P83/TK16/AD3 is P83/AD3 pin.
1: Functions as Touch Key pin, TK16 is TK Sensor.
Bits 6 (TKBEP6): Touch Key Enable Pin Control Bits
0: P82/TK15/AD2 is P82/AD2 pin.
1: Functions as Touch Key pin, TK15 is TK Sensor.
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eKTF5616/08
8-Bit Microcontroller
Bits 5 (TKBEP5): Touch Key Enable Pin Control Bits
0: P81/TK14/AD1/PWMB is P81/AD1/PWM pin.
1: Functions as Touch Key pin, TK14 is TK Sensor.
Bits 4 (TKBEP4): Touch Key Enable Pin Control Bits
0: P80/TK13/AD0/PWMA is P80/AD0/PWMA pin.
1: Functions as Touch Key pin, TK13 is TK Sensor.
Bits 3 (TKBEP3): Touch Key Enable Pin Control Bits
0: P73/TK12 is P73 pin.
1: Functions as Touch Key pin, TK12 is TK Sensor.
Bits 2 (TKBEP2): Touch Key Enable Pin Control Bits
0: P72/TK11 is P72 pin.
1: Functions as Touch Key pin, TK11 is TK Sensor.
Bits 1 (TKBEP1): Touch Key Enable Pin Control Bits
0: P71/TK10 is P71 pin.
1: Functions as Touch Key pin, TK10 is TK Sensor.
Bits 0 (TKBEP0): Touch Key Enable Pin Control Bits
0: P70/TK9 is P70 pin.
1: Functions as Touch Key pin, TK9 is TK Sensor.
6.1.110 Bank 2 R7: TKASCR (Touch Key Group A Select Control
Register)
Bit 7
TKAEN
R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
TKASW2 TKASW1 TKASW0
R/W R/W R/W
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bit 7 (TKAEN): Touch Key Group A Enable Bit
0: Disable.
1: Enable.
Bit 6~3: not used, fixed to “0” all the time.
Bits 2~0 (TKASW2~TKASW0): Touch Key Group A pin Selected Bits.
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
61
eKTF5616/08
8-Bit Microcontroller
TKASW[2:0]
Selected Channel
000
001
010
011
100
101
110
111
TK1
TK2
TK3
TK4
TK5
TK6
TK7
TK8
6.1.111 Bank 2 R8: TKBSCR (Touch Key Group B Select Control
Register)
Bit 7
TKBEN
R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
TKBSW2 TKBSW1 TKBSW0
R/W
R/W
R/W
Bit 7 (TKBEN): Touch Key Group B Enable Bit
0: Disable.
1: Enable.
Bit 6~3: not used, fixed to “0” all the time.
Bits 2~0 (TKBSW2~TKBSW0): Touch Key Group B pin Selected Bits.
TKBSW[2:0]
000
Selected Channel
TK9
001
TK10
010
TK11
011
TK12
100
TK13
101
TK14
110
TK15
111
TK16
6.1.112 Bank 2 R9 ~ RC: (Reserved)
6.1.113 Bank 2 RD: TKCR (Touch Key Control Register)
Bit 7
TKS
R/W
Bit 6
LDOEN
R/W
Bit 5
TKPSB
R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GMC
R/W
-
-
-
-
-
-
-
-
Bit 7 (TKS): TK Conversion start bit.
0: Reset on completion of the conversion by hardware, this bit cannot be reset by
software.
1: Conversion start
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eKTF5616/08
8-Bit Microcontroller
Bit 6 (LDOEN): LDO Enable bit, if TK power source from VDD, this bit will be invalid.
0: LDO Disable
1: LDO Enable (Default)
Bit 5 (TKPSB): TK power source select bit.
0: TK power source from TK Regulator. (Default)
1: TK power source from VDD.
Bit 4~1: not used, fixed to “0” all the time.
Bits 0 (GMC): Touch Key Gain control Bit.
0: High gain sensing (Default)
1: Normal gain sensing
6.1.114 Bank 2 RE: TKCCR (Touch Key Calculate Cycle Register)
Bit 7
TCCY7
R/W
Bit 6
TCCY6
R/W
Bit 5
TCCY5
R/W
Bit 4
TCCY4
R/W
Bit 3
TCCY3
R/W
Bit 2
TCCY2
R/W
Bit 1
TCCY1
R/W
Bit 0
TCCY0
R/W
Bits 7~0 (TCCY7~TCCY0): Touch Key Calculate Cycle set bits, the register default value
= 0x40.
*Cycle=(TKCCR+1)*2
6.1.115 Bank 2 RF: TKCSR (Touch Key Calculate Step Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CS3
R/W
Bit 2
CS2
R/W
Bit 1
CS1
R/W
Bit 0
CS0
R/W
-
-
-
-
-
-
-
-
Bit 7~4: not used, fixed to “0” all the time.
Bits 3~0 (CS3~CS0): Calculate Step select bits, the register default value = 0x0A.
6.1.116 Bank 2 R10: TKCTR (Touch Key Calculate Time Register)
Bit 7
TCT7
R/W
Bit 6
TCT6
R/W
Bit 5
TCT5
R/W
Bit 4
TCT4
R/W
Bit 3
TCT3
R/W
Bit 2
TCT2
R/W
Bit 1
TCT1
R/W
Bit 0
TCT0
R/W
Bits 7~0 (TCT7~TCT0): Calculate time set bits, the register default value = 0x40.
Note: The TKCTR must be greater than 0x35.
IC Product Specification (V1.3) 09.10.2019
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63
eKTF5616/08
8-Bit Microcontroller
6.1.117 Bank 2 R11: TKSWR (Touch Key Sensing Window Register)
Bit 7
Bit 6
Bit 5
Bit 4
TSW4
R/W
Bit 3
TSW3
R/W
Bit 2
TSW2
R/W
Bit 1
TSW1
R/W
Bit 0
TSW0
R/W
-
-
-
-
-
-
Bit 7~5: not used, fixed to “0” all the time.
Bits 4~0 (TSW4~TSW0): Touch Key Sensing Window set bits, the register default value =
0x0A.
6.1.118 Bank 2 R12: TKAH (The Most Significant Byte of A Group
Touch Key Buffer)
Bit 7
TKA[15]
R
Bit 6
TKA[14]
R
Bit 5
TKA[13]
R
Bit 4
TKA[12]
R
Bit 3
TKA[11]
R
Bit 2
TKA[10]
R
Bit 1
TKA[9]
R
Bit 0
TKA[8]
R
Bits 7~0 (TKA [15]~TKA[8]): The Most Significant Byte of A Group Touch Key Buffer.
6.1.119 Bank 2 R13: TKAL (The Least Significant Byte of A Group
Touch Key Buffer)
Bit 7
TKA[7]
R
Bit 6
TKA[6]
R
Bit 5
TKA[5]
R
Bit 4
TKA[4]
R
Bit 3
TKA[3]
R
Bit 2
TKA[2]
R
Bit 1
TKA[1]
R
Bit 0
TKA[0]
R
Bits 7~0 (TKA[7]~TKA[0]): The Least Significant Byte of A Group Touch Key Buffer.
6.1.120 Bank 2 R14: TKBH (The Most Significant Byte of B Group
Touch Key Buffer)
Bit 7
TKB[15]
R
Bit 6
TKB[14]
R
Bit 5
TKB[13]
R
Bit 4
TKB[12]
R
Bit 3
TKB[11]
R
Bit 2
TKB[10]
R
Bit 1
TKB[9]
R
Bit 0
TKB[8]
R
Bits 7~0 (TKB[15]~TKB[8]): The Most Significant Byte of B Group Touch Key Buffer.
6.1.121 Bank 2 R15: TKBL (The Least Significant Byte of B Group
Touch Key Buffer)
Bit 7
TKB[7]
R
Bit 6
TKB[6]
R
Bit 5
TKB[5]
R
Bit 4
TKB[4]
R
Bit 3
TKB[3]
R
Bit 2
TKB[2]
R
Bit 1
TKB[1]
R
Bit 0
TKB[0]
R
Bits 7~0 (TKB[7]~TKB[0]): The Least Significant Byte of B Group Touch Key Buffer.
64
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
6.1.122 Bank 2 R16: TKSCR (Touch Key idle Scan Control Register)
Bit 7
TKMCS1 TKMCS0
R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
TKISE
R/W
Bit 2
TKST2
R/W
Bit 1
TKST1
R/W
Bit 0
TKST0
R/W
-
-
-
-
Bit 7~6 (TKMCS1~0): Touch Key Multi-pin combine mode select bits.
Group A
Condition Condition
Group B
TKMCS1 TKMCS0
Note
Depend
on
TKASCR
Depend
on
TKBSCR
0
0
0
1
1.Suggest for “TK idle with scan
Mode” Application.
2. TK Idle with scan mode only have 1
flow
TK1~8
Combine
TK9~16
Combine
1.Suggest for “TK idle with scan
Mode” Application.
TK1~4
Combine
TK9~12
Combine
2. TK Idle with scan mode have 2
flows,
1
1
0
1
And this condition is the 1st flow mode
1.Suggest for “TK idle with scan
Mode” Application.
TK5~8
Combine
TK13~16
Combine
2. TK Idle with scan mode have 2 flows
And this condition is the 2nd flow mode
Bit 5,4: not used, fixed to “0” all the time.
Bit 3 (TKISE): TK idle with scan mode enable bit, for Low consumption application.
0: Disable
1: Enable, TK automatically scan for sleep mode condition.
Bits 2~0 (TKST2~TKST0): Touch Key idle scan time setting Bits.
000: 12.5ms
001: 25ms
010: 50ms
011: 100ms
100: 200ms
101: 400ms
110: 800ms
111: 1600ms
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6.1.123 Bank 2 R17: TKA1WBH (TK Group A idle Scan Wakeup Base
High byte Register 1)
Bit 7
TA1WB[15] TA1WB[14] TA1WB[13] TA1WB[12] TA1WB[11] TA1WB[10] TA1WB[9] TA1WB[8]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (TA1WB[15]~TA1WB[8]): 1st flow TK group A idle scan wakeup base high byte
set bits.
6.1.124 Bank 2 R18: TKA1WBL (TK Group A idle Scan Wakeup Base
Low byte Register 1)
Bit 7
TA1WB[7] TA1WB[6] TA1WB[5] TA1WB[4] TA1WB[3] TA1WB[2] TA1WB[1] TA1WB[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (TA1WB[7]~TA1WB[0]): 1st flow TK group A idle scan wakeup base high byte set
bits.
6.1.125 Bank 2 R19: TKA1WR (Touch Key of Group A idle scan
Wakeup Range Register 1)
Bit 7
TA1WR[7] TA1WR[6] TA1WR[5] TA1WR[4] TA1WR[3] TA1WR[2] TA1WR[1] TA1WR[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~6 (TA1WR[7:6]): 1st flow TK group A idle scan wakeup range multiple set bits.
Bits 5~0 (TA1WR[5:0]): 1st flow TK group A idle scan wakeup range multiplicand set bits.
Tx1WR[7:6]
Idle scan wakeup range
Tx1WR[5:0] x 1
00
01
10
Tx1WR[5:0] x 2
Tx1WR[5:0] x 4
11
Tx1WR[5:0] x 8
*X = A, B
6.1.126 Bank 2 R1A: TKA2WBH (TK Group A idle Scan Wakeup Base
High byte Register 2)
Bit 7
TA2WB[15] TA2WB[14] TA2WB[13] TA2WB[12] TA2WB[11] TA2WB[10] TA2WB[9] TA2WB[8]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (TA2WB[15]~TA2WB[8]): 2nd flow TK group A idle scan wakeup base high byte
set bits.
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8-Bit Microcontroller
6.1.127 Bank 2 R1B: TKA2WBL (TK Group A idle Scan Wakeup Base
Low byte Register 2)
Bit 7
TA2WB[7] TA2WB[6] TA2WB[5] TA2WB[4] TA2WB[3] TA2WB[2] TA2WB[1] TA2WB[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (TA2WB[7]~TA2WB[0]): 2nd flow TK group A idle scan wakeup base high byte
set bits.
6.1.128 Bank 2 R1C: TKA2WR (Touch Key of Group A idle scan
Wakeup Range Register 2)
Bit 7
TA2WR[7] TA2WR[6] TA2WR[5] TA2WR[4] TA2WR[3] TA2WR[2] TA2WR[1] TA2WR[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~6 (TA2WR[7:6]): 1st flow TK group A idle scan wakeup range multiple set bits.
Bits 5~0 (TA2WR[5:0]): 1st flow TK group A idle scan wakeup range multiplicand set bits.
Tx2WR[7:6]
Idle scan wakeup range
Tx2WR[5:0] x 1
00
01
10
Tx2WR[5:0] x 2
Tx2WR[5:0] x 4
11
Tx2WR[5:0] x 8
*X = A,B
6.1.129 Bank 2 R1D: TKB1WBH (TK Group B idle Scan Wakeup Base
High byte Register 1)
Bit 7
TB1WB[15] TB1WB[14] TB1WB[13] TB1WB[12] TB1WB[11] TB1WB[10] TB1WB[9] TB1WB[8]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (TB1WB[15]~TB1WB[8]): 1st flow TK group B idle scan wakeup base high byte
set bits.
6.1.130 Bank 2 R1E: TKB1WBL (TK Group B idle Scan Wakeup Base
Low byte Register 1)
Bit 7
TB1WB[7] TB1WB[6] TB1WB[5] TB1WB[4] TB1WB[3] TB1WB[2] TB1WB[1] TB1WB[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (TB1WB[7]~TB1WB[0]): 1st flow TK group B idle scan wakeup base high byte set
bits.
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8-Bit Microcontroller
6.1.131 Bank 2 R1F: TKB1WR (Touch Key of Group B idle scan
Wakeup Range Register 1)
Bit 7
TB1WR[7] TB1WR[6] TB1WR[5] TB1WR[4] TB1WR[3] TB1WR[2] TB1WR[1] TB1WR[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~6 (TB1WR[7:6]): 1st flow TK group B idle scan wakeup range multiple set bits.
Bits 5~0 (TB1WR[5:0]): 1st flow TK group B idle scan wakeup range multiplicand set bits.
Tx1WR[7:6]
Idle scan wakeup range
Tx1WR[5:0] x 1
00
01
10
Tx1WR[5:0] x 2
Tx1WR[5:0] x 4
11
Tx1WR[5:0] x 8
*X = A, B
6.1.132 Bank 2 R20: TKB2WBH (TK Group B idle Scan Wakeup Base
High byte Register 2)
Bit 7
TB2WB[15] TB2WB[14] TB2WB[13] TB2WB[12] TB2WB[11] TB2WB[10] TB2WB[9] TB2WB[8]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (TB2WB[15]~TB2WB[8]): 2nd flow TK group B idle scan wakeup base high byte
set bits.
6.1.133 Bank 2 R21: TKB2WBL (TK Group B idle Scan Wakeup Base
Low byte Register 2)
Bit 7
TB2WB[7] TB2WB[6] TB2WB[5] TB2WB[4] TB2WB[3] TB2WB[2] TB2WB[1] TB2WB[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (TB2WB[7]~TB2WB[0]): 2nd flow TK group B idle scan wakeup base high byte
set bits.
6.1.134 Bank 2 R22: TKB2WR (Touch Key of Group B idle scan
Wakeup Range Register 2)
Bit 7
TB2WR[7] TB2WR[6] TB2WR[5] TB2WR[4] TB2WR[3] TB2WR[2] TB2WR[1] TB2WR[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~6 (TB2WR[7:6]): 2nd flow TK group B idle scan wakeup range multiple set bits.
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eKTF5616/08
8-Bit Microcontroller
Bits 5~0 (TB2WR[5:0]): 2nd flow TK group B idle scan wakeup range multiplicand set bits.
Tx2WR[1:0]
Idle scan wakeup range
Tx2WR[5:0] x 1
00
01
10
11
Tx2WR[5:0] x 2
Tx2WR[5:0] x 4
Tx2WR[5:0] x 8
*X = A,B
6.1.135 Bank 2 R23 ~ R46: (Reserved)
6.1.136 Bank 2 R47: LOCKPR (Lock Page Number Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
LOCKPR4 LOCKPR3 LOCKPR2 LOCKPR1 LOCKPR0
R/W
R/W
R/W
R/W
R/W
Bits 4~0 (LOCKPR6~ LOCKPR0): Lock Page Number
*IAP Enhanced Protect Lock Address (1step = 128word)
6.1.137 Bank 2 R48: LOCKCR (Lock Control Register)
Bit 7
LOCKEN
R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit 7 (LOCKEN): Enhanced Protect Control Bit
1: Enable
0: Disable (Default)
Bits 6~0: Not used, set to “0” all the time.
6.1.138 Bank 2 R49 ~ R4F: (Reserved)
6.1.139 R50~R7F, Banks 0~3 R80~RFF
These are all 8-bit general-purpose registers.
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8-Bit Microcontroller
6.2 TCC/WDT and Prescaler
Two 8-bit counters are available as prescalers for the TCC and WDT. The TPSR0~ TPSR2
bits of the TCCCR register (Bank 0 R22) are used to determine the ratio of the TCC
prescaler. Likewise, the WPSR0~WPSR2 bits of the WDTCR register (Section 6.1.28
Bank 0 R21) are used to determine the WDT prescaler. The prescaler counter is cleared
by the instructions each time they are written into TCC. The WDT and prescaler are
cleared by the “WDTC” and “SLEP” instructions. Figure 6-3 below depicts the circuit
diagram of TCC/WDT.
The TCCD (Section 6.1.27 TCC Data Register) is an 8-bit timer/counter. The TCC clock
source is from the internal clock only and TCC will be incremented by 1 at Fc clock (without
prescaler). The TCC will stop running when Sleep mode occurs.
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep on running
even after the oscillator driver has been turned off (i.e., in Sleep mode). During Normal
operation or Sleep mode, a WDT time-out (if enabled) will cause the device to reset. The
WDT can be enabled or disabled any time during Normal mode by software programming
(see WDTE bit of WDTCR (Section 6.1.28Bank 0 R21) register). With no prescaler, the
WDT time-out period is approximately 18 ms1 (one oscillator start-up timer period).
Data Bus
8 Bit Counter
TCC(R23)
8 to 1 MUX
Prescaler
TCC overflow
interrupt
TPSR2~TPSR0
(R22)
WDT
8 Bit Counter
8 to 1 MUX
Prescaler
WDTE(R21)
WDT time out
WPSR2~ WPSR0
(R21)
Figure 6-3 TCC and WDT Block Diagram
1 VDD=5V, WDT time-out period = 16.5ms ± 8%.
VDD=3V, WDT time-out period = 18ms ± 8%.
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eKTF5616/08
8-Bit Microcontroller
6.3 I/O Ports
The I/O registers, Port 5~Port 8 are bidirectional tri-state I/O ports. All can be pulled high
and pulled low internally by software. Furthermore, they can also be set as open-drain
output and high sink/drive by software. Ports 5~8 features wake-up and interrupt function
as well as input status change interrupt function. Each I/O pin can be defined as "input" or
"output" pin by the I/O control register (IOC5 ~ IOC8).
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5 ~ Port 8 are shown in the following Figures 6-4a to 6-4d.
PCRD
P
Q
D
R
PCWR
CLK
_
Q
C
L
P
R
IOD
PORT
Q
D
CLK
PDWR
_
Q
C
L
PDRD
0
1
M
U
X
Note: Pull-down is not shown in the figure.
Figure 6-4a I/O Port and I/O Control Register for Port 5~8 Circuit Diagram
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eKTF5616/08
8-Bit Microcontroller
PCRD
P
Q
D
R
_
Q
PCWR
PDWR
CLK
C
L
INT
IOD
P
R
Q
PORT
D
_
Q
CLK
C
L
0
1
P
R
D
Q
M
U
X
_
Q
CLK
C
L
T10
PDRD
P
R
D
Q
CLK
_
Q
C
L
INT
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-4b I/O Port and I/O Control Register for /INT Circuit
PCRD
P
Q
_
Q
D
D
R
CLK
PCWR
PDWR
C
L
P61~P67
PORT
IOD
P
R
Q
_
Q
CLK
C
L
0
1
M
U
X
TIN
PDRD
P
R
D
Q
CLK
_
Q
C
L
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-4c I/O Port and I/O Control Register for Ports 5~8 Circuit
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eKTF5616/08
8-Bit Microcontroller
IOCE.1
P
Q
D
R
CLK
Interrupt
_
Q
C
L
RE.
1
ENI Instruction
P
R
T10
T11
D
Q
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
C
L
T17
DISI Instruction
Interrupt
(Wake-up from SLEEP)
/SLEP
Next Instruction
(Wake-up from SLEEP)
Figure 6-4d I/O Port 5~8 with Input Change Interrupt/Wake-up Block Diagram
6.3.1 Usage of Ports 5~8 Input Change Wake-up/Interrupt Function
1. Wake-up
a) Before Sleep:
1) Disable WDT
2) Read I/O Port (MOV R6,R6)
3) Execute "ENI" or "DISI"
4) Enable Wake-up bit (Set ICWKPx = 1)
5) Execute "SLEP" instruction
b) After Wake-up:
Next instruction
2. Wake-up and Interrupt
a) Before SLEEP
1) Disable WDT
2) Read I/O Port (MOV R6,R6)
3) Execute "ENI" or "DISI"
4) Enable Wake-up bit (Set ICWKPx = 1)
5) Enable interrupt (Set PxICIE = 1)
6 Execute "SLEP" instruction
b) After Wake-up
1) IF "ENI" Interrupt vector (0006H)
2) IF "DISI" Next instruction
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8-Bit Microcontroller
6.4 Reset and Wake-up
A Reset is initiated by one of the following events:
1) Power-on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
4) LVR (if enabled)
The device is kept in a Reset condition for a period of approximately 18ms2 (one oscillator
start-up timer period) after a reset is detected. If the /Reset pin goes “low” or the WDT
time-out is active, a reset is generated. In IRC mode, the reset time is 8-/32 clocks. Once
a Reset occurs, the following functions are performed (see Figure 6-5 below):
The oscillator is continuously running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog Timer and prescaler are cleared.
The control register bits are set as shown in the table below under Section 6.4.3,
Summary of Register Initial Values after Reset.
The Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering Sleep mode, WDT (if enabled) is cleared but keeps on running. Wake-up is then
generated (in IRC mode the wake-up time is 8-/32 clocks). The controller can be
awakened by any of the following events:
1) External reset input on /RESET pin
2) WDT time-out (if enabled)
3) External (/INT) pin changes (if INTWE is enabled)
4) Port input status changes (if ICWKPx is enabled)
5) SPI receives data while it serves as Slave device (if SPIWK is enabled)
6) I2C receives data while it serves as Slave device (if I2CWK is enabled)
7) Low Voltage Detector (if LVDWK is enabled)
8) A/D conversion completed (if ADWK is enabled)
The first two events (1 and 2) will cause the eKTF5616/08 to reset. The T and P flags of R3
are used to determine the source of the reset (Wake-up). Events 3 to 7 are considered as
continuation of program execution and the global interrupt ("ENI" or "DISI" being executed)
decides whether or not the controller branches to the interrupt vector following a wake-up.
If ENI is executed before SLEP, the instruction will begin to execute from Address
0x02~0x40 after wake-up. If DISI is executed before SLEP, the execution will restart from
the instruction right next to SLEP after wake-up.
2 Vdd = 5V, set up time period = 16.5ms ± 8%
Vdd = 3V, set up time period = 16.5ms ± 8%
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eKTF5616/08
8-Bit Microcontroller
Only one event (from Events 3 to 6) can be enabled before entering into Sleep mode. That
is:
a) If WDT is enabled before SLEP, the eKTF5616/08 can wake up only when Events 1 or
2 occurs. Refer to Section 6.5 Interrupt for further details.
b) If External (/INT) pin change is used to wake up the eKTF5616/08 and the EXWE bit is
enabled before SLEP (with WDT disabled), the eKTF5616/08 can only wake up when
Event 3 occurs.
c) If Port Input Status Change is used to wake-up the eKTF5616/08 and the
corresponding wake-up setting is enabled before SLEP (with WDT disabled), the
eKTF5616/08 will wake up only when Event 4 occurs.
d) With SPI serves as Slave device and the SPIWK bit of Bank0 R11 register is enabled
before SLEP (with WDT disabled), the SPI will wake up the eKTF5616/08 after it
receives data. Hence, the eKTF5616/08 can wake up only when Event 5 occurs.
e) When I2C is serving as Slave device and I2CWK bit of Bank 0 R11 register is enabled
before SLEP (with WDT disabled), the I2C will wake up the eKTF5616/08 after it
receives data. Hence, the eKTF5616/08 can only be woken up by Event 6.
f) If Low voltage detector is used to wake up the eKTF5616/08 and the LVDWK bit of
Bank 0 R10 register is enabled before SLEP, WDT must be disabled by software.
Hence, the eKTF5616/08 can only be woken up by Event 7.
g) If AD conversion completed is used to wake up the eKTF5616/08 and the ADWK bit
of Bank 0 R10 register is enabled before SLEP, WDT must be disabled by software.
Hence, the eKTF5616/08 can only be woken up by Event 8.
6.4.1 Summary of Wake-up and Interrupt Mode Operation
Sleep Mode
Idle Mode
DISI ENI
Green Mode
Normal Mode
Wake-up
Signal
Condition
Signal
DISI
ENI
DISI
ENI
DISI
ENI
INTWK = 0,
EXIE = 0
/INT pin Disable
Interrupt
+
Interrupt
+
INTWK = 0,
EXIE = 1
Next
Next
Wake-up is invalid.
Instruction Interrupt Instruction Interrupt
Vector
Vector
External INT
INTWK = 1,
EXIE = 0
/INT pin Disable
Wake up
Wake up
+
Next
Wake up
+
Interrupt
Vector
Wake up
+
Next
Interrupt
+
Interrupt
+
INTWK = 1,
EXIE = 1
+
Next
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Instruction
Vector
Vector
Vector
TCIE = 0
TCIE = 1
Wake-up is invalid.
Interrupt is invalid.
Wake up
+
Wake up
+
Interrupt
Interrupt
+
TCC INT
Next
+
Next
Wake-up is invalid.
Wake-up is invalid
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
Wake-up is Interrupt is
TC1IE = 0
TC1IE = 1
Interrupt is invalid
TC1 Interrupt
(Used as
timer)
invalid.
invalid
Next
Instructio
Wake up
+
Wake up
+
Next
Instruction
Interrupt
+
Interrupt
+
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eKTF5616/08
8-Bit Microcontroller
Sleep Mode
Idle Mode
Green Mode
Normal Mode
Wake-up
Signal
Condition
Signal
DISI
ENI
DISI
ENI
DISI
ENI
DISI
ENI
Next
Instruction
Interrupt
Vector
Interrupt
Vector
n
Interrupt
Vector
TC1IE = 0
TC1IE = 1
Wake-up is invalid
Interrupt is invalid.
Interrupt
TC1 Interrupt
(Used as
counter)
Wake up
+
Next
Wake up Wake up
Wake up
+
Interrupt
+
+
+
Next
+
Next
Interrupt
Vector
Next
Instruction
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
PWMxPIE = 0
PWMxPIE = 1
Wake-up is invalid.
Interrupt is invalid.
PWMA/B
(When
TimerA/B
Match PRD or
DT)
Wake up
+
Wake up
+
Interrupt
Interrupt
+
Next
+
Next
Wake-up is invalid.
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
WKPxH/L = 0,
PxICIE = 0
Wake-up is invalid.
Wake-up is invalid.
Interrupt is invalid.
Interrupt
Interrupt
+
WKPxH/L = 0,
PxICIE = 1
Next
+
Next
Instruction Interrupt Instruction Interrupt
Vector
Vector
Pin Change
INT
Wake up
+
Next Instruction
WKPxH/L = 1,
PxICIE = 0
Interrupt is invalid.
Interrupt
Wake up
+
Next
Wake up
+
Wake up
+
Wake up
+
Interrupt
+
WKPxH/L = 1,
PxICIE = 1
Next
+
Next
Interrupt
Vector
Next
Instruction
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
LVDWK = 0,
LVDIE = 0
Wake-up is invalid.
Interrupt is invalid.
Interrupt
Interrupt
+
LVDWK = 0,
LVDIE = 1
Next
+
Next
Wake-up is invalid.
Instruction Interrupt Instruction Interrupt
Vector
Vector
Low Voltage
Detector
Wake up
Wake up
LVDWK = 1,
LVDIE = 0
+
+
Interrupt is invalid.
Next Instruction
Next Instruction
Wake up
Wake up
Wake up
Wake up
Interrupt
Interrupt
+
LVDWK = 1,
LVDIE = 1
+
+
+
+
Next
+
Next
Next
Instruction
Interrupt
Vector
Next
Instruction
Interrupt Instruction Interrupt Instruction Interrupt
Vector
Vector
Vector
Interrupt is invalid.
Interrupt
I2CWK = 0,
I2CxIE = 0
I2C
Wake-up is invalid.
Can’t use
I2CWK = 0,
I2CxIE = 1
I2C
Can’t use
Next
+
Wake-up is invalid.
Instruction Interrupt
Vector
I2C
(Slave mode)
Wake up
+
Next Instruction
I2C must be slave mode
I2CWK = 1,
I2CxIE = 0
I2C
Can’t use
Interrupt is invalid.
Wake up
+
Next
Wake up
+
Interrupt
Vector
Wake up
+
Next
Wake up
+
Interrupt
Vector
Interrupt
I2CWK = 1,
I2CxIE = 1
I2C
Can’t use
Next
+
Instruction Interrupt
Vector
Instruction
Instruction
SPI
(Slave mode)
SPIWK = 0,
SPIE = 0
Wake-up is invalid.
Interrupt is invalid.
76
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Sleep Mode
Idle Mode
Green Mode
Normal Mode
Wake-up
Signal
Condition
Signal
DISI
ENI
DISI
ENI
DISI
ENI
DISI
ENI
Interrupt
+
Interrupt
+
SPIWK = 0,
SPIE = 1
Next
Next
Wake-up is invalid.
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake up
+
Next Instruction
SPIWK = 1,
SPIE = 0
Interrupt is invalid.
Interrupt
Wake up
+
Next
Wake up
+
Wake up
+
Wake up
+
Interrupt
+
SPIWK = 1,
SPIE = 1
Next
+
Next
Interrupt
Vector
Next
Instruction
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Interrupt is invalid.
Interrupt
Vector
Interrupt is invalid.
Interrupt
UTIE = 0
UART
Transmit
complete
Interrupt
Wake-up is invalid.
Wake-up is invalid.
Next
+
Next
+
UTIE = 1
URIE = 0
URIE = 1
UTIE = 0
UTIE = 1
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid.
Interrupt
Vector
Interrupt is invalid.
Interrupt
UART
Receive data
Buffer full
Interrupt
Wake-up is invalid.
Wake-up is invalid
Wake-up is invalid.
Wake-up is invalid
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid.
Interrupt
Vector
Interrupt is invalid.
Interrupt
UART
Receive Error
Interrupt
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Vector
ADWK = 0,
ADIE = 0
wake-up is invalid.
Interrupt is invalid.
Interrupt
Interrupt
+
ADWK = 0,
ADIE = 1
Next
+
Next
wake-up is invalid.
Instruction Interrupt Instruction Interrupt
Vector
Vector
Wake up
+
Next Instruction
Fs and Fm don’t stop
ADWK = 1,
ADIE = 0
AD INT
Interrupt is invalid.
Wake up
+
Next
Interrupt
Interrupt
+
ADWK = 1,
ADIE = 1
Next
Next
Next
Next
+
Next
Instruction Instruction Instruction Instruction Instruction Interrupt Instruction Interrupt
Fs and Fm
Vector
Vector
don’t stop
RESET
RESET
RESET
RESET
RESET
WDT time out
RESET
RESET
RESET
NOTE
After wake up:
1. If interrupt enables interrupt + next instruction
2. If interrupt disables next instruction
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
77
eKTF5616/08
8-Bit Microcontroller
6.4.2 The Status of RST, T, and P of the Status Register
A reset condition is initiated by one of the following events:
1) Power-on condition
2) High-low-high pulse on the /RESET pin
3) Watchdog timer time-out
4) When LVR occurs
The values of T and P, as listed in the following table are used to check how the MCU
wakes up. The next table shows the events that may affect the status of T and P.
Values of RST, T and P after Reset:
Reset Type
T
P
Power-on
1
1
P
/RESET during Operation mode
P
/RESET Wake-up during Sleep mode
WDT during Operation mode
1
0
0
1
0
P
WDT Wake-up during Sleep mode
Wake up on pin change during Sleep mode
0
0
P: Previous status before reset
Status of T and P being affected by Events:
Event
T
P
Power-on
1
1
0
1
1
1
1
WDTC instruction
WDT time-out
P
0
SLEP instruction
Wake up on pin change during Sleep mode
0
P: Previous value before reset
78
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
VDD
D
CLK
Q
CLK
Oscillator
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT Timeout
Setup Time
RESET
WDT
/RESET
Figure 6-5 Block Diagram of Controller Reset
6.4.3 Summary of Register Initial Values after Reset
Legend: U: Unknown or don’t care
C: Same with Code option
P: Previous value before reset
t: Check tables under Section 6.4.2
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Power-On
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
R0
0x00
/RESET and WDT
Wake-up from
Sleep/Idle
(IAR)
P
P
P
P
P
P
P
P
Bit Name
-
-
SBS1
SBS0
-
-
GBS1
GBS0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1
0x01
/RESET and WDT
Wake-up from
Sleep/Idle
(BSR)
0
0
P
P
0
0
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R2
0x02
/RESET and WDT
Wake-up from
Sleep/Idle
(PCL)
P
P
P
P
P
P
P
P
Bit Name
INT
0
N
U
P
OV
U
T
1
t
P
1
t
Z
U
P
DC
U
C
U
P
Power-On
R3
0x03
(SR)
/RESET and WDT
Wake-up from
Sleep/Idle
0
P
P
P
P
P
t
t
P
P
P
Bit Name
RSR7
RSR6
RSR5
RSR4
RSR3
RSR2
RSR1
RSR0
Power-On
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
R4
0x04
/RESET and WDT
Wake-up from
Sleep/Idle
(RSR)
P
P
P
P
P
P
P
P
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
79
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
Bit Name
Power-On
Bit 7
-
0
0
Bit 6
-
0
0
Bit 5
P55
0
Bit 4
P54
0
Bit 3
P53
0
Bit 2
P52
0
Bit 1
P51
0
Bit 0
P50
0
Bank 0, R5
0X05
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
(Port 5)
0
0
P
P
P
P
P
P
Bit Name
Power-On
P67
0
P66
0
P65
0
P64
0
P63
0
P62
0
P61
0
P60
0
Bank 0, R6
0x06
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
(Port 6)
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
-
0
0
-
0
0
-
0
0
-
0
0
P73
0
0
P72
0
0
P71
0
0
P70
0
0
Bank 0, R7
0x07
(Port 7)
0
0
0
0
P
P
P
P
Bit Name
Power-On
P87
0
P86
0
P85
0
P84
0
P83
0
P82
0
P81
0
P80
0
Bank 0, R8
0x08
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
(Port 8)
P
P
P
P
P
P
P
P
Bit Name
-
-
IOC55
IOC54
IOC53
IOC52
IOC51
IOC50
Power-On
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 0, RB
0X0B
/RESET and WDT
Wake-up from
Sleep/Idle
(IOCR5)
0
0
P
P
P
P
P
P
Bit Name
IOC67
IOC66
IOC65
IOC64
IOC63
IOC62
IOC61
IOC60
Power-On
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 0, RC
0x0C
/RESET and WDT
Wake-up from
Sleep/Idle
(IOCR6)
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
IOC73
IOC72
IOC71
IOC70
Power-On
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bank 0, RD
0X0D
/RESET and WDT
Wake-up from
Sleep/Idle
(IOCR7)
0
0
0
0
-
P
P
-
P
P
Bit Name
CPUS
Code
IDLE
PERCS
FMSF
RCM1
Code
RCM0
Code
Power-On
option
(HLFS)
Code
1
0
0
1
0
option
(RCM1) (RCM0)
option
Bank 0, RE
0x0E
(OMCR)
/RESET and WDT
option
(HLFS)
1
0
0
0
1
0
0
P
P
Wake-up from
Sleep/Idle
P
P
P
P
P
P
Bit Name
-
-
-
-
EIES1
EIES0
-
-
Power-On
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
Bank 0, RF
0X0F
/RESET and WDT
Wake-up from
Sleep/Idle
EIESCR
0
0
0
0
P
P
0
0
Bit Name
-
-
LVDWK
ADWK INTWK1 INTWK0
-
-
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R10
0x10
/RESET and WDT
Wake-up from
Sleep/Idle
(WUCR1)
0
0
P
P
P
P
0
0
80
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
Bit Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
SPIWK I2CWK
Bit 2
Bit 1
-
Bit 0
-
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R11
0x11
/RESET and WDT
Wake-Up from
Sleep/Idle
WUCR2
0
0
0
0
P
P
0
0
Bit Name
ICWKP8 ICWKP7 ICWKP6 ICWKP5
-
-
-
-
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R12
0x12
/RESET and WDT
Wake-up from
Sleep/Idle
WUCR3
P
P
P
P
0
0
0
0
-
-
-
LVDSF
ADSF
EXSF1 EXSF0
-
TCSF
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R14
0X14
/RESET and WDT
Wake-up from
Sleep/Idle
SFR1
0
0
P
P
P
P
0
P
-
-
-
UERRSF URSF
UTSF
-
-
TC1SF
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R15
0X15
SFR2
0
-
0
-
P
P
P
0
0
P
PWMBP PWMBD PWMAP PWMAD
SF
Bit Name
-
-
SF
SF
SF
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R16
0X16
SFR3
0
0
0
0
P
P
P
P
I2CSTPS
Bit Name
P8ICSF P7ICSF P6ICSF P5ICSF SPISF
I2CRSF I2CTSF
F
0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R17
0X17
SFR4
P
P
P
P
P
P
P
P
TKTOS
F
Bit Name
SHSF
-
-
TKCSF TKPESF TKOESF TKSF
Bank 0, R19
0X19
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SFR6
P
0
0
P
P
P
P
P
Bit Name
-
-
LVDIE
ADIE
EXIE1
EXIE0
-
TCIE
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R1B
0X1B
IMR1
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
P
P
P
P
0
P
Bit Name
-
-
UERRIE
URIE
UTIE
-
-
TC1IE
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R1C
0X1C
IMR2
0
-
0
-
P
-
P
-
P
0
0
P
PWMBPI PWMBDI PWMAPI PWMADI
Bit Name
E
0
0
E
0
0
E
0
0
E
0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
BANK 0, R1D
0X1D
IMR3
0
0
0
0
P
P
P
P
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
81
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2CSTPI
E
P8ICIE P7ICIE
P6ICIE
P5ICIE
SPIIE
I2CRIE I2CTIE
Bank 0, R1E
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0X1E
IMR4
P
P
P
P
P
P
P
P
TKERRI
E
Bit Name
SHIE
-
-
-
TKCIE
-
TKIE
Bank 0, R20
0X20
IMR6
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
0
0
0
P
0
P
P
Bit Name
WDTE
FSSF
-
-
PSWE WPSR2 WPSR1 WPSR0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R21
0X21
/RESET and WDT
Wake-up from
Sleep/Idle
WDTCR
P
P
0
0
P
P
P
P
Bit Name
-
TCCS
-
-
PSTE
TPSR2 TPSR1 TPSR0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R22
0X22
/RESET and WDT
Wake-up from
Sleep/Idle
TCCCR
0
P
P
P
P
P
P
P
Bit Name
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R23
0X23
/RESET and WDT
Wake-up from
Sleep/Idle
TCCD
P
P
P
P
P
P
P
P
Bit Name
TC1S TC1RC TC1SS1
-
TC1FF TC1MOS TC1IS1 TC1IS0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R24
0X24
TC1CR1
P
P
P
0
P
P
P
P
Bit Name
TC1M2 TC1M1 TC1M0 TC1SS0 TC1CK3 TC1CK2 TC1CK1 TC1CK0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R25
0X25
TC1CR2
P
P
P
P
P
P
P
P
Bit Name
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R26
0X26
TC1DA
P
P
P
P
P
P
P
P
Bit Name
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R27
0X27
TC1DB
P
P
P
P
P
P
P
P
Strobe/P
end
SAR_EM
PTY
Bit Name
IMS
ISS
STOP
ACK
FULL
EMPTY
Bank 0, R30
0X30
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
I2CCR1
P
P
P
P
P
-
P
P
P
Bit Name
I2CBF
GCEN
I2COPT
Code
option
(I2COPT)
P
BBF
I2CTS1 I2CTS0 I2CEN
Bank 0, R31
0X31
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
1
1
I2CCR2
/RESET and WDT
82
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
Wake-up from
Sleep/Idle
Bit 7
P
Bit 6
P
Bit 5
P
Bit 4
P
Bit 3
0
Bit 2
P
Bit 1
P
Bit 0
P
Bit Name
Power-On
SA6
0
SA5
0
SA4
0
SA3
0
SA2
0
SA1
0
SA0
0
IRW
0
Bank 0, R32
0X32
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
I2CSA
P
P
P
P
P
P
P
P
Bit Name
Power-On
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
0
Bank 0, R33
0X33
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
I2CDB
P
P
P
P
P
P
P
P
Bit Name
Power-On
DA7
1
DA6
1
DA5
1
DA4
1
DA3
1
DA2
1
DA1
1
DA0
1
Bank 0, R34
0X34
/RESET and WDT
Wake-up from
Sleep/Idle
1
1
1
1
1
1
1
1
I2CDAL
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
DA9
1
1
DA8
1
1
Bank 0, R35
0X35
I2CDAH
0
0
0
0
0
0
P
P
Bit Name
CES
SPIE
SRO
SSE
SDOC
SBRS2 SBRS1 SBRS0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R36
SPICR
0X36
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
DORD
0
0
TD1
0
0
TD0
0
0
-
0
0
OD3
0
0
OD4
0
0
-
0
0
RBF
0
0
Bank 0, R37
0X37
SPIS
P
P
P
0
P
P
0
P
Bit Name
Power-On
SRB7
U*
SRB6
U*
SRB5
U*
SRB4
U*
SRB3
U*
SRB2
U*
SRB1
U*
SRB0
U*
Bank 0, R38
0X38
SPIR
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Bit Name
Power-On
SWB7
U*
SWB6
U*
SWB5
U*
SWB4
U*
SWB3
U*
SWB2
U*
SWB1
U*
SWB0
U*
BANK 0, R39
0X39
SPIW
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Bit Name
CKR2
CKR1
CKR0
ADRUN
ADP
ADOM
SHS1
SHS0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BANK 0, R3E
0X3E
/RESET and WDT
Wake-up from
Sleep/Idle
ADCR1
P
P
P
P
P
P
P
P
Bit Name
-
VPIS2
ADIM
ADCMS VPIS1
VPIS0
VREFP
-
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BANK 0, R3F
0X3F
/RESET and WDT
Wake-up from
Sleep/Idle
ADCR2
0
P
P
P
P
P
P
0
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
83
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
BANK 0,
Reset Type
Bit Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
Bit 2
Bit 1
Bit 0
ADIS3
ADIS2
ADIS1
ADIS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0X40
0X41
0X43
0X44
0X45
0X46
R40
ADISR
0
0
0
0
P
P
P
P
ADE4
ADE3
ADE2
ADE1
ADE0
Bit Name
ADE7
ADE6
ADE5
BANK 0,
R41
ADER1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
ADD2
ADD1
ADD0
Bit Name
ADD7
ADD6
ADD5
ADD4
ADD3
BANK 0,
R43
ADDL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
ADD10
ADD9
ADD8
Bit Name
ADD11
ADD7
ADD6
ADD5
ADD4
BANK 0,
R44
ADDH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
ADCD2 ADCD1 ADCD0
Bit Name
ADCD7 ADCD6 ADCD5 ADCD4 ADCD3
BANK 0,
R45
ADCVL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
-
Bit Name
-
ADCD11 ADCD10 ADCD9 ADCD8
BANK 0,
R46
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
ADCVH
0
0
0
0
P
P
P
P
IOC87
IOC86
IOC85
IOC84
IOC83
IOC82
IOC81
IOC80
Bit Name
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Power-On
Bank 1, R5
IOCR8
0X05
0X08
0X09
0X0A
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-Up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
PH55
1
1
PH54
1
1
PH53
1
1
PH52
1
1
PH51
1
1
PH50
1
1
0
0
0
0
Bank 1, R8
P5PHCR
0
0
P
P
P
P
P
P
PH67
1
1
PH66
1
1
PH65
1
1
PH64
1
1
PH63
1
1
PH62
1
1
PH61
1
1
PH60
1
1
Bank 1, R9
P6PHCR
P
P
P
P
P
P
P
P
-
-
-
-
P8HPH P8LPH
-
0
0
P7LPH
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Bank 1, RA
P78PHCR
0
0
0
0
P
P
0
P
84
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
Bit Name
Power-On
Bit 7
-
Bit 6
-
Bit 5
PL55
1
Bit 4
PL54
1
Bit 3
PL53
1
Bit 2
PL52
1
Bit 1
PL51
1
Bit 0
PL50
1
0
0
0
0
Bank 1, RB
0X0B
1
1
1
1
1
1
/RESET and WDT
Wake-up from
Sleep/Idle
P5PLCR
0
0
P
P
P
P
P
P
PL67
PL66
PL65
PL64
PL63
PL62
PL61
PL60
Bit Name
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Power-On
Bank 1, RC
0X0C
/RESET and WDT
Wake-up from
Sleep/Idle
P6PLCR
P
P
P
P
P
P
P
P
-
-
-
-
P8HPL
P8LPL
-
P7LPL
Bit Name
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
Power-On
Bank 1, RD
0X0D
/RESET and WDT
Wake-up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P78PLCR
0
0
0
0
P
P
0
P
-
-
H55
1
1
H54
1
1
H53
1
1
H52
1
1
H51
1
1
H50
1
1
0
0
0
0
Bank 1, RE
0X0E
P5HDSCR
0
0
P
P
P
P
P
P
H67
1
1
H66
1
1
H65
1
1
H64
1
1
H63
1
1
H62
1
1
H61
1
1
H60
1
1
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bank 1, RF
0X0F
P6HDSCR
P
P
P
P
P
P
P
P
-
-
-
-
P8HHDS P8LHDS
-
P7LHDS
Bit Name
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
Power-On
Bank 1, R10
0X10
/RESET and WDT
Wake-up from
Sleep/Idle
P78HDSCR
0
0
0
0
P
P
0
P
-
-
OD55
OD54
OD53
OD52
OD51
OD50
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
Bank 1, R11
0X11
/RESET and WDT
Wake-up from
Sleep/Idle
P5ODCR
0
0
P
P
P
P
P
P
OD67
OD66
OD65
OD64
OD63
OD62
OD61
OD60
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
Bank 1, R12
0X12
/RESET and WDT
Wake-up from
Sleep/Idle
P6ODCR
P
P
P
P
P
P
P
P
-
-
-
-
P8HOD P8LOD
-
P7LOD
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
Bank 1, R13
0X13
/RESET and WDT
Wake-up from
Sleep/Idle
P78ODCR
0
0
0
0
P
P
0
P
-
-
-
-
-
-
PWMBS PWMAS
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
Bank 1, R16
0X16
/RESET and WDT
Wake-up from
Sleep/Idle
PWMSCR
0
0
0
0
0
0
P
P
-
-
-
PWMAE
TAEN
TAP2
TAP1
TAP0
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
Bank 1, R17
0X17
/RESET and WDT
Wake-up from
Sleep/Idle
PWMACR
P
0
0
0
P
P
P
P
PRDA7 PRDA6 PRDA5 PRDA4 PRDA3 PRDA2 PRDA1 PRDA0
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
Bank 1, R18
0X18
/RESET and WDT
Wake-up from
Sleep/Idle
PRDAL
P
P
P
P
P
P
P
P
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
85
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
PRDA1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDA15
PRDA13 PRDA12 PRDA11 PRDA10 PRDA9 PRDA8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bank 1, R19
0X19
PRDAH
P
P
P
P
P
P
P
P
DTA7
DTA6
DTA5
DTA4
DTA3
DTA2
DTA1
DTA0
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
Bank 1, R1A
0X1A
DTAL
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
DTA15 DTA14
DTA13
DTA12 DTA11 DTA10
DTA9
DTA8
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
Bank 1, R1B
0X1B
/RESET and WDT
Wake-up from
Sleep/Idle
DTAH
P
P
P
P
P
P
P
P
TMRA7 TMRA6 TMRA5 TMRA4 TMRA3 TMRA2 TMRA1 TMRA0
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Power-On
Bank 1,
R1C
TMRAL
0X1C
0X1D
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
TMRA1
TMRA1
TMRA15
TMRA13
TMRA11 TMRA10 TMRA9 TMRA8
Bit Name
4
0
0
2
0
0
Bank 1,
R1D
TMRAH
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
-
-
-
PWMBE
TBEN
TBP2
TBP1
TBP0
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
BANK 1,
R1E
PWMBCR
0X1E
0X1F
/RESET and WDT
Wake-Up from
Sleep/Idle
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
P
0
0
0
P
P
P
P
PRDB7 PRDB6 PRDB5 PRDB4 PRDB3 PRDB2 PRDB1 PRDB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R1F
PRDBL
P
P
P
P
P
P
P
P
PRDB1
PRDB15
PRDB13 PRDB12 PRDB11 PRDB10 PRDB9 PRDB8
Bit Name
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
Bank 1, R20
PRDBH
0X20
P
P
P
P
P
P
P
P
86
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
Bit Name
Power-On
Bit 7
DTB7
0
Bit 6
DTB6
0
Bit 5
DTB5
0
Bit 4
DTB4
0
Bit 3
DTB3
0
Bit 2
DTB2
0
Bit 1
DTB1
0
Bit 0
DTB0
0
Bank 1, R21
0X21
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
DTBL
P
P
P
P
P
P
P
P
Bit Name
DTB15 DTB14
DTB13
DTB12 DTB11 DTB10
DTB9
DTB8
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R22
0X22
/RESET and WDT
Wake-up from
Sleep/Idle
DTBH
P
P
P
P
P
P
P
P
Bit Name
TMRB7 TMRB6 TMRB5 TMRB4 TMRB3 TMRB2 TMRB1 TMRB0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R23
0X23
/RESET and WDT
Wake-up from
Sleep/Idle
TMRBL
P
P
P
P
P
P
P
P
TMRB1
TMRB1
Bit Name
TMRB15
TMRB13
TMRB11 TMRB10 TMRB9 TMRB8
4
0
0
2
0
0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R24
0X24
TMRBH
P
P
P
P
P
P
P
P
UMODE
1
Bit Name
UINVEN
UMODE0 BRATE2 BRATE1 BRATE0 UTBF
TXE
Bank 1, R33
0X33
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
URCR
P
P
P
P
P
P
P
P
Bit Name
URTD8
EVEN
PRE
PRERR OVERR FMERR URBF
RXE
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R34
0X34
URS
P
P
P
P
P
P
P
P
Bit Name
URTD7 URTD6 URTD5 URTD4 URTD3 URTD2 URTD1 URTD0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R35
0X35
URTD
P
P
P
P
P
P
P
P
Bit Name
URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R36
0X36
URRDL
P
P
P
P
P
P
P
P
Bit Name
URRD8
-
-
-
-
-
-
URSS
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Bank 1, R37
0X37
URRDH
P
0
0
0
0
0
0
P
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
87
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
Bit Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
RD
Bit 0
WR
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R40
0X40
EECR1
0
0
0
0
0
0
P
P
Bit Name
-
-
-
-
-
EEWE
EEDF
EEPC
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R41
0X41
EECR2
P
P
P
0
0
0
0
0
Bit Name
-
EERA6 EERA5 EERA4 EERA3 EERA2 EERA1 EERA0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R42
0X42
EERA
0
P
P
P
P
P
P
P
Bit Name
EERD7 EERD6 EERD5 EERD4 EERD3 EERD2 EERD1 EERD0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R43
0X43
EERD
P
P
P
P
P
P
P
P
Bit Name
FLK[7]
FLK[6]
FLK[5]
FLK[4]
FLK[3]
FLK[2]
FLK[1]
FLK[0]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R44
0X44
FLKR
P
P
P
P
P
P
P
P
Bit Name
Power-On
TB7
0
TB6
0
TB5
0
TB4
0
TB3
0
TB2
0
TB1
0
TB0
0
Bank 1, R45
TBPTL
0X45
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bit Name
HLB
-
-
-
TB11
TB10
TB9
TB8
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R46
0X46
TBPTH
P
P
0
0
P
P
P
P
Bit Name
STOV
-
-
-
STL3
STL2
STL1
STL0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R47
0X47
/RESET and WDT
Wake-up from
Sleep/Idle
STKMON
P
0
0
0
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
-
0
0
-
0
0
-
0
0
-
0
0
PC11
0
0
PC10
0
0
PC9
0
0
PC8
0
0
Bank 1, R48
0X48
PCH
0
0
0
0
P
P
P
P
Bit Name
HLVDEN IRVSF
VDSB
VDM HLVDS3 HLVDS2 HLVDS1 HLVDS0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R49
0X49
HLVDCR
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
IAP
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R4D
0X4D
TBWCR
0
0
0
0
0
0
0
P
TBWA[4
Bit Name
Power-On
Bank 1, R4E
0X4E
TBWA[7] TBWA[6] TBWA[5]
TBWA[3] TBWA[2] TBWA[1] TBWA[0]
]
TBWAL
0
0
0
0
0
0
0
0
88
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
/RESET and WDT
Wake-up from
Sleep/Idle
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
P
-
P
-
P
-
P
-
P
P
P
P
TBWA[1 TBWA[1
Bit Name
TBWA[9] TBWA[8]
1]
0]
Bank 1, R4F
0X4F
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TBWAH
0
0
0
0
P
P
P
P
Bit Name
TKAEP7 TKAEP6 TKAEP5 TKAEP4 TKAEP3 TKAEP2 TKAEP1 TKAEP0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R5
0X05
/RESET and WDT
Wake-up from
Sleep/Idle
TKAPC
P
P
P
P
P
P
P
P
Bit Name
TKBEP7 TKBEP6 TKBEP5 TKBEP4 TKBEP3 TKBEP2 TKBEP1 TKBEP0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R6
0X06
/RESET and WDT
Wake-up from
Sleep/Idle
TKBPC
P
P
P
P
P
P
P
P
Bit Name
TKAEN
-
-
-
-
TKASW2 TKASW1 TKASW0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R7
0X07
/RESET and WDT
Wake-up from
Sleep/Idle
TKASCR
P
0
0
0
0
P
P
P
Bit Name
TKBEN
-
-
-
-
TKBSW2 TKBSW1 TKBSW0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R8
0X08
/RESET and WDT
Wake-up from
Sleep/Idle
TKBSCR
P
0
0
0
0
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
TKS
0
0
LDOEN TKPSB
-
0
0
-
0
0
-
0
0
-
0
0
GMC
0
0
1
1
0
0
Bank 2, RD
0X0D
TKCR
P
P
P
P
P
P
P
P
Bit Name
TCCY7 TCCY6 TCCY5 TCCY4 TCCY3 TCCY2 TCCY1 TCCY0
Power-On
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, RE
0X0E
/RESET and WDT
Wake-up from
Sleep/Idle
TKCCR
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
-
0
0
-
0
0
-
0
0
-
0
0
CS3
1
1
CS2
0
0
CS1
1
1
CS0
0
0
Bank 2, RF
0X0F
TKCSR
0
0
0
0
P
P
P
P
Bit Name
TCT7
TCT6
TCT5
TCT4
TCT3
TCT2
TCT1
TCT0
Power-On
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R10
0X10
/RESET and WDT
Wake-up from
Sleep/Idle
TKCTR
P
P
P
P
P
P
P
P
Bit Name
-
-
-
TSW4
TSW3
TSW2
TSW1
TSW0
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
Bank 2, R11
0X11
TKSWR
0
0
0
P
P
P
P
P
Bit Name
TKA[15] TKA[14] TKA[13] TKA[12] TKA[11] TKA[10] TKA[9] TKA[8]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R12
0X12
TKAH
P
P
P
P
P
P
P
P
Bit Name
TKA[7]
TKA[6]
TKA[5]
TKA[4] TKA[3]
TKA[2]
TKA[1] TKA[0]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R13
0X13
TKAL
P
P
P
P
P
P
P
P
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
89
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TKB[15] TKB[14] TKB[13] TKB[12] TKB[11] TKB[10] TKB[9] TKB[8]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R14
0X14
TKBH
P
P
P
P
P
P
P
P
Bit Name
TKB[7]
TKB[6]
TKB[5]
TKB[4] TKB[3]
TKB[2]
TKB[1] TKB[0]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R15
0X15
TKBL
P
P
P
P
P
P
P
P
Bit Name
TKMCS1 TKMCS0
-
-
TKISE
TKST2 TKST1 TKST0
Power-On
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R16
0X16
/RESET and WDT
Wake-up from
Sleep/Idle
TKSCR
P
P
0
0
P
P
P
P
TA1WB[1 TA1WB[1 TA1WB[1 TA1WB[ TA1WB[1 TA1WB[1 TA1WB[9 TA1WB[
Bit Name
5]
4]
3]
12]
1]
0]
]
8]
Power-On
/RESET and WDT
Wake-Up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R17
0X17
TKA1WBH
P
P
P
P
P
P
P
P
TA1WB[7 TA1WB[6
TA1WB[ TA1WB[3 TA1WB[2 TA1WB[1 TA1WB[
Bit Name
TA1WB[5]
]
]
4]
]
]
]
0]
Power-On
/RESET and WDT
Wake-Up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R18
0X18
TKA1WBL
P
P
P
P
P
P
P
P
TA1WR[7 TA1WR[
TA1WR[ TA1WR[3 TA1WR[2 TA1WR[1 TA1WR[
Bit Name
TA1WR[5]
]
6]
4]
]
]
]
0]
Power-On
/RESET and WDT
Wake-Up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R19
0X19
TKA1WR
P
P
P
P
P
P
P
P
TA2WB[1 TA2WB[1 TA2WB[1 TA2WB[ TA2WB[1 TA2WB[1 TA2WB[9 TA2WB[
Bit Name
5]
4]
3]
12]
1]
0]
]
8]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R1A
0X1A
TKA2WBH
P
P
P
P
P
P
P
P
TA2WB[7 TA2WB[6
TA2WB[ TA2WB[3 TA2WB[2 TA2WB[1 TA2WB[
Bit Name
TA2WB[5]
]
]
4]
]
]
]
0]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R1B
0X1B
TKA2WBL
P
P
P
P
P
P
P
P
TA2WR[7 TA2WR[
TA2WR[ TA2WR[3 TA2WR[2 TA2WR[1 TA2WR[
Bit Name
TA2WR[5]
]
6]
4]
]
]
]
0]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R1C
0X1C
TKA2WR
P
P
P
P
P
P
P
P
TB1WB[ TB1WB[ TB1WB[1 TB1WB[ TB1WB[1 TB1WB[ TB1WB[ TB1WB[
Bit Name
15]
14]
3]
12]
1]
10]
9]
8]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R1D
0X1D
TKB1WBH
P
P
P
P
P
P
P
P
TB1WB[ TB1WB[
TB1WB[ TB1WB[ TB1WB[ TB1WB[ TB1WB[
Bit Name
TB1WB[5]
7]
6]
4]
3]
2]
1]
0]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R1E
0X1E
TKB1WBL
P
P
P
P
P
P
P
P
TB1WR[ TB1WR[
TB1WR[ TB1WR[ TB1WR[ TB1WR[ TB1WR[
Bit Name
Power-On
TB1WR[5]
0
Bank 2, R1F
0X1F
7]
6]
4]
3]
2]
1]
0]
TKB1WR
0
0
0
0
0
0
0
90
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Address Bank Name
Reset Type
/RESET and WDT
Wake-up from
Sleep/Idle
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
P
P
P
P
P
P
P
P
TB2WB[ TB2WB[ TB2WB[1 TB2WB[ TB2WB[1 TB2WB[ TB2WB[ TB2WB[
Bit Name
15]
14]
3]
12]
1]
10]
9]
8]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R20
0X20
TKB2WBH
P
P
P
P
P
P
P
P
TB2WB[ TB2WB[
TB2WB[ TB2WB[ TB2WB[ TB2WB[ TB2WB[
Bit Name
TB2WB[5]
7]
6]
4]
3]
2]
1]
0]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R21
0X21
TKB2WBL
P
P
P
P
P
P
P
P
TB2WR[ TB2WR[
TB2WR[ TB2WR[ TB2WR[ TB2WR[ TB2WR[
Bit Name
TB2WR[5]
7]
6]
4]
3]
2]
1]
0]
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R22
0X22
TKB2WR
P
P
P
P
P
P
P
P
LOCKP LOCKPR LOCKPR LOCKPR LOCKPR
Bit Name
-
-
-
R4
3
2
1
0
Bank 2, R47
0X47
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LOCKPR
0
0
0
P
P
P
P
P
Bit Name
LOCKEN
-
-
-
-
-
-
-
Power-On
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 2, R48
0X48
LOCKCR
P
0
0
0
0
0
0
0
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
91
eKTF5616/08
8-Bit Microcontroller
6.5 Interrupt
The eKTF5616/08 has 21 interrupts (External, Internal) as listed below:
Interrupt Source
Enable Condition
Int. Flag
Int. Vector Priority
Internal /
Reset
-
-
0
High 0
External
External
External
Internal
INT
Pin change
TCC
ENI + EXIE=1
ENI +ICIE=1
ENI + TCIE=1
ENI+LVDEN &
LVDIE=1
EXSF
ICSF
TCSF
2
4
6
1
2
3
Internal
LVD
LVDSF
8
4
Internal
Internal
SPI
AD
ENI + SPIIE=1
SPISF
ADSF
C
5
6
ENI + ADIE=1
ENI + TC1IE=1
10
Internal
TC1
TC1SF
12
7
Internal
Internal
Internal
Internal
Internal
Internal
PWMPA
PWMDA
I2C Transmit
I2C Receive
I2CSTOP
PWMPB
ENI+PWMAPIE=1 PWMAPSF
ENI+PWMADIE=1 PWMADSF
14
16
1A
1C
1E
24
26
8
9
ENI+ I2CTIE
ENI+ I2CRIE
I2CTSF
I2CRSF
10
11
12
13
14
ENI+ I2CSTPIE
I2CSTPSF
ENI+PWMBPIE=1 PWMBPSF
ENI+PWMBDIE=1 PWMBDSF
PWMDB
Internal
Internal
Internal
UART Receive error ENI+UERRIE=1
UERRSF
URSF
2E
30
32
15
16
17
UART Receive
UART Transmit
ENI + URIE=1
ENI + UTIE=1
UTSF
Internal
Internal
System hold
Touch Key
ENI+SHIE=1
ENI+TKIE=1
SHSF
TKSF
3A
3C
18
19
TKPESF
TKOESF
TKCSF
TKTOSF
Internal
Internal
Touch Key error
ENI+TKERRIE=1
ENI+TKCIE=1
3E
40
20
21
Touch Key Idle with
scan
Bank 0 R14~R19 are the interrupt status registers that record the interrupt requests in the
relative flags/bits. Bank0 R1B~R20 are the interrupt Mask register. The global interrupt is
enabled by the ENI instruction and is disabled by the DISI instruction. When one of the
enabled interrupts occurs, the next instruction will be fetched from individual address. The
interrupt flag bit must be cleared by instructions before leaving the interrupt service routine
and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICSF bit which is set to “0”) in the Interrupt Status Register is set
regardless of the status of its mask bit or the execution of ENI. The RETI instruction ends
the interrupt routine and enables the global interrupt (the execution of ENI).
External interrupt is equipped with digital noise rejection circuit (input pulse of less than 4
System Clock Time is eliminated as noise). When an interrupt (Falling edge) is
generated by the External interrupt (if enabled), the next instruction will be fetched from
Address 002H.
Before the interrupt subroutine is executed, the contents of ACC and the R3 (Bit 0~Bit 6)
and R4 registers are saved by hardware. If another interrupt occurs, the ACC, R3
(Bit 0~Bit 4), and R4 will be replaced by the new interrupt. After the interrupt service
routine is completed, ACC, R3 (Bit 0~Bit 6), and R4 restore.
92
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Interrupt
Interrupt
sources
occurs
ACC
R1
STACKACC
ENI/ DISI
STACKR 1
STACKR 3
STACKR 4
R3(bit6~bit0)
R4
RETI
Figure 6-6a Interrupt Backup Diagram
VCC
P
D
Q
IRQn
R
/IRQn
CLK
INT
_
Q
IRQm
RFRD
C
L
RF
ENI/DISI
P
IOD
Q
D
R
CLK
_
Q
IOCFWR
C
L
IOCF
/RESET
IOCFRD
RFWR
Figure 6-6b Interrupt Input Circuit
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
93
eKTF5616/08
8-Bit Microcontroller
6.6 A/D Converter
R_BANK Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CKR2
CKR1
R/W
VPIS2
-
CKR0
R/W
ADIM
R/W
-
ADRUN
ADP
ADOM
R/W
SHS1
R/W
SHS0
R/W
-
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
0x3E
0x3F
0x40
0x41
0x43
0x44
0x45
0x46
0x10
0x14
0x1B
ADCR1
ADCR2
ADISR
ADER1
ADDL
R/W
R/W
R/W
-
ADCMS VPIS1
VPIS0
R/W
VREFP
R/W
-
R/W
-
R/W
ADIS3
R/W
ADE3
R/W
ADD3
R
-
-
-
-
ADIS2
R/W
ADIS1
R/W
ADIS0
R/W
ADE0
R/W
ADD0
R
-
-
-
ADE7
R/W
ADD7
R
ADE6
R/W
ADD6
R
ADE5
R/W
ADD5
R
ADE4
R/W
ADD4
R
ADE2
R/W
ADE1
R/W
ADD2
R
ADD1
R
ADD11 ADD10
ADD9
R
ADD8
R
ADD7
R
ADD6
R
ADD5
R
ADD4
R
ADDH
ADCVL
ADCVH
WUCR2
SFR1
R
R
ADCD7 ADCD6 ADCD5 ADCD4 ADCD3 ADCD2 ADCD1 ADCD0
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADCD11 ADCD10 ADCD9 ADCD8
-
R/W
R/W
R/W
R/W
ADWK
R/W
ADSF
R/W
ADIE
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IMR1
1/2 VDD
PowerDet.
AVDD / 4V / 3V / 2.5V / 2V
VREFP
AD7
ADC
Successive Approximatio)n
Power Down
(
Start to Convert
Fsub
Fmain/4
Fmain/8
Fmain/16
Fmain/32
Fmain/64
Fmain/128
8 to1
MUX
AD0
Fmain/256
3~0
7- 0
7
6
5
4
4
11 10 9 8 7 6 5 4 3 2 1 0
4
3
1
ADCR1
ADER1
ADIS
IMR1
ADDH
ADDL
ADCR1
ADCR2
ISFR1
DATA BUS
Figure 6-10 AD Converter Functional Block Diagram
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This is a 12-bit successive approximation register analog-to-digital converter (SAR ADC).
There are two reference voltages for SAR ADC. The positive reference voltage can select
internal AVDD, internal voltage sources or external input pin by setting the VREFP and
VPIS1~0 bits in ADCR2. Connecting to external positive reference voltage provides more
accuracy than using internal AVDD.
6.6.1 ADC Data Register
When the AD conversion is completed, the result is loaded to the ADDH and ADDL. And
the ADSF is set if ADIE is enabled.
6.6.2 A/D Sampling Time
The accuracy, linearity, and speed of the successive approximation AD converter are
dependent on the properties of the ADC. The source impedance and the internal sampling
impedance directly affect the time required to charge the sample and hold capacitor. The
application program controls the length of the sample time to meet the specified accuracy.
The maximum recommended impedance for the analog source is 10k at VDD = 5V. After
the analog input channel is selected; this acquisition time must be done before AD
conversion can be started.
6.6.3 A/D Conversion Time
CKR2~0 select the conversion time (TAD). This allows the MCU to run at maximum
frequency without sacrificing the accuracy of AD conversion. The following tables show
the relationship between TAD and the maximum operating frequencies. The TAD is 1µs for
3V~5.5V, TAD is 4µs for 2.5V~3V and TAD is 32µs for 2.2V~2.5V.
Max. System
Operation
Frequency in
2.2~2.5V
Max. System
Operation
Frequency in
2.5~3V
Max. System
Operation
Frequency in
3~5.5V
Clock
Rate
System
Mode
CKR2~0
000
001
010
011
100
101
110
111
FMain/4
FMain/8
-
-
-
-
-
8 MHz
16 MHz
16 MHz
16 MHz
16 MHz
16 MHz
Fs
FMain/16
FMain/32
FMain/64
FMain/128
FMain/256
FSub
-
-
-
8 MHz
12 MHz
16 MHz
16 MHz
Fs
Normal
Mode
-
-
8 MHz
Fs
Green
Mode
Fs
Fs
xxx
FSub
Fs
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6.6.4 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD
conversion remains operational during sleep mode. As the SLEP instruction is executed,
all MCU operations will stop except for the Oscillator, TCC, TC1, PWM and AD conversion.
The AD Conversion is considered completed as determined by:
1. The ADRUN bit of the Bank 0-R3E register is cleared to “0”.
2. The ADSF bit of the Bank 0-R14 register is set to “1”.
3. The ADWK bit of the Bank 0-R10 register is set to “1”. Wakes up from ADC
conversion (where it remains in operation during sleep mode).
4. Wake up and execution of the next instruction if the ADIE bit of the Bank 0-R1B
is enabled and the “DISI” instruction is executed.
5. Wake up and enter into Interrupt vector if the ADIE bit of Bank 0-R1B is enabled
and the “ENI” instruction is executed.
6. Enter into an Interrupt vector if the ADIE bit of the Bank 0-R1B is enabled and the
“ENI” instruction is executed.
The results are fed into the ADDL and ADDH registers when the conversion is completed.
If the ADWK is enabled, the device will wake up. Otherwise, the AD conversion will be shut
off, no matter what the status of the ADPD bit is.
6.6.5 Programming Process/Considerations
Follow these steps to obtain data from the ADC:
1. Write to the 8 bits (ADE7~0) on the Bank 0-R41(ADER1) register to define the
characteristics of P80~P87 (digital I/O, analog channels, or voltage reference
pin)
2. Write to the Bank 0-R3E~R41 register to configure the AD module:
a) Select the ADC input channel (ADIS4~0)
b) Define the AD conversion clock rate (CKR2~0)
c) Select the VREFS input source of the ADC
d) Set the ADP bit to “1” to begin sampling
3. Set the ADWK bit, if the wake-up function is employed
4. Set the ADIE bit, if the interrupt function is employed
5. Write “ENI” instruction, if the interrupt function is employed
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6. Set the ADRUN bit to “1”
7. Write “SLEP” instruction or Polling.
8. Wait for either Wake-up or for the ADRUN bit to be cleared to “0” , and the Status
flag (ADSF) is set “1”, or ADC interrupt occurs.
9. Read the ADDL and ADDH conversion data registers. If the ADC input channel
changes at this time, the ADDL and ADDH values can be cleared to “0”.
10. Clear the status flag (ADSF).
11. For next conversion, go to Step 1 or Step 2 as required. At least two TAD are
required before the next acquisition starts. On the other hand, the timing setting
ADRUN = 1 must be later than the timing setting ADPD=1, and the difference
between the two timings is also two TAD.
NOTE
In order to obtain accurate values, it is necessary to avoid any data transition on the I/O
pins during AD conversion
6.6.6 Programming Process for Detecting Internal VDD
VDD is detected within the operation, as described in the previous section, the difference is
that before starting the ADC conversion, the first detection of VDD is ready. Therefore in
Detecting VDD:
It should be noted that before starting the AD conversion operation, the channel has to be
switched to 1/2VDD channel, the voltage divider is started, then AD can be converted.
Several points to note is that, precise conversion values can be added in the VDD Pin
capacitance, or more than twice the conversion, taking the average or the last few strokes
data in order to increase the reliability of the data.
Note that usually before VDD is detected, do not switch the channel to 1/2VDD channel. As
it has always been a DC current consumption, it must be switched to another analog
multiplexer channel, and will be shut out of the resistor divider, which requires user’s
attention.
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6.7 Touch Key Sensor Function
The Touch Key Sensor provides multiple touch key sensing and calculating. The touch key
function is fully integrated and does not require external components, allowing touch key
functions to be implemented by the simple
6.7.1 Touch Key Function Block & Control Register
The Touch Key are pin shared with the P60~P67, P70~P73, P80~P83 I/O pins. Touch Key
are organized into two groups. Each group supports 8 detected pins.
Touch Key group
Sensing I/O pins
TK1
P60
TK2 TK3
P61 P62
TK4
P63
TK5
P64
TK6
P65
TK7
P66
TK8
P67
A
TK9 TK10 TK11 TK12 TK13 TK14 TK15 TK16
P70 P71 P72 P73 P80 P81 P82 P83
B
User can set the TKx Pin Control Register (TKAPC/TKBPC) to select this pin as Touch key
function or GP I/O pin.
TKxEP7~0
Pin function
0
1
GPIO or Other function
Touch Key Sensor
Touch Key frequency table:
Internal RC Frequency
Touch Key Frequency
24MHz
8MHz
12MHz
16MHz
24MHz
16MHz
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The following shows the touch key function block & control register
The Touch Key function Block:
LDOEN
LDO
TKPSB
TKxSCR
TKxPC
TKCCR
TKCSR
TKCTR
TKSF
TKOESF
TKPESF
Fsys
TKSWR
Key1
IO/TK
GMC
TKxH
TKxL
MUX
Gain
Sensing & Calculate
TKS
Data Counter
TKCSF
TKTOSF
TKIE
TKERRIE
Key8
IO/TK
Wake Up
Comparator
TKxWBH
TKxWBL
TKxWR
TKSCR
TKCIE
*X = A,B
Registers for Touch key circuit :
R_BANK
Bank 0
Address
Name
SFR6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
TKTOSF
TKCSF
TKPESF
TKOESF
TKSF
0x19
0x20
0x0D
0x0E
0x0F
0x10
0x11
0x16
-
-
R/W
R/W
R/W
R/W
R/W
-
-
-
TKC IE
-
TKERRIE
TKIE
Bank 0
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
IMR6
TKCR
-
-
-
R/W
-
R/W
R/W
TKS
LDOEN
TKPSB
-
-
-
-
GMC
R/W
R/W
R/W
-
-
-
-
R/W
TCCY7
TCCY6
TCCY5
TCCY4
TCCY3
TCCY2
TCCY1
TCCY0
TKCCR
TKCSR
TKCTR
TKSWR
TKSCR
R/W
R/W
R/W
R/W
R/W
CS3
R/W
CS2
R/W
CS1
R/W
CS0
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
TCT7
TCT6
TCT5
TCT4
TCT3
TCT2
TCT1
TCT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
TSW4
TSW3
TSW2
TSW1
TSW0
-
-
-
R/W
R/W
R/W
R/W
R/W
-
-
TKISE
TKST2
TKST1
TKST0
TKMCS1 TKMCS0
R/W R/W
-
-
R/W
R/W
R/W
R/W
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Registers for Touch key Group A :
R_BANK
Bank 2
Address
0x05
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TKAEP7
TKAEP6
TKAEP5
TKAEP4
TKAEP3
TKAEP2
TKAEP1
TKAEP0
TKAPC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TKAEN
-
-
-
-
TKASW2
TKASW1
TKASW0
Bank 2
Bank 2
Bank 2
0x07
0x12
0x13
TKASCR
TKAH
R/W
TKA[15]
R
-
TKA[14]
R
-
TKA[13]
R
-
TKA[12]
R
-
TKA[11]
R
R/W
TKA[10]
R
R/W
TKA[9]
R
R/W
TKA[8]
R
TKA[7]
R
TKA[6]
R
TKA[5]
R
TKA[4]
R
TKA[3]
R
TKA[2]
R
TKA[1]
R
TKA[0]
R
TKAL
TA1WB[15] TA1WB[14] TA1WB[13] TA1WB[12] TA1WB[11] TA1WB[10] TA1WB[9] TA1WB[8]
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
0x17
0x18
0x19
0x1A
0x1B
0x1C
TKA1WBH
TKA1WBL
TKA1WR
R/W
TA1WB[7] TA1WB[6] TA1WB[5] TA1WB[4] TA1WB[3] TA1WB[2] TA1WB[1] TA1WB[0]
R/W R/W R/W R/W R/W R/W R/W R/W
TA1WR[7] TA1WR[6] TA1WR[5] TA1WR[4] TA1WR[3] TA1WR[2] TA1WR[1] TA1WR[0]
R/W R/W R/W R/W R/W R/W R/W R/W
TA2WB[15] TA2WB[14] TA2WB[13] TA2WB[12] TA2WB[11] TA2WB[10] TA2WB[9] TA2WB[8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TKA2WBH
TKA2WBL
TKA2WR
R/W
TA2WB[7] TA2WB[6] TA2WB[5] TA2WB[4] TA2WB[3] TA2WB[2] TA2WB[1] TA2WB[0]
R/W R/W R/W R/W R/W R/W R/W R/W
TA2WR[7] TA2WR[6] TA2WR[5] TA2WR[4] TA2WR[3] TA2WR[2] TA2WR[1] TA2WR[0]
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Registers for Touch key Group B :
R_BANK
Bank 2
Address
0x06
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TKBEP7
TKBEP6
TKBEP5
TKBEP4
TKBEP3
TKBEP2
TKBEP1
TKBEP0
TKBPC
R/W
TKBEN
R/W
R/W
R/W
R/W
R/W
R/W
TKBSW2
R/W
R/W
TKBSW1
R/W
R/W
TKBSW0
R/W
-
-
-
-
-
-
-
-
Bank 2
Bank 2
0x08
0x14
TKBSCR
TKBH
TKB[15]
TKB[14]
TKB[13]
TKB[12]
TKB[11]
TKB[10]
TKB[9]
R
TKB[8]
R
R
TKB[7]
R
R
TKB[6]
R
R
TKB[5]
R
R
TKB[4]
R
R
TKB[3]
R
R
TKB[2]
R
TKB[1]
R
TKB[0]
R
Bank 2
0x15
TKBL
TB1WB[15] TB1WB[14] TB1WB[13] TB1WB[12] TB1WB[11] TB1WB[10] TB1WB[9] TB1WB[8]
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
0x1D
0x1E
0x1F
0x20
0x21
0x22
TKB1WBH
TKB1WBL
TKB1WR
R/W
TB1WB[7] TB1WB[6] TB1WB[5] TB1WB[4] TB1WB[3] TB1WB[2] TB1WB[1] TB1WB[0]
R/W R/W R/W R/W R/W R/W R/W R/W
TB1WR[7] TB1WR[6] TB1WR[5] TB1WR[4] TB1WR[3] TB1WR[2] TB1WR[1] TB1WR[0]
R/W R/W R/W R/W R/W R/W R/W R/W
TB2WB[15] TB2WB[14] TB2WB[13] TB2WB[12] TB2WB[11] TB2WB[10] TB2WB[9] TB2WB[8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TKB2WBH
TKB2WBL
TKB2WR
R/W
TB2WB[7] TB2WB[6] TB2WB[5] TB2WB[4] TB2WB[3] TB2WB[2] TB2WB[1] TB2WB[0]
R/W R/W R/W R/W R/W R/W R/W R/W
TB2WR[7] TB2WR[6] TB2WR[5] TB2WR[4] TB2WR[3] TB2WR[2] TB2WR[1] TB2WR[0]
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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6.7.2 Touch Key Operation
When a finger touches, the capacitance of the pad will increase. By using sensing and
calculate the capacitance variation to change to the counter data, user can set the sensed
control register to get apposite counter data. touch actions can be sensed by measuring
these counter data changes.
Each touch key group supports 8 detect pins. It senses pins by selecting TKx Select Pin
Register (TKxSCR). User select the Touch pin one by one, then set the Start bit (TKxEN) to
detect the capacitance.
TKxSW[2:0]
000
Sensing pin (TKA)
Sensing pin (TKB)
TK9
TK1
TK2
TK3
TK4
TK5
TK6
TK7
TK8
001
TK10
010
TK11
011
TK12
100
TK13
101
TK14
110
TK15
111
TK16
Each touch pin will sense (TKCCR+1)*2 periods. During each period, pin’s capacitance is
sensed and calculated. Accumulate multiple periods to get the counter data from register
(TKAH_TKAL) or (TKBH_TKBL).
TKS
TK1
TK2
TK3 ~ TK8
1 2 3
1
1 2 3
4
4
period (Cycle+1)*2
User can set the TKCTR register to control the Touch pin sensing frequency. If the TK scan
time is less than the touch sensing time, TK Error Interrupt will happen, and the Touch Key
Period Error status flag (TKPESF) will be set to 1.
Period time = TK initial time + TK scan time
= {[(TKCTR+1)*2+1] + [( TKCTR+1 ) * 16]} * 1/FTK
Note: The TKCTR must be greater than 0x35.
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period time
TK initial
TK Scan time
TK sensing
TK sensing
OK, TKSF=1
Fail, TKPESF=1
Control the TKCSR register to adjust touch key sensitivity. TKCSR =0x00 has a higher
sensitivity, whereas TKCSR= 0x0F has a lower sensitivity.
In some high noise environment or waterproof applications, user can adjust the TKSWR
register to control the sensing detect window. TKSWR =0x00 is a small sensing window
with less noise & sensing data. On the other hand, TKSWR =0x1F is a big sensing window
with greater noise & sensing data.
6.7.3 Touch Key Idle-Scan mode
This body support Idle-Scan touch key in IDLE mode. User can enable it by setting the
TKISE. In this mode, when the CPU enters into Idle mode, it will interval some time to scan
the touch key automatically. Also, touch and pins will be combined to scan together.
TKST[2:0]
000
Idle-Scan interval Time (mS)
12.5
25
001
010
50
011
100
200
400
800
1600
100
101
110
111
TKMC[1:0]
Group A combine pins
Group B combine pins
00
01
10
11
Not Combined, Only 1 Key with TKxSCR is selected
TK1~ TK8
TK1~Tk4
TK5~TK6
TK9~TK16
TK9~TK12
TK13~TK16
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Idle-Scan interval Time
Idle
Idle-Scan interval Time
scan
Key
scan
TK1~TK8 (TK9~TK16)
scan
TK1~TK8 (TK9~TK16)
TKCM =01
TKCM =1x
TKCM =00
1'st scan
TK1~TK4 (TK9~TK12)
2'nd scan
TK5~TK8 (TK13~TK16)
scan
TKn (TKASCR)
scan
TKn (TKASCR)
When the touch key scan data is greater than (TKxWBH_L + TKxWR) or less than
(TKxWBH_L – TKxWR), the IC will wake up and TKCIE Interrupt will happen (TKCSF=1).
TKMC=01
Group A
Group B
Wakeup Base data Wakeup Range data
TK1~TK8
TKA1WBH_L
TKB1WBH_L
TKA1WR
TKB1WR
TK9~TK16
TKMC=1x
Group A
Wakeup Base data Wakeup Range data
TK1~TK4
TK5~TK8
TKA1WBH_L
TKA2WBH_L
TKB1WBH_L
TKB2WBH_L
TKA1WR
TKA2WR
TKB1WR
TKB2WR
TK9~TK12
TK13~TK16
Group B
In Idle scan mode, if no wake-up happens after scanning key for 16 times, it will
automatically wake up one time and the TKTOSF=1. User can run the normal touch key
scan to check the Touch level or go to Idle again.
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6.8 Dual Set of PWM (Pulse Width Modulation)
6.8.1 Overview
In PWM mode, PWMA~B produce up to 16-bit resolution PWM outputs (see functional
block diagram below). A PWM output consists of a time period and a duty cycle, and it
keeps the output high. The PWM baud rate is the inverse of the time period. Figure 6-7b
PWM Output Timing below depicts the relationships between a time period and a duty
cycle.
Data
Bus
DTH+DTL
Writing DTL
TXP2 TXP1 TXP0
Duty
Fosc
1:1
1:2
1:4
TMRX
prescaler
1:8
MUX
1:16
1:64
1:128
1:256
To
PWMXDIF
Comparator
TMRX
prescaler TXEN
PWMXE
PWMXA
MUX
1
0
PWMX
R
S
Q
Q
TMRXH+TMRXL
Period match
Reset
Comparator
Period
To
PWMXPIF
Writing PRDL
PRDH+
PRDL
Data
Bus
Figure 6-7a Dual PWMs Functional Block Diagram
Period
Duty
Cycle
PRDA = TMRA
DTA = TMRA
Figure 6-7b PWM Output Timing
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6.8.2 Control Register
Addres
R_BANK
Bank 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
PWMBPSF PWMBDSF PWMAPSF PWMADSF
0x16
SFR3
-
-
-
-
F
F
F
F
PWMBPIE PWMBDIE PWMAPIE PWMADIE
-
-
-
-
0x1D
IMR3
Bank 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
-
R/W
PWMBS
R/W
R/W
PWMAS
R/W
-
-
-
-
0x16 PWMSCR
0x17 PWMACR
Bank 1
Bank 1
-
PWMAE
R/W
TAEN
R/W
TAP2
R/W
TAP1
R/W
TAP0
R/W
PRDA7 PRDA6 PRDA5 PRDA4
R/W R/W R/W R/W
PRDA3
PRDA2
R/W
PRDA1
R/W
PRDA0
R/W
0x18 PRDAL
0x19 PRDAH
Bank 1
Bank 1
R/W
PRDA15 PRDA14 PRDA13 PRDA12 PRDA11
PRDA10
PRDA9
PRDA8
R/W
DTA7
R/W
R/W
DTA6
R/W
R/W
DTA5
R/W
R/W
DTA4
R/W
R/W
DTA3
R/W
R/W
DTA2
R/W
R/W
DTA1
R/W
R/W
DTA0
R/W
0x1A
0x1B
DTAL
DTAH
Bank 1
Bank 1
Bank 1
DTA15 DTA14 DTA13 DTA12
R/W R/W R/W R/W
TMRA7 TMRA6 TMRA5 TMRA4
DTA11
R/W
DTA10
R/W
DTA9
R/W
DTA8
R/W
TMRA3
R/W
TMRA2
R/W
TMRA1
R/W
TMRA0
R/W
0x1C TMRAL
0x1D TMRAH
0x1E PWMBCR
0x1F PRDBL
R/W
R/W
R/W
R/W
TMRA15 TMRA14 TMRA13 TMRA12 TMRA11
TMRA10
TMRA9
TMRA8
Bank 1
Bank 1
Bank 1
R/W
PWMBE
R/W
R/W
R/W
R/W
R/W
TBEN
R/W
R/W
TBP2
R/W
R/W
TBP1
R/W
R/W
TBP0
R/W
-
-
-
-
-
-
PRDB7 PRDB6 PRDB5 PRDB4
R/W R/W R/W R/W
PRDB3
PRDB2
R/W
PRDB1
R/W
PRDB0
R/W
R/W
PRDB15 PRDB14 PRDB13 PRDB12 PRDB11
PRDB10
PRDB9
PRDB8
0x20 PRDBH
Bank 1
R/W
DTB7
R/W
R/W
DTB6
R/W
R/W
DTB5
R/W
R/W
DTB4
R/W
R/W
DTB3
R/W
R/W
DTB2
R/W
R/W
DTB1
R/W
R/W
DTB0
R/W
0x21
0x22
DTBL
DTBH
Bank 1
Bank 1
Bank 1
DTB15 DTB14 DTB13 DTB12
R/W R/W R/W R/W
TMRB7 TMRB6 TMRB5 TMRB4
R/W R/W R/W R/W
DTB11
R/W
DTB10
R/W
DTB9
R/W
DTB8
R/W
TMRB3
R/W
TMRB2
R/W
TMRB1
R/W
TMRB0
R/W
0x23 TMRBL
0x24 TMRBH
TMRB15 TMRB14 TMRB13 TMRB12 TMRB11 TMRB10
R/W R/W R/W R/W R/W R/W
TMRB9
TMRB8
Bank 1
R/W
R/W
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6.8.3 Increment Timer Counter (TMRX: TMRxH/TMRxL)
TMRXs are 16-bit clock counters with programmable prescalers. They are designed for
the PWM module as baud rate clock generators. TMR can be read only. If employed, they
can be turned off for power saving by setting the TxEN Bit to “0”. TMRA and TMRB are
internal designs and cannot be read.
6.8.4 PWM Time Period (PRDX: PRDxL/H)
The PWM time period has a 16-bit resolution and is defined by writing to the PRDX
register. When TMRX is equal to PRDX, the following events occur on the next increment
cycle:
1) TMRX is cleared
2) The PWMX pin is set to “1”
NOTE
The PWM output cannot be set if the duty cycle is “0.”
3) The PWMXPSF bit is set to “1”
To calculate PWM time period, use the following formula:
Example:
PRDX = 49; Fosc = 4 MHz; TMRX (0, 0, 0) = 1 : 1;
Then
1
Period
49 1
1 12.5s
4M
6.8.5 PWM Duty Cycle (DTX: DTxH/DT1L)
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to
DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX
can be loaded at anytime, however it cannot be latched into DLX until the current value of
DLX is equal to TMRX.
The following formula shows how to calculate the PWM duty cycle:
1
Duty cycle
DTX
TMRX prescale value
FOSC
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Example:
DTX = 10;
Then
Fosc = 4 MHz;
TMRX (0, 0, 0) = 1 : 1;
1
Duty cycle
10
1 2.5s
4M
6.8.6 PWM Programming Process/Steps
1) Load the PWM duty cycle to DT
2) Load the PWM time period to PRD
3) Enable the interrupt function by writing Bank0-R1D, if required
4) Load a desired value for the timer prescaler
5) Enable PWMX function (i.e., enable PWMXE control bit)
6) Finally, enable TMRX function (i.e., enable TXEN control bit)
If the application needs to change PWM duty and period cycle at run time, refer to the
following programming steps:
1) Load new duty cycle (if using dual PWM function) at any time.
2) Load new period cycle. You must take note of the order of loading period cycle. As the
low byte of PWM period cycle is assigned a value, the new PWM cycle is loaded into a
circuit.
3) The circuit will automatically update the new duty and period cycles to generate new
PWM waveform at the next PWM cycle.
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6.9 Timer
R_BANK Address Name
Bit 7
Bit 6
TC1RC TC1SS1
R/W R/W
Bit 5
Bit 4
Bit 3
TC1FF TC1OMS TC1IS1 TC1IS0
R/W R/W R/W
Bit 2
Bit 1
Bit 0
TC1S
-
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
0x24
0x25
0x26
0x27
0x15
0x1C
TC1CR1
TC1CR2
TC1DA
TC1DB
SFR2
R/W
-
R
TC1M2 TC1M1 TC1M0 TC1SS0 TC1CK3 TC1CK2 TC1CK1 TC1CK0
R/W R/W R/W R/W R/W R/W R/W R/W
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
R/W R/W R/W R/W R/W R/W R/W R/W
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TC1SF
F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TC1IE
R/W
IMR2
6.9.1 Timer/Counter Mode
TCxM2~0
TCxM2~0=timer/counter mode
TCx pin
M
fc/215
fc/20
MUX
clear
8-bit up counter
TC1S
TCxCK
Comparator
TCx
interrupt
4
TCxCR
TCxDB
TCxDA
Data Bus
Figure 6-12a Timer/Counter Mode Block Diagram
In Timer/Counter mode, counting up is performed using internal clock or TCx pin. When
the contents of the up-counter are matched with the TCxDA, an interrupt is generated and
the counter is cleared. Counting up resumes after the counter is cleared. The current
contents of the up-counter are loaded into TCxDB by setting TCxRC to “1”.
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Internal clock
Up-counter
TCxDA
n
5
n-2
0
1
2
3
4
n-3
n-1
0
1
2
3
n
match
counter clear
TCx interrupt
TCx Pin
1
2
3
n 0
4
n-2
Up-counter
TCxDA
0
n-1
1
2
3
n
match
counter clear
TCx interrupt
Figure 6-12b Timer/Counter Mode Waveform
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6.9.2 Window Mode
TCx pin
fc/215
Window
clear
8-bit up counter
MUX
fc/20
Comparator
TCx interrupt
TCxCK
TCxS
4
TCcCR2
TCxDA
Data Bus
Figure 6-13a Window Mode Block Diagram
In Window mode, counting up is performed on a rising edge of the pulse that is logical AND
of an internal clock and the TCx pin (window pulse). When the contents of the up-counter
are matched with the TCxDA, interrupt is generated and the counter is cleared. The
frequency (window pulse) must be lower than the selected internal clock.
TCx pin
Internal clock
Up-counter
TCxDA
n-1
n
0
n-2
0
1
2
n-3
1
2
3
n
match
counter clear
TCx interrupt
Figure 6-13b Window Mode Waveform
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6.9.3 Capture Mode
Inhibit
Rising
Edge
detector
Capture
control
TCx
Falling
TCxM2~0
M
interrupt
TCxM2~0=010
TCx pin
fc/215
Overflow
8-bit up counter
MUX
fc/20
TC1S
CAP
TCxCK
4
Capture
Capture
TC1CR
TCxDB
TCxDA
Data Bus
Figure 6-14a Capture Mode Block Diagram
In Capture mode, the pulse width, period and duty of the TCx input pin are measured and
can be used to decode the remote control signal. The counter is free running by the
internal clock. On a rising (falling) edge of TCx pin, the contents of the counter are loaded
into TCxDA, then the counter is cleared and interrupt is generated. On a falling (rising)
edge of TC1 pin, the contents of the counter are loaded into TCxDB. At this time, the
counter is still counting. Once the next rising edge of TCx pin is triggered, the contents of
the counter are loaded into TCxDA, the counter is cleared and interrupt is generated once
again. If overflow before the edge is detected, the FFH is loaded into TCxDA and an
overflow interrupt is generated. During interrupt processing, user can determine whether
or not there is an overflow by checking if the TCxDA value is FFH. After an interrupt
(capture to TCxDA or overflow detection) is generated, capture and overflow detection are
halted until TCxDA is read out.
Clock source
m
m+1
1
m-1
n
0
1
2
3
FE FF0
1
2
3
K-2
K-1 K 0
n-1
Up-counter
TCx pin input
TCxDA
K
n
FF (overflow)
overflow
m
FE
TCxDB
capture
capture
TCx Interrupt
Reading TCxDA
Figure 6-14b Capture Mode Waveform
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8-Bit Microcontroller
6.9.4 Programmable Divider Output Mode and Pulse Width
Modulation Mode
TCxFF
TCxM2~0=101
TCx interrupt
F/F
PWMx,PDOx pin
Q
clear
TCxM2~0=10x
toggle
8-bit up counter
fc/215
fc/20
MUX
match
Comparator
TCxS
TCxCK2~0
match
Comparator
4
TCxCR
TCxDA_buffer2
TCxDA_buffer1
TCxDB_buffer2
TCxDB_buffer1
TCxDB
Write TCxDA[0]
TCxDA
Data Bus
Figure 6-15a PDO/PWM Mode Block Diagram
Programmable Divider Output (PDO)
In Programmable Divider Output (PDO) mode, counting up is performed using the internal
clock. The contents of TCxDA are compared with the contents of the up- counter. The F/F
output is toggled and the counter is cleared each time a match is found. The F/F output is
inverted and output to PDO pin. This mode can generate 50% of the duty pulse output.
The PDO pin is initialized to “0” during reset. A TCx interrupt is generated each time the
PDO output is toggled.
Clock source
n
n
0
Up-counter
0
1
2
3
n-1
2
3
n-1
3
n
n-1 0
0
1
1
2
1
2
n
TCxDA
PDO pin
(TCxFF = 0)
PDO pin
(TCxFF = 1)
TCx Interrupt
Figure 6-15b PDO Mode Waveform
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Pulse Width Modulation (PWM)
In Pulse Width Modulation (PWM) Output mode, counting up is performed using the
internal clock with prescaler. The Duty of PWMx is controlled by TCxDB, and the period of
PWMx is controlled by TCxDA. The pulse at the PWMx pin is held to high levels as long as
TCxS=1 or timerx matches TCxDA, while the pulse is held to low levels as long as Timerx
matches TCxDB. Once TCxFF is set to 1, PWMx signal is inverted. A TCx interrupt is
generated and defined by TCxIS. On the other hand, the TCxDA and TCxDB can be
written anytime, but the data of TCxDA and TCxDB can only be latched when writing
TCxDA0. Therefore, the new duty and new period of PWM appear at the PMW pin during
the last period–match.
Clock source
Up-counter
n
p
p+2
p+1
n+1 n+2
p-1
q-1
q
0
1
n-1
n-1
n
m-1
m
0
m-1
m
0
n+2
n+1
1
n
p
Duty
duty-match
Writing duty register
period-match
duty-match
duty-match
period-match
period-match
m
q
Period
PWM
Writing period register
n
p
m+1
q+1
TCx Interrupt
Figure 6-15c PWM Mode Waveform
6.9.5 Buzzer Mode
The TCx pin outputs the clock after dividing the frequency.
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6.10SPI (Serial Peripheral Interface)
R_BANK Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CES
SPIE
SRO
SSE
SDOC
SBRS2 SBRS1 SBRS0
Bank 0
Bank 0
Bank 0
Bank 0
0X36
0X37
0X38
0X39
SPICR
SPIS
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
-
-
DORD
TD1
TD0
OD3
OD4
-
-
RBF
R/W
R/W
R
R/W
R/W
R/W
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
SPIR
SPIW
R
R
R
R
R
R
R
R
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
SPISF
R/W
-
-
-
-
-
-
Bank 0
Bank 0
0X17
0X1E
SFR4
IMR4
-
-
-
-
-
-
-
-
SPIIE
R/W
-
-
-
-
-
-
6.10.1 Overview and Features
Overview:
Figures 6-8a and 6-8b show how the eKTF5616/08 communicates with other devices
through SPI module. If the eKTF5616/08 is the Master controller, it will send clock through
the SCK pin. A couple of 8-bit data are transmitted and received at the same time.
However, if the eKTF5616/08 is defined as a Slave, its SCK pin could be programmed as
an input pin. Data will continue to be shifted based on both clock rate and the selected
edge. User can also set the –
SPIS Bit 7 (DORD) to determine the SPI transmission order,
SPICR Bit 3 (SDOC) to control SDO pin after serial data output status,
SPIS Bit 6 (TD1) and Bit 5 (TD0) to determine the SDO status output delay times.
Features:
1) Operation in either Master mode or Slave mode
2) Three-wire or four-wire full duplex synchronous communication
3) Programmable baud rates of communication
4) Programmable clock polarity (Bank 0 R36 Bit 7)
5) Interrupt flag available for read buffer full
6) SPI transmission order
7) SDO status select after serial data output
8) SDO status output delay time
9) SPI handshake pin
10) Up to 8 MHz (maximum) bit frequency
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SDO
SPIR Reg
SPIW Reg
SPIR Reg
SPIW Reg
/SS
SDI
SPIS Reg
SPIS Module
SCK
Master Device
Slave Device
Figure 6-8a SPI Master/Slave Communication Block Diagram
SDI
SDO
SCK
/SS
Vdd
Master
P60
P61
P62
P63
Slave Device 1
Slave Device 2
Slave Device 4
Slave Device 3
Figure 6-8b Single-Master and Multi-Slave SPI Configuration
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6.10.2 SPI Function Description
Read
Write
RBF
SPIIF
SSE
SPIW
SPIR reg
reg
Set to 1
Buffer Full Detector
shift right
SPIS reg
SI
SPIC reg
SO
Edge
Select
SBR0 ~SBR2
SBR2~SBR0
Noise
Filter
/SS
/ SS
Clock Select
Prescaler
2, 4, 8, 16, 32
Fosc
Edge
Select
SCK
TMR2
CES
Figure 6-9a SPI Function Block Diagram
SPI
SO
SI
Shift Clock
SPI Shift
Buffer
FOSC
2 1 0
SPIC
7 6 4 5 4
3
0
7~0
SPIW
7~0
SPIR
SPIC
ISR4
SPIC
SPIS
DATA Bus
Figure 6-9b SPI Transmission Function Block Diagram
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The following explains the functions of each block in the above figures as SPI carries out
communication with the depicted signals:
P51/SI: Serial Data In
P52/SO: Serial Data Out
P53/SCK: Serial Clock
P50//SS: /Slave Select (Option). This pin (/SS) may be required during Slave mode.
RBF: Set by Buffer Full Detector
Buffer Full Detector: Set to 1 when an 8-bit shifting is completed.
SSE: Load the data in SPIS register, and begin shifting. The SSE bit will be kept in “1”
if the communication is still undergoing. This flag must be cleared as shifting is
completed. You can determine if the next write attempt is available.
SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIR and the
SPIW registers are shifted at the same time. Once data is written, SPIS starts
transmitting/receiving. The received data will be moved to the SPIR register as the
shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the SPISF
(SPI Interrupt) flag are then set.
SPIR reg.: Read buffer. The buffer is updated as the 8-bit shifting is completed. The
data must be read before the next reception is completed. The RBF flag is cleared as
the SPIR register reads.
SPIW reg.: Write buffer. The buffer will deny any attempts to write until the 8-bit
shifting is completed.
SBRS2~SBRS0: Programming of the clock frequency/rates and sources.
Clock Select: Select either the internal or the external clock as shifting clock.
Edge Select: Select the appropriate clock edges by programming the CES bit
6.10.3 SPI Signal and Pin Description
The detailed functions of the four pins, SI, SO, SCK, and /SS are as follows:
P52/SI/TPA2:
Serial Data In
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
last.
Defined as high-impedance if not selected.
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Program the same clock rate and clock edge to latch on both Master and Slave devices.
The byte received will update the transmitted byte.
The RBF will be set as the SPI operation is completed.
Timing is shown in Figures 6-10a and 6-10b below.
P52/SO:
Serial Data Out
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
last.
Program the same clock rate and clock edge to latch on both the Master and Slave
devices.
The received byte will update the transmitted byte.
The CES bit is reset, as the SPI operation is completed.
Timing is shown in Figures 6-10a and 6-10b.
P53/SCK:
Serial Clock
Generated by a Master device
Synchronize the data communication on both the SI and SO pins.
The CES is used to select the edge to communicate.
The SBR0~SBR2 is used to determine the baud rate of communication.
The CES, SBR0, SBR1, and SBR2 bits have no effect in Slave mode.
Timing is shown in Figures 6-10a and 6-10b.
P50//SS:
Slave Select; negative logic.
Generated by a Master device to indicate the Slave(s) has to receive data.
Go low before the first cycle of SCK occurs, and remain low until the last (8th) cycle is
completed
Ignore the data on the SI and SO pins when /SS is high, because SO is no longer driven
Timing is shown in Figures 6-10a and 6-10b.
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6.10.4 SPI Mode Timing
Figure 6-10a SPI Mode with /SS Disabled Timing Diagram
The SCK edge is selected by programming the bit CES. The waveform shown in Figure
6-10a above is applicable regardless of whether the eKTF5616/08 is in Master or Slave
mode with /SS disabled. However, the waveform in Figure 6-10b below can only be
implemented in Slave mode with /SS enabled.
Figure 6-10b SPI Mode with /SS Enabled Timing Diagram
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8-Bit Microcontroller
6.11 UART (Universal Asynchronous Receiver/Transmitter)
Registers for UART Circuit
R_BANK Addr. Name
Bank 0 0x15 SFR2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
UTSF
R/W
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
UERRSF URSF
-
-
-
-
-
-
-
-
-
-
-
-
R/W
UERRIE
R/W
R/W
URIE
R/W
UTIE
R/W
Bank 0 0x1C IMR2
Bank 1 0X33 URCR
Bank 1 0X34 URS
Bank 1 0x35 URTD
Bank 1 0X36 URRDL
Bank 1 0X37 URRDH
UINVEN UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE
TXE
R/W
RXE
R/W
R/W
URTD8 EVEN
R/W
R/W
R/W
PRE
R/W
R/W
PRERR OVERR FMERR URBF
R/W R/W R/W
R/W
R/W
R/W
W
R
URTD7 URTD6 URTD5 URTD4 URTD3 URTD2 URTD1 URTD0
W
W
W
W
W
W
W
W
URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0
R
URRD8
R
R
-
R
-
R
-
R
-
R
-
R
-
R
URSS
R/W
-
-
-
-
-
-
Baud Rate
Generator
selector
Fsystem
Interrupt
Control
TXE
RXE
RX Control
TX Control
RX
RX Shift Register
URRD
Parity Control
TX
URRD8
Error Flag
Data Bus
URTD8
URTD
UINVEN
UINVEN
Figure 6-16 UART Functional Block Diagram
In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received
character is individually synchronized by framing it with a start bit and a stop bit.
Full duplex data transfer is possible since the UART has independent transmit and receive
sections. Double buffering for both sections allows the UART to be programmed for
continuous data transfer.
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8-Bit Microcontroller
The figure below shows the general format of one character sent or received. The
communication channel is normally held in the marked state (high). Character
transmission or reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits, in
which the least significant bit (LSB) comes first. The data bits are followed by the parity bit.
If present, the stop bit or bits (high) confirm the end of the frame.
In receiving, the UART synchronizes on a falling edge of the start bit. When two or three
“0”s are detected during three samples, it is recognized as normal start bit and the
receiving operation is started.
Idle state
(mark)
Parity
bit
Start
Bit
Stop
Bit
D0
D1
D2
Dn
1 bit
7 or 8 bits
1 bit
One character of frame
Figure 6-17 Data Format in UART
6.11.1 UART Mode
There are three UART modes. Mode 1 (7 bits data) and Mode 2 (8 bits data) allow the
addition of a parity bit. The parity bit addition is not available in Mode 3. Figure 6-18a
below shows the data format in each mode.
UMODE PRE
1
2
3
5
6
7
8
9
10
11
4
Start
Stop
7 bits data
0
0
0
0
0
1
Mode 1
Start
Start
Start
Start
Parity
Stop
Stop
7 bits data
8 bits data
8 bits data
0
0
1
1
0
1
Mode 2
Mode 3
Parity
Stop
Stop
9 bits data
1
0
X
Figure 6-18a UART Model
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8-Bit Microcontroller
6.11.2 Transmitting
In transmitting serial data, the UART operates as follows:
1. Set the TXE bit of the URCR1 register to enable the UART transmission function.
2. Write data into the URTD register and the UTBE bit of the URCR register will be
cleared by hardware.
3. Then start transmitting.
4. Serially transmitted data are transmitted in the following order from the TX pin.
5. Start bit: one “0” bit is output.
6. Transmit data: 7, 8 or 9 bits’ data are outputs from the LSB to the MSB.
7. Parity bit: one parity bit (odd or even selectable) is output.
8. Stop bit: one “1” bit (stop bit) is output.
Mark state: output “1” continues until the start bit of the next transmitted data.
After transmitting the stop bit, the UART generates a UTSF interrupt (if enabled).
6.11.3 Receiving
In receiving, the UART operates as follows:
1. Set the RXE bit of the URS register to enable the UART receiving function. The UART
monitors the RX pin and synchronizes internally when it detects a start bit.
2. Received data is shifted into the URRD register in the order of LSB to MSB.
3. The parity bit and the stop bit are received. After one character is received, the URBF
bit of the URS register will be set to “1”. This means UART interrupt will occur.
4. The UART conducts the following checks:
(a) Parity check: The number of “1” of the received data must match the even or odd
parity setting of the EVEN bit in the URS register.
(b) Frame check: The start bit must be “0” and the stop bit must be “1”.
(c) Overrun check: The URBF bit of the URS register must be cleared (that means the
URRD register should be read out) before the next received data is loaded into the
URRD register.
If any checks failed, the UERRSF interrupt will be generated (if enabled), and an error
flag is indicated in PRERR, OVERR or FMERR bit. The error flag should be cleared by
software, otherwise, UERRSF interrupt will occur when the next byte is received.
5. Read received data from URRD register. And URBF bit will be set by hardware.
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8-Bit Microcontroller
6.11.4 Baud Rate Generator
The baud rate generator is comprised of a circuit that generates a clock pulse to determine
the transfer speed for transmission/reception in the UART.
The BRATE2~BRATE0 bits of the URC register can determine the desired baud rate.
6.11.5 UART Timing
1. Transmission Counter Timing:
1
2
3
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
4
FUART*16
One bit cycle
TXD pin
Start bit
Bit 0
2. Receiving Counter Timing:
Synchronization
(reset counter)
15 16
1
2
3
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
4
FUART*16
One bit cycle
RXD pin
Stop bit
Start bit
Bit 0
Sampling timing
Figure 6-18b UART Timing Diagrams
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8-Bit Microcontroller
6.12 I2C Function
The I2C function and transmit/receive pin are enabled by default when eKTF5616/08 is
powered-on.
Registers for I2C circuit:
R_BANK Address Name
Bit 7
Bit 6
IMS
Bit 5
ISS
Bit 4
Bit 3
Bit 2
ACK
R/W
Bit 1
FULL
R/W
Bit 0
Strobe
/Pend
SAR_
EMPTY
STOP
EMPTY
Bank 0
0x30
I2CCR1
R/W
R/W
GCEN
R/W
SA5
R/W
DB6
R/W
DA6
R/W
-
R/W
R/W
BBF
R
R/W
R/W
I2CEN
R/W
IRW
R/W
DB0
R/W
DA0
R/W
DA8
R/W
I2CBF
I2COPT
I2CTS2 I2CTS1 I2CTS0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
0x31
0x32
0x33
0x34
0x35
0x17
0x1E
I2CCR2
I2CSA
I2CDB
I2CDAL
I2CDAH
SFR4
R
R/W
R/W
R/W
SA1
R/W
DB2
R/W
DA2
R/W
-
R/W
SA0
R/W
DB1
R/W
DA1
R/W
DA9
R/W
SA6
SA4
SA3
R/W
DB4
R/W
DA4
R/W
-
SA2
R/W
R/W
R/W
DB7
DB5
DB3
R/W
R/W
R/W
DA7
DA5
DA3
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2CSTPIF I2CRSF I2CTSF
-
-
-
-
R/W
I2CSTPIE I2CRIE
R/W R/W
R/W
R/W
I2CTIE
R/W
-
-
IMR4
-
-
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8-Bit Microcontroller
Read
Write
FULL
I2CRIF
I2CTIF
I2CDB reg
Buffer Full Detector
Control and
Status reg
SCL
I2CSA reg
MSb
LSb
SDA
Add Match
Match Detect
I2CDA reg
Start and Stop
bit Detect
Figure 6-11 eKTF5616/08 I2C Block Diagram
The eKTF5616/08 supports a bidirectional, 2-wire bus, 7/10-bit addressing, and data
transmission protocol. A device sending data to the bus is defined as transmitter, while a
device receiving the data is defined as a receiver. The bus has to be controlled by a
Master device which generates the Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions. Both Master and Slave can operate as
transmitter or receiver, but the Master device determines which mode is activated.
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a
pull-up resistor. When the bus is free, both lines are HIGH. The output stages of the
devices connected to the bus must have an open-drain or open-collector to perform the
wired-AND function. Data on the I2C-bus can be transferred at the rates of up to 100
kbit/sec in Standard-mode or up to 400 kbit/sec in Fast-mode.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or
LOW state of the data line can only be changed when the clock signal on the SCL line is
LOW.
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The I2C interrupt occurs as describe below:
Condition
Master/Slave Transmit Address Transmit Data
Stop
Master
Slave
Transmit interrupt Transmit interrupt
NA
Master Transmitter
(transmits to
Slave-Receiver)
Receive interrupt Receive interrupt Stop interrupt
Master Receiver
(read Slave-
Transmitter)
Master
Slave
Transmit interrupt Receive interrupt
NA
Transmit interrupt
Transmit interrupt Stop interrupt
Within the procedure of the I2C bus, unique situations could arise which are defined as
START (S) and STOP (P) conditions.
A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case.
This situation indicates a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.
SCL
SDA
data line change
stable;
data valid allowed
of data
START
STOP
Figure 6-12 I2C Transfer Condition
6.12.1 7-Bit Slave Address
Master-transmitter transmits to Slave-receiver. The transfer direction is not changed.
Master reads Slave immediately after the first byte. At the moment of the first
acknowledgement, the Master-transmitter becomes a Master-receiver and the
Slave-receiver becomes a Slave-transmitter. This first acknowledgement is still generated
by the Slave. The STOP condition is generated by the Master, which has previously sent a
Not-Acknowledge (A). The only difference between Master-transmitter and
Master-receiver is their R//W bits. If the R//W bit is “0”, the Master device would be a
transmitter. Otherwise, the Master device would be a receiver (R//W Bit = “1”).
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8-Bit Microcontroller
Communications between the Master-transmitter/receiver and Slave- transmitter/receiver
are illustrated in the following Figures 6-13a and 6-13b.
8 Bits
8 Bits
Data
8 Bits
Data
S
Slave Address
7 Bits
R//W
A
A
A//A
P
'0'
Write
data transferred
(n byte + acknowledge)
Master to Slave
Slave to Master
A = acknowledge (SDA low)
/A = not acknowledge (SDA high)
S = Start
P = Stop
Figure 6-13a Master-Transmitter Transmits to Slave-Receiver with 7-Bit Slave Address
8 Bits
S
Slave Address
7 Bits
R//W
A
Data
A
Data
/A
P
'1' Read
data transferred
(n byte + acknowledge)
Figure 6-13b Master-Receiver Reads from Slave-Transmitter with 7-Bit Slave Address
6.12.2 10-Bit Slave Address
In 10-Bit Slave address mode, using 10-bit for addressing exploits the reserved
combination 11110XX for the first seven bits of the first byte following a START(S) or
repeated START (Sr) condition. The first seven bits of the first byte are the combination
11110XX of which the last two bits (XX) are the two most-significant bits of the 10-bit
address. If the R//W bit is “0”, the second byte after acknowledge would be the eighth
address bit of 10-bits Slave address. Otherwise, the second byte would just be the next
transmitted data from a Slave to Master device. The first byte 11110XX is transmitted by
using the Slave address register (I2CSA), and the second byte XXXXXXXX is transmitted
by using the data buffer (I2CDB).
The possible data transfer formats for 10-bit Slave address mode are explained in the
following paragraphs and Figures 6-14a ~ 6-14e.
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Master-Transmitter Transmits to Slave-Receiver with a 10-bit
Slave Address
When the Slave receives the first byte after START bit from Master, each Slave device will
compare the first seven bits of the first byte (11110XX) with their own address and check
the 8th bit (R//W). If the R//W bit is “0”, a Slave or more, will return an Acknowledge (A1).
Then all Slave devices will continue to compare the second address (XXXXXXXX). If a
Slave device finds a match, that particular Slave device will be the only one to return an
Acknowledge (A2). The matched Slave device will remain addressed by the Master until it
receives the STOP condition or until a repeated START condition followed by the different
Slave address is received.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A1
A2
A
A//A
R//W
Data
Data
P
Write
1st 7 Bits
2nd 8 Bits
Figure 6-14a Master-Transmitter Transmits to Slave-Receiver with a 10-Bit Slave Address
Master-Receiver Read Slave-Transmitter with a 10-bit Slave Address
Up to, and including Acknowledge Bit A2, the procedure is the same as that described
above for Master-Transmitter addressing a Slave-Receiver. After the Acknowledge (A2), a
repeated START condition (Sr) takes place followed by seven bits Slave address
(11110XX), but the 8th bit R//W is “1.” The addressed Slave device will then return the
Acknowledge (A3). If the repeated START (Sr) condition occurs and the seven bits of first
byte (11110XX) are received by Slave device, all the Slave devices will compare with their
own addresses and check the 8th bit (R//W). However, none of the Slave devices can
return an acknowledgement because R//W=1.
1 1 1 1 0 X X
0
1 1 1 1 0 X X
1
Slave
Address
Slave
Address
Slave
Address
S
DATA
A1
A2 Sr
A3
A
DATA /A
P
R//W
R//W
1st 7 Bits
2nd 8 Bits
1st 7 Bits Read
Write
Figure 6-14b Master-Receiver reads Slave-Transmitter with a 10-Bit Slave Address
Master Transmits and Receives Data to and from the Same Slave Device
with 10-Bit Addresses
The initial operation of this data transfer format is the same as explained in the above
paragraph on “Master-Transmitter transmits to Slave-Receiver with a 10-bit Slave
Address.” Then the Master device starts to transmit the data to the Slave device. When
the Slave device receives the Acknowledge or None-Acknowledge that is followed by
repeat START (Sr), the above operation under “Master-Receiver Reads Slave-Transmitter
with a 10-Bit Slave Address” is repeatedly performed.
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8-Bit Microcontroller
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
R//W
A
A
A
A//A
Data
Data
1st 7 Bits
Write
2nd 8 Bits
1 1 1 1 0 X X
1
Slave
Address
Sr
R//W
A
A
/A
Data
Data
P
1st 7 Bits
Read
Figure 6-14c Master Addresses a Slave with 10-Bit Addresses Transmits and Receives Data with
the Same Slave Device
Master Device Transmits Data to Two or More Slave Devices with 10 & 7
Bits Slave Address
For 10-bit address, the initial operation of this data transfer format is the same as the one
explained in the above paragraph on “Master-Transmitter transmits to Slave-Receiver with
a 10-bit Slave Address” describing how to transmit data to Slave device. After the Master
device completes the initial transmittal, and wants to continue transmitting data to another
device, the Master needs to address each of the new Slave devices by repeating the initial
operation mentioned above. If the Master device wants to transmit the data in 7-bit and
10-bit Slave address modes successively, this could be done after the Start or repeat Start
conditions as illustrated in the following figures.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A
A
A
A//A
Data
Data
R//W
1st 7-Bits
Write
2nd 8-Bits
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
R//W
A
A
A
A//A
Data
Data
P
1st 7-Bits
Write
2nd 8-Bits
Figure 6-14d Master Transmitting to More than One Slave Devices with 10-Bit Slave Address
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8-Bit Microcontroller
0
Slave
Address
S
A
A
A//A
R//W
Data
Data
7 Bits
Write
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
R//W
A
A
A
A//A
Data
Data
P
1st 7 Bits
Write
2nd 8 Bits
Figure 6-14e Master Successively Transmitting to 7-Bit and 10-Bit Slave Address
6.12.3 Master Mode
In transmitting (receiving) serial data, the I2C is carried on as follows:
1) Set I2CTS1~0, I2CCS, and ISS bits to select I2C transmit clock source.
2) Set I2CEN and IMS bits to enable THE I2C Master function.
3) Write Slave address into the I2CSA register and IRW bit to select read or write.
4) Set strobe bit to start transmitting and then check I2CTSF (I2CTSF) bit.
5) Write 1st data into the I2CDB register, set strobe bit, and check I2CTSF (I2CRSF) bit.
6) Write 2nd data into the I2CDB register, set strobe bit, STOP bit, and check I2CTSF
(I2CRSF) bit.
6.13.4 Slave Mode I2C Transmit
In receiving (transmitting) serial data, the I2C is carried on as follows:
1) Set I2CTS1~0, I2CCS, and ISS bits to select I2C transmit clock source.
2) Set I2CEN and IMS bits to enable I2C Slave function.
3) Write device address into the I2CDA register.
4) Check I2CRSF (I2CTSF) bit, read I2CDB register (address), and then clear the Pend
bit.
5) Check I2CRSF (I2CTSF) bit, read I2CDB register (1st data), and then clear the Pend
bit.
6) Check I2CRSF (I2CTSF) bit, read I2CDB register (2nd data), and then clear the Pend
bit.
7) Check the I2CSTPSF bit, end transmission.
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8-Bit Microcontroller
6.13 HLVD (High / Low Voltage Detector)
R_BANK Address
Name
Bit 7
HLVDEN IRVSF
R/W
Bit 6
Bit 5
VDSB
R
Bit 4
VDM HLVDS3 HLVDS2 HLVDS1 HLVDS0
R/W R/W R/W R/W R/W
Bit 3
Bit 2
Bit 1
Bit0
Bank 1
Bank 0
Bank 0
Bank 0
0x49
0x14
0x1B
0x10
HLVDCR
R
LVDSF
R/W
SFR
IMR
LVDIE
R/W
LVDWK
R/W
WUCR
Under unstable power source condition, such as external power noise interference or EMS
test condition, a violent power vibration could occur. At the time, the VDD could become
unstable as it could be operating below working voltage. When the system supply voltage
(VDD) is below operating voltage, the IC kernel will automatically keep all register status.
The following steps are needed to set up the HLVD function:
1. Set the HLVDEN to “1”, then use Bits 3~0 (HLVDS3~HLVDS0) of Register Bank R to set
the HLVD interrupt level
2. Wait for HLVD interrupt to occur
3. Clear the HLVD interrupt flag
The internal HLVD module uses the internal circuit to fit. When user set the HLVDEN to
enable the HLVD module, the current consumption will increase to A.
During sleep mode, the HLVD module continues to operate. If the device voltage drops
slowly and crosses the detect point. The LVDSF bit will be set and the device will not wake
up from Sleep mode. Until another wake-up source wakes up eKTF5616/08, the HLVD
interrupt flag is still set as the prior status.
When the system resets, the HLVD flag will be cleared.
The Figure 6-30 shows the HLVD module to detect the external voltage situation.
When VDD drops above VLVD, LVDSF remain at “0”.
When VDD drops below VDB, LVDSF set to “1”. If global ENI enable, LVDSF will be set to
“1”, the next instruction will branch to the interrupt vector. The HLVD interrupt flag is
cleared to “0” by software.
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8-Bit Microcontroller
Figure 6-30 HLVD Waveform Characteristics Showing Detection Point in an External Voltage Condition
Power Condition-A
Power Condition-B
Power Condition-C
Power Condition-D
HLVD_EN
HLVD_EN
HLVD_EN
HLVD_EN
VDD
HLVD Release
HLVD Reset
Trim POR Release
Trim POR Reset
AC+DC POR Realease
AC+DC POR Reset
t
t
t
t
MCU Free Run
(Active Hi)
VDSB
VDM=0
HLVDSF
(Active Hi)
* MCU has already finished the Latch Code Option , the Trim POR is working
* Trim POR has 1us deglitch , response time us @ over drive mV
Figure 1.HLVD waveform situation
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eKTF5616/08
8-Bit Microcontroller
6.14 Oscillator
6.14.1 Oscillator Modes
The eKTF5616/08 can be operated in the one oscillator mode, i.e., Internal RC oscillator
mode (IRC). Users need to set the main-oscillator modes by selecting the OSC0, and set
sub-oscillator modes by selecting the FSS in the Code Option register to complete the
overall oscillator mode setting.
Main-Oscillator Modes Defined By OSC0
Main-Oscillator Mode
OSC0
IRC (Internal RC oscillator mode; default)
RCOUT (P55) acts as I/O pin
1
IRC (Internal RC oscillator mode)
RCOUT (P55) acts as clock output pin
0
Summary of Maximum Operating Speeds
Conditions
VDD
Fxt Max. (MHz)
2.1
8.0
4
5
12.0
16.0
Two cycles with two clocks
6.14.2 Internal RC Oscillator Mode
The eKTF5616/08 offers a versatile internal RC mode with default frequency value of
8 MHz. The Internal RC oscillator mode has other frequencies (16 MHz, and 12 MHz) that
can be set by Code Option; RCM1~RCM0. The Table below describes a typical drift rate of
the calibration.
Internal RC Drift Rate
Drift Rate
Temperature(-40℃
Touch
Key
Frequency
Process
Internal RC
Frequency
~+85℃) +
Total
(UWTR:+1%
Voltage(2V~5.5V)
NUWTR:
+0.5%)
VDD
±9.5%
Regulator
VDD
±10.5%
±10.5%
±10.5%
Regulator
8MHz
24MHz
24MHz
16MHz
±2%
±2%
±2%
±1%
±1%
±1%
±3%
±3%
±3%
12MHz
16MHz
±9.5%
±9.5%
Note: These are theoretical values intended for reference only. Actual values may vary depending
on actual conditions.
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8-Bit Microcontroller
6.15 Power-On Considerations
Any microcontroller is not guaranteed to start to operate properly before the power supply
reaches its steady state. The eKTF5616/08 is equipped with a Power-on Voltage Detector
(POVD) with a detection level of 1.9V. It will work well if Vdd rises fast enough (50 ms or
less). However, in critical applications, extra devices are still required to assist in solving
power-up problems.
6.16 External Power-on Reset Circuit
The circuits diagram in Figure 6-15 implements an external RC to generate the reset pulse.
The pulse width (time constant) should be kept long enough for VDD to reach minimum
operational voltage. Apply this circuit when the power supply has slow rise time. Since the
current leakage from the /RESET pin is about 5 A, it is recommended that R should not
be greater than 40KΩ in order for the /RESET pin voltage to remain at below 0.2V. The
diode (D) functions as a short circuit at the instant of power down. The capacitor (C) will
discharge rapidly and fully. The current-limited resistor (Rin) will prevent high current or
ESD (electrostatic discharge) from flowing into /RESET pin.
VDD
/RESET
R
D
Rin
C
Figure 6-15 External Power-Up Reset Circuit
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eKTF5616/08
8-Bit Microcontroller
6.17 Residue-Voltage Protection
When the battery is replaced, device power (VDD) is taken off but residue-voltage remains.
The residue-voltage may trip below VDD minimum, but not to zero. This condition may
cause a poor power-on reset. Figures 6-16a and 6-16b show how to accomplish a proper
residue-voltage protection circuit.
VDD
VDD
33K
Q1
10K
/RESET
100K
1N4684
Figure 6-16a Circuit 1 for Residue Voltage Protection
VDD
VDD
R1
R2
Q1
R3
/RESET
Figure 6-16b Circuit 2 for Residue Voltage Protection
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eKTF5616/08
8-Bit Microcontroller
6.18 Code Option
6.18.1 Code Option Register (Word 0)
Word 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Mnemonic
-
-
High
Low
IRCWUT
32 clks
8 clks
IODG1
High
Low
Bit 4
NRHL
8/fc
IODG0
High
Low
Bit 3
NRE
HLFS
Green
Normal
Bit 2
EEPR2
High
HLP
Low
LVR1
High
Low
Bit 0
EEPR0
High
1
0
High
Low
Bit 7
LVR0
High
Low
High
Bit 1
EEPR1
High
Low
Bit 6
Bit 5
Mnemonic
RESETEN
/RST
P50
ENWDT
Enable
Disable
1
0
Disable
Enable
32/fc
Low
Low
Bits 15~14, 11: Not used, set to "0" all the time.
Bit 13 (IRCWUT): IRC Warm Up time (Support IRC Frequency 8MHz)
1: 32 clocks
0: 8 clocks (default)
Waiting time before CPU starting to work
CPU mode
switch
IRC
Frequency
POR/LVR
PERCS = 1
PERCS = 0
16ms + WSTO + 32
clocks
(main frequency)
16ms + WSTO + 8/32
clocks
(main frequency)
16ms + WSTO + 8
clocks
32 clocks
(main frequency)
WSTO + 32 clocks
(main frequency)
12M, 16M
8M
Sleep -> Normal
Idle -> Normal
Green -> Normal
8/32 clocks
(main frequency)
WSTO + 8/32 clocks
(main frequency)
Sleep -> Green
Idle -> Green
WSTO + 8 clocks
(sub frequency)
WSTO + 8 clocks
(sub frequency)
32KHz
(sub frequency)
Bits 12~11 (IODG1~IODG0): I2C pin deglitch time select bits.
SPI pin deglitch time I2C pin deglitch time UART pin deglitch time
typical delay=8ns 50ns@5v,Min.(default) 50ns@5v,Min.(default)
IODG1~0
OCD pin deglitch time
00
01
typical delay=15ns
typical delay=25ns
no deglitch
100ns@5v,Min.
150ns@5v,Min.
no deglitch
200ns@5v,Min.
400ns@5v,Min.
no deglitch
20ns@5v,Typical(default)
no deglitch
10
11
Bit 10 (HLFS): Reset to Normal or Green Mode Select Bit
1: CPU is selected as Green mode when a reset occurs.
0: CPU is selected as Normal mode when a reset occurs (default)
Bit 9 (HLP): Power Consumption Selection
1: Low power consumption, apply to working frequency at 8 MHz or below
0: High power consumption, apply to working frequency above 8 MHz
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
137
eKTF5616/08
8-Bit Microcontroller
Bits 8~7 (LVR1~LVR0): Low voltage reset enable bit.
VDD Release Level
LVR1, LVR0
*VDD Reset Level
00
01
10
11
NA (Power on reset) (default)
2.7V
3.8V
4.4V
2.5V
3.6V
4.2V
Note *: If VDD < 2.5V and keep about 5µs, IC will be reset.
If VDD < 3.6V and keep about 5µs, IC will be reset.
If VDD < 4.2V and keep about 5µs, IC will be reset.
Bit 6 (RESETEN): P50//RESET pin selection bit
1: Enable, /RESET pin.
0: Disable, P50 pin (default)
Note *: When P50//RESET is /RESET pin, P50 must set input.
Bit 5 (ENWDT): WDT enable bit
1: Enable
0: Disable (default)
Bit 4 (NRHL): noise rejection high/low pulse defined bit.
1: pulses equal to 8/fc [s] is regarded as signal
0: pulses equal to 32/fc [s] is regarded as signal (default)
Bit 3 (NRE): noise rejection enable bit
1: Disable.
0: Enable (default)
Note *: In Green, Idle, and Sleep modes the noise rejection circuit is always disabled.
Bits 2~0(EEPR2~EEPR0): EEPROM Protect Bit. Each protect status is as follows:
Protect
EEPR2
1
EEPR1
0
EEPR0
1
Disable
Enable
Other Value
138
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
6.18.2 Code Option Register (Word 1)
Word 1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
-
-
FSS
32K
16K
Bit 5
RCM1
High
Low
Mnemonic
1
0
High
Low
Bit 7
-
High
Low
Bit 6
-
High
Low
High
Low
High
Low
High
Low
High
Low
Bit 4
RCM0
High
Low
Bit 3
Bit 2
Bit 1
OSC0
High
Low
Bit 0
RCOUT
High
Mnemonic
1
0
High
Low
High
Low
High
Low
High
Low
Low
Bits 15~14: Not used, set to "0" all the time.
Bits 13 (FSS): Sub-oscillator mode selection bits
1: Fs is 32kHz
0: Fs is 16kHz
Note: WDT frequency is always 16kHz whatever the FSS bits are set.
Bits 12~6: Not used, set to "0" all the time.
Bits 5~4 (RCM1~RCM0): IRC frequency selection.
* Corresponding with control register Bank0 RE RCM1~RCM0
RCM1
RCM0
Frequency (MHz)
0
0
1
1
0
1
0
1
NA
8(default)
12*
16
*OCDS simulation 12MHz need select other frequency first, then set Bank0 RE bit1~0(RCM1~RCM0) change to
12MHz
Bits 3~2: Not used, set to "0" all the time.
Bit 1 (OSC0): Main-oscillator mode selection bits.
Main-Oscillator Mode
IRC (Internal RC oscillator mode) (default)
OSC0
0
RCOUT (P55) acts as I/O pin
IRC (Internal RC oscillator mode)
RCOUT (P55) acts as clock output pin
1
Bit 0 (RCOUT): System Clock Output Enable Bit in IRC mode
1: OSCO pin is open-drain
0: OSCO output instruction cycle time (default)
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
139
eKTF5616/08
8-Bit Microcontroller
6.18.3 Code Option Register (Word 2)
Word 2
Bit 12
SHCLK1 SHCLK0
Bit 15
Bit 14
Bit 13
Bit 11
Bit 10
Bit 9
Bit 8
Mnemonic
-
SHEN
Disable
Enable
Bit 6
-
-
-
-
-
1
0
High
Low
High
Low
Bit 5
-
High
Low
High
Low
Bit 3
-
High
Low
Bit 2
-
High
Low
Bit 1
-
High
Low
Bit 0
-
Bit 7
Bit 4
IRCPSS
Mnemonic
I2COPT
High
VDD
1
0
High
High
Low
High
Low
High
Low
High
Low
High
Low
Int. Vref
Low
Low
Bit 15: Not used, set to "0" all the time.
Bit 14 (SHEN): System hold enable bit.
1: Disable
0: Enable
Bits 13~12 (SHCLK1~SHCLK0): System hold clock selection bits (extra 32kHz source)
SHCLK1~0
System Hold Clock
4 clocks (default)
2 clocks
00
01
10
8 clocks
11
16 clocks
Bit 11~8: Not used, set to "0" all the time.
Bit 7 (IRCPSS): IRC Power Source Selection
1: VDD
0: Internal reference (default)
Bit 6: Not used, set to "0" all the time.
Bit 4 (I2COPT): I2C pin optional bit. It is used to switch the pin position of I2C function.
1: Placed I2C pins in P54 (SDA1) and P55 (SCL1).
0: Placed I2C pins in P52 (SDA0) and P53 (SCL0) (default)
*Corresponding with control register Bank 0 R31 I2COPT
Bits 3~0: Not used, set to "1" all the time.
140
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
6.18.4 Code Option Register (Word 3)
Word 3
Bit 15
-
Bit 14
EFTIM
Heavy
Light
Bit 13
-
Bit 12
-
Bit 11
-
Bit 10
-
Bit 9
-
Bit 8
-
Mnemonic
1
0
High
Low
Bit 7
-
High
Low
Bit 5
ID5
High
Low
Bit 4
ID4
High
Low
Bit 3
ID3
High
Low
Bit 2
ID2
High
Low
Bit 1
ID1
High
Low
Bit 0
ID0
Bit 6
TBWEN
Mnemonic
Enable
Disable
1
0
High
Low
Customer ID
Bits 15: Not used, set to "0" all the time
Bit 14 (EFTIM): Low Pass Filter
1: Pass ~ 10MHz (heavy LPS)
0: Pass ~ 25MHz (light LPS) (default)
Bits 13~7: Not used, set to "0" all the time
Bit 6 (TBWEN): Table write enable bit.
1: Enable.
0: Disable. (default)
Bits 5~0 (ID5~ID0): Customer’s ID Code
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
141
eKTF5616/08
8-Bit Microcontroller
6.19 Instruction Set
Each instruction in the instruction set is a 15-bit word divided into an OP code and one or
more operands. Normally, all instructions are executed within one single instruction cycle
(one instruction consists of 2 oscillator periods), unless the program counter is changed by
instruction "MOV R2, A", "ADD R2, A", or by instructions of arithmetic or logic operation on
R2 (e.g., "SUB R2, A", "BS(C) R2, 6", "CLR R2", etc). In this case, the execution takes
two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
"JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip ("JBS", "JBC", "JZ", "JZA",
"DJZ", "DJZA") commands which were tested to be true, are executed within two
instruction cycles. The instructions that are written to the program counter also take two
instruction cycles.
Moreover, the instruction set has the following features:
1) Every bit of any register can be directly set, cleared, or tested.
2) The I/O register can be considered as general register. That is; the same instruction
can operate on I/O register.
142
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eKTF5616/08
8-Bit Microcontroller
Instruction Set Table:
In the following Instruction Set table, the following symbols are used:
"R" represents a register designator that specifies which one of the registers (including operational
registers and general purpose registers) is to be utilized by the instruction.
"b" represents a bit field designator that selects the value for the bit which is located in the register
"R", and affects operation.
"k" represents an 8 or 10-bit constant or literal value.
Mnemonic
NOP
Operation
No Operation
Status Affected
None
DAA
Decimal Adjust A
C
SLEP
WDTC
ENI
T,P
T,P
None
0 WDT, Stop oscillator
0 WDT
Enable Interrupt
DISI
Disable Interrupt
None
RET
RETI
None
None
[Top of Stack] PC
[Top of Stack] PC, Enable Interrupt
ALL Registers
= Reset Value
Flags*
RESET
Software Device Reset
= Reset Value
TBWR
INT k
Table Writer Start instruction
PC+1 → [SP], k*2 → PC
None
None
Bit Toggle R ; /(R<b>)->R<b>
BTG R,b
None
*Range R5~RA
MOV R,A
CLRA
None
Z
A R
0 A
CLR R
Z
0 R
SUB A,R
Z,C,DC,OV,N
R-A A
SUB R,A
Z,C,DC,OV,N
R-A R
DECA R
DEC R
OR A,R
Z,C,DC,OV,N
Z,C,DC,OV,N
Z,N
R-1 A
R-1 R
A R A
A R R
A & R A
A & R R
A R A
A R R
A + R A
A + R R
OR R,A
Z,N
Z,N
Z,N
Z,N
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
Z,N
Z,C,DC,OV,N
Z,C,DC,OV,N
IC Product Specification (V1.3) 09.10.2019
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143
eKTF5616/08
8-Bit Microcontroller
Mnemonic
Operation
R A
R R
/R A
/R R
Status Affected
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
Z
Z
Z,N
Z,N
Z,C,DC,OV,N
Z,C,DC,OV,N
None
R+1 A
R+1 R
DJZA R
DJZ R
R-1 A, skip if zero
R-1 R, skip if zero
R(n) A(n-1),
R(0) C, C A(7)
R(n) R(n-1),
R(0) C, C R(7)
R(n) A(n+1),
R(7) C, C A(0)
R(n) R(n+1),
R(7) C, C R(0)
R(0-3) A(4-7),
R(4-7) A(0-3)
R(0-3) R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 R(b)
None
RRCA R
RRC R
C, N
C, N
C, N
C,N
RLCA R
RLC R
SWAPA R
None
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
None
None
None
None <Note2>
None <Note3>
None
1 R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 [SP],
(Page, k) PC
(Page, k) PC
k A
None
CALL k
None
JMP k
MOV A,k
None
None
JE R
Compare R with ACC, Skip =
None
None
JGE R
Compare R with ACC, Skip >
JLE R
OR A,k
JE k
Compare R with ACC Skip <
A k A
Compare K with ACC, Skip =
None
Z,N
None
ROM[(TABPTR)] → R, A
A ← program code (low byte) ;
R ← program code (high byte)
A & k A
TBRDA R
AND A,k
None
Z,N
144
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eKTF5616/08
8-Bit Microcontroller
Mnemonic
Operation
Status Affected
Short jump to K if Carry
if C=1 PC+1+offset → PC
*offset = -128≦k≦127
SJC k
None
Short jump to K if Not Carry
if C=0 PC+1+offset → PC
*offset = -128≦k≦127
SJNC k
None
Short jump to K if Zero
if Z=1 PC+1+offset → PC
*offset = -128≦k≦127
SJZ k
XOR A,k
SJNZ k
None
Z,N
A k A
Short jump to K if Not Zero
if Z=0 PC+1+offset → PC
*offset = -128≦k≦127
None
R(n) → A(n-1), R(0) → A(7)
R(n) → R(n-1), R(0) → R(7)
RRA R
RR R
N
N
k A,
[Top of Stack] PC
RETL k
None
R ←→ A
XCH R
RLA R
None
N
R(n) → A(n+1), R(7) → A(0)
R(n) → R(n+1), R(7) → R(0)
RL R
N
SUB A,k
SUBB A,R
Z,C,DC,OV,N
k-A A
R-A-/C → A
Z, C, DC, OV, N
Z, C, DC, OV, N
None
R-A-/C → R
SUBB R,A
SBANK k
GBANK k
KR1(4)
KR1(3:0)
None
Next instruction : k kkkk kkkk kkkk
PC+1[SP], kPC
Next instruction : k kkkk kkkk kkkk
KPC
LCALL k
LJMP k
None
None
TBRD R
ADD A,k
NEG R
ROM[(TABPTR)] R
k+A A
2's complement, /R +1 → R
None
Z,C,DC,OV,N
Z,C,DC,OV,N
Z,C,DC,OV,N
Z,C,DC,OV,N
A+R+C → A
A+R+C → R
ADC A,R
ADC R,A
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
145
eKTF5616/08
8-Bit Microcontroller
7 Absolute Maximum Ratings
Items
Rating
Temperature under bias
Storage temperature
Input voltage
-40C
-65C
to
to
to
to
to
to
85C
150C
Vss-0.3V
Vss-0.3V
2.1V
VDD+0.3V
VDD+0.3V
5.5V
Output voltage
Working Voltage
Working Frequency
DC
16 MHz
8 DC Electrical Characteristics
(Ta=25 C, VDD=5.0V5%, VSS=0V)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
8 MHz,
12 MHz, 16 MHz
Fxt
IRC: VDD to 5 V
F
Hz
IRCE
IRC1
IRC2
IRC3
IIL
Internal RC oscillator error per stage
IRC:VDD to 5V
IRC:VDD to 5V
IRC:VDD to 5V
Input Leakage Current for input pins
±1
8
12
16
0
%
RCM1~RCM0=01
RCM1~RCM0=10
RCM1~RCM0=11
VIN = VDD, VSS
MHz
MHz
MHz
A
-1
1
0.7
VDD
VDD
+0.3V
0.3
VDD
VDD
+0.3V
0.3
VDD
VDD
+0.3V
0.3
VIH1
VIL1
Input High Voltage (Schmitt trigger )
Input Low Voltage (Schmitt trigger )
Ports 5, 6, 7, 8
Ports 5, 6, 7, 8
/RESET
V
-0.3V
V
Input High Threshold Voltage (Schmitt
trigger )
Input Low Threshold Voltage (Schmitt
trigger )
Input High Threshold Voltage (Schmitt
trigger )
Input Low Threshold Voltage (Schmitt
trigger )
0.7
VDD
VIHT1
VILT1
VIHT2
VILT2
IOH1
IOH2
IOH3
IOL1
IOL2
IOL3
IPH
V
/RESET
-0.3V
V
0.7
VDD
TCC,INT
V
TCC,INT
-0.3V
V
VDD
Output High Voltage
(Ports 5, 6, 7, 8)
Output High Voltage (high drvie)
(Ports 5, 6, 7, 8)
Output High Voltage (high drvie)
(Ports 5, 6, 7, 8)
Output Low Voltage
(Ports 5, 6, 7, 8)
Output Low Voltage (high sink)
(Ports 5, 6, 7, 8)
Output Low Voltage (high sink)
(Ports 5, 6, 7, 8)
VOH = VDD-0.1VDD
VOH = VDD-0.1VDD
VOH = VDD-0.3VDD
VOL = GND+0.1VDD
VOL = GND+0.1VDD
VOL = GND+0.3VDD
-3.4
-11
-30
18
mA
mA
mA
mA
mA
mA
A
A
V
34
80
Pull-high active, input pin at
VSS
Pull-low active, input pin at
IO_VDD
Pull-high current
Pull-low current
-43
14
IPL
TA = -40~85℃
LVR1
LVR2
Low voltage reset level
Low voltage reset level
2.2
3.3
2.5
3.6
2.8
3.9
TA = -40~85℃
V
146
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eKTF5616/08
8-Bit Microcontroller
Symbol
Parameter
Condition
Min
Typ
Max
Unit
TA = -40~85℃
LVR3
Low voltage reset level
3.9
4.2
4.5
V
/RESET= 'High', Fm & Fs off
All input and I/O pins at VDD,
output pin floating, WDT
disabled
/RESET= 'High', Fm & Fs off
All input and I/O pins at VDD,
output pin floating, WDT
enabled
/RESET= 'High', Fm off,
Fs=32K/16KHz (IRC type)
output pin floating, WDT
disabled,
/RESET= 'High', Fm off,
Fs=32K/16KHz (IRC type),
output pin floating, WDT
enabled
/RESET= 'High', Fm off,
Fs=32K/16KHz (IRC type),
output pin floating, WDT
disabled
/RESET= 'High', Fm off,
Fs=32K/16KHz (IRC type),
output pin floating, WDT
enabled
Power down current
(Sleep mode)
ISB1
ISB2
ISB3
ISB4
ICC1
ICC2
1
5
A
A
A
A
A
A
Power down current
(Sleep mode)
Power down current
(Idle mode)
6
Power down current
(Idle mode)
6
Operating supply current
(Green mode, CPU only)
15
15
Operating supply current
(Green mode, CPU only)
NOTE
The above parameters are theoretical values only and have not been tested or verified.
Data under the “Min.”, “Typ.”, and “Max.” columns are based on theoretical results at
25C. These data are for design reference only and have not been tested or verified.
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
147
eKTF5616/08
8-Bit Microcontroller
9 AC Electrical Characteristics
(eKTF5616/08 Ta=-40 ~ 85C, VDD=5.5V, VSS=0V)
Symbol
Dclk
Parameter
Conditions
Min.
Typ.
50
-
Max.
55
Unit
%
Input CLK duty cycle
Instruction cycle time
TCC input period
-
45
Tins
RC type
500
DC
-
ns
Ttcc
-
(Tins+20)/N*
-
ns
Tdrh
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
Output pin delay time
-
11.3
2000
11.3
-
16.2
-
21.6
-
ms
ns
Trst
Ta = 25C
Twdt
Tset
Ta = 25C
16.2
0
21.6
ms
ns
-
Thold
Tdelay
-
15
20
50
25
55
ns
Cload=20pF
45
ns
* N: Selected prescaler ratio…
NOTE
The above parameters are theoretical values only and have not been tested or verified.
Data under the “Min.”, “Typ.”, and “Max.” columns are based on theoretical results at
25C. These data are for design reference only and have not been tested or verified.
Data EEPROM Characteristics (VDD=2.1V to 5.5V, VSS=0V, Ta = -40 to 85 C)
Symbol
Parameter
Condition
Min. Typ.
Max.
Unit
-
2
3
ms
Erase/Write cycle time
Tprog
Vdd = 2.1V~ 5.5V
Treten Data Retention
-
-
10
100K
-
-
Years
Cycle
s
Temperature = -40C ~ 85C
Endurance time
Tendu
Program Flash Memory Electrical Characteristics (VDD=2.1V to 5.5V, VSS=0V, Ta = -40 to 85 C)
Symbol
Parameter
Condition
Min. Typ.
Max.
Unit
-
1
1.5
ms
Erase/Write cycle time
Tprog
Vdd = 2.1V~ 5.5V
Treten Data Retention
-
-
10
100K
-
-
Years
Cycle
s
Temperature = -40C ~ 85C
Endurance time
Tendu
148
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(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
AD Characteristics (Vdd = 5.0V, Vss=0V, Ta=25C)
Type
Parameter
Symbol
Test Conditions
Unit
Remark
Min. Typ. Max.
For 5.5v Fs=100KHz,
Fin=1KHz, For 2.5V
Fs=25KHz, Fin=1KHz
Vdd
2.5
5.5
V
VREFT
2.5
Vdd
V
V
Top reference voltage
Operating
Range
VREFT
ΔVREF
-
VREFB
Vss
2.5
-
Bottom reference voltage
Reference Voltage Range
ΔVREF
V1/2VDD
T1/2VDD
I1/2VDD
V
V
1/2*VDD AD channel Input
Voltage
2.475 2.5V 2.525
Vdd=5V
Vdd=5V
Vdd=5V
1/2 *VDD AD
Input
1/2*VDD Warn up time
for ADC sample
2.8
35
4
uS
uA
1/2*VDD Current
Consumption
42
Ivdd
Iref
1.4
10
mA
uA
VREFT= Vdd=5.5V,
SVREFT=”00”,
Fs=100kHz, Fin=1kHz
Current
Consumption
The ADC top reference
voltage is internal Vdd
Ivdd
Iref
0.9
0.5
0.1
10k
mA
mA
uA
VREFT= Vdd=5.5V,
SVREFT=”01”or”10”,
Fs=100kHz, Fin=1kHz
Current
Consumption
The ADC top reference
voltage is external VREF
Standby Current
Isb
Including voltage reference
The external impedance of
analog input channel.
ZAI
SNR
THD
ZAI
ohm
dBc
dBc
dBc
VREFT= Vdd=5.0V,
Fs=100KHz, Fin=1kHz
SNR
THD
SNDR
70
68
Signal-To-Noise Ratio
VREFT= Vdd=5.0V,
Fs=100KHz, Fin=1KHz
-70
Total Harmonic Distortion
VREFT= Vdd=5.0V,
Fs=100KHz, Fin=1kHz
Signal-to-Noise & Distortion
Ratio
SNDR
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149
eKTF5616/08
8-Bit Microcontroller
Type
Parameter
Symbol
Test Conditions
Unit
Remark
Min. Typ. Max.
VREFT= Vdd=5.0V,
Fs=100KHz, Fin=1kHz
Worst Harmonic
WH
-73
dBc
VREFT= Vdd=5.0v,
Fs=100KHz, Fin=1kHz
Spurious Free Dynamic
Range
SFDR
Offset Error
Gain Error
DNL
SFDR
OE
73
dBc
LSB
LSB
LSB
LSB
VREFT= Vdd=5.0v,
Fs=100K Hz
+/-4
+/-8
+/-1
+/-4
VREFT= Vdd=5.0v,
Fs=100kHz
GE
VREFT= Vdd=5.0v,
Fs=100K Hz, Fin=1kHz
DNL
INL
Differential Nonlinearity
Integral Nonlinearity
VREFT= Vdd=5.0v,
Fs=100K Hz, Fin=1kHz
INL
K
SPS
Fs1
Fs2
Vdd=3.0~5.5V, Fin=1kHz
Vdd=2.5~3.0v, Fin=1kHz
100
25
Including sampling &
conversion phase
Conversion Rate
K
SPS
The change in DC output
code from the value with the
LSB supply at the Min. limit to the
value with the supply at its
Max. limit.
VREFT=2.5v,
SVREF=”01”or”10”,
Vdd=2.5V ~ 5.5V, Fs=25K
Hz, Vin=0v ~ 2.5v
Power Supply
Rejection Ratio
PSRR
2
HLVD :
Condition
Parameter
Min.
-40
Typ.
17
Max.
20
unit
A
℃
LVD Enable,VDD=5V
Combine with VREF
ILVD
LVD Operation current
Temp.
25
85
ΔV1
ΔV2
VH,VL tolerance
VH,VL tolerance
VDD = 2.1v~4V
VDD = 4v~5.5V
+/- 0.15
+/- 0.2
100
V
V
VHYST
Hysteresis Voltage
VREF stable time
50
150
80
mV
us
nA
LVD Enable,VDD=5V
LVD disable,VDD=5V
60
IPD
LVD power-down current
52
62
150
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Vref(Vdd = 5.0V, Ta=25C):
IC
Verify
Teststation
symbol
parameter
condition
Min.
Typ.
Max.
5.5
Unit
V
Verify
Vdd
Ivdd
power supply
2.7
Yes
Yes
DC supply
current
Vref=4V,
No load
220
270
uA
Yes
Yes
Yes
Power down
current
Ipd
<0.1
20
uA
us
Yes
Yes
Trim bit and
VREF select
setting time
Tresponse
Response time
10
15
Yes
Yes
time ready for
voltage
reference
warn up
time
50
us
V
Yes
Yes
2.028
2.534
3.041
2.048
2.560
3.072
4.096
2.048
2.560
3.072
4.096
2.068
2.586
3.103
Voltage
reference
output
Vref
Yes
4.055
4.137
Typ.-3%
Typ.-3%
Typ.-3%
Typ.-3%
Typ.+3%
Typ.+3%
Typ.+3%
Typ.+3%
Voltage
reference
output
Temp=-40℃~
85℃
Vref
V
V
Yes
Yes
Yes
Yes
Minimum
power supply
Vdd_min
Vref+0.1 Vref+0.2*
GND
0.1014
0.2028
0.4055
0.1024
0.2048
0.4096
0.1034
0.2068
0.4137
Vref_sensor Vref for Sensor
V
Yes
Yes
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
151
eKTF5616/08
8-Bit Microcontroller
APPENDIX
A Package Type
MCU
Package Type
SOP
Pin Count
28 pins
24 pins
20 pins
16 pins
20 pins
Package Size
300 mil
eKTF5616SOP28
eKTF5616QN24
QFN
4x4x0.8 mm
300 mil
eKTF5616SOP20
eKTF5608SOP16A
eKTF5616SSOP20A
SOP
SOP
150 mil
SSOP
150 mil
These are Green products which do not contain hazardous substances and comply with
the third edition of Sony SS-00259 standard.
The Pb contents are less 100ppm and comply with Sony specifications.
Part No.
Electroplate type
Ingredient (%)
Melting point(°C)
eKTF5616/08 S/J
Pure Tin
Sn: 100%
232°C
Electrical resistivity
11.4
(µ-cm)
Hardness (hv)
Elongation (%)
8~10
>50%
152
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
B Package Information
B.1 eKTF5616SOP28
Symbal
Min
2.370
0.102
0.350
Normal
2.500
Max
2.630
0.300
0.500
A
A1
b
c
E
E1
D
L
L1
e
0.406
0.254(TYP)
7.500
7.410
10.000
17.700
0.678
7.590
10.650
18.100
1.084
10.325
17.900
0.881
1.397
1.194
1.600
1.27(TYP)
θ
0
8
TITLE:
SOP-28L(300MIL)
PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
SO28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-1 eKTF5616 28-pin SOP Package Type
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
153
eKTF5616/08
8-Bit Microcontroller
B.2 eKTF5616QN24
Figure B-2 eKTF5616 24-pin QFN Package Type
154
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
B.3 eKTF5616SOP20
Symbal
Min
2.350
0.102
Normal
Max
2.650
0.300
A
A1
b
0.406(TYP)
c
E
0.230
7.400
0.320
7.600
H
D
L
10.000
12.600
0.630
10.650
12.900
1.100
0.838
e
1.27(TYP)
θ
0
8
b
e
c
TITLE:
SOP-20L(300MIL) PACKAGE
OUTLINE DIMENSION
File :
Edtion: A
SO20
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-3 eKTF5616 20-pin SOP Package Type
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
155
eKTF5616/08
8-Bit Microcontroller
B.4 eKTF5608SOP16A
Symbal
Min
1.350
0.100
1.300
0.330
0.190
3.800
5.800
9.800
0.600
Normal
1.400
Max
1.750
0.250
1.500
0.510
0.250
4.000
6.200
10.000
1.270
A
A1
A2
b
c
E
H
D
L
1.27(TYP)
e
0
8
θ
b
e
c
TITLE:
SOP-16L(150MIL) PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
NSO16
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-4 eKTF5608 16-pin SOP Package Type
156
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
B.5 eKTF5616SSOP20A
Symbol
Min.
Nor.
Max.
1.75
0.25
1.5
A
A1
A2
b
0.1
1.3
0.2
0.2
5.8
3.8
8.55
0.5
0.15
1.4
0.31
0.24
6.2
c
E
6
E1
D
3.9
4
8.65
8.75
0.8
L
1.05 BSC
L1
e
0.635 BSC
ɵ
0˚
8˚
TITLE:
SSOP 20L ( 150 MIL
)
PACKAGE OUTLINE DIMENSION
File :
Edtion:
A
SSOP 20L
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-5 eKTF5616 20-pin SSOP Package Type
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
157
eKTF5616/08
8-Bit Microcontroller
C Ordering and Manufacturing Information
eKTF5616QN24J
Material Type
J: RoHS complied
S: Sony SS- 00259complied
Contact Elan Sales for details
Pin Number
Package Type
QN : QFN
SO: SOP
Product Number
Product Type
F :Flash
Elan8- bit Product
For examp:le
eKTF5616QN24J
is eKTF5616 with Flash program memory ,
package
in24 -pinQFN
‧‧‧‧‧‧‧
Elan Product Number
Batch Number
eKTFaaaa
1041 bbbbbb
Manufacture Date
“YYWW”
YY is year and WW is week
‧‧‧‧‧‧‧
158
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
eKTF5616/08
8-Bit Microcontroller
Ordering Code
KTF5616QN24J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
159
eKTF5616/08
8-Bit Microcontroller
D Quality Assurance and Reliability
Test Category
Solderability
Test Conditions
Remarks
Solder temperature=2455°C, for 5 seconds up to the
stopper using a rosin-type flux
–
Step 1: TCT, 65°C (15 min)~150°C (15 min), 10 cycles
Step 2: Bake at 125°C, TD (endurance)=24 hrs
Step 3: Soak at 30°C/60%，TD (endurance)=192 hrs
Step 4: IR flow 3 cycles
For SMD IC (such as
SOP, QFP, SOJ, etc)
Pre-condition
(Pkg thickness 2.5 mm or
Pkg volume 350 mm3 ----225 5°C)
(Pkg thickness 2.5 mm or
Pkg volume 350 mm3 ----240 5°C)
Temperature cycle test
Pressure cooker test
-65°C (15mins)~150°C (15 min), 200 cycles
–
–
TA =121°C, RH=100%, pressure=2 atm,
TD (endurance)= 96 hrs
High temperature /
High humidity test
TA=85°C, RH=85%，TD (endurance) = 168, 500 hrs
–
–
High-temperature
storage life
TA=150°C, TD (endurance) = 500, 1000 hrs
High-temperature
operating life
TA=125°C, VCC = Max. operating voltage,
TD (endurance) = 168, 500, 1000 hrs
–
–
Latch-up
TA=25°C, VCC = Max. operating voltage, 150mA/20V
ESD (HBM)
TA=25°C, ∣ ± 8KV∣
–
D.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects MCU
malfunction caused by noise or the like. Whenever the MCU attempts to fetch an instruction from a
certain section of ROM, an internal recovery circuit is auto started. If a noise-caused address error is
detected, the MCU will repeat execution of the program until the noise is eliminated. The MCU will
then continue to execute the next program.
160
IC Product Specification (V1.3) 09.10.2019
(This specification is subject to change without prior notice)
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