EM78P153BD14 [ELAN]
8-Bit Microcontroller with OTP ROM;
| 型号： | EM78P153BD14 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller with OTP ROM OTP只读存储器 局域网 微控制器 外围集成电路 |
| 文件： | 总46页 (文件大小：1566K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P153B
8-Bit Microcontroller
with OTP ROM
Product
Specification
DOC. VERSION 1.4
ELAN MICROELECTRONICS CORP.
April 2016
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2016 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road
Hsinchu Science Park
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Elan Information
Technology Group
(U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Fax: +852 2723-7780
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
ELAN Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-Tech Industrial Park
South Area, Shenzhen
CHINA 518057
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elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
5
General Description ......................................................................................1
Features .........................................................................................................1
Pin Assignment..............................................................................................2
Pin Description ..............................................................................................2
Functional Description..................................................................................3
5.1 Operation Registers..........................................................................................4
5.1.1 R0 (Indirect Addressing Register) .......................................................................4
5.1.2 R1 (Timer Clock/Counter) ...................................................................................4
5.1.3 R2 (Program Counter and Stack)........................................................................4
5.1.4 R3 (Status Register)............................................................................................6
5.1.5 R4 (RAM Select Register)...................................................................................6
5.1.6 R5 ~ R6 (Port 5 ~ Port 6) ....................................................................................6
5.1.7 RF (Interrupt Status Register) .............................................................................7
5.1.8 R10 ~ R2F...........................................................................................................7
5.2 Special Function Registers ...............................................................................7
5.2.1 A (Accumulator)...................................................................................................7
5.2.2 CONT (Control Register).....................................................................................7
5.2.3 IOC5 ~ IOC6 (I/O Port Control Register) ............................................................8
5.2.4 IOCB (Pull-Down Control Register).....................................................................8
5.2.5 IOCC (Open-Drain Control Register) ..................................................................9
5.2.6 IOCD (Pull-High Control Register) ......................................................................9
5.2.7 IOCE (WDT Control Register)...........................................................................10
5.2.8 IOCF (Interrupt Mask Register).........................................................................10
5.3 TCC/WDT and Prescaler ................................................................................ 11
5.4 I/O Ports .........................................................................................................12
5.4.1 Usage of Port 6 Input Change Wake-Up / Interrupt Function ...........................14
5.5 Reset and Wake-up........................................................................................................15
5.5.1 Reset .................................................................................................................15
5.5.2 Wake-up and Interrupt Modes Operation Summary .........................................17
5.5.3 Summary of Registers Initialized Values...........................................................18
5.5.4 Status of RST, T, and P of the Status Register..................................................20
5.6 Interrupt ..........................................................................................................21
5.7 Oscillator.........................................................................................................22
5.7.1 Oscillator Modes................................................................................................22
5.7.2 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................22
5.7.3 External RC Oscillator Mode.............................................................................24
5.7.4 Internal RC Oscillator Mode ..............................................................................25
Product Specification (V1.4) 04.25.2016
iii
Contents
5.8 Code Option Register.....................................................................................................25
5.8.1 Code Option Register (Word 0).........................................................................26
5.8.2 Code Option Register (Word 1).........................................................................27
5.8.3 Code Option Register (Word 2).........................................................................28
5.9 Power-On Considerations...............................................................................28
5.10 Programmable Oscillator Set-up Time ............................................................28
5.11 External Power-on Reset Circuits ...................................................................28
5.12 Residue-Voltage Protection.............................................................................29
5.13 Instruction Set.................................................................................................30
6
7
Absolute Maximum Ratings........................................................................33
Electrical Characteristics............................................................................33
7.1 DC Characteristics..........................................................................................33
7.2 AC Characteristics..........................................................................................35
Timing Diagrams .........................................................................................36
8
APPENDIX
A
B
C
Ordering and Manufacturing Information..................................................37
Package Type...............................................................................................39
Package Information ...................................................................................40
Specification Revision History
Doc. Version
Revision Description
Initial Official Release Version
Date
1.0
2012/09/25
Revised the Min./Max. values of theDC Characteristics
(Section 7)
1.1
2012/10/16
1.2
1.3
2013/01/07
2015/10/14
Added DC Charasteristics of LVR
Modified the descriptions related to Sub IRC
1. Modified the package type in the Features section
2. Modified package type in the Pin Assignment section
1.4
2016/04/25
3. Modified Appendix A “Ordering and Manufacturing
Information”
iv
Product Specification (V1.4) 04.25.2016
EM78P153B
8-Bit Microcontroller with OTP ROM
1 General Description
The EM78P153B is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS
technology. The device has an on-chip 102413-bit Electrical One Time Programmable Read Only Memory
(OTP-ROM). It provides three protection bits to prevent intrusion of user’s OTP memory code. Fifteen code
option bits are also available to meet user’s special requirements.
With enhanced OTP-ROM features, the EM78P153B provides a convenient method of developing and
verifying user’s programs. Moreover, this OTP device offers easy and effective program updates with the
use of development and programming tools. You can avail of ELAN’s Writer to easily program your
development codes.
2 Features
CPU Configuration
Drift Rate
Voltage Process
Internal
RC Freq.
1k 13 bits on-chip ROM
32 8 bits on-chip registers (SRAM, general
Temp.
(0~70C)
Total
purpose)
4 MHz
8 MHz
1 MHz
±1.5% ±8%@2.3~5.5V ±2%
±1.5% ±8%@3.0~5.5V ±2%
±1.5% ±8%@2.3~5.5V ±2%
±11.5%
±11.5%
±11.5%
±11.5%
5-level stacks for subroutine nesting
Less than 1.5 mA at 5V / 4 MHz
Typically 15 µA at 3V / 32kHz
455kHz ±1.5% ±8%@2.3~5.5V ±2%
Typically 1 µA during Sleep mode
Peripheral Configuration
I/O Port Configuration
8-bit real time clock / counter (TCC) with selective
signal sources, trigger edges, and overflow
interrupt
2 bidirectional I/O ports : P5, P6
12 I/O pins
Wake-up port : P6
6 Programmable pull-down I/O pins
7 programmable pull-high I/O pins
7 programmable open-drain I/O pins
External interrupt : P60
Power on reset and 3 programmable level voltage
reset
POR: 1.8V (Default), LVR: 4.0, 3.5, 2.7V
2- / 4- clocks per instruction cycle selected by code
option
Operating Voltage Range:
Three Available Interrupts:
TCC overflow interrupt
2.3V ~ 5.5V at 0 ~ 70C (Commercial Grade)
Input-port status changed interrupt (Wake-up from
Sleep mode)
Operating Frequency Range (Base on 2 clocks):
Crystal Mode:
External interrupt
DC ~ 20 MHz / 2clks @ 5V
Special Features
DC ~ 8 MHz / 2clks @ 3V
DC ~ 4 MHz / 2clks @ 2.3V
Programmable free running watchdog timer
Power saving Sleep mode
Selectable oscillation mode
The transient point of system frequency
between HXT and LXT is 400kHz.
ERC Mode:
Programmable prescaler of oscillator set-up time
DC ~ 2MHz / 2clks @ 2.1V
Package Type:
IRC Mode:
14-pin DIP 300mil
: EM78P153BD14
Oscillation Mode: 4 / 8 / 1MHz and 455kHz
Process Deviation: Type: Max. ± 3%
Temperature Deviation: ± 2% (0 ~ 70°C)
14-pin SOP 150mil : EM78P153BSO14
10-pin SSOP 150mil : EM78P153BSS10
NOTE
These are all Green Products which do not contain hazardous substances.
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
1
EM78P153B
8-Bit Microcontroller with OTP ROM
3 Pin Assignment
14-Pin DIP/SOP
10-Pin SSOP
P50
P67
1
2
3
4
5
6
7
14
13
12
11
10
9
P51
P52
P60//INT
VSS
1
2
3
4
5
10
9
P61
P66
P53
P62/TCC
VDD
Vss
P67
8
P63//RST
P65/OSCI/ERCin
P64/OSCO/RCOUT
P63//RST
P60//INT
P61
P66
7
P64/OSCO/RCOUT
P65/OSCI/ERCin
VDD
6
8
P62/TCC
Figure 3-1b EM78P153BSS10
Figure 3-1a EM78P153BD14, EM78P153BSO14
4 Pin Description
Input
Type
Output
Type
Name
Function
Description
P50
P51
P52
P50
P51
P52
ST
CMOS
CMOS
CMOS
Bidirectional I/O pin with programmable pull-low
Bidirectional I/O pin
P53
P53
P60
/INT
P61
ST
ST
ST
ST
Bidirectional I/O pin with programmable pull-high, pull-low,
open-drain and wake-up pin from Sleep mode when the pin
status changes.
P60/INT
External interrupt pin triggered by a falling edge
Bidirectional I/O pin with programmable pull-high, pull-low,
open-drain and wake-up pin from Sleep mode when the pin
status changes.
P61
CMOS
Bidirectional I/O pin with programmable pull- high, pull-low,
open-drain and wake-up pin from Sleep mode when the pin
status changes.
P62
ST
CMOS
P62/TCC
TCC
ST
ST
ST
External Input of real Time Clock / Counter Clock
Input pin and wake-up pin from Sleep mode when the pin
status changes.
P63
P63//RESET
/RESET
External pull-high reset pin, active low.
Bidirectional I/O pin with programmable pull-high,
open-drain and wake-up pin from Sleep mode when the pin
status changes.
P64
ST
CMOS
P64/OSCO/
RCOUT
OSCO
XTAL
Clock output of Crystal/Resonator Oscillator
Clock output of internal RC Oscillator and External RC
Oscillator
RCOUT
CMOS
2
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
(Continuation)
Input
Type
Output
Type
Name
Function
Description
Bidirectional I/O pin with programmable pull-high,
open-drain and wake-up pin from Sleep mode when the pin
status changes.
P65
ST
CMOS
P65/OSCI/
ERCin
OSCI
XTAL
AN
Clock input of Crystal/Resonator Oscillator
External RC input pin
ERCin
Bidirectional I/O pin with programmable pull-high,
open-drain and wake-up pin from Sleep mode when the pin
status changes.
P66
P67
P66
P67
ST
CMOS
VDD
VSS
VDD
VSS
Power
Power
Power supply for chip
Ground for chip
5 Functional Description
Ext.
OSC.
Int.
RC
Ext.
RC
PC
ROM
TCC
WDT
TCC
Oscillation
Generation
5-level
Stack
(13 bit)
Instruction
Register
P5
Reset
P50
Instruction
Decoder
P51
P52
P53
Ext INT
Mux.
ALU
P6
R4
P60
P61
P62
LVR
P63
P64
P65
P66
RAM
Interrupt
Control
Circuit
R3 (Status
Reg.)
P67
ACC
Figure 5-1 EM78P153B Functional Block Diagram
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
3
EM78P153B
8-Bit Microcontroller with OTP ROM
5.1 Operation Registers
5.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the
RAM Select Register (R4).
5.1.2 R1 (Timer Clock/Counter)
Incremented by an external signal edge, which is defined by TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.
Writable and readable as any other registers.
Defined by resetting PAB (CONT-3).
The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
The contents of the prescaler counter will be cleared only when the TCC register is
written with a value.
5.1.3 R2 (Program Counter and Stack)
Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in the following figure.
000H
001H
008H
Reset Vector
PC (A9 ~ A0)
CALL
S/W Interrupt Vector (INT)
H/W Interrupt Vector
RET
RETL
RETI
On-chip Program
Memory
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
3FFH
Figure 5-2 Program Counter Organization
The configuration structure generates 1024 13 bits on-chip OTP ROM addresses
to the relative programming instruction codes. One program page is 1024 words
long.
R2 is set as all "0" when under RESET condition.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows the PC to go to any location within a page.
4
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
"CALL" instruction loads the lower 10 bits of the PC, and then PC + 1 are pushed
onto the stack. Thus, the subroutine entry address can be located anywhere within
a page.
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.
Any instruction written to R2 (e.g., “ADD R2, A”, "MOV R2, A", "BC R2, 6",) will
cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to be cleared. Hence, the
computed jump is limited to the first 256 locations of a page.
All instructions are single instruction cycle (FCLK / 2 or FCLK / 4) except for
instructions that would change the contents of R2. Such instructions will need one
more instruction cycle.
The Data Memory Configuration is as follows:
Address
R Registers
IOC Registers
CONT
(Control Register)
(Indirect Addressing
Register)
00
R0
Reserve
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R1
R2
R3
R4
R5
R6
(TCC Buffer)
Reserve
Reserve
Reserve
Reserve
IOC5
(Program Counter)
(Status Register)
(Ram Select Register)
(Port 5 I/O Data)
(Port 6 I/O Data)
(I/O Port Control Register)
(I/O Port Control Register)
IOC6
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
IOCB
(Pull-Down Control Register)
(Open-Drain Control Register)
(Pull-high Control Register)
(WDT Control Register)
IOCC
IOCD
IOCE
RF
(Interrupt Status Register)
IOCF
(Interrupt Mask Register)
10
:
General Registers
2F
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
5
EM78P153B
8-Bit Microcontroller with OTP ROM
5.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
GP1
GP0
T
P
Z
DC
C
Bit 7 (RST): Bit for reset type
0: Set to “0” if the device wakes up from other reset type
1: Set to “1” if the device wakes up from Sleep mode on a pin change
Bits 6 ~ 5 (GP1 ~ GP0): General-purpose read/write bits
Bit 4 (T):
Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up;
and reset to “0” by WDT time-out.
Bit 3 (P):
Power down bit
Set to “1” during power on or by a "WDTC" command; and reset to “0” by
a "SLEP" command.
Bit 2 (Z):
Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
5.1.5 R4 (RAM Select Register)
Bits 7 ~ 6:
Bits 5 ~ 0:
Not used (Read only). Set to “1” all the time.
Are used to select registers (Address: 0x00 ~ 0x06, 0x0F ~ 0x2F) in
indirect addressing mode. See the table on Data Memory Configuration
in Section 5.1.3, R2 (Program Counter and Stack).
5.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 and R6 are I/O registers.
Only the lower 4 bits of R5 are available.
The upper 4 bits of R5 are fixed to “0”.
P63 is input only.
6
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
5.1.7 RF (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIF
ICIF
TCIF
Bits 7 ~ 3:
Not used. Set to “0” all the time.
Bit 2 (EXIF): External Interrupt Flag. Set by a falling edge on /INT pin, reset by
software.
0: No interrupt occurs
1: Interrupt is requested
Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input changes,
reset by software.
0: No interrupt occurs
1: Interrupt is requested
Bit 0 (TCIF): TCC Overflow Interrupt Flag. Set when TCC overflows, reset by
software.
0: No interrupt occurs
1: Interrupt is requested
NOTE
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
The result of reading RF is the "logic AND" of RF and IOCF.
5.1.8 R10 ~ R2F
These are all 8-bit general-purpose registers.
5.2 Special Function Registers
5.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator; which is not an addressable register.
5.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
/INT
TS
TE
PAB
PSR2
PSR1
PSR0
Bit 7 (GP): General purpose register
Bit 6 (/INT): Interrupt Enable flag
0: Masked by DISI or hardware interrupt
1: Enabled by ENI/RETI instructions
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
7
EM78P153B
8-Bit Microcontroller with OTP ROM
Bit 5 (TS):
Bit 4 (TE):
TCC signal source
0: Internal instruction cycle clock. P62 is a bidirectional I/O pin.
1: Transition on TCC pin
TCC signal edge
0: Increment if the transition from low to high takes place on the TCC pin
1: Increment if the transition from high to low takes place on the TCC pin
Bit 3 (PAB): Prescaler assigned bit
0: TCC
1: WDT
Bits 2 ~ 0 (PSR2 ~ PSR0): TCC / WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
1:2
WDT Rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:2
1:8
1:4
1:16
1:8
1:32
1:16
1:32
1:64
1:128
1:64
1:128
1:256
The CONT register is both readable and writable by instruction “CONTW” and “CONTR”.
5.2.3 IOC5 ~ IOC6 (I/O Port Control Register)
0: Defines the relative I/O pin as output
1: Puts the relative I/O pin into high impedance
Only the lower 4 bits of IOC5 are available to be defined.
IOC5 and IOC6 registers are both readable and writable.
5.2.4 IOCB (Pull-Down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
/PD62
/PD61
/PD60
-
/PD52
/PD51
/PD50
Bit 7:
Not used. Set to “1” all the time.
0: Enable internal pull-down
1: Disable internal pull-down
Bit 6 (/PD62): Control bit used to enable pull-down of the P62 pin.
Bit 5 (/PD61): Control bit used to enable pull-down of the P61 pin.
Bit 4 (/PD60): Control bit used to enable pull-down of the P60 pin.
8
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
Bit 3:
Not used. Set to “1” all the time.
Bit 2 (/PD52): Control bit used to enable pull-down of the P52 pin.
Bit 1 (/PD51): Control bit used to enable pull-down of the P51 pin.
Bit 0 (/PD50): Control bit used to enable pull-down of the P50 pin.
The IOCB Register is both readable and writable.
5.2.5 IOCC (Open-Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD67
OD66
OD65
OD64
-
OD62
OD61
OD60
Bit 7 (OD67): Control bit used to enable open-drain of the P67 pin.
0: Disable open-drain output
1: Enable open-drain output
Bit 6 (OD66): Control bit used to enable open-drain of the P66 pin.
Bit 5 (OD65): Control bit used to enable open-drain of the P65 pin.
Bit 4 (OD64): Control bit used to enable open-drain of the P64 pin.
Bit 3:
Not used. Set to “0” all the time.
Bit 2 (OD62): Control bit used to enable open-drain of the P62 pin.
Bit 1 (OD61): Control bit used to enable open-drain of the P61 pin.
Bit 0 (OD60): Control bit used to enable open-drain of the P60 pin.
The IOCC Register is both readable and writable.
5.2.6 IOCD (Pull-High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH67
/PH66
/PH65
/PH64
-
/PH62
/PH61
/PH60
Bit 7 (/PH67): Control bit is used to enable pull-high of the P67 pin.
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH66): Control bit used to enable pull-high of the P66 pin.
Bit 5 (/PH65): Control bit used to enable pull-high of the P65 pin.
Bit 4 (/PH64): Control bit used to enable pull-high of the P64 pin.
Bit 3:
Not used. Set to “1” all the time.
Bit 2 (/PH62): Control bit used to enable pull-high of the P62 pin.
Bit 1 (/PH61): Control bit used to enable pull-high of the P61 pin.
Bit 0 (/PH60): Control bit used to enable pull-high of the P60 pin.
The IOCD Register is both readable and writable.
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
9
EM78P153B
8-Bit Microcontroller with OTP ROM
5.2.7 IOCE (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
-
-
-
-
-
-
Bit 7 (WDTE): Control bit used to enable the Watchdog timer.
0: Disable WDT
1: Enable WDT
WDTE is both readable and writable.
Bit 6 (EIS):
Control bit used to define the function of the P60 (/INT) pin.
0: P60, bidirectional I/O pin
1: /INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC6) must be set to "1."
When EIS is "0," the path of the /INT is masked. When EIS is "1," the
status of the /INT pin can also be read through Port 6 (R6).
See Figure 5-4b under Section 5.4, I/O Ports; for reference.
EIS is both readable and writable.
Bits 5 ~ 0:
Not used. Set to “0” all the time.
5.2.8 IOCF (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIE
ICIE
TCIE
Bits 7 ~ 3:
Not used. Set to “1” all the time.
Individual interrupt is enabled by setting its associated control bit in the
IOCF to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. Refer to Figure 5-6 in Section 5.6, Interrupt.
Bit 2 (EXIE): EXIF interrupt enable bit
0: Disable EXIF interrupt
1: Enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: Disable ICIF interrupt
1: Enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit
0: Disable TCIF interrupt
1: Enable TCIF interrupt
The IOCF register is both readable and writable.
10
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
5.3 TCC/WDT and Prescaler
An 8-bit counter is provided as prescaler for the TCC or WDT. The prescaler is only
available for either TCC or WDT at a time. The PAB bit of the CONT register is used to
determine the prescaler assignment. The PSR0 ~ PSR2 bits determine the ratio. The
prescaler is cleared each time an instruction is written to TCC under TCC mode. The
WDT and prescaler, when assigned to WDT mode, are cleared by the “WDTC” or
“SLEP” instructions. Figure 5-3 below depicts the circuit diagram of TCC/WDT.
R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be an internal or
external clock input (edge selectable from TCC pin). If the TCC signal source is
from an internal clock, TCC will be incremented by 1 at every instruction cycle
(without prescaler). Refer to the following figure (Figure 5-3) to determine whether
CLK = FOSC/2 or CLK = FOSC/4 is used. It will depend on the status of the Code
Option bit CLK. CLK = FOSC/2 is used if CLK bit is "0", and CLK = FOSC/4 is used
if CLK bit is "1". If the TCC signal source is from an external clock input, TCC is
incremented by 1 at every falling edge or rising edge of the TCC pin.
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep
running even when the oscillator driver has been turned off (i.e., in Sleep mode).
During normal operation or Sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal mode
by software programming. Refer to WDTE bit of the IOCE register (Section 5.2.7).
Without prescaler, the WDT time-out period is approximately 23.5ms1 (default).
Data Bus
CLK (FOSC / 2 or FOSC / 4)
0
1
M
U
X
M
U
X
TCC
Pin
SYNC
2 cycles
TCC (R1)
0
1
TE
TS
PAB
TCC Overflow Interrupt
0
1
M
U
X
8-bit Counter
WDT
PSR0~PSR2
PAB
8-to-1 MUX
PAB
0
1
WDTE
(in IOCE)
MUX
WDT Time Out
Figure 5-3 TCC and WDT Block Diagram
1
°
VDD = 5V, set up time period = 23.5ms ± 30% at 25 C
°
VDD = 3V, set up time period = 26ms ± 30% at 25 C
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
11
EM78P153B
8-Bit Microcontroller with OTP ROM
5.4 I/O Ports
The I/O registers, Port 5 and Port 6 are both bidirectional tri-state I/O ports. Port 6 can
be pulled-high internally by software except for P63 pin. In addition, Port 6 can also
have open-drain output by software except for P63 pin. Input status change interrupt
(or Wake-up) function is also available from Port 6. Pins P50 ~ P52 and P60 ~ P62 can
be pulled-down by software. Each I/O pin can be defined as "input" or "output" pin by
the I/O control register (IOC5 ~ IOC6) except for P63 pin. The I/O registers and I/O
control registers are both readable and writable. The I/O interface circuits for Port 5
and Port 6 are shown in Figures 5-4a to 5-4d below.
PCRD
P
Q
D
R
PCWR
PDWR
CLK
_
C
L
Q
P
R
IOD
Port
Q
D
CLK
_
Q
C
L
PDRD
0
1
M
U
X
NOTE: Pull-down is not shown in the figure.
Figure 5-4a I/O Port and I/O Control Register Circuit for Port 5
12
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
PCRD
P
Q
_
D
R
PCWR
PDWR
CLK
Q C
L
IOD
P
Q
Port
D
R
_
CLK
Bit 6 of
IOCE
Q C
L
0
1
P
M
U
X
D
Q
_
Q
R
CLK
C
L
T10
PDRD
P
D
Q
R
CLK
C
_
Q
L
NOTE: Pull-high (down) and open-drain are not shown in the figure.
Figure 5-4b I/O Port and I/O Control Register Circuit for P60 (/INT)
P
Q
_
Q
D
D
R
CLK
PCWR
PDWR
C
L
IOD
P
R
Q
PORT
_
Q
CLK
C
L
0
1
M
U
X
TIN
PDRD
P
R
D
Q
CLK
_
Q
C
L
NOTE: Pull-high (down) and open-drain are not shown in the figure.
Figure 5-4c I/O Port and I/O Control Register Circuit for P61, P62, and P64~P67
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
13
EM78P153B
8-Bit Microcontroller with OTP ROM
ICIE
P
Q
D
R
CLK
Interrupt
_
Q
C
L
ICIF
ENI Instruction
P
R
P60
D
Q
P61
P62
P63
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
P64
P65
P66
C
L
P67
DISI Instruction
Interrupt
(Wake-up from
SLEEP)
/SLEP
Next Instruction
(Wake-up from
SLEEP)
Figure 5-4d Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-Up
5.4.1 Usage of Port 6 Input Change Wake-Up / Interrupt Function
1. Wake-up from Input Status Change
a) Before SLEEP:
1) Disable WDT
2) Read I/O Port 6 (MOV R6,R6)
3) Execute "ENI" or "DISI"
4) Enable Interrupt (Set IOCF.1)
5) Execute "SLEP" instruction
b) After Wake-up:
1) IF "ENI" Interrupt vector (008H)
2) IF "DISI" Next instruction
2. Input Status Change Interrupt
1) Read I/O Port 6 (MOV R6, R6)
2) Execute "ENI"
3) Enable Interrupt (Set IOCF.1)
4) IF Port 6 Change (Interrupt)
Interrupt Vector (008H)
14
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
5.5 Reset and Wake-up
5.5.1 Reset
A Reset is initiated by one of the following events:
1) Power-on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
4) Low Voltage Reset
The device is kept under reset condition for a period of approximately 23.5ms2 (one
oscillator start-up timer period) after a reset is detected. Once a Reset occurs, the
following functions are performed:
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0."
All I/O port pins are configured as input mode (high-impedance state)
The Watchdog Timer and prescaler are cleared.
When power is switched on, the upper 3 bits of R3 are cleared.
The bits of the CONT register are set to all "1" except for Bit 6 (INT flag).
The bits of the IOCB register are set to all "1".
The IOCC register is cleared.
The bits of the IOCD register are set to all "1."
Bit 7 of the IOCE register is set to "1" and Bit 6 is cleared.
Bits 0 ~ 2 of RF and Bits 0 ~ 2 of IOCF registers are cleared.
The Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering Sleep mode, WDT (if enabled) is cleared but keeps on running.
The controller can be awakened by:
1) External reset input on /RESET pin
2) WDT time-out (if enabled)
3) Port 6 Input Status changes (if enabled)
2
°
VDD = 5V, set up time period = 23.5ms ± 30% at 25 C
°
VDD = 3V, set up time period = 26ms ± 30% at 25 C
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
15
EM78P153B
8-Bit Microcontroller with OTP ROM
The first two cases will cause the EM78P153B to reset. The T and P flags of R3 are
used to determine the source of the reset (Wake-up). The last case is considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a Wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from Address 008H after Wake-up. If DISI is executed before SLEP, the
operation will restart from the succeeding instruction right next to SLEP after a
Wake-up.
Only one of Cases 2 and 3 can be enabled before going into the Sleep mode. That is;
a] If Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be
disabled by software. Hence, the EM78P153B can be awakened only by Case 1 or
Case 3.
b) If WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be
disabled. Hence, the EM78P153B can be awakened only by Case 1 or Case 2.
Refer to Section 5.6, Interrupt for further details.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78P153B (Case [a]
above), the following instructions must be executed before SLEP:
MOV A, @xxxx1110b
; Select the WDT prescaler, it must be
; set over 1:1
CONTW
WDTC
; Clear WDT and prescaler
; Disable WDT
MOV A, @0xxxxxxxb
IOW RE
MOV R6, R6
MOV A, @00000x1xb
IOW RF
; Read Port 6
; Enable Port 6 input change interrupt
ENI (or DISI)
SLEP
; Enable (or disable) global interrupt
; Sleep
NOTE
1. After waking up from Sleep mode, the WDT is automatically enabled. WDT enable
/ disable operation after waking up from Sleep mode must be appropriately defined
in the software.
2. To avoid a reset from occurring when Port 6 Input Status Change Interrupt enters
into an interrupt vector or is used to Wake-up the MCU, the WDT prescaler must be
set above the 1:1 ratio.
9
16
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
5.5.2 Wake-up and Interrupt Modes Operation Summary
The controller can be awakened from sleep mode and idle mode. The wake-up signals
are listed as follows.
Sleep Mode
DISI ENI
Normal Mode
ENI
Wake-up
Signal
Condition
Signal
DISI
EXIE = 0
INT is invalid
External INT
Wake-up is invalid
INT +
INT Vector
EXIE = 1
Next Inst.
Next Inst.
ENWDT = 1
ICIE = 0
Wake-up is invalid
INT is invalid
ENWDT = 1
ICIE = 1
Wake-up is Wake-up +
INT +
INT Vector
invalid
INT Vector
Port 6
Pin change
ENWDT = 0
ICIE = 0
Wake-up is invalid
INT is invalid
WDTEN = 0
ICIE = 1
Wake-up is Wake up +
INT +
INT Vector
Next Inst.
Next Inst.
invalid
INT Vector
TCIE = 0
TCIE = 1
INT is invalid
TCC
Overflow
Wake-up is invalid
INT +
INT Vector
WDT Timeout
WDTE = 1
Wake up + Reset
Wake up + Reset
Reset
Reset
Low Voltage Reset
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
17
EM78P153B
8-Bit Microcontroller with OTP ROM
5.5.3 Summary of Registers Initialized Values
Legend: : Not used U: Unknown or don’t care P: Previous value before reset
Addr. Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
-
U
P
P
-
Power-on
R0
000
(IAR)
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
R1
001
(TCC)
/RESET and WDT
Wake-up from Pin Change
Bit Name
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R2
002
(PC)
/RESET and WDT
Wake-up from Pin Change
Bit Name
Jump to Address 0x08 or continue to execute next instruction
RST
GP1
0
GP0
0
T
1
P
1
Z
U
DC
U
C
U
Power-on
0
0
1
R3
003
(SR)
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
P
P
P
*
*
*
*
P
P
-
P
P
P
-
-
-
-
-
Power-on
1
1
1
1
U
P
P
U
P
P
U
P
U
U
U
R4
004
(RSR)
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
P
P
1
1
P
P
P
P
P53
1
P52
1
P51
1
P50
1
Power-on
1
1
1
1
005
006
00F
P5
P6
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
P
P67
1
P
P
P66
1
P
P
P65
1
P
P
P64
1
P
P
P
P
P
P
P
P
P63
1
P62
1
P61
1
P60
1
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
EXIF
0
ICIF
0
TCIF
0
Power-on
0
0
0
0
0
RF
(ISR)
/RESET and WDT
Wake-up from Pin Change
0
0
0
0
0
0
0
0
0
0
0
0
0
P
N
P
* Refer to tables provided in Sections 5.5.4 “Status of RST, T and P of the Status Register”
18
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
(Continuation)
Addr. Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
TS
1
Bit 4
TE
1
Bit 3
PAB
1
Bit 2
Bit 1
Bit 0
/INT
0
PSR2 PSR1 PSR0
Power-on
1
1
1
1
1
1
1
N/A CONT
005 IOC5
006 IOC6
00B IOCB
00C IOCC
00D IOCD
00E IOCE
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
0
1
1
1
P
0
P
P
P
C53
1
P
P
P
C52
1
C51
1
C50
1
Power-on
0
0
0
0
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
0
0
0
1
1
1
1
0
0
0
0
P
C63
1
P
P
P
C67
1
C66
1
C65
1
C64
1
C62
1
C61
1
C60
1
Power-on
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
1
1
1
1
1
1
1
P
P
P
P
P
x
P
P
P
/PD66 /PD65 /PD64
/PD52 /PD51 /PD50
Power-on
1
1
1
P
1
1
P
1
1
P
1
1
1
P
1
1
P
1
1
P
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
1
P
P
OD67 OD66 OD65 OD64
OD62 OD61 OD60
Power-on
0
0
P
0
0
P
0
0
P
0
0
P
0
0
0
P
0
0
P
0
0
P
/RESET and WDT
Wake-up from Pin Change
Bit Name
0
P
/PH67 /PH66 /PH65 /PH64
/PH62 /PH61 /PH60
Power-on
1
1
P
1
1
P
1
1
P
1
1
1
1
1
1
-
1
1
P
1
1
1
1
1
1
-
1
1
1
1
1
1
1
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
P
P
P
P
WDTE EIS
Power-on
1
1
1
1
1
1
-
0
0
P
1
1
1
-
1
1
1
1
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
1
1
1
1
1
1
1
EXIE
0
ICIE
0
TCIE
0
Power-on
1
00F IOCF
010 R10
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
0
0
0
1
P
P
-
P
-
-
-
Power-on
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
U
P
P
U
P
/RESET and WDT
Wake-up from Pin Change
02F R2F
P
P
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
19
EM78P153B
8-Bit Microcontroller with OTP ROM
5.5.4 Status of RST, T, and P of the Status Register
A Reset condition is initiated by the following events:
1) A power-on condition
2) A high-low-high pulse on /RESET pin
3) Watchdog timer time-out
Values of RST, T, and P after a Reset:
The values of T and P as listed in the following table are used to check how the
processor wakes up.
Reset Type
RST
T
1
P
1
Power on
0
0
0
0
0
1
/RESET during Operating mode
/RESET wake-up during Sleep mode
WDT during Operating mode
*P
1
*P
0
0
*P
0
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
1
0
* P: Previous status before reset
Status of T and P being Affected by Events:
The following table shows the events that may affect the status of T and P.
Event
RST
0
T
1
1
0
1
1
P
1
Power on
WDTC instruction
WDT time-out
SLEP instruction
*P
0
1
*P
0
*P
1
Wake-up on pin change during Sleep mode
0
* P: Previous status before reset
VDD
D
CLK
Q
CLK
Oscillator
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT
Setup Time
RESET
Timeout
/RESET
Figure 5-5 Controller Reset Block Diagram
20
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
5.6 Interrupt
The EM78P153B has three falling-edge interrupts as listed below:
1) TCC overflow interrupt
2) Port 6 Input Status Change Interrupt
3) External interrupt [(P60, /INT) pin]
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV
R6, R6") is necessary. Each pin of Port 6 will have this feature if its status changes.
Any pin configured as output or P60 pin that is configured as /INT is excluded from this
function. The Port 6 Input Status Change Interrupt can wake up the EM78P153B from
Sleep mode if Port 6 is enabled prior to going into Sleep mode by executing SLEP
instruction. When the chip wakes-up, the controller will continue to execute the
program in-line if the global interrupt is disabled. If the global interrupt is enabled, it will
branch to the interrupt Vector 008H.
RF is the Interrupt Status Register that records the interrupt requests in the relative
flags/bits. IOCF is an Interrupt Mask Register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one enabled interrupt
occurs, the next instruction will be fetched from Address 008H. Once in the interrupt
service routine, the source of an interrupt can be determined by polling the flag bits in
RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt
service routine before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to Figure 5-6 below). The RETI instruction ends the
interrupt routine and enables the global interrupt (the execution of ENI).
When an interrupt is generated by the INT instruction (if enabled), the next instruction
will be fetched from Address 001H.
VCC
P
IRQn
D
Q
_
Q
R
/IRQn
CLK
INT
C
IRQm
RFRD
L
RF
ENI/DISI
P
IOD
Q
_
Q
D
R
CLK
C
IOCFWR
L
IOCF
/RESET
IOCFRD
RFWR
Figure 5-6 Interrupt Input Circuit
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
21
EM78P153B
8-Bit Microcontroller with OTP ROM
5.7 Oscillator
5.7.1 Oscillator Modes
The EM78P153B can be operated in four different oscillator modes, such as External
RC oscillator mode (ERC), Internal RC oscillator mode (IRC), High Crystal oscillator
mode (HXT), and Low Crystal oscillator mode (LXT). The desired mode can be
selected by programming OSC1 ~ OSC0 in the Code Option register. Table below
describes how these four oscillator modes are defined.
Oscillator Modes Defined by OSC
Oscillator Modes
RCOUT OSC1 OSC0
LXT (Low crystal oscillator mode, Freq. range is over 400kHz)
HXT (High crystal oscillator mode, Freq. range is above 400kHz)
ERC1 (External RC oscillator mode); P64/RCOUT act as P64
ERC1 (External RC oscillator mode); P64/RCOUT act as RCOUT
IRC2 (Internal RC oscillator mode); P64/RCOUT act as P64
IRC2 (Internal RC oscillator mode); P64/RCOUT act as RCOUT
x
x
0
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1 Under ERC mode, ERCin is used as oscillator pin. RCOUT/P64 is defined by Code Option
Word 1 Bit 3.
2 In IRC mode, P64 is normal I/O pin. RCOUT/P64 is defined by Code Option Word 1 Bit 3.
The maximum operating frequency of the crystal/resonator under different VDD is
listed below.
Summary of Maximum Operating Speeds
Conditions
VDD
2.3
Max Freq. (MHz)
4.0
8.0
Two cycles with two clocks
3.0
5.0
20.0
5.7.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P153B can be
driven by an external clock
OSCI
Ext. Clock
signal through the OSCI pin
as shown in the figure at
OSCO
right.
EM78P153B
Figure 5-7 Circuit for External Clock Input
22
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
In most applications, Pin OSCI and
Pin OSCO can be connected with a
crystal or ceramic resonator to
generate oscillation. Figure 5-8a
depicts such a circuit. The same
thing applies whether it is in the
HXT mode or in the LXT mode.
C1
OSCI
EM78P153B
OSCO
Crystal
RS
C2
In Figure 5-8b, when the connected
resonator in OSCI and OSCO is
used in applications, the 1 M R1
needs to be shunted with a
resonator.
Figure 5-8a Circuit for Crystal/Resonator
C1
OSCI
Resonator
EM78P153B
R1
OSCO
C2
Figure 5-8b Circuit for Crystal/Resonator
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attributes, refer to its specification for appropriate values of C1
and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency
mode.
Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode
Frequency
455kHz
C1 (pF)
100 ~ 150
20 ~ 40
10 ~ 30
25
C2 (pF)
100 ~ 150
20 ~ 40
10 ~ 30
15
Ceramic Resonators
HXT
2.0 MHz
4.0 MHz
32768Hz
100kHz
LXT
HXT
25
25
200kHz
25
25
Crystal Oscillator
455kHz
20 ~ 40
15 ~ 30
15
20 ~ 150
15 ~ 30
15
1.0 MHz
2.0 MHz
4.0 MHz
15
15
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
23
EM78P153B
8-Bit Microcontroller with OTP ROM
5.7.3 External RC Oscillator Mode
For some applications that do not
require a very precise timing
Vcc
calculation, the RC oscillator (right
figure) offers a cost-effective oscillator
configuration. Nevertheless, it should
be noted that the frequency of the RC
oscillator is influenced by the supply
voltage, the values of the resistor
(REXT), the capacitor (CEXT), and
even by the operation temperature.
Moreover, the frequency also changes
slightly from one chip to another due to
REXT
OSCI
CEXT
EM78P153B
Figure 5-9 External RC Oscillator Mode Circuit
manufacturing process variations. In order to maintain a stable system frequency, the
value of the CEXT should not be lesser than 20pF, and that of REXT should not be
greater than 1 M. If they cannot be kept under this range, the frequency can be easily
affected by noise, humidity, and leakage.
The smaller the REXT value in the RC oscillator, the faster its frequency will be.
However, a very low REXT value of less than 3.3k, for instance 1 k; the oscillator will
become unstable as the NMOS will not be able to correctly discharge the capacitance
current.
Based on the above reason, it must be kept in mind that the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, and
the PCB layout, may affect the system frequency.
RC Oscillator Frequencies
Average FOSC
Average FOSC
CEXT
REXT
5V, 25C
3V, 25C
3.3k
2.064MHz
1.403MHz
750kHz
1.901MHz
1.316MHz
719.7kHz
81.33kHz
615.1MHz
414.3kHz
219.8kHz
23.96kHz
245.3kHz
163.0kHz
86.14kHz
9.255kHz
5.1k
10k
20pF
100k
3.3k
5.1k
10k
81.45kHz
647.3kHz
430.8kHz
225.8kHz
23.88kHz
256.6kHz
169.5kHz
88.53kHz
9.283kHz
100pF
300pF
100k
3.3k
5.1k
10k
100k
NOTE
1) These are measured in DIP packages
2) The values are for design reference only
3) The frequency drift is 30%
24
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
5.7.4 Internal RC Oscillator Mode
EM78P153B offers a versatile internal RC mode with default frequency value of 4 MHz.
The Internal RC oscillator mode has other frequencies (1 MHz, 8 MHz, and 455kHz)
that can be set by Code Option (Word 1), RCM1, and RCM0. All these four main
frequencies can be calibrated by programming the Option Bits C0 ~ C4. The table
below describes the EM78P153B internal RC drift with variation of voltage,
temperature, and process.
Internal RC Drift Rate (TA = 25°C, VDD = 5V, VSS = 0V)
Drift Rate
Internal RC Freq.
Temp. (0°C ~ 70°C)
± 1.5%
Voltage
Process
± 2%
Total
4 MHz
8 MHz
1 MHz
455kHz
± 8% @ 2.3V ~ 5.5V
± 8% @ 3.0V ~ 5.5V
± 8% @ 2.3V ~ 5.5V
± 8% @ 4.0V ~ 5.5V
± 11.5%
± 11.5%
± 11.5%
± 11.5%
± 1.5%
± 2%
± 1.5%
± 2%
± 1.5%
± 2%
NOTE: These are theoretical values provided for reference only. Actual values may vary
depending on the actual process.
5.8 Code Option Register
The EM78P153B has a Code Option word that is not part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register Arrangement Distribution:
Word 0
Word 1
Word 2
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
25
EM78P153B
8-Bit Microcontroller with OTP ROM
5.8.1 Code Option Register (Word 0)
Word 0
Bit
Bit 12
Bit 11
Bit 10 Bit 9 Bit 8 Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2~0
Mnemonic RESETEN ENWDT
CLKS LVR1 LVR0
Disable Disable 4 clocks High High
Enable Enable 2 clocks Low Low
WDTPS1 WDTPS0
Protect
Disable
Enable
1
0
High
Low
High
Low
Bit 12 (RESETEN): Define Pin 63 as a Reset pin
0: /RESET enable
1: /RESET disable
Bit 11 (ENWDT): Watchdog timer enable bit
0: Enable
1: Disable
Bit 10 (CLKS):
Instruction period option bit.
0: Two oscillator periods
1: Four oscillator periods
Refer to the Instruction Set (Section 5.13).
Bits 9 ~ 8 (LVR1 ~ LVR0): Low Voltage Reset control bits
VDD Reset Level
LVR1, LVR0
VDD Release Level
11
10
01
00
NA (Power-on Reset) (default)
2.7V
3.5V
4.0V
2.9V
3.7V
4.0V
Bit 7:
Not used. Set to “1” all the time.
Bits 6 ~ 5 (WDTPS1 ~ WDTPS0): WDT Time-out Period of device bits.
WDT Time-out Period for Device Programming
WDTPS1
WDTPS0
*WDT Time-out Period
1
1
0
0
1
0
1
0
23.5 ms
5.9 ms
376 ms
94 ms
*These are values tested in Laboratory.
Actual values may vary depending on the actual process
Bits 4 ~ 3:
Not used. Set to “1” all the time
Bits 2 ~ 0 (Protect): Protect Bits. Each protect status is as follows:
Protect Bits
Protect
0
1
Enable
Disable (Default)
26
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
5.8.2 Code Option Register (Word 1)
Word 1
Bit
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2 Bit 1 Bit 0
Mnemonic
C4
C3
C2
C1
C0 RCM1 RCM0
RCOUT OSC1 OSC0
1
0
High High High High High High High
Low Low Low Low Low Low Low
High
Low
High High
Low Low
Bit 12: Not used. Set to “1” all the time.
Bits 11 ~ 7 (C4 ~ C0): Internal RC mode Calibration bits. These bits must always be
set to “1” only (Auto calibration).
Bits 6 ~ 5 (RCM1, RCM0): RC mode selection bits
RCM 1
RCM 0
* Frequency (MHz)
1
1
0
0
1
0
1
0
4
8
1
455kHz
*These are theoretical values provided for reference only.
Actual values may vary depending on the actual process
Bit 4: Not used. Set to “1”all the time.
Bit 3 (RCOUT Selection bit of oscillator output or I/O port (see table below)
0: P64
1: OSCO
Bits 2 ~ 1 (OSC1 and OSC0): Oscillation mode select bits
Oscillation modes selection:
Oscillation Modes
RCOUT OSC1 OSC0
LXT (Low crystal oscillator mode, Freq. range is over 400kHz)
HXT (High crystal oscillator mode, Freq. range is above 400kHz)
ERC1 (External RC oscillator mode); P64/RCOUT acts as P64
ERC1 (External RC oscillator mode); P64/RCOUT acts as RCOUT
IRC2 (Internal RC oscillator mode); P64/RCOUT acts as P64
IRC2 (Internal RC oscillator mode); P64/RCOUT acts as RCOUT
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
1 In ERC mode, ERCin is used as oscillator pin. RCOUT/P64 is defined by Code Option Word 1
Bit 3 ~ Bit 1.
2 In IRC mode, P64 is normal I/O pin. RCOUT/P64 is defined by Code Option Word 1 Bit 3 ~ Bit 1.
Bit 0: Not used. Set to “1” all the time.
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
27
EM78P153B
8-Bit Microcontroller with OTP ROM
5.8.3 Code Option Register (Word 2)
Word 2
Bit
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic ID12
ID11
High
Low
ID10
High High High High High High High High High High High
Low Low Low Low Low Low Low Low Low Low Low
ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
1
0
High
Low
Bits 12 ~ 0: Bits 12 ~ 0 of Customer’s ID code
5.9 Power-On Considerations
Any microcontroller is not guaranteed to start operating properly before the power
supply stabilizes at steady state. Under customer application, when power is OFF,
VDD must drop to below 1.8V and remains OFF for 10µs before power can be switched
ON again. In this way, the EM78P153B will reset and operate normally. The extra
external reset circuit will work well if VDD can rise at a very fast speed (50ms or less).
However, under critical applications, extra devices are still required to assist in solving
the power-up problems.
5.10 Programmable Oscillator Set-up Time
The Code Option Register Words (Word 0/1/2) contains SUT0 and SUT1 which are
used to define the oscillator set-up time. Theoretically, its range is from 6.5ms to
104ms. For most of the crystal or ceramic resonators, the lower the operation
frequency is, the longer the set-up time may be required.
5.11 External Power-on Reset Circuit
The circuitry in the figure at
right implements an external
VDD
RC to produce the reset
R
/RESET
pulse. The pulse width
D
(time constant) should be
EM78P153B
kept long enough for VDD to
Rin
C
reach minimum operation
voltage. This circuit is used
when the power supply has
a slow rise time.
Figure 5-10 External Power-up Reset Circuit
Since the current leakage from the /RESET pin is 5µA, it is recommended that R
should not be greater than 40k in order for the /RESET pin voltage to remain and kept
at below 0.2V. The diode (D) functions as a short circuit at the instant of power down.
The capacitor C will discharge rapidly and fully. The current-limited resistor (Rin), will
prevent high current or ESD (electrostatic discharge) from flowing into /RESET pin.
28
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
5.12 Residue-Voltage Protection
When the battery is replaced, the device power (VDD) is cut off but residue-voltage
remains. The residue-voltage may trips below the minimum VDD, but not to zero. This
condition may cause a poor power-on reset. The following figures illustrate two
recommended methods on how to accomplish a proper residue-voltage protection
circuit for the EM78P153B.
Vdd
VDD
33K
EM78P153B
/RESET
Q1
10K
100K
1N4684
Figure 5-11a Residue Voltage Protection Circuit 1
Vdd
VDD
R1
EM78P153B
Q1
/RESET
R2
R3
Figure 5-11b Residue Voltage Protection Circuit 2
NOTE
Circuits should be designed to ensure that the voltage of the /RESET pin is larger than
VIH (min).
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
29
EM78P153B
8-Bit Microcontroller with OTP ROM
5.13 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of two oscillator periods), unless the program counter is
changed by instructions "MOV R2, A", "ADD R2, A", or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2, A", "BS(C) R2, 6", "CLR R2", etc.). In this case,
the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
A) Modify one instruction cycle to consist of four oscillator periods.
B) "JMP," "CALL," "RET," "RETL," "RETI," or the conditional skip ("JBS", "JBC", "JZ",
"JZA", "DJZ”, "DJZA") commands which were tested to be true, are executed within
two instruction cycles. The instructions that are written to the program counter also
take two instruction cycles.
Case A is selected by the Code Option bit, called CLK. One instruction cycle consists
of two oscillator clocks if CLK is low; and four oscillator clocks if CLK is high.
Note that once the four oscillator periods within one instruction cycle is selected as in
Case A, the internal clock source to TCC should be CLK = FOSC/4, instead of FOSC/2.
Moreover, the Instruction Set also offers the following features:
1) Every bit of any register can be set, cleared, or tested directly.
2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
30
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
Instruction Set Table:
The following symbols are used in the Instruction Set table:
“R” Register designator that specifies which one of the registers (including operation and
general purpose registers) is to be utilized by the instruction.
“b” Bit field designator that selects the value for the bit located in the register R and which
affects the operation.
“k” 8 or 10-bit constant or literal value
Mnemonic
NOP
Operation
Status Affected
No Operation
None
C
DAA
CONTW
SLEP
WDTC
IOW
Decimal Adjust A
A CONT
0 WDT, Stop oscillator
0 WDT
None
T, P
T, P
*
R
A IOCR
None
ENI
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
[Top of Stack] PC, Enable Interrupt
CONT A
IOCR A
None
None
None
None
None
DISI
RET
RETI
CONTR
IOR
*
R
None
MOV
CLRA
CLR
R, A
A R
None
0 A
Z
R
0 R
Z
SUB
SUB
DECA
DEC
OR
A, R
R, A
R
R - A A
Z, C, DC
R - A R
Z, C, DC
R - 1 A
Z
R
R - 1 R
Z
A, R
R, A
A, R
R, A
A, R
R, A
A, R
R, A
A, R
R, R
A R A
Z
OR
A R R
Z
AND
AND
XOR
XOR
ADD
ADD
MOV
MOV
A & R A
Z
A & R R
Z
A R A
Z
A R R
Z
A + R A
Z, C, DC
A + R R
Z, C, DC
R A
Z
Z
R R
*
This instruction is applicable to IOC5~IOC6, IOCB ~ IOCF only.
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
31
EM78P153B
8-Bit Microcontroller with OTP ROM
(Continuation)
Mnemonic
Operation
Status Affected
COMA
COM
INCA
INC
R
R
R
R
R
R
/R A
Z
Z
/R R
R + 1 A
R + 1 R
Z
Z
DJZA
DJZ
R - 1 A, skip if zero
R - 1 R, skip if zero
None
None
R(n) A(n - 1),
R(0) C, C A(7)
RRCA
RRC
R
R
R
R
R
C
C
R(n) R(n – 1),
R(0) C, C R(7)
R(n) A(n + 1),
R(7) C, C A(0)
RLCA
RLC
C
R(n) R(n + 1),
R(7) C, C R(0)
C
R(0 - 3) A(4 - 7),
R(4 - 7) A(0 - 3)
SWAPA
None
SWAP
JZA
JZ
R
R(0 - 3) R(4 - 7)
R + 1 A, skip if zero
R + 1 R, skip if zero
0 R(b)
None
None
None
R
R
*
BC
R, b
R, b
R, b
R, b
None
**
BS
1 R(b)
None
JBC
JBS
if R(b) = 0, skip
if R(b) = 1, skip
None
None
PC + 1 [SP],
(Page, k) PC
CALL
k
None
JMP
MOV
OR
k
(Page, k) PC
k A
None
A, k
A, k
A, k
A, k
None
A k A
A & k A
A k A
Z
Z
Z
AND
XOR
k A,
[Top of Stack] PC
RETL
SUB
INT
k
None
Z, C,DC
None
A, k
k - A A
PC + 1 [SP],
001H PC
ADD
A, k
k + A A
Z, C, DC
*
This instruction is not recommended for RF operation.
**
This instruction cannot operate under RF.
32
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
6 Absolute Maximum Ratings
Items
Rating
Temperature under bias
Storage temperature
0C
-65C
to
to
to
to
to
to
70C
150C
Input voltage
VSS - 0.3V
VSS - 0.3V
2.3V
VDD + 0.5V
VDD + 0.5V
5.5V
Output voltage
Working Voltage
Working Frequency
DC
20 MHz
NOTE
These parameters are theoretical values only and have not been tested or verified.
7 Electrical Characteristics
7.1 DC Characteristics
TA = 25 C, VDD = 5V, VSS = 0V
Symbol
Parameter
Crystal: VDD to 2.3V
Crystal: VDD to 3V
Crystal: VDD to 5V
ERC: VDD to 5V
Condition
Min.
DC
DC
DC
Typ.
Max.
4.0
Unit
MHz
MHz
MHz
Two cycles with two clocks
Two cycles with two clocks
Two cycles with two clocks
R: 5k, C: 39 pF
FXT
8.0
20.0
ERC
IIL
F30 750 F30 kHz
Input Leakage Current for input pins VIN = VDD, VSS
2
1
µA
V
VIH1
VIL1
Input High Voltage (VDD = 5V)
Input Low Voltage (VDD = 5V)
Ports 5, 6
Ports 5, 6
0.8
V
Input High Threshold Voltage
(VDD = 5V)
/RESET, TCC
(Schmitt trigger)
VIHT1
VILT1
VIHX1
VILX1
2
VDD+0.3
0.8
V
V
V
V
Input Low Threshold Voltage
(VDD = 5V)
/RESET, TCC
(Schmitt trigger)
VSS-0.3
2.5
Clock Input High Voltage
(VDD = 5V)
OSCI
OSCI
VDD+0.3
1.0
Clock Input Low Voltage
(VDD = 5V)
VSS-0.3
VIH2
VIL2
Input High Voltage (VDD = 3V)
Input Low Voltage (VDD = 3V)
Ports 5, 6
Ports 5, 6
1.5
VDD+0.3
0.4
V
V
VSS-0.3
Input High Threshold Voltage
(VDD = 3V)
/RESET, TCC
(Schmitt trigger)
VIHT2
VILT2
1.5
VDD+0.3
0.4
V
V
Input Low Threshold Voltage
(VDD = 3V)
/RESET, TCC
(Schmitt trigger)
VSS-0.3
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
33
EM78P153B
8-Bit Microcontroller with OTP ROM
(Continuation)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Clock Input High Voltage
(VDD = 3V)
VIHX2
1.5
VDD+0.3
V
OSCI
OSCI
Clock Input Low Voltage
(VDD = 3V)
VILX2
IOH
IOL
VSS-0.3
-12
0.6
V
High Drive Current
(Ports 5 and 6)
VOH = 2.4V
VOL = 0.4V
-17
15
mA
mA
µA
µA
Low Sink Current
(Ports 5 and 6)
10.5
Pull-high active,
Input pin at VSS
IPH
-37.5 -57.5
-77.5
57.5
Pull-high current
Pull-down current
Pull-down active,
Input pin at VDD
IPD
17.5
37.5
Ta = 25C
2.41
2.15
3.1
2.7
2.7
3.5
3.5
4.0
4.0
2.99
3.29
3.9
V
V
V
V
V
V
LVR1 Low voltage reset Level 1 (2.7V)
LVR2 Low voltage reset Level 2 (3.5V)
LVR3 Low voltage reset Level 3 (4.0V)
Ta = -40C ~ 85C
Ta = 25C
Ta = -40C ~ 85C
Ta = 25C
2.73
3.55
3.16
4.27
4.44
4.82
Ta = -40C ~ 85C
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
ISB1
ISB2
0.5
5
1
µA
µA
Power down current
Power down current
All input and I/O pins at VDD,
Output pin floating,
WDT enabled
10
/RESET = 'High',
FOSC = 32kHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT disabled
Operating supply current
at two clocks (VDD = 3V)
ICC1
ICC2
15
19
30
35
µA
µA
/RESET = 'High',
FOSC = 32kHz
(Crystal type, CLKS="0"),
Output pin floating,
WDT enabled
Operating supply current
at two clocks (VDD = 3V)
/RESET = 'High',
FOSC = 4MHz
(Crystal type, CLKS="0"),
Output pin floating
Operating supply current
at two clocks (VDD = 5.0V)
ICC3
ICC4
2.0
4.0
mA
mA
/RESET = 'High',
FOSC = 10MHz
(Crystal type, CLKS="0"),
Output pin floating
Operating supply current
at two clocks (VDD = 5.0V)
34
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
NOTE
These parameters are theoretical values only and have not been tested or verified.
7.2 AC Characteristics
TA = 25C, VDD = 5V, VSS = 0V
Symbol
Parameter
Conditions
Min.
Typ.
Max.
55
Unit
%
Dclk
Input CLK duty cycle
-
45
50
-
Crystal type
RC type
100
500
DC
DC
-
ns
Instruction cycle time
(CLKS="0")
Tins
-
ns
Ttcc
Tdrh
Trst
TCC input period
-
(Tins + 20) / N5
23.5 - 30%
2000
-
ns
Device reset hold time
/RESET pulse width
TXAL, SUT1, SUT0=1, 1
23.5 23.5 + 30% ms
ns
23.5 23.5 + 30% ms
-
SUT1, SUT0=1,1
SUT1, SUT0=1,0
SUT1, SUT0=0,1
SUT1, SUT0=0,0
-
-
-
Twdt11 Watchdog timer period
Twdt22 Watchdog timer period
Twdt33 Watchdog timer period
Twdt44 Watchdog timer period
23.5 - 30%
5.9 - 30%
376 - 30%
94 - 30%
-
5.9
5.9 + 30%
ms
ms
ms
ns
376 376 + 30%
94
0
94 + 30%
Tset
Input pin setup time
Input pin hold time
-
-
-
Thold
-
-
20
50
ns
Tdelay Output pin delay time
CLOAD = 20pF
-
ns
1Twdt1: The Option word (SUT1, SUT0) is used to define the oscillator set-up time.
In Crystal mode the WDT time-out length is the same as set-up time (23.5 ms).
2Twdt2: The Option word (SUT1, SUT0) is used to define the oscillator set-up time.
In Crystal mode the WDT time-out length is the same as set-up time (5.9 ms).
3Twdt3: The Option word (SUT1, SUT0) is used to define the oscillator set-up time.
In Crystal mode the WDT time-out length is the same as set-up time (376 ms).
4Twdt4: The Option word (SUT1, SUT0) is used to define the oscillator set-up time.
In Crystal mode the WDT time-out length is the same as set-up time (94 ms).
5N = Selected prescaler ratio
NOTE
These parameters are theoretical values only and have not been tested or verified.
The Watchdog Timer duration is determined by Option Code (Bit 6, Bit 5)
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
35
EM78P153B
8-Bit Microcontroller with OTP ROM
8 Timing Diagrams
AC Test Input/Output Waveform
2.4
2.0
0.8
2.0
0.8
TEST POINTS
0.4
Note: AC Testing: Input are driven at 2.4V for logic “1,” and 0.4V for logic “0”
Timing measurements are made at 2.0V for logic “1,” and 0.8V for logic “0”
Figure 8-1a AC Test Input/Output Waveform Timing Diagram
Reset Timing (CLK = "0")
Instruction 1
NOP
Executed
CLK
/RESET
Tdrh
Figure 8-1b Reset Timing Diagram
TCC Input Timing (CLKS = "0")
ins
CLK
TCC
tcc
Figure 8-1c TCC Input Timing Diagram
36
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
APPENDIX
A Ordering and Manufacturing Information
EM78P153BD14J
Material Type
J: RoHS complied
Pin Number
Package Type
D: DIP
SO: SOP
SS: SSOP
Specific Annotation
K: Industrial Grad
Product Number
Product Type
P: OTP
Elan 8-bit Product
For example:
EM78P153BSO14J
is EM78P153B with OTP program memory, product, in 14-pin SOP
300mil package with RoHS complied
IC Mark
‧‧‧‧‧‧‧
Elan Product Number / Package, Material Type
EM78Paaaaaa
1041c bbbbbb
Batch Number
Manufacture Date
“YYWW”
YY is year and WW is week
c is Alphabetical suffix code for Elan use only
‧‧‧‧‧‧‧
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
37
EM78P153B
8-Bit Microcontroller with OTP ROM
Ordering Code
EM78P153BD14J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
38
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
B Package Type
OTP MCU
Package Type
Pin Count
Package Size
EM78P153BD14
EM78P153BSO14
EM78P153BSS10
DIP
SOP
14
14
10
300 mil
150 mil
150 mil
SSOP
These are Green products that comply with RoHS specifications.
Part No.
Electroplate type
Ingredient (%)
EM78P153BD14J, EM78P153BSO14J, EM78P153BSS10J
Pure Tin
Sn: 100%
Melting point (C)
Electrical resistivity (-cm)
Hardness (hv)
232 C
11.4
8~10
Elongation (%)
50%
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
39
EM78P153B
8-Bit Microcontroller with OTP ROM
C Package Information
14-Lead Plastic Dual in-line (DIP) — 300 mil
Symbol
Min. Normal Max.
A
A1
A2
c
4.318
D
E1
0.381
14
8
3.175
0.203
3.302
0.254
3.429
0.356
C
D
18.796 19.050 19.304
E
E
6.174
7.366
8.409
0.356
1.143
3.048
6.401
7.696
6.628
8.025
9.625
0.559
1.778
3.556
eB
E1
eB
B
9.017
1
7
θ
0.457
B1
L
1.524
3.302
e
2.540(Typ.)
θ
0
15
A1
A2
A
L
B
B1
e
TITLE:
PDIP-14L 300MIL PACKAGE
OUTLINE DIMENSION
File :
Edtion: A
D14
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-1a EM78P153B 14-Lead DIP Package Type
40
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
EM78P153B
8-Bit Microcontroller with OTP ROM
14-Lead Small-Outline Package (SOP) — 150 mil
Symbol
M in.
1.350
0.100
0.330
0.190
3.800
5.800
8.550
0.600
Normal
M ax.
1.750
0.250
0.510
0.250
4.000
6.200
8.750
1.270
A
A1
b
c
E
H
E
H
D
L
e
1.27(TYP)
θ
0
8
e
b
c
D
A2
A
TITLE:
SOP-14L(150MIL) PACKAGE
OUTLINE DIMENSION
File :
Edtion: A
NSO14
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-1b EM78P153B 14-Lead DIP/SOP Package Type
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
41
EM78P153B
8-Bit Microcontroller with OTP ROM
10-Lead Shrink Small-Outline Package (SSOP) — 150 mil
Symbol
Min
1.35
0.075
1.18
4.7
Normal
1.55
0.175
1.38
4.9
Max
1.75
0.275
1.58
5.1
A
A1
A2
D
E
5.8
6.0
6.2
E1
b
3.7
3.9
4.1
0.406
0.406
0.178
0.178
0.55
0.496
0.456
0.278
0.228
0.75
b1
c
c1
L
0.65
1.00TYP
-
e
θ
0°
7°
TITLE:
SSOP 10L (150MIL)PACKAGE OUTLINE
DIMENSION
File :
SSOP 10L
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-1c EM78P153B 10-Lead SSOP Package Type
42
Product Specification (V1.4) 04.25.2016
(This specification is subject to change without prior notice)
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