EM78P176NJSS20J/S [ELAN]
8-Bit Microcontroller with OTP ROM;
| 型号： | EM78P176NJSS20J/S |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller with OTP ROM OTP只读存储器 微控制器 |
| 文件： | 总64页 (文件大小：1802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P176N
8-Bit Microcontroller
with OTP ROM
Product
Specification
DOC. VERSION 1.2
ELAN MICROELECTRONICS CORP.
December 2015
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2010~2015 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road
Hsinchu Science Park
Elan (HK) Microelectronics
Corporation, Ltd.
Elan Information
Technology Group
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Flat A, 19F., World Tech Centre 95 (U.S.A.)
How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
PO Box 601
Cupertino, CA 95015
U.S.A.
Fax: +852 2723-7780
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
ELAN Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
General Description ................................................................................................ 1
Features ................................................................................................................... 1
Pin Assignment ....................................................................................................... 2
Pin Description........................................................................................................ 3
4.1 EM78P176N-20PIN ..........................................................................................3
4.2 EM78P176N-18PIN ..........................................................................................4
5
6
Block Diagram ......................................................................................................... 5
Functional Description............................................................................................ 6
6.1 Operational Registers .......................................................................................6
6.1.1 R0 (Indirect Addressing Register) .......................................................................6
6.1.2 R1 (Timer Clock/Counter) ...................................................................................6
6.1.3 R2 (Program Counter and Stack)........................................................................6
6.1.4 R3 (Status Register)............................................................................................8
6.1.5 R4 (RAM Select Register)...................................................................................8
6.1.6 R5 ~ R7 (Port 5 ~ Port 7) ....................................................................................8
6.1.7 Bank 0 RE (LVD Control Register)......................................................................9
6.1.8 Bank 0 RF (Interrupt Status Register).................................................................9
6.1.9 Bank 1 R5 (TBHP: Table Point Register for Instruction TBRD) ........................10
6.1.10 Bank 1 R6 (TBLP: Table Point Register for Instruction TBRD) .........................10
6.1.11 Bank 1 RE (LVD Interrupt and Wake-up Register)............................................10
6.1.12 Bank 1 RF (System Control Register)...............................................................11
6.1.13 R10 ~ R3F.........................................................................................................14
6.2 Special Function Registers .............................................................................15
6.2.1 A (Accumulator).................................................................................................15
6.2.2 CONT (Control Register)...................................................................................15
6.2.3 IOC5 ~ IOC7 (I/O Port Control Register) ..........................................................16
6.2.4 IOCB (Pull-down Control Register) ...................................................................16
6.2.5 IOCC (Open-drain Control Register).................................................................16
6.2.6 IOCD (Pull-high Control Register).....................................................................17
6.2.7 IOCE (WDT Control Register)...........................................................................17
6.2.8 IOCF (Interrupt Mask Register).........................................................................18
6.3 TCC/WDT and Prescaler ................................................................................18
6.4 I/O Ports .........................................................................................................19
6.5 Reset and Wake-up ........................................................................................22
6.5.1 Reset .................................................................................................................22
6.5.2 Wake-up and Interrupt Modes Operation Summary .........................................24
6.5.3 Summary of Registers Initialized Values...........................................................26
6.5.4 Status of RST, T, and P of the Status Register..................................................28
Product Specification (V1.2) 12.16.2015
iii
Contents
6.6 Interrupt ..........................................................................................................29
6.7 Oscillator.........................................................................................................31
6.7.1 Oscillator Modes................................................................................................31
6.7.2 Crystal Oscillator/Ceramic Resonators (Crystal)...............................................32
6.7.3 External RC Oscillator Mode.............................................................................34
6.7.4 Internal RC Oscillator Mode ..............................................................................35
6.8 Code Option Register .....................................................................................36
6.8.1 Code Option Register (Word 0).........................................................................36
6.8.2 Code Option Register (Word 1).........................................................................37
6.8.3 Customer ID Register (Word 2).........................................................................38
6.9 Power-on Consideration .................................................................................39
6.10 External Power-on Reset Circuits ...................................................................39
6.11 Residue-Voltage Protection.............................................................................40
6.12 Low Voltage Detector......................................................................................41
6.12.1 Low Voltage Reset (LVR) ..................................................................................41
6.12.2 Low Voltage Detector (LVD)..............................................................................41
6.12.3 Programming Process.......................................................................................43
6.13 Instruction Set.................................................................................................44
7
8
Absolute Maximum Ratings.................................................................................. 47
Electrical Characteristics...................................................................................... 47
8.1 DC Characteristics..........................................................................................47
8.2 AC Characteristics..........................................................................................49
9
Timing Diagrams ................................................................................................... 50
APPENDIX
A
B
C
D
Ordering and Manufacture Information ............................................................... 52
Package Type......................................................................................................... 52
Package Information ............................................................................................. 53
Quality Assurance and Reliability ........................................................................ 57
D.1 Address Trap Detect.......................................................................................57
iv
Product Specification (V1.2) 12.16.2015
Contents
Specification Revision History
Doc. Version
Revision Description
Date
0.9
1.0
Preliminary version
2010/03/24
2010/04/21
Initial version
Deleted the EM78P176NSS10J/S Package Type
Deleted the EM78P176NMS10J/S Package Type
Added EM78P176NJSS20J Package Type
Modified the Electrical Characteristics
1.1
1.2
2011/07/08
Add description about J/S
Modified the description of LVR and POR
Add ordering and manufactire information
Modified pin assignment EM78P176NJSS20J package
2015/012/16
Product Specification (V1.2) 12.16.2015
v
Contents
vi
Product Specification (V1.2) 12.16.2015
EM78P176N
8-Bit Microcontroller with OTP ROM
1 General Description
The EM78P176N is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. It has an on-chip 1k 13-bit Electrical One Time Programmable Read Only Memory
(OTP-ROM). They provide a protection bit to prevent intrusion of user’s OTP memory code. Three Code
option words are also available to meet user’s requirements.
With its enhanced OTP-ROM features, the EM78P176N provides a convenient way of developing and
verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program
updates, using development and programming tools. User can avail of the ELAN Writer to easily program
your development code.
2 Features
IRCERC mode:
DC ~ 2 MHz / 2clks @ 2.1V
CPU Configuration
1k 13 bits on-chip ROM
48 8 bits on-chip registers (SRAM, General
purpose)
5-level stacks for subroutine nesting
4 programmable level voltage detector
LVD : 4.5, 4.0, 3.3, 2.2V
3 programmable level voltage reset
LVR Less than 1.5mA at 5V / 4MHz
Typically 15 µA at 3V / 32kHz
Typically 1 µA during Sleep mode
Peripheral Configuration
8-bit real time clock/counter (TCC) with
selective signal sources, trigger edges, and
overflow interrupt
4 programmable level voltage detector
LVD : 4.5, 4.0, 3.3, 2.2V
3 programmable level voltage reset
LVR : 4.0, 3.5, 2.7V
External interrupt input pin
2/4 clocks per instruction cycle selected by
code option
I/O Port Configuration
3 bidirectional I/O ports : P5, P6, P7
18 I/O pins
Wake-up port : P6
7 Programmable pull-down I/O pins
8 programmable pull-high I/O pins
8 programmable open-drain I/O pins
External interrupt with wake-up: P60
Power down (Sleep) mode
High EFT immunity
Four Available Interrupts:
TCC overflow interrupt
Input-port status changed interrupt
External interrupt
Low voltage detect interrupt
Operating Voltage Range:
Special featuresFeatures
2.1V ~ 5.5V at 0 ~ 70(C (Commercial)
2.3V ~ 5.5V at -40 ~ 85C (Industrial)
Programmable free running watchdog timer
Power-on voltage detector available
Operating Frequency Range (Base on 2 clocks):
IRC mode:
Package Type:
20-pin SSOP 209mil :EM78P176NSS20J/S
20-pin SOP 300mil :EM78P176NSO20J/S
Drift Rate
Internal
Temp.
RC Freq.
Voltage
Process Total
18-pin DIP 300mil
:EM78P176ND18J/S
(-40~85°C)
18-pin SOP 300mil :EM78P176NSO18J/S
20-pin SSOP 209mil :EM78P176NJSS20J/S
4 MHz
16 MHz
8 MHz
1 MHz
± 1%
± 1%
± 1%
± 1%
± 3% @ 2.1~5.5V ± 2% ± 6%
± 1% @ 4.0~5.5V ± 2% ± 4%
± 2% @ 3.0~5.5V ± 2% ± 5%
± 3% @ 2.1~5.5V ± 2% ± 6%
Note: These are all Green products which do not
contain hazardous substances.
* Operating voltage range
Crystal mode:
DC ~ 20MHz / 2clks @ 5V
DC ~ 8MHz / 2clks @ 3V
DC ~ 4MHz / 2clks @ 2.1V
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
1
EM78P176N
8-Bit Microcontroller with OTP ROM
3 Pin Assignment
(1) 20-Pin SSOP/SOP
(2) 18-Pin DIP/SOP
20
1
2
P56
P57
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
P52
P53
P51
P50
19
18
17
16
15
14
13
P51
P50
P52
P53
3
P55/OSCO/ERCin
P70/OSCI/RCOUT
VDD
P54/TCC
P55/OSCO/ERCin
P70/OSCI/RCOUT
VDD
4
P54/TCC
P71//RESET
VSS
P71//RESET
VSS
5
6
P67
P60//INT
P61
P67
7
P60//INT
P61
12
11
P66
P65
P64
P66
P65
P64
8
P62
12
11
9
P62
P63
10
P63
10
Figure 3-1 20-pin EM78P176N
Figure 3-2 18-pin EM78P176N
(3) 20-Pin JSSOP
20
1
2
P52
P51
19
18
17
16
15
14
13
P50
P53
P55/OSCO/ERCin
P54/TCC
3
P70/OSCI/RCOUT
4
P71/RESET
VSS
VDD
VDD
P67
5
6
VSS
7
P60//INT
P61
P66
P65
P64
8
12
11
9
P62
P63
10
Figure 3-3 20-pin EM78P176N
2
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
4 Pin Description
4.1 EM78P176N-20PIN
Input Output
Name
P50~P52
Function
Description
Type
Type
Bidirectional I/O pin with programmable
pull-down.
P50~P52 ST
CMOS
P53
P53
P54
TCC
P55
ST
ST
ST
ST
CMOS Bidirectional I/O pin
CMOS Bidirectional I/O pin
P54/TCC
Real Time Clock/Counter clock input
CMOS Bidirectional I/O pin.
XTAL
P55/OSCO/ERCin OSCO
ERCin
Clock output of crystal/resonator oscillator
AN
External RC input pin
CMOS Bidirectional I/O pin
Bidirectional I/O pin with programmable
P56~P57
P56~P57 ST
P60
/INT
ST
ST
CMOS pull-down, open-drain, pull-high and pin
change wake-up.
P60//INT
External interrupt pin
Bidirectional I/O pin with programmable
pull-down, open-drain, pull-high and pin
change wake-up.
CMOS
P61~P63
P64~P67
P61~P63 ST
P64~P67 ST
Bidirectional I/O pin with programmable
CMOS open-drain, pull-high and pin change
wake-up.
P70
ST
CMOS Bidirectional I/O pin
XTAL
OSCI
Clock input of crystal/resonator oscillator
Clock output of internal RC oscillator
P70/OSCI/RCOUT
RCOUT
CMOS Clock output of external RC oscillator
(open-drain)
P71
ST
CMOS Bidirectional I/O pin. (open-drain)
P71//RESET
/RESET
VDD
ST
External pull-high reset pin
VDD
VSS
Power
Power
Power
VSS
Ground
Legend: ST: Schmitt Trigger input
CMOS: CMOS output
AN: analog pin
XTAL: oscillation pin for crystal / resonator
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
3
EM78P176N
8-Bit Microcontroller with OTP ROM
4.2 EM78P176N-18PIN
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable
pull-down.
P50~P52
P50~P52
ST
CMOS
P53
P53
P54
TCC
P55
ST
ST
ST
ST
CMOS
CMOS
Bidirectional I/O pin
Bidirectional I/O pin
P54/TCC
Real Time Clock/Counter clock input
Bidirectional I/O pin
CMOS
XTAL
Clock output of crystal/resonator
oscillator
P55/OSCO/ERCin OSCO
ERCin
AN
External RC input pin
Bidirectional I/O pin with programmable
pull-down, open-drain, pull-high and pin
change wake-up.
P60
ST
ST
ST
CMOS
P60//INT
/INT
External interrupt pin
Bidirectional I/O pin with programmable
pull-down, open-drain, pull-high and pin
change wake-up.
CMOS
P61~P63
P64~P67
P61~P63
Bidirectional I/O pin with programmable
open-drain, pull-high and pin change
wake-up.
P64~P67
ST
CMOS
P70
ST
CMOS
Bidirectional I/O pin
XTAL
OSCI
Clock input of crystal/resonator oscillator
Clock output of internal RC oscillator
P70/OSCI/RCOUT
P71//RESET
RCOUT
CMOS
Clock output of external RC oscillator
(open-drain)
P71
ST
CMOS
Bidirectional I/O pin (open-drain)
External pull-high reset pin
Power
/RESET
VDD
ST
VDD
VSS
Power
Power
VSS
Ground
Legend: ST: Schmitt Trigger input
CMOS: CMOS output
AN: analog pin
XTAL: oscillation pin for crystal / resonator
4
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
5 Block Diagram
Ext.
OSC.
Int.
RC
Ext.
RC
PC
ROM
WDT
TCC
LVD
TCC
LVD
Oscillation
Generation
8-level
stack
(13 bit)
Instruction
Register
P5
Reset
P50
P51
P52
P53
P54
P55
P56
P57
Instruction
Decoder
Ext INT
Mux.
ALU
P6
LVD
LVR
R4
P60
P61
P62
P63
P64
P65
P66
P67
RAM
Interrupt
control
circuit
R3(Status
Reg.)
ACC
P70
P71
Figure 5-1 EM78P176N Functional Block Diagram
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
5
EM78P176N
8-Bit Microcontroller with OTP ROM
6 Functional Description
6.1 Operational Registers
6.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as a pointer actually accesses data pointed by the
RAM Select Register (R4).
6.1.2 R1 (Timer Clock/Counter)
Incremented by an external signal edge, which is defined by TE bit (CONT-4)
through the TCC pin, or by the instruction cycle clock.
Writable and readable as any other registers.
Defined by resetting PAB (CONT-3).
The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
The contents of the prescaler counter will be cleared only when the TCC register is
written with a value.
6.1.3 R2 (Program Counter and Stack)
Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in the following figure.
000H
008H
Reset Vector
Interrupt Vector
PC (A9 ~ A0)
On-chip Program
Memory
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
3FFH
Figure 6-1 Program Counter Organization
When ICE300N tries to simulate the stack of EM78P176N, and when the simulated
stacks exceed 5 levels, the simulated result will be inconsistent with the
EM78P176N.
The configuration structure generates 102413 bits on-chip OTP ROM addresses
to the relative programming instruction codes. One program page is 1024 words
long.
R2 is set as all "0" when under RESET condition.
6
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows the PC to go to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 are pushed
onto the stack. Thus, the subroutine entry address can be located anywhere within
a page.
"RET" ("RETLk", "RETI") instruction loads the program counter with the contents of
the top-level stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and tenth bits of the PC will increase progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.
Any instruction (except “ADD R2,A”) that is written to R2 (e.g., "MOV R2, A", "BC
R2, 6" etc.) will cause the ninth bit and above bits of the PC to remain unchanged.
All instructions are single instruction cycle (fclk/2 or fclk/4) except for instructions
that would change the contents of R2. Such instructions will need one more
instruction cycle.
Register
Bank 0
Register
Bank 1
Control
Register
Address
R1 (TCC Buffer)
R2 (PC)
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
R3 (STATUS)
R4(6)
R4 (RSR, bank select)
R5 (Port 5 I/O data)
R6 (Port 6 I/O data)
R7 (Port 7 I/O data)
R8 (Reserved)
R5 (TBHP)
IOC50 (Port 5 I/O Control)
IOC60 (Port 6 I/O Control)
R6 (TBLP)
IOC70 (Port 7 I/O Control)
IOC80 (Reserved)
R7 (Reserved)
R8 (Reserved)
R9 (Reserved)
RA (Reserved)
IOC90 (Reserved)
R9 (Reserved)
RA (Reserved)
IOCA0 (Reserved)
IOCB0 (Pull-down Control
Register)
IOCC0 (Open-drain Control
Register)
IOCD0 (Pull-High Control
Register)
RB (Reserved)
RC (Reserved)
RD (Reserved)
RB (Reserved)
RC (Reserved)
RC (Reserved)
RE (LVD Interrupt &
Wake-up Register)
RF (System Control
Register)
IOCE0 (WDT Control Register)
IOCF0 (IMR)
RE (LVD Control Register)
RF (ISR)
0F
10
:
1F
20
:
16-Byte Register
32-Byte Register
3F
Figure 6-2 Data Memory Configuration
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
7
EM78P176N
8-Bit Microcontroller with OTP ROM
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
GP1
GP0
T
P
Z
DC
C
Bit 7 (RST): Bit for reset type
0: Set to 0 if the device wakes up from other reset type.
1: Set to 1 if the device wakes up from sleep mode on a pin change,
external interrupt or low voltage detector interrupt.
Bits 6 ~ 5 (GP1 ~ GP0): General-purpose read/write bits
Bit 4 (T): Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up;
and reset to “0” by WDT time-out.
Bit 3 (P): Power down bit
Set to “1” during power on or by a "WDTC" command; and reset to “0” by
a "SLEP" command.
Bit 2 (Z): Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7: General-purpose read/write bits.
Bit 6: Used to select Banks 0~1.
See the Data Memory Configuration in Figure 6-2.
6.1.6 R5 ~ R7 (Port 5 ~ Port 7)
R5, R6 and P70 ~ P71 are I/O registers.
P72 ~ P77 are fixed to 0.
8
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
6.1.7 Bank 0 RE (LVD Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
-
-
-
-
-
LVDWE
Bit 7 (/LVD): Low voltage Detector state.
When the VDD pin voltage is lower than LVD voltage interrupt level
(selected by LVD1 and LVD0), this bit will be cleared.
0: Low voltage is detected.
1: Low voltage is not detected or LVD function is disabled.
Bit 6 (LVDIF): LVD Interrupt Flag bit.
0: No interrupt occurs
1: With interrupt request
Bits 5 ~ 1: Not used. Set to “0” at all time.
Bit 0 (LVDWE): Low Voltage Detect wake-up.
0: Disable Low Voltage Detect wake-up.
1: Enable Low Voltage Detect wake-up.
6.1.8 Bank 0 RF (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIF
ICIF
TCIF
NOTE
“ 1 ” means with interrupt request
“ 0 ” means no interrupt occurs
Bits 7 ~ 3: Not used. Set to “0” at all time.
Bit 2 (EXIF): External Interrupt Flag. Set by a falling edge on the /INT pin, reset by
software.
Bit 1 (ICIF): Port 6 input status changed interrupt flag. Set when Port 6 input changes,
reset by software.
Bit 0 (TCIF): TCC Overflow Interrupt Flag. Set when TCC overflows, reset by
software.
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
NOTE
The result of reading RF is the "logic AND" of RF and IOCF.
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
9
EM78P176N
8-Bit Microcontroller with OTP ROM
6.1.9 Bank 1 R5 (TBHP: Table Point Register for Instruction TBRD)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MLB
-
-
-
-
-
RBit9
RBit8
Bit 7 (MLB): Chooses the MSB or LSB machine code to move into the register.
The machine code is pointed by TBLP and TBHP register.
Bits 6 ~ 2: Not used. Set to “0” at all time.
Bits 1 ~ 0: Most 2 significant bits of address for program code
6.1.10 Bank 1 R6 (TBLP: Table Point Register for Instruction
TBRD)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBit7
RBit6
RBit5
RBit4
RBit3
RBit2
RBit1
RBit0
Bits 7 ~ 0: These are the least 8 significant bits of address for program code.
6.1.11 Bank 1 RE (LVD Interrupt and Wake-up Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIE
LVDEN
LVD1
LVD0
-
-
-
EXWE
Bit 7 (LVDIE): Low voltage detector interrupt enable bit
0: Disable the low voltage detector interrupt
1: Enable the low voltage detector interrupt
Bit 6 (LVDEN): Low voltage detector enable bit
0: Disable the Low voltage detector function
1: Enable the Low voltage detector function
Bits 5 ~ 4: Low voltage detector level bits
LVDEN
LVD1, LVD0
LVD Voltage Interrupt Level
Vdd 2.2V
Vdd > 2.2V
Vdd 3.3V
Vdd > 3.3V
Vdd 4.0V
Vdd > 4.0V
Vdd 4.5V
Vdd > 4.5V
N/A
/LVD
0
1
0
1
0
1
0
1
1
1
11
1
1
10
01
1
0
00
10
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
NOTE
IF Vdd has crossover at LVD voltage in interrupt level as VDD varies, LVD interrupt
will occur.
Bits 3 ~ 1: Not used. Set to “0” at all time.
Bit 0 (EXWE): External /INT wake-up enable bit
0: Disable External /INT pin wake-up
1: Enable External /INT pin wake-up
6.1.12 Bank 1 RF (System Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
TIMERSC
CPUS
IDLE
-
-
RCM1
RCM0
Bits 7, 3 ~ 2: not used, fixed to "0" all the time.
Bit 6 (TIMERSC): TCC clock source select.
0: FS is used as FC
1: FM is used as FM / 2 or FM / 4 (Default)
Bit 5 (CPUS): CPU Oscillator Source Select
0: Fs: sub frequency for WDT internal RC time base 16 kHz
1: Fm: main oscillator (FM) (Default)
When CPUS = 0, the CPU oscillator selects the sub-oscillator and the
main oscillator is stopped.
Bit 4 (IDLE): Idle Mode Enable Bit.
From SLEP instruction, this bit will determine as to which mode to
choose.
0: IDLE = ‘0’ + SLEP instruction sleep mode (Default)
1: IDLE = ‘1’ + SLEP instruction idle mode
RESET
Normal Mode
fm:oscillation
fs: oscillation
Wake up
wake up
CPU: using fm
CPUS="0"
CPUS="1"
IDLE="0"
+SLEP
IDLE="1"
+SLEP
IDLE="1
"+SLEP
Wake up
Sleep Mode
fm:stop
Green Mode
fm:stop
Idle Mode
fm:stop
fs: stop
fs: oscillation
fs: oscillation
IDLE="0"
+ SLEP
CPU: stop
CPU: using fs
CPU: stop
wake up
Figure 6-3 CPU Operation Mode Diagram
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
11
EM78P176N
8-Bit Microcontroller with OTP ROM
Oscillator
Oscillator Stable
Time (S)1
Count from
Normal/Green (CLK)2
CPU Mode Status
(Normal Mode Source)
Sleep/Idle → Normal
Green → Normal
510 CLK
510 CLK
8 CLK
0.5 ms ~ 2 ms
< 100 µs
< 5 µs
Crystal
1M ~ 20 MHz
Sleep/Idle → Green
Sleep/Idle → Normal
Green → Normal
ERC
8 CLK
8 CLK
2 MHz
Sleep/Idle → Green
Sleep/Idle → Normal
Green → Normal
< 100 µs
< 2 µs
IRC
1M, 4M, 8M, 16 MHz
Sleep/Idle → Green
< 100 µs
NOTE
■
■
1The oscillator stable time depends on the oscillator characteristics.
2After the oscillator has stabilized, the CPU will count 510/8 CLK in Normal/Green
mode and continue to work in Normal/Green mode.
Ex 1 : The 4 MHz IRC wakes-up from Sleep mode to Normal mode,
the total wake-up time is 2 µs + 8 CLK @ 4 MHz.
Ex 2 : The 4 MHz IRC wakes-up from Sleep mode to Green mode,
the total wake-up time is 100 µs + 8 CLK @ 16kHz.
Bits 1 ~ 0 (RCM1 ~ RCM0): IRC mode select bits.
RCM 1
RCM 0
Frequency (MHz)
1
1
0
0
1
0
1
0
4
16
8
1
12
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
Bank 1 RF<1, 0> will be enabled.
Bank 1 RF<1,0>
Writer Trim IRC
Operating Voltage
Frequency
Stable Time
Range
RCM1
RCM0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
4 MHz ± 2%
16 MHz ± 10%
8 MHz ± 10%
1MHz ± 10%
4 MHz ± 10%
16 MHz ± 2%
8 MHz ± 10%
1MHz ± 10%
4 MHz ± 10%
16 MHz ± 10%
8 MHz ± 2%
1MHz ± 10%
4 MHz ± 10%
16 MHz ± 10%
8 MHz ± 10%
1 MHz ± 2%
2.1V ~ 5.5V
4.5V ~ 5.5V
3.0V ~ 5.5V
2.1V ~ 5.5V
2.1V ~ 5.5V
4.5V ~ 5.5V
3.0V ~ 5.5V
2.1V ~ 5.5V
2.1V ~ 5.5V
4.5V ~ 5.5V
3.0V ~ 5.5V
2.1V ~ 5.5V
2.1V ~ 5.5V
4.5V ~ 5.5V
3.0V ~ 5.5V
2.1V ~ 5.5V
< 5 µs
< 1.5 µs
< 3 µs
4 MHz
16 MHz
8 MHz
1 MHz
< 24 µs
< 6 µs
< 1.25 µs
< 3 µs
< 24 µs
< 6 µs
< 1.5 µs
< 2.5 µs
< 24 µs
< 6 µs
< 1.5 µs
< 3 µs
< 20 µs
NOTE
■ The initial values of Bank1 RF<1, 0> will be kept the same as Word 1<6, 5>.
■ If user changes the IRC frequency from A-frequency to B-frequency, the MCU needs
to wait for some time for it to work. The waiting time corresponds to the B-frequency.
For Example:
1st step When user selects the 4 MHz at the Writer, the initial values of Bank 1 RF<1,0>
would be “11”, the same as the value of Word 1<6,5> which is “11”.
If the MCU is free-running, it will work at 4 MHz ± 2%. Refer to the table below.
Bank 1 RF<1,0>
Operating Voltage
Range
Stable
Time
Writer Trim IRC
Frequency
RCM1
RCM0
1
1
0
0
1
0
1
0
4 MHz ± 2%
16 MHz ± 10%
8 MHz ± 10%
1MHz ± 10%
2.1V ~ 5.5V
4.5V ~ 5.5V
3.0V ~ 5.5V
2.1V ~ 5.5V
< 5 µs
< 1.5 µs
< 3 µs
4 MHz
< 24 µs
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
13
EM78P176N
8-Bit Microcontroller with OTP ROM
2nd step If it is desired to set Bank 1 RF<1,0> = “10” while the MCU is working at 4 MHz
± 2%, the MCU needs to hold for 1.5 µs, then it will continue to work at 16 MHz
± 10%.
Bank 1 RF<1,0>
Operating Voltage
Range
Stable
Time
Writer Trim IRC
Frequency
RCM1
RCM0
1
1
0
0
1
0
1
0
4 MHz ± 2%
16 MHz ± 10%
8 MHz ± 10%
1MHz ± 10%
2.1V ~ 5.5V
4.5V ~ 5.5V
3.0V ~ 5.5V
2.1V ~ 5.5V
< 5 µs
< 1.5 µs
< 3 µs
4 MHz
< 24 µs
3rd step If it is desired to set Bank 1 RF<1,0> = “00” while the MCU is working at
16 MHz ± 10%, the MCU needs to hold for 24 µs, then it will continue to work at
1 MHz ± 10%.
Bank 1 RF<1,0>
Operating Voltage
Range
Stable
Time
Writer Trim IRC
4 MHz
Frequency
RCM1
RCM0
1
1
0
0
1
0
1
0
4 MHz ± 2%
16 MHz ± 10%
8 MHz ± 10%
1MHz ± 10%
2.1V ~ 5.5V
4.5V ~ 5.5V
3.0V ~ 5.5V
2.1V ~ 5.5V
< 5 µs
< 1.5 µs
< 3 µs
< 24 µs
4th step If it is desired to set Bank 1 RF<1,0> = “11” while the MCU is working at
1 MHz ± 10%, the MCU needs to hold for 5 µs, then it will continue to work at 4
MHz ± 2%.
Bank 1 RF<1,0>
Operating Voltage
Range
Stable
Time
Writer Trim IRC
4 MHz
Frequency
RCM1
RCM0
1
1
0
0
1
0
1
0
4 MHz ± 2%
16 MHz ± 10%
8 MHz ± 10%
1MHz ± 10%
2.1V ~ 5.5V
4.5V ~ 5.5V
3.0V ~ 5.5V
2.1V ~ 5.5V
< 5 µs
< 1.5 µs
< 3 µs
< 24 µs
6.1.13 R10 ~ R3F
These are all 8-bit general-purpose registers.
14
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
6.2 Special Function Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
6.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GP
INT
TS
TE
PAB
PSR2
PSR1
PSR0
Bit 7 (GP): General purpose register.
Bit 6 (INT): Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
Bit 5 (TS): TCC signal source
0: internal instruction cycle clock, P54 is a bidirectional I/O pin
1: transition on TCC pin
Bit 4 (TE): TCC Signal Edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
Bit 3 (PAB): Prescaler Assigned Bit
0: TCC
1: WDT
Bit 2 ~ Bit 0 (PSR2 ~ PSR0): TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
1:2
WDT Rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:2
1:8
1:4
1:16
1:8
1:32
1:16
1:32
1:64
1:128
1:64
1:128
1:256
The CONT register is both readable and writable.
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
15
EM78P176N
8-Bit Microcontroller with OTP ROM
6.2.3 IOC5 ~ IOC7 (I/O Port Control Register)
0: defines the relative I/O pin as output
1: puts the relative I/O pin into high impedance
IOC5 and IOC6 and P70~P71 registers are both readable and writable.
6.2.4 IOCB (Pull-down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD63
/PD62
/PD61
/PD60
-
/PD52
/PD51
/PD50
Bit 7 (/PD63): Control bit used to enable pull-down of the P63 pin.
0: Enable internal pull-down
1: Disable internal pull-down
Bit 6 (/PD62): Control bit used to enable pull-down of the P62 pin.
Bit 5 (/PD61): Control bit used to enable pull-down of the P61 pin.
Bit 4 (/PD60): Control bit used to enable pull-down of the P60 pin.
Bit 3: Not used. Set to “1” at all time.
Bit 2 (/PD52): Control bit used to enable pull-down of the P52 pin.
Bit 1 (/PD51): Control bit used to enable pull-down of the P51 pin.
Bit 0 (/PD50): Control bit used to enable pull-down of the P50 pin.
The IOCB Register is both readable and writable.
6.2.5 IOCC (Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD67
OD66
OD65
OD64
OD63
OD62
OD61
OD60
Bit 7 (OD67): Control bit used to enable open-drain of the P67 pin.
0: Disable open-drain output
1: Enable open-drain output
Bit 6 (OD66): Control bit used to enable open-drain of the P66 pin.
Bit 5 (OD65): Control bit used to enable open-drain of the P65 pin.
Bit 4 (OD64): Control bit used to enable open-drain of the P64 pin.
Bit 3 (OD63): Control bit used to enable open-drain of the P63 pin.
Bit 2 (OD62): Control bit used to enable open-drain of the P62 pin.
Bit 1 (OD61): Control bit used to enable open-drain of the P61 pin.
Bit 0 (OD60): Control bit used to enable open-drain of the P60 pin.
The IOCC Register is both readable and writable.
16
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
6.2.6 IOCD (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Bit 7 (/PH67): Control bit is used to enable pull-high of the P67 pin.
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (/PH66): Control bit used to enable pull-high of the P66 pin.
Bit 5 (/PH65): Control bit used to enable pull-high of the P65 pin.
Bit 4 (/PH64): Control bit used to enable pull-high of the P64 pin.
Bit 3 (/PH63): Control bit used to enable pull-high of the P63 pin.
Bit 2 (/PH62): Control bit used to enable pull-high of the P62 pin.
Bit 1 (/PH61): Control bit used to enable pull-high of the P61 pin.
Bit 0 (/PH60): Control bit used to enable pull-high of the P60 pin.
The IOCD Register is both readable and writable.
6.2.7 IOCE (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
GP
GP
GP
GP
GP
GP
Bit 7 (WDTE): Control bit used to enable the Watchdog timer.
0: Disable WDT
1: Enable WDT
Bit 6 (EIS): Control bit is used to define the function of P60 (/INT) pin.
0: P60, bidirectional I/O pin.
1: /INT, external interrupt pin.
When EIS is "0," the path of /INT is masked. When EIS is "1," the status
of /INT pin can also be read by way of reading Port 6 (R6).
See Figure 6-6 under Section 6.4 for reference.
EIS is both readable and writable.
WDTE is both readable and writable.
Bits 5 ~ 0: General purpose register.
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
17
EM78P176N
8-Bit Microcontroller with OTP ROM
6.2.8 IOCF (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
EXIE
ICIE
TCIE
Bits 7 ~ 3: Not used. Set to “1” at all time.
Individual interrupt is enabled by setting its associated control bit in the
IOCF to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the
DISI instruction. Refer to Figure 6-10.
Bit 2 (EXIE): EXIF interrupt enable bit
0: disable EXIF interrupt
1: enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: disable ICIF interrupt
1: enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit
0: disable TCIF interrupt
1: enable TCIF interrupt
The IOCF register is both readable and writable.
6.3 TCC/WDT and Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is
available for the TCC only or the WDT only at the same time and the PAB bit of the
CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits
determine the ratio. The prescaler is cleared each time the instruction is written to TCC
under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared
by the “WDTC” or “SLEP” instructions. Figure 6-4 depicts the circuit diagram of
TCC/WDT.
R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be internal or
external clock input (edge selectable from TCC pin). If the TCC signal source is
from an internal clock, TCC will be incremented by 1 at FM / 2 or FM / 4 (without
prescaler). Referring to Figure 6-4, CLK= FM / 2 or CLK= FM / 4, depends on the
Code Option bit CLK. CLK= FM / 2 is used if CLK bit is "0", and CLK= FM / 4 is used
if CLK bit is "1". If the TCC signal source is from an external clock input, TCC is
incremented by 1 at every falling edge or rising edge of the TCC pin.
18
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep
running even when the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause
the device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming. Refer to WDTE bit of the IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms1 (Default).
TIMERSC (BANK1-RF)
1
Fm/2 or Fm/4
Data Bus
TCC (R1)
MUX
0
Fs
1
0
0
1
MUX
MUX
PAB
TCC Pin
TE (CONT)
TCC overflow
interrupt
TS
0
1
8-Bit Counter
8 to 1 MUX
MUX
PAB
WDT
1
0
WDTE
(IOCE)
PAB
MUX
WDT Time Out
Figure 6-4 TCC and WDT Block Diagram
6.4 I/O Ports
The I/O registers, Port 5, Port 6 and Port 70~71, are bidirectional tri-state I/O ports.
Port 6 can be pulled-high internally by software. In addition, Port 6 can also have
open-drain output by software. Input status changed interrupt (or wake-up) function is
available from Port 6. P50 ~ P52 and P60 ~ P63 pins can be pulled-down by software.
Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~
IOC7). The I/O registers and I/O control registers are both readable and writable. The
I/O interface circuits for Port 5, Port 6 and Port 7 are shown in Figure 6-5, Figure 6-6
and Figure 6-7 respectively.
1
Vdd = 5V, WDT time-out period = 16.8ms ± 30% at 25 C
Vdd = 3V, WDT time-out period = 18ms ± 30% at 25 C
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
19
EM78P176N
8-Bit Microcontroller with OTP ROM
PCRD
P
Q
D
R
PCWR
PDWR
CLK
_
C
L
Q
P
R
IOD
Port
Q
D
CLK
_
Q
C
L
PDRD
0
1
M
U
X
Note: Pull-down is not shown in the figure.
Figure 6-5 I/O Port and I/O Control Register Circuit for Port 5, 6 and Port 70~71
PCRD
P
Q
_
D
R
CLK
PCWR
PDWR
Q C
L
IOD
P
Q
_
Q C
L
Port
D
R
CLK
Bit 6 of
IOCE
0
1
P
M
U
X
D
Q
_
Q
R
CLK
C
L
T10
PDRD
P
D
Q
R
CLK
_
Q
C
L
Note: Pull-high (down) and open-drain are not shown in the figure.
Figure 6-6 I/O Port and I/O Control Register Circuit for P60 (/INT)
20
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
P
R
Q
_
Q
D
CLK
PCWR
PDWR
C
L
IOD
P
R
Q
D
PORT
_
Q
CLK
C
L
0
1
M
U
X
TIN
PDRD
P
R
D
Q
CLK
_
Q
C
L
Note: Pull-high (down) and open-drain are not shown in the figure.
Figure 6-7 I/O Port and I/O Control Register Circuit for P61~P67
ICIE
P
Q
D
R
CLK
Interrupt
_
Q
C
L
ICIF
ENI Instruction
P
R
P60
D
Q
P61
P62
P63
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
P64
P65
P66
C
L
P67
DISI Instruction
Interrupt
(Wake-up from
SLEEP)
/SLEP
Next Instruction
(Wake-up from
SLEEP)
Figure 6-8 Block Diagram of I/O Port 6 with input change interrupt/wake-up
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
21
EM78P176N
8-Bit Microcontroller with OTP ROM
Table 6-1 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 Input Status Change Wake-up/Interrupt
(I) Wake-up from Port 6 Input Status Change
(II) Port 6 Input Status Change Interrupt
1. Read I/O Port 6 (MOV R6,R6)
2. Execute “ENI”
(a) Before Sleep
1. Disable WDT
2. Read I/O Port 6 (MOV R6,R6)
3. Execute "ENI" or "DISI"
4. Enable interrupt (Set IOCF.1)
5. Execute "SLEP" instruction
(b) After Wake-up
3. Enable interrupt (Set IOCF.1)
4. IF Port 6 change (interrupt)
Interrupt Vector (008H)
1. IF "ENI" Interrupt Vector (008H)
2. IF "DISI" Next instruction
6.5 Reset and Wake-up
6.5.1 Reset
A Reset is initiated by one of the following events:
1) Power-on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
4) Low Voltage Reset
The device is kept under reset condition for a period of approximately 18 ms or
150 µs (Events 1 and 4 are approximately 18 ms and Events 2 and 3 are
approximately 150 µs) after a reset is detected.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state)
The Watchdog timer and prescaler are cleared.
When power is switched on, the upper 3 bits of R3 are cleared.
The bits of the CONT register are set to all "1" except for Bit 6 (INT flag).
The bits of the IOCB register are set to all "1".
The IOCC register is cleared.
The bits of the IOCD register are set to all "1".
Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared.
Bits 0 ~ 2 of RF and Bits 0 ~ 2 of IOCF registers are cleared.
22
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering Sleep mode, WDT (if enabled) is cleared but keeps on running. After a
wake-up, in IRC mode (IRC 4MHz / 5V) the wake-up time 1.5 µs, XT mode (4 MHz / 5V)
wake-up time is 1.5 ms.
The controller can be awakened by:
1) External reset input on /RESET pin
2) WDT time-out (if enabled)
3) Port 6 Input Status changed (if enabled)
4) External (P60, /INT) pin changes (if EXWE is enabled)
5) Low voltage detector (if LVDWE is enabled). The first two cases will cause the
EM78P176N to reset. The T and P flags of R3 are used to determine the source of
the reset (wake-up). The last case is considered the continuation of program
execution and the global interrupt ("ENI" or "DISI" being executed) determines
whether or not the controller branches to the interrupt vector following a wake-up. If
ENI is executed before SLEP, the instruction will begin to execute from Address
008H after a wake-up. If DISI is executed before SLEP, the operation will restart
from the succeeding instruction right next to SLEP after a wake-up.
After a wake-up in IRC mode (IRC 4 MHz / 5V), the wake-up time is 1.5 µs, in XT mode
(4 MHz / 5V), the wake-up time is 1.5 ms.
One or mode of Cases 2 and 5 can be enabled before going into Sleep mode. That is,
[a] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be
disabled. Hence, the EM78P176N can be awakened only by Case 1 or Case 2.
Refer to Section 6.6, Interrupt for further details.
[b] if Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be
disabled. Hence, the EM78P176N can be awakened only by Case 3.
[c] if External (P60,INT) pin change is used to wake-up EM78P176N and EXWE bit
of Bank 1-RE register is enabled before SLEP, WDT must be disabled. Hence, the
EM78P176N can be waken-up only by Case 4.
[d] if Low voltage detector is used to wake up the EM78P176N and LVDWE bit of Bank
0-RE register is enabled before SLEP, the WDT must be disabled by software.
Hence, the EM78P176N can be awakened only by Case 5.
If Port 6 Input Status Change Interrupt is used to wake-up the EM78P176N (Case [a]
above), the following instructions must be executed before SLEP:
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
23
EM78P176N
8-Bit Microcontroller with OTP ROM
MOV A, @xxxx1110b
; Select the WDT prescaler, it must be
; set over 1:1
CONTW
WDTC
; Clear WDT and prescaler
; Disable WDT
MOV A, @0xxxxxxxb
IOW RE
MOV R6, R6
MOV A, @00000x1xb
IOW RF
; Read Port 6
; Enable Port 6 input change interrupt
ENI (or DISI)
SLEP
; Enable (or disable) global interrupt
; Sleep
NOTE
1. After waking up from sleep mode, WDT is automatically enabled. The WDT
enable/disable operation after waking up from sleep mode should be appropriately
defined in the software.
2. To avoid a reset from occurring when the Port 6 Input Status Changed Interrupt enters
into interrupt vector or is used to wake-up the MCU, the WDT prescaler must be set
above the 1:1 ratio.
6.5.2 Wake-up and Interrupt Modes Operation Summary
The controller can be awakened from sleep mode and idle mode. The wake-up signals
are listed as follows.
Sleep Mode
ENI
Idle Mode
DISI ENI
Green Mode
DISI ENI
Normal Mode
DISI ENI
Wake-up Condition
Signal
Signal
DISI
EXWE = 0
EXIE = 0
Wake-up is invalid Wake-up is invalid
Wake-up is invalid Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
EXWE = 0
EXIE = 1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
External
INT
Wake up
+
Next Instruction
Wake up
+
Next Instruction
EXWE = 1
EXIE = 0
Wake up Wake up Wake up Wake up
EXWE = 1
EXIE = 1
+
Next
+
+
Next
+
Next
+
Next
+
Interrupt
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Wake-up is invalid Wake-up is invalid
Wake up Wake up Wake up Wake up
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
ICIE = 0
ICIE = 1
Port 6
Pin
+
+
+
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Vector Vector
+
Next
+
change
Next
Interrupt
Next
Instruction Vector Instruction Vector
24
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
(Continuation)
Sleep Mode
ENI
Idle Mode
DISI ENI
Green Mode
DISI ENI
Normal Mode
DISI ENI
Wake-up Condition
Signal
Signal
DISI
TCIE = 0
Wake-up is invalid
Wake up Wake up
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
TCC
Wake-up is invalid
+
+
+
+
Next
Next
Overflow
TCIE = 1
Next
Interrupt
Interrupt
Vector
Interrupt
Vector
Instruction
Instruction
Instruction Vector
LVDWE = 0
LVDIE = 0
Wake-up is invalid Wake-up is invalid
Wake-up is invalid Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
+
LVDWE = 0
LVDIE = 1
Next
Next
+
Interrupt
Vector
Instruction
Instruction Interrupt
Vector
Low
Voltage
Detector
Wake up
+
Wake up
+
LVDWE = 1
LVDIE = 0
Interrupt is invalid
Interrupt
Interrupt is invalid
Next Instruction
Next Instruction
Wake up
+
Wake up Wake up Wake up
Interrupt
LVDWE = 1
LVDIE = 1
+
+
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Vector Vector
+
Next
+
Next
Interrupt
Next
Instruction
Vector Instruction Vector
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
25
EM78P176N
8-Bit Microcontroller with OTP ROM
6.5.3 Summary of Registers Initialized Values
Address
Name
Reset Type
Bit Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
C57 C56 C55 C54 C53 C52 C51 C50
Power-on
1
1
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
N/A
IOC5
/RESET and WDT
Wake-up
P
C67
1
Bit Name
C66 C65 C64 C63
C62 C61 C60
Power-on
1
1
1
1
P
0
0
P
1
1
P
0
0
P
1
1
1
1
1
1
P
1
1
P
N/A
N/A
IOC6
IOC7
P6
/RESET and WDT
Wake-up
1
P
0
P
0
P
P
Bit Name
C71 C70
0
0
Power-on
1
1
P
1
1
P
/RESET and WDT
Wake-up
0
0
0
0
P
P57
1
P
P56
1
P
P
Bit Name
P55 P54
P53
1
P52
1
P51 P50
Power-on
1
P
P
1
P
P
1
P
P
1
P
P
006
006
007
N/A
/RESET and WDT
Wake-up
P
P
P67
1
P
P
P66
1
P
P
P
P
Bit Name
P65 P64
P63
1
P62
1
P61 P60
Power-on
1
P
P
1
P
P
1
P
P
1
P
P
P6
/RESET and WDT
Wake-up from Pin Change
Bit Name
P
P
P
P
P
P
P
P
P71 P70
0
0
Power-on
0
0
0
0
1
P
P
1
P
P
P7
/RESET and WDT
Wake-up
0
0
0
0
0
0
P
GP
1
P
INT
0
P
TS
1
P
TE
1
P
P
Bit Name
PAB PSR2 PSR1 PSR0
Power-on
1
1
P
-
1
1
P
-
1
1
P
-
1
1
P
-
CONT
R0 (IAR)
R1 (TCC)
/RESET and WDT
Wake-up from Pin Change
Bit Name
1
0
1
1
P
-
P
-
P
-
P
-
Power-on
U
P
P
-
U
P
P
-
U
P
P
-
U
P
P
-
U
P
P
-
U
P
P
-
U
P
P
-
U
P
P
-
000
001
/RESET and WDT
Wake-up
Bit Name
Power-on
0
0
0
0
0
0
P
-
0
0
P
-
0
0
P
-
0
0
P
-
/RESET and WDT
Wake-up
0
0
0
0
P
-
P
-
P
-
P
-
Bit Name
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
R2 (PC)
002
/RESET and WDT
0
0
0
0
Jump to Address 0x08 or continue to execute next
instruction
Wake-up
26
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
(Continuation)
Address
Name
Reset Type
Bit Name
Bit 7
RST
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
GP1
GP0
T
1
*
*
-
P
1
*
*
-
Z
U
P
P
-
DC
U
P
C
U
P
P
-
Power-on
0
0
0
P
-
R3 (SR)
003
/RESET and WDT
Wake-up
0
0
P
1
P
Bit Name
GP
Bank 0
-
Power-on
0
0
0
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
R4 (RSR)
004
/RESET and WDT
Wake-up
0
P
P
P
P
/LVD
1
LVDIF
LVDWE
Bit Name
Bank 0
RE
Power-on
0
0
P
0
0
0
0
0
0
0
00E
00F
005
/RESET and WDT
1
0
0
0
0
0
(LVDCR)
Wake-up
P
P
P
P
P
EXIF
0
P
ICIF
0
P
TCIF
0
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power-on
Bank 0
RF (ISR)
/RESET and WDT
Wake-up
0
0
0
P
P
P
Bit Name
MLB
RBit 9 RBit 8
0
0
P
0
0
P
0
0
P
0
0
P
Bank 1
Power-on
0
0
0
0
P
0
0
P
R5
(TBHP)
/RESET and WDT
Wake-up
0
0
P
RBit7
0
P
Bit Name
RBit 6
RBit 5 RBit 4 RBit 3 RBit 2 RBit 1 RBit 0
Bank 1
Power-on
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
006
R6
(TBLP)
/RESET and WDT
0
Wake-up
P
P
Bit Name
LVDIE LVDEN
LVD1 LVD0
EXWE
0
0
P
0
0
0
P
0
0
0
P
Bank 1
RE (LVD
ICR)
Power-on
/RESET and WDT
Wake-up
0
0
P
0
0
0
P
1
1
P
1
1
P
0
0
P
00E
00F
Bit Name
TIMERSC CPUS IDLE
RCM1 RCM0
Bank 1
RF (SC &
COCR)
Power-on
1
1
P
1
1
P
0
0
P
Word 1
<6,5>
/RESET and WDT
Wake-up
0
0
P
x
0
P
P
P
P
Bit Name
/PD63 /PD62
/PD61 /PD60
/PD52 /PD51 /PD50
Power-on
1
1
1
1
P
1
1
P
1
1
1
1
1
P
1
1
P
1
1
P
IOCB
IOCC
00B
00C
/RESET and WDT
Wake-up
1
1
P
P
Bit Name
OD67
OD66
OD65 OD64 OD63 OD62 OD61 OD60
Power-on
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
0
0
P
/RESET and WDT
Wake-up
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
27
EM78P176N
8-Bit Microcontroller with OTP ROM
(Continuation)
Address
Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH67 /PH66 /PH65 /PH64 /PH63 /PH62 /PH61 /PH60
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOCD
00D
/RESET and WDT
Wake-up
1
P
P
EIS
0
P
GP
1
P
GP
1
P
GP
1
P
P
P
Bit Name
WDTE
GP
1
GP
1
GP
1
Power-on
1
1
1
1
1
1
-
IOCE
IOCF
00E
00F
/RESET and WDT
Wake-up
0
1
1
1
1
1
1
P
1
P
1
P
1
P
1
P
P
P
Bit Name
EXIE
0
ICIE
0
TCIE
0
Power-on
/RESET and WDT
Wake-up
1
1
1
1
0
0
0
1
1
1
1
P
P
P
Bit Name
-
-
-
-
-
-
-
Power-on
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
U
P
U
010~
03F
R10~R3F
/RESET and WDT
Wake-up
P
P
P
P
P
Legend: : Not used U: Unknown or don’t care P: Previous value before reset
* Refer to the tables provided in the next section (Section 6.5.4).
6.5.4 Status of RST, T, and P of the Status Register
A Reset condition is initiated by the following events
1) A power-on condition
2) A high-low-high pulse on /RESET pin
3) Watchdog timer time-out
The values of T and P listed in the table below are used to check how the processor
wakes up.
Table 6-2 Values of RST, T, and P after a Reset
Reset Type
RST
T
1
P
1
Power on
0
0
0
0
0
1
/RESET during Operating mode
/RESET wake-up during Sleep mode
WDT during Operating mode
*P
1
*P
0
0
*P
0
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
1
0
* P: Previous status before reset
28
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
The following table shows the events that may affect the status of T and P.
Table 6-3 Status of T and P Being Affected by Events
Event
RST
0
T
1
1
0
1
1
P
1
Power on
WDTC instruction
WDT time-out
SLEP instruction
*P
0
1
*P
0
*P
1
Wake-up on pin change during Sleep mode
0
* P: Previous status before reset
VDD
D
CLK
Q
CLK
Oscillator
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT
Setup Time
RESET
Timeout
/RESET
Figure 6-9 Controller Reset Block Diagram
6.6 Interrupt
The EM78P176N has four interrupts as listed below:
1) TCC overflow interrupt
2) Port 6 Input Status Change Interrupt
3) External interrupt [(P60, /INT) pin]
4) Low Voltage Detect Interrupt
Before the Port 6 Input Status Changed Interrupt is enabled, reading Port 6 (e.g. "MOV
R6, R6") is necessary. Each pin of Port 6 will have this feature if its status changes.
Any pin configured as output or P60 pin configured as /INT is excluded from this
function. The Port 6 Input Status Changed Interrupt can wake up the EM78P176N from
Sleep mode if Port 6 is enabled prior to going into Sleep mode by executing SLEP
instruction. When the chip wakes-up, the controller will continue to execute the
program in-line if the global interrupt is disabled. If the global interrupt is enabled, it will
branch to the interrupt Vector 008H.
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
29
EM78P176N
8-Bit Microcontroller with OTP ROM
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(enabled) occurs, the next instruction will be fetched from Address 008H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to Figure 6-10). The RETI instruction ends the
interrupt routine and enables the global interrupt (the execution of ENI).
VCC
P
IRQn
D
Q
_
Q
R
/IRQn
CLK
INT
C
IRQm
RFRD
L
RF
ENI/DISI
P
IOD
Q
_
Q
D
CLK
R
C
IOCFWR
L
IOCF
/RESET
IOCFRD
RFWR
Figure 6-10 Interrupt Input Circuit
Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4
registers will be saved by the hardware. If another interrupt occurs, the ACC, R3, and
R4 will be replaced by the new interrupt. After the interrupt service routine is
completed, the ACC, R3, and R4 registers are restored.
Interrupt
Interrupt sources
occurs
ACC
STACKACC
ENI/DISI
R3
R4
STACKR3
STACKR4
RETI
Figure 6-11 Interrupt Backup Diagram
30
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
6.7 Oscillator
6.7.1 Oscillator Modes
The EM78P176N can be operated in four different oscillator modes, such as External
RC oscillator mode (ERC), Internal RC oscillator mode (IRC), High Crystal oscillator
mode (XT, HXT12), and Low Crystal oscillator mode (LXT1, 2). The desired mode can
be selected by programming OSC3, OSC2, OSC1 and OSC0 in the Code Option
register. Table 6-4 shows how these four oscillator modes are defined.
Table 6-4 Oscillator Modes Defined by OSC
Oscillator Modes
OSC3 OSC2 OSC1 OSC0
ERC1 (External RC oscillator mode); P70/RCOUT act as P70
ERC1 (External RC oscillator mode); P70/RCOUT act as RCOUT
IRC2 (Internal RC oscillator mode); P70/RCOUT act as P70
IRC2 (Internal RC oscillator mode); P70/RCOUT act as RCOUT
LXT13 (Frequency range of LXT1 mode is 1MHz~100kHz)
HXT13 (Frequency range of HXT1 mode is 20 MHz~12 MHz)
LXT23 (Frequency range of LXT2 mode is 32.768kHz)
HXT23 (Frequency range of HXT2 mode is 12 MHz~6 MHz)
XT (Frequency range of XT mode is 6 MHz~1 MHz) (default)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
1 In ERC mode, ERCin is used as oscillator pin. RCOUT/P70 is defined by Code Option Word 1
Bit 4 ~ Bit 1.
2 In IRC mode, P55 is normal I/O pin. RCOUT/P70 is defined by code option Word 1 Bit 4 ~ Bit 1.
3 In LXT1, LXT2, HXT1, HXT2 and XT modes; OSCI and OSCO are used as oscillator pins.
These pins cannot and should not be defined as normal I/O pins.
The maximum operational frequency of the crystal/resonator under different VDD is
listed below.
Table 6-5 Summary of Maximum Operating Speeds
Conditions
VDD
Max Freq. (MHz)
2.1
4.0
Two cycles with two clocks
3.0
5.0
8.0
20.0
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
31
EM78P176N
8-Bit Microcontroller with OTP ROM
6.7.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P176N can be driven by an external clock signal through the OSCI pin as
shown in the following figure.
OSCI
Ext. Clock
OSCO
EM78P176N
Figure 6-12 Circuit for External Clock Input
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Figure 6-13 depicts such a circuit. The
same thing applies whether it is in the HXT mode or in the LXT mode.
In Figure 6-14, when the connected resonator in OSCI and OSCO is used in
applications, the 1 M R1 needs to be shunted with resonator.
C1
OSCI
EM78P176N
Crystal
OSCO
C2
RS
Figure 6-13 Circuit for Crystal/Resonator
32
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
C1
OSCI
EM78P176N
OSCO
Resonator
R1
C2
Figure 6-14 Circuit for Crystal/Resonator
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attribute, refer to its specification for appropriate values of C1 and
C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency
mode.
Table 6-6 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode
Frequency
100 kHz
200 kHz
455 kHz
1 MHz
C1 (pF)
60pF
60pF
40pF
30pF
30pF
30pF
20pF
40pF
60pF
60pF
40pF
30pF
30pF
30pF
30pF
20pF
30pF
30pF
20pF
30pF
30pF
30pF
20pF
15pF
C2 (pF)
60pF
60pF
40pF
30pF
30pF
30pF
20pF
40pF
60pF
60pF
40pF
30pF
30pF
30pF
30pF
20pF
30pF
30pF
20pF
30pF
30pF
30pF
20pF
15pF
LXT1
(100k ~ 1 MHz)
Ceramic Resonators
1.0 MHz
2.0 MHz
4.0 MHz
32.768 kHz
100 kHz
200 kHz
455 kHz
1 MHz
XT
(1 ~ 6 MHz)
LXT2 (32.768kHz)
LXT1
(100k ~ 1 MHz)
455 kHz
1.0 MHz
2.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
8.0 MHz
10.0 MHz
12.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
XT
(1 ~ 6 MHz)
Crystal Oscillator
HXT2
(6 ~ 12 MHz)
HXT1
(12 ~ 20 MHz)
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
33
EM78P176N
8-Bit Microcontroller with OTP ROM
6.7.3 External RC Oscillator Mode
For some applications that do not require a very precise timing calculation, the RC
oscillator (Figure 6-15) offers a cost-effective oscillator configuration. Nevertheless, it
should be noted that the frequency of the RC oscillator is influenced by the supply
voltage, the values of the resistor (REXT), the capacitor (CEXT), and even by the
operation temperature. Moreover, the frequency also changes slightly from one chip to
another due to manufacturing process variations.
In order to maintain a stable system frequency, the values of the CEXT should not be
less than 20pF, and that the value of REXT should not be greater than 1 M. If they
cannot be kept in this range, the frequency can be easily affected by noise, humidity,
and leakage.
The smaller the REXT in the RC oscillator is, the faster its frequency will be. On the
contrary, for very low REXTvalues, for instance, 1 k, the oscillator becomes unstable
because the NMOS cannot correctly discharge the current of the capacitance.
Based on the above reasons, it must be kept in mind that all the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
way the PCB is layout, will affect the system frequency.
Vcc
Rext
ERCin
Cext
EM78P176N
Figure 6-15 External RC Oscillator Mode Circuit
34
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
Table 6-7 RC Oscillator Frequencies
Average Fosc
Average Fosc
Cext
Rext
5V, 25C
3V, 25C
3.3k
5.1k
10k
2.064 MHz
1.403 MHz
750kHz
1.901 MHz
1.316 MHz
719.7kHz
81.33kHz
615.1 MHz
414.3kHz
219.8kHz
23.96kHz
245.3kHz
163.0kHz
86.14kHz
9.255kHz
20pF
100k
3.3k
5.1k
10k
81.45kHz
647.3kHz
430.8kHz
225.8kHz
23.88kHz
256.6kHz
169.5kHz
88.53kHz
9.283kHz
100pF
300pF
100k
3.3k
5.1k
10k
100k
Note: 1: These are measured in DIP packages.
2. The values are for design reference only.
3. The frequency drift is 30%.
6.7.4 Internal RC Oscillator Mode
EM78P176N offers a versatile internal RC mode with default frequency value of
4 MHz. The Internal RC oscillator mode has other frequencies (1 MHz, 8 MHz, and
16 MHz) that can be set by Code Option (Word 1), RCM1, and RCM0. All these four
main frequencies can be calibrated by programming the Option Bits C0 ~ C4. The
table below describes the EM78P176N internal RC drift with variation of voltage,
temperature, and process.
Table 6-8 Internal RC Drift Rate (TA = 25C, VDD = 5V, VSS = 0V)
Drift Rate
Internal RC
Temperature
(-40C~85C)
Voltage
(2.1V~5.5V)
Process
± 2%
Total
± 6%
± 4%
± 5%
± 6%
± 3%
4 MHz
16 MHz
8 MHz
1 MHz
± 1%
± 1%
± 1%
± 1%
(2.1~5.5V)
± 1%
± 2%
(4.0~5.5V)
± 2%
± 2%
(3.0~5.5V)
± 3%
± 2%
(2.1~5.5V)
Note: These are theoretical values provided for reference only. Actual values may vary
depending on the actual process.
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
35
EM78P176N
8-Bit Microcontroller with OTP ROM
6.8 Code Option Register
The EM78P176N has a Code Option word that is not a part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register Arrangement Distribution:
Word 0
Word 1
Word 2
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
6.8.1 Code Option Register (Word 0)
Word 0
Bit
Bit 12
Bit 11 Bit 10 Bit9
Bit8
Bit7 Bit6 Bit5
Bit4
Bit3
Bits2~0
Mnemonic RESETEN ENWDT CLKS LVR1 LVR0
NRHL NRE
Protect
1
0
Disable Disable 4clocks High
Enable Enable 2clocks Low
High
Low
32/fc Enable Disable
8/fc Disable Enable
Bit 12 (RESETEN): Define Pin 71 as a reset pin
0: /RESET enable
1: /RESET disable
Bit 11 (ENWDT): Watchdog timer enable bit
0: Enable
1: Disable
Bit 10 (CLKS): Instruction period option bit.
0: Two oscillator periods
1: Four oscillator periods
Refer to the Instruction Set section.
Bits 9 ~ 8 (LVR1 ~ LVR0): Low Voltage Reset control bits
VDD Reset Level
LVR1, LVR0
VDD Release Level
11
10
01
00
NA (Power-on Reset) (default)
2.7V
3.5V
4.0V
2.9V
3.7V
4.0V
Bit 7: Not used. Set to “1” at all time.
Bit 6 and Bit 5: Not used. Set to “1” at all time.
36
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
Bit 4 (NRHL): Noise rejection high/low pulse define bit. INT pin has a falling edge
trigger.
0: Pulses equal to 8/fc is regarded as signal
1: Pulses equal to 32/fc is regarded as signal (Default)
Bit 3 (NRE): Noise rejection enable
0: Disable noise rejection
1: Enable noise rejection (default). However in Low Crystal oscillator
(LXT2) mode, the noise rejection circuit is always disabled.
Bits 2 ~ 0 (Protect): Protect Bits. Each protect status is as follows:
Protect Bits
Protect
0
1
Enable
Disable (Default)
6.8.2 Code Option Register (Word 1)
Word 1
Bit Bit12 Bit11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit2 Bit1
Bit 0
Mne
HLP C4 C3
C2
C1
C0 RCM1 RCM0 OSC3 OSC2 OSC1 OSC0
RCOUT
monic
1
0
High High High High High High High High High High High High System-clock
Low Low Low Low Low Low Low Low Low Low Low Low Open-drain
Bit 12 (HLP): Power consumption mode
0: Low power consumption mode, applies to operating frequency at
400kHz or below 400kHz
1: High power consumption mode, applies to operating frequency above
400kHz (default)
Bits 11 ~ 7 (C4 ~ C0): Internal RC mode Calibration bits. These bits must always be
set to “1” only (auto calibration)
Bit 6 and Bit 5 (RCM1, RCM0): RC mode selection bits
RCM 1
RCM 0
*Frequency (MHz)
1
1
0
0
1
0
1
0
4
16
8
1
* Theoretical values, for reference only
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
37
EM78P176N
8-Bit Microcontroller with OTP ROM
Bits 4 ~ 1 (OSC3, OSC2, OSC1 and OSC0): Oscillator Mode Selection bits
Oscillator Modes
OSC3 OSC2 OSC1 OSC0
ERC1 (External RC oscillator mode); P70/RCOUT act as P70
ERC1 (External RC oscillator mode); P70/RCOUT act as RCOUT
IRC2 (Internal RC oscillator mode); P70/RCOUT act as P70
IRC2 (Internal RC oscillator mode); P70/RCOUT act as RCOUT
LXT13 (Frequency range of LXT1 mode is 1MHz~100kHz)
HXT13 (Frequency range of HXT1 mode is 20 MHz~12 MHz)
LXT23 (Frequency range of LXT2 mode is 32.768kHz)
HXT23 (Frequency range of HXT2 mode is 12 MHz~6 MHz)
XT (Frequency range of XT mode is 6 MHz~1 MHz) (default)
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
1 In ERC mode, ERCin is used as oscillator pin. RCOUT/P70 is defined by code option Word 1
Bit 4 ~ Bit 1.
2 In IRC mode, P55 is normal I/O pin. RCOUT/P70 is defined by code option Word 1 Bit 4 ~ Bit 1.
3 In LXT1, LXT2, HXT1, HXT2 and XT modes; OSCI and OSCO are used as oscillator pins.
These pins cannot and should not be defined as normal I/O pins.
Bit 0 (RCOUT): System clock or open-drain enable bit in IRC or ERC mode
0: RCOUT pin is open drain
1: RCOUT output system clock (Default)
6.8.3 Customer ID Register (Word 2)
Word 2
Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mne
SFS TYPE ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
monic
1
0
16K 20 PIN High High High High High High High High High High
128K 18 PIN Low Low Low Low Low Low Low Low Low Low
Bit 12: Not used. Set to “1” at all time.
Bit 11 (SFS): Sub Frequency Select for Green mode.
(Not included WDT time out and POR release setup-up time)
0: 128kHz
1: 16kHz (Default)
Bit 10 (TYPE): Type selection for EM78P176N
Type
MCU Type
EM78P176N-18Pin
EM78P176N-20Pin (Default)
0
1
Bits 9 ~ 0: Customer’s ID code
38
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
6.9 Power-on Consideration
Any microcontroller is not guaranteed to start to operate properly before the power
supply stabilizes at its steady state. Under customer application, when power is OFF,
Vdd must drop to below 1.8V and remains OFF for 10 µs before power can be switched
ON again. This way, the EM78P176N will reset and operate normally. The extra
external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less).
However, under most cases where critical applications are involved, extra devices are
required to assist in solving the power-up problems.
6.10 External Power-on Reset Circuits
The circuitry in the figure
implements an external RC
Vdd
to produce the reset pulse.
R
The pulse width (time
constant) should be kept
long enough for Vdd to
reach minimum operation
voltage. This circuit is
used when the power
supply has a slow rise
time.
/RESET
D
EM78P176N
Rin
C
Figure 6-16 External Power-up Reset Circuit
Since the current leakage from the /RESET pin is 5 A, it is recommended that R
should not be greater than 40k. In this way, the /RESET pin voltage is held below 0.2V.
The diode (D) acts as a short circuit at the moment of power down. The capacitor C will
discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or
ESD (electrostatic discharge) from flowing to pin /RESET.
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
39
EM78P176N
8-Bit Microcontroller with OTP ROM
6.11 Residue-Voltage Protection
When the battery is replaced, the device power (Vdd) is cut off but the residue-voltage
remains. The residue-voltage may trip below the minimum Vdd, but not to zero. This
condition may cause a poor power-on reset. The following figures illustrate two
recommended methods on how to build a residue-voltage protection circuit for the
EM78P176N.
Vdd
Vdd
33K
EM78P176N
/RESET
Q1
10K
100K
1N4684
Figure 6-17 Residue Voltage Protection Circuit 1
Vdd
Vdd
R1
EM78P176N
/RESET
Q1
R3
R2
Figure 6-18 Residue Voltage Protection Circuit 2
NOTE
Figure 6-17 and Figure 6-18 should be designed to ensure that the voltage of the
/RESET pin is larger than VIH (min).
40
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
6.12 Low Voltage Detector
When an unstable power source condition occurs, such as external power noise
interference or EMS test condition, a violent power vibration is generated. At the same
time, the Vdd becomes unstable as it could be operating below working voltage. When
the system supply voltage (Vdd) is below the operating voltage, the IC kernel will
automatically keep all register status.
6.12.1 Low Voltage Reset (LVR)
LVR property is set at Bits 9 and 8 of Code Option Word 0. Detailed operation mode is
as follows:
Word 0
Bit 12
Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2~ Bit0
NRHL NRE Protect
RESETEN ENWDT CLKS LVR1 LVR0
Bits 9 ~ 8 (LVR1 ~ LVR0): Low Voltage Reset enable bits
LVR1, LVR0
VDD Reset Level
VDD Release Level
11
10
01
00
N/A (Power-on Reset)
2.7V
3.5V
4.0V
2.9V
3.7V
4.2V
6.12.2 Low Voltage Detector (LVD)
LVD property is set at Registers Bank 0-RE and Bank 1-RE. Detailed operation mode
is explained below.
6.12.2.1 Bank 0 RE (LVD Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
-
-
-
-
-
LVDWE
Bit 7 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin
voltage is lower than the LVD voltage interrupt level (selected by LVD1
and LVD0), this bit will be cleared.
0: Low voltage is detected.
1: Low voltage is not detected or LVD function is disabled.
Bit 6 (LVDIF): Low Voltage Detector Interrupt Flag
LVDIF is reset to “0” by software or hardware
“1” means there’s interrupt request
“0” means no interrupt occurs
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
41
EM78P176N
8-Bit Microcontroller with OTP ROM
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit
0: Disable Low Voltage Detect wake-up
1: Enable Low Voltage Detect wake-up
When the Low Voltage Detect is used to enter interrupt vector or to
wake-up IC from Sleep/Idle mode with the Low Voltage Detect running,
the LVDWE bit must be set to “Enable.“
6.12.2.2 Bank 1 RE (LVD Interrupt and Wake-up Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIE
LVDEN
LVD1
LVD0
-
-
-
EXWE
NOTE
The BANK1-RE <7> register is both readable and writable.
Individual interrupt is enabled by setting its associated control bit in the
BANK1-RE<7> to "1."
Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Figure 6-10 (Interrupt Input Circuit) in Section 6.6 (Interrupt).
Bit 7 (LVDIE): Low voltage Detector interrupt enable bit
0: Disable Low Voltage Detector interrupt
1: Enable Low Voltage Detector interrupt
When a detected low level voltage state is used to enter an interrupt
vector or enter the next instruction, the LVDIE bit must be set to “Enable.”
Bit 6 (LVDEN): Low Voltage Detector enable bit
0: Disable Low voltage detector
1: Enable Low voltage detector
Bits 5 ~ 4 (LVD1 ~ LVD0): Low Voltage Detector level bits
LVDEN
LVD1, LVD0
LVD Voltage Interrupt Level
Vdd 2.2V
Vdd 2.2V
Vdd 3.3V
Vdd 3.3V
Vdd 4.0V
Vdd 4.0V
Vdd 4.5V
Vdd 4.5V
NA
/LVD
0
1
0
1
0
1
0
1
1
1
11
1
1
10
01
1
0
00
42
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
NOTE
IF Vdd has crossover at LVD voltage in interrupt level as VDD varies, LVD interrupt
will occur.
6.12.3 Programming Process
Follow these steps to obtain data from the LVD:
1. Write to the two bits (LVD1: LVD0) on the BANK1-RE (LVDCR) register to define
the LVD level
2. Set the LVDWE bit if the wake-up function is in use.
3. Set the LVDIE bit if the interrupt function is in use.
4. Write “ENI” instruction if the interrupt function is in use.
5. Set LVDEN bit to “1”
6. Write “SLEP” instruction or Polling /LVD bit
7. Clear the interrupt flag bit (LVDIF) when Low Voltage Detect occurs.
NOTE
The internal LVD module uses the internal circuit, and when the code option is set to
enable the LVD module, the current consumption will increase to about 5 µA.
During Sleep mode, the LVD module continues to operate. If the device voltage
drops slowly and crosses the detection point, the LVDIF bit will be set and the device
will wake up from Sleep mode. The LVD interrupt flag will remain set at priority
status.
When the system resets, the LVD flag is cleared.
The following figure shows the LVD module detection point in an external voltage
condition.
LVDIF is cleared by software
Vdd
VLVD
VRESET
LVDIF
Internal
18ms
Reset
<LVR Voltage drop
>LVR Voltage drop
Vdd < Vreset not longer than 80us, the system still keeps on operating
System occur reset
Figure 6-19 LVD/LVR Waveform with the Detection Point in an External Voltage Condition
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
43
EM78P176N
8-Bit Microcontroller with OTP ROM
When the Vdd drops, but above VLVD, the LVDIF is kept at “0”.
When Vdd drops below VLVD, the LVDIF is set to “1”. If global ENI is enabled, the
LVDIF is also set to “1” and the next instruction will branch to an interrupt vector.
The LVD interrupt flag is cleared to “0” by software.
When Vdds drops below VRESET at less than 80 µs, the system will keep all the
registers’ status and halts it operation, but with the oscillation remaining active.
When Vdd drops below VRESET at more than 80 µs, a system reset will occur.
Refer to Section 6.5.1, Reset for the detailed Reset description.
6.13 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of two oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6", "CLR R2", etc.). In this case,
the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
A) Modify one instruction cycle to consist of four oscillator periods.
B) "JMP", "CALL", "RET", "RETL", "RETI" or the conditional skip ("JBS", "JBC", "JZ",
"JZA", "DJZ”, "DJZA") commands which were tested to be true, are executed within
one instruction cycle. The instructions that are written to the program counter also
take one instruction cycle.
Case (A) is selected by the Code Option bit, called CLK. One instruction cycle consists
of two oscillator clocks if CLK is low; and four oscillator clocks if CLK is high.
Note that once the four oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead of Fosc/2.
Moreover, the instruction set has the following features:
1) Every bit of any register can be set, cleared, or tested directly.
2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
44
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
The following symbols are used in the Instruction Set table:
Convention:
R = Register designator that specifies which one of the registers (including operation and general
purpose registers) is to be utilized by the instruction.
Bit 6 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects
the operation.
k = 8 or 10-bit constant or literal value
Binary Instruction
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
Hex
0000
Mnemonic
NOP
Operation
No Operation
Status Affected
None
0001
0002
0003
0004
000r
0010
0011
0012
DAA
Decimal Adjust A
A CONT
C
CONTW
SLEP
WDTC
IOW R
ENI
None
0 WDT, Stop oscillator
0 WDT
T, P
T, P
None 1
A IOCR
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
None
DISI
None
RET
None
[Top of Stack] PC,
Enable Interrupt
0 0000 0001 0011
0013
RETI
None
0 0000 0001 0100
0 0000 0001 rrrr
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0014
001r
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
CONTR
IOR R
CONT A
IOCR A
A R
None
None 1
MOV R,A
CLRA
None
0 A
Z
CLR R
0 R
Z
SUB A,R
SUB R,A
DECA R
DEC R
R-A A
R-A R
R-1 A
Z, C, DC
Z, C, DC
Z
R-1 R
Z
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
A R A
A R R
A & R A
A & R R
A R A
A R R
A + R A
A + R R
Z
Z
Z
Z
Z
Z
Z, C, DC
Z, C, DC
1 This instruction is applicable to IOC5~IOC6, IOCB ~ IOCF only.
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
45
EM78P176N
8-Bit Microcontroller with OTP ROM
(Continuation)
Binary Instruction
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
Hex
04rr
Mnemonic
MOV A,R
MOV R,R
COMA R
COM R
Operation
Status Affected
R A
R R
/R A
/R R
Z
04rr
04rr
04rr
05rr
05rr
05rr
05rr
Z
Z
Z
INCA R
INC R
R+1 A
Z
R+1 R
Z
DJZA R
DJZ R
R-1 A, skip if zero
R-1 R, skip if zero
None
None
R(n) A(n-1),
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
06rr
06rr
06rr
06rr
07rr
RRCA R
RRC R
C
C
R(0) C, C A(7)
R(n) R(n-1),
R(0) C, C R(7)
R(n) A(n+1),
R(7) C, C A(0)
R(n) R(n+1),
R(7) C, C R(0)
R(0-3) A(4-7),
R(4-7) A(0-3)
RLCA R
RLC R
C
C
SWAPA R
None
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
0 101b bbrr rrrr
0 110b bbrr rrrr
0 111b bbrr rrrr
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
SWAP R
JZA R
R(0-3) R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 R(b)
None
None
None
None 2
None 3
None
None
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 [SP],
(Page, k) PC
1 00kk kkkk kkkk
1kkk
CALL k
None
1 01kk kkkk kkkk
1 1000 kkkk kkkk
1 1001 kkkk kkkk
1 1010 kkkk kkkk
1 1011 kkkk kkkk
1kkk
18kk
19kk
1Akk
1Bkk
JMP k
(Page, k) PC
k A
None
MOV A,k
OR A,k
AND A,k
XOR A,k
None
A k A
A & k A
A k A
Z
Z
Z
k A,
[Top of Stack] PC
1 1100 kkkk kkkk
1Ckk
RETL k
None
1 1101 kkkk kkkk
1 1111 kkkk kkkk
1 1110 1001 kkkk
1Dkk
1Fkk
1E9k
SUB A,k
ADD A,k
BANK k
k-A A
k+A A
k R4(6)
Z, C,DC
Z, C, DC
None
If Bank1 R5.7=0,
machine code (7:0) R
Else
1 1110 11rr rrrr
1Err
TBRD R
None
Bank1 R5.7 = 1
machine code (12:8)
R(4:0),
R(7:5)=(0,0,0)
Note: 2 This instruction is not recommended for interrupt status register operation.
3 This instruction cannot operate under interrupt status register.
46
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
7 Absolute Maximum Ratings
EM78P176N
Items
Rating
85 C
Temperature under bias
Storage temperature
Input voltage
-40 C
to
to
to
to
to
to
-65 C
150 C
Vss-0.3V
Vss-0.3V
2.1V
Vdd+0.5V
Vdd+0.5V
5.5V
Output voltage
Working Voltage
Working Frequency
DC
20 MHz
NOTE
These parameters are theoretical values and have not been tested.
8 Electrical Characteristics
8.1 DC Characteristics
Ta=25C, VDD=5V, VSS=0V
Symbol
Parameter
Crystal: VDD to 2.1V
Condition
Min. Typ. Max. Unit
Two cycles with two clocks DC
Two cycles with two clocks DC
Two cycles with two clocks DC
4.0
8.0
MHz
MHz
FXT
Crystal: VDD to 3V
Crystal: VDD to 5V
20.0 MHz
ERC
IIL
ERC: VDD to 5V
R: 5K, C: 39pF
VIN = VDD, VSS
Ports 5, 6, 7
F30 1500 F30 kHz
Input Leakage Current for input pins
1
µA
V
VIH1 Input High Voltage (VDD=5V)
2.0
VIL1
Input Low Voltage (VDD=5V)
Ports 5, 6, 7
0.8
V
Input High Threshold Voltage
(VDD=5V)
/RESET, TCC
(Schmitt trigger)
/RESET, TCC
(Schmitt trigger)
VIHT1
2.0
V
V
VILT1 Input Low Threshold Voltage (VDD=5V)
0.8
VIHX1 Clock Input High Voltage (VDD=5V)
VILX1 Clock Input Low Voltage (VDD=5V)
VIH2 Input High Voltage (VDD=3V)
OSCI
2.5
V
V
V
V
OSCI
1.0
Ports 5, 6, 7
Ports 5, 6, 7
1.5
VIL2
Input Low Voltage (VDD=3V)
0. 4
Input High Threshold Voltage
(VDD=3V)
/RESET, TCC
(Schmitt trigger)
/RESET, TCC
(Schmitt trigger)
VIHT2
1.5
V
V
VILT2 Input Low Threshold Voltage (VDD=3V)
0.4
VIHX2 Clock Input High Voltage (VDD=3V)
VILX2 Clock Input Low Voltage (VDD=3V)
OSCI
OSCI
1.5
V
V
0.6
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
47
EM78P176N
8-Bit Microcontroller with OTP ROM
Symbol
Parameter
Condition
IOH = -12mA
Min. Typ. Max. Unit
Output High Voltage
(Port 5, Port 6, Port 7)
VOH1
2.4
V
V
Output Low Voltage
(P50~54, P56~57, Port 6)
(Schmitt trigger)
VOL1
IOL = 12mA
0.4
VOL2
VOL3
IOL = 16.0mA
IOL = 20mA
0.4
0.4
V
V
Output Low Voltage (P70, P55)
Output Low Voltage (P71)
Pull-high active,
Input pin at VSS
70
30
IPH
IPD
Pull-high current
Pull-down current
µA
µA
Pull-down active,
Input pin at VDD
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
ISB1 Power down current
ISB2 Power down current
1
µA
µA
All input and I/O pins at VDD,
Output pin floating,
WDT enabled
10
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS="0"),
Output pin floating,
Operating supply current
ICC1
15
20
25
µA
µA
at two clocks (VDD=3V)
WDT disabled
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS="0"),
Output pin floating,
Operating supply current
ICC2
15
at two clocks (VDD=3V)
WDT enabled
/RESET= 'High',
Fosc=4 MHz
(Crystal type, CLKS="0"),
Output pin floating
Operating supply current at two
ICC3
1.5
2.8
mA
mA
clocks (VDD=5.0V)
/RESET= 'High',
Fosc=10 MHz
(Crystal type, CLKS="0"),
Output pin floating
Operating supply current at two
ICC4
clocks (VDD=5.0V)
NOTE
These parameters are theoretical values and have not been tested.
48
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
Internal RC Electrical Characteristics (Ta=25C, VDD=5 V, VSS=0V)
Drift Rate
Min.
Internal RC
Temperature
25C
Voltage
5V
Typ.
4 MHz
16 MHz
8 MHz
1 MHz
Max.
4 MHz
16 MHz
8 MHz
1 MHz
3.92 MHz
15.68 MHz
7.84 MHz
0.98 MHz
4.08 MHz
16.32 MHz
8.16 MHz
1.02 MHz
25C
5V
25C
5V
25C
5V
Internal RC Electrical Characteristics (Ta= -40 ~85C)
Drift Rate
Internal RC
Temperature
-40 ~ 85C
-40 ~ 85C
-40 ~ 85C
-40 ~ 85C
Voltage
Min.
Typ.
4 MHz
16 MHz
8 MHz
1 MHz
Max.
4 MHz
16 MHz
8 MHz
1 MHz
2.1V~5.5V
3.76 MHz
4.24 MHz
16.64 MHz
8.40 MHz
1.06 MHz
4.0V~5.5V 15.36 MHz
3.0V~5.5V
2.1V~5.5V
7.60 MHz
0.94 MHz
8.2 AC Characteristics
Ta=25°C, VDD=5V, VSS=0V
Symbol
Parameter
Conditions
Min.
45
Typ.
50
Max.
Unit
%
Dclk
Input CLK duty cycle
Crystal type
RC type
55
DC
DC
100
ns
Instruction cycle time
(CLKS="0")
Tins
500
ns
Ttcc
Tdrh
Trst
TCC input period
(Tins+20)/N
ns
Device reset hold time
/RESET pulse width
Ta = 25C, XTAL 16.8-30% 16.8 16.8+30% ms
Ta = 25C
2000
ns
Twdt1 Watchdog timer period
Ta = 25C
16.8-30% 16.8 16.8+30% ms
Tset
Input pin setup time
Input pin hold time
0
ns
ns
ns
Thold
20
50
Tdelay Output pin delay time
Cload=20pF
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
49
EM78P176N
8-Bit Microcontroller with OTP ROM
9 Timing Diagrams
AC Test Input/Output Waveform
2.4
0.4
2.0
0.8
2.0
0.8
TEST POINTS
Note: AC Testing: Input are driven at 2.4V for logic “1”, and 0.4V for logic “0”
Timing measurements are made at 2.0V for logic “1”, and 0.8V for logic “0”
Figure 9-1a AC Test Input/Output Waveform Timing Diagram
Reset Timing (CLK = "0")
Instruction 1
NOP
Executed
CLK
/RESET
Tdrh
Figure 9-1b Reset Timing Diagram
TCC Input Timing (CLKS = "0")
ins
CLK
TCC
tcc
Figure 9-1c TCC Input Timing Diagram
50
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
APPENDIX
A Ordering and Manufacture Information
EM78P176NSS20J
Material Type
J: RoHS complied
S: Sony SS-00259 complied
Pin Number
Package Type
D: DIP
SO: SOP
SS: SSOP
Specific Annotation
N: Industrial Grad
Product Number
Product Type
P: OTP
F: Flash
none: Mask
Elan RISC I Kernel Product
For example:
EM78P176ND18S
is EM78P176N with OTP program memory, industrial grade product,
in 18-pin DIP 300mil package with Sony SS-00259 complied
‧‧‧‧‧‧‧
Elan Product Number
EM78Paaaa
1041 bbbbbb
Batch Number
Manufacture Date
“YYWW”
YY is year and WW is week
‧‧‧‧‧‧‧
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
51
EM78P176N
8-Bit Microcontroller with OTP ROM
B Package Type
OTP MCU
EM78P176NSS20J/S
EM78P176NSO20J/S
EM78P176ND18J/S
EM78P176NSO18J/S
EM78P176NJSS20J/S
Package Type
SSOP
SOP
Pin Count
Package Size
209 mil
20
20
18
18
20
300 mil
DIP
300 mil
SOP
300 mil
SSOP
209 mil
For product code "S"
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
That also Pb content is less than 100ppm and complies with Sony specifications.
For product code "J"
These are Green products and all complies with RoHS specifications
Part No.
Electroplate type
Ingredient (%)
EM78P176N
Pure Tin
Sn: 100%
Melting point ( C)
232 C
Electrical resistivity (µ-cm)
Hardness (hv)
11.4
8~10
50%
Elongation (%)
52
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
C Package Information
20-Lead Shrink Small Outline Package (SSOP) — 209 mil
Figure B-1a EM78P176N 20-Lead SSOP Package Type
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
53
EM78P176N
8-Bit Microcontroller with OTP ROM
20-Lead Small Outline Package (SOP) — 300 mil
Figure B-1b EM78P176N 20-Lead SOP Package Type
54
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
18-Lead Plastic Dual In–line Package (DIP) — 300 mil
Figure B-1c EM78P176N 18-Lead DIP Package Type
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
55
EM78P176N
8-Bit Microcontroller with OTP ROM
18-Lead Small Outline Package (SOP) — 300 mil
Figure B-1d EM78P176N 18-Lead SOP Package Type
56
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
EM78P176N
8-Bit Microcontroller with OTP ROM
D Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature = 245 5°C, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
–
Step 1: TCT, 65°C (15 min)~150°C (15 min), 10 cycles
Step 2: Bake at 125°C, TD (endurance) = 24 hrs
Step 3: Soak at 30°C/60%, TD (endurance) = 192 hrs
Step 4: IR flow 3 cycles
For SMD IC (such as
SOP, QFP, SOJ, etc)
Pre-condition
(Pkg thickness 2.5 mm or
Pkg volume 350 mm3 ---- 225 5°C)
(Pkg thickness 2.5 mm or
Pkg volume 350 mm3 ---- 240 5°C)
Temperature cycle
test
-65°C (15 min) ~ 150°C (15 min), 200 cycles
–
–
–
–
TA = 121°C, RH = 100%, pressure = 2 atm,
TD (endurance) = 96 hrs
Pressure cooker test
High temperature /
High humidity test
TA = 85°C , RH = 85%, TD (endurance) = 168 , 500 hrs
TA = 150°C, TD (endurance) = 500, 1000 hrs
High-temperature
storage life
High-temperature
operating life
TA = 125°C, VCC = Max. operating voltage,
TD (endurance) = 168, 500, 1000 hrs
–
–
Latch-up
TA = 25°C, VCC = Max. operating voltage, 800mA/40V
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (HBM)
TA = 25°C, ∣± 4KV∣
ESD (MM)
TA = 25°C, ∣± 400V∣
VDD-VSS(+),VDD_VSS
(-) mode
D.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise-caused address error is detected, the MCU will repeat execution of the
program until the noise is eliminated. The MCU will then continue to execute the next
program.
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
57
EM78P176N
8-Bit Microcontroller with OTP ROM
58
Product Specification (V1.2) 12.16.2015
(This specification is subject to change without prior notice)
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