EM78P224NK28A [ELAN]
8-Bit Microcontroller;
| 型号： | EM78P224NK28A |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller 微控制器 |
| 文件： | 总104页 (文件大小：1869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P224N
8-Bit Microcontroller
Product
Specification
DOC. VERSION 1.4
ELAN MICROELECTRONICS CORP.
May 2016
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2016 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road
Hsinchu Science Park
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
ELAN (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
ELAN Information
Technology Group
(U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Fax: +852 2723-7780
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Shenzhen:
Shanghai:
ELAN Microelectronics
Shenzhen, Ltd.
ELAN Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5, Bibo Road
Shenzhen Hi-Tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
General Description ................................................................................................ 1
Features ................................................................................................................... 1
Pin Assignment ....................................................................................................... 2
Pin Description........................................................................................................ 3
4.1 EM78P224N .....................................................................................................3
4.1.1 Pin Status under Enabled Function.....................................................................5
Block Diagram ......................................................................................................... 6
Functional Description............................................................................................ 7
5
6
6.1 Operational Registers .......................................................................................7
6.1.1 R0 (Indirect Addressing Register).......................................................................7
6.1.2 R1 (Bank Select Control Register)......................................................................7
6.1.3 R2 (Program Counter Low and Stack)................................................................7
6.1.4 R3 (Status Register)..........................................................................................12
6.1.5 R4 (RAM Select Register).................................................................................12
6.1.6 Bank 0 R5 ~ R8 (Port 5 ~ Port 8)......................................................................12
6.1.7 Bank 0 RB~RD (IOCR5 ~ IOCR7)....................................................................12
6.1.8 Bank 0 RE OMCR (Operating Mode Control Register) ....................................13
6.1.9 Bank 0 RF EIESCR (External Interrupt Edge Select Control Register)............14
6.1.10 Bank 0 R10 WUCR1 (Wake-up Control Register 1) .........................................15
6.1.11 Bank 0 R12 WUCR3 (Wake-up Control Register 3) .........................................15
6.1.12 Bank 0 R14 SFR1 (Status Flag Register) .........................................................15
6.1.13 Bank 0 R15 SFR2 (Status Flag Register 2) ......................................................16
6.1.14 Bank 0 R17 SFR4 (Status Flag Register 4) ......................................................16
6.1.15 Bank 0 R1B IMR1 (Interrupt Mask Register 1) .................................................17
6.1.16 Bank 0 R1C IMR2 (Interrupt Mask Register 2).................................................17
6.1.17 Bank 0 R1E IMR4 (Interrupt Mask Register 4) .................................................18
6.1.18 Bank 0 R21 WDTCR (Watchdog Timer Control Register)................................18
6.1.19 Bank 0 R22 TCCCR (TCC Control Register)....................................................19
6.1.20 Bank 0 R23 TCCD (TCC Data Register) ..........................................................20
6.1.21 Bank 0 R24 TC1CR1 (Timer/Counter 1 Control Register 1).............................20
6.1.22 Bank 0 R25 TC1CR2 (Timer/Counter 1 Control Register 2).............................21
6.1.23 Bank 0 R26 TC1DA (Timer/Counter 1 Data Buffer A).......................................22
6.1.24 Bank 0 R27 TC1DB (Timer/Counter 1 Data Buffer B) ......................................22
6.1.25 Bank 1 R5 IOCR8 .............................................................................................23
6.1.26 Bank 1 R8: P5PHCR (Port 5 Pull-high Control Register) .................................23
6.1.27 Bank 1 R9 P6PHCR (Port 6 Pull-high Control Register) ..................................23
6.1.28 Bank 1 RA P78PHCR (Ports 7~8 Pull-high Control Register) ..........................24
6.1.29 Bank 1 RD P7PLCR (Port 7 Pull-low Control Register)....................................24
6.1.30 Bank 1 RF P6HDSCR (Port 6 High Drive/Sink Control Register).....................24
6.1.31 Bank 1 R10 P78HDSCR (Ports 7 ~ 8 High Drive/Sink Control Register)........25
6.1.32 Bank 1 R12 P6ODCR (Port 6 Open-Drain Control Register) ...........................25
Product Specification (V1.4) 05.12.2016
iii
Contents
6.1.33 Bank 1 R45 TBPTL (Table Point Low Register)................................................25
6.1.34 Bank 1 R46 TBPTH (Table Point High Register) ..............................................25
6.1.35 Bank 1 R47 Stack Pointer .................................................................................26
6.1.36 Bank 1 R48 PCH (Program Counter High) .......................................................26
6.1.37 Bank 1 R49 LVDCR (Low Voltage Detect Control Register).............................26
6.2 TCC/WDT and Prescaler ................................................................................27
6.3 I/O Ports .........................................................................................................28
6.3.1 Usage of Ports 5~8 Input Changed Wake-up/Interrupt Function.....................30
6.4 Reset and Wake-up Operations......................................................................31
6.4.1 Reset.................................................................................................................31
6.4.2 Wake-up............................................................................................................33
6.4.3 Status of RST, T, and P of the Status Register..................................................33
6.4.4 Summary of Register Initial Values after Reset ................................................35
6.5 Interrupt ..........................................................................................................41
6.6 Timer ..............................................................................................................42
6.6.1 Timer/Counter Mode .........................................................................................43
6.6.2 Window Mode ...................................................................................................44
6.6.3 Capture Mode ...................................................................................................45
6.6.4 Programmable Divider Output (PDO) Mode and
Pulse Width Modulation (PWM) Mode ..............................................................46
6.6.5 Buzzer Mode.....................................................................................................48
6.7 LVD (Low Voltage Detector)............................................................................48
6.7.1 Low Voltage Reset ............................................................................................48
6.7.2 Low Voltage Detect ...........................................................................................48
6.8 Oscillator.........................................................................................................50
6.8.1 Oscillator Modes ...............................................................................................50
6.8.2 Crystal Oscillator/Ceramic Resonators (XTAL).................................................50
6.8.3 Internal RC Oscillator Mode..............................................................................52
6.9 Power-on Considerations................................................................................52
6.10 External Power-on Reset Circuit.....................................................................52
6.11 Residue-Voltage Protection.............................................................................53
6.12 Code Option Register .....................................................................................53
6.12.1 Code Option Register (Word 0) ........................................................................54
6.12.2 Code Option Register (Word 1) ........................................................................55
6.12.3 Code Option Register (Word 2) ........................................................................57
6.12.4 Code Option Register (Word 3) ........................................................................58
6.13 Instruction Set.................................................................................................58
Timing Diagrams ................................................................................................... 61
Absolute Maximum Ratings.................................................................................. 62
DC Electrical Characteristics................................................................................ 62
7
8
9
10 AC Electrical Characteristics................................................................................ 65
11 Device Characteristics.......................................................................................... 66
iv
Product Specification (V1.4) 05.12.2016
Contents
APPENDIX
A
B
C
Ordering and Manufacturing Information ............................................................ 89
Package Type......................................................................................................... 90
Packaging Information.......................................................................................... 91
C.1 EM78P224ND32 600mil .................................................................................91
C.2 EM78P224NSO32 450 mil..............................................................................92
C.3 EM78P224NSO32A 300mil.............................................................................93
C.4 EM78P224ND28 600mil .................................................................................94
C.5 EM78P224NK28A 400mil ...............................................................................95
C.6 EM78P224NSO28 300mil...............................................................................96
C.7 EM78P224NSS28 209mil ...............................................................................97
Quality Assurance and Reliability ........................................................................ 98
D.1 Address Trap Detect.......................................................................................98
D
Product Specification (V1.4) 05.12.2016
v
Contents
Specification Revision History
Doc. Version
Revision Description
Date
1.0
Initial version
2010/11/22
1. Modified the Pin Assignment.
2. Added the pin status with enabled functions.
3. Modified the operating voltage on the IRC drift rate table.
4. Modified the measured value of ESD and Latch up.
5. Modified Figure 6-3 and the Note.
1.1
2010/12/03
6. Modified the Stack status after reset occured.
7. Modified the table of AC electrical characteristic.
1. Modified description of P67 at pin description.
2. Modified description of R3 Bit 7.
3. Modified description of Bank 0 R12, Bits 7~4.
4. Modified decscription of Chapter 6.8.2.
5. Deleted HLP at Code Option Word 0 Bit 9.
6. Added Code Option Word 3 for Customer ID
7. Deleted Code Option Word 2 Bit 14.
1.2
2012/06/08
8. Added Ordering and Manufacturing Information.
9. Added diagram on Frequency to Voltage Curve.
10. Modified descriptions on POR and LVR in the feature spec.
1.3
1.4
1. Added device characteristic curve.
2012/11/27
2016/05/12
1. Added LVR characteristics in the DC Electrical Characteristics.
2. Added P53 remark at the Pin Description section.
3. Modified Apendix A for Ordering and Manufacturing Information
4. Added User Application Note
User Application Note
(Before using this IC, take a look at the following description note, it includes important messages.)
1.
We strongly recommend that users have to place an external pull-down or pull-high resistor on
P53 no matter what the pin function is. The purpose of this is to prevent P53 from floating.
vi
Product Specification (V1.4) 05.12.2016
EM78P224N
8-Bit Microcontroller
1 General Description
EM78P224N is an 8-bit microprocessor with low-power, high-speed CMOS technology, and high noise
immunity. It has a built-in 4K15-bit in system programmable SRAM, and 1768 bits in OTP-ROM
(Electrical One Time Programmable Read Only Memory). It provides three protection bits to prevent
intrusion of user’s OTP memory code. Seven option bits are also available to meet user’s unique
requirements.
With its enhanced OTP-ROM features, the EM78P224N can provide a convenient way of developing and
verifying user’s programs. Moreover, this OTP device offers the advantages of effective program updates
with the use of development and programming tools, such as the ELAN Writer to easily program your
development codes.
2 Features
CPU Configuration:
IRC oscillation circuit selected by code option for
sub clock
Support 4K15 bits program ROM
1768 bits on-chip registers (SRAM)
8-level stacks for subroutine nesting
Dual clock operation mode
Main Clock
Crystal mode:
DC ~ 20 MHz at 5V
DC ~ 8 MHz at 3V
DC ~ 4 MHz at 2.1V
Power on reset level Voltage:
1.8V(Reset)~1.9V (Release)
IRC mode:
DC ~ 16 MHz/2clks at 4.5V
DC ~ 8 MHz/2clks at 3V
DC ~ 4 MHz/2clks at 2.1V
Less than 1.0mA at 5V/4 MHz
Typically 15A, at 3V/16kHz
Typically 2A, during Sleep mode
Four operation modes:
Main
IRC Drift Rate (Ta=25°C, VDD=5V ± 5%, VSS=0V)
Drift Rate
Internal RC
Frequency
Mode
CPU
Sub Clock
Voltage
(2.3V~5.5V)
Temprature
(-40°C+85°C)
Clock
Sleep mode Turn off Turn off
Idle Mode Turn off Turn off
Process Total
Turn off
Turn on
Turn on
Turn on
±2%
±2%
±2%
±2%
±3%
±3%
±3%
±3%
±2%
±2%
±2%
±2%
±7%
±7%
±7%
±7%
1 MHz
4 MHz
8 MHz
16 MHz
Green mode Turn on Turn off
Normal mode Turn on Turn on
I/O Port Configuration:
Sub Clock
IRC mode: 32kHz/16kHz
4 bidirectional I/O ports: P5, P6, P7, P8
30 I/O pins
Peripheral Configuration:
8 Programmable open-drain I/O pins
24 programmable pull-high I/O pins
8 programmable pull-low I/O pins
16 programmable high sink I/O pins
16 programmable high drive I/O pins
External interrupt : INT
8-bit real time clock/counter (TCC) with selective
signal sources and trigger edges
8-bit Timer/Counter
TC1: Timer/Counter/capture/window/buzzer/PWM
/PDO (Programmable Divider Output) Mode
External interrupt wake-up
Function: Rising or falling edges interrupt
Operating voltage range:
Four Ports input status change wake-up
2.1V~5.5V at 0~70C (commercial)
2.3V~5.5V at -40~85C (industrial)
Operating frequency range:
Four programmable Level Voltage Detectors
(LVD): 4.5V, 4V, 3.3V, & 2.2V.
Four programmable Level Voltage Resets
(LVR): 4.0V, 3.5V, 2.7V, & 1.8V(POR)
Crystal/IRC oscillation circuit selected by
code option for system clock
5 available interrupts
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
1
EM78P224N
8-Bit Microcontroller
Special Features:
28-pin SSOP 209 mil:
32-pin DIP 600 mil:
32-pin SOP 450 mil:
32-pin SOP 300 mil:
EM78P224SS28
EM78P224ND32
EM78P224NSO32
EM78P224NSO32A
Programmable free running watchdog timer
High ESD immunity
Power saving Sleep mode
Selectable Oscillation mode
Package Types:
28-pin DIP 600 mil: EM78P224ND28
NOTE
28-pin Skinny DIP
These are all Green products which do not
contain hazardous substances.
400 mil: EM78P224NK28A
28-pin SOP 300 mil: EM78P224NSO28
3 Pin Assignment
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P81
P82
P83
2
P80
3
P67//RESET (VPP)
P70/TCC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P67//RESET (VPP)
P70/TCC
1
2
VDD (VDD)
4
P57/OSCI/RCOUT
VDD (VDD)
P57/OSCI/RCOUT
P56/OSCO
5
P56/OSCO
P53 (CLK)
P55 (DATA)
P84
P54
3
P54
6
VSS (VSS)
P53 (CLK)
VSS (VSS)
4
7
P52/INT
P51/TC1
P50
P55 (DATA)
P84
5
P52/INT
P51/TC1
8
6
9
P85
7
P85
P50
P60
P61
P62
10
11
12
13
14
15
16
P77
P60
P77
8
P76
P61
P76
9
P75
P62
10
11
12
13
14
P75
P74
P73
P74
P63
P63
P64
P65
P66
P73
P64
P72
P65
P72
P71
P71
P66
DIP/SOP
DIP/SOP
Figure 3-1b EM78P224ND28/SO28/K28A/SS28
Figure 3-1a EM78P224ND32/SO32
2
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
4 Pin Description
4.1 EM78P224N
Legend: ST:
Schmitt Trigger input
AN: analog pin
CMOS: CMOS output
XTAL: Oscillation pin for crystal / resonator
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable pull-high and pin change
wake-up.
P50
P50
ST
CMOS
Bidirectional I/O pin with programmable pull-high and pin change
wake-up.
P51
TC1
P52
INT
ST
ST
ST
ST
ST
CMOS
P51/TC1
P52/INT
CMOS Timer 1 (Counter1/CAP1/Window/PDO1/PWM1/BUZ1)
Bidirectional I/O pin with programmable pull-high and pin change
wake-up.
CMOS
External interrupt pin
Bidirectional I/O pin with pin change wake-up.
P53
CMOS
Remark: Off-chip pull-down or pull-high
P53
(CLK)
Clock pin for Writer programming
(CLK)
ST
Remark: Off-chip pull-down or pull-high
P54
P54
P55
ST
ST
ST
ST
CMOS Bidirectional I/O pin with pin change wake-up.
CMOS Bidirectional I/O pin with pin change wake-up.
CMOS Data pin for Writer programming
P55
(DATA)
(DATA)
P56
CMOS Bidirectional I/O pin with pin change wake-up.
XTAL Clock output of crystal / resonator oscillator
CMOS Bidirectional I/O pin with pin change wake-up.
P56
P57
OSCO
P57
ST
XTAL
OSCI
RCOUT
Clock input of crystal / resonator oscillator
COMS Clock output of internal RC oscillator
Bidirectional I/O pin with programmable pull-high, open-drain,
high-sink and pin change wake-up.
P60
P61
P62
P63
P64
P65
P66
P60
P61
P62
P63
P64
P65
P66
P67
ST
ST
ST
ST
ST
ST
ST
ST
CMOS
Bidirectional I/O pin with programmable pull-high, open-drain,
high-sink and pin change wake-up.
CMOS
Bidirectional I/O pin with programmable pull-high, open-drain, and
pin change wake-up.
CMOS
Bidirectional I/O pin with programmable pull-high, open-drain, and
pin change wake-up.
CMOS
Bidirectional I/O pin with programmable pull-high, open-drain, and
pin change wake-up.
CMOS
Bidirectional I/O pin with programmable pull-high, open-drain, and
pin change wake-up.
CMOS
Bidirectional I/O pin with programmable pull-high, open-drain, and
pin change wake-up.
CMOS
Bidirectional I/O pin with pin change wake-up.This pin is always
open-drain.
CMOS
P67//RESET
(VPP)
/RESET
(VPP)
ST
Reset pin
power
VPP pin for Writer programming
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
3
EM78P224N
8-Bit Microcontroller
(Continuation)
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable pull-low, pull-high,
high-sink/drive and pin change wake-up.
P70
TCC
P72
ST
ST
ST
CMOS
P70/TCC
Real Time Clock/Counter clock input
Bidirectional I/O pin with programmable pull-low, pull-high,
high-sink/drive and pin change wake-up.
P72
P73
P74
P75
P76
P77
P80
P81
P82
P83
P84
P85
CMOS
Bidirectional I/O pin with programmable pull-low, pull-high,
high-sink/drive and pin change wake-up.
P73
P74
P75
P76
P77
P80
P81
P82
P83
P84
P85
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
CMOS
CMOS
CMOS
CMOS
CMOS
COMS
COMS
COMS
CMOS
CMOS
CMOS
Bidirectional I/O pin with programmable pull-low, pull-high,
high-sink/drive and pin change wake-up.
Bidirectional I/O pin with programmable pull-low, pull-high,
high-sink/drive and pin change wake-up.
Bidirectional I/O pin with programmable pull-low, pull-high,
high-sink/drive and pin change wake-up.
Bidirectional I/O pin with programmable pull-low, pull-high,
high-sink/drive and pin change wake-up.
Bidirectional I/O pin with programmable pull-high, high-sink/drive
and pin change wake-up.
Bidirectional I/O pin with programmable pull-high, high-sink/drive
and pin change wake-up.
Bidirectional I/O pin with programmable pull-high, high-sink/drive
and pin change wake-up.
Bidirectional I/O pin with programmable pull-high, high-sink/drive
and pin change wake-up.
Bidirectional I/O pin with programmable pull-high, high-sink/drive
and pin change wake-up.
Bidirectional I/O pin with programmable pull-high, high-sink/drive
and pin change wake-up.
VDD
(VDD)
VSS
VDD
(VDD)
VSS
Power
Power
Power
Power
Power
VDD pin for Writer programming
Ground
(VSS)
(VSS)
Ground pin for Writer programming
NOTE
It is strongly recommended that user has to place external pull-down or pull-high
resistor on P53 no matter what the pin function is.
The purpose of this is to prevent P53 from floating.
4
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
4.1.1 Pin Status under Enabled Function
I/O Status
Pin Control
Pin Function
Pin Change
Wake-up/Interrupt
I/O Direction
Pull High
Pull Low
O.D.
General Input
General Output
TCC
Input
Output
Input
Input
Output
Input
Input
Input
Input
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
S/W
S/W
TC-IN
S/W
S/W
TC-OUT
Reset
S/W
S/W
Init: ENABLE
S/W
S/W
EX_INT
OSCI
S/W
Disable
Disable
Disable
Disable
OSCO
NOTE
Disable: It is always disabled
Enable: It is always enabled
S/W: It can be controlled by register. The initial status is disabled.
1. If the pin is not working as general I/O, the Pin Change Wake-up/Interrupt function
must be at disable status.
2. Priority: Digital function output > digital function input > general I/O
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
5
EM78P224N
8-Bit Microcontroller
5 Block Diagram
P5
Flash
ROM
Ext.
OSC.
PC
Int. RC
P50
P51
P52
P53
P54
P55
P56
P57
Oscillation
Generation
Instruction
Register
8-level
stack
Start-up
timer
WDT
TCC
Sub
P6
Reset
Int. RC
TCC
TC1
Instruction
Decoder
P60
P61
P62
P63
P64
P65
P66
P67
TC1
LVD
LVR
Mux.
ALU
Ext INT
P7
R4
P70
P71
P72
P73
P74
RAM
P75
P76
P77
Interrupt
control
circuit
R3(Status
Reg.)
ACC
P8
P80
P81
P82
P83
P84
P85
Figure 5-1 EM78P224N Functional Block Diagram
6
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6 Functional Description
6.1 Operational Registers
6.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect addressing pointer. Any instruction using R0 as a pointer actually accesses
data pointed by the RAM Select Register (R4).
6.1.2 R1 (Bank Select Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
SBS0
R/W
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7 ~ 5:
Not used. Set to “0” all the time.
Bit 4 (SBS0): Special register bank select bit. It is used to select Bank 0 or Bank 1 of
the special Registers R5~R4F.
0: Bank 0
1: Bank 1
Bits 3 ~ 0:
Not used. Set to “0” all the time.
6.1.3 R2 (Program Counter Low and Stack)
Bit 7
PC7
R/W
Bit 6
PC6
R/W
Bit 5
PC5
R/W
Bit 4
PC4
R/W
Bit 3
PC3
R/W
Bit 2
PC2
R/W
Bit 1
PC1
R/W
Bit 0
PC0
R/W
Bits 7 ~ 0 (PC7 ~ PC0): The low byte of the program counter.
Depending on the device type, R2 and hardware stack are 12-bit
wide. The structure is depicted in the following Figure 6-1;
EM78P224N Program Counter Configuration.
The configuration structure generates 4K15 bits on-chip OTP ROM
addresses to the relative programming instruction codes. One
program page is 4096 words long.
R2 is set as all "0"s when under Reset condition.
"JMP" instruction allows direct loading of the lower 12 program
counter bits. Thus, "JMP" allows the PC to go to any location within a
page.
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
7
EM78P224N
8-Bit Microcontroller
"CALL" instruction loads the lower 12 bits of the PC, and the present
PC value will add 1 and is pushed onto the stack. Thus, the
subroutine entry address can be located anywhere within a page.
"LJMP" instruction allows direct loading of the lower 15 program
counter bits. Therefore, "LJMP" allows PC to jump to any location
14
within 16K (2 ).
"LCALL" instruction loads the lower 15 bits of the PC, and then PC+1
is pushed onto the stack. Thus, the subroutine entry address can be
14
located anywhere within 16K (2 ).
"RET" ("RETL k", "RETI") instruction loads the program counter with
the contents of the top-level stack.
"ADD R2, A" allows a relative address to be added to the current PC,
and the ninth and above bits of the PC will increase progressively.
"MOV R2, A" allows to load an address from the "A" register to the
lower 8 bits of the PC, and the ninth and above bits of the PC will not
change.
Any instruction except “ADD R2,A” that is written to R2 (e.g., "MOV
R2, A", "BC R2, 6", etc.) will cause the ninth bit and the above bits
(A8~A11) of the PC to remain unchanged.
All instructions are single instruction cycle (Fsys/2) except “LCALL”
and “LJMP” instructions. The “LCALL” and “LJMP” instructions need
two instructions cycle.
0000h
0002h
PC
A11
~
A0
Reset vector
INT interrupt vector
Pin change interrupt vector
TCC interrupt vector
LVD interrupt vector
TC1 interrupt vector
0004h
0006h
0008h
0012h
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
On-chip Program memory
0FFFh
Figure 6-1 EM78P224N Program Counter Organization
8
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
Data Memory Configuration
Address
0X00
0X01
0X02
0X03
0X04
0X05
0X06
0X07
0X08
0X09
0X0A
0x0B
0X0C
0X0D
0X0E
Bank 0
Bank 1
IAR (Indirect Addressing Register)
BSR (Bank Select Control Register)
PC (Program Counter)
SR (Status Register)
RSR (RAM Selection Register)
IOCR8
Port 5
Port 6
Port 7
Port 8
P5PHCR
P6PHCR
P78PHCR
IOC5
IOC6
P7PLCR
IOC7
OMCR (Operating Mode Control Register)
EIESCR (External Interrupt Edge Selection
Control Register)
0X0F
P6HDSCR
WUCR1
P78HDSCR
0X10
0X11
0X12
0X13
0X14
0X15
0X16
0X17
0X18
0X19
0X1A
0X1B
0X1C
0X1D
0X1E
0X1F
0X20
WUCR3
P6ODCR
SFR1 (Status Flag Register 1)
SFR2 (Status Flag Register 2)
SFR4 (Status Flag Register 4)
IMR1 (Interrupt Mask Register 1)
IMR2 (Interrupt Mask Register 2)
IMR4 (Interrupt Mask Register 4)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
9
EM78P224N
8-Bit Microcontroller
(Continuation)
Address
Bank 0
Bank 1
0x21
0X22
0X23
0X24
0X25
0X26
0X27
0X28
0X29
0X2A
0x2B
0X2C
0X2D
0X2E
0X2F
0X30
0X31
0X32
0X33
0X34
0X35
0X36
0X37
0X38
0X39
0X3A
0x3B
0X3C
0X3D
0X3E
0X3F
0X40
0X41
0X42
WDTCR
TCCCR
TCCD
TC1CR1
TC1CR2
TC1DA
TC1DB
10
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
(Continuation)
Address
0X43
0X44
0X45
0X46
0X47
0X48
0X49
0X4A
0x4B
0X4C
0X4D
0X4E
0X4F
0X50
0X51
.
Bank 0
Bank 1
TBPTL
TBPTH
STKMON
PCH
LVDCR
General Purpose Register
.
0X7F
0X80
0X81
.
Bank 0
.
General Registers
(1288 bits)
.
0XFE
0XFF
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
11
EM78P224N
8-Bit Microcontroller
6.1.4 R3 (Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
T
Bit 3
P
Bit 2
Z
Bit 1
DC
Bit 0
C
INT
F
R/W
R/W
R/W
R/W
R/W
Bit 7 (INT): Interrupt Enable flag
0: Interrupt masked by DISI or hardware interrupt
1: Interrupt enabled by ENI/RETI instructions
Bits 6 ~ 5: Not used. Set to “0” all the time.
Bit 4 (T): Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up
and reset to “0” by WDT time-out.
Bit 3 (P): Power down bit
Set to “1” during power on or by a "WDTC" command and reset to “0” by a
"SLEP" command.
Bit 2 (Z): Zero flag
Set to “1” if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7
RSR7
R/W
Bit 6
RSR6
R/W
Bit 5
RSR5
R/W
Bit 4
RSR4
R/W
Bit 3
RSR3
R/W
Bit 2
RSR2
R/W
Bit 1
RSR1
R/W
Bit 0
RSR0
R/W
Bits 7 ~ 0 (RSR7 ~ RSR0): These bits are used to select registers (Address: 00~FF) in
indirect addressing mode. You can refer to the table on Data Memory
Configuration for more details under Section 6.1.3; R2: PCL (Program
Counter Low and Stack).
6.1.6 Bank 0 R5 ~ R8 (Port 5 ~ Port 8)
R5, R6, R7, and R8 are I/O data registers.
6.1.7 Bank 0 RB~RD (IOCR5 ~ IOCR7)
These registers are used to control the I/O port direction. They are both
readable and writable.
0: Put the relative I/O pin as output
1: Put the relative I/O pin into high impedance
12
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.1.8 Bank 0 RE OMCR (Operating Mode Control Register)
Bit 7
CPUS
R/W
Bit 6
IDLE
R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RCM1
R/W
Bit 0
RCM0
R/W
Bit 7 (CPUS): CPU Oscillator Source Select.
0: Fs: sub-oscillator
1: Fm: main-oscillator
When CPUS=0, the CPU oscillator selects the sub-oscillator and the
main oscillator is stopped.
Bit 6 (IDLE): Idle Mode Enable Bit. This bit determines which mode (see figure
below) to use with SLEP instruction.
0: “IDLE=0”+SLEP instruction Sleep mode
1: “IDLE=1”+SLEP instruction Idle mode
Code option
HLFS=1
RESET
Normal mode
Fm: oscillation
Fs: oscillation
CPU: using Fm
Code option
HLFS=0
wakeup
Interrupt or
wakeup
IDLE=0
+ SLEP
CPUS=1
CPUS=0
IDLE=1
+ SLEP
IDLE=1
+ SLEP
wakeup
(*)
Sleep mode
Fm: stop
Green mode
Fm: stop
Idle mode
Fm: stop
Fs: stop
CPU: stop
Fs: oscillation
CPU: using Fs
Fs: oscillation
CPU: stop
Interrupt or
wakeup
IDLE=0
+ SLEP
(*)
switching operation mode at idle>normal, idle->green:
If the clock source of timer is Fs, timer/counter must continue to count in idle
mode.When the matching condition of the timer/counter happens in idle mode, the
interrupt flag of timer/counter would be active. However, the MCU will jump to interrupt
vector when corresponding interrupt is enabled.
Figure 6-2 CPU Operation Mode
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
13
EM78P224N
8-Bit Microcontroller
Oscillation Characteristics
Oscillation Mode
CPU Mode Switch
Sleep Normal
Idle Normal
Green Normal
Sleep Green
Idle Green
Waiting Time before CPU Starts to Work
WSTO + 510 clocks (main frequency)
WSTO + 510 clocks (main frequency)
WSTO + 510 clocks (main frequency)
WSTO + 8 clocks (sub frequency)
WSTO + 8 clocks (sub frequency)
WSTO + 8 clocks (main frequency)
WSTO + 8 clocks (main frequency)
WSTO + 8 clocks (main frequency)
WSTO + 8 clocks (sub frequency)
WSTO + 8 clocks (sub frequency)
WSTO: Waiting Time from Start-to-Oscillation
Crystal mode
Sleep Normal
Idle Normal
Green Normal
Sleep Green
Idle Green
IRC mode
Bits 5 ~ 2:
Not used. Set to “0” all the time.
Bits 1 ~ 0 (RCM1 ~ RCM0): Internal RC mode select bits
RCM1
RCM0
Frequency (MHz)
0
0
1
1
0
1
0
1
1
8
16
4
NOTE
The initial value of RCM1~0 is the same with settings in Code Option
Word 0.
6.1.9 Bank 0 RF EIESCR (External Interrupt Edge Select Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EIES
R/W
Bit 2
Bit 1
Bit 0
Bits 7 ~ 4:
Not used. Set to “0” all the time.
Bit 3 (EIES): External interrupt edge select bit
0: Falling edge interrupt
1: Rising edge interrupt
Bits 2 ~ 0:
Not used. Set to “0” all the time.
14
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.1.10 Bank 0 R10 WUCR1 (Wake-up Control Register 1)
Bit 7
Bit 6
Bit 5
LVDWK
R/W
Bit 4
Bit 3
INTWK
R/W
Bit 2
Bit 1
Bit 0
Bits 7 ~ 6:
Not used. Set to “0” all the time.
Bit 5 (LVDWK): Low Voltage Detect Wake-up Enable Bit
0: Disable Low Voltage Detect wake-up.
1: Enable Low Voltage Detect wake-up.
Bit 4:
Not used. Set to “0” all the time.
Bit 3 (INTWK): External Interrupt (INT pin) Wake-up Function Enable Bit
0: Disable external interrupt wake-up
1: Enable external interrupt wake-up
Bits 2 ~ 0:
Not used. Set to “0” all the time.
6.1.11 Bank 0 R12 WUCR3 (Wake-up Control Register 3)
Bit 7
ICWKP8 ICWKP7 ICWKP6 ICWKP5
R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7 ~ 4 (ICWKP8 ~ 5): (Ports 8~5) Pin-change Wake-up Function Enable Bit
0: Disable Pin-change wake-up
1: Enable Pin-change wake-up
Bits 3 ~ 0:
Not used. Set to “0” all the time.
6.1.12 Bank 0 R14 SFR1 (Status Flag Register)
Bit 7
Bit 6
Bit 5
LVDSF
F
Bit 4
Bit 3
EXSF
F
Bit 2
Bit 1
Bit 0
TCSF
F
Each corresponding status flag is set to “1” when the interrupt condition is triggered.
Bits 7 ~ 6: Not used. Set to “0” all the time.
Bit 5 (LVDSF): Low Voltage Detector status flag
LVDEN LVDS1, LVDS0 LVD Voltage Interrupt Level
LVDSF
1
1
1
1
0
11
10
01
00
XX
2.2V
3.3V
4.0V
4.5V
NA
1*
1*
1*
1*
0
* If Vdd crossovers at the LVD voltage interrupt level as Vdd varies,
LVDSF =1.
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
15
EM78P224N
8-Bit Microcontroller
Bit 4:
Not used. Set to “0” all the time.
Bit 3 (EXSF): External interrupt status flag
Bits 2 ~ 1: Not used. Set to “0” all the time.
Bit 0 (TCSF): TCC overflow status flag. Set when TCC overflows. Reset by
software.
NOTE
If a function is enabled, the corresponding status flag will be active regardless
whether the interrupt mask is enabled or not.
6.1.13 Bank 0 R15 SFR2 (Status Flag Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1SF
F
Each corresponding status flag is set to “1” when the interrupt condition is triggered.
Bits 7~1: Not used. Set to “0” all the time.
Bit 0 (TC1SF): 8-bit timer/Counter 1 status flag, cleared by software.
NOTE
If a function is enabled, the corresponding status flag will be active regardless
whether the interrupt mask is enabled or not.
6.1.14 Bank 0 R17 SFR4 (Status Flag Register 4)
Bit 7
P8ICSF
F
Bit 6
P7ICSF
F
Bit 5
P6ICSF
F
Bit 4
P5ICSF
F
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7 (P8ICSF): Port 8 status flag. The flag is cleared by software.
Bit 6 (P7ICSF): Port 7 status flag. The flag is cleared by software.
Bit 5 (P6ICSF): Port 6 status flag. The flag is cleared by software.
Bit 4 (P5ICSF): Port 5 status flag. The flag is cleared by software.
Bits 3 ~ 0: Not used. Set to “0” all the time.
16
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.1.15 Bank 0 R1B IMR1 (Interrupt Mask Register 1)
Bit 7
Bit 6
Bit 5
LVDIE
R/W
Bit 4
Bit 3
EXIE
R/W
Bit 2
Bit 1
Bit 0
TCIE
R/W
Bits 7 ~ 6: Not used. Set to “0” all the time.
Bit 5 (LVDIE): LVDSF interrupt enable bit.
0: Disable LVDSF interrupt
1: Enable LVDSF interrupt
Bit 4: Not used. Set to “0” all the time.
Bit 3 (EXIE): EXSF interrupt enable bit.
0: Disable EXSF interrupt
1: Enable EXSF interrupt
Bits 2 ~ 1: Not used. Set to “0” all the time.
Bit 0 (TCIE): TCSF interrupt enable bit.
0: Disable TCSF interrupt
1: Enable TCSF interrupt
NOTE
If the interrupt mask is enabled, the program counter will jump to the corresponding
interrupt vector when the corresponding status flag is set.
6.1.16 Bank 0 R1C IMR2 (Interrupt Mask Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1IE
R/W
Bits 7 ~ 1: Not used. Set to “0” all the time.
Bit 0 (TC1IE): Interrupt enable bit.
0: Disable TC1SF interrupt
1: Enable TC1SF interrupt
NOTE
If the interrupt mask is enabled, the program counter will jump to the corresponding
interrupt vector when the corresponding status flag is set.
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
17
EM78P224N
8-Bit Microcontroller
6.1.17 Bank 0 R1E IMR4 (Interrupt Mask Register 4)
Bit 7
Bit 6
P7ICIE
R/W
Bit 5
P6ICIE
R/W
Bit 4
P5ICIE
R/W
Bit 3
Bit 2
Bit 1
Bit 0
P8ICIE
R/W
Bit 7 (P8ICIE): Interrupt enable bit.
0: Disable P8ICSF interrupt
1: Enable P8ICSF interrupt
Bit 6 (P7ICIE): Interrupt enable bit.
0: Disable P7ICSF interrupt
1: Enable P7ICSF interrupt
Bit 5 (P6ICIE): Interrupt enable bit.
0: Disable P6ICSF interrupt
1: Enable P6ICSF interrupt
Bit 4 (P5ICIE): Interrupt enable bit.
0: Disable P5ICSF interrupt
1: Enable P5ICSF interrupt
Bits 3 ~ 0:
Not used. Set to “0” all the time.
NOTE
If the interrupt mask is enabled, the program counter will jump to the corresponding
interrupt vector when the corresponding status flag is set.
6.1.18 Bank 0 R21 WDTCR (Watchdog Timer Control Register)
Bit 7
WDTE
R/W
Bit 6
Bit 5
Bit 4
Bit 3
PSWE
R/W
Bit 2
WPSR2
R/W
Bit 1
WPSR1
R/W
Bit 0
WPSR0
R/W
Bit 7 (WDTE): Watchdog Timer Enable Bit. WDTE is both readable and writable.
0: Disable WDT
1: Enable WDT
Bits 6 ~ 4:
Bit 3 (PSWE): Prescaler enable bit for WDT
0: Prescaler disable bit. WDT Rate is 1:1.
1: Prescaler enable bit. WDT rate is set at Bits 2~0.
Not used. Set to “0” all the time.
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Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
Bit 2 ~ 0 (WPSR2 ~ WPSR0): WDT Prescale Bits
WPSR2 WPSR1 WPSR0 WDT Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.1.19 Bank 0 R22 TCCCR (TCC Control Register)
Bit 7
Bit 6
TCCS
R/W
Bit 5
TS
Bit 4
TE
Bit 3
PSTE
R/W
Bit 2
TPSR2
R/W
Bit 1
TPSR1
R/W
Bit 0
TPSR0
R/W
R/W
R/W
Bit 7:
Not used. Set to “0” all the time.
Bit 6 (TCCS): TCC Clock Source Select Bit
0: Fs (sub clock)
1: Fm (main clock)
Bit 5 (TS):
TCC signal source
0: Internal instruction cycle clock
1: Transition on the TCC pin. The TCC period must be larger than the
internal instruction clock period.
Bit 4 (TE):
TCC Signal Edge
0: Increment if a transition from low to high takes place on the TCC pin
1: Increment if a transition from high to low takes place on the TCC pin
Bit 3 (PSTE): Prescaler enable bit for TCC
0: Prescaler disable bit. The TCC rate is 1:1.
1: Prescaler enable bit. The TCC rate is set at Bit 2 ~ Bit 0.
Bits 2 ~ 0 (TPSR2 ~ TPSR0): TCC Prescaler Bits
TPSR2 TPSR1 TPSR0 TCC Rate
0
0
0
1:2
0
0
1
1:4
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1:8
1:16
1:32
1:64
1:128
1:256
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
19
EM78P224N
8-Bit Microcontroller
6.1.20 Bank 0 R23 TCCD (TCC Data Register)
Bit 7
Bit 6
TCC6
R/W
Bit 5
TCC5
R/W
Bit 4
TCC4
R/W
Bit 3
TCC3
R/W
Bit 2
TCC2
R/W
Bit 1
TCC1
R/W
Bit 0
TCC0
R/W
TCC7
R/W
Bits 7 ~ 0 (TCC7 ~ TCC0): TCC data
The counter is increased by an external signal edge through the TCC
pin, or by the instruction cycle clock. The external signal of the TCC
trigger pulse width must be greater than one instruction. The signals
to increase the counter are determined by
Bit 4 and Bit 5 of the TCCCR register. Writable and readable as any
other registers. If there is an overflow, the value previously written to
TCCD will be auto-reloaded to the TCC circuit.
6.1.21 Bank 0 R24 TC1CR1 (Timer/Counter 1 Control Register 1)
Bit 7
TC1S
R/W
Bit 6
TC1RC
R/W
Bit 5
TC1SS1
R/W
Bit 4
Bit 3
TC1FF
R/W
Bit 2
TC1OMS TC1IS1
R/W R/W
Bit 1
Bit 0
TC1IS0
R/W
Bit 7 (TC1S):
Timer/Counter 1 start control (the total of all mode switches)
0: Stop and clear the counter (default)
1: Start
Bit 6 (TC1RC): Timer 1 Read Control Bit
0: When this bit is set to 0, cannot read data from TC1DB (default).
1: When this bit is set to 1, data read from TC1DB is a number of
counting.
Bit 5 (TC1SS1): Timer/Counter 1 clock source select bit1
0: Internal clock as counting source (Fc), Fs/Fm (default)
1: External TC1 pin as counting source (Fc). It is used only for
timer/counter mode.
Bit 4: Not used. Set to “0” all the time.
Bits 3 (TC1FF): Inversion for Timer/Counter 1 as PWM
0: Duty is Logic 1 (default)
1: Duty is Logic 0
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EM78P224N
8-Bit Microcontroller
Bit 2 (TC1OMS): Timer Output Mode Select Bit
0: Repeating mode (default)
1: One-shot mode
NOTE
One-shot mode means the timer only counts a cycle.
Bits 1 ~ 0 (TC1IS1 ~ TC1IS0): Timer 1 Interrupt Type Select Bits. These two bits are
used when the Timer operates in PWM mode.
TC1IS1 TC1IS0
Timer 1 Interrupt Type Select
TC1DA (period) matching
TC1DB (duty) matching
0
0
1
0
1
TC1DA and TC1DB matching
6.1.22 Bank 0 R25 TC1CR2 (Timer/Counter 1 Control Register 2)
Bit 7
TC1M2
R/W
Bit 6
TC1M1
R/W
Bit 5
TC1M0
R/W
Bit 4
TC1SS0 TC1CK3 TC1CK2 TC1CK1
R/W R/W R/W R/W
Bit 3
Bit 2
Bit 1
Bit 0
TC1CK0
R/W
Bits 7 ~ 5 (TC1M2 ~ TC1M0): Timer/Counter 1 Operation Mode Select.
TC1M2
TC1M1
TC1M0
Operating Mode Select
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Timer/Counter Rising Edge
Timer/Counter Falling Edge
Capture Mode Rising Edge
Capture Mode Falling Edge
Window mode
Programmable Divider output
Pulse Width Modulation output
Buzzer (output timer timer/counter
clock source. The duty cycle of the
clock source must be 50/50)
1
1
1
Bit 4 (TC1SS0): Timer/Counter 1 clock source select bit
0: Fs is used as counting source (Fc) (default)
1: Fm is used as counting source (Fc)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
21
EM78P224N
8-Bit Microcontroller
Bits 3 ~ 0 (TC1CK3 ~ TC1CK0): Timer/Counter 1 clock source prescaler select
Max. Time
8 MHz
Max. Time
16kHz
Clock
Source
Resolution
8 MHz
Resolutio
n 16kHz
TC1CK3 TC1CK2 TC1CK1 TC1CK0
Normal
FC
FC=8M
125ns
250ns
500ns
1 μs
FC=8M
32 μs
FC=16K
62.5 μs
125 μs
250 μs
500 μs
1 ms
FC=16K
16 ms
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FC/2
64 μs
32 ms
FC/22
FC/23
FC/24
FC/25
FC/26
FC/27
FC/28
FC/29
FC/210
FC/211
FC/212
FC/213
FC/214
FC/215
128 μs
64 ms
256 μs
128 ms
2 μs
512 μs
256 ms
4 μs
1024 μs
2048 μs
4096 μs
8192 μs
16384 μs
32768 μs
65536 μs
131072 μs
262144 μs
2 ms
512 ms
8 μs
4 ms
1024 ms
2048 ms
4096 ms
8192 ms
16384 ms
32768 ms
65536 ms
131072 ms
262144 ms
524288 ms
16 μs
8 ms
32 μs
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
64 μs
128 μs
256 μs
512 μs
1.024 ms
2.048 ms
4.096 ms
524.288 ms 1.024 s
1.048 s 2.048 s
6.1.23 Bank 0 R26 TC1DA (Timer/Counter 1 Data Buffer A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 ~ 0 (TC1DA7 ~ TC1DA0): Data buffer A of 8 bit timer/counter
6.1.24 Bank 0 R27 TC1DB (Timer/Counter 1 Data Buffer B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
R/W R/W R/W R/W R/W R/W R/W R/W
Bits 7 ~ 0 (TC1DB7 ~ TC1DB0): Data buffer B of 8-bit Timer/Counter 1
NOTE
1. When Timer / Counter x is used in PWM mode, the duty value stored at Register
TCxDB must be smaller than or equal to the period value stored at Register
TCxDA.,i.e;. duty period. Then the PWM waveform is generated. If the duty is
greater than the period, the PWM output waveform is kept at high voltage level.
2. The period value set by user is automatically added by 1 within the inner circuit.
For example:
When the period value is set as 0x4F, the circuit processes 0x50 as actual period
length.
When the period value is set as 0xFF, the circuit processes 0x100 as actual period
length.
22
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.1.25 Bank 1 R5 IOCR8
These registers are used to control the I/O port direction. They are both readable and
writable.
0: Put the relative I/O pin as output
1: Put the relative I/O pin into high impedance
6.1.26 Bank 1 R8: P5PHCR (Port 5 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PH52
R/W
Bit 1
PH51
R/W
Bit 0
PH50
R/W
Bits 7 ~ 3:
Not used. Set to “1” all the time.
Bit 2 (PH52): Control bit used to enable pull-high of P52 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 1 (PH51): Control bit used to enable pull-high of the P51 pin
Bit 0 (PH50): Control bit used to enable pull-high of the P50 pin
6.1.27 Bank 1 R9 P6PHCR (Port 6 Pull-high Control Register)
Bit 7
Bit 6
PH66
R/W
Bit 5
PH65
R/W
Bit 4
PH64
R/W
Bit 3
PH63
R/W
Bit 2
PH62
R/W
Bit 1
PH61
R/W
Bit 0
PH60
R/W
All of these bits are low active
Bit 7: Not used. Set to “1” all the time.
Bit 6 (PH66): Control bit used to enable pull-high of the P66 pin
Bit 5 (PH65): Control bit used to enable pull-high of the P65 pin
Bit 4 (PH64): Control bit used to enable pull-high of the P64 pin
Bit 3 (PH63): Control bit used to enable pull-high of the P63 pin
Bit 2 (PH62): Control bit used to enable pull-high of the P62 pin
Bit 1 (PH61): Control bit used to enable pull-high of the P61 pin
Bit 0 (PH60): Control bit used to enable pull-high of the P60 pin
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
23
EM78P224N
8-Bit Microcontroller
6.1.28 Bank 1 RA P78PHCR (Ports 7~8 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HPH
R/W
Bit 2
P8LPH
R/W
Bit 1
P7HPH
R/W
Bit 0
P7NPH
R/W
All of these bits are low active.
Bits 7 ~ 4: Not used. Set to “1” all the time.
Bit 3 (P8HPH): Control bit used to enable pull-high of the Port 8 high nibble pin
Bit 2 (P8LPH): Control bit used to enable pull-high of the Port 8 low nibble pin
Bit 1 (P7HPH): Control bit used to enable pull-high of the Port 7 high nibble pin
Bit 0 (P7LPH): Control bit used to enable pull-high of the Port 7 low nibble pin
6.1.29 Bank 1 RD P7PLCR (Port 7 Pull-low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
P7HPL
R/W
Bit 0
P7LPL
R/W
All of these bits are low active.
Bits 7 ~ 2: Not used. Set to “1” all the time.
Bit 1 (P7HPH): Control bit used to enable pull low of the Port 7 high nibble pin
Bit 0 (P7LPH): Control bit used to enable pull low of the Port 7 low nibble pin
6.1.30 Bank 1 RF P6HDSCR (Port 6 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
H61
R/W
Bit 0
H60
R/W
Bits 7 ~ 2:
Not used. Set to “1” all the time.
Bits 1 ~ 0 (H61 ~ H60): P61~P60 high sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
24
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.1.31 Bank 1 R10 P78HDSCR (Ports 7 ~ 8 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P8HHDS P8LHDS P7HHDS P7LHDS
R/W R/W R/W R/W
Bit 2
Bit 1
Bit 0
All of these bits are low active.
Bits 7 ~ 4: Not used. Set to “1” all the time.
Bit 3 (P8HHDS): Control bit used to enable high drive/sink of Port 8 high nibble pin
Bit 2 (P8LHDS): Control bit used to enable high drive/sink of Port 8 low nibble pin
Bit 1 (P7HHDS): Control bit used to enable high drive/sink of Port 7 high nibble pin
Bit 0 (P7LHDS): Control bit used to enable high drive/sink of Port 7 low nibble pin
6.1.32 Bank 1 R12 P6ODCR (Port 6 Open-Drain Control Register)
Bit 7
OD67
R/W
Bit 6
OD66
R/W
Bit 5
OD65
R/W
Bit 4
OD64
R/W
Bit 3
OD63
R/W
Bit 2
OD62
R/W
Bit 1
OD61
R/W
Bit 0
OD60
R/W
Bit 7 (OD67):
Open-Drain control bit. This bit is set to “0” all the time as P67 is
always enabled as Open-Drain.
Bits 6 ~ 0 (OD66 ~ OD60): Open-Drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.1.33 Bank 1 R45 TBPTL (Table Point Low Register)
Bit 7
TB7
R/W
Bit 6
TB6
R/W
Bit 5
TB5
R/W
Bit 4
TB4
R/W
Bit 3
TB3
R/W
Bit 2
TB2
R/W
Bit 1
TB1
R/W
Bit 0
TB0
R/W
Bits 7 ~ 0 (TB7 ~ TB0): Table Point Address Bits 7 ~ 0.
6.1.34 Bank 1 R46 TBPTH (Table Point High Register)
Bit 7
HLB
R/W
Bit 6
GP0
R/W
Bit 5
Bit 4
Bit 3
TB11
R/W
Bit 2
TB10
R/W
Bit 1
TB9
R/W
Bit 0
TB8
R/W
Bit 7 (HLB):
Bit 6 (GP0):
Bits 5 ~ 4:
Take MLB or LSB at machine code
General purpose read/write bits
Not used. Set to “0” all the time.
Bits 3 ~ 0 (TB11 ~ TB8): Table Point Address Bits 11 ~ 8.
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
25
EM78P224N
8-Bit Microcontroller
6.1.35 Bank 1 R47 Stack Pointer
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
STL2
R
Bit 1
STL1
R
Bit 0
STL0
R
STOV
R
Bit 7 (STOV): Stack pointer overflow indication bit. Read only.
Bits 2 ~ 0 (STL2 ~ 0): Stack pointer number. Read only.
6.1.36 Bank 1 R48 PCH (Program Counter High)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PC11
R/W
Bit 2
PC10
R/W
Bit 1
PC9
R/W
Bit 0
PC8
R/W
Bits 7 ~ 4:
Not used. Set to “0” all the time.
Bits 3 ~ 0 (PC11 ~ PC8): High byte of the program counter.
6.1.37 Bank 1 R49 LVDCR (Low Voltage Detect Control Register)
Bit 7
LVDEN
R/W
Bit 6
Bit 5
LVDS1
R/W
Bit 4
LVDS0
R/W
Bit 3
LVDB
R
Bit 2
Bit 1
Bit 0
Bit 7 (LVDEN):
Low Voltage Detector Enable Bit
0: Disable low voltage detector
1: Enable low voltage detector
Bit 6: Not used. Set to “0” all the time.
Bits 5 ~ 4 (LVDS1 ~ LVDS0): Low Voltage Detector Level Bits.
LVD Voltage Interrupt
Level
LVDEN LVDS1, LVDS0
LVDB
VDD < 2.2V
VDD > 2.2V
VDD < 3.3V
VDD > 3.3V
VDD < 4.0V
VDD > 4.0V
VDD < 4.5V
VDD > 4.5V
NA
0
1
0
1
0
1
0
1
1
1
1
1
11
10
01
1
0
00
XX
26
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
Bit 3 (LVDB): Low Voltage Detector State Bit. This is a read only bit. When the VDD
pin voltage is lower than the LVD voltage interrupt level (selected by
LVDS2 ~ LVDS0), this bit will be cleared.
0: Low voltage is detected
1: Low voltage is not detected or LVD function is disabled.
Bits 2 ~ 0:
Not used. Set to “0” all the time.
6.2 TCC/WDT and Prescaler
Two 8-bit counters are available as prescalers for the TCC and WDT respectively. The
TPSR0~ TPSR2 bits of the TCCCR register (Bank 0 R22) are used to determine the
ratio of the TCC prescaler. Likewise, the WPSR0~WPSR2 bits of the WDTCR register
(Bank 0 R21) are used to determine the WDT prescaler. The prescaler counter is
cleared by the instructions each time they are written into TCC. The WDT and
prescaler counter are cleared by the “WDTC” and “SLEP” instructions. Figure 6-3
below depicts the block diagram of TCC/WDT.
TCCD (Bank 0 R23) is an 8-bit timer/counter. The clock source of TCC can be either
internal clock or external signal input (edge selectable from the TCC pin). As illustrated
in Figure 6-3, if the TCC signal source is from an internal clock, TCC will increase by 1
at every instruction cycle (without prescaler). If the TCC signal source is from an
external clock input, TCC will increase by 1 at every falling edge or rising edge of the
TCC pin. The TCC pin input time length (keep in High or Low level) must be greater
than 1CLK. The TCC will stop running when Sleep mode occurs.
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep on
running even after the oscillator driver has been turned off (i.e., in Sleep mode). During
normal operation or the Sleep mode, a WDT time-out (if enabled) will cause the device
to reset. The WDT can be enabled or disabled at any time during the Normal mode by
software programming (refer to WDTE bit of WDTCR (Bank 0 R21) register in Section.
6.1.8). With no prescaler, the WDT time-out period is approximately 16 ms1 (one
oscillator start-up timer period).
1 VDD=5V, WDT time-out period = 16ms ± 10%.
VDD=3V, WDT time-out period = 16ms ± 10%.
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
27
EM78P224N
8-Bit Microcontroller
CLK (Fosc/2)
0
1
Data Bus
8 Bit Counter
MUX
SYNC
2 cycles
TCC(R23)
TCC Pin
TE (R22)
8 to 1 MUX
Prescaler
TCC overflow
interrupt
TS (R22)
TPSR2~TPSR0
(R22)
WDT
8 Bit Counter
8 to 1 MUX
Prescaler
WDTE (R21)
WDT time out
WPSR2~WPSR0
(R21)
Figure 6-3 TCC and WDT Block Diagram
1
6.3 I/O Ports
The I/O registers, Port 5~Port 8 are bi-directional tri-state I/O ports. They can be pulled
high and pulled low internally by software. They can also be set as open-drain output
and high sink/drive setting by software. Ports 5~8 feature Wake-up and interrupt
functions as well as input status change interrupt function. Each I/O pin can be defined
as "input" or "output" pin by the I/O control registers (IOC5 ~ IOC8).
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5 ~ Port 8 are shown in the following Figures 6-4a to 6-4c.
The EM78P224N has two different types of packaging with different number of pins. To
achieve maximum power consumption, it is highly recommended to program P80, P81,
P82, and P83 on the 32 and 28-packagings as “not used” under the following
conditions:
1. When the “not-used” pins need to be defined as output ports, the pins should be set
as output high or pull low relative to its pull high/low status.
2. When the “not-used” pins need to be defined as input ports, the pins should be set as
input pull high or pull low.
28
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
PCRD
P
Q
D
R
_
Q
PCWR
PDWR
CLK
C
L
INT
IOD
P
Q
PORT
D
R
_
Q
CLK
C
L
0
1
P
D
R
Q
M
U
X
_
CLK
C
L
Q
T10
PDRD
P
R
D
Q
CLK
_
Q
C
L
INT
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-4a I/O Port and I/O Control Register Circuit for /INT
PCRD
P
Q
_
Q
D
D
R
CLK
PCWR
PDWR
C
L
P61~P67
PORT
IOD
P
R
Q
_
Q
CLK
C
L
0
1
M
U
X
TIN
PDRD
P
R
D
Q
CLK
_
Q
C
L
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-4b I/O Port and I/O Control Register Circuit for Port 5~8
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
29
EM78P224N
8-Bit Microcontroller
IOCE.1
P
Q
D
R
CLK
Interrupt
_
Q
C
L
RE.
1
ENI Instruction
P
R
T10
T11
D
Q
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
C
L
T17
DISI Instruction
Interrupt
(Wake-up from SLEEP)
/SLEP
Next Instruction
(Wake-up from SLEEP)
Figure 6-4c I/O Port 5~8 with Input Change Interrupt/Wake-up Block Diagram
6.3.1 Usage of Ports 5~8 Input Changed Wake-up/Interrupt
Function
1. Wake-up
a) Before SLEEP:
1) Disable WDT
2) Read I/O Port (MOV R6,R6)
3) Execute "ENI" or "DISI"
4) Enable wake-up bit (Set ICWK6 =1)
5) Execute "SLEP" instruction
b) After Wake-up:
Next instruction
2. Wake-up and Interrupt
a) Before SLEEP
1) Disable WDT
2) Read I/O Port (MOV R6, R6)
3) Execute "ENI" or "DISI"
4) Enable wake-up bit (Set ICWK6 =1)
5) Enable interrupt (Set P6ICIE =1)
6 Execute "SLEP" instruction
b) After Wake-up
1) IF "ENI" Interrupt vector (0006H)
2) IF "DISI" Next instruction
30
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.4 Reset and Wake-up Operations
6.4.1 Reset
A reset is initiated by one of the following events:
1) Power-on reset
2) /RESET pin input "low", or
3) WDT time-out (if enabled)
4) LVR (if enabled)
The device is kept in a reset condition for a period of approximately 18 ms (one
oscillator start-up timer period) after the Power-on reset is detected. If the /Reset pin
goes “low” or WDT time-out is active, a reset is generated. In RC mode the reset time
is 8 clocks, in XTAL mode, the reset time is 510 clocks. Once a RESET occurs, the
following functions are performed.
The oscillator continues running, or will be started.
The Program Counter (R2) is set to all "0".
The contents of the stack are cleared to all “0”.
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog Timer and prescaler are cleared.
When power is switched on, R1 is cleared.
The control register bits are set according to the table shown in Section 6.4.4,
Summary of Register Initial Values after Reset.
Executing the “SLEP” instruction will assert the Sleep (power down) mode. While
entering Sleep mode, the Oscillator, TCC and Timer1 are stopped. The WDT (if
enabled) is cleared but keeps on running. Wake-up time is then generated (in RC
mode, the wake-up time is 8 clocks, in High XTAL mode, the wake-up time is 2 ms and
510 clocks, in Low XTAL mode, the wake-up time is 255 clocks). The controller can be
awakened by any of the following events:
1) External reset input on /RESET pin
2) WDT time-out (if enabled)
3) Port input status change (if ICWKx is enabled)
4) External Interrupt status change (if INTWK is enabled)
5) Low Voltage Detector (if LVDWE is enabled)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
31
EM78P224N
8-Bit Microcontroller
The first two events will cause the MCU to reset. The T and P flags of R3 can be used
to determine the source of the reset (Wake-up). Cases 3~5 are considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a Wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from the Address 0x03~0x22 by each interrupt vector after Wake-up. If DISI is
executed before SLEP, the execution will restart from the instruction right next to SLEP
after Wake-up. From Sleep to Normal mode, the Wake-up time is 510 clocks +
warm-up time with Crystal oscillator and 8 clocks (Fm) + warm-up time with IRC
oscillator. From Idle to Green mode, only warm-up time is needed. From Sleep to
Green mode the wake-up time is 8 clocks (Fs) + warm-up time.
One or more of the Events 3 to 5 can be enabled before entering into Sleep mode. That
is:
a) If WDT is enabled before SLEP, all Wake-up bits are disabled. Hence, the MCU
can be waked up only under Events 1 or 2 conditions. Refer to the Section 6.5,
Interrupt; for further details.
b) If Port Input Status Change is used to wake-up the MCU and Bank 0-R11 register is
enabled before SLEP, the WDT must be disabled. Hence, the MCU can be waked
up only under Event 3 condition.
c) If External Interrupt Status Change is used to wake-up MCU and INTWK bit is
enabled before SLEP, WDT must be disabled by software. Hence, the MCU can be
waked up only under Event 4 condition.
d) If Low voltage detector is used to wake-up the MCU and LVDWK bit of Bank 0-RF
register is enabled before SLEP, WDT must be disabled by software. Hence, the
MCU can be waked up only under Event 5 condition.
If input Status Change Interrupt is used to Wake-up the MCU (as in the Event b above),
the subsequent instructions must be executed before SLEP:
32
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.4.2 Wake-up
Summary of Wake-up and Interrupt modes
Event
Sleep Mode
Idle Mode
Green
Mode
Normal
Mode
(Corresponding
Wake-up Bit is
Enabled)
Interrupt
Enable
Interrupt
Disable
Interrupt
Enable
Interrupt
Disable
Wake-up only
for external
clock source
Wake-up
+ interrupt +
next instruction is enabled) is enabled)
Interrupt
(if interrupt
Interrupt
(if interrupt
TCC
INT pin
Timer 1
Pin change
LVD
X
X
Wake-up +
interrupt + next
instruction
Wake-up +
interrupt + next (if interrupt
instruction
Wake-up +
interrupt + next (if interrupt
instruction
Interrupt
Interrupt
(if interrupt
Wake-up +
next instruction
Wake-up + next
instruction
is enabled) is enabled)
Wake-up only
for external
clock source
Interrupt
Interrupt
(if interrupt
X
X
is enabled) is enabled)
Wake-up +
interrupt + next
instruction
Wake-up +
interrupt + next (if interrupt
instruction
Interrupt
Interrupt
(if interrupt
Wake-up +
next instruction
Wake-up + next
instruction
is enabled) is enabled)
Wake-up +
interrupt + next
instruction
Wake-up +
interrupt + next (if interrupt
instruction
Interrupt
Interrupt
(if interrupt
Wake-up +
next instruction
Wake-up + next
instruction
is enabled) is enabled)
Low Voltage
Reset
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
WDT Time-out
RESET
NOTE
After Wake-up:
1. If interrupt is enabled interrupt+ next instruction
2. If interrupt is disabled next instruction
6.4.3 Status of RST, T, and P of the Status Register
A reset condition is initiated by one of the following events:
1) A power-on condition
2. A high-low-high pulse on /RESET pin, and
3. Watchdog timer time-out.
The values of T and P as listed in the following table are used to check how the
processor wakes up. The second table shows the events that may affect the status of T
and P.
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
33
EM78P224N
8-Bit Microcontroller
Values of RST, T and P after RESET
Reset Type
T
1
P
1
Power on
/RESET during Operating mode
/RESET wake-up during Sleep mode
WDT during Operating mode
*P
1
*P
0
0
*P
0
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
1
0
*P: Previous status before reset
Status of T and P Being Affected by Events
Event
T
1
1
0
1
1
P
1
Power on
WDTC instruction
1
WDT time-out
*P
0
SLEP instruction
Wake-up on pin change during Sleep mode
0
*P: Previous value before reset
VDD
D
Q
CLK
Oscillator
CLK
CLR
Power-On Reset
Low Voltage Reset
Setup time
WDTE
WDT
WDT Timeout
Reset
/RESET
Figure 6-5 Block Diagram of Controller Reset
34
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.4.4 Summary of Register Initial Values after Reset
Legend: U: Unknown or don’t care
C: Same with Code option
P: Previous value before reset
t: Check tables under Section 6.4.2
Address Bank, Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Power-On
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
R0
0x00
/RESET and WDT
(IAR)
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
SBS0
0
0
0
0
0
0
0
0
0
0
0
0
Power-on
0
0
R1
0x01
/RESET and WDT
(BSR)
Wake-up from
Sleep/Idle
0
0
0
P
0
0
0
0
Bit Name
PC7
0
PC6
0
PC5
0
PC4
0
PC3
0
PC2
0
PC1
0
PC0
0
Power-on
R2
0x02
/RESET and WDT
0
0
0
0
0
0
0
0
(PC)
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
INT
0
0
0
0
0
0
0
T
1
t
P
1
t
Z
U
P
DC
U
C
U
P
Power-on
R3
0x03
/RESET and WDT
0
P
(SR)
Wake-up from
Sleep/Idle
P
0
0
t
t
P
P
P
Bit Name
RSR7
RSR6
RSR5
RSR4
RSR3
RSR2
RSR1
RSR0
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
R4
0x04
/RESET and WDT
(RSR)
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
P57
0
P56
0
P55
0
P54
0
P53
0
P52
0
P51
0
P50
0
Power-on
Bank 0, R5
0X05
/RESET and WDT
0
0
0
0
0
0
0
0
(Port 5)
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
P67
0
P66
0
P65
0
P64
0
P63
0
P62
0
P61
0
P60
0
Power-on
Bank 0, R6
0x06
/RESET and WDT
0
0
0
0
0
0
0
0
(Port 6)
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
35
EM78P224N
8-Bit Microcontroller
(Continuation)
Address Bank, Name
Reset Type
Bit Name
Bit 7
P77
0
Bit 6
P76
0
Bit 5
P75
0
Bit 4
P74
0
Bit 3
P73
0
Bit 2
P72
0
Bit 1
P71
0
Bit 0
P70
0
Power-on
Bank 0, R7
(Port 7)
0x07
0x08
0X0B
0x0C
0X0D
0x0E
0X0F
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
P85
0
P84
0
P83
0
P82
0
P81
0
P80
0
Power-on
Bank 0, R8
(Port 8)
/RESET and WDT
0
0
0
0
0
0
Wake-up from
Sleep/Idle
0
0
P
P
P
P
P
P
Bit Name
IOC57
IOC56
IOC55
IOC54
IOC53
IOC52
IOC51
IOC50
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 0, RB
(IOCR5)
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
IOC67
IOC66
IOC65
IOC64
IOC63
IOC62
IOC61
IOC60
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 0, RC
(IOCR6)
/RESET and WDT
Wake-Up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
IOC77
IOC76
IOC75
IOC74
IOC73
IOC72
IOC71
IOC70
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 0, RD
(IOCR7)
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
CPUS
IDLE
0
0
0
0
0
0
0
0
0
0
0
0
RCM1
RCM0
Power-on
1
1
1
1
0
0
0
0
Bank 0, RE
(OMCR)
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
0
0
0
0
P
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
EIES
0
0
0
0
0
0
0
0
0
Power-on
1
1
Bank 0, RF
(EIESCR)
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
P
0
0
0
36
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
(Continuation)
Address Bank, Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
LVDWK
0
0
0
INTWK
0
0
0
0
0
0
0
0
0
Power-on
0
0
0
0
Bank 0, R10
0x10
/RESET and WDT
(WUCR1)
Wake-up from
Sleep/Idle
0
0
P
0
P
0
0
0
Bit Name
ICWKP8 ICWKP7 ICWKP6 ICWKP5
0
0
0
0
0
0
0
0
0
0
0
0
Power-on
0
0
0
0
0
0
0
0
Bank 0, R12
0X12
/RESET and WDT
(WUCR3)
Wake-up from
Sleep/Idle
P
P
P
P
0
0
0
0
Bit Name
0
0
0
0
0
0
LVDSF
0
0
0
EXSF
0
0
0
0
0
0
TCSF
Power-on
0
0
0
0
0
0
Bank 0, R14
0X14
/RESET and WDT
SFR1
Wake-up from
Sleep/Idle
0
0
P
0
P
0
0
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TC1SF
Power-on
0
0
Bank 0, R15
0X15
/RESET and WDT
SFR2
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
P
Bit Name
P8ICSF P7ICSF P6ICSF P5ICSF
0
0
0
0
0
0
0
0
0
0
0
0
Power-on
0
0
0
0
0
0
0
0
Bank 0, R17
0X17
/RESET and WDT
SFR4
Wake-up from
Sleep/Idle
P
P
P
P
0
0
0
0
Bit Name
0
0
0
0
0
0
LVDIE
0
0
0
EXIE
0
0
0
0
0
0
TCIE
Power-on
0
0
0
0
0
0
Bank 0, R1B
0X1B
IMR1
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
P
0
P
0
0
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TC1IE
Power-on
0
0
Bank 0, R1C
0X1C
IMR2
/RESET and WDT
Wake-up from
Sleep/Idle
0
0
0
0
0
0
0
P
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
37
EM78P224N
8-Bit Microcontroller
(Continuation)
Address Bank, Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P8ICIE P7ICIE P6ICIE P5ICIE
0
0
0
0
0
0
0
0
0
0
0
0
Power-on
0
0
0
0
0
0
0
0
Bank 0, R1E
IMR4
0X1E
0X21
0X22
0X23
0X24
0X25
0X26
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
0
0
0
0
Bit Name
WDTE
0
0
0
0
0
0
0
0
0
PSWE WPSR2 WPSR1 WPSR0
Power-on
0
0
0
0
0
0
0
0
0
0
BANK 0, R21
WDTCR
/RESET and WDT
Wake-up from
Sleep/Idle
P
0
0
0
P
P
P
P
Bit Name
0
0
0
TCCS
TS
0
TE
0
PSTE
TPSR2 TPSR1 TPSR0
Power-on
0
0
0
0
0
0
0
0
0
0
Bank 0, R22
TCCR
/RESET and WDT
0
0
Wake-up from
Sleep/Idle
0
P
P
P
P
P
P
P
Bit Name
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R23
TCCD
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
TC1S
TC1RC TC1SS1
0
0
0
TC1FF TC1OMS TC1IS1 TC1IS0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R24
TC1CR1
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
0
P
P
P
P
Bit Name
TC1M2 TC1M1 TC1M0 TC1SS0 TC1CK3 TC1CK2 TC1CK1 TC1CK0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R25
TC1CR2
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R26
TC1DA
/RESET and WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
38
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
(Continuation)
Address Bank, Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R27
0X27
/RESET and WDT
TC1DB
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
IOC85
IOC84
IOC83
IOC82
IOC81
IOC80
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1, R5
0X05
/RESET and WDT
IOCR8
Wake-up from
Sleep/Idle
0
0
P
P
P
P
P
P
Bit Name
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PH52
PH51
PH50
Power-on
1
1
1
1
1
1
Bank 1, R8
0X08
/RESET and WDT
P5PHCR
Wake-up from
Sleep/Idle
1
1
1
1
1
P
P
P
Bit Name
1
1
1
PH66
PH65
PH64
PH63
PH62
PH61
PH60
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bank 1, R9
0X09
/RESET and WDT
P6PHCR
Wake-up from
Sleep/Idle
1
P
P
P
P
P
P
P
Bit Name
1
1
1
1
1
1
1
1
1
1
1
1
P8HPH P8LPH P7HPH P7LPH
Power-on
1
1
1
1
1
1
1
1
Bank 1, RA
0X0A
/RESET and WDT
P78PHCR
Wake-up from
Sleep/Idle
1
1
1
1
P
P
P
P
Bit Name
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P7HPL P7LPL
Power-on
1
1
1
1
Bank 1, RD
0X0D
/RESET and WDT
P7PLCR
Wake-up from
Sleep/Idle
1
1
1
1
1
1
P
P
Bit Name
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
H61
1
H60
1
Power-on
Bank 1, RF
0X0F
/RESET and WDT
1
1
P6HDSCR
Wake-up from
Sleep/Idle
1
1
1
1
1
1
P
P
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
39
EM78P224N
8-Bit Microcontroller
(Continuation)
Address Bank, Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
1
1
1
1
P8HHDS P8LHDS P7HHDS P7LHDS
Power-on
1
1
1
1
1
1
1
1
Bank 1, R10
P78HDSCR
0X10
0X12
0X45
0X46
0X47
0X48
0X49
/RESET and WDT
Wake-up from
Sleep/Idle
1
1
1
1
P
P
P
P
Bit Name
OD67
OD66
OD65
OD64
OD63
OD62
OD61
OD60
Power-on
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R12
P6ODCR
/RESET and WDT
Wake-up from
Sleep/Idle
1
P
P
P
P
P
P
P
Bit Name
TB7
0
TB6
0
TB5
0
TB4
0
TB3
0
TB2
0
TB1
0
TB0
0
Power-on
Bank 1, R45
TBPTL
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
HLB
0
GP0
0
0
0
0
0
0
TB11
TB10
TB9
0
TB8
0
Power-on
0
0
0
0
0
0
Bank 1, R46
TBPTH
/RESET and WDT
0
0
0
Wake-up from
Sleep/Idle
P
P
0
0
P
P
P
P
Bit Name
STOV
0
0
0
0
0
0
0
0
0
0
0
0
STL2
STL1
STL0
Power-on
0
0
0
0
0
0
0
0
Bank 1, R47
STKMON
/RESET and WDT
Wake-up from
Sleep/Idle
P
0
0
0
0
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
PC11
PC10
PC9
0
PC8
0
Power-on
0
0
0
0
Bank 1, R48
PCH
/RESET and WDT
0
0
Wake-up from
Sleep/Idle
0
0
0
0
P
P
P
P
Bit Name
LVDEN
0
0
0
LVDS1 LVDS0
LVDB
0
0
0
0
0
0
0
0
0
Power-on
0
0
0
0
0
0
1
1
Bank 1, R49
LVDCR
/RESET and WDT
Wake-up from
Sleep/Idle
P
0
P
P
P
0
0
0
40
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.5 Interrupt
The EM78P224N has five interrupts as listed below:
Interrupt Source
Enable Condition
Int. Flag Int. Vector Priority
Internal /
Reset
-
-
0
High 0
External
External
External
Internal
Internal
Internal
INT
ENI + EXIE=1
ENI +ICIE=1
ENI + TCIE=1
EXSF
ICSF
TCSF
2
4
1
2
3
4
5
Pin change
TCC
6
LVD
ENI+LVDEN & LVDIE=1 LVDSF
ENI + TC1IE=1 TC1SF
8
TC1(TCXDA)
12
Bank 0 R14~R17 are the interrupt status registers that record the interrupt requests in
the relative flags/bits. Bank 0 R1B~R1E is the interrupt mask register. The global
interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When
one of the interrupts (if enabled) occurs, the next instruction will be fetched from an
individual address. The interrupt flag bit must be cleared by instructions before leaving
the interrupt service routine and before interrupts are enabled to avoid recursive
interrupts.
The flag (except when PxICSF bit is deleted) in the Interrupt Status Register is set
regardless of the status of its mask bit or the execution of ENI. The RETI instruction
ends the interrupt routine and enables the global interrupt (the execution of ENI).
External interrupt is equipped with digital noise rejection circuit (input pulse of less than
4 system clocks time is eliminated as noise if code option NRHL=0), but in Low
XTAL oscillator (LXT) mode the noise rejection circuit is disabled. When an
interrupt (falling edge) is generated by the External interrupt (when enabled), the next
instruction will be fetched from Address 003H.
Before the interrupt subroutine is executed, the contents of ACC, R3, and R4 registers
are saved by hardware. If another interrupt occurs, the ACC, R3, and R4 will be
replaced by the new interrupt. After the interrupt service routine is finished, ACC, R3,
and R4 are restored.
When the RESET (POR, LVR, WDT, and /RESET) occurs, the contents of stack would
be cleared to all “0”.
Interrupt
occurs
Interrupt sources
ENI/DISI
ACC
R1
STACKACC
STACKR1
STACKR3
STACKR4
R3
R4
RETI
Figure 6-6a Interrupt Back-up Diagram
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
41
EM78P224N
8-Bit Microcontroller
VCC
P
D
Q
IRQn
R
/IRQn
CLK
INT
_
Q
IRQm
C
L
RFRD
RF
ENI/DISI
P
IOD
Q
D
R
CLK
_
Q
IOCFWR
C
L
IOCF
/RESET
IOCFRD
RFWR
Figure 6-6b Interrupt Input Circuit
6.6 Timer
The EM78P224N has a timer, Timer 1 which can be an 8-bit up-counter.
R_BANK Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1S
R/W
TC1RC TC1SS1 TC1MOD TC1FF TC1OMS TC1IS1 TC1IS0
R/W R/W R/W R/W R/W R/W
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
0x24
0x25
0x26
0x27
0x16
0x1C
TC1CR1
TC1CR2
TC1DA
TC1DB
ISR2
R
TC1M2 TC1M1 TC1M0 TC1SS0 TC1CK3 TC1CK2 TC1CK1 TC1CK0
R/W R/W R/W R/W R/W R/W R/W R/W
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
R/W R/W R/W R/W R/W R/W R/W R/W
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TC1SF
F
TC1IE
R/W
IMR2
42
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
6.6.1 Timer/Counter Mode
TCxM2~0
TCxM2~0=timer/counter mode
TCx pin
M
fc/215
fc/20
MUX
clear
8-bit up counter
TC1S
TCxCK
Comparator
TCx
interrupt
4
TCxCR
TCxDB
TCxDA
Data Bus
Figure 6-7a Timer/Counter Mode Diagram
In Timer/Counter mode, counting up is performed using internal clock or TCx pin.
When the contents of the up-counter match the TCxDA, the interrupt is generated and
the counter is cleared. Counting up resumes after the counter is cleared. The current
contents of the up-counter are loaded into TCxDB by setting TCxRC to “1”.
When in Counter mode with the MCU operating in Sleep mode, the counting edge of
the timer TCx Pin is selected to rising edge. When the contents of the up-counter
match the TCxDA, the MCU will wake-up and enters into interrupt by generating a
falling edge from TCx pin and vice versa.
The Timer/Counter mode waveforms are illustrated in the following figures.
Internal clock
Up-counter
TCxDA
n
5
n-2
0
1
2
3
4
n-3
n-1
0
1
2
3
n
match
counter clear
(a)
TCx interrupt
Figure 6-7b Timer/Counter Mode Waveform Using Internal Clock
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
43
EM78P224N
8-Bit Microcontroller
TCx Pin
1
2
3
n 0
4
n-2
Up-counter
TCxDA
0
n-1
1
2
3
n
match
counter clear
(b)
TCx interrupt
Figure 6-7c Timer/Counter Mode Waveform using External Clock
TCx Pin
1
2
3
n
0
1
4
n-2
Up-counter
TCxDA
0
n-1
n
counter
clear
Interrupt and
wake up
(c)
match
TCx interrupt
Figure 6-7d Timer/Counter Mode Waveform using External Clock under Sleep Mode
6.6.2 Window Mode
TCx pin
fc/215
Window
clear
8-bit up counter
MUX
fc/20
Comparator
TCx interrupt
TCxCK
TCxS
4
TCcCR2
TCxDA
Data Bus
Figure 6-8a Window Mode
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Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
In Window mode, counting up is performed on a rising edge of the pulse that is logical
AND of an internal clock and the TCx pin (window pulse). When the contents of the
up-counter match the TCxDA, interrupt is generated and the counter is cleared. The
frequency (window pulse) must be slower than the selected internal clock.
TCx pin
Internal clock
Up-counter
TCxDA
n-1
n
0
n-2
0
1
2
n-3
1
2
3
n
match
counter clear
TCx interrupt
Figure 6-8b Window Mode Waveform
6.6.3 Capture Mode
Inhibit
Capture
control
Rising
Edge
detector
TCx
Falling
TCxM2~0
M
interrupt
TCxM2~0=010
TCx pin
fc/215
Overflow
8-bit up counter
MUX
fc/20
TC1S
CAP
TCxCK
4
Capture
Capture
TC1CR
TCxDB
TCxDA
Data Bus
Figure 6-9a Capture Mode
In Capture mode, the pulse width, period, and duty of the TCx input pin are measured in
this mode and are used to decode the remote control signal. The counter is free
running by the internal clock. On the rising (falling) edge of the TCx pin, the contents of
counter is loaded into TCxDA, then the counter is cleared and interrupt is generated.
On the falling (rising) edge of the TC1 pin, the contents of counter are loaded into
TCxDB while the counter is still counting.
Product Specification (V1.4) 05.12.2016
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45
EM78P224N
8-Bit Microcontroller
Once the next rising edge of TCx pin is triggered, the contents of the counter are loaded
into TCxDA and the counter is cleared. Then interrupt is generated again. If overflow
before the edge is detected, the FFH is loaded into TCxDA and the overflow interrupt is
generated. During interrupt processing, it can be determined whether or not the
TCxDA value is FFH. After an interrupt (capture to TCxDA or overflow detection) is
generated, capture and overflow detection are halted until TCxDA is read out.
source clock
m
m+1
1
m-1
n
0
1
2
3
FE FF0
1
2
3
K-2
K-1 K 0
n-1
up-counter
TCx pin input
TCxDA
K
n
FF (overflow)
overflow
m
FE
TCxDB
capture
capture
TCx interrupt
reading TCxDA
Figure 6-9b Capture Mode Waveform
6.6.4 Programmable Divider Output (PDO) Mode and Pulse Width
Modulation (PWM) Mode
TCxFF
TCxM2~0=101
TCx interrupt
F/F
PWMx,PDOx pin
Q
clear
TCxM2~0=10x
toggle
8-bit up counter
fc/215
fc/20
MUX
match
Comparator
TCxS
TCxCK2~0
match
Comparator
4
TCxCR
TCxDA_buffer2
TCxDA_buffer1
TCxDB_buffer2
TCxDB_buffer1
TCxDB
Write TCxDA[0]
TCxDA
Data Bus
Figure 6-10a PWM/PDO Mode
46
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
Programmable Divider Output (PDO) Mode
In Programmable Divider Output (PDO) mode, counting up is performed by using the
internal clock. The contents of TCxDA are compared with the contents of up-counter.
The F/F output is toggled and the counter is cleared each time a match is found. The
F/F output is inverted and output to PDO pin. This mode can generate 50% duty pulse
output. The PDO pin is initialized to “0” during reset. A TCx interrupt is generated each
time the PDO output is toggled.
source clock
n
n
0
up-counter
0
1
2
3
n-1
2
3
n-1
3
n
n-1 0
0
1
1
2
1
2
n
TCxDA
PDO pin
(TCxFF = 0)
PDO pin
(TCxFF = 1)
TCx interrupt
Figure 6-10b PDO Mode Waveform
Pulse Width Modulation (PWM) Mode PWM
In Pulse Width Modulation (PWM) Output mode, counting up is performed using the
internal clock with prescaler. The Duty of PWMx is controlled by TCxDB, and the
Period of PWM1 is controlled by TCxDA. The pulse at the PWMx pin is held to a high
level as long as TCxS=1 or Timerx matches TCxDA, while the pulse is held to a low
level as long as Timerx matches TCxDB. Once TCxFF is set to “1”, the signal of PWMx
is inverted. A TCx interrupt is generated and defined by TCxS. On the other hand, the
TCxDA and TCxDB can be written anytime, but the data of TCxDA and TCxDB are
latched only at writing TCxDA[0]. Therefore, the new Duty and new Period of PWM
appear at the PMW pin at the last period–match.
Clock source
Up-counter
n
p
p+2
p+1
p-1
q-1
q
0
1
n-1
n+1 n+2
m-1
m
0
n-1
n
m-1
m
0
n+1 n+2
1
n
p
Duty
duty-match
Writing duty register
period-match
duty-match
duty-match
period-match
period-match
m
q
Period
PWMx
Writing period register
n
p
m
q
TCx interrupt
Figure 6-10c PWM Mode Waveform
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
47
EM78P224N
8-Bit Microcontroller
6.6.5 Buzzer Mode
TCx pin outputs the clock after dividing the frequency.
6.7 LVD (Low Voltage Detector)
Under unstable power source condition, such as external power noise interference or
EMS test condition, a violent power vibration could occur. At the same time, the VDD
could become unstable as it could be operating below the working voltage. When the
system supply voltage (VDD) is below the operating voltage, the IC kernel will
automatically keep all register status.
6.7.1 Low Voltage Reset
The detailed LVR operation mode is as follows:
LVR1
LVR0
VDD Reset Level
VDD Release Level
0
0
1
1
0
1
0
1
4.0V
4.2V
3.7V
2.9V
3.5V
2.7V
NA ( Power-on Reset )
If VDD < 4.0V and is kept for about 5s, the IC will be reset.
If VDD < 3.5V and is kept for about 5s, the IC will be reset.
If VDD < 2.7V and is kept for about 5s, the IC will be reset.
6.7.2 Low Voltage Detect
Registers for LVD Circuit
R_BANK Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 ~ Bit 0
Bank 1
Bank 0
Bank 0
Bank 0
0X49
0X10
0x1B
0x15
LVDCR LVDEN
LVDS1 LVDS0
LVDB
WUCR2
IMR1
LVDWK
LVDIE
ISR1
LVDSF
Corresponding Bits for LVD
LVDEN
LVDS1,LVDS0
LVD Voltage Interrupt Level
VDD < 2.2V
VDD > 2.2V
VDD < 3.3V
VDD > 3.3V
VDD < 4.0V
VDD > 4.0V
VDD < 4.5V
VDD > 4.5V
NA
LVDB
0
1
0
1
0
1
0
1
1
1
11
1
1
10
01
1
0
00
XX
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EM78P224N
8-Bit Microcontroller
Follow the steps below to obtain data from the LVD:
1) Write to the two bits (LVDS1 ~ LVDS0) on the Bank1-R49 register to define the LVD
level (See Section 6.1.37 for details).
2) Set the LVDWK bit if the wake-up function is implemented.
3) Set the LVDIE bit if the interrupt function is implemented.
4) Write “ENI” instruction if the interrupt function is implemented.
5) Set LVDEN bit to “1”.
6) Write “SLEP” instruction or poll /LVDB bit.
7) Clear the interrupt flag bit (LVDSF) when Low Voltage is detected.
NOTE
When the LVDEN bit is set to enable the LVD module, the current consumption will
increase to 10µA.
During the Sleep mode, the LVD module continues to operate. If the device voltage
drop slowly and crosses the detect point, the LVDSF bit will be set and the device
will wake-up from Sleep mode.
When the system resets, the LVD flag will be cleared.
Figure below shows the LVD module detection point in an external voltage condition.
When VDD drops but remains above VLVD, the LVDSF remains at “0”.
When VDD drops, but above VLVD, LVDSF remains at “0”. When VDD drops below
VLVD, LVDSF is set to “1.” If global ENI is enabled, the LVDSF is also set to “1”, and
the next instruction will branch to interrupt vector.
After the VDD rises above VLVD again, the LVDSF will set to “1” again. When the
global ENI is enabled, the next instruction will be executed in the interrupt vector.
Then the LVD interrupt flag is cleared to “0” by software.
When VDD drops below VRESET in less than 80µs, the system will keep all the
registers status, and the system halts but with the oscillation remaining active.
When VDD drops below VRESET but in more than 80µs, a system reset occurs (refer
to Section 6.1.12 for more details).
LVDSF clear by software
VDD
VLVD
VRESET
LVDSF
> 5 us
< 5 us
Internal Reset
18ms
System occur
Vdd < Vreset not longer than 80us,system keep on going
reset
Figure 6-11 LVD Waveform
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
49
EM78P224N
8-Bit Microcontroller
6.8 Oscillator
6.8.1 Oscillator Modes
The MCU can be operated in five different oscillator modes (Fm), such as:
High XTAL Oscillator Mode 2 (HXT2)
High XTAL oscillator mode1 (HXT1)
XTAL oscillator mode (XT)
Low XTAL oscillator mode (LXT)
Internal RC oscillator mode (IRC)
You can select one of the above modes by programming the Option pin. There are two
types of clock source which is used for Fs. Fs is determined by Fss1 and Fss0 options.
The maximum operating frequency of crystal/resonator on the different VDD is listed in
the following table.
Summary of Maximum Operating Speeds
Conditions
VDD
1.8
Fxt max. (MHz)
4
8
Two clocks
3.0
5.0
20
6.8.2 Crystal Oscillator/Ceramic Resonators (XTAL)
The EM78P224N can be
driven by an external clock
signal through the OSCI pin
as shown in the figure at
right.
OSCI
Ext. Clock
OSCO
Figure 6-12a External Clock Input Circuit
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Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation as depicted in the following circuit diagram.
The same thing applies to HXT mode or LXT mode.
C1
C1
Xin
OSCI
XTAL
RS
XTAL
RS
Xout
OSCO
C2
C2
Figure 6-12b Crystal/Resonator Circuits
The table below provides the recommended values of C1 and C2. Since each
resonator has its own attributes, user should refer to its specification for appropriate
values of C1 and C2. The serial resistor, RS; may be required for AT strip cut crystal or
low frequency mode.
Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Source
Oscillator Type
Frequency
455kHz
C1 (pF)
30
C2 (pF)
30
Ceramic Resonators
2.0 MHz
4.0 MHz
100kHz
30
30
30
30
68
68
100K~1 MHz
1M~6 MHz
200kHz
30
30
455kHz
30
30
1.0 MHz
2.0 MHz
4.0 MHz
6.0 MHz
8.0 MHz
10.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
30
30
Main Oscillator
30
30
30
30
Crystal
Oscillator
30
30
6M~12 MHz
30
30
30
30
30
30
12M~20 MHz
20
20
15
15
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51
EM78P224N
8-Bit Microcontroller
6.8.3 Internal RC Oscillator Mode
The EM78P224N offers a versatile internal RC mode with default frequency value of
4 MHz. Internal RC oscillator mode has other frequencies (16 MHz, 8 MHz, and 1
MHz) that can be set by Code Option: RCM1 and RCM0. All these four main
frequencies can be calibrated by programming the Code Option Word 1 Bits C5~C0.
Table below shows a typical drift rate of the calibration.
Internal RC Drift Rate (Ta=25 C, VDD=5V ± 5%, VSS=0V)
Drift Rate
Internal RC
Temperature
(-40℃~+85℃)
±2%
Voltage
(2.3V~5.5V)
±3%
Frequency
Process
Total
1 MHz
4 MHz
8 MHz
16 MHz
±2%
±2%
±2%
±2%
±7%
±7%
±7%
±7%
±2%
±2%
±2%
±3%
±3%
±3%
NOTE
These are theoretical values provided for reference only. Actual values may vary
depending on the actual process.
6.9 Power-on Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply stabilizes to a steady state. The EM78P224N is equipped with a built-in
Power-on Voltage Detector (POVD) with a detecting level of 2.0V. It will work well if
Vdd rises fast enough (50 ms or less). However, under critical applications, extra
devices may still be required to assist in solving power-up problems.
6.10 External Power-on Reset Circuit
The circuits shown at the right
figure implements an external RC
Vdd
to generate the reset pulse. The
R
/RESET
pulse width (time constant) should
be kept long enough for Vdd to
achieve minimum operating
D
Rin
C
voltage. Apply this circuit when the
power supply has a slow rising
time. Since the current leakage
from the /RESET pin is about 5A,
it is recommended that R should
Figure 6-13 External Power-up Reset Circuit
not be greater than 40KΩ in order for the /RESET pin voltage to remain at below 0.2V.
The diode (D) acts as a short circuit at the moment of power down. The capacitor (C)
will discharge rapidly and fully. The current-limited resistor (Rin), will prevent high
current or ESD (electrostatic discharge) from flowing to Pin /RESET.
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EM78P224N
8-Bit Microcontroller
6.11 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residue-voltage remains.
The residue-voltage may trip below Vdd minimum, but not to zero. This condition may
cause a poor power-on reset. Figure 6-14a and Figure 6-14b show how to build a
residue-voltage protection circuit.
Vdd
Vdd
33K
Q1
10K
/RESET
1N4684
40K
Figure 6-14a Residue Voltage Protection Circuit 1
Vdd
Vdd
R1
Q1
/RESET
R2
40K
Figure 6-14b Residue Voltage Protection Circuit 2
6.12 Code Option Register
The EM78P224N has a code option Word that is not part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
Word 0
Word 1
Word 2
Bit 12~Bit 0
Bit 12~Bit 0
Bit 12~Bit 0
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
53
EM78P224N
8-Bit Microcontroller
6.12.1 Code Option Register (Word 0)
Word 0
Bit
Bit 14Bit 13Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2Bit 1Bit 0
Mnemonic
-
-
-
-
-
-
-
-
HLFS
Normal
Green
1
-
-
LVR1 LVR0 RESETEN ENWDT NRHL NRE PR2 PR1 PR0
1
0
High High
Low Low
P67
/RST
1
Disable 32/fc Enable
Enable 8/fc Disable
Enable
Disable
1
-
-
-
-
-
Default
0
1
0
0
0
1
1
1
1
1
1
1
Bit 14:
Bit 13:
Not used. Set to “0” all the time.
Not used. Set to “1” all the time.
Not used. Set to “0” all the time.
Bits 12 ~ 11:
Bit 10 (HLFS):
Reset to Normal or Green Mode select bit
0: CPU is selected as Green mode when a reset occurs.
1: CPU is selected as Normal mode when a reset occurs (default).
Not used. Set to “0” all the time.
Bit 9:
Bits 8 ~ 7 (LVR1 ~ LVR0): LVR Low Voltage Reset Enable bits
LVR1
LVR0
VDD Reset Level
VDD Release Level
0
0
1
1
0
1
0
1
4.0V
4.2V
3.7V
2.9V
3.5V
2.7V
NA ( Power-on Reset )
If VDD < 4.0V and is kept for about 5s, the IC will be reset.
If VDD < 3.5V and is kept for about 5s, the IC will be reset.
If VDD < 2.7V and is kept for about 5s, the IC will be reset.
Bit 6 (RESETEN): P67//RST pin selection bit
0: Enable, /RST pin
1: Disable, P67 pin (default)
Bit 5 (ENWDT): WDT enable bit
0: Enable
1: Disable (default)
Bit 4 (NRHL):
Noise rejection high/low pulse define bit.
0: pulses equal to 8/fc [s] are regarded as signal
1: pulses equal to 32/fc [s] are regarded as signal (default)
NOTE
Under Low XTAL oscillator (LXT) mode, the noise rejection
high/low pulses are always 8/Fm.
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EM78P224N
8-Bit Microcontroller
Bit 3 (NRE): Noise Rejection Enable bit
0: Disable
1: Enable (default)
NOTE
Under Green, Idle, and Sleep modes, the noise rejection circuit is
always disabled.
Bits 2 ~ 0 (Protect): Protect Bit
Protect Bits
Protect
Enable
0
1
Disable (default)
6.12.2 Code Option Register (Word 1)
Word 1
Bit
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
-
-
FSS0 C5
C4
C3
C2
C1
C0 RCM1 RCM0
-
-
OSC2 OSC1 OSC0 RCOUT
1
0
16kHz
32kHz
1
-
-
High High High High High High High
Low Low Low Low Low Low Low
High High High High
-
-
Low Low Low
Low
1
Default
1
1
1
1
1
1
1
1
1
0
0
1
1
Bit 14:
Not used. Set to “0” all the time.
Bit 13 (FSS0): Sub Frequency Selection
FSS0
0
Fs is 32kHz, Xin/Xout pin act as I/O
Fs is 16kHz, Xin/Xout pin act as I/O
1 (default)
Bit 12:
Bits 11 ~ 7 (C4 ~ C0): IRC trim bits
Trimming Code
CA[4] CA[3] CA[2] CA[1] CA[0]
Not used. Set to “0” all the time.
CLK Period
Frequency
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Period*(1+32%) F*(1-24.2%)
Period*(1+30%) F*(1-23.1%)
Period*(1+28%) F*(1-21.9%)
Period*(1+26%) F*(1-20.6%)
Period*(1+24%) F*(1-19.4%)
Period*(1+22%)
F*(1-18%)
Period*(1+20%) F*(1-16.7%)
Period*(1+18%) F*(1-15.3%)
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55
EM78P224N
8-Bit Microcontroller
(Continuation)
Trimming Code
CA[4] CA[3] CA[2] CA[1] CA[0]
CLK Period
Frequency
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Period*(1+16%) F*(1-13.8%)
Period*(1+14%) F*(1-12.3%)
Period*(1+12%) F*(1-10.7%)
Period*(1+10%)
Period*(1+8%)
Period*(1+6%)
Period*(1+4%)
Period*(1+2%)
Period (default)
Period*(1-2%)
Period*(1-4%)
Period*(1-6%)
Period*(1-8%)
F*(1-9.1%)
F*(1-7.4%)
F*(1-5.7%)
F*(1-3.8%)
F*(1-2%)
F (default)
F*(1+2%)
F*(1+4.2%)
F*(1+6.4%)
F*(1+8.7%)
Period*(1-10%) F*(1+11.1%)
Period*(1-12%) F*(1+13.6%)
Period*(1-14%) F*(1+16.3%)
Period*(1-16%)
Period*(1-18%)
Period*(1-20%)
F*(1+19%)
F*(1+22%)
F*(1+25%)
Period*(1-22%) F*(1+28.2%)
Period*(1-24%) F*(1+31.6%)
Period*(1-26%) F*(1+35.1%)
Period*(1-28%) F*(1+38.9%)
Period*(1-30%) F*(1+42.9%)
Bits 6 ~ 5 (RCM1 ~ RCM0): IRC frequency selection bits
RCM1
RCM0
Frequency (MHz)
0
0
1
1
0
1
0
1
1
8
16
4 (default)
Bit 4: Not used. Set to “0” all the time.
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EM78P224N
8-Bit Microcontroller
Bits 3 ~ 1 (OSC2 ~ OSC0): Oscillator modes selection bits
Mode
OSC2 OSC1 OSC0
HXT1(High XTAL1 oscillator mode)
Frequency range: 12 ~ 20 MHz
1
1
1
1
1
1
0
0
1
0
1
0
HXT2 (High XTAL2 oscillator mode)
Frequency range: 6 ~ 12 MHz
XT ( XTAL oscillator mode)
Frequency range: 1 ~ 6 MHz
LXT1 (Low XTAL1 oscillator mode)
Frequency range: 100kHz ~ 1MHz
IRC(Internal RC oscillator mode); OSCI pin act as I/O(default)
IRC(Internal RC oscillator mode); OSCI pin act RCOUT
0
0
1
1
1
0
Bit 0 (RCOUT): System Clock Output Enable Bit in IRC mode
0: OSCI pin output instruction cycle time with open drain
1: OSCI output instruction cycle time (default)
6.12.3 Code Option Register (Word 2)
Word 2
Bit
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
0
0
0
SC3 SC2 SC1 SC0
High High High High
Low Low Low Low
0
0
1
0
0
0
0
0
1
0
Default
1
1
1
1
Bits 14~12:
Not used. Set to “0” all the time.
Bits 11 ~ 8 (SC3 ~ SC0): Trim bits of sub-frequency IRC
Trimming Code
Clock Period Frequency
SC[3] SC[2] SC[1] SC[0]
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Period*(1+32%) F*(1-24.24%)
Period*(1+28%) F*(1-21.88%)
Period*(1+24%) F*(1-19.35%)
Period*(1+20%) F*(1-16.67%)
Period*(1+16%) F*(1-13.79%)
Period*(1+12%) F*(1-10.71%)
Period*(1+8%) F*(1-7.41%)
Period*(1+4%) F*(1-3.85%)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
57
EM78P224N
8-Bit Microcontroller
(Continuation)
Trimming Code
SC[3] SC[2] SC[1] SC[0]
Clock Period
Frequency
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Period (default)
Period*(1-4%)
Period*(1-8%)
F (default)
F*(1+4.17%)
F*(1+8.70%)
Period*(1-12%) F*(1+13.64%)
Period*(1-16%) F*(1+19.05%)
Period*(1-20%) F*(1+25.00%)
Period*(1-24%) F*(1+31.58%)
Period*(1-28%) F*(1+38.89%)
Bits 7 ~ 6:
Not used. Set to “0” all the time.
Not used. Set to “1” all the time.
Not used. Set to “0” all the time.
Bit 5:
Bits 4 ~ 0:
6.12.4 Code Option Register (Word 3)
Word 3
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
1
1
1
1
1
1
1
1
1
ID5
ID4
ID3
ID2
ID1
ID0
1
0
Customer ID
Default
Bits 14 ~ 6:
Bits 5 ~ 0:
Not used. Set to “1” all the time.
Customer ID
6.13 Instruction Set
Each instruction in the Instruction Set is a 15-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6", "CLR R2", etc.). In this case,
the execution takes two instruction cycles.
58
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ",
"DJZA") commands which were tested to be true, to be executed within two instruction
cycles. The instructions that are written to the program counter also take two instruction
cycles.
Moreover, the Instruction Set also offers the following features:
a) Every bit of any register can be set, cleared, or tested directly.
b) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
Instruction Set Convention:
R = Register designator that specifies which one of the registers (including operation and
general purpose registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the Register R and which
affects the operation.
k = An 8 or 12-bit constant or literal value
Mnemonic
NOP
Operation
Status Affected
No Operation
None
DAA
Decimal Adjust A
0 WDT, Stop oscillator
0 WDT
C
SLEP
T, P
WDTC
ENI
T, P
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
[Top of Stack] PC, Enable Interrupt
A R
None
DISI
None
RET
None
RETI
None
MOV R,A
CLRA
None
0 A
Z
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
0 R
Z
R-A A
Z, C, DC
R-A R
Z, C, DC
R-1 A
Z
R-1 R
Z
A R A
Z
A R R
Z
A & R A
Z
A & R R
Z
A R A
Z
A R R
Z
A + R A
Z, C, DC
Z, C, DC
Z
A + R R
R A
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
59
EM78P224N
8-Bit Microcontroller
(Continuation)
Mnemonic
MOV R,R
Operation
Status Affected
R R
Z
Z
COMA R
COM R
INCA R
INC R
/R A
/R R
R+1 A
R+1 R
Z
Z
Z
DJZA R
DJZ R
R-1 A, skip if zero
R-1 R, skip if zero
None
None
R(n) A(n-1),
RRCA R
RRC R
C
C
R(0) C, C A(7)
R(n) R(n-1),
R(0) C, C R(7)
R(n) A(n+1),
RLCA R
RLC R
C
R(7) C, C A(0)
R(n) R(n+1),
R(7) C, C R(0)
C
R(0-3) A(4-7),
R(4-7) A(0-3)
SWAPA R
None
SWAP R
JZA R
R(0-3) R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 R(b)
None
None
None
None
None
None
None
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 [SP],
(Page, k) PC
CALL k
None
JMP k
(Page, k) PC
k A
None
MOV A,k
OR A,k
AND A,k
XOR A,k
None
A k A
A & k A
A k A
Z
Z
Z
k A, [
Top of Stack] PC
RETL k
None
SUB A,k
ADD A,k
SBANK k
GBANK k
k-A A
k+A A
K->R1(4)
K->R1(0)
Z,C,DC
Z,C,DC
None
None
Next instruction:
k kkkk kkkk kkkk
PC+1[SP], kPC
LCALL k
None
Next instruction:
k kkkk kkkk kkkk
KPC
LJMP k
None
None
TBRD R
ROM[(TABPTR)] R
60
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
7 Timing Diagrams
AC Test Input/Output Waveform
2.4
0.4
2.0
0.8
2.0
0.8
TEST POINTS
Note: AC Testing: Input are driven at 2.4V for logic “1,” and 0.4V for logic “0”
Timing measurements are made at 2.0V for logic “1,” and 0.8V for logic “0”
Figure 7-1 AC Test Input/Output Waveform Timing Diagram
Reset Timing (CLK = "0")
Instruction 1
Executed
NOP
CLK
/RESET
Tdrh
Figure 7-2 Reset Timing Diagram
TCC Input Timing (CLKS = "0")
ins
CLK
TCC
tcc
Figure 7-3 TCC Input Timing Diagram
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
61
EM78P224N
8-Bit Microcontroller
8 Absolute Maximum Ratings
Items
Rating
Temperature under bias
Storage temperature
Input voltage
-40C
to
to
to
to
to
to
85C
150C
-65C
Vss-0.3V
Vss-0.3V
2.3V
Vdd+0.5V
Vdd+0.5V
5.5V
Output voltage
Working Voltage
Working Frequency
DC
20 MHz
Note: These parameters are theoretical values only and have not been tested nor verified.
9 DC Electrical Characteristics
Ta=25C, VDD = 5.0V 5%, VSS = 0V
Symbol
Parameter
XTAL: VDD to 3V
Condition
Min. Typ.
Max.
Unit
MHz
MHz
Hz
DC 10(-) 14(8)
DC 20(-) 24(20)
Two cycles with two clocks
Fxt
XTAL: VDD to 5V
IRC: VDD to 5V
4 MHz, 1 MHz, 8kHz, 16 MHz
F
0
IIL
Input Leakage Current for input pins
Internal RC oscillator error per stage
IRC: VDD to 5V
VIN = VDD, VSS
-1
1
A
IRCE
IRC1
IRC2
IRC3
IRC4
IIL
±1
4
%
RCM0:RCM1=1:1
RCM0:RCM1=1:0
RCM0:RCM1=0:1
RCM0:RCM1=0:0
VIN = VDD, VSS
Ports 5, 6, 7, 8
MHz
MHz
MHz
MHz
A
IRC: VDD to 5V
8
IRC: VDD to 5V
16
1
IRC: VDD to 5V
Input Leakage Current for input pins
Input High Voltage (Schmitt trigger )
Input Low Voltage (Schmitt trigger )
-1
0
1
VIH1
VIL1
0.7Vdd
-0.3V
Vdd+0.3V
0.3Vdd
V
Ports 5, 6, 7, 8
V
Input High Threshold Voltage
(Schmitt trigger)
VIHT1
VILT1
VIHT2
VILT2
/RESET
/RESET
TCC, INT
TCC, INT
0.7Vdd
-0.3V
Vdd+0.3V
0.3Vdd
V
V
V
V
Input Low Threshold Voltage
(Schmitt trigger )
Input High Threshold Voltage
(Schmitt trigger)
0.7Vdd
-0.3V
Vdd+0.3V
0.3Vdd
Input Low Threshold Voltage
(Schmitt trigger)
VIHX1 Clock Input High Voltage
VILX1 Clock Input Low Voltage
OSCI in crystal mode
OSCI in crystal mode
VOH = VDD-0.1VDD
2.9
1.7
3.0
1.8
-4
3.1
1.9
V
V
IOH1
Output High Voltage (Ports 5, 6, 7, 8)
mA
Output High Voltage (high drvie)
(Ports 6, 7, 8)
IOH2
VOH = VDD-0.1VDD
-7.5
mA
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Product Specification (V1.4) 05.12.2016
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EM78P224N
8-Bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
Min. Typ. Max. Unit
IOL1
IOL2
Output Low Voltage (Ports 5, 6, 7, 8) VOL = GND+0.1VDD
14
30
mA
mA
Output Low Voltage (high sink)
VOL = GND+0.1VDD
(Ports 6, 7, 8)
Ta= 25C
2.41
2.14
3.1
2.7
2.7
3.5
3.5
4.0
4.0
-75
40
2.99
3.25
3.92
4.25
4.43
4.81
V
V
LVR1 Low voltage reset level
LVR2 Low voltage reset level
LVR3 Low voltage reset level
Ta= -40~85C
Ta= 25C
V
Ta= -40~85C
2.73
3.56
3.16
V
Ta= 25C
V
Ta= -40~85C
V
IPH
IPL
Pull-high current
Pull-low current
Pull-high active, input pin at VSS
Pull-low active, input pin at Vdd
A
A
/RESET= 'High', Fm and Fs off
All input and I/O pins at VDD,
Output pin floating, WDT disabled
Power down current
(Sleep mode)
ISB1
ISB2
ISB3
ICC1
ICC2
ICC3
ICC4
ICC5
1.0
9
A
A
A
A
A
mA
mA
mA
/RESET= 'High', Fm and Fs off
Power down current
(Sleep mode)
All input and I/O pins at VDD,
Output pin floating, WDT enabled
/RESET= 'High', Fm off,
Fs=32kHz (IRC type), output pin
floating, WDT enabled,
Power down current
(Idle mode)
9
/RESET= 'High', Fm off,
Fs=16kHz (IRC type), output pin
floating, WDT enabled
Operating supply current
(Green mode)
19
25
1.2
1.1
2.2
/RESET= 'High', Fm off,
Fs=32KHz (IRC type), output pin
floating, WDT enabled
Operating supply current
(Green mode)
/RESET= 'High', Fm = 4 MHz
(Crystal type), Fs on, output pin
floating, WDT enabled
Operating supply current
(Normal mode)
/RESET= 'High', Fm= 4 MHz (IRC
type), Fs on, output pin floating,
WDT enabled
Operating supply current
(Normal mode)
/RESET= ‘High’,
Fm=10 MHz (Crystal type), Fs on,
Output pin floating, WDT enabled
Operating supply current
(Normal mode)
/RESET= ‘High’,
Operating supply current
(Normal mode)
Fm=16 MHz (IRC type),
Fs on, output pin floating, WDT
enabled
ICC6
ICC7
3.2
3.5
mA
mA
/RESET= ‘High’,
Fm=16 MHz (Crystal type), Fs on,
Output pin floating, WDT enabled
Operating supply current
(Normal mode)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
63
EM78P224N
8-Bit Microcontroller
NOTE
The above parameters are theoretical values only and have not been tested nor
verified.
Data under the “Min.”, “Typ.”, and “Max.” columns are based on theoretical results at
25 C. These data are for design reference only and were not tested or verified.
Internal RC Electrical Characteristics (TA = 25C, VDD = 5V, VSS = 0V)
Drift Rate
Temperature Operating Voltage
Internal RC
Selected Band
Min.
3.92 MHz
Typ.
Max.
4 MHz
16 MHz
8 MHz
1 MHz
25C
25C
25C
25C
5V
5V
5V
5V
4 MHz
4.08 MHz
15.68 MHz 16 MHz 16.32 MHz
7.84 MHz
0.98 MHz
8 MHz
1 MHz
8.16 MHz
1.02 MHz
Internal RC Electrical Characteristics (Process, Voltage, and Temperature
Deviation)
Drift Rate (Process & Operating Voltage and Temperature Variation)
Internal RC
Selected Band
Temperature
-40 ~ 85C
-40 ~ 85C
-40 ~ 85C
-40 ~ 85C
Operating Voltage
2.1V ~ 5.5V
Min.
Typ.
Max.
4 MHz
16 MHz
8 MHz
1 MHz
3.76 MHz
4 MHz
4.24 MHz
4.0V ~ 5.5V
15.36 MHz 16 MHz 16.64 MHz
3.0V ~ 5.5V
7.60 MHz
0.94 MHz
8 MHz
1 MHz
8.40 MHz
1.06 MHz
2.1V ~ 5.5V
64
Product Specification (V1.4) 05.12.2016
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EM78P224N
8-Bit Microcontroller
10 AC Electrical Characteristics
Ta =25C, VDD=5V, VSS=0V
Symbol
Dclk
Parameter
Input CLK duty cycle
Conditions
Min.
45
Typ.
50
Max.
55
Unit
%
Crystal type
IRC type
100
125
DC
ns
Tins
Tpor
Instruction cycle time
DC
ns
Delay time after Power-On-Reset
release
FSS0=1 (16kHz)
16+/-3% *
ms
Crystal type,
WSTO**+510/
µs
HLFS=1
Fm
Delay time after /Reset,WDT,and
LVR release
Trstrl
IRC type HLFS=1
WSTO+8/Fm
µs
µs
µs
µs
ms
HLFS=0
WSTO+8/Fs
Trsth1
Trsth2
Hold time after /RESET pin reset
Hold time after LVR occurred
1
1
FSS0=1 (16kHz)
16+/-3% *
Twdt
Watchdog timer time-out
FSS0=0 (32kHz)
8+/-3%
ms
Tset
Input pin setup time
Input pin hold time
0
ns
ns
Thold
15
20
25
Cload=20pF
Rload=1MΩ
Tdelay
Output pin delay time
20
ns
* Tpor and Twdt: are16 10% ms at FSS0=1(16kHz), Ta=-40~85C, and VDD=2.1~5.5V
** WSTO: Waiting time of Start-to-Oscillation
NOTE
The above parameters are theoretical values only and have not been tested or
verified.
Data under the “Min.”, “Typ.”, and “Max.” columns are based on theoretical results at
25 C. These data are for design reference only and were not tested or verified.
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
65
EM78P224N
8-Bit Microcontroller
11 Device Characteristics
The graphs provided in the following pages were derived based on a limited number of
samples and are shown here for reference only. The device characteristics illustrated
herein are not guaranteed for its accuracy. In some graphs, the data maybe out of the
warranted operating range.
Volt. to Freq. Curve (1MHz)
1060
1040
1020
1000
980
960
940
Chip
Package
2
2.5
3
3.5
4
4.5
5
5.5
Volt. (V)
Figure 11-1a Voltage vs. Frequency Curve (1MHz)
Volt. to Freq. Curve (4MHz)
4.21
4.16
4.11
4.06
4.01
3.96
3.91
3.86
3.81
3.76
Chip
Pacakge
2
2.5
3
3.5
4
4.5
5
5.5
Volt. (V)
Figure 11-1b Voltage vs. Frequency Curve (4MHz)
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Product Specification (V1.4) 05.12.2016
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EM78P224N
8-Bit Microcontroller
Volt. to Freq. Curve (8MHz)
8.42
8.32
8.22
8.12
8.02
7.92
7.82
7.72
7.62
7.52
Chip
Package
3
3.5
4
4.5
5
5.5
Volt. (V)
Figure 11-1c Voltage vs. Frequency Curve (8 MHz)
Volt. to Freq. Curve (16MHz)
16.84
16.64
16.44
16.24
16.04
15.84
15.64
15.44
15.24
15.04
Chip
Package
4
4.5
5
5.5
Volt. (V)
Figure 11-1d Voltage vs. Frequency Curve (16 MHz)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
67
EM78P224N
8-Bit Microcontroller
P5/P6/P7/P8 Vih/Vil vs VDD (Input pin with schmit inverter) at 85℃
3.0
2.5
2.0
1.5
1.0
VIH
VIL
0.5
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
Figure 11-2 VIH/VIL vs. VDD (85°C)
P5/P6/P7/P8 Vih/Vil vs VDD (Input pin with schmit inverter) at 25℃
3.0
2.5
2.0
1.5
1.0
VIH
VIL
0.5
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
Figure 11-3 VIH/VIL vs. VDD (25°C)
68
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(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
P5/P6/P7/P8 Vih/Vil vs VDD (Input pin with schmit inverter) at -40℃
3.0
2.5
2.0
1.5
1.0
0.5
VIH
VIL
2.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
6.0
Figure 11-4 VIH/VIL vs. VDD (-40°C)
Reset Vih vs VDD (Input pin with schmitt inverter)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIH max(-40~85℃)
VIH typ(25℃)
VIH min(-40~85℃)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(V)
Figure 11-5 VIH of RESET Pin vs. VDD
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
69
EM78P224N
8-Bit Microcontroller
Reset Vil vs VDD (Vil, input pins with inverter)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VIL max(-40~85℃)
VIL typ(25℃)
VIL min(-40~85℃)
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(V)
Figure 11-6 VIL of RESET Pin vs. VDD
P5/P6/P7/P8 Ioh1 vs Voh at VDD=5V
0
-5
-10
-15
-20
-25
85℃
25℃
-40℃
-30
0
1
2
3
4
5
Voh (V)
Figure 11-7 VOH vs. IOH1, VDD=5V
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EM78P224N
8-Bit Microcontroller
P5/P6/P7/P8 Ioh1 vs Voh at VDD=3V
0
-2
-4
85℃
25℃
-40℃
-6
-8
-10
-12
0
0.5
1
1.5
Voh (V)
2
2.5
3
Figure 11-8 VOH vs. IOH1, VDD=3V
P6/P7/P8 Ioh2 vs Voh at VDD=5V
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
85℃
25℃
-40℃
0.0
1.0
2.0
3.0
4.0
5.0
Voh (V)
Figure 11-9 VOH vs. IOH2, VDD=5V
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
71
EM78P224N
8-Bit Microcontroller
P6/P7/P8 Ioh2 vs Voh at VDD=3V
0
-2
-4
-6
-8
85℃
25℃
-40℃
-10
-12
-14
-16
-18
-20
0
0.5
1
1.5
2
2.5
3
Voh (V)
Figure 11-10 VOH vs. IOH2, VDD=3V
P5/P6/P7/P8 Iol1 vs Vol at VDD=5V
70
60
50
40
30
20
10
85℃
25℃
-40℃
0
0.0
1.0
2.0
3.0
4.0
5.0
Vol (V)
Figure 11-11 VOL vs. IOL1, VDD=5V
72
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EM78P224N
8-Bit Microcontroller
P5/P6/P7/P8 Iol1 vs Vol at VDD=3V
30
25
20
15
10
5
85℃
25℃
-40℃
0
0
0.5
1
1.5
Vol (V)
2
2.5
3
Figure 11-12 VOL vs. IOL1, VDD=3V
P6/P7/P8 Iol2 vs Vol at VDD=5V
140
120
100
80
85℃
25℃
-40℃
60
40
20
0
0.0
1.0
2.0
3.0
4.0
5.0
Vol (V)
Figure 11-13 VOL vs. IOL2, VDD=5V
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
73
EM78P224N
8-Bit Microcontroller
P6/P7/P8 Iol2 vs Vol at VDD=3V
70
60
50
40
30
20
10
85℃
25℃
-40℃
0
0
0.5
1
1.5
Vol (V)
2
2.5
3
Figure 11-13 VOL vs. IOL, VDD=3V
P5/P6/P7/P8 IPH vs Temperature at VDD=3V&5V
0
-15
-30
-45
-60
-75
-90
3.0V
5.0V
-60
-40
-20
0
20
40
60
80
100
Temperature(℃)
Figure 11-14 IPH vs. Temperature, VDD=3V and 5V
74
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
P7 IPL vs Temperature at VDD=3V&5V
72
63
54
45
36
27
18
9
3.0V
5.0V
0
-60
-40
-20
0
20
40
60
80
100
Temperature(℃)
Figure 11-15 IPL of Ports 7 vs. Temperature, VDD=3V and 5V
Typical & Maximum ICC1 and ICC2 vs Temperature at VDD=5V
16
14
12
10
8
Typ. ICC1
Typ. ICC2
Max. ICC1
Max. ICC2
6
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-16 ICC1 and ICC2 vs. Temperature, VDD=5V
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
75
EM78P224N
8-Bit Microcontroller
Typical & Maximum ICC1 and ICC2 vs Temperature at VDD=3V
10
8
Typ. ICC1
Typ. ICC2
Max. ICC1
Max. ICC2
6
4
2
-60
-40
-20
0
20
40
60
80
100
Temperature(℃)
Figure 11-17 ICC1 and ICC2 vs. Temperature, VDD=3V
Typical & Maximum ICC3 and ICC4 vs Temperature at VDD=5V
1.8
1.7
1.6
1.5
1.4
1.3
Typ. ICC3
Typ. ICC4
Max. ICC3
Max. ICC4
1.2
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-18 ICC3 and ICC4 vs. Temperature, VDD=5V
76
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
Typical & Maximum ICC3 and ICC4 vs Temperature at VDD=3V
1.4
1.2
1.0
0.8
0.6
0.4
Typ. ICC3
Typ. ICC4
Max. ICC3
Max. ICC4
-60
-40
-20
0
20
40
60
80
100
Temperature(℃)
Figure 11-19 ICC3 and ICC4 vs. Temperature, VDD=3V
Typical & Maximum ICC5 vs Temperature at VDD=5V
5
4
3
2
1
0
Typ. ICC5
Max. ICC5
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-20 ICC5 vs. Temperature, VDD=5V
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
77
EM78P224N
8-Bit Microcontroller
Typical & Maximum ICC5 vs Temperature at VDD=3V
5
4
3
2
1
Typ. ICC5
Max. ICC5
0
-60
-40
-20
0
20
40
60
80
100
Temperature(℃)
Figure 11-21 ICC5 vs. Temperature, VDD=3V
Typical & Maximum ICC6 and ICC7 vs Temperature at VDD=5V
8
7
6
5
4
3
Typ. ICC6
Typ. ICC7
Max. ICC6
Max. ICC7
2
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-22 ICC6 and ICC7 vs. Temperature, VDD=5V
78
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
Typical & Maximum ISB1 and ISB2 vs Temperature at VDD=5V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max. ISB1
Max. ISB2
Typ. ISB1
Typ. ISB2
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-23 ISB1 and ISB2 vs. Temperature, VDD=5V
Typical & Maximum ISB1 and ISB2 vs Temperature at VDD=3V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max. ISB1
Max. ISB2
Typ. ISB1
Typ. ISB2
-60
-40
-20
0
20
40
60
80
100
Temperature(℃)
Figure 11-24 ISB1 and ISB2 vs. Temperature, VDD=3V
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
79
EM78P224N
8-Bit Microcontroller
Typical & Maximum ISB3 vs Temperature at VDD=5V
8
7
6
5
4
3
2
1
Max. ISB3
Typ. ISB3
0
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-25 ISB3 and ISB4 vs. Temperature, VDD=5V
Typical & Maximum ISB3 vs Temperature at VDD=3V
8
7
6
5
4
3
2
1
Max. ISB3
Typ. ISB3
0
-60
-40
-20
0
20
40
60
80
100
Temperature(℃)
Figure 11-26 ISB3 and ISB4 vs. Temperature, VDD=3V
80
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
Power Consumption in XT Mode (4MHz)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
max
min
0
.
5
.
0
.
5
.
0
.
5
.
0
.
5
.
0
.
2
2
3
3
4
4
5
5
6
VDD(V)
Figure 11-27 Power Consumption in XT Mode (4MHz)
Power Consumption in Green Mode(16KHz)
18
16
14
12
10
8
max
min
6
4
2
0
.
5
.
0
.
5
.
0
.
5
.
0
.
5
.
0
.
2
2
3
3
4
4
5
5
6
VDD(V)
Figure 11-28 Power Consumption in Green Mode (16KHz)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
81
EM78P224N
8-Bit Microcontroller
P5 Wake-up Time when Sleep to Normal Mode with XTAL
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
85℃
25℃
-40℃
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(V)
Figure 11-29 P5 Wake-up Time when Sleep to Normal, Crystal mode (Sub. Freq.=16kHz, 4 MHz)
P5 Wake-up Time when Sleep to Normal Mode with IRC
3.2
3.1
3.0
85℃
2.9
2.8
2.7
2.6
25℃
-40℃
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(V)
Figure 11-30 P5 Wake-up Time when Sleep to Normal, IRC mode (Sub. Freq.=16kHz, 4 MHz)
82
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
P5 Wake-up Time when Idle to Normal Mode with XTAL
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
85℃
25℃
-40℃
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(V)
Figure 11-31 P5 Wake-up Time when Idle to Normal, Crystal mode (Sub. Freq.=16kHz, 4 MHz)
P5 Wake-up Time when Idle to Normal Mode with IRC
3.2
3.1
3.0
85℃
2.9
2.8
2.7
2.6
25℃
-40℃
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(V)
Figure 11-32 P5 Wake-up Time when Idle to Normal, IRC mode (Sub. Freq.=16kHz, 4 MHz)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
83
EM78P224N
8-Bit Microcontroller
WDT Time_out Period vs VDD in Normal in IRC mode(4MHz)
17.0
16.5
16.0
15.5
85℃
25℃
-40℃
2.0
2.5
3.0
3.5
4.0
VDD(V)
4.5
5.0
5.5
6.0
Figure 11-33 WDT Timer Time-out in Normal, IRC Mode (Sub. Freq.=16kHz, 4 MHz)
WDT Time_out Period vs VDD When Sleep to Normal in IRC
mode(4MHz)
17.0
16.5
85℃
25℃
-40℃
16.0
15.5
2.0
2.5
3.0
3.5
4.0
VDD(V)
4.5
5.0
5.5
6.0
Figure 11-34 WDT Timer Time Out when Sleep to Normal, IRC Mode (4 MHz)
84
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
WDT Time_out Period vs VDD When Idle to Normal in IRC
mode(4MHz)
17.0
16.5
16.0
15.5
85℃
25℃
-40℃
2.0
2.5
3.0
3.5
4.0
VDD(V)
4.5
5.0
5.5
6.0
Figure 11-35 WDT Timer Time-out when in Idle to Normal, IRC Mode (4 MHz)
Power On Reset Time vs VDD in Normal, IRC Mode
16.5
16.0
15.5
15.0
14.5
14.0
85℃
25℃
-40℃
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(V)
Figure 11-36 Power on Reset Time in Normal, IRC Mode (Sub. Freq.=16kHz, 4 MHz)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
85
EM78P224N
8-Bit Microcontroller
IRC OSC Frequency(4MHz) vs Temperature at VDD=3V&5V
4.15
4.10
4.05
4.00
3.95
3.90
3.85
3.80
3.0V
5.0V
3.75
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-37 IRC OSC Freq, vs. Temp. (4MHz)
IRC OSC Frequency(16MHz) vs Temperature at VDD=5V
16.20
16.15
16.10
16.05
16.00
15.95
15.90
15.85
5.0V
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-38 IRC OSC Freq, vs. Temp. (16 MHz)
86
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
IRC OSC Frequency(8MHz) vs Temperature at VDD=3V&5V
8.05
8.00
7.95
7.90
7.85
7.80
7.75
7.70
7.65
3.0V
5.0V
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-39 IRC OSC Freq, vs. Temp. (8MHz)
IRC OSC Frequency(1MHz) vs Temperature at VDD=3V&5V
1.03
1.01
0.99
0.97
0.95
3.0V
5.0V
-60
-40
-20
0
20
40
60
80
100
Temperature (℃)
Figure 11-40 IRC OSC Freq, vs. Temp. (1MHz)
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
87
EM78P224N
8-Bit Microcontroller
LVR Level vs Temperature
6
5
4
3
2
1
0
4.0reset
4.0release
3.5reset
3.5release
2.7reset
2.7release
1.8reset
1.8release
-60
-40
-20
0
20
40
60
80
100
Temperature(℃)
Figure 11-41 LVR Level vs Temperature
LVD Level vs Temperature
6
5
4
3
2
1
0
4.5V(5.5V→0)
4.5V(0→5.5V)
4.0V(5V→0)
4.0V(0→5V)
3.3V(5V→0)
3.3V(0→5V)
2.2V(5V→0)
2.2V(0→5V)
-60
-40
-20
0
20
40
60
80
100
Temperature(℃)
Figure 11-42 LVD Level vs. Temperature
88
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
APPENDIX
A Ordering and Manufacturing Information
EM78P224ND28J
Material Type
J: RoHS complied
S: Sony SS-00259 complied
Contact Elan Sales for details
Pin Number
Package Type
D: DIP
SO: SOP
Check the following section for details
Specific Annotation
Product Number
Product Type
P: OTP
Elan 8-bit Product
For example:
EM78P224ND28S
is EM78P224N with OTP program memory,
in 28-pin DIP 600mil package with Sony SS-00259 complied
IC Mark
‧‧‧‧‧‧‧
Elan Product Number / Package, Material Type
EM78Paaaaaa
1041c bbbbbb
Batch Number
Manufacture Date
“YYWW”
YY is year and WW is week
c is Alphabetical suffix code for Elan use only
‧‧‧‧‧‧‧
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
89
EM78P224N
8-Bit Microcontroller
Ordering Code
EM78P224ND28J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the followingsection
Elan IC Product Number
B Package Type
OTP MCU
EM78P224ND32
EM78P224NSO32
EM78P224NSO32A
EM78P224ND28
EM78P224NK28A
EM78P224NSO28
EM78P224NSS28
Package Type
Pin Count
Package Size
600mil
PDIP
SOP
32
32
32
28
28
28
28
450 mil
SOP
300 mil
PDIP
600 mil
Skinny DIP
SOP
400 mil
300 mil
SSOP
209 mil
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
The Pb content is less than 100ppm and complies with Sony specifications.
Part No.
Electroplate type
EM78P224NS/J
Pure Tin
Sn:100%
232°C
Ingredient (%)
Melting point (°C)
Electrical resistivity (µ cm)
Hardness (hv)
11.4
8~10
Elongation (%)
>50%
90
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
C Packaging Information
C.1 EM78P224ND32 600mil
Figure C-1 EM78P224N 32-Pin PDIP Package Type
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
91
EM78P224N
8-Bit Microcontroller
C.2 EM78P224NSO32 450 mil
Symbol
A
Min.
2.540
0.102
2.540
0.350
Normal
Max.
3.048
0.350
2.744
0.500
A1
A2
b
2.642
c
0.254(TYP)
11.303
E
11.176
13.692
20.300
0.678
11.430
14.502
20.700
1.084
E1
D
14.097
20.500
L
0.881
L1
e
1.194
1.397
1.600
1.27(TYP)
θ
0
8
c
TITLE:
SOP-32L(450MIL) PACKAGE OUTLINE
DIMENSION
File :
Edtion:
A
SO32
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-2 EM78P224N 32-Pin SOP Package Type
92
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
C.3 EM78P224NSO32A 300mil
Figure C-3 EM78P224N 32-Pin SOP Package Type
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
93
EM78P224N
8-Bit Microcontroller
C.4 EM78P224ND28 600mil
Figure C-4 EM78P224N 28-Pin PDIP Package Type
94
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
C.5 EM78P224NK28A 400mil
Figure C-5 EM78P224N 28-Pin Skinny DIP Package Type
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
95
EM78P224N
8-Bit Microcontroller
C.6 EM78P224NSO28 300mil
Symbol Min.
Normal
2.500
Max.
2.630
0.300
0.500
A
A1
b
2.370
0.102
0.350
0.406
0.254 (TYP)
7.500
c
E
7.410
10.000
17.700
0.678
7.590
10.650
18.100
1.084
E1
D
L
10.325
17.900
0.881
L1
e
1.194
1.397
1.600
1.27 (TYP)
θ
0
8
TITLE:
SOP-28L(300MIL)
PACKAGE OUTLINE
DIMENSION
File :
Edtion: A
SO28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-6 EM78P224N 28-Pin SOP Package Type
96
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
EM78P224N
8-Bit Microcontroller
C.7 EM78P224NSS28 209mil
Symbol
Min.
Normal
Max.
2.130
0.250
1.880
0.380
0.200
8.200
5.600
10.500
1.030
A
A1
A2
b
0.050
1.620
0.220
0.090
7.400
5.000
9.900
0.630
1.750
c
E
7.800
5.300
E1
D
L
10.200
0.900
e
θ
0.650 (TYP)
4
0
8
b
e
c
TITLE:
SSOP-28L(209MIL) OUTLINE PACKAGE PACKA
OUTLINE DIMENSION
File :
Edtion:
A
SSO28
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-7 EM78P224N 28-Pin SSOP Package Type
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
97
EM78P224N
8-Bit Microcontroller
D Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=2455°C, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
–
Step 1: TCT, 65°C (15mins)~150°C (15mins), 10 cycles
Step 2: Bake at 125°C, TD (endurance)=24 hrs
Step 3: Soak at 30°C/60%, TD (endurance)=192 hrs
Step 4: IR flow 3 cycles
For SMD IC (such as
SOP, QFP, SOJ, etc)
Pre-condition
(Pkg thickness 2.5mm or
Pkg volume 350mm3 ----2255°C)
(Pkg thickness 2.5mm or
Pkg volume 350mm3 ----2405°C)
Temperature cycle test -65°C (15 min) ~ 150°C (15 min), 200 cycles
–
–
TA =121°C, RH=100%, pressure=2 atm,
Pressure cooker test
TD (endurance)= 96 hrs
High temperature /
TA=85°C , RH=85%, TD (endurance) = 168 , 500 hrs
High humidity test
–
–
High-temperature
TA=150°C, TD (endurance) = 500, 1000 hrs
storage life
High-temperature
operating life
TA=125°C, VCC = Max. operating voltage,
TD (endurance) = 168, 500, 1000 hrs
–
–
Latch-up
TA=25°C, VCC = Max. operating voltage, 800mA/40V
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (HBM)
TA=25°C, ∣± 4KV∣
ESD (MM)
TA=25°C, ∣± 400V∣
VDD-VSS(+),VDD_VSS
(-) mode
D.1 Address Trap Detect
An Address Trap Detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise-caused address error is detected, the MCU will repeat execution of the
program until the noise is eliminated. The MCU will then continue to execute the next
program.
98
Product Specification (V1.4) 05.12.2016
(This specification is subject to change without prior notice)
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