EM78P372KSO20 [ELAN]
8-BIT Microcontroller;
| 型号： | EM78P372KSO20 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-BIT Microcontroller 微控制器 |
| 文件： | 总118页 (文件大小：3451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P372K
8-BIT
Microcontroller
Product
Specification
DOC. VERSION 1.4
ELAN MICROELECTRONICS CORP.
May 2016
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2016 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road
Hsinchu Science Park
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Elan Information
Technology Group
(U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Fax: +852 2723-7780
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-Tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
5
6
7
General Description ................................................................................................1
Features ...................................................................................................................1
Applications.............................................................................................................2
Pin Assignment (Package)......................................................................................2
Block Diagram .........................................................................................................4
Pin Description........................................................................................................5
Functional Description............................................................................................7
7.1 Operational Registers....................................................................................... 7
7.1.1 R0 (Indirect Addressing Register).......................................................................7
7.1.2 R1 (Timer Clock Counter) ...................................................................................7
7.1.3 R2 (Program Counter) and Stack........................................................................7
7.1.4 R3 (Status Register)..........................................................................................10
7.1.5 R4 (RAM Select Register).................................................................................10
7.1.6 Bank 0 R5~R7 (Ports 5~7 I/O Data Register)................................................... 11
7.1.7 Bank 0 R8 (ADC Input Select Register)............................................................ 11
7.1.8 Bank 0 R9 (ADC Control Register) ...................................................................13
7.1.9 Bank 0 RA (ADC Offset Calibration Register)...................................................14
7.1.10 Bank 0 RB (Converted value AD11~AD4 of ADC)............................................15
7.1.11 Bank 0 RC (Converted value AD11~AD8 of ADC)............................................15
7.1.12 Bank 0 RD (Converted value AD7~AD0 of ADC) .............................................16
7.1.13 Bank 0 RE (Interrupt Status 2 and Wake-up Control Register 1) .....................16
7.1.14 Bank 0 RF (Interrupt Status Register 1)............................................................17
7.1.15 Bank 1 R5 (TBHP: Table Point Register)..........................................................18
7.1.16 Bank 1 R6 (TBLP: Table Point Register)...........................................................18
7.1.17 Bank 1 R7 (PWMCON: PWM Control Register)...............................................19
7.1.18 Bank 1 R8 (TMRCON: Timer Control Register)................................................19
7.1.19 Bank 1 R9 (PRD1: PWM1 Time Period) ...........................................................20
7.1.20 Bank 1 RA (PRD2: PWM2 Time Period)...........................................................20
7.1.21 Bank 1 RB (DT1: PWM1 Duty Cycle) ...............................................................20
7.1.22 Bank 1 RC (DT2: PWM2 Duty Cycle) ...............................................................21
7.1.23 Bank 1 RE (LVD Control and Wake-up Control Register 2)...............................21
7.1.24 Bank 1 RF (Mode Select and IRC Switch Register) .........................................22
7.1.25 R10~R1F...........................................................................................................24
7.2 Special Purpose Registers.............................................................................. 25
7.2.1 A (Accumulator).................................................................................................25
7.2.2 CONT (Control Register)...................................................................................25
7.2.3 IOC50 ~ IOC70 (I/O Port Control Register) ......................................................26
7.2.4 IOC80 (Comparator Control Register) ..............................................................26
7.2.5 IOC90 (TMR1: PWM1 Timer)............................................................................26
Product Specification (V1.4) 05.11.2016
iii
Contents
7.2.6 IOCA0 (TMR2: PWM2 Timer) ...........................................................................26
7.2.7 IOCB0 (Pull-down Control Register).................................................................27
7.2.8 IOCC0 (Open-drain Control Register)...............................................................27
7.2.9 IOCD0 (Pull-high Control Register)...................................................................28
7.2.10 IOCE0 (WDT Control Register and Interrupt Mask Register 2)........................28
7.2.11 IOCF0 (Interrupt Mask Register 1)....................................................................29
7.2.12 IOC51 (HSCR1: High Sink Control Register 1) ................................................30
7.2.13 IOC61 (HSCR2: High Sink Control Register 2) ................................................31
7.2.14 IOC71 (HDCR1: High Driver Control Register 1)..............................................31
7.2.15 IOC81 (HDCR2: High Driver Control Register 2)..............................................32
7.2.16 IOC91 (DeadTCR: Dead Time Control Register)..............................................32
7.2.17 IOCA1 (DeadTR: Dead Time Register) ............................................................33
7.2.18 IOCF1 (Pull-high Control Register)...................................................................33
7.3 TCC/WDT and Prescaler............................................................................... 34
7.4 I/O Ports ......................................................................................................... 36
7.4.1 Usage of Ports 5, 7 Input Change Wake-up/Interrupt Function........................38
7.5 Reset and Wake-up....................................................................................... 38
7.5.1 Reset and Wake-up Operation..........................................................................38
7.5.2 Wake-up and Interrupt Modes Operation Summary.........................................41
7.5.3 Register Initial Values after Reset.....................................................................43
7.5.4 Controller Reset Block Diagram........................................................................49
7.5.5 The T and P Status under Status Register........................................................49
7.6 Interrupt.......................................................................................................... 50
7.7 Analog-to-Digital Converter (ADC).................................................................. 52
7.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA) ...............................53
7.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD)...............56
7.7.3 ADC Sampling Time..........................................................................................57
7.7.4 AD Conversion Time.........................................................................................57
7.7.5 ADC Operation during Sleep Mode ..................................................................58
7.7.6 Programming Process/Considerations .............................................................58
7.8 Dual Sets of PWM (Pulse Width Modulation).................................................. 62
7.8.1 Overview ...........................................................................................................62
7.8.2 Increment Timer Counter (TMRX: TMR1 or TMR2)..........................................67
7.8.3 PWM Time Period (TMRX: TMR1 or TMR2).....................................................67
7.8.4 PWM Duty Cycle (DTX: DT1 or DT2; DLX: DL1 or DL2)..................................68
7.8.5 Comparator X....................................................................................................68
7.8.6 PWM Programming Process/Steps...................................................................68
7.9 Timer.............................................................................................................. 69
7.9.1 Overview ...........................................................................................................69
7.9.2 Function Description .........................................................................................69
7.9.3 Programming the Related Registers.................................................................70
7.9.4 Timer Programming Process/Steps ..................................................................70
7.9.5 PWM Cascade Mode ........................................................................................70
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Product Specification (V1.4) 05.11.2016
Contents
7.10 Comparator .................................................................................................... 71
7.11 Oscillator ........................................................................................................ 74
7.11.1 External RC Oscillator Mode.............................................................................78
7.11.2 Internal RC Oscillator Mode..............................................................................79
7.12 Power-on Considerations ............................................................................... 79
7.12.1 Programmable WDT Time-out Period...............................................................79
7.12.2 External Power-on Reset Circuit.......................................................................80
7.12.3 Residual Voltage Protection..............................................................................80
7.13 Code Option ................................................................................................... 81
7.13.1 Code Option Register (Word 0) .......................................................................81
7.13.2 Code Option Register (Word 1) .......................................................................83
7.13.3 Code Option Register (Word 2) .......................................................................84
7.13.4 Code Option Register (Word 3) .......................................................................85
7.13.5 Customer ID Register (Word 0x10)...................................................................85
7.13.6 Customer ID Register (Word 0x11)...................................................................85
7.14 Low Voltage Detector/Low Voltage Reset ....................................................... 86
7.14.1 Low Voltage Reset ............................................................................................86
7.14.2 Low Voltage Detector........................................................................................86
7.14.3 Programming Process ......................................................................................88
7.15 Instruction Set ................................................................................................ 89
Absolute Maximum Ratings..................................................................................91
DC Electrical Characteristics................................................................................91
8
9
9.1 AD Converter Characteristics ......................................................................... 93
9.2 Comparator Characteristics ............................................................................ 94
9.3 OP Characteristics.......................................................................................... 94
9.4 Vref 2V/2.5V/3V/4V Characteristics ................................................................ 95
10 AC Electrical Characteristics................................................................................96
11 Timing Diagrams ...................................................................................................97
Product Specification (V1.4) 05.11.2016
v
Contents
APPENDIX
A
B
C
Ordering and Manufacturing Information ............................................................98
Package Type.........................................................................................................99
Packaging Configuration ....................................................................................100
C.1 EM78P372KD14...........................................................................................100
C.2 EM78P372KSO14 ........................................................................................101
C.3 EM78P372KSO16A......................................................................................102
C.4 EM78P372KD18...........................................................................................103
C.5 EM78P372KSO18 ........................................................................................104
C.6 EM78P372KD20...........................................................................................105
C.7 EM78P372KSO20 ........................................................................................106
C.8 EM78P372KSS20.........................................................................................107
C.9 EM78P372KMS10 ........................................................................................108
C.10 EM78P372KQN16 ........................................................................................109
D
Quality Assurance and Reliability ...................................................................... 110
D.1 Address Trap Detect..................................................................................... 110
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Product Specification (V1.4) 05.11.2016
Contents
Specification Revision History
Version
0.1
Revision Description
Date
Preliminary version
2014/06/11
2014/09/30
1.0
Initial release version
1. Modified the Pin Description
2. Modified the Program Counter Organization and the description in
Section 7.1.3.
1.1
1.2
2015/02/09
2016/01/05
3. Deleted the Block Diagram of ADC in Section 7.1.9.
4. Modified the description about Bank 1 R6 Control Register.
1. Modified the pin description of P51.
2. Added note on dead-time register and on PWM function.
1. Modified the package type in Section 2 Features
2. Added User Application Note
1.3
1.4
2016/03/10
2016/05/11
3. Modified Appendix A “Ordering and Manufacturing Information”
4. Modified Section 7.8.2 Increment Timer Counter.
Modified the User Application Note
Product Specification (V1.4) 05.11.2016
vii
Contents
User Application Note
(Before using this IC, take a look at the following description note, it includes important messages.)
1.
We strongly recommend that users have to individually place an external pull-down or pull-high
resistor (0Ω/1kΩ/10kΩ/100kΩ) on P51 and P50 respectively, no matter what the pin function is.
The purpose of this is to prevent P51 or P50 from floating.
2.
The value in the dead-time register must be less than the value in the duty cycle register, in order
to prevent unexpected behavior on both of the PWM outputs.
3.
4.
The PWM output will not be set, if the duty cycle is “0”.
The internal TCC will stop running when in sleep mode. However, during AD conversion, when
TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is enabled, the TCC will keep
on running.
5.
6.
During ADC conversion, do not perform output instruction to maintain precision for all of the pins.
In order to obtain accurate values, it is necessary to avoid any data transition on the I/O pins
during AD conversion.
When using operational amplifier:
(1) The CMPIE (IOCE0.4), CMPWE (RE.2), and CMPIF (RE.4) bits are invalid.
(2) The comparator interrupt is invalid.
(3) The comparator wake-up is invalid.
7.
8.
The noise rejection function is turned off in the LXT2 and sleep mode.
The Low Voltage Reset (LVR) is designed for unstable power situation. If the EM78P372K is
targeted to operate at 8 MHz, the working voltage should be avoided to drop below 2.5 V. The
LVR does not work in this case when the working voltage is between 2.5 V and POR level.
viii
Product Specification (V1.4) 05.11.2016
EM78P372K
8-bit Microcontroller
1 General Description
The EM78P372K is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. The device has an on-chip 2K13-bit Electrical One Time Programmable Read Only
Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s OTP memory code. Three
Code option bits are also available to meet user’s requirements.
With enhanced OTP-ROM features, the EM78P372K provides a convenient way of developing and verifying
user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates,
using development and programming tools. Users can avail of ELAN’s Writer to easily program their
development code.
2 Features
CPU configuration
Peripheral configuration
2K13 bits on-chip ROM
8-bit real time clock/counter (TCC) with selective
signal sources, trigger edges, and overflow interrupt
808 bits on-chip registers (SRAM)
8-level stacks for subroutine nesting
4 programmable Level Voltage Detector
(LVD) : 4.5V, 4.0V, 3.3V, 2.2V
Three programmable Level Voltage Reset
(LVR) : 4.0V, 3.5V, 2.7V
Less than 1.5 mA at 5V/4 MHz
Typically 15 A, at 3V/32kHz
Typically 2 A, during sleep mode
8-bit multi-channel Analog-to-Digital Converter with
12-bit resolution in Vref mode
Two Pulse Width Modulation (PWM) with
8-bitresolution.
One pair of comparator or OP
(offset voltage: smaller than 10mV)
Ten available interrupts
I/O port configuration
TCC overflow interrupt
Three bidirectional I/O ports: P5, P6, P7
18 I/O pins
Input-port status changed interrupt (wake up from
sleep mode)
Wake-up ports : P5, P70, P71
8 programmable pull-down I/O pins
16 programmable pull-high I/O pins
8 programmable open-drain I/O pins
14 high driver I/O pins
External interrupt
ADC completion interrupt
Comparator status change interrupt
Low voltage detect (LVD) interrupt
PWM period match interrupt
PWM duty match interrupt
14 high sink I/O pins
External interrupt : P60
Special Features:
Operating voltage range:
Programmable free running Watchdog Timer
(4.5ms, 18ms)
2.1V~5.5V at 0C~70C (commercial)
2.3V~5.5V at -40C~85C (industrial)
Power saving Sleep mode
Operating frequency range (based on 2 clocks):
Selectable Oscillation mode
Crystal mode: DC ~ 16 MHz, 3.0V;
DC ~ 8 MHz, 2.5V; DC ~ 4 MHz, 2.1V
ERC mode: DC ~ 2 MHz, 2.1V;
IRC mode
Power-on voltage detector available (1.9V 0.2V)
High EFT immunity (better performance at 4 MHz or
below)
Package Type:
Oscillation mode: 4 MHz, 16 MHz, 8 MHz, 1 MHz
10-pin MSOP 118mil
:
:
:
:
:
:
:
:
:
:
EM78P372KMS10
EM78P372KD14
EM78P372KSO14
EM78P372KSO16A
EM78P372KD18
EM78P372KSO18
EM78P372KD20
EM78P372KSO20
EM78P372KSS20
EM78P372KQN16
Drift Rate
14-pin DIP 300mil
14-pin SOP 150mil
16-pin SOP 150mil
18-pin DIP 300mil
18-pin SOP 300mil
20-pin DIP 300mil
20 pin SOP 300mil
20 pin SSOP 209mil
16-pin QFN 3×3×0.8mm
Internal RC
Frequency
Temperature
(-40°C~85°C)
Voltage
Process
Total
(2.1V~5.5V)
4 MHz
16 MHz
8 MHz
1 MHz
±2%
±2%
±2%
±2%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±4%
±4%
±4%
±4%
Fast set-up time requires only 0.8ms (VDD: 5V
Crystal: 4 MHz, C1/C2: 30pF) in HXT2 mode and 10s in
IRC mode (VDD: 5V, IRC: 4 MHz)
Note: These are Green products which do not contain
hazardous substances.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
1
EM78P372K
8-bit Microcontroller
3 Applications
Charger
Washing machine
Toaster
Control board of an air conditioner
Electromagnetic-stove
Coffee pot
4 Pin Assignment (Package)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P51/ADC1/PWM2
P50/ADC0
P52/ADC2/PWM2A
P53/ADC3/PWM1A
P54/TCC/VREF
P71//RESET
Vss
P52/ADC2/PWM2A
P53/ADC3/PWM1A
P54/TCC/VREF
P71//RESET
Vss
1
2
3
4
5
6
7
14
13
12
11
10
9
P51/ADC1/PMW2
P50/ADC0
P55/ADC6/OSCO/ERCin
P70/ADC5/OSCI/RCOUT
VDD
P55/ADC6/OSCO/ERCin
P70/ADC5/OSCI/RCOUT
VDD
P60//INT
P67/ADC4/PWM1
P66/CIN-
P61
P60//INT
P67/ADC4/PWM1
P66/CIN-
P65/CIN+
P64/CO
8
P61
Figure 4-1 EM78P372KD14/SO14
Figure 4-2 EM78P372KSO16A
1
2
20
19
18
17
16
15
14
13
12
11
P56
P57/ADC7
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P51/ADC1/PWM2
P50/ADC0
P52/ADC2/PWM2A
P51/ADC1/PWM2
P50/ADC0
P52/ADC2/PWM2A
P53/ADC3/PWM1A
P54/TCC/VREF
P71//RESET
Vss
P53/ADC3/PWM1A
P54/TCC/VREF
3
P55/ADC6/OSCO/ERCin
P70/ADC5/OSCI/RCOUT
VDD
4
P55/ADC6/OSCO/ERCin
P70/ADC5/OSCI/RCOUT
VDD
P71//RESET
Vss
5
6
P60//INT
P61
P67/ADC4/PWM1
P66/CIN-
7
P67/ADC4/PWM1
P60//INT
P61
8
P66/CIN-
P65/CIN+
P64/CO
P62
P65/CIN+
P62
9
P63
P64/CO
P63
10
Figure 4-3 EM78P372KD18/SO18
Figure 4-4 EM78P372KD20/SO20/SS20
2
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
P51/ADC1/PWM2
P52/ADC2/PWM2A
1
2
3
4
5
10
9
P50/ADC0
P55/ADC6/OSCO/ERCin
P70/ADC5/OSCI/RCOUT
VDD
8
P53/ADC3/PWM1A
P71//RESET
Vss
7
6
P67/ADC4/PWM1
Figure 4-5 EM78P372KMS10
16
15
14
13
53/ADC3/PWM1A
P54/TCC/VREF
P71//RESET
1
2
3
P70/ADC5/OSCI/RCOUT
VDD
12
11
EM78P372K-QFN16
10
9
P67/ADC4/PWM1
P66/CIN-
4
5
6
7
8
Figure 4-6 EM78P372KQN16
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
3
EM78P372K
8-bit Microcontroller
5 Block Diagram
Ext.
OSC. RC
Int.
Ext.
RC
PC
ROM
Oscillation
Generation
8-level stack
(13 bit)
Instruction
Register
Start-up
timer
PWM2A
PWM1A
P70
P71
WDT
PWM2
PWM1
TCC
Reset
Instruction
Decoder
PWM2
PWM1
P6
TCC
P60
Mux
P61
P62
P63
P64
P65
P66
P67
ALU
R4
LVD
LVR
RAM
Interrupt
control
register
R3 (Status
Reg.)
P5
ACC
P50
P51
P52
P53
P54
P55
P56
P57
Interrupt
circuit
Comparator
(CO) or OP
ADC
Cin+ Cin- CO
Ain0~7
Ext INT
Figure 5-1 Functional Block Diagram
4
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
6 Pin Description
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable
pull-down, pull-high and pin change
wake-up.
P50
ST
CMOS
P50
P51
Remark: Off-chip pull-down or pull-high
ADC Input 0
Remark: Off-chip pull-down or pull-high
ADC0
P51
AN
ST
Bidirectional I/O pin with programmable
pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
CMOS
Remark: Off-chip pull-down or pull-high
ADC Input 1
Remark: Off-chip pull-down or pull-high
ADC1
AN
PWM2 output
Remark: Off-chip pull-down or pull-high
PWM2
CMOS
Bidirectional I/O pin with programmable
P52
ST
CMOS pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
P52
P53
P54
ADC2
AN
ADC Input 2
CMOS Inverse PWM2 output
Bidirectional I/O pin with programmable
CMOS pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
PWM2A
P53
ST
ADC3
AN
ADC Input 3
CMOS Inverse PWM1 output
Bidirectional I/O pin with programmable
PWM1A
P54
ST
CMOS pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
TCC
ST
AN
Real Time Clock/Counter clock input
VREF
ADC external voltage reference
Bidirectional I/O pin with programmable
P55
ST
CMOS pull-down, pull-high and pin change
wake-up.
ADC6
OSCO
ERCin
AN
ADC Input 6
XTAL
P55
Clock output of crystal/ resonator oscillator
AN
External RC input pin
Bidirectional I/O pin with programmable
P56
P57
P56
ST
CMOS pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
Bidirectional I/O pin with programmable
CMOS pull-down, pull-high, high-driver, high-sink
and pin change wake-up.
P57
ST
ST
ADC7
ADC Input 7
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
5
EM78P372K
8-bit Microcontroller
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable
open-drain, pull-high, high-driver and high sink.
P60
/INT
ST
CMOS
P60//INT
ST
External interrupt pin
Bidirectional I/O pins with programmable
open-drain, pull-high, high-driver and high sink.
Bidirectional I/O pins with programmable
open-drain, pull-high, high-driver and high sink.
CMOS
P61~P63
P64/CO
P61~P63 ST
CMOS
P64
CO
ST
ST
ST
ST
ST
ST
Comparator output
Bidirectional I/O pins with programmable
open-drain, pull-high, high-driver and high sink.
CMOS
P65
CIN+
P66
CIN-
P67
P65/CIN+
P66/CIN-
Non-inverting end of comparator
Bidirectional I/O pins with programmable
open-drain, pull-high, high-driver and high sink.
CMOS
Inverting end of comparator
Bidirectional I/O pins with programmable
open-drain, pull-high, high-driver and high sink.
CMOS
P67/ADC4/PWM1
ADC4
PWM1
P70
AN
ADC Input 4
CMOS
PWM1 output
P70
AN
Bidirectional I/O pin
ADC5
OSCI
ADC Input 5
P70/ADC5/OSCI/
RCOUT
XTAL
Clock input of crystal/ resonator oscillator
Clock output of internal RC oscillator
CMOS
ROCUT
Clock output of external RC oscillator
(open-drain)
CMOS
P71
ST
ST
Bidirectional I/O pin (open-drain)
P71//RESET
System reset pin
(should be external pull-high)
/RESET
VDD
VSS
VDD
VSS
Power
Power
Power
Ground
Legend: ST: Schmitt Trigger input
AN: analog pin
XTAL: oscillation pin for crystal/resonator
CMOS: CMOS output
NOTE
We strongly recommend that user has to place an external pull-down or pull-high
resistor (0Ω/1kΩ/10kΩ/100kΩ) on P50 and P51 no matter what the pin function is.
The purpose of this is to prevent P50 or P51 from floating.
6
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7 Functional Description
7.1 Operational Registers
7.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect address pointer. Any instruction using R0 as a pointer, actually accesses the
data pointed by the RAM Select Register (R4).
7.1.2 R1 (Timer Clock Counter)
R1 is incremented by an external signal edge, which is defined by the TE bit (CONT-4)
through the TCC pin, or by the internal clock (Fm/Fs). It is writable and readable as any
other registers. It is defined by resetting PSTE (CONT-3).
The prescaler is assigned to TCC, if the PSTE bit (CONT-3) is reset. The content of the
prescaler counter is cleared only when the TCC register is written with a value.
7.1.3 R2 (Program Counter) and Stack
R3 [5]
A10 A9 A8 A7
~
A0
PC
0000h
Reset vector
CALL
LCALL
RET
0 : PAGE0 0000~03FF
0003h
0006h
0009h
000Ch
000Fh
0012h
0015h
0018h
001Bh
001Eh
0021h
External interrupt
1 : PAGE1 0400~07FF
Port 5, P70, P71 pin change
TCC overflow interrupt
RETL
RETI
Store ACC, R3, R4
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
AD conversion complete interrupt
Comparator interrupt
PWM1 Period Match interrupt
PWM2 Period Match interrupt
PWM1 Duty Match interrupt
PWM2 Duty Match interrupt
Low Voltage Detector interrupt
On-Chip Program memory
07FFh
Figure 7-1 Program Counter Organization
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
7
EM78P372K
8-bit Microcontroller
R2 and hardware stacks are 11-bit wide. The structure is depicted in the Data Memory
Configuration (next page).
Generates 2K13 bits on-chip ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
The contents of R2 are all set to "0"s when a RESET condition occurs.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to jump to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto the
stack. Thus, the subroutine entry address can be located anywhere within a page.
"LJMP" instruction allows direct loading of the program counter bits (A0 ~ A10).
Therefore, "LJMP" allows PC to jump to any location within 2K (211)
"LCALL" instruction loads the program counter bits (A0 ~ A10), and then PC+1 is
pushed onto the stack. Thus, the subroutine entry address can be located anywhere
within 2K (211)
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of
the top of stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of
the PC, and the ninth and above bits of the PC will remain unchanged.
Any instruction (except “ADD R2, A”) that is written to R2 (e.g., "MOV R2, A", "BC R2,
6",) will cause the ninth bit and the above bits (A8 ~ A10) of the PC to remain
unchanged.
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instructions
that are written to R2.
8
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
Register
Bank 0
Register
Bank1
IOC
IOC
Page 0
Page1
Address
R0 (Indirect Addressing
Register)
0 0
R1 (Timer Clock Counter)
R2 (Program Counter)
R3 (Status Register)
R4 (RSR,bank select)
R5 (Port 5 I/O data)
R6 (Port 6 I/O data)
R7 (Port 7 I/O data)
01
02
03
04
R5 (TBHP: Table Point
Register)
IOC51 (HSCR1: High Sink
Control Register1)
IOC50 (Port 5 I/O control)
IOC60 (Port 6 I/O control)
IOC70 (Port 7 I/O control)
05
R6 (TBLP: Table Point
Register)
IOC61 (HSCR2: High Sink
Control Register2)
06
R7 (PWMCON: PWM
Control Register)
IOC71 (HDCR1: High Driver
Control Register1)
07
R8 (ADC Input Select
Register)
R8 (TMRCON: Timer Control
Register)
IOC80 (Comparator Control
Register)
IOC81 (HDCR2: High Driver
Control Register2)
08
IOC91 (DeadTCR:Dead
R9 (ADC Control
Register)
R9 (PRD1: PWM1 Time
Period)
IOC90 (TMR1: PWM1 Timer)
IOCA0 (TMR2: PWM2 Timer)
09
Time Control Register)
IOCA1 (DeadTR:Dead Time
Register)
RA (ADC Offset
Calibration Register)
RA(PRD2: PWM2 Time
Period)
0 A
0 B
0 C
0 D
0 E
0 F
RB (Converted value
AD11~AD4 of ADC)
RB(DT1: PWM1 Duty
Cycle)
IOCB0 (Pull-down Control
Register)
IOCB1 (Reserved)
RC (Converted value
AD11~AD8 of ADC)
RC (DT2: PWM2 Duty
Cycle)
IOCC0 (Open-drain Control
Register)
IOCC1 (Reserved)
IOCD1 (Reserved)
IOCE1 (Reserved)
RD (Converted value
AD7~AD0 of ADC)
IOCD0 (Pull-high Control
Register)
RD (
)
Reserved
IOCE0 (WDT Control
Register and Interrupt Mask
Register 2)
RE (LVD Controland
Wake-up Control Register2)
RE (Interrupt Status2 and
Wake-up Control Register1)
IOCF0 (Interrupt Mask
Register 1)
IOCF1 (Pull-high Control
Register)
RF (Interrupt Status
Register 1)
RF (Mode Select and IRC
Switch Register)
10
:
16 - Byte Common Register
1 F
20
:
Bank
32 x 8
0
Bank
1
32 x 8
3 F
Figure 7-2 Data Memory Configuration
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
9
EM78P372K
8-bit Microcontroller
7.1.4 R3 (Status Register)
Bit 7
RST
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOCS
-
T
P
Z
DC
C
Bit 7 (RST): Bit of reset type
Set to “1” if wake-up from sleep on pin change, comparator status
change, External interrupt, Low Voltage Detector interrupt, or AD
conversion completed. Set to “0” if wake-up from other reset types.
Bit 6 (IOCS): Select the Segment of I/O control register
0 : Segment 0 (IOC50 ~ IOCF0) selected
1 : Segment 1 (IOC51 ~ IOCF1) selected
Not used, set “0” at all the time.
Bit 5:
Bit 4 (T):
Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during
power on, and reset to “0” by WDT time-out (for more details see Section
6.5.2, The T and P Status under Status Register).
Bit 3 (P):
Bit 2 (Z):
Power-down bit. Set to “1” during power-on or by a "WDTC" command
and reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P
Status under Status Register for more details).
Zero flag. Set to "1" if the result of an arithmetic or logic operation is
zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
7.1.5 R4 (RAM Select Register)
Bit 7 (SBANK):Special Register 0X05~0X0F Bank Selection Bit.
0 : SBANK 0
1 : SBANK 1
Bit 6:
Used to select Bank 0 ~ Bank 1 of the register.
Bits 5~0:
Used to select a register (Address: 00~0F, 10~3F) in indirect addressing
mode.
10
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.1.6 Bank 0 R5~R7 (Ports 5~7 I/O Data Register)
R5~R6 and P70, P71 are I/O registers.
7.1.7 Bank 0 R8 (ADC Input Select Register)
The AISR register individually defines the I/O Port as analog input or as digital I/O.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Bit 7 (ADE7): AD converter enable bit of P57 pin
0 : Disable ADC7, P57 functions as I/O pin
1 : Enable ADC7 to function as analog input pin
Bit 6 (ADE6): AD converter enable bit of P55 pin
0 : Disable ADC6, P55 functions as I/O pin
1 : Enable ADC6 to function as analog input pin
Bit 5 (ADE5): AD converter enable bit of P70 pin
0 : Disable ADC5, P70 functions as I/O pin
1 : Enable ADC5 to function as analog input pin
Bit 4 (ADE4): AD converter enable bit of P67 pin
0 : Disable ADC4, P67 functions as I/O pin
1 : Enable ADC4 to function as analog input pin
Bit 3 (ADE3): AD converter enable bit of P53 pin
0 : Disable ADC3, P53 functions as I/O pin
1 : Enable ADC3 to function as analog input pin
Bit 2 (ADE2): AD converter enable bit of P52 pin
0 : Disable ADC2, P52 functions as I/O pin
1 : Enable ADC2 to function as analog input pin
Bit 1 (ADE1): AD converter enable bit of P51 pin
0 : Disable ADC1, P51 functions as I/O pin
1 : Enable ADC1 to function as analog input pin
Bit 0 (ADE0): AD converter enable bit of P50 pin
0 : Disable ADC0, P50 functions as I/O pin
1 : Enable ADC0 to function as analog input pin
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
11
EM78P372K
8-bit Microcontroller
NOTE
The P55/ADC6/OSCO/ERCin pin cannot be applied to OSCO and ADC6 at the same
time.
If P55/ADC6/OSCO/ERCin functions as OSCO oscillator input pin, then ADE6 bit for
R8 must be “0” and ADIS2~0 do not select “110”. The P55/ADC6/OSCO/ERCin pin
priority is as follows:
P55/ADC6/OSCO/ERCin Pin Priority
High
Medium
ADC6
Low
P55
OSCO/ERCin
The P70/ADC5/OSCI/RCOUT pin cannot be applied to OSCI and ADC5 at the same
time.
If P70/ADC5/OSCI/RCOUT acts as OSCI oscillator input pin, then ADE5 bit for R8 must
be “0” and ADIS2~0 do not select “101”. The P70/ADC5/OSCI/RCOUT pin priority is as
follows:
P70/ADC5/OSCI/RCOUT Pin Priority
High
Medium
ADC5
Low
P70
OSCI/RCOUT
The P67/ADC4/PWM1 pin cannot be applied to PWM1 and ADC4 at the same time.
If P67/ADC4/PWM1 functions as ADC4 analog input pin,
The P67/ADC4/PWM1 pin priority is as follows:
P67/ADC4/PWM1 Pin Priority
High
Medium
PWM1
Low
P67
ADC4
The P51/ADC1/PWM2 pin cannot be applied to PWM2 and ADC1 at the same time.
If P51/ADC1/PWM2 functions as ADC1 analog input pin,
The P51/ADC1/PWM2 pin priority is as follows:
P51/ADC1/PWM2 Pin Priority
High
ADC1
Medium
PWM2
Low
P51
The P50/ADC0 pin cannot be applied to and ADC0 at the same time.
If P50/ADC0 functions as ADC0 analog input pin,
The P50/ADC0 pin priority is as follows:
P50/ADC0 Pin Priority
High
ADC0
Low
P50
12
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.1.8 Bank 0 R9 (ADC Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VREFS
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
Bit 7 (VREFS): The input source of Vref of the ADC
0: The Vref of the ADC is connected to internal reference voltage
(default value), and the P54/TCC/VREF pin carries out the
function of P54.
1: The Vref of the ADC is connected to P54/TCC/VREF
NOTE
The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time.
If P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 “TS”
must be “0”.
The VREF/TCC/P54 Pin Priority is as follows:
P54/TCC/VREF Pin Priority
High
Medium
TCC
Low
P54
VREF
Bit 6 and Bit 5 (CKR1 and CKR0): The prescaler of ADC oscillator clock rate
Max. Operation Max. Operation
Frequency
( if TAD=4µs,
match 372N )
Frequency
( if TAD=1µs,
match 372N )
CPUS
CKR1 : CKR0
Operation Mode
1
1
1
1
0
00 (default)
FOSC/16
FOSC/4
FOSC/64
FOSC/1
-
4 MHz
1 MHz
16 MHz
4 MHz
01
10
11
16 MHz
-
-
1 MHz
16K/128kHz
16K/128kHz
Bit 4 (ADRUN): ADC starts to RUN
0: Reset upon completion of the conversion. This bit cannot be reset
through software
1: AD conversion is started. This bit can be set by software
Bit 3 (ADPD): ADC Power-down mode
0: Switch off the resistor reference to save power even while the CPU
is operating.
1: ADC is operating
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
13
EM78P372K
8-bit Microcontroller
Bits 2 ~ 0 (ADIS2 ~ ADIS0): Analog Input Select
ADICS
ADIS2
ADIS1
ADIS0
Analog Input Select
ADC0 / P50
ADC1 / P51
ADC2 / P52
ADC3 / P53
ADC4 / P67
ADC5 / P70
ADC6 / P55
ADC7 / P57
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Internal ADC Channel
Select: OPOUT
1
1
1
0
1
1
x
0
0
x
0
1
Internal ADC Channel
Select: 1/4 VDD
Internal ADC Channel
Select: 1/2 VDD
1
1
1
1
1
1
0
1
Reserved
Reserved
7.1.9 Bank 0 RA (ADC Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
VREF1
VREF0
ADICS
Bit 7 (CALI):
Bit 6 (SIGN):
Calibration enable bit for ADC offset
0: Disable the Calibration
1: Enable the Calibration
Polarity bit of offset voltage
0: Negative voltage
1: Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
EM78P372K
0 LSB
VOF[2]
VOF[1]
VOF[0]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 LSB
4 LSB
6 LSB
8 LSB
10 LSB
12 LSB
14 LSB
14
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
Bits 2 ~ 1 (VREF1 ~ VREF0): ADC internal reference voltage source.
VREFSEL in
Option Word 3
Bit 11
ADC Int. Ref.
Volt
VREF[1]
VREF[0]
0
0
0
0
1
1
1
1
0
0
0
1
VDD
4.0V ± 1%
3.0V ± 1%
2.5V ± 1%
VDD
1
0
1
1
0
0
0
1
4.0V ± 1%
3.0V ± 1%
2.0V ± 1%
1
0
1
1
If VREF[1:0]＝00, internal reference does not turn on. If VREF[1:0]≠00, internal
reference will turn on automatically. Moreover, the power of internal reference is
irrelevant to power of ADC. That means one of VREF[1:0] is set, the internal reference
turns on.
If VREF[1:0]＝11, internal reference will turn on by code option selected with VREF
2.0V or VREF 2.5V.
Bit 0 (ADICS): ADC internal channel select. (Select ADC internal 1/4 VDD or OP
output pin connects to ADC input)
0 : Disable
1 : Enable
7.1.10 Bank 0 RB (Converted value AD11~AD4 of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
When AD conversion is completed, the result is loaded into the ADDATA. The ADRUN
bit is cleared and the ADIF is set.
RB is read only.
7.1.11 Bank 0 RC (Converted value AD11~AD8 of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
AD11
AD10
AD9
AD8
When AD conversion is completed, the result is loaded into the ADDATA1H. The
ADRUN bit is cleared and the ADIF is set.
RC is read only.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
15
EM78P372K
8-bit Microcontroller
7.1.12 Bank 0 RD (Converted value AD7~AD0 of ADC)
Bit 7
AD7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD6
AD5
AD4
AD3
AD2
AD1
AD0
When AD conversion is completed, the result is loaded into the ADDATA1L. The
ADRUN bit is cleared and the ADIF is set.
RD is read only
7.1.13 Bank 0 RE (Interrupt Status 2 and Wake-up Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
ADIF
CMP1IF
ADWE
CMPWE
ICWE
LVDWE
Note: 1. RE <5, 4> can be cleared by instruction but cannot be set.
2. IOCE0 is the interrupt mask register.
3. Reading RE will result to “Logic AND” of the RE and IOCE0.
Bit 7 (/LVD):
Low voltage Detector state. This is a read only bit. When the VDD
pin voltage is lower than LVD voltage interrupt level (selected by
LVD1 and LVD0), this bit will be cleared.
0 : Low voltage is detected
1 : Low voltage is not detected or LVD function is disabled
Bit 6 (LVDIF):
Bit 5 (ADIF):
Low Voltage Detector Interrupt flag
LVDIF is reset to “0” by software.
Interrupt flag for Analog to Digital conversion. Set when AD
conversion is completed. Reset by software.
0 : no interrupt occurs
1 : with interrupt request
Bit 4 (CMP1IF): Comparator 1 Interrupt flag. Set when a change occurs in the
Comparator 1 output. Reset by software.
0 : no interrupt occurs
1 : with interrupt request
Bit 3 (ADWE): ADC wake-up enable bit
0 : Disable ADC wake-up
1 : Enable ADC wake-up
When AD Conversion enters sleep/idle mode, this bit must be set to
“Enable”.
16
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
Bit 2 (CMPWE): Comparator wake-up enable bit
0 : Disable Comparator wake-up
1: Enable Comparator wake-up
When Comparator 1 enters sleep/idle mode, this bit must be set to
“Enable”.
Bit 1 (ICWE):
Port 5, P70, and P71 input change to wake-up status enable bit
0 : Disable Port 5, P70, P71 input change to wake-up status
1 : Enable Port 5, P70, P71 input change to wake-up status
When Port 5, P70, P71 change enters sleep/idle mode, this bit must
be set to “Enable”.
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit
0 : Disable Low Voltage Detect wake-up
1 : Enable Low Voltage Detect wake-up
When the Low Voltage Detect is used to enter an interrupt vector or to
wake-up the IC from sleep/idle with Low Voltage Detect running, the
LVDWE bit must be set to “Enable”.
7.1.14 Bank 0 RF (Interrupt Status Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P7ICIF
DT2IF
DT1IF
PWM2IF PWM1IF
EXIF
ICIF
TCIF
Note: 1. “1” means there is an interrupt request, “0” means no interrupt occurs.
2. RF can be cleared by instruction but cannot be set.
3. IOCF0 is the interrupt mask register.
4. Reading RF will result to “Logic AND” of the RF and IOCF0.
Bit 7 (P7ICIF):
Port 7 input status change interrupt flag. Set when Port 7 input
changes. Reset by software.
Bit 6 (DT2IF):
Bit 5 (DT1IF):
PWM2 duty match interrupt flag. Reset by software.
PWM1 duty match interrupt flag. Reset by software.
Bit 4 (PWM2IF): PWM2 period match interrupt flag. Reset by software.
Bit 3 (PWM1IF): PWM1 period match interrupt flag. Reset by software.
Bit 2 (EXIF):
Bit 1 (ICIF):
Bit 0 (TCIF):
External interrupt flag. Set by falling edge on /INT pin. Reset by
software.
Port 5 input status change interrupt flag. Set when Port 5 input
changes. Reset by software.
TCC overflow interrupt flag. Set when TCC overflows. Reset by
software.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
17
EM78P372K
8-bit Microcontroller
7.1.15 Bank 1 R5 (TBHP: Table Point Register)
Bit 7
MLB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRS
-
-
-
RBit10
RBit9
RBit8
Bit 7 (MLB): Choosing MSB or LSB machine code to be moved to the register.
The machine code is pointed by TBLP and TBHP register.
Bit 6 (TRS): Table Read Select
0: read ROM
1: read Customer ID Register
NOTE
When TRS = 1 (read Customer ID Register)
■ Can read Customer ID Register II, III (Word 0x10 or Word 0x11)
■ Cannot read Customer ID Register I (Word 2)
■ Don’t care RBit10 ~ RBit3
Bits 5~3: Not used, set to “0” at all time.
Bits 2~0: These are the most 3 significant bits of address for program code.
7.1.16 Bank 1 R6 (TBLP: Table Point Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBit7
RBit6
RBit5
RBit4
RBit3
RBit2
RBit1
RBit0
Bits 7~0 (RBit7~RBit0): Table point low byte bits.
When TRS = 0 (Read ROM):
RBit7~RBit6 are the least 8 significant bits of address for program code.
When TRS = 1 (Read Customer ID Register):
RBit7 RBit6 RBit5 RBit4 RBit3 RBit2 RBit1 RBit0
Customer ID
Word 0x10
Word 0x11
Reserved
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
1
0
0
1
x
0
1
x
x
Reserved
NOTE
■ Bank 1 R6 overflow will carry to Bank 1 R5.
■ Bank 1 R6 underflow will borrow from Bank 1 R5.
18
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.1.17 Bank 1 R7 (PWMCON: PWM Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IPWM2E IPWM1E
-
-
-
PWMCAS PWM2E
PWM1E
Bit 7 (IPWM2E): Inverse PWM2 Enable bit
0: Inverse PWM2 is off (default value), and its related pin carries out the
P52 function.
1: Inverse PWM2 is on, and its related pin is automatically set to output.
Bit 6 (IPWM1E): Inverse PWM1 Enable bit
0: Inverse PWM1 is off (default value), and its related pin carries out the
P53 function.
1: Inverse PWM1 is on, and its related pin is automatically set to output.
Bits 5 ~ 3:
Not used
Bit 2 (PWMCAS):PWM Cascade Mode
0: Two Independent 8-bit PWM function (default value)
1: 16-bit PWM Mode (Cascaded from two 8-bit PWM function)
Bit 1 (PWM2E): PWM2 Enable bit
0: PWM2 is off (default value), and its related pin carries out the P67
function.
1: PWM2 is on, and its related pin is automatically set to output.
Bit 0 (PWM1E): PWM1 Enable bit
0: PWM1 is off (default value), and its related pin carries out the P51
function.
1: PWM1 is on, and its related pin is automatically set to output.
7.1.18 Bank 1 R8 (TMRCON: Timer Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T2EN
T1EN
T2P2
T2P1
T2P0
T1P2
T1P1
T1P0
Bit 7 (T2EN): TMR2 Enable bit
0: TMR2 is off (default value)
1: TMR2 is on
Bit 6 (T1EN): TMR1 Enable bit
0: TMR1 is off (default value)
1: TMR1 is on
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
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EM78P372K
8-bit Microcontroller
Bit 5 ~ Bit 3 (T2P2 ~ T2P0): TMR2 clock prescaler option bits
T2P2
T2P1
T2P0
Prescaler
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
Bit 2 ~ Bit 0 (T1P2 ~ T1P0): TMR1 clock prescaler option bits
T1P2
T1P1
T1P0
Prescaler
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
7.1.19 Bank 1 R9 (PRD1: PWM1 Time Period)
The content of Bank 1-R9 is the time period (time base) of PWM1. The frequency of
PWM1 is the reverse of the period.
7.1.20 Bank 1 RA (PRD2: PWM2 Time Period)
The content of Bank 1-RA is the time period (time base) of PWM2. The frequency of
PWM2 is the reverse of the period.
7.1.21 Bank 1 RB (DT1: PWM1 Duty Cycle)
A specified value keeps the output of PWM1 to remain high until the value matches with
TMR1.
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Product Specification (V1.4) 05.11.2016
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EM78P372K
8-bit Microcontroller
7.1.22 Bank 1 RC (DT2: PWM2 Duty Cycle)
A specified value keeps the output of PWM2 to remain high until the value matches with
TMR2.
7.1.23 Bank 1 RE (LVD Control and Wake-up Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIE
LVDEN
LVD1
LVD0
-
-
-
EXWE
Bit 7 (LVDIE): Low voltage Detector interrupt enable bit
0 : Disable Low voltage Detector interrupt
1 : Enable Low voltage Detector interrupt
When detect low level voltage is used to enter an interrupt vector or
enter the next instruction, the LVDIE bit must be set to “Enable”.
Bit 6 (LVDEN): Low Voltage Detector enable bit
0 : Low voltage detector disable
1 : Low voltage detector enable
Bits 5~4 (LVD1:0): Low Voltage Detector level bits.
LVDEN
LVD1, LVD0
LVD Voltage Interrupt Level
Vdd 2.2V
Vdd 2.2V
Vdd 3.3V
Vdd 3.3V
Vdd 4.0V
Vdd 4.0V
Vdd 4.5V
Vdd 4.5V
NA
/LVD
0
1
0
1
0
1
0
1
1
1
11
1
1
10
01
1
0
00
XX
Bits 3~1: Not used, set to “0” at all time.
Bit 0 (EXWE): External /INT wake-up enable bit
0: Disable External /INT pin wake-up
1: Enable External /INT pin wake-up
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
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EM78P372K
8-bit Microcontroller
7.1.24 Bank 1 RF (Mode Select and IRC Switch Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
TIMERSC CPUS
IDLE
SHS1
SHS0
RCM1
RCM0
Bit 7: Not used. Set “0” all the time.
Bit 6 (TIMERSC): TCC, PWM1, PWM2 clock sources select 0/1 Fs/Fm*
0 : Fs: Sub-oscillator clock from WDT 16kHz ± 30% or System
hold RC 128kHz ± 30% (determined by Word 2 SFS bit)
1 : Fm: main-oscillator clock
Bit 5 (CPUS):
CPU Oscillator Source Select
0 : Sub-oscillator (Fs)
1 : Main-oscillator (Fm)
When CPUS=0, the CPU oscillator selects the sub-oscillator and
the main oscillator is stopped.
Bit 4 (IDLE):
Idle Mode Enable Bit. From SLEP instruction, this bit will determine
as to which mode to go.
0 : Idle= “0”+SLEP instruction Sleep mode
1 : Idle= “1”+SLEP instruction Idle mode
Bits 3 ~ 2 (SHS1~0): Select AD sample and hold period.
SHS1
SHS0
AD Sample and Hold Period (TAD)
0
0
1
1
0
1
0
1
2
4
8
12 (default)
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EM78P372K
8-bit Microcontroller
CPU Operation Mode
Normal mode
Fm: oscillation
Fs: oscillation
CPU: using Fm
wakeup
Interrupt or
wakeup
IDLE=0
+ SLEP
CPUS=1
CPUS=0
IDLE=1
+ SLEP
IDLE=1
wakeup
Idle mode
Fm: stop
+ SLEP
Sleep mode
Green mode
(*)
(**)
(**)
Fm : stop
Fs : stop
Fm : stop
Fs : oscillation
CPU : using Fs
Fs: oscillation
CPU: stop
CPU : stop
Interrupt or
wakeup
IDLE=0
+ SLEP
Figure 7-5 CPU Operation Mode
(*)
If the Watchdog function is enabled before going into sleep mode, some circuits like the Timer (its
clock source is Fs) must stop counting.
If the Watchdog function is enabled before going into sleep mode, some circuits like the Timer (its
clock source is an external pin) can still count and its Interrupt flag can be active at matching
conditions, as corresponding interrupt is enabled. But CPU cannot be awakened by this event.
(**)
Switching Operation Mode from Sleep Normal, Green Normal
If the clock source of the Timer is Fm, the Timer/Counter must stop counting at Sleep or Green
mode. Then the Timer can continue to count until the clock source is stable at Normal mode. That
the clock source is stable means that the CPU starts to work at Normal mode.
Switching Operation Mode from Sleep Green
If the clock source of the Timer is Fs, the Timer must stop counting at Sleep mode. Then the
Timer can continue to count until the clock source is stable at Green mode. That the clock source
is stable means that the CPU starts to work at Green mode.
Switching Operation Mode from Sleep Normal
If the clock source of the Timer is Fs, the Timer must stop counting at Sleep mode. Then the
Timer can continue to count until the clock source is stable at Normal mode. That the clock
source is stable means that the CPU starts to work at Normal mode.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
23
EM78P372K
8-bit Microcontroller
NOTE
■ Crystal MOD1 for LXT1, XT, HXT2, HXT1:
Sleep Normal = Oscillator Stable Time + 510 clock (main frequency).
Sleep Green = Oscillator Stable Time + 8 clock (sub frequency).
Green Normal = Oscillator Stable Time + 510 clock (main frequency)
NOTE
■ Crystal MOD2 for LXT2 :
Sleep Normal = Oscillator Stable Time + 254 clock (main frequency).
Sleep Green = Oscillator Stable Time + 8 clock (sub frequency).
Green Normal = Oscillator Stable Time + 254 clock (main frequency)
■ IRC MOD :
Sleep Normal = Oscillator Stable Time + 8 or 32 clock (main frequency).
Sleep Green = Oscillator Stable Time + 8 clock (sub frequency).
Green Normal = Oscillator Stable Time + 8 clock (main frequency)
Bits 3~2: Not used, set to “0” at all time.
Bits 1~0 (RCM1~RCM0): IRC mode selection bits
RCM 1
RCM 0
*Frequency (MHz)
1
1
0
0
1
0
1
0
4
16
8
1
NOTE
■ Word 2 <11> COBS0=0 :
Bank 1 RF<1~0> of the initialized values will be kept the same as Word 1<6~5>.
Bank 1 RF<1~0> cannot change
■ Word 2<11> COBS0=1 :
Bank 1 RF<1~0> of the initialized values will be kept the same as Word 1<6~5>.
Bank 1 RF<1~0> can change, When user wants to work on other IRC frequency.
Stable Time is 8 clocks
7.1.25 R10~R1F
All of these are 8-bit general-purpose registers.
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EM78P372K
8-bit Microcontroller
7.2 Special Purpose Registers
7.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
7.2.2 CONT (Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTE
INT
TS
TE
PSTE
PST2
PST1
PST0
Note: The CONT register is both readable and writable.
Bit 6 is read only.
Bit 7 (INTE):
INT signal edge
0 : Interrupt occurs at a rising edge of the INT pin
1 : Interrupt occurs at a falling edge of the INT pin
Bit 6 (INT):
Interrupt Enable flag
0 : Masked by DISI or hardware interrupt
1 : Enabled by the ENI/RETI instructions
This bit is readable only.
TCC signal source
Bit 5 (TS):
Bit 4 (TE):
0 : Internal instruction cycle clock. If P54 is used as I/O pin
1 : Transition on the TCC pin
TCC signal edge
0 : Increment if the transition from low to high takes place on the
TCC pin
1 : Increment if the transition from high to low takes place on the
TCC pin.
Bit 3 (PSTE):
Prescaler enable bit for TCC
0 = prescaler disable bit. TCC rate is 1:1.
1 = prescaler enable bit. TCC rate is set at Bit 2 ~ Bit 0.
Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1
1
1
1:256
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25
EM78P372K
8-bit Microcontroller
Note:
1
TCC Timeout period
256 TCC cnt 1 ,
FT
where
FT Fm or Fs , decide by BANK1 RF TIMERSC bit.
7.2.3 IOC50 ~ IOC70 (I/O Port Control Register)
"0" defines the relative I/O pin as output
"1" sets the relative I/O pin into high impedance
7.2.4 IOC80 (Comparator Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
CMPOUT
COS1
COS0
–
–
–
Note: Bits 4~0 of the IOC80 register are both readable and writable.
Bit 5 of the IOC80 register is read only.
Bit 7 and Bit 6: Not used
Bit 5 (CMPOUT): Result of the comparator output. This bit is readable only.
Bit 4 and Bit 3 (COS1 and COS0): Comparator/OP Select bits
COS1
COS0
Function Description
0
0
0
1
Comparator and OP are not used. P64, P65, and P66 are normal I/O pins
P65 and P66 are Comparator input pins and P64 is a normal I/O pin
P65 and P66 are Comparator input pins and P64 is a Comparator output
pin (CO)
1
1
0
1
Used as OP and P64 is OP output pin (CO)
Bits 2~0: Not used.
7.2.5 IOC90 (TMR1: PWM1 Timer)
7.2.6 IOCA0 (TMR2: PWM2 Timer)
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EM78P372K
8-bit Microcontroller
7.2.7 IOCB0 (Pull-down Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PD57
/PD56
/PD55
/PD54
/PD53
/PD52
/PD51
/PD50
The IOCB0 register is both readable and writable.
Bit 7 (/PD57): Control bit used to enable internal pull-down of the P57 pin.
0 : Enable internal pull-down
1 : Disable internal pull-down
Bit 6 (/PD56): Control bit used to enable internal pull-down of the P56 pin.
Bit 5 (/PD55): Control bit used to enable internal pull-down of the P55 pin.
Bit 4 (/PD54): Control bit used to enable internal pull-down of the P54 pin.
Bit 3 (/PD53): Control bit used to enable internal pull-down of the P53 pin.
Bit 2 (/PD52): Control bit used to enable internal pull-down of the P52 pin.
Bit 1 (/PD51): Control bit used to enable internal pull-down of the P51 pin.
Bit 0 (/PD50): Control bit used to enable internal pull-down of the P50 pin.
7.2.8 IOCC0 (Open-drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD67
OD66
OD65
OD64
OD63
OD62
OD61
OD60
The IOCC0 register is both readable and writable.
Bit 7 (OD67): Control bit used to enable open-drain output of the P67 pin.
0 : Disable open-drain output
1 : Enable open-drain output
Bit 6 (OD66): Control bit used to enable open-drain output of the P66 pin.
Bit 5 (OD65): Control bit used to enable open-drain output of the P65 pin.
Bit 4 (OD64): Control bit used to enable open-drain output of the P64 pin.
Bit 3 (OD63): Control bit used to enable open-drain output of the P63 pin.
Bit 2 (OD62): Control bit used to enable open-drain output of the P62 pin.
Bit 1 (OD61): Control bit used to enable open-drain output of the P61 pin.
Bit 0 (OD60): Control bit used to enable open-drain output of the P60 pin.
Product Specification (V1.4) 05.11.2016
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EM78P372K
8-bit Microcontroller
7.2.9 IOCD0 (Pull-high Control Register)
Bit 7
/PH57
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
The IOCD0 register is both readable and writable.
Bit 7 (/PH57): Control bit used to enable internal pull-high of the P57 pin.
0 : Enable internal pull-high
1 : Disable internal pull-high
Bit 6 (/PH56): Control bit used to enable internal pull-high of the P56 pin.
Bit 5 (/PH55): Control bit used to enable internal pull-high of the P55 pin.
Bit 4 (/PH54): Control bit used to enable internal pull-high of the P54 pin.
Bit 3 (/PH53): Control bit used to enable internal pull-high of the P53 pin.
Bit 2 (/PH52): Control bit used to enable internal pull-high of the P52 pin.
Bit 1 (/PH51): Control bit used to enable internal pull-high of the P51 pin.
Bit 0 (/PH50): Control bit used to enable internal pull-high of the P50 pin.
7.2.10 IOCE0 (WDT Control Register and Interrupt Mask Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS
ADIE
CMPIE
PSWE
PSW2
PSW1
PSW0
Bit 7 (WDTE): Control bit used to enable Watchdog Timer
0 : Disable WDT
1 : Enable WDT
WDTE is both readable and writable.
Bit 6 (EIS):
Control bit used to define the function of the P60 (/INT) pin
0 : P60, bidirectional I/O pin
1 : /INT, external interrupt pin. In this case, the I/O control bit of P60
(Bit 0 of IOC60) must be set to "1".
NOTE
■ When EIS is "0", the path of /INT is masked. When EIS is "1", the status of the /INT
pin can also be read by way of reading Port 6 (R6).
■ EIS is both readable and writable.
Bit 5 (ADIE): ADIF interrupt enable bit
0 : Disable ADIF interrupt
1 : Enable ADIF interrupt
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EM78P372K
8-bit Microcontroller
Bit 4 (CMPIE): CMPIF interrupt enable bit.
0 : Disable CMPIF interrupt
1 : Enable CMPIF interrupt
Bit 3 (PSWE): Prescaler enable bit for WDT
0 : Prescaler disable bit, WDT rate is 1:1
1 : Prescaler enable bit, WDT rate is set as Bit 2 ~ Bit 0
Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits
PSW2 PSW1 PSW0 WDT Rate
1:2
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
7.2.11 IOCF0 (Interrupt Mask Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P7ICIE
DT2IE
DT1IE
PWM2IE PWM1IE
EXIE
ICIE
TCIE
Note: The IOCF0 register is both readable and writable.
Individual interrupt is enabled by setting to “1” its associated control bit in the IOCF0 and
in IOCEO Bits 4 and 5.
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
Bit 7 (P7ICIE): P7ICIF interrupt enable bit
0 : Disable ICIF interrupt
1 : Enable ICIF interrupt
Bit 6 (DT2IE):
Bit 5 (DT1IE):
DT2IE interrupt enable bit
0 : Disable DT2IF interrupt
1 : Enable DT2IF interrupt
DT1IE interrupt enable bit
0 : Disable DT1IF interrupt
1 : Enable DT1IF interrupt
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EM78P372K
8-bit Microcontroller
Bit 4 (PWM2IE): PWM2IE interrupt enable bit
0 : Disable PWM2IF interrupt
1 : Enable PWM2IF interrupt
Bit 3 (PWM1IE): PWM1IE interrupt enable bit
0 : Disable PWM1IF interrupt
1 : Enable PWM1IF interrupt
Bit 2 (EXIE):
Bit 1 (ICIE):
Bit 0 (TCIE):
EXIF interrupt enable bit
0 : Disable EXIF interrupt
1 : Enable EXIF interrupt
ICIF interrupt enable bit
0 : Disable ICIF interrupt
1 : Enable ICIF interrupt
TCIF interrupt enable bit.
0 : Disable TCIF interrupt
1 : Enable TCIF interrupt
7.2.12 IOC51 (HSCR1: High Sink Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HS57
HS56
-
HS54
HS53
HS52
HS51
-
Bit 7 (HS57): Output High Sink Current Select for P57
Bit 6 (HS56): Output High Sink Current Select for P56
Bit 5: Not used
Bit 4 (HS54): Output High Sink Current Select for P54
Bit 3 (HS53): Output High Sink Current Select for P53
Bit 2 (HS52): Output High Sink Current Select for P52
Bit 1 (HS51): Output High Sink Current Select for P51
Bit 0: Not used
HDxx
VDD = 5V, Sink Current
10 mA (in 0.1VDD)
0
1
25 mA (in 0.1VDD)
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EM78P372K
8-bit Microcontroller
7.2.13 IOC61 (HSCR2: High Sink Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HS67
HS66
HS65
HS64
HS63
HS62
HS61
HS60
Bit 7 (HS67): Output High Sink Current Select for P67
Bit 6 (HS66): Output High Sink Current Select for P66
Bit 5 (HS65): Output High Sink Current Select for P65.
Bit 4 (HS64): Output High Sink Current Select for P64
Bit 3 (HS63): Output High Sink Current Select for P63
Bit 2 (HS62): Output High Sink Current Select for P62
Bit 1 (HS61): Output High Sink Current Select for P61
Bit 0 (HS60): Output High Sink Current Select for P60
HDxx
VDD = 5V, Sink Current
10 mA (in 0.1VDD)
0
1
25 mA (in 0.1VDD)
7.2.14 IOC71 (HDCR1: High Driver Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HD57
HD56
-
HD54
HD53
HD52
HD51
-
Bit 7 (HD57): Output High Driver Current Select for P57
Bit 6 (HD56): Output High Driver Current Select for P56
Bit 5: Not used
Bit 4 (HD54): Output High Driver Current Select for P54
Bit 3 (HD53): Output High Driver Current Select for P53
Bit 2 (HD52): Output High Driver Current Select for P52
Bit 1 (HD51): Output High Driver Current Select for P51
Bit 0: Not used
HDxx
VDD = 5V, Drive Current
3.7 mA (in 0.9VDD)
10 mA (in 0.9VDD)
0
1
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EM78P372K
8-bit Microcontroller
7.2.15 IOC81 (HDCR2: High Driver Control Register 2)
Bit 7
HD67
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HD66
HD65
HD64
HD63
HD62
HD61
HD60
Bit 7 (HD67): Output High Driver Current Select for P67
Bit 6 (HD66): Output High Driver Current Select for P66
Bit 5 (HD65): Output High Driver Current Select for P65
Bit 4 (HD64): Output High Driver Current Select for P64
Bit 3 (HD63): Output High Driver Current Select for P63
Bit 2 (HD62): Output High Driver Current Select for P62
Bit 1 (HD61): Output High Driver Current Select for P61
Bit 0 (HD60): Output High Driver Current Select for P60
HDxx
VDD = 5V, Driver Current
3.7 mA (in 0.9VDD)
0
1
10 mA (in 0.9VDD)
7.2.16 IOC91 (DeadTCR: Dead Time Control Register)
Bit 7
IPWM2A IPWM1A
R/W-0 R/W-0
Bit 6
Bit 5
PWM2A
R/W-0
Bit 4
PWM1A DEADT2E DEADT1E DEADTP1 DEADTP0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7 (IPWM2A): Active level of inverse PWM2
0: Period-duty-dead time is Logic 1 (default)
1: Period-duty-dead time is Logic 0
Bit 6 (IPWM1A): Active level of inverse PWM1
0: Period-duty-dead time is Logic 1 (default)
1: Period-duty-dead time is Logic 0
Bit 5 (PWM2A): Active level of PWM2
0: Duty-dead time is Logic 1 (default)
1: Duty-dead time is Logic 0
Bit 4 (PWM1A): Active level of PWM1
0: Duty-dead time is Logic 1 (default)
1: Duty-dead time is Logic 0
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8-bit Microcontroller
Bit 3 (DEADT2E): Enable dead-time function for PWM2 and /PWM2 (for dual PWM)
0: Disable (default)
1: Enable
Bit 2 (DEADT1E): Enable dead-time function for PWM1 and /PWM1 (for dual PWM)
0: Disable (default)
1: Enable
Bits 1~0 (DEADTP1~DEADTP0): Dead-time prescaler
DEADTP1
DEADTP0
Prescale
1:1 (default)
1:2
0
0
1
1
0
1
0
1
1:4
1:8
NOTE
The dead time function is only for dual PWM. If used in single PWM function
(not dual PWM), the dead time function is always disabled.
7.2.17 IOCA1 (DeadTR: Dead Time Register)
Bit 7
DEADTR7 DEADTR6 DEADTR5 DEADTR4 DEADTR3 DEADTR2 DEADTR1 DEADTR0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7~0 (DEADTR7~0): The content of the register is dead-time.
Note
The value in the dead-time register must be less than the value in the duty
cycle register in order to prevent unexpected behavior on both of PWM
outputs.
7.2.18 IOCF1 (Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Note: The IOCD0 register is both readable and writable.
Bit 7 (/PH67): Control bit used to enable pull-high of the P67 pin.
0 : Enable internal pull-high
1 : Disable internal pull-high
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
33
EM78P372K
8-bit Microcontroller
Bit 6 (/PH66): Control bit used to enable internal pull-high of the P66 pin.
Bit 5 (/PH65): Control bit used to enable internal pull-high of the P65 pin.
Bit 4 (/PH64): Control bit used to enable internal pull-high of the P64 pin.
Bit 3 (/PH63): Control bit used to enable internal pull-high of the P63 pin.
Bit 2 (/PH62): Control bit used to enable internal pull-high of the P62 pin.
Bit 1 (/PH61): Control bit used to enable internal pull-high of the P61 pin.
Bit 0 (/PH60): Control bit used to enable internal pull-high of the P60 pin.
7.3 TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT respectively.
The PST2 ~ PST0 bits of the CONT register are used to determine the ratio of the TCC
prescaler, and the PSW2 ~ PSW0 bits of the IOCE0 register are used to determine the
prescaler of WDT. The prescaler counter is cleared by the instructions each time such
instructions are written into TCC. The WDT and prescaler will be cleared by the
“WDTC” and “SLEP” instructions. Figure 7-3 depicts the block diagram of TCC/WDT.
TCC (R1) is an 8-bit timer/counter. The TCC clock source can be an internal clock
(Fm/Fs) or external signal input (edge selectable from the TCC pin). If TCC signal
source is from the internal clock (Fm/Fs), TCC will increase by 1 at every Fm clock or
Fs clock (without prescaler), determined by BANK1 RF TIMERSC bit. If TCC signal
source is from an external clock input, TCC will increase by 1 at every falling edge or
rising edge of the TCC pin. The TCC pin input time length (kept in High or Low level)
must be greater than Fm clock or Fs clock, determined by Bank 1 RF CPUS bit.
NOTE
The internal TCC will stop running when in sleep mode. However, during AD
conversion, when TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is
enabled, the TCC will keep on running.
The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode). During
normal operation or in sleep mode, a WDT time-out (if enabled) will cause the device to
reset. The WDT can be enabled or disabled any time during normal mode through
software programming. With no prescaler, the WDT time-out period is approximately
18ms1 or 4.5ms2.
1
VDD=5V, WDT time-out period = 16.5ms ± 30%
VDD=3V, WDT time-out period = 18ms ± 30%
2
VDD=5V, WDT time-out period = 4.2ms ± 30%
VDD=3V, WDT time-out period = 4.5ms ± 30%
34
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
TIMERSC
(BANK1 RF)
0
1
Fs
MUX
Fm
Data Bus
TCC (R1)
0
1
8-Bit Counter
MUX
TCC Pin
8 to 1 MUX
Prescaler
TE (CONT)
TS (CONT)
TCC overflow
interrupt
PST2~0
(CONT)
WDT
8-Bit counter
8 to 1 MUX
Prescaler
WDTE
(IOCE0)
PSW2~0
(IOCE0)
WDT Time out
Figure 7-6 TCC and WDT Block Diagram
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
35
EM78P372K
8-bit Microcontroller
7.4 I/O Ports
The I/O registers (Port 5, Port 6, and Port 7) are bidirectional tri-state I/O ports. Port 5 is
pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain
output set through software. Port 5 features an input status changed interrupt (or
wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O
control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both
readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are
illustrated in Figures 7-7, 7-8, 7-9, and 7-10.
PCRD
P
R
Q
D
CLK
PCWR
_
C
L
Q
P
R
PORT
D
IOD
Q
CLK
PDWR
_
C
L
Q
PDRD
M
U
X
0
1
Note: Pull-high and Open-drain are not shown in the figure.
Figure 7-7 I/O Port and I/O Control Register Circuit for Port 6 and Port 7
PCRD
P
R
Q
D
_
Q
PCWR
PDWR
CLK
C
L
IOD
P
R
Q
PORT
D
_
Q
CLK
C
L
Bit 6 of IOCE0
P
D
Q
R
0
1
M
U
X
_
CLK
C
L
Q
PDRD
INT
Note: Pull-high and Open-drain are not shown in the figure.
Figure 7-8 I/O Port and I/O Control Register Circuit for P60 (/INT)
Product Specification (V1.4) 05.11.2016
36
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
PCRD
P
R
Q
D
CLK
PCWR
_
C
L
Q
P50 ~ P57
PORT
P
R
Q
D
IOD
CLK
_
PDWR
C
L
Q
M
U
X
0
1
PDRD
TI n
P
R
D
Q
CLK
_
C
L
Q
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 7-9 I/O Port and I/O Control Register Circuit for Ports 50~57
IOCF.1
RF.1
TI 0
TI 1
TI 8
Figure 7-10 Port 5 Input Change Interrupt / Wake-up Block Diagram
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
37
EM78P372K
8-bit Microcontroller
7.4.1 Usage of Ports 5, 7 Input Change Wake-up/Interrupt Function
(1) Wake-up
(a) Before Sleep
(2) Wake-up and Interrupt
(a) Before Sleep
1. Disable WDT
1. Disable WDT
2-1. Read I/O Port 5 (MOV R5,R5)
2-2. Read I/O Port 7 (MOV R7,R7)
3. Execute "ENI" or "DISI"
2-1. Read I/O Port 5 (MOV R5,R5)
2-2. Read I/O Port 7 (MOV R7,R7)
3. Execute "ENI" or "DISI"
4. Enable wake-up bit (Set RE
ICWE =1)
4. Enable wake-up bit (Set RE ICWE =1)
5. Execute "SLEP" instruction
(b) After wake-up
5. Enable interrupt (Set IOCF ICIE =1)
6. Execute "SLEP" instruction
(b) After wake-up
Next instruction
1. IF "ENI" Interrupt vector (008H)
2. IF "DISI" Next instruction
(3) Interrupt
(a) Before Port 5,7 pin change
1-1. Read I/O Port 5 (MOV R5,R5)
1-2. Read I/O Port 7 (MOV R7,R7)
2. Execute "ENI" or "DISI"
3. Enable interrupt (Set IOCF ICIE =1)
(b) After Port 5,7 pin changed (interrupt)
1. IF "ENI" Interrupt vector (006H)
2. IF "DISI" Next instruction
7.5 Reset and Wake-up
7.5.1 Reset and Wake-up Operation
A reset is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
The device is kept in reset condition for a period of approximately 18ms3 (except in LXT
mode) after the reset is detected. When in LXT2 mode, the reset time is 500ms. Two
choices (18ms3 or 4.5ms4) are available for WDT-time out period. Once a reset occurs,
the following functions are performed (the initial Address is 000h):
The oscillator continues running, or will be started (if in sleep mode).
The Program Counter (R2) is set to all "0".
3
VDD=5V, Setup time period = 16.5ms ± 30%
VDD=3V, Setup time period = 18ms ± 30%
4
VDD=5V, Setup time period = 4.2ms ± 30%
VDD=3V, Setup time period = 4.5ms ± 30%
38
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
All I/O port pins are configured as input mode (high-impedance state)
The Watchdog Timer and prescaler are cleared
When power is switched on, the upper three bits of R3 is cleared
The IOCB0 register bits are set to all "1"
The IOCC0 register bits are set to all "0"
The IOCD0 register bits are set to all "1"
Bits 7, 5, and 4 of the IOCE0 register are cleared
Bits 5 and 4 of the RE register are cleared
RF and IOCF0 registers are cleared
Executing the “SLEP” instruction will assert the sleep (power down) mode (When
IDLE=“0”.). While entering into sleep mode, the Oscillator, TCC, TMR1 and TMR2 are
stopped. The WDT (if enabled) is cleared but keeps on running.
During AD conversion, when “SLEP” instruction is set; the Oscillator, TMR1 and TMR2
keep on running. The WDT (if enabled) is cleared but keeps on running.
The controller can be awakened by:
Case 1 External reset input on /RESET pin
Case 2 WDT time-out (if enabled)
Case 3 Port 5, P70, P71 input status changes (if ICWE is enabled)
Case 4 Comparator output status changes (if CMPWE is enabled)
Case 5 AD conversion completed (if ADWE is enabled)
Case 6 Low Voltage Detector (if LVDWE is enabled)
The first two cases (1 and 2) will cause the EM78P372K to reset. The T and P flags of
R3 can be used to determine the source of the reset (wake-up). Cases 3, 4, 5 and 6 are
considered the continuation of program execution and the global interrupt ("ENI" or
"DISI" being executed) determines whether or not the controller branches to the
interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will
begin to execute from Address 0x06 (Case 3), 00F (Case 4), 0x0C (Case 5) and 021
(Case 6) after wake-up. If DISI is executed before SLEP, the execution will restart from
the instruction next to SLEP after wake-up.
Only one of Cases 2 to 6 can be enabled before entering into sleep mode. That is:
Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the
EM78P372K can be awakened only with Case 1 or Case 2. Refer to the
section on Interrupt (Section 6.6) for further details.
Case [b] If Port 5, P70, P71 Input Status Change is used to wake up the EM78P372K
and the ICWE bit of the RE register is enabled before SLEP, and WDT must
be disabled. Hence, the EM78P372K can be awakened only with Case 3.
Wake-up time is dependent on the oscillator mode. In RC mode, Wake-up
time is 10s (for stable oscillators). In HXT2 (4 MHz) mode, Wake-up time is
800s (for stable oscillators), and in LXT2 mode, Wake-up time is 2 ~ 3s.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
39
EM78P372K
8-bit Microcontroller
Case [c] If the Comparator output status change is used to wake-up the EM78P372K
and the CMPWE bit of the RE register is enabled before SLEP, WDT must be
disabled by software. Hence, the EM78P372K can be awakened only with
Case 4. Wake-up time is dependent on the oscillator mode. In RC mode,
Wake-up time is 10s (for stable oscillators). In HXT2 (4MHz) mode,
Wake-up time is 800s (for stable oscillators), and in LXT2 mode, Wake-up
time is 2s ~ 3s.
Case [d] If completed AD conversion is used to wake-up the EM78P372K and ADWE
bit of RE register is enabled before SLEP, WDT must be disabled by
software. Hence, the EM78P372K can be awakened only with Case 5. The
wake-up time is 15 TAD (ADC clock period).
Case[e] If Low voltage detector is used to wake-up the EM78P372K and the LVDWE
bit of Bank 0-RE register is enabled before SLEP, WDT must be disabled by
software. Hence, the EM78P372K can be awakened only with Case 6.
Wake-up time is dependent on oscillator mode.
If Port 5, P70, P71 Input Status Change Interrupt is used to wake up the EM78P372K
(as in Case [b] above), the following instructions must be executed before
SLEP:
BC
R3, 6
; Select Segment 0
MOV
IOW
A, @00xx1110b
IOCE0
; Select WDT prescaler and Disable WDT
WDTC
MOV
MOV
; Clear WDT and prescaler
; Read Port 5
; Read Port 7
R5, R5
R7, R7
ENI (or DISI)
; Enable (or disable) global interrupt
; Enable Port 5,7 input change wake-up bit
MOV
MOV
MOV
IOW
SLEP
A, @xxxxxx1xb
RE
A, @1xxxxx1xb
IOCF0
; Enable Port 5,7 input change interrupt
; Sleep
Similarly, if the Comparator Interrupt is used to wake up the EM78P372K (as in Case [c]
above), the following instructions must be executed before SLEP:
BC
R3, 6
; Select Segment 0
MOV
A, @xxx10XXXb
; Select a comparator and P64 functions as
; CO pin
IOW
MOV
IOC80
A, @00x11110b
; Select WDT prescaler and Disable WDT,
; and enable comparator output status
; change interrupt
IOW
IOCE0
WDTC
; Clear WDT and prescaler
ENI (or DISI)
MOV
; Enable (or disable) global interrupt
; Enable comparator output status change
; wake-up bit
A, @xxx0x1xxb
RE
MOV
SLEP
; Sleep
40
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.5.2 Wake-up and Interrupt Modes Operation Summary
The controller can be awakened from sleep mode and idle mode. The wake-up signals are
listed as follows.
Sleep Mode
DISI ENI
Idle Mode
DISI ENI
Green Mode
DISI ENI
Normal Mode
DISI ENI
Wake-up
Signal
Condition
Signal
EXWE = 0,
EXIE = 0
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
EXWE = 0,
EXIE = 1
Next
+
Next
+
Wake-up is invalid
Wake-up is invalid
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
External INT
Wake up
+
Next Instruction
Wake up
+
Next Instruction
EXWE = 1,
EXIE = 0
Wake up
+
Wake up
+
Wake up
+
Wake up
+
EXWE = 1,
EXIE = 1
Next
+
Next
+
Next
Instruction
Interrupt
Vector
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
ICWE = 0,
ICIE = 0,
P7ICIE = 0
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid.
Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
ICWE = 0,
ICIE = 1,
P7ICIE = 1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Port 5, P70,
P71 pin
change
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
ICWE = 1,
ICIE = 0,
P7ICIE = 0
Wake up
+
Next Instruction
Wake up
+
Next Instruction
Wake up
+
Wake up
+
Wake up
+
Wake up
+
ICWE = 1,
ICIE = 1,
P7ICIE = 1
Next
+
Next
+
Next
Instruction
Interrupt
Vector
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Interrupt is invalid.
Interrupt
Vector
Interrupt is invalid.
Interrupt
TCIE = 0
TCIE = 1
Wake-up is invalid.
Wake up
+
Wake up
+
TCC Overflow
Wake-up is invalid
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Interrupt is invalid.
Interrupt
Vector
Interrupt is invalid.
Interrupt
ADWE = 0,
ADIE = 0
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
ADWE = 0,
ADIE = 1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
AD
Conversion
complete
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Wake up
+
Next Instruction
Wake up
+
Next Instruction
ADWE = 1,
ADIE = 0
Wake up
+
Wake up
+
Wake up
+
Wake up
+
ADWE = 1,
ADIE = 1
Next
+
Next
+
Next
Instruction
Interrupt
Vector
Next
Instruction
Interrupt Instruction Interrupt Instruction Interrupt
Vector Vector Vector
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
41
EM78P372K
8-bit Microcontroller
Sleep Mode
DISI ENI
Idle Mode
DISI ENI
Green Mode
DISI ENI
Normal Mode
DISI ENI
Wake-up
Signal
Condition
Signal
CMPWE = 0,
CMPIE = 0
Wake-up is invalid
Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
CMPWE = 0,
CMPIE = 1
Next
+
Next
+
Wake-up is invalid
Wake-up is invalid
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Comparator
Interrupt
Wake up
+
Next Instruction
Wake up
+
Next Instruction
CMPWE = 1,
CMPIE = 0
Wake up
+
Wake up
+
Wake up
+
Wake up
+
CMPWE = 1,
CMPIE = 1
Next
+
Next
+
Next
Instruction
Interrupt
Vector
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
PWM1IE = 0
PWM1IE = 1
PWM2IE = 0
PWM2IE = 1
DT1IE = 0
Wake-up is invalid
PWM1 period
Wake up
+
Wake up
+
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
match interrupt
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Wake-up is invalid
PWM2 period
match interrupt
Wake up
+
Wake up
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Wake-up is invalid
PWM1 duty
match interrupt
Wake up
+
Wake up
+
Next
+
Next
+
DT1IE = 1
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
DT2IE = 0
wake-up is invalid
PWM2 duty
match interrupt
Wake up
+
Wake up
+
Next
+
Next
+
DT2IE = 1
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
LVDWE = 0,
LVDIE = 0
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
Wake-up is invalid
LVDWE = 0,
LVDIE = 1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Low Voltage
Detector
Wake up
+
Next Instruction
Wake up
+
Next Instruction
LVWE = 1,
LVDIE = 0
Wake up
+
Wake up
+
Wake up
+
Wake up
+
LVDWE = 1,
LVDIE = 1
Next
+
Next
+
Next
Instruction
Interrupt
Vector
Next
Instruction
Interrupt Instruction Interrupt Instruction Interrupt
Vector Vector Vector
WDT Timeout
WDTE = 1
Wake up + Reset
Wake up + Reset
Wake up + Reset
Wake up + Reset
Reset
Reset
Reset
Reset
Low voltage
reset
42
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.5.3 Register Initial Values after Reset
The following summarizes the initialized values for registers.
Address Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C57
C56
C55
C54
C53
C52
C51
C50
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
IOC50
IOC60
IOC70
IOC80
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
C67
1
C66
1
C65
1
C64
1
C63
1
C62
1
C61
1
C60
1
Power-on
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
C71
1
C70
1
Power-on
/RESET and WDT
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
CMPOUT COS1
COS0
0
0
0
0
0
0
Power-on
0
0
0
0
0
0
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
TMR1[7] TMR1[6] TMR1[5] TMR1[4] TMR1[3] TMR1[2] TMR1[1] TMR1[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
IOC90
/RESET and WDT
(TMR1)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
TMR2[7] TMR2[6] TMR2[5] TMR2[4] TMR2[3] TMR2[2] TMR2[1] TMR2[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
IOCA0
/RESET and WDT
(TMR2)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PD57
/PD56
/PD55
/PD54
/PD53
/PD52
/PD51
/PD50
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOCB0
/RESET and WDT
(PDCR)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
43
EM78P372K
8-bit Microcontroller
Address Name
Reset Type
Bit Name
Bit 7
OD67
0
Bit 6
OD66
0
Bit 5
OD65
0
Bit 4
OD64
0
Bit 3
OD63
0
Bit 2
OD62
0
Bit 1
OD61
0
Bit 0
OD60
0
Power-on
IOCC0
(ODCR)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PH57
/PH56
/PH55
/PH54
/PH53
/PH52
/PH51
/PH50
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOCD0
(PHCR1)
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
WDTE
EIS
0
ADIE
CMPIE PSWE
PSW2
PSW1
PSW0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCE0
IOCF0
/RESET and WDT
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P7ICIE DT2IE
DT1IE PWM2IE PWM1IE EXIE
ICIE
0
TCIE
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
HS57
HS56
0
0
HS54
HS53
HS52
HS51
0
0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
IOC51
(HSCR1)
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
HS67
HS66
HS65
HS64
HS63
HS62
HS61
HS60
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOC61
(HSCR2)
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
HD57
HD56
0
0
HD54
HD53
HD52
HD51
0
0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
IOC71
(HDCR1)
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
HD67
HD66
HD65
HD64
HD63
HD62
HD61
HD60
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOC81
(HDCR2)
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
IPWM2A IPWM1A PWM2A PWM1A DEADT2E DEADT1E DEADTP1 DEADTP0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOC91
(DeadTCR)
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
44
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
DEADTR7 DEADTR6 DEADTR5 DEADTR4 DEADTR3 DEADTR2 DEADTR1 DEADTR0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCA1
(DeadTR)
N/A
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/PH67
/PH66
/PH65
/PH64
/PH63
/PH62
/PH61
/PH60
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOCF1
(PHCR2)
N/A
N/A
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
INTE
INT
0
TS
1
TE
1
PSTE
PST2
PST1
PST0
Power-on
1
1
0
0
0
0
0
0
0
0
CONT
/RESET and WDT
0
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
Power-on
000
001
R0 (IAR)
R1 (TCC)
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
–
0
0
–
0
0
–
0
0
–
0
0
–
0
0
–
0
0
–
0
0
–
0
0
Power-on
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
45
EM78P372K
8-bit Microcontroller
Address Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
–
–
–
–
–
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
002
003
004
005
006
007
008
009
00A
R2 (PC)
R3 (SR)
R4 (RSR)
R5
/RESET and WDT
Wake-up from Pin
Change
Jump to Address 0x06 or continue to execute next instruction
Bit Name
RST
IOCS
–
0
0
T
1
T
P
1
t
Z
U
P
DC
U
C
U
P
Power-on
0
0
0
0
/RESET and WDT
P
Wake-up from Pin
Change
1
P
P
T
t
P
P
P
Bit Name
SBANK
BS0
0
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
Power-on
0
0
/RESET and WDT
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P57
1
P56
1
P55
1
P54
1
P53
1
P52
1
P51
1
P50
1
Power-on
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P67
1
P66
1
P65
1
P64
1
P63
1
P62
1
P61
1
P60
1
Power-on
R6
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
P71
1
P70
1
Power-on
R7
/RESET and WDT
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R8
/RESET and WDT
(AISR)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
VREFS CKR1
CKR0 ADRUN ADPD
ADIS2
ADIS1 ADIS0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R9
/RESET and WDT
(ADCON)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
CALI
SIGN
VOF[2] VOF[1] VOF[0] VREF1 VREF0 ADICS
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RA
/RESET and WDT
(ADOC)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
46
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
Address
Name
Reset Type
Bit Name
Bit 7
AD11
U
Bit 6
AD10
U
Bit 5
AD9
U
Bit 4
AD8
U
Bit 3
AD7
U
Bit 2
AD6
U
Bit 1
AD5
U
Bit 0
AD4
U
Power-on
RB
00B
/RESET and WDT
U
U
U
U
U
U
U
U
(ADDATA)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
Bit Name
AD11
U
AD10
U
AD9
U
AD8
U
Power-on
RC
00C
00D
00E
/RESET and WDT
U
U
U
U
(ADDATA1H)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
AD7
U
AD6
U
AD5
U
AD4
U
AD3
U
AD2
U
AD1
U
AD0
U
Power-on
RD
/RESET and WDT
U
U
U
U
U
U
U
U
(ADDATA1L)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
/LVD
LVDIF
ADIF
CMPIF ADWE CMPWE ICWE LVDWE
Power-on
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RE
/RESET and WDT
(ISR2)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
P7ICIF
DT2IF
DT1IF PWM2IF PWM1IF EXIF
ICIF
0
TCIF
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RF
00F
005
006
007
/RESET and WDT
0
(ISR1)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
MLB
TRS
0
0
0
0
RBit11 RBit10
RBit9
RBit8
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
BANK1 R5
BANK1 R6
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
RBit7
RBit6
RBit5
RBit4
RBit3
RBit2
RBit1
RBit0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
IPWM2E IPWM1E
0
0
0
0
0
0
PWMCAS PWM2E PWM1E
Power-on
0
0
0
0
0
0
0
0
0
0
BANK1 R7
(PWMCON)
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
47
EM78P372K
8-bit Microcontroller
Address Name
Reset Type
Bit Name
Bit 7
T2EN
0
Bit 6
T1EN
0
Bit 5
T2P2
0
Bit 4
T2P1
0
Bit 3
T2P0
0
Bit 2
T1P2
0
Bit 1
T1P1
0
Bit 0
T1P0
0
Power-on
BANK1 R8
(TMRCON)
008
009
00A
00B
00C
00E
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BANK1 R9
(PRD1)
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BANK 1
RA
/RESET and WDT
(PRD2)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
DT1[7] DT1[6]
DT1[5] DT1[4] DT1[3] DT1[2] DT1[1] DT1[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BANK 1
RB
/RESET and WDT
(DT1)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
DT2[7] DT2[6]
DT2[5] DT2[4] DT2[3] DT2[2] DT2[1] DT2[0]
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BANK 1
RC
/RESET and WDT
(DT2)
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
LVDIE LVDEN
LVD1
LVD0
0
0
0
0
0
0
EXWE
Power-on
0
0
0
0
1
1
1
1
0
0
BANK 1
RE
/RESET and WDT
Wake-up from Pin
Change
P
-
P
P
P
IDLE
0
P
SHS1
1
P
SHS0
1
P
P
Bit Name
Power-on
TIMERSC CPUS
RCM1
RCM0
WORD1
<6~5>
0
1
1
P
1
1
P
BANK 1
RF
00F
WORD1
<6~5>
/RESET and WDT
0
0
1
1
Wake-up from Pin
Change
P
P
P
P
P
P
Bit Name
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
–
U
P
Power-on
0x10~0x3F R10~R3F
/RESET and WDT
Wake-up from Pin
Change
P
P
P
P
P
P
P
P
Legend: “” = not used
“u” = unknown or don’t care
“P” = previous value before reset
“t” = check “Reset Type” Table in Section 6.5.2
48
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.5.4 Controller Reset Block Diagram
VDD
D
Q
CLK
Oscillator
CLK
CLR
Power-on Reset
Voltage
Detector
ENWDTB
WDT Timeout
Reset
Setup time
WDT
/RESET
Figure 7-11 Controller Reset Block Diagram
7.5.5 The T and P Status under Status Register
A reset condition is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
The values of T and P as listed in the table below, are used to check how the processor
wakes up.
Reset Type
RST
0
T
1
P
1
Power-on
/RESET during Operating mode
/RESET wake-up during Sleep mode
LVR during Operating mode
0
*P
1
*P
0
0
0
*P
1
*P
0
LVR wake-up during Sleep mode
WDT during Operating mode
0
0
0
1
WDT wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
0
0
1
1
0
*P: Previous status before reset
The following shows the events that may affect the status of T and P.
Event
RST
0
T
1
1
0
1
1
P
1
Power-on
WDTC instruction
WDT time-out
SLEP instruction
*P
0
1
*P
0
*P
1
Wake-up on pin changed during Sleep mode
0
*P: Previous value before reset
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
49
EM78P372K
8-bit Microcontroller
7.6 Interrupt
The EM78P372K has seven interrupts enumerated below:
1. PWM1~2 period match and duty cycle match interrupt
2. Port 5, P70, P71 Input Status Change Interrupt
3. External interrupt [(P60, /INT) pin]
4. Analog to Digital conversion completed
5. PWM1, 2 underflow interrupt
6. When the comparators status changes
7. Low Voltage Detector Interrupt
Before the Port 5, P70, P71 Input Status Change Interrupt is enabled, reading Port 5,
P70, P71 (e.g. "MOV R5, R5" and "MOV R7, R7") is necessary. Each Port 5, P70, P71
pin will have this feature if its status changes. The Port 5, P70, P71 Input Status Change
Interrupt will wake up the EM78P372K from sleep mode if it is enabled prior to going into
sleep mode by executing SLEP instruction. When wake up occurs, the controller will
continue to execute program in-line if the global interrupt is disabled. If enabled, the
global interrupt will branch out to the Interrupt Vector 006H.
External interrupt equipped with digital noise rejection circuit (input pulse less than
system clock time) is eliminated as noise. However, under Low Crystal oscillator (LXT)
mode the noise rejection circuit will be disabled. Edge selection is possible with INTE of
CONT. When an interrupt is generated by the External interrupt (when enabled), the
next instruction will be fetched from Address 003H. Refer to Word 1 Bits 9 and 8,
Section 6.14.2, Code Option Register (Word 1) for digital noise rejection definition.
RF and RE are the interrupt status register that records the interrupt requests in the
relative flags/bits. IOCF0 and IOCE0 are Interrupt mask registers. The global interrupt
is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine to avoid recursive interrupts.
When interrupt mask bits is “Enable”, the flag in the Interrupt Status Register (RF) is set
regardless of the ENI execution. Note that the result of RF will be the Logic AND of RF
and IOCF0 (refer to the figure below). The RETI instruction ends the interrupt routine
and enables the global interrupt (the ENI execution).
When an interrupt is generated by the Timer clock/counter (when enabled), the next
instruction will be fetched from Address 009, 012, 015, 018 and 01BH (PWM1~2 period
match and duty match respectively).
When an interrupt generated by AD conversion is completed (when enabled), the next
instruction will be fetched from Address 00CH.
When an interrupt is generated by the Comparators (when enabled), the next
instruction will be fetched from Address 00FH (Comparator interrupt).
50
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
When an interrupt is generated by the Low Voltage Detect (when enabled), the next
instruction will be fetched from Address 021H (Low Voltage Detector interrupt).
Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4
registers are saved first by the hardware. If another interrupt occurs, the ACC, R3, and
R4 will be replaced by the new interrupt. After an interrupt service routine is completed,
the ACC, R3, and R4 registers are restored.
VCC
P
D
Q
IRQn
R
/IRQn
CLK
INT
_
Q
IRQm
C
L
RFRD
RF
ENI/DISI
P
IOD
Q
D
R
CLK
_
Q
IOCFWR
C
L
IOCF
/RESET
IOCFRD
RFWR
Interrupt
occurs
Interrupt sources
ENI/DISI
ACC
Stack ACC
R3 (7~5, 2~0)
R4 (6~0)
Stack R3
Stack R4
RETI
Figure 7-12 Interrupt Back-up Diagram
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
51
EM78P372K
8-bit Microcontroller
In EM78P372K, each individual interrupt source has its own interrupt vector as
depicted in the table below.
Interrupt Vector
Interrupt Status
Priority *
003H
006H
009H
00CH
00FH
012H
015H
018H
01BH
021H
External interrupt
2
3
Port 5, P70, P71 pin change
TCC overflow interrupt
4
AD conversion complete interrupt
Comparator interrupt
5
6
PWM1 period match interrupt
PWM2 period match interrupt
PWM1 duty match interrupt
PWM2 duty match interrupt
Low Voltage Detector interrupt
7
8
9
10
1
Note: *Priority: 1 = highest ; 11 = lowest priority
7.7 Analog-to-Digital Converter (ADC)
The analog-to-digital circuitry consists of an 8-bit analog multiplexer; three control
registers (AISR/R8, ADCON/R9, and ADOC/RA), three data registers (ADDATA1/RB,
ADDATA1H/RC, and ADDATA1L/RD) and an ADC with 12-bit resolution as shown in
the functional block diagram below. The analog reference voltage (Vref) and the analog
ground are connected via separate input pins. Connecting to an external VREF is more
accurate than connecting to an internal VDD.
The ADC module utilizes successive approximation to convert the unknown analog
signal into a digital value. The result is fed to the ADDATA, ADDATA1H, and
ADDATA1L. Input channels are selected by the analog input multiplexer via the
ADCON register Bits ADIS1 and ADIS0.
ADC7
Vref
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
Power-Down
Start to Convert
ADC
( successive approximation )
Fsco
4-1
MUX
Internal RC
7
~ 0
2
1
0
3
4
3
11 10
9
8
7
6
5
4
3
2
1
0
6
5
ADCON
ADCON
ADCON
DATA BUS
RF
AISR
ADDATA1H
ADDATA1L
Figure 7-13 Analog-to-Digital Conversion Functional Block Diagram
52
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)
7.7.1.1 R8 (AISR: ADC Input Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
The AISR register individually defines the P5, P6 and P7 pins as analog inputs or as
digital I/O.
Bit 7 (ADE7): AD converter enable bit of P57 pin
0 : Disable ADC7, P57 functions as I/O pin
1 : Enable ADC7 to function as analog input pin
Bit 6 (ADE6): AD converter enable bit of P55 pin
0 : Disable ADC6, P55 functions as I/O pin
1 : Enable ADC6 to function as analog input pin
Bit 5 (ADE5): AD converter enable bit of P70 pin
0 : Disable ADC5, P70 functions as I/O pin
1 : Enable ADC5 to function as analog input pin
Bit 4 (ADE4): AD converter enable bit of P67 pin
0 : Disable ADC4, P67 functions as I/O pin
1 : Enable ADC4 to function as analog input pin
Bit 3 (ADE3): AD converter enable bit of P53 pin
0 : Disable ADC3, P53 functions as I/O pin
1 : Enable ADC3 to function as analog input pin
Bit 2 (ADE2): AD converter enable bit of P52 pin
0 : Disable ADC2, P52 functions as I/O pin
1 : Enable ADC2 to function as analog input pin
Bit 1 (ADE1): AD converter enable bit of P51 pin
0 : Disable ADC1, P51 acts as I/O pin
1 : Enable ADC1 acts as analog input pin
Bit 0 (ADE0): AD converter enable bit of P50 pin
0 : Disable ADC0, P50 functions as I/O pin
1 : Enable ADC0 to function as analog input pin
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7.7.1.2 R9 (ADCON: ADC Control Register)
Bit 7
VREFS
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CKR1
CKR0
ADRUN
ADPD
ADIS2
ADIS1
ADIS0
The ADCON register controls the operation of the AD conversion and determines
which pin should be currently active.
Bit 7 (VREFS):The input source of the ADC Vref
0 : The Vref of the ADC is connected to internal reference voltage
(default value), and the
P54/TCC/VREF pin carries out the function of P54.
1 : The Vref of the ADC is connected to P54/TCC/VREF
NOTE
The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If
P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 (TS) must be “0”.
The P54/TCC/VREF pin priority is as follows:
P54/TCC/VREF Pin Priority
High
Medium
TCC
Low
P54
VREF
Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The prescaler of ADC oscillator clock rate
Max. Operation Freq.
( if TAD=4us, match
372N )
Max. Operation Freq.
( if TAD=1us, match
372N )
CKR1 :
CKR0
Operation
Mode
CPUS
1
1
1
1
0
00 (default)
FOSC/16
FOSC/4
FOSC/64
FOSC/1
–
4 MHz
1 MHz
16 MHz
4 MHz
01
10
11
16 MHz
–
–
1 MHz
16K/128kHz
16K/128kHz
Bit 4 (ADRUN): ADC starts to RUN
0: Reset upon completion of the conversion. This bit cannot be reset
though software.
1: AD conversion is started. This bit can be set by software.
Bit 3 (ADPD): ADC Power-down mode
0: Switch off the resistor reference to conserve power even while the
CPU is operating
1: ADC is operating
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8-bit Microcontroller
Bits 2 ~ 0 (ADIS2 ~ ADIS0): Analog Input Select
ADICS
ADIS2
ADIS1
ADIS0
Analog Input Select
ADIN0/P50
ADIN1/P51
ADIN2/P52
ADIN3/P53
ADIN4/P67
ADIN5/P70
ADIN6/P55
ADIN7/P57
OPOUT
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
Internal ADC Channel
Select: 1/4 VDD
1
1
1
1
0
0
0
1
Internal ADC Channel
Select: 1/2 VDD
1
1
1
1
1
1
0
1
Reserved
Reserved
7.7.1.3 RA (ADOC: AD Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
VREF1
VREF0
ADICS
Bit 7 (CALI): Calibration enable bit for ADC offset
0 = Disable the Calibration
1 = Enable the Calibration
Bit 6 (SIGN): Polarity bit of offset voltage
0 = Negative voltage
1 = Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits
VOF[2]
VOF[1]
VOF[0]
EM78P372K
0 LSB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 LSB
4 LSB
6 LSB
8 LSB
10 LSB
12 LSB
14 LSB
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Bits 2 ~ 1 (VREF1~ VREF0): ADC internal reference voltage source.
VREFSEL
in Option Word 3 bit
11
ADC Int. Ref.
Volt.
VREF1
VREF0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VDD
4.0V ± 1%
3.0V ± 1%
2.5V ± 1%
VDD
4.0V ± 1%
3.0V ± 1%
2.0V ± 1%
1 : Positive voltage
Bit 0 (ADICS): ADC internal channel select. (Select ADC internal 1/4 VDD or OP
output pin connects to ADC input)
0 : Disable
1 : Enable
7.7.1.4 Bank 1 RF (IRC switch Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
TIMERSC
CPUS
IDLE
SHS1
SHS0
RCM1
RCM0
Bits 3 ~ 2 (SHS1~0): Select AD sample and Hold period
SHS1
SHS0
AD sample and Hold period (TAD)
0
0
1
1
0
1
0
1
2
4
8
12 (default)
7.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC,
ADDATA1L/RD)
When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H
and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.
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7.7.3 ADC Sampling Time
The accuracy, linearity, and speed of the successive approximation of the AD converter
are dependent on the properties of the ADC and the comparator. The source
impedance and the internal sampling impedance directly affect the time required to
charge the sample holding capacitor. The application program controls the length of the
sample time to meet the specified accuracy. Generally speaking, the program should
wait for 2s for each K of the analog source impedance and at least 2s for the
low-impedance source. The maximum recommended impedance for analog source is
10K at Vdd=5V. After the analog input channel is selected, this acquisition time must
be done before the conversion is started.
7.7.4 AD Conversion Time
CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This
allows the MCU to run at the maximum frequency without sacrificing the AD conversion
accuracy. For the EM78P372K, the conversion time per bit is about 1s. The table
below shows the relationship between Tct and the maximum operating frequencies.
TAD = 1µs
Max. Conversion
Rate/Bit
Operation Max. Operation
CPUS CKR1 : CKR0
Max. Conversion Rate
Mode
FOSC/16
FOSC/4
FOSC/64
FOSC/1
Frequency
16 MHz
4 MHz
1
1
1
1
0
00 (default)
1 MHz (1µs)
1 MHz (1µs)
-
16*1µs=16µs (62.5kHz)
16*1µs=16µs (62.5kHz)
-
01
10
11
-
1 MHz
1 MHz (1µs)
16*1µs=16µs (62.5kHz)
16K/128kHz
TAD = 4µs
Max. Conversion
Rate/Bit
Operation Max. Operation
CPUS CKR1 : CKR0
Max. Conversion Rate
Mode
FOSC/16
FOSC/4
FOSC/64
FOSC/1
Frequency
1
1
1
1
0
00 (default)
4 MHz
250kHz (4µs) 16*4µs=64µs (15.625kHz)
250kHz (4µs) 16*4µs=64µs (15.625kHz)
250kHz (4µs) 16*4µs=64µs (15.625kHz)
01
10
11
1 MHz
16 MHz
-
-
-
16K/128kHz
NOTE
■ Pin not used as an analog input pin can be used as regular input or output pin.
■ During conversion, do not perform output instruction to maintain precision for all of
the pins.
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7.7.5 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD
conversion remains operational during sleep mode. As the SLEP instruction is
executed, all the MCU operations will stop except for the Oscillator, TCC, and AD
conversion.
The AD Conversion is considered completed as determined by:
1. The ADRUN bit of the R9 register is cleared to “0”.
2. The ADIF bit of the RE register is set to “1”.
3. The ADWE bit of the RE register is set to “1”. Wakes up from ADC conversion
(where it remains in operation during sleep mode).
4. Wake up and execution of the next instruction if the ADIE bit of the IOCE0 is
enabled and the “DISI” instruction is executed.
5. Wake up and enters into Interrupt vector (Address 0x00C) if the ADIE bit of the
IOCE0 is enabled and the “ENI” instruction is executed.
6. Enters into an Interrupt vector (Address 0x00C) if the ADIE bit of the IOCE0 is
enabled and the “ENI” instruction is executed.
The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the
conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise, the
AD conversion will be shut off, no matter what the status of the ADPD bit is.
7.7.6 Programming Process/Considerations
7.7.6.1 Programming Process
Follow these steps to obtain data from the ADC:
1. Write to the eight bits (ADE7: ADE0) on the R8 (AISR) register to define the
characteristics of R5 (digital I/O, analog channels, or voltage reference pin)
2. Write to the R9/ADCON register to configure the AD module:
a) Select the ADC input channel ( ADIS2 : ADIS0 )
b) Define the AD conversion clock rate ( CKR1 : CKR0 )
c) Select the VREFS input source of the ADC
d) Set the ADPD bit to 1 to begin sampling
3. Set the ADWE bit, if the wake-up function is employed
4. Set the ADIE bit, if the interrupt function is employed
5. Write “ENI” instruction, if the interrupt function is employed
6. Set the ADRUN bit to “1”
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7. Write “SLEP” instruction or Polling.
8. Wait for wake-up or for the ADRUN bit to be cleared to “0” , interrupt flag (ADIF) is
set “1” or ADC interrupt occurs.
9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If the
ADC input channel changes at this time, the ADDATA, ADDATA1H, and
ADDATA1L values can be cleared to ‘0’.
10. Clear the interrupt flag bit (ADIF).
11. For next conversion, go to Step 1 or Step 2 as required. At least two Tct is required
before the next acquisition starts.
NOTE
In order to obtain accurate values, it is necessary to avoid any data transition on I/O
pins during AD conversion
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7.7.6.2 Sample Demo Programs
R_0 == 0
; Indirect addressing register
PSW == 3
; Status register
PORT5 == 5
PORT6 == 6
RE== 0XE
; Interrupt status register
B. Define a Control Register
IOC50 == 0X5
IOC60 == 0X6
IOCE0== 0XE
C_INT== 0XF
; Control Register of Port 5
; Control Register of Port 6
; Interrupt Mask Register 2
; Interrupt Mask Register
C. ADC Control Register
ADDATA == 0xB
AISR == 0x08
ADCON == 0x9
; The contents are the results of ADC
; ADC input select register
;
7
6
5
4
3
2
1
0
;VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0
D. Define Bits in ADCON
ADRUN == 0x4
ADPD == 0x3
; ADC is executed as the bit is set
; Power Mode of ADC
E. Program Starts
ORG 0
; Initial address
JMP INITIAL
;
ORG 0x0C
JMP CLRRE
;
; Interrupt vector
;(User program section)
;
CLRRE:
MOV A,RE
AND A, @0BXX0XXXXX ; To clear the ADIF bit, “X” by application
MOV RE,A
BS ADCON, ADRUN
; To start to execute the next AD conversion
; if necessary
RETI
INITIAL:
MOV A,@0B00000001
MOV AISR,A
; To define P50 as an analog input
MOV A,@0B00001000
; To select P50 as an analog input channel, and
AD power on
MOV ADCON,A
; To define P50 as an input pin and set clock
rate at fosc/16
En_ADC:
MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others
; are dependent on applications
IOW PORT5
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MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, “X”
; by application
MOV RE,A
MOV A, @0BXX1XXXXX ; Enable the ADIE interrupt function of ADC,
; “X” by application
IOW IOCE0
ENI
; Enable the interrupt function
; Start to run the ADC
BS ADCON, ADRUN
; If the interrupt function is employed, the following three lines
may be ignored
; If Sleep:
SLEP
;
; (User program section)
;
or
; If Polling:
POLLING:
JBC ADCON, ADRUN
JMP POLLING
; To check the ADRUN bit continuously;
; ADRUN bit will be reset as the AD conversion
; is completed
;
; (User program section)
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7.8 Dual Sets of PWM (Pulse Width Modulation)
7.8.1 Overview
In PWM mode, PWM1 and PWM2 pins produce to 8-bit resolution PWM output (see.
the functional block diagram below). A PWM output consists of a time period and a duty
cycle, and it keeps the output high. The baud rate of PWM is the inverse of the time
period. Figure 6-13 ~ Figure 6-16 (PWM Output Timing) depicts the relationships
between a time period and a duty cycle.
Data
Bus
DeadTR
DTL
Duty
TXP2 TXP1 TXP0
Writing PRDL
DeadTP1 DeadTP0
Deadtime
Fosc
Fosc
1:1
1:2
1:4
1:8
1:1
1:2
MUX
1:4
TMRX
prescaler
1:8
MUX
1:16
1:64
1:128
1:256
deadtime
prescaler
Duty+Deadtime
To
PWMXDIF
PWMXE
Comparator
Comparator
TMRX
prescaler
TXEN
PWMXA
MUX
IPWMXA
MUX
IPWMXE
1
0
1
0
PWMX
/PWMX
R
S
Q
Q
Q
Q
S
TMRXL
R
Period match
Reset
Comparator
deadtime
Comparator
Period
To
PWMXPIF
Writing PRDL
PRDL
Data
Bus
Figure 7-14 PWM System Block Diagram
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8-bit Microcontroller
PWM and /PWM (inverted PWM) can be used individually or used as dual PWM. When
used individually, the definitions of active level between PWM and /PWM are somewhat
different.
For example, set period and duty cycle (period > duty), PWMXE=1/0 and
IPWMXE=0/1, PWMXA = 1/0, /PWMXA=1/0, and finally set TXEN = 1. The following
figures show PWM output timing according to different PWMXA and /PWMXA settings.
PWMX
PWMXE=1 &
IPWMXE=0
/PWMX
PWMXE=0 &
IPWMXE=1
Duty
Period-duty
Period
Figure 7-15 PWM Output Timing (PWMXA=0 and /PWMXA=0)
PWMX
PWMXE=1 &
IPWMXE=0
/PWMX
PWMXE=0 &
IPWMXE=1
Duty
Period-duty
Period
Figure 7-16 PWM Output Timing (PWMXA=0 and /PWMXA=1)
PWMX
PWMXE=1 &
IPWMXE=0
/PWMX
PWMXE=0 &
IPWMXE=1
Duty
Period-duty
Period
Figure 7-17 PWM Output Timing (PWMXA=1 and /PWMXA=0)
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EM78P372K
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PWMX
PWMXE=1 &
IPWMXE=0
/PWMX
PWMXE=0 &
IPWMXE=1
Duty
Period-duty
Period
Figure 7-18 PWM Output Timing (PWMXA=1 and /PWMXA=1)
7.8.1.1 Dual PWM function
It consists of a complementary PWM (i.e. PWMX and /PWMX), one outputs PWM
signal and the other outputs inverted PWM signal, It can output any pulse width signal
you want by programming relative control registers.
The dead time mode is supported. It means that the complementary PWM signals can
be controlled to get a time interval that the complementary PWM signals won’t be
intersected.
The following Figures 6-17 ~ 6-18 show the dual PWM output waveform.
Disable dead time control (DEADTXE = 0). Set period and duty cycle (period > duty).
Set PWMXE & IPWMXE =1, PWMXA = 0/1, IPWMXA = 0/1, and finally set TXEN = 1.
duty
duty
Period-duty
PWMX
PWMXA=0
IPWMXA=0
/PWMX
PWMX
Period-duty
PWMXA=1
IPWMXA=1
/PWMX
Figure 7-19 Dual PWMX Output Waveform (DEADTXE = 0)
Set dead time > 0 (set dead time prescaler if required). Enable dead time control
( DEADTXE = 1). Set period and duty cycle (period > duty). Set PWMXE and IPWMXE
=1, PWMXA = 0, IPWMXA = 0, and finally set TXEN = 1. For loading new duty, period,
and dead time value at run time, follow the subsection “PWM Programming Process /
Steps” to see the descriptions.
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PWMX
/PWMX
Period-duty
Period-duty
duty
duty
Dead time
Dead time
Dead time
Any time
new duty, period, deadtime
Load new duty, period, deadtime (load PRDL last)
Cycle N
Cycle N+1
Figure 7-20 Dual PWMX output waveform (DEADTXE = 1, Dead Time > 0)
The following figures show PWM output timing according to different PWMXA and
/PWMXA settings.
PWMX
Period-duty
duty
/PWMX
Figure 7-21 Dual PWMX output waveform (PWMXA = 0, IPWMXA=0, Dead Time = 0)
PWMX
Period-duty
duty
Dead time
/PWMX
Dead time
Figure 7-22 Dual PWMX output waveform (PWMXA = 0, IPWMXA=0, Dead Time > 0)
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EM78P372K
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PWMX
/PWMX
duty
Period-duty
Dead time
Dead time
Figure 7-23 Dual PWMX output waveform (PWMXA = 1, IPWMXA=0, Dead Time > 0)
duty
Dead time
PWMX
/PWMX
Period-duty
Dead time
Figure 7-24 Dual PWMX output waveform (PWMXA = 0, IPWMXA=1, Dead Time > 0)
Period-duty
duty
PWMX
/PWMX
Dead time
Dead time
Figure 7-25 Dual PWMX output waveform (PWMXA = 1, IPWMXA=1, Dead Time > 0)
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Note
The value in the dead-time register must be less than the value in the duty
cycle register in order to prevent unexpected behavior on both of PWM
outputs.
7.8.2 Increment Timer Counter (TMRX: TMR1 or TMR2)
TMRX are 8-bit clock counters with programmable prescalers. They are designed for
the PWM module as baud rate clock generators. If employed, they can be turned off for
power saving purposes by setting the T1EN bit [BANK1-R8<6>] or T2EN bit
[BANK1-R8<7>] to “0”.
TMR1 and TMR2 are internal designs and can be read only
7.8.3 PWM Time Period (TMRX: TMR1 or TMR2)
PPWM Time Period (PRDX: PRD1 or PRD2) The PWM time period is defined by
writing to the PRDX register. When TMRX is equal to PRDX, the following events
occur on the next increment cycle:
1) TMR is cleared
2) The PWMX pin is set to “1”
3) The PWM duty cycle is latched from DT1/DT2 to DL1/DL2
NOTE
The PWM output will not be set, if the duty cycle is “0”.
4) The PWMXIF pin is set to “1”
The following formula describes how to calculate the PWM time period:
1
Period
PRDX 1
TMRX prescale value
FOSC
Example:
PRDX=49; Fosc=4 MHz; TMRX (0, 0, 0) = 1:1,
1
Period
49 1
1 12.5
µS
then
4M
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7.8.4 PWM Duty Cycle (DTX: DT1 or DT2; DLX: DL1 or DL2)
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX
to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared.
DTX can be loaded anytime. However, it cannot be latched into DLX until the current
value of DLX is equal to TMRX.
The following formula describes how to calculate the PWM duty cycle:
1
Duty Cycle
DTX
TMRX prescale value
FOSC
Example:
DTX=10; Fosc=4 MHz; TMRX (0, 0, 0) = 1:1,
1
then
µS
Duty Cycle 10
1 2.5
4M
7.8.5 Comparator X
Changing the output status while a match occurs will simultaneously set the PWMXIF
(TMRXIF) flag.
7.8.6 PWM Programming Process/Steps
Load PRDX with the PWM time period.
1. Load DTX with the PWM Duty Cycle.
2. Enable interrupt function by writing IOCF0, if required.
3. Set PWMX pin to be output by writing a desired value to Bank 1-R7.
4. Load a desired value to BANK1-R8 with TMRX prescaler value and enable both
PWMx and TMRX
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7.9 Timer
7.9.1 Overview
Timer 1 (TMR1) and Timer 2 (TMR2) (TMRX) are 8-bit clock counters with
programmable prescalers. They are designed for the PWM module as baud rate clock
generators. TMRX can be read only. The Timer 1 and Timer 2 will stop running when
sleep mode occurs with AD conversion not running. However, if AD conversion is
running when sleep mode occurs, Timer 1 and Timer 2 will keep on running.
7.9.2 Function Description
1:1
1:2
Fosc
1:4
To TMR1IF(PWM1IF)
1:8
MUX
1:16
1:64
reset
1:128
1:256
Period
Match
TMR1
Comparator
T1P2 T1P1 T1P0 T1EN
PRD1
Data Bus
Data Bus
PRD2
T2P2 T2P1 T2P0 T2EN
Comparator
reset
Period
Match
TMR2
1:1
1:2
Fosc
1:4
1:8
MUX
1:16
1:64
To TMR2IF(PWM2IF)
1:128
1:256
Figure 7-26 Timer Block Diagram
Where:
Fosc: Input clock.
Prescaler (T1P2, T1P1 and T1P0 / T2P2, T2P1 and T2P0): The options 1:1, 1:2, 1:4,
1:8, 1:16, 1:64, 1:128, and 1:256 are defined by TMRX. It is cleared when any type of
reset occurs.
TMR1 and TMR2: Timer X register. TMRX is increased until it matches with PRDX,
and then is reset to “0” (default value).
DT1 and DT2: Timer X register. TMRX is increased until it matches with DTX, and
then is reset to “0” (default value).
PRDX (PRD1, PRD2): PWM time period register
Comparator X (Comparator 1 and Comparator 2): Reset TMRX while a match
occurs. The TMRXIF (PWMXIF) flag is set at the same time.
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7.9.3 Programming the Related Registers
When defining TMRX, refer to the operation of its related registers as shown in the
following table. It must be noted that the PWMX bits must be disabled if their related
TMRXs are utilized. That is, Bit 7 ~ Bit 3 of the PWMCON register must be set to “0”.
Related Control Registers of TMR1 and TMR2
Addr.
0x07
0x08
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
IPWM2 IPWM1
PWMCON/R7
TMRCON/R8
“0”
“0”
“0” PWMCAS PWM2E PWM1E
T1P2 T1P1 T1P0
E
E
T2EN T1EN T2P2 T2P1 T2P0
7.9.4 Timer Programming Process/Steps
1. Load PRDX with the Timer duration
2. Enable interrupt function by writing IOCF0, if required
3. Load a desired value for the TMRX prescaler, enable TMRX and disable PWMX
7.9.5 PWM Cascade Mode
The PWM Cascade Mode merges two 8-bit PWM function into one 16-bit. In this mode,
the necessary parameters are redefined as shown on the table below:
Parameter
DT (Duty)
PRD (Period)
TMR (Timer)
16-bit PWM
MSB (15~8)
LSB (7~0)
DT2
DT1
PRD2
PRD1
TMR2
TMR1
The prescaler of this 16-bit PWM uses the prescaler of the TMR1. The MSB of TMR is
counted when LSB carry and the PWM1IF bit/PWM1 pins are redefined as the PWMIF
bit/PWM pin (or PWM1 pin).
To PWMIF
(PWM1IF)
latch
DL
Fosc
DT
1:1
1:2
1:4
1:8
1:16
1:64
1:128
1:256
Duty Cycle
Match
16-bit Comparator
TMR
MUX
PWM
(PWM1)
R
S
Q
reset
IOC51,2
16-bit Comparator
T1P2 T1P1T1P0 T1EN
Period
Match
PRD
Data Bus
Data Bus
Figure 7-27 16-Bit PWM Functional Block Diagram (Merged from Two 8 Bits)
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Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.10 Comparator
-
Cin
The EM78P372K has one
comparator which has two
analog inputs and one output.
The comparator can be
-
CO
CMP
Cin+
+
Cin-
Cin+
employed to wake up the system
from sleep/idle mode. The Figure
at right shows the comparator
circuit.
Output
10mV
Figure 7-28 Comparator Operating
Mode
7.10.1 External Reference Signal
The analog signal that is presented at Cin– compares to the signal at Cin+, and the
digital output (CO) of the comparator is adjusted accordingly by taking the following
notes into considerations:
NOTE
■ The reference signal must be between Vss and Vdd.
■ The reference voltage can be applied to either pin of the comparator.
■ Threshold detector applications may be of the same reference.
■ The comparator can operate from the same or different reference sources.
7.10.2 Comparator Output
The compared result is stored in the CMPOUT of IOC80.
The comparator outputs are sent to CO (P64) by programming Bit 4 and Bit 3
<COS1, COS0> of the IOC80 register to <1,0>. See table under Section 6.2.4,
IOC80 (Comparator and TCCA Control Registers) for Comparator/OP select bits
function description.
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71
EM78P372K
8-bit Microcontroller
The following figure shows the Comparator Output block diagram.
To C0
From OP I/O
CMRD
EN
EN
Q
D
Q
D
To CMPOUT
RESET
To CPIF
CMRD
From other
comparator
Figure 7-29 Comparator Output Configuration
7.10.3 Using Comparator as an Operation Amplifier
The comparator can be used as an operation amplifier if a feedback resistor is
externally connected from the input to the output. In this case, the Schmitt trigger
function can be disabled for power saving purposes, by setting Bit 4, Bit 3 <COS1,
COS0> of the IOC80 register to <1,1>. See table under Section 6.2.4, IOC80
(Comparator and TCCA Control Registers) for Comparator/OP select bits function
description.
NOTE
Under Operation Amplifier:
■ The CMPIE (IOCE0.4), CMPWE (RE.2), and CMPIF (RE.4) bits are invalid.
■ The comparator interrupt is invalid.
■ The comparator wake-up is invalid.
7.10.4 Comparator Interrupt
CMPIE (IOCE0.4) must be enabled for the “ENI” instruction to take effect
Interrupt is triggered whenever a change occurs on the comparator output pin
The actual change on the pin can be determined by reading the Bit CMPOUT,
IOC80<5>.
CMPIF (RE.4), the comparator interrupt flag, can only be cleared by software
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EM78P372K
8-bit Microcontroller
7.10.5 Wake-up from Sleep Mode
If the CMPWE bit of the RE register is set to “1,” the comparator remains active
and the interrupt remains functional, even under Sleep mode.
If a mismatch occurs, the change will wake up the device from Sleep mode.
The power consumption should be taken into consideration for the benefit of
energy conservation.
If the function is unemployed during Sleep mode, turn off the comparator before
entering into sleep mode.
The Comparator is considered completed as determined by:
1. COS1 and COS0 bits of IOC80 register setting selects Comparator.
2. CMPIF bit of RE register is set to “1”.
3. CMPWE bit of RE register is set to “1”. Wakes up from Comparator (where it
remains in operation during sleep/idle mode).
4. Wakes-up and executes the next instruction, if CMPIE bit of IOCE0 is enabled and
the “DISI” instruction is executed.
5. Wake-up and enters into Interrupt vector (Address 0x00F), if CMPIE bit of IOCE0 is
enabled and the “ENI” instruction is executed.
6. Enters into Interrupt vector (Address 0x00F), if CMPIE bit of IOCE0 is enabled and
the “ENI” instruction is executed.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
73
EM78P372K
8-bit Microcontroller
7.11 Oscillator
7.11.1 Oscillator Modes
The EM78P372K can be operated in seven different oscillator modes, such as Crystal
Oscillator Mode (XT), High Crystal Oscillator Mode 1 (HXT1), High Crystal Oscillator
Mode 2 (HXT2), Low Crystal Oscillator Mode 1 (LXT1), Low Crystal Oscillator Mode 2
(LXT2), External RC Oscillator Mode (ERC), and RC Oscillator Mode with Internal RC
Oscillator Mode (IRC). You can select one of them by programming the OSC3 ~ OSC0
in the Code Option register.
The Oscillator modes defined by OSC3 ~ OSC0 are described below.
Oscillator Modes
ERC1 (External RC oscillator mode);
OSC3
OSC2
OSC1
OSC0
P55/ADC6/OSCO/ERCin acts as ERCin
P70/ADC5/OSCI/RCOUT acts as P70
0
0
0
0
ERC1 (External RC oscillator mode);
P55/ADC6/OSCO/ERCin acts as ERCin
P70/ADC5/OSCI/RCOUT acts as RCOUT
0
0
0
0
0
0
0
1
1
1
0
1
IRC2 (Internal RC oscillator mode);
P55/ADC6/OSCO/ERCin acts as P55
P70/ADC5/OSCI/RCOUT acts as P70
(default)
IRC2 (Internal RC oscillator mode);
P55/ADC6/OSCO/ERCin acts as P55
P70/ADC5/OSCI/RCOUT acts as RCOUT
LXT13 (Frequency range of XT, mode is 100kHz ~ 1 MHz)
HXT13 (Frequency range of XT mode is 12 MHz ~ 20 MHz)
LXT23 (Frequency range of XT mode is 32.768kHz)
HXT23 (Frequency range of XT mode is 6 MHz ~ 12 MHz)
XT3 (Frequency range of XT mode is 1 MHz ~ 6 MHz)
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
The maximum operating frequency limit of crystal/resonator at different VDDs, are as
follows:
Conditions
VDD
2.1V
3.0V
4.5V
Max. Freq. (MHz)
4
8
Two clocks
16
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Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.11.2 Crystal Oscillator/Ceramic Resonators (Crystal)
The EM78P372K can be driven by an external clock signal through the OSCI pin as
illustrated below.
OSCI
OSCO
Figure 7-30 External Clock Input Circuit
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Figure 6-18 below depicts such a circuit.
The same applies to the XT mode, HXT1 mode, HTX2 mode, LXT1 mode and LXT2
mode.
C1
OSCI
Crystal
OSCO
RS
C2
Figure 7-31 Crystal/Resonator Circuit
The following table provides the recommended values for C1 and C2. Since each
resonator has its own attribute, user should refer to the resonator specifications for the
appropriate values of C1 and C2. RS, a serial resistor, maybe required for AT strip cut
crystal or low frequency mode. Figure 6-21 is PCB layout suggestion. When the
system works in Crystal mode (16 MHz), a 10 K is connected between OSCI and
OSCO.
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75
EM78P372K
8-bit Microcontroller
Capacitor selection guide for crystal oscillator or ceramic resonators:
Oscillator Type
Frequency Mode
Frequency
100kHz
C1 (pF)
60 pF
C2 (pF)
60 pF
60 pF
40 pF
200kHz
60 pF
LXT1
(100 K ~ 1 MHz)
455kHz
40 pF
Ceramic Resonators
1 MHz
30 pF
30 pF
30 pF
20 pF
40 pF
60 pF
60 pF
40 pF
30 pF
30 pF
30 pF
20 pF
30 pF
30 pF
20 pF
30 pF
30 pF
20 pF
30 pF
30 pF
30 pF
20 pF
40 pF
60 pF
60 pF
40 pF
30 pF
30 pF
30 pF
20 pF
30 pF
30 pF
20 pF
30 pF
30 pF
20 pF
1.0 MHz
2.0 MHz
4.0 MHz
32.768kHz
100kHz
200kHz
455kHz
1 MHz
XT
(1 M ~ 6 MHz)
LXT2 (32.768kHz)
LXT1
(100 K ~ 1 MHz)
1.0 MHz
2.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
8.0 MHz
12.0 MHz
12.0 MHz
16.0 MHz
XT
Crystal Oscillator
(1~6 MHz)
HXT2
(6~12 MHz)
HXT1
(12~20 MHz)
Circuit diagrams for serial and parallel modes Crystal/Resonator:
330
330
C
OSCI
7404
7404
7404
Crystal
Figure 7-32 Serial Mode Crystal/Resonator Circuit Diagram
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Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
4.7K
10K
7404
Vdd
OSCI
7404
10K
Crystal
10K
C1
C2
Figure 7-33 Parallel Mode Crystal/Resonator Circuit Diagram
Figure 7-34 Parallel Mode Crystal/Resonator Circuit Diagram
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
77
EM78P372K
8-bit Microcontroller
7.11.1 External RC Oscillator Mode
For some applications that do not require
precise timing calculation, the RC
Vcc
oscillator (Figure 7-35) could offer an
effective cost savings. Nevertheless, it
should be noted that the frequency of the
RC oscillator is influenced by the supply
voltage, the values of the resistor (Rext),
the capacitor (Cext), and even by the
operation temperature. Moreover, the
frequency also changes slightly from one
chip to another due to the manufacturing
process variation.
Rext
ERCin
Cext
Figure 7-35 External RC Oscillator Mode
Circuit
In order to maintain a stable system frequency, the values of the Cext should be no less
than 20 pF, and the value of Rext should not be greater than 1 M. If the frequency
cannot be kept within this range, the frequency can be affected easily by noise,
humidity, and leakage.
The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 K, the oscillator will become
unstable because the NMOS cannot correctly discharge the capacitance current.
Based on the above reasons, it must be kept in mind that all supply voltage, the
operation temperature, the components of the RC oscillator, the package types, and
the PCB layout have certain effects on the system frequency.
The RC Oscillator frequencies:
Cext
Rext
3.3k
5.1k
10k
Average Fosc 5V, 25C
2.064 MHz
1.403 MHz
750.0 kHz
Average Fosc 3V, 25C
1.901 MHz
1.316 MHz
719.0 kHz
20 pF
100k
3.3k
5.1k
10k
81.45 kHz
81.33 kHz
647.0 kHz
615.0 kHz
430.8 kHz
414.3 kHz
100 pF
300 pF
225.8 kHz
219.8 kHz
100k
3.3k
5.1k
10k
23.88 kHz
23.96 kHz
256.6 kHz
245.3 kHz
169.5 kHz
163.0 kHz
88.53 kHz
86.14 kHz
100k
9.283 kHz
9.255 kHz
Note: 1: Measured based on DIP packages.
2: The values are for design reference only.
3: The frequency drift is 30%
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Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.11.2 Internal RC Oscillator Mode
The EM78P372K offers a versatile internal RC mode with default frequency value of
4MHz. The Internal RC oscillator mode has other frequencies (16 MHz, 8 MHz, and 1
MHz) that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below
describes the EM78P372K internal RC drift with voltage, temperature, and process
variations.
Internal RC Drift Rate (Ta=25°C, VDD=5V±5%, VSS=0V)
Drift Rate
Internal
Temperature
Voltage
RC Frequency
Process
Total
(-40°C ~+85°C)
(2.1V~5.5V)
4 MHz
16 MHz
8 MHz
1 MHz
±2%
±2%
±2%
±2%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±4%
±4%
±4%
±4%
Note: Theoretical values are for reference only. Actual values may vary depending on the actual
process.
7.12 Power-on Considerations
Any microcontroller is not warranted to start operating properly before the power supply
stabilizes in steady state. The EM78P372K POR voltage range is 1.9V 0.2V. Under
customer application, when power is switched OFF, Vdd must drop below 1.6V and
remains at OFF state for 10s before power can be switched ON again. Subsequently,
the EM78P372K will reset and work normally. The extra external reset circuit will work
well if Vdd rises fast enough (50ms or less). However, under critical applications, extra
devices are still required to assist in solving power-on problems.
7.12.1 Programmable WDT Time-out Period
The Option word (WDTPS) is used to define the WDT time-out period (18ms5 or
4.5ms6). Theoretically, the range is from 4.5ms or 18ms. For most crystal or ceramic
resonators, the lower the operation frequency is, the longer is the required set-up time.
5
VDD=5V, WDT time-out period = 16.5ms ± 30%.
VDD=3V, WDT time-out period = 18ms ± 30%.
6
VDD=5V, WDT time-out period = 4.2ms ± 30%.
VDD=3V, WDT time-out period = 4.5ms ± 30%.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
79
EM78P372K
8-bit Microcontroller
7.12.2 External Power-on Reset Circuit
The circuits shown in the
following figure implements
an external RC to produce a
reset pulse. The pulse width
(time constant) should be
kept long enough to allow
the Vdd to reach the
VDD
/RESET
R
D
Rin
C
minimum operating voltage.
This circuit is used when the
power supply has a slow
power rise time. Because
Figure 7-36 External Power-on Reset
Circuit
the current leakage from the /RESET pin is about 5A, it is recommended that R
should not be greater than 40KΩ. This way, the voltage at Pin /RESET is held below
0.2V. The diode (D) functions as a short circuit at power-down. The “C” capacitor is
discharged rapidly and fully. Rin, the current-limited resistor, prevents high current
discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
7.12.3 Residual Voltage Protection
When the battery is replaced, device power (Vdd) is removed but residual voltage
remains. The residual voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. Figure 7-37 and Figure 7-38 show how to
create a protection circuit against residual voltage.
VDD
VDD
33K
Q1
10K
/RESET
100K
1N4684
Figure 7-37 Residual Voltage Protection Circuit 1
80
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
VDD
VDD
R1
R2
Q1
R3
/RESET
Figure 7-38 Residual Voltage Protection Circuit 2
7.13 Code Option
EM78P372K has six Code Option Words and three Customer ID words that are not part
of the normal program memory.
Word 0
Word1
Word 2
Word 3
Word 0x10
Word 0x11
Bit 12~Bit 0
Bit 12~Bit 0
Bit12~Bit 0
Bit12~Bit 0
Bit12~Bit 0
Bit12~Bit 0
7.13.1 Code Option Register (Word 0)
Word 0
Bit
Bit 12 Bit 11 Bit 10
Bit9
Bit 8
Bit 7
Bit6
Bit5
Bit4
Bit3
NRE
32/fc Enable
Bits2~0
Mne
TYPE1 TYPE0 WK_CLK CLKS LVR1
LVR0
RESETEN
ENWDT NRHL
Protect
monic
1
0
High
Low
High
Low
8clock
High
High
Low
High
Low
Disable
Enable
Disable
Enable
Disable
Enable
32clock Low
8/fc
Disable
Bits 12~11 (TYPE1 ~ TYPE0): Type selection for EM78P372K
TYPE 1, TYPE 0
MCU Type
PIN Not Used
00
01
10
11
EM78P372K-10Pin
Ports 60 ~ 66 / 54 / 56 / 57 are output low.
Ports 62 / 63 / 64 / 65 / 56 / 57 are output low.
Ports 56 / 57 are output low.
X
EM78P372K-14Pin
EM78P372K-18Pin
EM78P372K-20Pin (Default)
Bit 10 (WK_CLK): Selecting 8 or 32 clocks wake up from sleep and idle mode
(only IRC mode)
0 : 32 clocks
1 : 8 clocks (default)
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EM78P372K
8-bit Microcontroller
Bit 9 (CLKS):
Instruction period option bit
0 = two oscillator periods
1 = four oscillator periods (default)
Bits 8~7 (LVR1 ~ LVR0): Low Voltage Reset Enable bits
LVR1, LVR0
VDD Reset Level
VDD Release Level
11
10
01
00
NA (Power-on Reset) (Default)
2.7V
3.5V
4.0V
2.9V
3.7V
4.2V
Bit 6 (RESETEN): RESET/P71 Pin Select Bit
0 : P71 set to /RESET pin
1 : P71 is general purpose input pin or open-drain for output Port
(default)
Bit 5 (ENWDT):
Watchdog timer enable bit
0 = Enable
1 = Disable (default)
Bit 4 (NRHL): Noise rejection high/low pulses define bit. INT pin is falling or rising
edge trigger
0 : Pulses equal to 8/fc is regarded as signal
1 : Pulses equal to 32/fc is regarded as signal (default)
NOTE
The noise rejection function is turned off in the LXT2 and sleep mode.
Bit 3 (NRE):
Noise Rejection Enable
0 : Disable noise rejection
1 : Enable noise rejection (default), but in Low Crystal oscillator
(LXT) mode, the noise rejection circuit is always disabled.
Bits 2 ~ 0 (Protect): Protect Bit
Protect Bits
Protect
Enable
0
1
Disable (default)
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EM78P372K
8-bit Microcontroller
7.13.2 Code Option Register (Word 1)
Word 1
Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Bit1 Bit0
Mnem
RCOU
T
C5
C4
C3
C2
C1
C0 RCM1 RCM0 OSC3 OSC2 OSC1 OSC0
onic
Syste
m_clk
1
High High High High High High High High High High High High
Open_
drain
0
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Bits 12~7 (C5~C0): Calibrator of internal RC mode
C5~C0 must be set to “1” only (auto-calibration).
Bits 6~5 (RCM1, RCM0): RC mode selection bits
RCM 1 RCM 0 Frequency (MHz)
1
1
4 (Default)
1
0
0
0
1
0
16
8
1
Bits 4 ~ 1 (OSC3 ~ OSC0): Oscillator Modes Selection bits
Oscillator Modes
OSC3 OSC2 OSC1 OSC0
ERC1 (External RC oscillator mode);
P55/ADC6/OSCO/ERCin acts as ERCin
P70/ADC5/OSCI/RCOUT acts as P70
0
0
0
0
0
0
0
1
ERC1 (External RC oscillator mode);
P55/ADC6/OSCO/ERCin acts as ERCin
P70/ADC5/OSCI/RCOUT acts as RCOUT
IRC2 (Internal RC oscillator mode);
P55/ADC6/OSCO/ERCin acts as P55
P70/ADC5/OSCI/RCOUT acts as P70
(default)
0
0
1
0
IRC2 (Internal RC oscillator mode);
P55/ADC6/OSCO/ERCin acts as P55
P70/ADC5/OSCI/RCOUT acts as RCOUT
0
0
1
1
LXT13 (Frequency range of XT, mode is 100kHz~1 MHz)
HXT13 (Frequency range of XT mode is 12MHz~20 MHz)
LXT23 (Frequency range of XT mode is 32.768kHz)
HXT23 (Frequency range of XT mode is 6 MHz~12 MHz)
XT3 (Frequency range of XT mode is 1 MHz~6 MHz)
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
Bit 0 (RCOUT): Instruction clock output enable bit in IRC or ERC mode.
0 : RCOUT pin output instruction clock with open drain.
1 : RCOUT pin output instruction clock(default)
Product Specification (V1.4) 05.11.2016
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83
EM78P372K
8-bit Microcontroller
7.13.3 Code Option Register (Word 2)
Word 2
Bit 7 Bit 6
Bit
Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 5
Bit 4
Bit 3
Bit2
Bit1
Bit0
Mne
monic
–
–
–
–
–
SFS
IRCPSS IRCIRS
HLP
WDTPS ID2
ID1
ID0
1
0
–
–
–
–
–
–
16kHz
–
–
Internal Regulator High
VDD Bandgap Low
–
–
18ms
High
Low
High
Low
High
Low
128kHz
4.5ms
Bit 12:
Bit 11:
Bit 10:
Not used, (reserved). This bit is set to “1” all the time.
Not used, (reserved). This bit is set to “0” all the time.
Not used, (reserved). This bit is set to “1” all the time.
Bit 9 (SFS):
Sub-oscillator select for Green mode and TCC, PWM1, PWM2
clock source.
(Not include WDT time-out and free run setup-up time)
0 : 128kHz
1 : 16kHz (default)
Bit 8:
Not used, (reserved). This bit is set to “0” all the time.
Bit 7 (IRCPSS):
IRC Power Source Select
0 = VDD
1 = Internal reference (default)
Bit 6 (IRCIRS):
IRC Internal reference Select.
0 = IRC Bandgap Mode (Vref is used from Bandgap).
1 = IRC Regulator Mode (default)
Bit 5 (HLP):
Power consumption selection
0: Low power consumption mode, applies to operating frequency
at 400 kHz or below 400kHz
1: High power consumption mode, applies to operating frequency
above 400 kHz (Default)
(User selects LXT1 or LXT2 in crystal mode, HLP function
automatically selects low)
Bit 4 (LPS):
Not used, (reserved). This bit is set to “1” all the time.
Bit 3 (WDTPS):
WDT Time-out Period
WDT Time
Watchdog Timer*
18 ms (Default)
4.5 ms
1
0
*Theoretical values, for reference only.
Bits 2 ~ 0:
Customer’s ID Ⅰcode (Can’t be read from Table Point Register)
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EM78P372K
8-bit Microcontroller
7.13.4 Code Option Register (Word 3)
Word 3
Bit
Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
–
–
–
VREFSEL
High
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
0
Low
Bit 12:
Not used, (reserved). This bit is set to “1” all the time.
Bit 11 (VREFSEL): ADC internal reference voltage select. [Depend on VREF[1:0]
(Bank 0-RA[2:1]) = 11]
0: ADC Internal reference voltage 2.5V.
1: ADC Internal reference voltage 2.0V (Default)
Bits 10 ~ 0: Not used (Reserved). This bit is set to “1” all the time.
7.13.5 Customer ID Register (Word 0x10)
Word 0x10
Bit
Bit 12 Bit 11
Bit 10
ID13
High
Low
Bit 9
ID12
High
Low
Bit 8
ID11
High
Low
Bit 7
ID10
High
Low
Bit 6
ID9
Bit 5
ID8
Bit 4
ID7
Bit 3
ID6
Bit2
ID5
Bit1
ID4
Bit0
ID3
Mnemonic ID15
ID14
High
Low
1
0
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
Bits 12 ~ 0: Customer’s ID Ⅱ code (Can be read from Table Point Register)
7.13.6 Customer ID Register (Word 0x11)
Word 0x11
Bit
Bit 12 Bit 11
Bit 10
ID26
High
Low
Bit 9
ID25
High
Low
Bit 8
ID24
High
Low
Bit 7
ID23
High
Low
Bit 6
ID22
High
Low
Bit 5
ID21
High
Low
Bit 4
ID20
High
Low
Bit 3
ID19
High
Low
Bit2
ID18
High
Low
Bit1
ID17
High
Low
Bit0
ID16
High
Low
Mnemonic ID28
ID27
High
Low
1
0
High
Low
Bits 12 ~ 0:
Customer’s ID Ⅲ code (Can be read from Table Point Register)
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
85
EM78P372K
8-bit Microcontroller
7.14 Low Voltage Detector/Low Voltage Reset
The Low Voltage Reset (LVR) and the Low Voltage Detector (LVD) are designed for
unstable power situation, such as external power noise interference or in EMS test
condition.
When LVR is enabled, the system supply voltage (Vdd) drops below Vdd reset level
(V ) and remains at 10s, a system reset will occur and the system will remain in
RESET
reset status. The system will remain at reset status until Vdd voltage rises above Vdd
release level.
If Vdd drops below the low voltage detector level, /LVD (Bit 7 of RE) is cleared to “0’ to
show a low voltage signal when LVD is enabled. This signal can be used for low voltage
detection.
7.14.1 Low Voltage Reset
LVR property is set at Bits 12 and 11 of Code Option Word 0. Detailed operation mode
is as follows:
Word 0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2~0
TYPE1
TYPE0
WK_CLK
CLKS
LVR1
LVR0 RESETEN ENWDT NRHL
NRE
Protect
Bits 8~7 (LVR1 ~ LVR0): Low Voltage Reset Enable bits.
LVR1, LVR0
VDD Reset Level
VDD Release Level
11
10
01
00
NA (Power-on Reset)
2.7V
3.5V
4.0V
2.9V
3.7V
4.2V
7.14.2 Low Voltage Detector
LVD property is set and Register detailed operation mode is as follows:
7.14.2.1 Bank 1 RE (LVD Control and Wake-up Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDIE
LVDEN
LVD1
LVD0
-
-
-
EXWE
NOTE
■ Bank 1 RE<6> register is both readable and writable
■ Individual interrupt is enabled by setting its associated control bit in the Bank 1
RE<7> to "1".
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction.
86
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EM78P372K
8-bit Microcontroller
Bit 7 (LVDIE): Low voltage Detector interrupt enable bit.
0 : Disable Low voltage Detector interrupt
1 : Enable Low voltage Detector interrupt
When detect low level voltage state is used to enter an interrupt vector
or enter next instruction, the LVDIE bit must be set to “Enable”.
Bit 6 (LVDEN): Low Voltage Detector Enable bit
0 : Low voltage detector disable
1 : Low voltage detector enable
Bits 5~4 (LVD1:0): Low Voltage Detector level bits.
LVDEN
LVD1, LVD0
LVD voltage Interrupt Level
Vdd ≤ 2.2V
Vdd > 2.2V
Vdd ≤ 3.3V
Vdd > 3.3V
Vdd ≤ 4.0V
Vdd > 4.0V
Vdd ≤ 4.5V
Vdd > 4.5V
NA
/LVD
0
1
0
1
0
1
0
1
1
1
11
1
1
10
01
1
0
00
××
7.14.2.2 Bank 0 RE (Interrupt Status 2 and Wake-up Control
Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
ADIF
CMPIF
ADWE
CMPWE
ICWE
LVDWE
NOTE
■ RE < 6, 5, 4 > can be cleared by instruction but cannot be set.
■ IOCE0 is the interrupt mask register.
■ Reading RE will result to "Logic AND" of RE and IOCE0.
Bit 7 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin
voltage is lower than LVD voltage interrupt level (selected by LVD1 and
LVD0), this bit will be cleared.
0 : Low voltage is detected.
1 : Low voltage is not detected or LVD function is disabled.
Bit 6 (LVDIF): Low Voltage Detector Interrupt flag
LVDIF reset to “0” by software or hardware.
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit.
0 : Disable Low Voltage Detect wake-up.
1 : Enable Low Voltage Detect wake-up.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
87
EM78P372K
8-bit Microcontroller
When the Low Voltage Detect is used to enter an interrupt vector or to
wake up the IC from sleep/idle with Low Voltage Detect running, the
LVDWE bit must be set to “Enable“.
7.14.3 Programming Process
Follow these steps to obtain data from the LVD:
1. Write to the two bits (LVD1: LVD0) on the LVDCR register to define the LVD level.
2. Set the LVDWE bit, if the wake-up function is employed.
3. Set the LVDIE bit, if the interrupt function is employed.
4. Write “ENI” instruction, if the interrupt function is employed.
5. Set LVDEN bit to 1
6. Write “SLEP” instruction or Polling /LVD bit.
7. Clear the low voltage detector interrupt flag bit (LVDIF) when Low Voltage Detector
interrupt occurred.
The LVD module uses the internal circuit. When LVDEN (Bit 6 of Bank 1 RE) is set to
“1”, the LVD module is enabled.
When LVDWE (Bit 0 of RE) is set to “1”, the LVD module will continue to operate during
sleep/idle mode. If Vdd drops slowly and crosses the detect point (VLVD), the LVDIF
(Bit 6 of RE) will be set to “1”, the /LVD (Bit 7 of RE) will be cleared to “0”, and the
system will wake up from Sleep/Idle mode. When a system reset occurs, the LVDIF will
be cleared.
When Vdd remains above VLVD, LVDIF is kept at “0” and /LVD is kept at “1”. When Vdd
drops below VLVD, LVDIF is set to “1” and /LVD is kept at “0”. If ENI instruction is
executed, LVDIF will be set to “1”, and the next instruction will branch to interrupt Vector
021H. The LVDIF is cleared to “0” by software. Refer Figure 6-26 below.
LVDIF is cleared by
software
Vdd
VLVD
VRESET
LVDIF
Internal
18ms
Reset
<LVR Voltage drop
>LVR Voltage drop
Vdd < Vreset not longer than 10us, the system still keeps on operating
System occur reset
Figure 7-34 LVD/LVR Waveform Situation
88
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
7.15 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of two oscillator time periods), unless the program
counter is changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of
arithmetic or logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.).
In addition, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O registers can be regarded as general registers. That is, the same
instruction can operate on I/O registers.
The following symbols are used in the Instruction Set table:
Convention:
R = Register designator that specifies which one of the registers (including operation and general
purpose registers) is to be utilized by the instruction.
Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects
the operation.
k = 8 or 10-bit constant or literal value
Mnemonic
Operation
Status Affected
NOP
DAA
No Operation
None
C
Decimal Adjust A
A CONT
0 WDT, Stop oscillator
0 WDT
CONTW
SLEP
None
T, P
T, P
None1
None
None
None
None
None
None1
None
Z
WDTC
IOW R
ENI
A IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
[Top of Stack] PC, Enable Interrupt
CONT A
IOCR A
A R
0 A
DISI
RET
RETI
CONTR
IOR R
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
0 R
R-A A
R-A R
R-1 A
Z
Z, C, DC
Z, C, DC
Z
R-1 R
Z
A VR A
A VR R
A & R A
A & R R
A R A
Z
Z
Z
Z
Z
A R R
Z
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
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EM78P372K
8-bit Microcontroller
Mnemonic
Operation
Status Affected
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
A + R A
A + R R
R A
R R
/R A
Z, C, DC
Z, C, DC
Z
Z
Z
/R R
Z
INCA R
INC R
R+1 A
R+1 R
Z
Z
DJZA R
DJZ R
R-1 A, skip if zero
R-1 R, skip if zero
R(n) A(n-1), R(0) C, C A(7)
R(n) R(n-1), R(0) C,
C R(7)
R(n) A(n+1), R(7) C,
C A(0)
R(n) R(n+1), R(7) C,
C R(0)
None
None
C
RRCA R
RRC R
RLCA R
RLC R
C
C
C
R(0-3) A(4-7),
R(4-7) A(0-3)
R(0-3) R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 R(b)
SWAPA R
None
SWAP R
JZA R
None
None
None
None 2
None 3
None
None
None
None
None
Z
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
JMP k
1 R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 [SP], (Page, k) PC
(Page, k) PC
k A
A k A
A & k A
A k A
k A, [Top of Stack] PC
k-A A
k+A A
k R3(5)
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
Add A,K
PAGE k
BANK k
Z
Z
None
Z, C, DC
Z, C, DC
None
None
k R4(6)
LCALL k
LJMP k
PC+1[SP], kPC
kPC
None
None
If Bank 1 R5.7=0, machine code(7~0) R
Else Bank1 R5.7=1, machine code(12~8) R(4~0),
R(7~5)=(0,0,0)
TBRD R
None
1
Note: This instruction is applicable to IOC50~IOCF0, IOC51 ~ IOCF1 only.
2
This instruction is not recommended for RF operation.
3
This instruction cannot operate under RF.
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Product Specification (V1.4) 05.11.2016
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EM78P372K
8-bit Microcontroller
8 Absolute Maximum Ratings
Items
Rating
Temperature under bias
Storage temperature
Input voltage
-40C
-65C
Vss-0.3V
Vss-0.3V
2.1V
to
to
to
to
to
to
85C
150C
Vdd+0.5V
Vdd+0.5V
5.5V
Output voltage
Working Voltage
Working Frequency
DC
16 MHz
9 DC Electrical Characteristics
Ta= 25C, VDD= 5.0V, VSS= 0V
Symbol
FXT
Parameter
Crystal: VDD to 5V
ERC: VDD to 5V
Condition
Min.
Typ.
4
Max.
16
Unit
MHz
kHz
Two cycles with two clocks 32.768k
ERC
R: 5.1K, C: 100 pF
760
950
1140
Input High Voltage
(Schmitt Trigger)
VIH1
Ports 5, 6, 7
0.7VDD
VDD+0.3
V
V
V
V
V
V
Input Low Voltage
(Schmitt Trigger )
VIL1
Ports 5, 6, 7
/RESET
-0.3V
0.3VDD
Input High Threshold
VIHT1
VILT1
VIHT2
VILT2
IOH1
1.8
1.1
Voltage (Schmitt Trigger)
Input Low Threshold
/RESET
Voltage (Schmitt trigger)
Input High Threshold
TCC, INT
TCC, INT
0.7VDD
-0.3V
VDD+0.3
0.3VDD
Voltage (Schmitt Trigger)
Input Low Threshold
Voltage (Schmitt Trigger)
Output High Voltage
(Ports 5, 6, 7)
-3.7
VOH = 0.9VDD
VOL = 0.1VDD
mA
mA
Output High Voltage
(Ports 51~54,
IOH2
IOL1
IOL2
-10
10
25
56~57,60~67)
Output Low Voltage
(Ports 5, 6, 7)
Output Low Voltage
(Ports 51~54, 56~57,
60~67)
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
91
EM78P372K
8-bit Microcontroller
Symbol
Parameter
Condition
Min. Typ.
Max.
2.99
3.25
3.92
4.25
4.43
4.81
Unit
V
Ta=25°C
2.41
2.14
3.1
2.7
2.7
3.5
3.5
4.0
4.0
70
LVR1
LVR2
LVR3
Low voltage reset level
Low voltage reset level
Low voltage reset level
Ta=-40~85°C
V
Ta=25°C
V
Ta=-40~85°C
2.73
3.56
3.16
V
Ta=25°C
V
Ta=-40~85°C
V
IPH
IPL
Pull-high current
Pull-low current
Pull-high active, input pin at VSS
Pull-low active, input pin at Vdd
A
A
40
All input and I/O pins at VDD,
ISB1
ISB2
Power down current
Power down current
1.0
2.0
10
A
A
Output pin floating, WDT disabled
All input and I/O pins at VDD,
Output pin floating, WDT enabled
/RESET= 'High', Fosc=32kHz
(Crystal type, CLKS="0"),
Operating supply current
at two clocks
ICC1
ICC2
ICC3
ICC4
15
15
20
25
A
A
Output pin floating, WDT disabled
/RESET= 'High', Fosc=32kHz
(Crystal type,CLKS="0"),
Operating supply current
at two clocks
Output pin floating, WDT enabled
/RESET= 'High', Fosc=4 MHz
(Crystal type, CLKS="0"),
Operating supply current
at two clocks
1.5
2.8
1.7
3.0
mA
mA
Output pin floating, WDT enabled
/RESET= 'High', Fosc=10 MHz
(Crystal type, CLKS="0"),
Operating supply current
at two clocks
Output pin floating, WDT enabled
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only.
2. Data under Minimum, Typical, and Maximum (Min., Typ., and Max.) columns are based on
hypothetical results at 25 C. These data are for design reference only.
92
Product Specification (V1.4) 05.11.2016
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EM78P372K
8-bit Microcontroller
9.1 AD Converter Characteristics
Vdd=2.5V to 5.5V, Vss=0V, Ta=-40 to 85°C
Symbol
VAREF
VASS
Parameter
Condition
Min. Typ. Max. Unit
2.5
Vss
VASS
Vdd
Vss
V
V
V
Analog reference
voltage
VAREF - VASS 2.5V
VAI
Analog input voltage
VAREF
Ivdd
VDD=VAREF=5.0V,
1400 µA
10 µA
IAI1
Analog supply current VASS = 0.0V
Ivref
Ivdd
IVref
(V reference from Vdd)
VDD=VAREF=5.0V,
Analog supply current VASS = 0.0V (V reference
from VREF)
900 µA
500 µA
IAI2
ADREF=0, Internal VDD
Resolution
10
12
RN1
9
Bits
Bits
VDD=5.0V, VSS = 0.0V
ADREF=1, External VREF
RN2
Resolution
11
VDD=VREF=5.0V,
VSS = 0.0V
LN1
DNL
Linearity error
VDD = 2.5 to 5.5V Ta=25°C
VDD = 2.5 to 5.5V Ta=25°C
±4 LSB
±1 LSB
Differential nonlinear
error
VDD=VAREF=5.0V,
VASS = 0.0V
FSE1
OE
Full scale error
Offset error
±8 LSB
±4 LSB
VDD=VAREF=5.0V,
VASS = 0.0V
Recommended
ZAI
impedance of analog
voltage source
10
KΩ
VDD=VAREF=5.0V,
VASS = 0.0V
2
TAD
TCN
PSR
ADC clock duration
AD conversion time
1
16
µs
VDD=VAREF=5.0V,
VASS = 0.0V
TAD
LSB
Power Supply
Rejection
VDD=5.0V±0.5V
±3
±3
V1/4VDD
V1/2VDD
Accuracy for 1/4 VDD
Accuracy for 1/2 VDD
%
%
Note: 1. These parameters are hypothetical (not tested) and provided for design reference use
only.
2. When ADC is off, there is no current consumption other than minor leakage current.
3. AD conversion result will not decrease when an increase of input voltage and no missing
code will result.
4. These parameters are subject to change without further notice.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
93
EM78P372K
8-bit Microcontroller
9.2 Comparator Characteristics
Vdd = 5.0V, Vss=0V, Ta=-40 to 85°C
Symbol
Parameter
Condition
Min.
Typ. Max. Unit
VOS
Vcm
Input offset voltage
10
mV
V
Input common-mode
voltage range
GND
VDD
Supply current of
comparator
ICO
TRS
TLRS
IOL
Co=0V, Ta= -40~85℃
70
1
µA
µs
VREF=1.0V, VRL=5V,
Response time
RL=5.1k, CL=15p (Note1)
Large signal response VREF=2.5V, VRL = 5V,
time
250
12
ns
RL = 5.1k (Note2)
Vi(-) = 1V, Vi(+) = 0V,
Vo = GND+0.5V (Note3)
Output sink current
mA
Vi(-)=1V, Vi(+)=0V,
IOL <= 4mA (Note3)
VSAT Saturation voltage
VS Operating voltage
0.2
-
0.4
5.5
V
V
2.5
Note: 1. The response time specified is a 100mV input step with 5mV overdrive.
2. The response time specified is a 0V~VDD input step with 1/2*VDD overdrive.
3. The driving ability is decided by digital output block.
9.3 OP Characteristics
Vdd = 5.0V, Vss=0V, Ta=-40 to 85°C
Symbol
VOS
SR
Parameter
Input offset voltage
Slew rate
Condition
, Vin+=0V
Min.
Typ.
10
Max. Unit
0
5
mV
V/µs
V
Ta= -40~85℃
1.5
IVR
Input voltage range
Vip=0V,IL=1.0mA
123
mV
V
Ta= -40~85℃
OVS
Output voltage swing
Vip=5V, IL=1.0mA
4.68
Ta= -40~85℃
IOP
Supply current of OP
Ta= -40~85℃
255
75
90
2.6
µA
dB
PSRR Power supply rejection ratio Ta= -40~85℃
CMRR Common mode reject ratio 0V≦VCM≦VDD
dB
GBP
VS
Gain bandwidth product
Operating Range
RL=1Meg, CL=100p
MHz
V
2.5
5.5
Note: 1. These parameters are hypothetical (not tested) and provided for design
reference use only.
2. These parameters are subject to change without further notice.
94
Product Specification (V1.4) 05.11.2016
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EM78P372K
8-bit Microcontroller
9.4 Vref 2V/2.5V/3V/4V Characteristics
Vdd = 5.0V, Vss=0V, Ta=-40 to 85°C
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDD
Power Supply
2.1
5.5
V
VDD = 5.5V, No
load
IVDD
Vref
DC Supply Current
200
±1
µA
%
2V
3V
4V
Voltage reference
output
VDD = 2.1 - 5.5V,
Cload = 19.2pf,
Rload = 15.36KΩ
Switch Vref
response time
VrefRT
5
µs
VDD = VDDmin
5.5V,
-
Enable Vref warm
up time
VrefWT
8
µs
V
Cload = 19.2pf,
Rload = 15.36KΩ
Minimum Power
Supply
Vref +
0.2*
VDDmin
*VDDmin : can work at (Vref+0.1V), but has a poor PSRR.
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
95
EM78P372K
8-bit Microcontroller
10 AC Electrical Characteristics
Ta=-40 to 85 C, VDD=5V 5%, VSS=0V
Symbol
Parameter
Conditions
–
Min.
45
Typ.
Max.
55
Unit
%
Dclk
Input CLK duty cycle
50
–
Crystal type
RC type
125
–
DC
–
ns
Instruction cycle time
(CLKS="0")
Tins
Ttcc
16 30%
ns
WSTO +
510/Fm
TCC input time period
–
–
–
ns
Tdrh
Trst
Device reset hold time
/RESET pulse width
Watchdog timer duration
Input pin setup time
Input pin hold time
Ta = 25C
Ta = 25C
Ta = 25C
–
–
–
–
–
–
–
–
WSTO + 8/Fs
WSTO + 8/Fm
WSTO + 8/Fs
1 s
–
–
–
–
–
–
–
ms
ns
ms
ns
ns
ns
ns
Twdt
Tset
Thold
Tdelay
Tdrc
–
1 s
Output pin delay time
ERC delay time
Cload=20pF
16 30%
20
Ta = 25 C
Note: 1. WSTO: The waiting time of Start-to-Oscillation
2. These parameters are hypothetical (not tested) and are provided for design reference
only.
3. Data under Minimum, Typical, and Maximum (Min., Typ. and Max.) columns are based
on hypothetical results at 25C. These data are for design reference use only.
*. Tpor and Twdt are 16 30% ms at FSS0=1(16kHz), Ta=-40~85C, and VDD=2.1~5.5V
96
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(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
11 Timing Diagrams
AC Test Input / Output Waveform
VDD-0.5
GND+0.5
0.75 VDD
0.25 VDD
0.75 VDD
TEST POINTS
0.25 VDD
Note: AC Testing: Input are driven at VDD-0.5V for Logic “1” and GND+0.5V for Logic “0”
Timing measurements are made at 0.75V VDD for Logic “1” and 0.25V VDD for Logic “0”
Figure 11-1a AC Test Input / Output Waveform Timing Diagram
Reset Timing (CLK=“0”)
Instruction 1
NOP
Executed
CLK
/RESET
Tdrh
Figure 11-1b Reset Timing Diagram
TCC Input Timing (CLKS=“0”)
ins
CLK
TCC
tcc
Figure 11-1c TCC Input Timing Diagram
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
97
EM78P372K
8-bit Microcontroller
APPENDIX
A Ordering and Manufacturing Information
EM78P372KD14J
Material Type
J: RoHS complied
S: Sony SS-00259 complied
Contact Elan Sales for details
Pin Number
Package Type
D: DIP
SO: SOP
Check the following section
Specific Annotation
Product Number
Product Type
P: OTP
Elan 8-bit Product
For example:
EM78P372KSO14S
is EM78P372K with OTP program memory product,
in 14-pin SOP 300mil package with Sony SS-00259 complied
IC Mark
‧‧‧‧‧‧‧
Elan Product Number / Package, Material Type
Batch Number
EM78Paaaaaa
1041c bbbbbb
Manufacture Date
“YYWW”
YY is year and WW is week
c is Alphabetical suffix code for Elan use only
‧‧‧‧‧‧‧
98
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
Ordering Code
EM78P372KD14J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
B Package Type
OTP MCU
EM78P372KMS10
EM78P372KD14
EM78P372KSO14
EM78P372KSO16A
EM78P372KD18
EM78P372KSO18
EM78P372KD20
EM78P372KSO20
EM78P372KSS20
EM78P372KQN16
Package Type
Pin Count
Package Size
118 mil
MSOP
DIP
10
14
14
16
18
18
20
20
20
16
300 mil
SOP
SOP
DIP
150 mil
150 mil
300 mil
SOP
DIP
300 mil
300 mil
SOP
SSOP
QFN
300 mil
209 mil
3×3×0.8mm
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
Pb content is less than 100ppm and complies with Sony specifications.
Part No.
EM78P372KxJ/xS
Pure Tin
Electroplate type
Ingredient (%)
Sn: 100%
Melting point (°C)
232°C
Electrical resistivity
(µ-cm)
11.4
Hardness (hv)
Elongation (%)
8~10
>50%
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
99
EM78P372K
8-bit Microcontroller
C Packaging Configuration
C.1 EM78P372KD14
Min.
Normal
Symbol
A
Max.
4.318
D
E1
A1
A2
c
0.381
14
8
3.175 3.302
0.203 0.254 0.356
18.796 19.050 19.304
3.429
C
D
E
E
E1
6.174 6.401
7.366 7.696
8.409 9.017
0.356 0.457 0.559
1.143 1.524 1.778
6.628
8.025
9.625
eB
e
B
1
7
B
B1
L
θ
3.302 3.556
3.048
2.540 (TYP)
e
θ
0
15
A1
A2
A
L
B
e
B1
TITLE:
PDIP-14L 300 MIL PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
D14
Unit: mm
Scale: Free
Material:
Sheet: 1 of1
Figure C-1 EM78P372K 14-pin PDIP Package Type
100
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
C.2 EM78P372KSO14
Symbol
Normal
Max.
1.750
0.250
0.510
0.250
4.000
6.200
8.750
1.270
Min.
1.350
0.100
0.330
0.190
3.800
5.800
8.550
0.600
A
A1
b
c
E
H
D
L
E
H
1.27 (TYP)
e
θ
0
8
e
b
c
D
A2
A
:
TITLE
SOP-14L(150MIL) PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
NSO14
Unit: mm
Scale: Free
Material:
Sheet: 1 of1
Figure C-2 EM78P372K 14-pin SOP Package Type
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
101
EM78P372K
8-bit Microcontroller
C.3 EM78P372KSO16A
Symbol
Min.
1.350
0.100
1.300
0.330
0.190
3.800
5.800
9.800
0.600
Normal
1.400
Max.
1.750
0.250
1.500
0.510
0.250
4.000
6.200
10.000
1.270
A
A1
A2
b
c
E
H
D
L
e
1.27 (TYP)
θ
0
8
b
e
c
TITLE:
SOP-16L(150MIL) PACKAGE OUTLINE
DIMENSION
File :
Edtion:
A
NSO16
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure C-3 EM78P372K 16-pin SOP Package Type
102
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
C.4 EM78P372KD18
Symbol
Min. Normal Max.
4.450
A
A1
A2
c
0.381
3.175
3.302
3.429
0.203 0.254 0.356
22.610 22.860 23.110
D
6.220
7.370
8.510
6.438
7.620
9.020
6.655
7.870
9.530
E1
E
eB
B
B1
L
0.356 0.457 0.559
1.143 1.524 1.778
eB
3.302 3.556
3.048
2.540 (TYP.)
e
θ
0
15
θ
TITLE:
PDIP-18L 300 MIL PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
D18
Unit: mm
Scale: Free
Material:
Sheet: 1 of1
Figure C-4 EM78P372K 18-pin PDIP Package Type
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
103
EM78P372K
8-bit Microcontroller
C.5 EM78P372KSO18
Min.
2.350
0.102
Normal
Max.
2.650
0.300
Symbol
A
A1
b
0.406 (TYP)
c
E
0.230
7.400
0.320
7.600
H
D
L
e
θ
10.000
11.350
0.406
10.650
11.750
1.270
0.838
1.27 (TYP)
0
8
b
e
c
TITLE :
SOP-18L (300MIL) PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
SO18
Unit: mm
Scale: Free
Material:
Sheet: 1 of1
Figure C-5 EM78P372K 18-pin SOP Package Type
104
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
C.6 EM78P372KD20
Symbol Min. Normal Max.
E
A
A1
A2
c
4.450
0.381
3.175
0.203
3.429
0.356
3.302
0.254
D
25.883
6.220
7.370
8.510
0.356
1.143
26.237
6.655
26.060
6.438
7.620
9.020
0.457
1.524
E1
E
7.870
9.530
0.559
1.778
3.556
eB
B
B1
L
3.048 3.302
2.540 (TYP.)
e
0
15
θ
:
TITLE
PDIP-20L 300MIL PACKAGE
OUTLINE DIMENSION
:
File
Edtion :A
D20
Unit :mm
Scale: Free
Material:
Sheet:1 of1
Figure C-6 EM78P372K 20-pin PDIP Package Type
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
105
EM78P372K
8-bit Microcontroller
C.7 EM78P372KSO20
Symbol
Min.
2.350
0.102
Normal
Max.
2.650
0.300
A
A1
b
0.406 (TYP.)
c
0.230
7.400
0.320
7.600
E
H
D
L
10.000
12.600
0.630
10.650
12.900
1.100
0.838
1.27 (TYP.)
e
0
8
θ
b
e
c
TITLE:
SOP-20L(300MIL) PACKAGE
OUTLINE DIMENSION
:
File
Edtion: A
SO20
Unit : mm
Scale: Free
Materia:l
Sheet: 1 of1
Figure C-7 EM78P372K 20-pin SOP Package Type
106
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
C.8 EM78P372KSS20
Symbol
Min.
Normal
Max.
2.130
0.250
1.880
0.380
0.200
8.200
5.600
7.500
0.850
A
A1
A2
b
c
E
E1
D
L
0.050
1.620
0.220
0.090
1.750
7.400
5.000
6.900
0.650
7.800
5.300
7.200
0.750
L1
e
1.250 (REF )
0.650 (TYP)
4
0
8
θ
b
e
c
L1
:
TITLE
SSOP-20L (209MIL) PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
SSOP20
Unit: mm
Scale: Free
Material:
Sheet: 1 of1
Figure C-8 EM78P372K 20-pin SSOP Package Type
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
107
EM78P372K
8-bit Microcontroller
C.9 EM78P372KMS10
Figure C-9 EM78P372K 10-pin MSOP Package Type
108
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
EM78P372K
8-bit Microcontroller
C.10 EM78P372KQN16
Figure C-10 EM78P372K 16-pin QFN Package Type
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
109
EM78P372K
8-bit Microcontroller
D Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=245 5 C, for 5 seconds up to the
Solderability
stopper using a rosin-type flux
Step 1: TCT, 65 C (15mins)~150 C (15mins), 10 cycles
Step 2: Bake at 125 C, TD (durance)=24 hrs
Step 3: Soak at 30 C / 60% , TD (durance)=192 hrs
For SMD IC (such as
SOP, QFP, SOJ, etc)
Step 4: IR flow 3 cycles
Pre-condition
(Pkg thickness 2.5mm or
3
Pkg volume 350mm 225 5 C)
(Pkg thickness 2.5mm or
Pkg volume 350mm3 240 5 C )
Temperature cycle test -65 (15mins)~150 C (15mins), 200 cycles
TA =121 C, RH=100%, pressure=2 atm,
Pressure cooker test
TD (durance) = 96 hrs
High temperature /
High humidity test
TA=85 C , RH=85% , TD (durance)=168 , 500 hrs
High-temperature
storage life
TA=150 C, TD (durance)=500, 1000 hrs
High-temperature
operating life
TA=125 C, VCC=Max. operating voltage,
TD (durance) =168, 500, 1000 hrs
TA=25 C, VCC=Max. operating voltage, 800mA/40V
Latch-up
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
°
TA=25 C, ≥ | ± 4KV |
ESD (HBM)
°
TA=25 C, ≥ | ± 400V |
ESD (MM)
VDD-VSS(+),VDD_VSS
(-)mode
D.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise-caused address error is detected, the MCU will repeat execution of the
program until the noise is eliminated. The MCU will then continue to execute the next
program.
110
Product Specification (V1.4) 05.11.2016
(This specification is subject to change without prior notice)
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