EM78P374ND20 [ELAN]
8-Bit Microcontroller;
| 型号： | EM78P374ND20 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller 微控制器 |
| 文件： | 总132页 (文件大小：3767K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P374N
8-Bit Microcontroller
Product
Specification
DOC. VERSION 1.8
ELAN MICROELECTRONICS CORP.
March 2016
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2016 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation 1st Road
Hsinchu Science Park
Hsinchu, TAIWAN 30076
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre 95
How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Elan Information
Technology Group (U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Fax: +852 2723-7780
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
5
6
General Description ......................................................................................1
Features .........................................................................................................1
Pin Configuration (Package).........................................................................2
Pin Description ..............................................................................................3
Functional Block Diagram ............................................................................6
Functional Description..................................................................................7
6.1 Operational Registers .......................................................................................7
6.1.1 R0: IAR (Indirect Addressing Register) ...............................................................7
6.1.2 R1: BSR (Bank Select Control Register).............................................................7
6.1.3 R2: PCL (Program Counter Low) ........................................................................7
6.1.4 R3: SR (Status Register)...................................................................................12
6.1.5 R4: RSR (RAM Select Register) .......................................................................13
6.1.6 Bank 0 R5 ~ R7: (Port 5 ~ Port 7).....................................................................13
6.1.7 Bank 0 R8~RA: .................................................................................................13
6.1.8 Bank 0 RB~RD: (IOCR5 ~ IOCR7) ...................................................................13
6.1.9 Bank 0 RE: OMCR (Operating Mode Control Register)....................................13
6.1.10 Bank 0 RF: IESCR (External Interrupt Edge Select Control Register) .............15
6.1.11 Bank 0 R10: WUCR1 (Wake-up Control Register 1) ........................................15
6.1.12 Bank 0 R11: WUCR2 (Wake-up Control Register 2).........................................15
6.1.13 Bank 0 R12: WUCR3 (Wake-up Control Register 3) ........................................16
6.1.14 Bank 0 R13: (Not used).....................................................................................16
6.1.15 Bank 0 R14: SFR1 (Status Flag Register 1) .....................................................17
6.1.16 Bank 0 R15: SFR2 (Status Flag Register 2) .....................................................18
6.1.17 Bank 0 R16: SFR3 (Status Flag Register 3) .....................................................18
6.1.18 Bank 0 R17: SFR4 (Status Flag Register 4) .....................................................19
6.1.19 Bank 0 R18: SFR5 (Status Flag Register 5) .....................................................19
6.1.20 Bank 0 R1B: IMR1 (Interrupt Mask Register 1) ................................................20
6.1.21 Bank 0 R1C: IMR2 (Interrupt Mask Register 2) ................................................20
6.1.22 Bank 0 R1D IMR3 (Interrupt Mask Register 3) .................................................21
6.1.23 Bank 0 R1E: IMR4 (Interrupt Mask Register 4) ................................................22
6.1.24 Bank 0 R1F: IMR5 (Interrupt Mask Register 5).................................................22
6.1.25 Bank 0 R21: WDTCR (Watchdog Timer Control Register) ...............................23
6.1.26 Bank 0 R22: TCCCR (TCC Control Register)...................................................23
6.1.27 Bank 0 R23: TCCD (TCC Data Register)..........................................................24
6.1.28 Bank 0 R24: TC1CR1 (Timer/Counter 1 Control Register 1)............................24
6.1.29 Bank 0 R25: TC1CR2 (Timer/Counter 1 Control Register 2)............................25
6.1.30 Bank 0 R26: TC1DA (Timer/Counter 1 Data Buffer A) ......................................26
6.1.31 Bank 0 R27: TC1DB (Timer/Counter 1 Data Buffer B)......................................26
6.1.32 Bank 0 R28~R2F: (Not used)............................................................................27
6.1.33 Bank 0 R30: I2CCR1 (I2C Status and Control Register 1) ...............................27
Product Specification (V1.8) 03.15.2016
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Contents
6.1.34 Bank 0 R31: I2CCR2 (I2C Status and Control Register 2) ...............................28
6.1.35 Bank 0 R32: I2CSA (I2C Slave Address Register)............................................29
6.1.36 Bank 0 R33: I2CDB (I2C Data Buffer Register) ................................................29
6.1.37 Bank 0 R34: I2CDAL (I2C Device Address Register) .......................................29
6.1.38 Bank 0 R35: I2CDAH (I2C Device Address Register).......................................29
6.1.39 Bank 0 R36~R3A: (Not used)............................................................................30
6.1.40 Bank 0 R3B: CMP2CR (Comparator 2 Control Register) .................................30
6.1.41 Bank 0 R3C: CMP3CR (Comparator 3 Control Register).................................30
6.1.42 Bank 0 R3D: (Not used) ....................................................................................31
6.1.43 Bank 0 R3E: ADCR1 (ADC Control Register 1)................................................31
6.1.44 Bank 0 R3F: ADCR2 (ADC Control Register 2) ................................................32
6.1.45 Bank 0 R40: ADISR (Analog to Digital Converter Input
Channel Select Register)..................................................................................33
6.1.46 Bank 0 R41: ADER1 (Analog to Digital Converter Input Control Register 1)....34
6.1.47 Bank 0 R42: ADER2 (Analog to Digital Converter Input Control Register 2)....35
6.1.48 Bank 0 R43: ADDL (Low Byte of Analog to Digital Converter Data) .................35
6.1.49 Bank 0 R44: ADDH (High Byte of Analog to Digital Converter Data)................36
6.1.50 Bank 0 R45 ADCVL (Low Byte of Analog to Digital Converter Comparison) ....36
6.1.51 Bank 0 R46 ADCVH (High Byte of Analog to Digital Converter Comparison) ..36
6.1.52 Bank 1 R5 ~ R7: (Not used)..............................................................................36
6.1.53 Bank 1 R8: P5PHCR (Port 5 Pull-high Control Register)..................................37
6.1.54 Bank 1 R9: P6PHCR (Port 6 Pull-high Control Register)..................................37
6.1.55 Bank 1 RA: P7PHCR (Port 7 Pull-high Control Register) .................................38
6.1.56 Bank 1 RB: P5PLCR (Port 5 Pull-low Control Register) ...................................38
6.1.57 Bank 1 RC: P6PLCR (Port 6 Pull-low Control Register)...................................38
6.1.58 Bank 1 RD: P7PLCR (Port 7 Pull-low Control Register)...................................39
6.1.59 Bank 1 RE: P5HDSCR (Port 5 High Drive/Sink Control Register)....................39
6.1.60 Bank 1 RF: P6HDSCR (Port 6 High Drive/Sink Control Register)....................39
6.1.61 Bank 1 R10: P7HDSCR (Port 7 High Drive/Sink Control Register) ..................40
6.1.62 Bank 1 R11: P5ODCR (Port 5 Open-drain Control Register) ...........................40
6.1.63 Bank 1 R12: P6ODCR (Port 6 Open-drain Control Register) ...........................40
6.1.64 Bank 1 R13: P7ODCR (Port 7 Open-drain Control Register) .........................40
6.1.65 Bank 1 R14~R15: (Not used)............................................................................41
6.1.66 Bank 1 R16: PWMSCR (PWM Source Clock Control Register) .......................41
6.1.67 Bank 1 R17: PWMACR (PWMA Control Register) ...........................................41
6.1.68 Bank 1 R18: PRDAL (Low Byte of PWMA Period)............................................42
6.1.69 Bank 1 R19: PRDAH (High Byte of PWMA Period) ..........................................42
6.1.70 Bank 1 R1A: DTAL (Low Byte of PMWA Duty)..................................................42
6.1.71 Bank 1 R1B: DTAH (High Byte of PMWA Duty) ................................................43
6.1.72 Bank 1 R1C: TMRAL (Low Byte of Timer A) .....................................................43
6.1.73 Bank 1 R1D: TMRAH (High Byte of Timer A)....................................................43
6.1.74 Bank 1 R1E: PWMBCR (PWMB Control Register)...........................................43
6.1.75 Bank 1 R1F: PRDBL (Low Byte of PWMB Period) ...........................................44
6.1.76 Bank 1 R20: PRDBH (High Byte of PWMB Period)..........................................44
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Product Specification (V1.8) 03.15.2016
Contents
6.1.77 Bank 1 R21: DTBL (Low Byte of PMWB Duty) .................................................44
6.1.78 Bank 1 R22: DTBH (High Byte of PMWB Duty)................................................44
6.1.79 Bank 1 R23: TMRBL (Low Byte of Timer B)......................................................45
6.1.80 Bank 1 R24: TMRBH (High Byte of Timer B) ....................................................45
6.1.81 Bank 1 R25: PWMCCR (PWMC Control Register)...........................................45
6.1.82 Bank 1 R26: PRDCL (Low Byte of PWMC Period) ...........................................46
6.1.83 Bank 1 R27: PRDCH (High Byte of PWMC Period)..........................................46
6.1.84 Bank 1 R28: DTCL (Low Byte of PMWC Duty).................................................46
6.1.85 Bank 1 R29: DTCH (High Byte of PMWC Duty) ...............................................46
6.1.86 Bank 1 R2A: TMRCL (Low Byte of Timer C).....................................................46
6.1.87 Bank 1 R2B: TMRCH (High Byte of Timer C) ...................................................47
6.1.88 Bank 1 R41 (Reserved).....................................................................................47
6.1.89 Bank 1 R42 (Reserved).....................................................................................47
6.1.90 Bank 1 R43 (Reserved).....................................................................................47
6.1.91 Bank 1 R44 (Reserved).....................................................................................47
6.1.92 Bank 1 R45: TBPTL (Table Pointer Low Register)............................................47
6.1.93 Bank 1 R46: TBPTH (Table Pointer High Register) ..........................................47
6.1.94 Bank 1 R48: PCH (Program Counter High) ......................................................47
6.1.95 Bank 1 R49: LVDCR (Low Voltage Detector Control Register).........................48
6.1.96 Bank 1 R4A~R4C (Reserved)...........................................................................48
6.1.97 Bank 1 R4D (Reserved) ....................................................................................48
6.1.98 Bank 1 R4E (Reserved) ....................................................................................48
6.1.99 Bank 1 R4F (Reserved).....................................................................................48
6.2 TCC/WDT and Prescaler ................................................................................49
6.3 I/O Ports .........................................................................................................50
6.3.1 Usage of Ports 5~6 Input Change Wake-up/Interrupt Function........................52
6.4 Reset and Wake-up Operation........................................................................53
6.4.1 Summary of Wake-up and Interrupt Modes ......................................................55
6.4.2 Status of RST, T, and P of Status Register........................................................57
6.4.3 Summary of Register Initial Values after Reset.................................................58
6.5 Interrupt ..........................................................................................................71
6.6 Analog-to-Digital Converter (ADC)..................................................................73
6.6.1 ADC Data Register............................................................................................74
6.6.2 A/D Sampling Time............................................................................................74
6.6.3 A/D Conversion Time ........................................................................................75
6.6.4 ADC Operation during Sleep Mode...................................................................75
6.6.5 Programming Process/Considerations..............................................................76
6.7 Timer ..............................................................................................................77
6.7.1 Timer/Counter Mode .........................................................................................78
6.7.2 Window Mode....................................................................................................79
6.7.3 Capture Mode....................................................................................................80
Product Specification (V1.8) 03.15.2016
v
Contents
6.7.4 Programmable Divider Output (PDO) Mode and
Pulse Width Modulation (PWM) Mode ..............................................................81
6.7.5 Buzzer Mode .....................................................................................................82
6.8 PWM Module..................................................................................................83
6.8.1 Overview ...........................................................................................................83
6.8.2 Control Register ................................................................................................84
6.8.3 Increment Timer Counter (TMRX: TMRAH/TMRAL, TMRBH/TMRBL,
TMRCH/TMRCL, or TMRDH/TMRDL)..............................................................85
6.8.4 PWM Time Period (PRDX: PRDAL/H, PRDBL/H, PRDCL/H, or PRDDL/H) ....85
6.8.5 PWM Duty Cycle (DTX: DTAH/DTAL, DTBH/DTBL, DTCH/DTCL, or
DTDH/DTDL) ....................................................................................................86
6.8.6 Comparator X....................................................................................................87
6.8.7 PWM Programming Process/Steps...................................................................87
6.9 Comparator.....................................................................................................88
6.9.1 External Reference Signal ................................................................................89
6.9.2 Comparator Outputs..........................................................................................89
6.9.3 Programming the Related Registers.................................................................90
6.9.4 Comparator Interrupt.........................................................................................90
6.9.5 Wake-up from Sleep Mode................................................................................90
6.10 I2C Function....................................................................................................90
6.10.1 7-Bit Slave Address...........................................................................................92
6.10.2 10-Bit Slave Address.........................................................................................93
6.10.3 Master Mode 12C Transmit................................................................................96
6.10.4 Slave Mode 12C Transmit..................................................................................96
6.11 LVD (Low Voltage Detector)............................................................................97
6.11.1 Low Voltage Reset (LVR) ..................................................................................97
6.11.2 Low Voltage Detect ...........................................................................................97
6.12 Oscillator.........................................................................................................99
6.12.1 Oscillator Modes................................................................................................99
6.12.2 Crystal Oscillator/Ceramic Resonators (XTAL).................................................99
6.12.3 Internal RC Oscillator Mode ............................................................................100
6.13 Power-on Considerations..............................................................................101
6.14 External Power-on Reset Circuit...................................................................101
6.15 Residue-Voltage Protection...........................................................................101
6.16 Code Option .................................................................................................102
6.16.1 Code Option Register (Word 0).......................................................................102
6.16.2 Code Option 1 (Word 1) ..................................................................................103
6.16.3 Code Option 2 (Word 2) ..................................................................................104
6.16.4 Code Option 3 (Word 3) ..................................................................................104
6.16.5 Code Option F (Word F).....................................................錯誤! 尚未定義書籤。
6.17 Instruction Set...............................................................................................105
vi
Product Specification (V1.8) 03.15.2016
Contents
7
8
Absolute Maximum Ratings......................................................................108
DC Electrical Characteristics....................................................................109
8.1 AD Converter Characteristics........................................................................ 111
8.2 Comparator Characteristics .......................................................................... 112
8.3 OP Characteristics........................................................................................ 112
8.4 VREF 2V/3V/4V Characteristics.................................................................... 113
AC Electrical Characteristics.............................................................................. 113
9
APPENDIX
A
B
C
Ordering and Manufacturing Information .......................................................... 114
Package Type....................................................................................................... 115
Packaging Configuration .................................................................................... 116
C.1 EM78P374NSS24 150 mil ............................................................................ 116
C.2 EM78P374NSO24 300 mil............................................................................ 117
C.3 EM78P374NK24 300 mil............................................................................... 118
C.4 EM78P374NSS20 209 mil ............................................................................ 119
C.5 EM78P374NSO20 300 mil............................................................................120
C.6 EM78P374ND20 300 mil ..............................................................................121
C.7 EM78P374NSO18 300 mil............................................................................122
C.8 EM78P374ND18...........................................................................................123
Quality Assurance and Reliability ......................................................................124
D.1 Address Trap Detect.....................................................................................124
D
Product Specification (V1.8) 03.15.2016
vii
Contents
Specification Revision History
Doc. Version
Revision Description
Date
1.0
Initial version
2011/04/26
1. Modified the Features
2. Modified the AD description
3. Modified the DC and AC Electrical Characteristics
4. Deleted VREFN
1.1
2011/08/17
1.2
1.3
1. Modified the Code Option Word 0 and Word 2
2012/08/30
2013/01/22
1. Added LVR specification in the DC Electrical
Characteristics section
1. Removed the dead time register from Section 6.8.2
2. Removed dead time from Figure 6-13a
3. Modified VIH/VIL in Section 8
1.4
1.5
1.6
2014/01/06
2014/08/27
2015/09/16
1. Modified the discription of Section 6.2
2. Modified Code Option 0-HLP in Section 6.16.1
3. Modified Code Option 1-C5~C0 in Section 6.16.2
4. Modified Code Option 2-SC3~SC0 in Section 6.16.3
1. Modified the name of the package type
2. Modified Section 6.8.2
3. Removed deadtime description from Section 6.8.7
1. Modified the drecription of Code Option 0-HLP in
Section 6.16.1
1.7
1.8
2015/10/07
2016/03/15
2. Modified the drecription of Code Option 0-LVR1~0 in
Section 6.16.1
Modified the Features and APPENDIX
viii
Product Specification (V1.8) 03.15.2016
EM78P374N
8-bit Microcontroller
1 General Description
The EM78P374N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS
technology. It is used for 15 bits kernel simulation and it simulates the 4K15-bit programmable ROM and
3048-bit In-system programmable SRAM. Using the ICE370N, users can develop their program for
ELAN’s several OTP types of IC.
2 Features
.
CPU Configuration
Drift Rate
Voltage
Internal RC
Frequency
Support 4K15 bits program ROM
Temperature
(-40C~+85C)
± 2%
Process
Total
± 4%
± 4%
± 4%
± 4%
3048 bits on-chip registers (SRAM)
More than 10 years data retention
8-level stacks for subroutine nesting
Dual clock operation mode
Four programmable Level Voltage Detector
(LVD) : 4.5V, 4V, 3.3V, 2.2V
(2.5V~5.5V)
1 MHz
4 MHz
8 MHz
16 MHz
± 1%
± 1%
± 1%
± 1%
± 1%
± 1%
± 1%
± 1%
± 2%
± 2%
± 2%
Sub Clock
IRC mode: 16kHz/32kHz
Four programmable Level Voltage Reset
(LVR) : 4.0V, 3.5V, 2.7V, 1.8V (POR)
.
Peripheral Configuration
Power on reset level Voltage: 1.8V~1.9V
Less than 1.0 mA at 5V/4MHz
Typically 15 A, at 3V/16kHz
Typically 2 A, during sleep mode
Four operation modes
8-bit real time clock/counter (TCC) with selective
signal sources and trigger edges
14+2-channels Analog-to-Digital Converter with
12-bit resolution+ 1 internal reference for Vref+.
One 8-bit Timer/Counter
Mode
Sleep mode
Idle Mode
Green mode
Normal mode Turn on
CPU Main clock Sub clock
TC1:
Turn off
Turn off
Turn on
Turn off
Turn off
Turn off
Turn on
Turn off
Turn on
Turn on
Turn on
Timer/Counter/capture//window/buzzer/PWM/PDO
(programmable divider output) Mode selection
External interrupt wake-up. Function: rising or
falling edge interrupt
.
I/O Port Configuration
6 bi-directional I/O ports : P5, P6 and P7
22 I/O pins
I2C-bus available. Function; 7/10-bit address,
8-bit data transmit/receive mode
22 Programmable open-drain I/O pins
21 programmable pull-high I/O pins
21 programmable pull-down I/O pins
21 programmable high sink/drive I/O pins
External interrupt : INT0
Port 56 input status change wake-up
Three 16 bits PWM
One Comparator/OP
.
.
16 available interrupts
Special Features
.
.
Operating voltage range:
Programmable free running watchdog timer
High ESD immunity
Power saving Sleep mode
Selectable Oscillation mode
2.1V~5.5V at 0~70C (commercial)
2.3V~5.5V at -40~85C (industrial)
Operating frequency range:
Crystal/IRC/ERC oscillation circuit selected by
code option for system clock
.
Package types:
IRC oscillation circuit selected by code option
18 pin DIP 300mil
18 pin SOP 300mil
20 pin DIP 300mil
20 pin SOP 300mil
20 pin SSOP 209mil
:EM78P374ND18
:EM78P374NSO18
:EM78P374ND20
:EM78P374NSO20
:EM78P374NSS20
for sub clock
Main Clock
Crystal mode:
DC ~ 16 MHz at 5~5.5V
DC ~ 8 MHz at 3~5.5V
DC ~ 4 MHz at 2.1V~5.5V
24 pin skinny DIP 300mil :EM78P374NK24
24 pin SOP 300mil
24 pin SSOP 150mil
:EM78P374NSO24
:EM78P374NSS24
IRC mode:
DC ~ 16 MHz at 5~5.5V
DC ~ 8 MHz/2clks at 3V~5.5V
DC ~ 4 MHz/2clks at 2.1V~5.5V
Note: These are Green product which do not contain
hazardous substances
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
1
EM78P374N
8-bit Microcontroller
3 Pin Configuration (Package)
P73/ADC11/SDA
1
2
24
23
22
21
20
19
18
17
16
15
14
13
P74/ADC12
P75/ADC13
P72/ADC10/SCL
P71/ADC9
P71/ADC9
P51/ADC1/TC1
P50/ADC0
P52/ADC2/PWMA
P53/ADC3/PWMB
1
2
20
19
18
17
16
15
14
13
12
11
3
P52/ADC2/PWMA
P53/ADC3/PWMB
P51/ADC1/TC1
P50/ADC0
4
3
P55/ADC5
5
P55/ADC5
P56/ADC6/OSCO
4
P70/TCC/Verf/ADC8
P67//RESET
Vss
P70/TCC/Verf/ADC8
6
P56/ADC6/OSCO
P57/ADC7/OSCI/RCOUT
VDD
P57/ADC7/OSCI/RCOUT
VDD
5
7
P67//RESET
Vss
6
8
P66/INT5
P65/PWMA1
P64/PWMB1
P63/PWMC1
7
P54/ADC4/PWMC
P60/C2-
9
P66/INT5
P65/PWMA1
P64/PWMB1
P63/PWMC1
P54/ADC4/PWMC
P60/C2-
8
10
11
12
9
P61/C2+/SCL
P62/CO2/SDA
P61/C2+/SCL
P62/CO2/SDA
10
Figure 3-1a 24-Pin DIP/SOP/SSOP Pin Assignment
Figure 3-1b 20-Pin DIP/SOP/SSOP Pin Assignment
P51/ADC1/TC1
P50/ADC0
18
17
16
15
14
13
12
11
10
P53/ADC3/PWMB
P55/ADC5
1
2
3
4
5
6
7
P70/TCC/Verf/ADC8
P56/ADC6/OSCO
P57/ADC7/OSCI/RCOUT
VDD
P67//RESET
Vss
P66/INT5
P65/PWMA1
P64/PWMB1
P63/PWMC1
P54/ADC4/PWMC
P60/C2-
P61/C2+/SCL
P62/CO2/SDA
8
9
Figure 3-1c 18-Pin DIP/SOP Pin Assignment
2
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
4 Pin Description
Input
Type
Output
Type
Pin Name
Function
Description
Bidirectional I/O pin with programmable pull-down,
P50
ADC0
P51
ST
AN
ST
AN
CMOS pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P50/ADC0
-
ADC Input 0
Bidirectional I/O pin with programmable pull-down,
CMOS pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P51/ADC1/
TC1
ADC1
-
ADC Input 1
Timer 1 clock input, capture input (TC1CAP), window
input (TC1W), programmable divider output (PDO),
pulse-width-modulation (PWM1), and buzzer ouput
(BUZ)
TC1
P52
ST
ST
CMOS
Bidirectional I/O pin with programmable pull-down,
CMOS pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P52/ADC2/
PWMA
ADC2
AN
-
-
ADC Input 2
CMOS PWMA output
Bidirectional I/O pin with programmable pull-down,
PWMA
P53
ST
CMOS pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P53/ADC3/
PWMB
ADC3
AN
-
-
ADC Input 3
CMOS PWMB output
Bidirectional I/O pin with programmable pull-down,
PWMB
P54
ST
CMOS pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P54/ADC4/
PWMC
ADC4
AN
-
-
ADC Input 4
CMOS PWMC output
Bidirectional I/O pin with programmable pull-down,
PWMC
P55
ADC5
P56
ST
AN
ST
CMOS pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P55/ADC5
-
ADC Input 5
Bidirectional I/O pin with programmable pull-down,
CMOS pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P56/ADC6/
OSCO
ADC6
AN
-
-
ADC Input 6
OSCO
XTAL
Clock output of crystal/resonator oscillator
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
3
EM78P374N
8-bit Microcontroller
(Continuation)
Output
Type
Pin Name Function Input Type
Description
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P57
ST
CMOS
P57/ADC7/
OSCI/
RCOUT
ADC7
OSCI
AN
XTAL
-
-
ADC Input 7
-
Clock input of crystal/ resonator oscillator
Clock output of internal RC oscillator
RCOUT
CMOS
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P60
ST
AN
ST
CMOS
-
P60/C2-
C2-
Inverting end of Comparator 2 / OP2
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P61
CMOS
P61/C2+/
SCL
C2+
SCL
AN
ST
-
Non-inverting end of Comparator 2/OP2
I2C serial clock input/output (SCL)
CMOS
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P62
ST
CMOS
P62/CO2/
SDA
CO2
SDA
-
CMOS
CMOS
Output of Comparator 2
I2C serial data input/output (SDA)
ST
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, high drive, and pin
change wake-up.
P63
PWMC1
P64
ST
-
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
-
P63/
PWMC1
PWMC1 ouput (complementary PWM)
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, high drive, and pin
change wake-up
ST
-
P64/
PWMB1
PWMB1
P65
PWMB1 ouput (complementary PWM)
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, high drive, and pin
change wake-up.
ST
-
P65/
PWMA1
PWMA1
P66
PWMA1 ouput (complementary PWM)
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, high drive, and pin
change wake-up.
ST
ST
ST
ST
P66/INT
INT
External interrupt pin
Bidirectional I/O pin with programmable pull-down,
high sink, and pin change wake-up. It is always
open-drain
P67
CMOS
-
P67/
/RESET
/RESET
Reset pin
4
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
(Continuation)
Input
Type
Output
Type
Pin Name
Function
Description
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, and high drive.
P70
ST
CMOS
P70/TCC/
Verf/ADC8
TCC
VREF
ADC8
ST
AN
AN
-
-
-
Real Time Clock/Counter clock input
ADC external voltage reference
ADC Input 8
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, and high drive.
P71
ADC9
P72
ST
AN
ST
CMOS
-
P71/ADC9
ADC Input 9
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, and high drive.
CMOS
P72/ADC10/
SCL
ADC10
SCL
AN
ST
-
ADC Input 10
I2C serial clock input/output (SCL)
CMOS
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, and high drive.
P73
ST
CMOS
P73/ADC11/
SDA
ADC11
SDA
AN
ST
-
ADC Input 11
I2C serial data input/output (SDA)
CMOS
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, and high drive.
P74
ADC12
P75
ST
AN
ST
CMOS
-
P74/ADC12
P75/ADC13
ADC Input 12
Bidirectional I/O pin with programmable pull-down,
pull-high, open-drain, high sink, and high drive.
CMOS
ADC13
VDD
AN
-
-
-
ADC Input 13
Power supply pin
Ground
VDD
VSS
Power
Power
VSS
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
5
EM78P374N
8-bit Microcontroller
5 Functional Block Diagram
P5
Start-up
timer
Ext.
OSC.
PC
Int. RC
ROM
P50
P51
P52
P53
P54
P55
P56
P57
WDT
TC3
TC3
TCC
Oscillation
Generation
Instruction
Register
8-level
stack
TCC
PWMA~C
/PWMA~C
PWMA~C
Sub
P6
Reset
Int. RC
Instruction
Decoder
P60
P61
P62
P63
P64
P65
P66
P67
C1+
C1-
CO1
Mux.
CMP1/O
P1
ALU
LVD
I2C
SDL, SDA
ADin0~7
R4
P7
ADC
P70
P71
P72
P73
P74
RAM
Interrupt
control
circuit
R3(Status
Reg.)
P75
ACC
LVR
Port5,6
pins
Ext INT0
change
Figure 5-1 EM78P374N Functional Block Diagram
6
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6 Functional Description
6.1 Operational Registers
6.1.1 R0: IAR (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect addressing pointer. Any instruction using R0 as a pointer actually accesses
data pointed by the RAM Select Register (R4).
6.1.2 R1: BSR (Bank Select Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
SBS0
R/W
Bit 3
Bit 2
GBS2
R/W
Bit 1
GBS1
R/W
Bit 0
GBS0
R/W
-
-
-
-
-
-
-
-
Bits 7 ~ 5:
Not used, set to “0” all the time.
Bit 4 (SBS0): Special register bank select bit. It is used to select Bank 0/1 of Special
Registers R5~R4F.
0: Bank 0
1: Bank 1
Bit 3:
Not used, fixed to “0” all the time.
Bits 2 ~ 0 (GBS2 ~ GBS0): General register bank select bit. It is used to select
Banks 0~7 of General Registers R80~RFF.
GBS2
GBS1
GBS0
RAM Bank
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
6.1.3 R2: PCL (Program Counter Low)
Bit 7
PC7
R/W
Bit 6
PC6
R/W
Bit 5
PC5
R/W
Bit 4
PC4
R/W
Bit 3
PC3
R/W
Bit 2
PC2
R/W
Bit 1
PC1
R/W
Bit 0
PC0
R/W
Bits 7 ~ 0 (PC7~PC0): Low byte of the program counter.
Depending on the device type, R2 and hardware stack are 14-bit
wide. The structure is depicted in Figure 6-1.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
7
EM78P374N
8-bit Microcontroller
Generates 4K15 bits on-chip Flash ROM addresses to the relative
programming instruction codes. One program page is 4096 words
long.
R2 is set as all "0"s when under reset condition.
“JMP” instruction allows direct loading of the lower 12 program
counter bits. Thus, “JMP” allows the PC to go to any location within a
page.
“CALL” instruction loads the lower 12 bits of the PC, and the current
PC value will be incremented by 1 and is pushed onto the stack.
Thus, the subroutine entry address can be located anywhere within a
page.
“LJMP” instruction allows direct loading of the lower 15 program
counter bits. Therefore, “LJMP” allows the PC to jump to any location
within 4K (212).
“LCALL” instruction loads the lower 15 bits of the PC, and PC+1 are
pushed onto the stack. Thus, the subroutine entry address can be
located anywhere within 4K (212).
“RET” (“RETL k”, “RETI”) instruction loads the program counter with
the contents of the top-level stack.
“ADD R2, A” allows a relative address to be added to the current PC,
and the ninth and above bits of the PC will increase progressively.
“MOV R2, A” allows to load an address from the “A” register to the
lower 8 bits of the PC, and the ninth and above bits of the PC will
remain unchanged.
Any instruction, except “ADD R2,A” that is written to R2 (e.g., “MOV
R2, A”, “BC R2, 6”,etc.) will cause the ninth bit and the above bits
(A8~A12) of the PC to remain unchanged.
All instructions are single instruction cycle (Fsys/2), except “LCALL”
and “LJMP” instructions. The “LCALL” and “LJMP” instructions need
two instruction cycles.
8
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
A13
~
A0
PC
0000h
0002h
0004h
0006h
0008h
000Ah
Reset vector
INT interrupt vector
pin change interrupt vector
TCC interrupt vector
LVD interrupt vector
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
000Ch
000Eh
0010h
0012h
0014h
0016h
0018h
001Ah
001Ch
001Eh
0020h
0022h
0024h
0026h
0028h
002Ah
002Ch
CMP2 interrupt vector
AD interrupt vector
TC1 interrupt vector
PWMPA interrupt vector
PWMDA interrupt vector
I2C Tx interrupt vector
I2C Rx interrupt vector
I2Cstop interrupt vector
PWMPB interrupt vector
PWMDB interrupt vector
PWMPC interrupt vector
PWMDC interrupt vector
On-chip Program Memory
7FFFh
Figure 6-1 EM78P374N Program Counter Organization
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
9
EM78P374N
8-bit Microcontroller
Data Memory Configuration
Address
Bank 0
Bank 1
0X00
0X01
0X02
0X03
0X04
0X05
0X06
0X07
0X08
0X09
0X0A
0x0B
0X0C
0X0D
0X0E
0X0F
0X10
0X11
0X12
0X13
0X14
0X15
0X16
0X17
0X18
0X19
0X1A
0X1B
0X1C
0X1D
0X1E
0X1F
0X20
0X21
0X22
0X23
0X24
0X25
0X26
0X27
0X28
0X29
0X2A
0x2B
IAR (Indirect Addressing Register)
BSR (Bank Select Control Register)
PC (Program Counter)
-
SR (Status Register)
RSR (RAM Select Register)
Port 5
-
-
Port 6
Port 7
-
-
P5PHCR
P6PHCR
P7PHCR
P5PLCR
P6PLCR
P7PLCR
P5HDSCR
P6HDSCR
P7HDSCR
P5ODCR
P6ODCR
P7ODCR
-
-
-
IOC5
IOC6
IOC7
OMCR (Operating Mode Control Reg.)
IESCR
WUCR1
WUCR2
WUCR3
-
SFR1 (Status Flag Register 1)
SFR2 (Status Flag Register 2)
-
SFR3 (Status Flag Register 3)
PWMSCR
PWMACR
PRDAL
PRDAH
DTAL
SFR4 (Status Flag Register 4)
SFR5 (Status Flag Register 5)
-
-
IMR1 (Interrupt Mask Register 1)
DTAH
IMR2 (Interrupt Mask Register 2)
TMRAL
TMRAH
PWMBCR
PRDBL
PRDBH
DTBL
IMR3 (Interrupt Mask Register 3)
IMR4 (Interrupt Mask Register 4)
IMR5 (Interrupt Mask Register 5)
-
WDTCR
TCCCR
DTBH
TCCD
TMRBL
TMRBH
PWMCCR
PRDCL
PRDCH
DTCL
TC1CR1
TC1CR2
TC1DA
TC1DB
-
-
-
-
DTCH
TMRCL
TMRCH
10
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
(Continuation)
Address
Bank 0
Bank 1
0X2C
0X2D
0X2E
0X2F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0X30
0X31
0X32
0X33
0X34
0X35
0X36
0X37
0X38
0X39
0X3A
0x3B
0X3C
0X3D
0X3E
0X3F
0X40
0X41
0X42
0X43
0X44
0X45
0X46
0X47
0X48
0X49
0X4A
0x4B
0X4C
0X4D
0X4E
0X4F
0X50
0X51
:
I2CCR1
I2CCR2
I2CSA
I2CDB
I2CDAL
I2CDAH
-
-
-
-
-
CMP2CR
CMP3CR
-
ADCR1
ADCR2
ADISR
ADER1
ADER2
ADDL
ADDH
ADCVL
ADCVH
Unused
TBPTL
TBPTH
STKMON
-
-
-
-
-
-
-
-
PCH
LVDCR
-
-
-
-
-
-
General Purpose Register
:
0X7F
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
11
EM78P374N
8-bit Microcontroller
(Continuation)
Address
Bank 0
Bank 1
0X80
0X81
:
Bank 0
Bank 1
:
:
0XFE
0XFF
6.1.4 R3: SR (Status Register)
Bit 7
INT
F
Bit 6
Bit 5
Bit 4
T
Bit 3
P
Bit 2
Bit 1
DC
Bit 0
C
-
-
-
-
Z
R/W
R/W
R/W
R/W
R/W
Bit 7 (INT):Interrupt Enable flag
0: Interrupt masked by DISI or hardware interrupt
1: Interrupt enabled by ENI/DISI instructions
Bits 6 ~ 5: Not used, set to “0” all the time.
Bit 4 (T): Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up.
Reset to “0” by WDT time-out.
Bit 3 (P): Power down bit
Set to “1” during power on or by a "WDTC" command
Reset to “0” by a "SLEP" command.
Bit 2 (Z): Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
12
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.5 R4: RSR (RAM Select Register)
Bit 7
RSR7
R/W
Bit 6
RSR6
R/W
Bit 5
RSR5
R/W
Bit 4
RSR4
R/W
Bit 3
RSR3
R/W
Bit 2
RSR2
R/W
Bit 1
RSR1
R/W
Bit 0
RSR0
R/W
Bits 7 ~ 0 (RSR7 ~ RSR0): These bits are used to select registers (Address: 00~FF) in
the indirect address mode. For more details, refer to the table on Data
Memory Configuration in Section 6.1.3, R2: PCL (Program Counter
Low).
6.1.6 Bank 0 R5 ~ R7: (Port 5 ~ Port 7)
R5, R6 and R7 are I/O data registers.
6.1.7 Bank 0 R8~RA:
(Not used. Set to “0” all the time)
6.1.8 Bank 0 RB~RD: (IOCR5 ~ IOCR7)
These registers are used to control I/O port direction. They are both
readable and writable.
0: Put the relative I/O pin as output
1: Put the relative I/O pin into high impedance
6.1.9 Bank 0 RE: OMCR (Operating Mode Control Register)
Bit 7
CPUS
R/W
Bit 6
IDLE
R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RCM1
R/W
Bit 0
RCM0
R/W
-
-
-
-
-
-
-
-
Bit 7 (CPUS): CPU Oscillator Source Select
0: Fs: sub-oscillator
1: Fm: main-oscillator
When CPUS=0, the CPU oscillator selects the sub-oscillator and the
main oscillator is stopped.
Bit 6 (IDLE): Idle Mode Enable Bit. This bit determines which mode (see figure
below) is to be activated after SLEP instruction.
0: “IDLE=0”+SLEP instruction Sleep mode
1: “IDLE=1”+SLEP instruction Idle mode
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
13
EM78P374N
8-bit Microcontroller
Code option
HLFS=1
RESET
Normal mode
Fm: oscillation
Fs: oscillation
CPU: using Fm
Code option
HLFS=0
wakeup
Interrupt or
wakeup
IDLE=0
+ SLEP
CPUS=1
CPUS=0
IDLE=1
+ SLEP
IDLE=1
+ SLEP
wakeup
Idle mode (*)
Fm: stop
Sleep mode
Fm: stop
Green mode
Fm: stop
Fs: stop
CPU: stop
Fs: oscillation
CPU: using Fs
Fs: oscillation
CPU: stop
Interrupt or
wakeup
IDLE=0
+ SLEP
Switching operation mode at Idle Normal, Idle Green:
*
If the clock source of timer is Fs, the timer/counter must continue to count in Idle mode. When
the matching condition of the timer/counter occurs during Idle mode, the interrupt flag of
timer/counter will be active. However, the MCU will jump to interrupt vector when the
corresponding interrupt is enabled.
Figure 6-2 CPU Operation Mode
Oscillation Characteristics
Oscillation Mode
CPU Mode Switch
Waiting Time before CPU Starts to Work
WSTO + 510 clocks (main frequency)
WSTO + 510 clocks (main frequency)
WSTO + 510 clocks (main frequency)
WSTO + 8 clocks (sub frequency)
WSTO + 8 clocks (sub frequency)
WSTO + 8 clocks (main frequency)
WSTO + 8 clocks (main frequency)
WSTO + 8 clocks (main frequency)
WSTO + 8 clocks (sub frequency)
WSTO + 8 clocks (sub frequency)
WSTO: Waiting time of Start-to-Oscillation
Sleep Normal
Idle Normal
Green Normal
Sleep Green
Idle Green
Crystal Mode
Sleep Normal
Idle Normal
Green Normal
Sleep Green
Idle Green
IRC Mode
Bits 5 ~ 3:
Not used. Set to “0” all the time
Bits 2 ~ 1 (RCM1 ~ RCM0): Internal RC mode selection bits
RCM1
RCM0
Frequency (MHz)
0
0
1
1
0
1
0
1
1
8
16
4
14
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.10 Bank 0 RF: IESCR (External Interrupt Edge Select Control
Register)
Bit 7
Bit 6
Bit 5
EIES54
R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit 5 (EIES54):
External interrupt edge select bit
0: Falling edge interrupt
1: Rising edge interrupt
6.1.11 Bank 0 R10: WUCR1 (Wake-up Control Register 1)
Bit 7
CMP2WK
R/W
Bit 6
Bit 5
LVDWK
R/W
Bit 4
ADWK
R/W
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
Bit 7 (CMP2WK): Comparator 2 Wake-up Enable bit
0: Disable Comparator 2 wake-up.
1: Enable Comparator 2 wake-up.
Bit 6:
Not used. Set to “0” all the time.
Bit 5 (LVDWK): Low Voltage Detect Wake-up Enable bit
0: Disable Low Voltage Detect wake-up.
1: Enable Low Voltage Detect wake-up.
Bit 4 (ADWK):
A/D Converter Wake-up Function Enable bit
0: Disable AD converter wake-up
1: Enable AD converter wake-up
When the AD Complete status is used to enter an interrupt vector or
to wake-up IC from Sleep/Idle mode with AD conversion running,
the ADWK bit must be set to “Enable“.
Bits 3 ~ 0:
Not used. Set to “0” all the time
6.1.12 Bank 0 R11: WUCR2 (Wake-up Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
I2CWK
R/W
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7 ~ 3:
Not used. Set to “0” all the time.
Bit 2 (I2CWK):
I2C wake-up enable bit. It is available when I2C works in Slave
mode.
0: Disable
1: Enable
Bits 1 ~ 0:
Not used. Set to “0” all the time.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
15
EM78P374N
8-bit Microcontroller
6.1.13 Bank 0 R12: WUCR3 (Wake-up Control Register 3)
Bit 7
Bit 6
Bit 5
ICWKP6 ICWKP5
R/W R/W
Bit 4
Bit 3
Bit 2
Bit 1
INTWK5
R/W
Bit 0
-
-
-
-
-
-
-
-
-
-
Bits 5 ~ 4 (ICWKP6 ~ 5): (Ports 6 ~ 5) Pin-change Wake-up Function Enable Bit
0: Disable external interrupt wake-up
1: Enable external interrupt wake-up
When the External Interrupt status change is used to enter an
interrupt vector or to wake-up the IC from Sleep/Idle, the INTWK bits
must be set to “Enable”.
Pin Change Wake-up Function Enable
CPU Mode
Normal / Green
Sleep / Idle
Global interrupt
DISI
ENI
DISI
+
ENI
ICIE = 0
Next instruction
(ICSF=1 or 0)
Next instruction
(ICSF=1 or 0)
Wake up (ICSF=1)
Next instruction
Wake up (ICSF=1)
ICIE = 1
Next instruction
(ICSF=1 or 0)
Interrupt vector
(ICSF=1)
Wake up (ICSF=1)
Next instruction
Wake up (ICSF=1)
+
If the Pin Change Wake-up function is disabled, the ICSF is always equals to “0”.
When the ICSF is equal to “1”, the MCU will wake-up from Sleep or Idle mode. If ICSF is equal
to “0”, pin change condition does NOT occur. Hence, the MCU will NOT be awakened by pin
change.
Bits 7 ~ 6, 3 ~ 2, 0: Not used. Set to “0” all the time.
Bit 1 (INTWK5): External Interrupt (INT pin) Wake-up Function Enable bit
0: Disable external interrupt wake-up
1: Enable external interrupt wake-up
When the External Interrupt status change is used to enter an
interrupt vector or to wake-up the MCU from Sleep/Idle mode, the
EXWE bits must be set to “Enable“.
6.1.14 Bank 0 R13:
(Not used. Set to “0” all the time)
16
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.15 Bank 0 R14: SFR1 (Status Flag Register 1)
Bit 7
CMP2SF
F
Bit 6
Bit 5
LVDSF
F
Bit 4
ADSF
F
Bit 3
Bit 2
Bit 1
Bit 0
TCSF
F
-
-
-
-
-
-
-
-
Each corresponding status flag is set to “1” when interrupt condition is triggered.
Bit 7 (CMP2SF): Comparator 2 status flag. Set when a change occurs in the output of
Comparator 2. Reset by software.
Bit 6:
Not used. Set to “0” all the time.
Bit 5 (LVDSF): Low Voltage Detector status flag:
LVDS2, LVDS1,
LVD Voltage
Interrupt Level
LVDEN
LVDS0
LVDSF
1
1
1
1
0
011
010
001
000
XX
2.2V
3.3V
4.0V
4.5V
NA
1*
1*
1*
1*
0
* If Vdd crossovers at the LVD voltage interrupt level as Vdd varies,
LVDSF =1.
Bit 4 (ADSF):
Status flag for analog to digital conversion. Set when AD conversion
is completed. Reset by software.
Bits 3 ~ 1:
Not used. Set to “0” all the time.
Bit 0 (TCSF):
TCC overflow status flag. Set when TCC overflows. Reset by
software.
NOTE
If a function is enabled, the corresponding status flag will be active regardless whether
the interrupt mask is enabled or not.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
17
EM78P374N
8-bit Microcontroller
6.1.16 Bank 0 R15: SFR2 (Status Flag Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1DSF
F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Each corresponding status flag is set to “1” when interrupt condition is triggered.
Bits 7 ~ 1: Not used. Set to “0” all the time.
Bit 0 (TC1DSF): 8-bit Timer/Counter 1 status flag. Clear by software.
NOTE
If a function is enabled, the corresponding status flag will be active regardless whether
the interrupt mask is enabled or not.
6.1.17 Bank 0 R16: SFR3 (Status Flag Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
PWMCPSF PWMCDSF PWMBPSF PWMBDSF PWMAPSF PWMADSF
F
F
F
F
F
F
Bits 7 ~ 6:
Not used. Set to “0” all the time.
Bit 5 (PWMCPSF): Status flag of period-matching for PWMC (Pulse Width Modulation).
Set when a selected period is reached. Reset by software.
Bit 4 (PWMCDSF): Status flag of duty-matching for PWMC (Pulse Width Modulation).
Set when a selected duty is reached. Reset by software.
Bit 3 (PWMBPSF): Status flag of period-matching for PWMB (Pulse Width Modulation).
Set when a selected period is reached. Reset by software.
Bit 2 (PWMBDSF): Status flag of duty-matching for PWMB (Pulse Width Modulation).
Set when a selected duty is reached. Reset by software.
Bit 1 (PWMAPSF): Status flag of period-matching for PWMA(Pulse Width Modulation).
Set when a selected period is reached. Reset by software.
Bit 0 (PWMADSF): Status flag of duty-matching for PWMA (Pulse Width Modulation).
Set when a selected duty is reached. Reset by software.
NOTE
If a function is enabled, the corresponding status flag will be active regardless whether
the interrupt mask is enabled or not.
18
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.18 Bank 0 R17: SFR4 (Status Flag Register 4)
Bit 7
Bit 6
Bit 5
P6ICSF
F
Bit 4
P5ICSF
F
Bit 3
Bit 2
Bit 1
Bit 0
I2CTSF
F
-
-
-
-
-
-
I2CSTPSF I2CRSF
F
F
Bits 7 ~ 6:
Not used. Set to “0” all the time.
Bit 5 (P6ICSF):
Bit 4 (P5ICSF):
Bit 3:
Port 6 status flag. Flag is cleared by software.
Port 5 status flag. Flag is cleared by software.
Not used. Set to “0” all the time.
Bit 2 (I2CSTPSF): I2C stop status flag. Set when I2C stop signal occurs.
Bit 1 (I2CRSF):
I2C receive status flag. Set when I2C receives 1 byte data and
responds with an ACK signal. Reset by firmware or disable I2C.
Bit 0 (I2CTSF):
I2C transmit status flag. Set when I2C transmits 1 byte data and
receives a handshake signal (ACK or NACK). Reset by firmware or
disable I2C.
NOTE
If a function is enabled, the corresponding status flag will be active regardless whether
the interrupt mask is enabled or not.
6.1.19 Bank 0 R18: SFR5 (Status Flag Register 5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EXSF5
F
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Each corresponding status flag is set to “1” when interrupt condition is triggered.
Bits 7 ~ 4, 2 ~ 0: Not used. Set to “0” all the time.
Bit 3 (EXSF5):
External interrupt status flag
Enable
INT Pin
Digital Noise
Reject
Edge
Condition
INTX
(ENI+) EXIEX Rising or Falling
8/Fc or 32/Fc
NOTE
If a function is enabled, the corresponding status flag will be active regardless whether
the interrupt mask is enabled or not.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
19
EM78P374N
8-bit Microcontroller
6.1.20 Bank 0 R1B: IMR1 (Interrupt Mask Register 1)
Bit 7
Bit 6
Bit 5
LVDIE
R/W
Bit 4
ADIE
R/W
Bit 3
Bit 2
Bit 1
Bit 0
TCIE
R/W
CMP2IE
R/W
-
-
-
-
-
-
-
Bit 7 (CMP2IE): CMP2SF interrupt enable bit
0: Disable CMP2SF interrupt
1: Enable CMP2SF interrupt
When the Comparator output status change is used to enter interrupt
vector, the CMP2IE bit must be set to “Enable”.
Bit 6:
Not used. Set to “0” all the time.
Bit 5 (LVDIE): LVDSF interrupt enable bit
0: Disable LVDSF interrupt
1: Enable LVDSF interrupt
Bit 4 (ADIE):
ADSF interrupt enable bit
0: Disable ADSF interrupt
1: Enable ADSF interrupt.
Not used. Set to “0” all the time.
TCSF interrupt enable bit.
0: Disable TCSF interrupt
1: Enable TCSF interrupt
Bits 3~1:
Bit 0 (TCIE):
NOTE
If the interrupt mask is enabled, the program counter would jump into the corresponding
interrupt vector when the corresponding status flag is set.
6.1.21 Bank 0 R1C: IMR2 (Interrupt Mask Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1DIE
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7 ~ 1:
Not used. Set to “0” all the time.
Bit 0 (TC1DIE): Interrupt enable bit
0: Disable TC1DSF interrupt
1: Enable TC1DSF interrupt
NOTE
If the interrupt mask is enabled, the program counter would jump into the corresponding
interrupt vector when the corresponding status flag is set.
20
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.22 Bank 0 R1D IMR3 (Interrupt Mask Register 3)
Bit 7
Bit 6
Bit 5
PWMCPIE PWMCDIE PWMBPIE PWMBDIE PWMAPIE PWMADIE
R/W R/W R/W R/W R/W R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
Bits 7 ~ 6:
Not used. Set to “0” all the time.
Bit 5 (PWMCPIE): PWMCPSF interrupt enable bit
0: Disable period-matching of PWMC interrupt
1: Enable period-matching of PWMC interrupt
Bit 4 (PWMCDIE): PWMCDSF interrupt enable bit
0: Disable duty-matching of PWMC interrupt
1: Enable duty-matching of PWMC interrupt
Bit 3 (PWMBPIE): PWMBPSF interrupt enable bit
0: Disable period-matching of PWMB interrupt
1: Enable period-matching of PWMB interrupt
Bit 2 (PWMBDIE): PWMBDSF interrupt enable bit
0: Disable duty-matching of PWMB interrupt
1: Enable duty-matching of PWMB interrupt
Bit 1 (PWMAPIE): PWMAPSF interrupt enable bit
0: Disable period-matching of PWMA interrupt
1: Enable period-matching of PWMA interrupt
Bit 0 (PWMADIE): PWMADSF interrupt enable bit.
0: Disable duty-matching of PWMA interrupt
1: Enable duty-matching of PWMA interrupt
NOTE
If the interrupt mask is enabled, the program counter would jump into the corresponding
interrupt vector when the corresponding status flag is set.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
21
EM78P374N
8-bit Microcontroller
6.1.23 Bank 0 R1E: IMR4 (Interrupt Mask Register 4)
Bit 7
Bit 6
Bit 5
P6ICIE
R/W
Bit 4
P5ICIE
R/W
Bit 3
Bit 2
I2CSTPIE I2CRIE
R/W R/W
Bit 1
Bit 0
I2CTIE
R/W
-
-
-
-
-
-
Bits 7 ~ 6:
Not used. Set to “0” all the time.
Bit 5 (P6ICIE):
Bit 4 (P5ICIE):
Bit 3:
Port 6 pin-change Interrupt Enable bit
0: Disable P6ICSF interrupt
1: Enable P6ICSF interrupt
Port 5 pin-change Interrupt Enable bit
0: Disable P5ICSF interrupt
1: Enable P5ICSF interrupt
Not used. Set to “0” all the time.
Bit 2 (I2CSTPIE): I2C stop interrupt enable bit
0: Disable interrupt
1: Enable interrupt
Bit 1 (I2CRIE): I2C Interface Rx Interrupt Enable bit
0: Disable interrupt
1: Enable interrupt
Bit 0 (I2CTIE):
I2C Interface Tx Interrupt Enable bit
0: Disable interrupt
1: Enable interrupt
NOTE
If the interrupt mask is enabled, the program counter would jump into the corresponding
interrupt vector when the corresponding status flag is set.
6.1.24 Bank 0 R1F: IMR5 (Interrupt Mask Register 5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
EXIE5
R/W
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7~ 4, 2 ~ 0: Not used. Set to “0” all the time.
Bit 3 (EXIE5):
EXSF5 interrupt enable bit
0: Disable EXSF5 interrupt
1: Enable EXSF5 interrupt
22
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
NOTE
If the interrupt mask is enabled, the program counter would jump into the corresponding
interrupt vector when the corresponding status flag is set.
6.1.25 Bank 0 R21: WDTCR (Watchdog Timer Control Register)
Bit 7
WDTE
R/W
Bit 6
Bit 5
Bit 4
Bit 3
PSWE
R/W
Bit 2
WPSR2
R/W
Bit 1
WPSR1
R/W
Bit 0
WPSR0
R/W
-
-
-
-
-
-
Bit 7 (WDTE): Watchdog Timer enable bit. WDTE is both readable and writable.
0: Disable WDT
1: Enable WDT
Bit 3 (PSWE): Prescaler enable bit for WDT
0: Prescaler disable bit. WDT rate is 1:1.
1: Prescaler enable bit. WDT rate is set at Bits 2~0.
Bits 2 ~ 0 (WPSR2 ~ WPSR0): WDT Prescale bits
WPSR2
WPSR1
WPSR0
WDT Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.1.26 Bank 0 R22: TCCCR (TCC Control Register)
Bit 7
Bit 6
TCCS
R/W
Bit 5
TS
Bit 4
TE
Bit 3
PSTE
R/W
Bit 2
TPSR2
R/W
Bit 1
TPSR1
R/W
Bit 0
TPSR0
R/W
-
-
R/W
R/W
Bit 7:
Not used. Set to “0” all the time.
Bit 6 (TCCS): TCC Clock Source Select Bit
0: Fs (sub clock)
1: Fm (main clock)
Bit 5 (TS):
TCC signal source
0: Internal instruction cycle clock
1: Transition on the TCC pin. The TCC period must be larger than
internal instruction clock period.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
23
EM78P374N
8-bit Microcontroller
Bit 4 (TE):
TCC Signal Edge
0: Increment if the transition from low to high takes place on the TCC
pin.
1: Increment if the transition from high to low takes place on the TCC
pin.
Bit 3 (PSTE): Prescaler enable bit for TCC
0: Prescaler disable bit. TCC rate is 1:1.
1: Prescaler enable bit. TCC rate is set at Bit 2 ~ Bit 0.
Bits 2 ~ 0 (TPSR2 ~ TPSR0): TCC Prescaler bits
TPSR2
TPSR1
TPSR0
TCC Rate
0
0
0
1:2
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.1.27 Bank 0 R23: TCCD (TCC Data Register)
Bit 7
TCC7
R/W
Bit 6
TCC6
R/W
Bit 5
TCC5
R/W
Bit 4
TCC4
R/W
Bit 3
TCC3
R/W
Bit 2
TCC2
R/W
Bit 1
TCC1
R/W
Bit 0
TCC0
R/W
Bits 7 ~ 0 (TCC7 ~ TCC0): TCC data
Increase by an external signal edge through the TCC pin, or by the instruction cycle
clock. The External signal of TCC trigger pulse width must be greater than one
instruction. The signals to increase the counter are determined by Bit 4 and Bit 5 of the
TCCCR register. They are writable and readable as any other registers. If there is an
overflow, the value previously written to TCCD will be auto-reloaded to the TCC circuit.
6.1.28 Bank 0 R24: TC1CR1 (Timer/Counter 1 Control Register 1)
Bit 7
TC1S
R/W
Bit 6
TC1RC
R/W
Bit 5
TC1SS1
R/W
Bit 4
Bit 3
TC1FF
R/W
Bit 2
TC1OMS TC1IS1
R/W R/W
Bit 1
Bit 0
TC1IS0
R/W
-
-
Bit 7 (TC1S): Timer/Counter 1 start control
0: Stop and clear the counter (default)
1: Start Timer/Counter 1
24
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
Bit 6 (TC1RC): Timer 1 Read Control bit
0: When this bit is set to “0”, data from TC1DB can’t be read (default).
1: When this bit is set to “1”, data is read from TC1DB. The read data
is the enumerated counting number.
Bit 5 (TC1SS1): Timer/Counter 1 clock source select bit
0: Select internal clock as count source (Fc) - Fs/Fm (default)
1: Select external TC1 pin as count source (Fc). It is used only for
timer/counter mode.
Bit 4:
Not used. Set to “0” all the time.
Bit 3 (TC1FF): Inversion for Timer/Counter 1 as PWM
0: Duty is Logic 1 (default)
1: Duty is Logic 0
Bit 2 (TC1OMS): Timer Output Mode select bit
0: Repeat mode (default)
1: One–shot mode
NOTE
One-shot mode means the Timer only counts a cycle.
Bits 1 ~ 0 (TC1IS1 ~ TC1IS0): Timer 1 Interrupt Type select bits. These two bits are
used when the Timer operates in PWM mode.
TC1IS1
TC1IS0
Timer 1 Interrupt Type Select
TC1DA (period) matching
0
0
1
0
1
TC1DB (duty) matching
TC1DA and TC1DB matching
6.1.29 Bank 0 R25: TC1CR2 (Timer/Counter 1 Control Register 2)
Bit 7
TC1M2
R/W
Bit 6
TC1M1
R/W
Bit 5
TC1M0
R/W
Bit 4
TC1SS0 TC1CK3 TC1CK2 TC1CK1 TC1CK0
R/W R/W R/W R/W R/W
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7 ~ 5 (TC1M2 ~ TC1M0): Timer/Counter 1 operation mode select
TC1M2
TC1M1
TC1M0
Operating Mode Select
Timer/Counter Rising Edge
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Timer/Counter Falling Edge
Capture Mode Rising Edge
Capture Mode Falling Edge
Window mode
Programmable Divider output
Pulse Width Modulation output
Buzzer (output timer/counter clock source. The
duty cycle of the clock source must be 50/50)
1
1
1
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
25
EM78P374N
8-bit Microcontroller
Bit 4 (TC1SS0): Timer/Counter 1 clock source selection bit
0: Fs is used as count source (Fc) (default)
1: Fm is used as count source (Fc)
Bits 3~0 (TC1CK3~TC1CK0): Timer/Counter 1 clock source prescaler select:
Max. Time
8 MHz
Max. Time
16kHz
Clock
Source
Resolution
8 MHz
Resolution
16kHz
TC3CK3
TC3CK2
TC3CK1
TC3CK0
Normal
FC
FC=8M
125ns
250ns
500ns
FC=8M
32μs
FC=16K
62.5μs
125μs
250μs
FC=16K
16ms
0
0
0
0
0
0
0
0
1
0
1
0
FC/2
64μs
32ms
FC/22
128μs
64ms
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
FC/23
FC/24
FC/25
FC/26
FC/27
FC/28
FC/29
FC/210
FC/211
FC/212
FC/213
FC/214
FC/215
1μs
2μs
256μs
512μs
500μs
1ms
128ms
256ms
4μs
1024μs
2048μs
4096μs
8192μs
16384μs
32768μs
65536μs
131072μs
2ms
512ms
8μs
4ms
1024ms
2048ms
4096ms
8192ms
16384ms
32768ms
65536ms
131072ms
262144ms
524288ms
16μs
32μs
64μs
128μs
256μs
512μs
8ms
16ms
32ms
64ms
128ms
256ms
512ms
1.024ms 262144μs
2.048ms 524.288ms 1.024s
4.096ms 1.048s 2.048s
6.1.30 Bank 0 R26: TC1DA (Timer/Counter 1 Data Buffer A)
Bit 7
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7 ~ 0 (TC1DA7 ~ TC1DA0): Data Buffer A of 8 bit Timer/Counter 1
6.1.31 Bank 0 R27: TC1DB (Timer/Counter 1 Data Buffer B)
Bit 7
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7 ~ 0 (TC1DB7 ~ TC1DB0): Data Buffer B of 8 bit Timer/Counter 1
26
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
NOTE
1. When Timer / Counter x is used in PWM mode, the duty value stored at register
TCxDB must be smaller than or equal to the period value stored at register TCxDA,
i.e., duty≦ period. Then the PWM waveform is generated. If the duty is larger than
period, the PWM output waveform is kept at high voltage level.
2. The period value set by users is extra plus 1 in the inner circuit.
For example: When the period value is set as 0x4F, the PWM waveform will actually
generate 0x50 period length.
When the period value is set as 0xFF, the PWM waveform will
actually generate 0x100 period length.
6.1.32 Bank 0 R28~R2F: (Not used. Set to “0” all the time)
6.1.33 Bank 0 R30: I2CCR1 (I2C Status and Control Register 1)
Bit 7
Strobe/Pend
R
Bit 6
IMS
Bit 5
ISS
Bit 4
Bit 3
Bit 2
ACK
R
Bit 1
FULL
R
Bit 0
EMPTY
R
STOP SAR_EMPTY
R/W
R/W
R
R
Bit 7 (Strobe/Pend): In Master mode, it is used as strobe signal to control the I2C
circuit from sending SCL clock. Automatically resets after
receiving or transmitting a handshake signal (ACK or NACK).
In Slave mode, it is used as pending signal. User should clear it
after writing data into the Tx buffer or taking data from the Rx
buffer to inform the Slave I2C circuit to release the SCL signal.
Bit 6 (IMS):
Bit 5 (ISS):
I2C Master/Slave mode select bit.
0: Slave
1: Master
I2C Fast/Standard mode select bit (if Fm is 6 MHz and
I2CTS1~0<0,0>)
0: Standard mode (100kbit/s)
1: Fast mode (400kbit/s)
Bit 4 (STOP):
In Master mode, if STOP=1 and R/nW=1, then the MCU must
return a nACK signal to the Slave device before sending a STOP
signal. If STOP=1 and R/nW=0, then the MCU sends a STOP
signal after receiving an ACK signal. Reset when the MCU
sends a STOP signal to the Slave device.
In Slave mode, if STOP=1 and R/nW=0, then the MCU must
return a nACK signal to the Master device.
Bit 3 (SAR_EMPTY):Set when the MCU transmits a 1 byte data from the I2C Slave
Address Register and receives an ACK (or nACK) signal. Reset
when the MCU writes a 1 byte data to the I2C Slave Address
Register.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
27
EM78P374N
8-bit Microcontroller
Bit 2 (ACK):
The ACK condition bit is set to “1” by hardware when the device
responds acknowledge (ACK). Resets when the device responds with
a “not-acknowledge” (nACK) signal.
Bit 1 (FULL): Set by hardware when the I2C Receive Buffer register is full. Reset by
hardware when MCU reads data from the I2C Receive Buffer register.
Bit 0 (EMPTY): Set by hardware when the I2C Transmit Buffer register is empty and
receives an ACK (or nACK) signal. Reset by hardware when the MCU
writes new data to I2C Transmit Buffer register.
6.1.34 Bank 0 R31: I2CCR2 (I2C Status and Control Register 2)
Bit 7
I2CBF
R
Bit 6
GCEN
R/W
Bit 5
Bit 4
BBF
R
Bit 3
I2CTS1
R/W
Bit 2
I2CTS0
R/W
Bit 1
I2CCS
R/W
Bit 0
I2CEN
R/W
-
-
Bit 7 (I2CBF): I2C Busy Flag Bit
0: Clear to “0” in Slave mode if the received STOP signal or the I2C
Slave Address does not match.
1: Set when I2C communicates with Master in Slave mode.
Bit 6 (GCEN): I2C General Call Function Enable Bit
0: Disable General Call Function
1: Enable General Call Function
Bit 5:
Not used. Set to “0” all the time.
Bit 4 (BBF):
Busy Flag Bit. I2C detection is busy in Master mode. Read only.
Bits 3~2 (I2CTS1~I2CTS0): I2C Transmit Clock select bits. When using different
operating frequency (Fm), these bits must be set correctly in order for
the SCL clock to be consistent in Standard/Fast mode.
I2CCR1 Bit 5=0, Standard mode:
I2CTS1
I2CTS0
SCL CLK
Operating Fm (MHz)
0
0
1
1
0
1
0
1
Fm/40
4
8
Fm/80
Fm/120
Fm/160
12
16
I2CCR1 Bit 5=1, Fast mode:
I2CTS1
I2CTS0
SCL CLK
Operating Fm (MHz)
0
0
1
1
0
1
0
1
Fm/10
4
8
Fm/20
Fm/30
12
16
Fm/40
28
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
Bit 1 (I2CCS): I2C Clock Source select bit
0: Fm (main clock)
1: Fs (sub clock). This is applicable in Master mode only.
Bit 0 (I2CEN): I2C Enable Bit
0: Disable I2C mode
1: Enable I2C mode
6.1.35 Bank 0 R32: I2CSA (I2C Slave Address Register)
Bit 7
SA6
R/W
Bit 6
SA5
R/W
Bit 5
SA4
R/W
Bit 4
SA3
R/W
Bit 3
SA2
R/W
Bit 2
SA1
R/W
Bit 1
SA0
R/W
Bit 0
IRW
R/W
Bits 7 ~ 1 (SA6 ~ SA0): When the MCU is used as Master device for I2C application,
these bits are the Slave Device Address register.
Bit 0 (IRW):
When the MCU is used as Master device for I2C application, this bit is
Read/Write transaction control bit.
0: Write
1: Read
6.1.36 Bank 0 R33: I2CDB (I2C Data Buffer Register)
Bit 6
DB6
R/W
Bit 5
DB5
R/W
Bit 4
DB4
R/W
Bit 3
DB3
R/W
Bit 2
DB2
R/W
Bit 1
DB1
R/W
Bit 0
DB0
R/W
Bit 7
DB7
R/W
Bits 7 ~ 0 (DB7~DB0): I2C Receive/Transmit Data Buffer
6.1.37 Bank 0 R34: I2CDAL (I2C Device Address Register)
Bit 6
DA6
R/W
Bit 5
DA5
R/W
Bit 4
DA4
R/W
Bit 3
DA3
R/W
Bit 2
DA2
R/W
Bit 1
DA1
R/W
Bit 0
DA0
R/W
Bit 7
DA7
R/W
Bits 7 ~ 0 (DA7 ~ DA0): When MCU used as slave device for I2C application, this
register stores the address of the MCU. It is used to identify the data on
the I2C bus to extract the message delivered to the MCU.
6.1.38 Bank 0 R35: I2CDAH (I2C Device Address Register)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DA9
R/W
Bit 0
DA8
R/W
Bit 7
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7 ~ 2:
Not used. Set to “0” all the time.
Bits 1 ~ 0 (DA9 ~ DA8): Device address bits
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
29
EM78P374N
8-bit Microcontroller
6.1.39 Bank 0 R36~R3A: (Not used. Set to “0” all the time)
6.1.40 Bank 0 R3B: CMP2CR (Comparator 2 Control Register)
Bit 7
C2RS
R/W
Bit 6
CP2OUT
R
Bit 5
C2S1
R/W
Bit 4
C2S0
R/W
Bit 3
Bit 2
Bit 1
Bit 0
SDPWMB
R/W
-
-
-
-
-
-
Bit 7 (C2RS):
Selects the reference source for Comparator 2/OP2 non-inverting
terminal.
0: CIN+ is connected to pad (default)
1: CIN+ is connected to internal reference
Bit 6 (CP2OUT): The result of the Comparator 2 output
Bits 5 ~ 4 (C2S1 ~ C2S0): Comparator 2 select bits
C2S1
C2S0
Function Description
0
0
Comparator 2 and OP2 are not used
Comparator 2 is used and its output is not connected to
pad.
0
1
1
1
0
1
Comparator 2 is used and its output is connected to pad
OP
Bits 3 ~ 1:
Bit 0 (SDPWMB): Shut-down PMWB
0: Disable (default value)
Not used. Set to “0” all the time.
1: Enable. The PWMBE and /PWMBE are disabled at the falling
edge of Comparator 2.
NOTE
When using internal reference, you need to wait for at least 6 µs (when code option is
IRCIRS=0) and 50 µs (when code option is IRCIRS=1) after control bits
“CIRL11~CIRL10” are set, so as to obtain accurate output result. Otherwise, the
output result would be inaccurate. It is also recommended that the control bits
“C2S1~C2S0” should not be set at (1:0) or (1:1) to avoid occurrence of unexpected
results.
6.1.41 Bank 0 R3C: CMP3CR (Comparator 3 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CIRL11
R/W
Bit 1
CIRL10
R/W
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
Bits 7 ~ 3:
Not used. Set to “0” all the time.
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Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
Bits 2 ~ 1 (CIRL11~CIRL10): Internal voltage reference:
CIRL11
CIRL10
Voltage Reference
0
0
1
0
1
0
Disable (default)
4V
3V
1
1
2V
Bit 0:
Not used. Set to “0” all the time.
6.1.42 Bank 0 R3D: (Not used. Set to “0” all the time)
6.1.43 Bank 0 R3E: ADCR1 (ADC Control Register 1)
Bit 7
CKR2
R/W
Bit 6
CKR1
R/W
Bit 5
CKR0
R/W
Bit 4
ADRUN
R/W
Bit 3
ADP
R/W
Bit 2
ADOM
R/W
Bit 1
SHS1
R/W
Bit 0
SHS0
R/W
Bits 7 ~ 5 (CKR2 ~ 0): Clock Rate select of ADC
System Mode
Normal Mode
Green Mode
CKR[2:0]
000
Clock Rate
FMain/16
FMain/8
FMain/4
FMain/2
FMain/64
FMain/32
FMain/1
FSub
001
010
011
100
101
110
111
xxx
FSub
Bit 4 (ADRUN): ADC starts to run
Single mode:
0: Reset on completion of the conversion by hardware. This bit
cannot be reset by software.
1: A/D conversion starts. This bit can be set by software
Continuous mode:
0: ADC is stopped.
1: ADC is running unless this bit is reset by software
Bit 3 (ADP): ADC Power
0: ADC is in power down mode.
1: ADC is operating normally.
Bit 2 (ADOM): ADC Operation Mode Selection
0: ADC operates in single mode
1: ADC operates in continuous mode
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
31
EM78P374N
8-bit Microcontroller
Bits 1 ~ 0 (SHS1 ~ 0): Sample and Hold Timing Select
Sample and Hold Timing
SHS[1:0]
00
01
10
11
2 x TAD
4 x TAD
8 x TAD
12 x TAD
SHS[1~0]=10 is recommended
6.1.44 Bank 0 R3F: ADCR2 (ADC Control Register 2)
Bit 7
Bit 6
Bit 5
ADIM
R/W
Bit 4
ADCMS
R/W
Bit 3
VPIS1
R/W
Bit 2
VPIS0
R/W
Bit 1
VREFP
R/W
Bit 0
-
-
-
-
-
-
Bits 7 ~ 6:
Not used. Set to “0” all the time.
Bit 5 (ADIM): ADC Interrupt Mode
0: Normal mode. Interrupt occurs after AD conversion is completed.
1: Compare mode. Interrupt occurs when comparison result conforms
to the ADCMS bits setting. Using continuous mode is
recommended.
Bit 4 (ADCMS): ADC Comparison Mode select
Compare mode:
0: Interrupt occurs when AD conversion data is equal to or greater
than the data in ADCD register (which means when ADD > ADCD,
interrupt occurs).
1: Interrupt occurs when AD conversion data is equal to or less than
the data in ADCD register (which means when ADD < ADCD,
interrupt occurs).
Normal mode:
No effect
Bits 3 ~ 2 (VPIS1 ~ 0): Internal Positive Reference Voltage select
VPIS[1:0] Reference Voltage
00 AVDD
01
10
11
4V
3V
2V
Bit 1 (VREFP): Positive Reference Voltage select
0: Internal positive reference voltage. The actual voltage is set by
VPIS [1:0] bit
1: From VREFP pin
32
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
NOTE
When using internal reference, users need to wait for at least 6 µs (when code option
is IRCIRS=0) and 50 µs (when code option is IRCIRS=1) before control bit “ADRUN”
is set, so as to obtain accurate AD conversion result. Otherwise, the conversion
result would be inaccurate.
6.1.45 Bank 0 R40: ADISR (Analog to Digital Converter Input
Channel Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
ADIS4
R/W
Bit 3
ADIS3
R/W
Bit 2
ADIS2
R/W
Bit 1
ADIS1
R/W
Bit 0
ADIS0
R/W
-
-
-
-
-
-
Bits 7 ~ 5:
Not used. Set to “0” all the time.
Bits 4 ~ 0 (ADIS4 ~ 0): ADC input channel select bits
Selected
Selected
Channel
ADIS[4:0]
ADIS[4:0]
Channel
Ch 0
Ch 1
Ch 2
Ch 3
Ch 4
Ch 5
Ch 6
Ch 7
Ch 8
Ch 9
Ch 10
Ch 11
Ch 12
Ch 13
N/A
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
1/4 VDD Power Detect
N/A
OPA 2
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
N/A
Used for internal signal source. User only need to set ADIS[4:0]=10000~10100.
These AD input channels are instantly active.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
33
EM78P374N
8-bit Microcontroller
6.1.46 Bank 0 R41: ADER1 (Analog to Digital Converter Input
Control Register 1)
Bit 7
ADE7
R/W
Bit 6
ADE6
R/W
Bit 5
ADE5
R/W
Bit 4
ADE4
R/W
Bit 3
ADE3
R/W
Bit 2
ADE2
R/W
Bit 1
ADE1
R/W
Bit 0
ADE0
R/W
Bit 7 (ADE7): AD converter enable bit of P57 pin
0: Disable ADC7, P57 acts as I/O pin
1: Enable ADC7 to act as analog input pin
Bit 6 (ADE6): AD converter enable bit of P56 pin
0: Disable ADC6, P56 acts as I/O pin
1: Enable ADC6 to act as analog input pin
Bit 5 (ADE5): AD converter enable bit of P55 pin
0: Disable ADC5, P55 acts as I/O pin
1: Enable ADC5 to act as analog input pin
Bit 4 (ADE4): AD converter enable bit of P54 pin.
0: Disable ADC4, P54 acts as I/O pin
1: Enable ADC4 to act as analog input pin
Bit 3 (ADE3): AD converter enable bit of P53 pin.
0: Disable ADC3, P53 acts as I/O pin
1: Enable ADC3 to act as analog input pin
Bit 2 (ADE2): AD converter enable bit of P52 pin.
0: Disable ADC2, P52 acts as I/O pin
1: Enable ADC2 to act as analog input pin
Bit 1 (ADE1): AD converter enable bit of P51 pin
0: Disable ADC1, P51 acts as I/O pin
1: Enable ADC1 to act as analog input pin
Bit 0 (ADE0): AD converter enable bit of P50 pin
0: Disable ADC0, P50 acts as I/O pin
1: Enable ADC0 to act as analog input pin
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Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.47 Bank 0 R42: ADER2 (Analog to Digital Converter Input
Control Register 2)
Bit 7
Bit 6
Bit 5
ADE13
R/W
Bit 4
ADE12
R/W
Bit 3
ADE11
R/W
Bit 2
ADE10
R/W
Bit 1
ADE9
R/W
Bit 0
ADE8
R/W
-
-
-
-
Bits 7 ~ 6:
Not used. Set to “0” all the time.
Bit 5 (ADE13): AD converter enable bit of P75 pin
0: Disable ADC13, P75 acts as I/O pin
1: Enable ADC13 to act as analog input pin
Bit 4 (ADE12): AD converter enable bit of P74 pin
0: Disable ADC12, P74 acts as I/O pin
1: Enable ADC12 to act as analog input pin
Bit 3 (ADE11): AD converter enable bit of P73 pin
0: Disable ADC11, P73 acts as I/O pin
1: Enable ADC11 to act as analog input pin
Bit 2 (ADE10): AD converter enable bit of P72 pin
0: Disable ADC10, P72 acts as I/O pin
1: Enable ADC10 to act as analog input pin
Bit 1 (ADE9): AD converter enable bit of P71 pin
0: Disable ADC9, P71 acts as I/O pin
1: Enable ADC9 to act as analog input pin
Bit 0 (ADE8): AD converter enable bit of P70 pin
0: Disable ADC8, P70 acts as I/O pin
1: Enable ADC8 to act as analog input pin
6.1.48 Bank 0 R43: ADDL (Low Byte of Analog to Digital
Converter Data)
Bit 7
ADD7
R
Bit 6
ADD6
R
Bit 5
ADD5
R
Bit 4
ADD4
R
Bit 3
ADD3
R
Bit 2
ADD2
R
Bit 1
ADD1
R
Bit 0
ADD0
R
Bits 7 ~ 0 (ADD7 ~ 0): Low Byte of AD Data Buffer
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
35
EM78P374N
8-bit Microcontroller
6.1.49 Bank 0 R44: ADDH (High Byte of Analog to Digital
Converter Data)
Bit 7
ADD15
R
Bit 6
ADD14
R
Bit 5
ADD13
R
Bit 4
ADD12
R
Bit 3
ADD11
R
Bit 2
ADD10
R
Bit 1
ADD9
R
Bit 0
ADD8
R
Bits 7 ~ 0 (ADD15 ~ 8): High Byte of AD Data Buffer.
The AD data format is dependent on code option ADFM. The
following table shows how the data justify the different ADFM
settings:
ADFM
ADDH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
-
-
-
-
ADD11 ADD10 ADD9 ADD8
0
ADDL ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
ADDH ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4
12 bits
1
ADDL
-
-
-
-
ADD3 ADD2 ADD1 ADD0
6.1.50 Bank 0 R45 ADCVL (Low Byte of Analog to Digital
Converter Comparison)
Bit 7
ADCV7
R/W
Bit 6
ADCV6
R/W
Bit 5
ADCV5
R/W
Bit 4
ADCV4
R/W
Bit 3
ADCV3
R/W
Bit 2
ADCV2
R/W
Bit 1
ADCV1
R/W
Bit 0
ADCV0
R/W
Bits 7 ~ 0 (ADCV7 ~ 0): Low Byte Data for AD comparison
User should use the same data format as with ADDH and
ADDL registers. Otherwise, faulty values will result after AD
comparison.
6.1.51 Bank 0 R46 ADCVH (High Byte of Analog to Digital
Converter Comparison)
Bit 7
ADCV15 ADCV14 ADCV13 ADCV12 ADCV11
R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ADCV10
R/W
Bit 1
ADCV9
R/W
Bit 0
ADCV8
R/W
Bits 7 ~ 0 (ADCV15 ~ 8): High Byte Data for AD comparison
User should use the same data format as with ADDH and
ADDL registers. Otherwise, faulty values will result after AD
comparison.
6.1.52 Bank 1 R5 ~ R7: (Not used. Set to “0” all the time)
36
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.53 Bank 1 R8: P5PHCR (Port 5 Pull-high Control Register)
Bit 7
PH57
R/W
Bit 6
PH56
R/W
Bit 5
PH55
R/W
Bit 4
PH54
R/W
Bit 3
PH53
R/W
Bit 2
PH52
R/W
Bit 1
PH51
R/W
Bit 0
PH50
R/W
Bit 7 (PH57): Control bit used to enable pull-high of the P57 pin
0: Enable internal pull-high
1: Disable internal pull-high
Bit 6 (PH56): Control bit used to enable pull-high of the P56 pin
Bit 5 (PH55): Control bit used to enable pull-high of the P55 pin
Bit 4 (PH54): Control bit used to enable pull-high of the P54 pin
Bit 3 (PH53): Control bit used to enable pull-high of the P53 pin
Bit 2 (PH52): Control bit used to enable pull-high of the P52 pin
Bit 1 (PH51): Control bit used to enable pull-high of the P51 pin
Bit 0 (PH50): Control bit used to enable pull-high of the P50 pin
6.1.54 Bank 1 R9: P6PHCR (Port 6 Pull-high Control Register)
Bit 7
Bit 6
PH66
R/W
Bit 5
PH65
R/W
Bit 4
PH64
R/W
Bit 3
PH63
R/W
Bit 2
PH62
R/W
Bit 1
PH61
R/W
Bit 0
PH60
R/W
-
-
All bits are low active.
Bit 7 (PH67): Not used. Set to “1” all the time.
Bit 6 (PH66): Control bit used to enable pull-high of the P66 pin
Bit 5 (PH65): Control bit used to enable pull-high of the P65 pin
Bit 4 (PH64): Control bit used to enable pull-high of the P64 pin
Bit 3 (PH63): Control bit used to enable pull-high of the P63 pin
Bit 2 (PH62): Control bit used to enable pull-high of the P62 pin
Bit 1 (PH61): Control bit used to enable pull-high of the P61 pin
Bit 0 (PH60): Control bit used to enable pull-high of the P60 pin
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
37
EM78P374N
8-bit Microcontroller
6.1.55 Bank 1 RA: P7PHCR (Port 7 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
P7HPH
R/W
Bit 0
P7LPH
R/W
-
-
-
-
-
-
-
-
-
-
-
-
All bits are low active
Bits 7 ~ 2: Not used. Set to “1” all the time
Bit 1 (P7HPH): Control bit used to enable pull-high of the Port 7 high nibble pin
Bit 0 (P7LPH): Control bit used to enable pull-high of the Port 7 low nibble pin
6.1.56 Bank 1 RB: P5PLCR (Port 5 Pull-low Control Register)
Bit 7
PL57
R/W
Bit 6
PL56
R/W
Bit 5
PL55
R/W
Bit 4
PL54
R/W
Bit 3
PL53
R/W
Bit 2
PL52
R/W
Bit 1
PL51
R/W
Bit 0
PL50
R/W
Bit 7 (PL57): Control bit used to enable pull-low of the P57 pin
0: Enable internal pull-low
1: Disable internal pull-low
Bit 6 (PL56): Control bit used to enable pull-low of the P56 pin
Bit 5 (PL55): Control bit used to enable pull-low of the P55 pin
Bit 4 (PL54): Control bit used to enable pull-low of the P54 pin
Bit 3 (PL53): Control bit used to enable pull-low of the P53 pin
Bit 2 (PL52): Control bit used to enable pull-low of the P52 pin
Bit 1 (PL51): Control bit used to enable pull-low of the P51 pin
Bit 0 (PL50): Control bit used to enable pull-low of the P50 pin
6.1.57 Bank 1 RC: P6PLCR (Port 6 Pull-low Control Register)
Bit 7
PL67
R/W
Bit 6
PL66
R/W
Bit 5
PL65
R/W
Bit 4
PL64
R/W
Bit 3
PL63
R/W
Bit 2
PL62
R/W
Bit 1
PL61
R/W
Bit 0
PL60
R/W
All bits are low active
Bit 7 (PL67): Control bit used to enable pull-low of the P67 pin
Bit 6 (PL66): Control bit used to enable pull-low of the P66 pin
Bit 5 (PL65): Control bit used to enable pull-low of the P65 pin
Bit 4 (PL64): Control bit used to enable pull-low of the P64 pin
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Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
Bit 3 (PL63): Control bit used to enable pull-low of the P63 pin
Bit 2 (PL62): Control bit used to enable pull-low of the P62 pin
Bit 1 (PL61): Control bit used to enable pull-low of the P61 pin
Bit 0 (PL60): Control bit used to enable pull-low of the P60 pin
6.1.58 Bank 1 RD: P7PLCR (Port 7 Pull-low Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
P7HPL
R/W
Bit 0
P7LPL
R/W
-
-
-
-
-
-
-
-
-
-
-
-
All of these bits are low active.
Bits 7 ~ 2: Not used. Set to “1” all the time.
Bit 1 (P7HPL): Control bit used to enable pull-low of the Port 7 high nibble pin
Bit 0 (P7LPL): Control bit used to enable pull-low of the Port 7 low nibble pin
6.1.59 Bank 1 RE: P5HDSCR (Port 5 High Drive/Sink Control
Register)
Bit 7
H57
R/W
Bit 6
H56
R/W
Bit 5
H55
R/W
Bit 4
H54
R/W
Bit 3
H53
R/W
Bit 2
H52
R/W
Bit 1
H51
R/W
Bit 0
H50
R/W
Bits 7 ~ 0 (H57 ~ H50): P57~P50 high drive/sink current control bits
0: Enable high drive/sink
1: Disable high drive/sink
6.1.60 Bank 1 RF: P6HDSCR (Port 6 High Drive/Sink Control
Register)
Bit 7
H67
R/W
Bit 6
H66
R/W
Bit 5
H65
R/W
Bit 4
H64
R/W
Bit 3
H63
R/W
Bit 2
H62
R/W
Bit 1
H61
R/W
Bit 0
H60
R/W
Bits 7 ~ 0 (H67 ~ H60): P67~P60 high drive/sink current control bits (only P67 has high
sink).
0: Enable high drive/sink
1: Disable high drive/sink
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
39
EM78P374N
8-bit Microcontroller
6.1.61 Bank 1 R10: P7HDSCR (Port 7 High Drive/Sink Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
P7HHDS P7LHDS
R/W R/W
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
All bits are low active.
Bits 7 ~ 2: Not used. Set to “1” all the time.
Bit 1 (P7HHDS): Control bit used to enable high drive/sink of Port 7 high nibble pin
Bit 0 (P7LHDS): Control bit used to enable high drive/sink of Port 7 low nibble pin
6.1.62 Bank 1 R11: P5ODCR (Port 5 Open-drain Control Register)
Bit 7
OD57
R/W
Bit 6
OD56
R/W
Bit 5
OD55
R/W
Bit 4
OD54
R/W
Bit 3
OD53
R/W
Bit 2
OD52
R/W
Bit 1
OD51
R/W
Bit 0
OD50
R/W
Bits 7 ~ 0 (OD57 ~ OD50): Open-drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.1.63 Bank 1 R12: P6ODCR (Port 6 Open-drain Control Register)
Bit 7
Bit 6
OD66
R/W
Bit 5
OD65
R/W
Bit 4
OD64
R/W
Bit 3
OD63
R/W
Bit 2
OD62
R/W
Bit 1
OD61
R/W
Bit 0
OD60
R/W
-
-
Bit 7:
Not used. Set to “0” all the time.
Bits 6 ~ 0 (OD66~OD60): Open-drain control bits
0: Disable open-drain function
1: Enable open-drain function
6.1.64 Bank 1 R13: P7ODCR (Port 7 Open-drain Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
P7HOD
R/W
Bit 0
P7LOD
R/W
-
-
-
-
-
-
-
-
-
-
-
-
All bits are high active.
Bits 7 ~ 2: Not used. Set to “0” all the time.
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Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
Bit 1 (P7HOD): Control bit used to enable open-drain of Port 7 high nibble pin
Bit 0 (P7LOD): Control bit used to enable open-drain of Port 7 low nibble pin
6.1.65 Bank 1 R14~R15: (Not used. Set to “0” all the time)
6.1.66 Bank 1 R16: PWMSCR (PWM Source Clock Control
Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
PWMCS PWMBS PWMAS
R/W
R/W
R/W
Bits 7 ~ 3:
Not used. Set to “0” all the time.
Bit 2 (PWMCS): Clock select for PWMC timer
0: Fs (default)
1: Fm
Bit 1 (PWMBS): Clock select for PWMB timer
0: Fs (default)
1: Fm
Bit 0 (PWMAS): Clock select for PWM timer
0: Fs (default)
1: Fm
6.1.67 Bank 1 R17: PWMACR (PWMA Control Register)
Bit 7
PWMAE IPWMAE
R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
TAEN
R/W
Bit 2
TAP2
R/W
Bit 1
TAP1
R/W
Bit 0
TAP0
R/W
-
-
-
-
Bit 7 (PWMAE): PWMA enable bit
0: Disable (default)
1: Enable
Bit 6 (IPWMAE): Inverse PWMA enable bit
0: Disable (default)
1: Enable.
Bits 5 ~ 4:
Not used. Set to “0” all the time.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
41
EM78P374N
8-bit Microcontroller
Bit 3 (TAEN):
TMRA enable bit. All PWM functions are valid only when this bit is
set.
0: TMRA is off (default value)
1: TMRA is on
PWMXEN TXEN
Function Description
Not used as PWM function, I/O pin, or as any other
pin function.
0
0
0
1
1
1
0
1
Timer function, I/O pin, or other pin function
PWM function, the waveform is kept at inactive level
PWM function, normal PWM output waveform.
Bits 2 ~ 0 (TAP2 ~ TAP0): TMRA clock prescale option bits
TAP2
TAP1
TAP0
Prescale
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
6.1.68 Bank 1 R18: PRDAL (Low Byte of PWMA Period)
Bit 7
PRDA7
R/W
Bit 6
PRDA6
R/W
Bit 5
PRDA5
R/W
Bit 4
PRDA4
R/W
Bit 3
PRDA3
R/W
Bit 2
PRDA2
R/W
Bit 1
PRDA1
R/W
Bit 0
PRDA0
R/W
Bits 7 ~ 0 (PRDA7 ~ 0): The contents of the register are the low byte of the PWMA
period.
6.1.69 Bank 1 R19: PRDAH (High Byte of PWMA Period)
Bit 7
PRDA15 PRDA14 PRDA13 PRDA12 PRDA11 PRDA10
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PRDA9
R/W
Bit 0
PRDA8
R/W
Bits 7~0 (PRDA15~8): The contents of the register are the high byte of PWMA period.
6.1.70 Bank 1 R1A: DTAL (Low Byte of PMWA Duty)
Bit 7
DTA7
R/W
Bit 6
DTA6
R/W
Bit 5
DTA5
R/W
Bit 4
DTA4
R/W
Bit 3
DTA3
R/W
Bit 2
DTA2
R/W
Bit 1
DTA1
R/W
Bit 0
DTA0
R/W
Bits 7 ~ 0 (DTA7 ~ 0): The contents of the register are the low byte of the PWMA duty.
42
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.71 Bank 1 R1B: DTAH (High Byte of PMWA Duty)
Bit 7
DTA15
R/W
Bit 6
DTA14
R/W
Bit 5
DTA13
R/W
Bit 4
DTA12
R/W
Bit 3
DTA11
R/W
Bit 2
DTA10
R/W
Bit 1
DTA9
R/W
Bit 0
DTA8
R/W
Bits 7 ~ 0 (DTA15 ~ 8): The contents of the register are the high byte of the PWMA
duty.
6.1.72 Bank 1 R1C: TMRAL (Low Byte of Timer A)
Bit 7
TMRA7
R
Bit 6
TMRA6
R
Bit 5
TMRA5
R
Bit 4
TMRA4
R
Bit 3
TMRA3
R
Bit 2
TMRA2
R
Bit 1
TMRA1
R
Bit 0
TMRA0
R
Bits 7 ~ 0 (TMRA7 ~ 0): The contents of the register are the low byte of the PWMA
timer which is counting. This is read-only.
6.1.73 Bank 1 R1D: TMRAH (High Byte of Timer A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMRA9
R
Bit 0
TMRA8
R
TMRA15 TMRA14 TMRA13 TMRA12 TMRA11 TMRA10
R
R
R
R
R
R
Bits 7 ~ 0 (TMRA15 ~ 8): The contents of the register are the high byte of the PWMA
timer which is counting. This is read-only
6.1.74 Bank 1 R1E: PWMBCR (PWMB Control Register)
Bit 7
PWMBE IPWMBE
R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
TBEN
R/W
Bit 2
TBP2
R/W
Bit 1
TBP1
R/W
Bit 0
TBP0
R/W
-
-
-
-
Bit 7 (PWMBE): PWMB enable bit
0: Disable (default)
1: Enable
Bit 6 (IPWMBE): Inverse PWMB enable bit
0: Disable (default)
1: Enable
Bits 5 ~ 4:
Not used. Set to “0” all the time.
Bit 3 (TBEN):
TMRB enable bit. All PWM functions are valid only as this bit is set
0: TMRB is off (default value)
1: TMRB is on
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
43
EM78P374N
8-bit Microcontroller
Bits 2 ~ 0 (TBP2 ~ TBP0): TMRB clock prescale option bits
TBP2
TBP1
TBP0
Prescale
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
6.1.75 Bank 1 R1F: PRDBL (Low Byte of PWMB Period)
Bit 7
PRDB7
R/W
Bit 6
PRDB6
R/W
Bit 5
PRDB5
R/W
Bit 4
PRDB4
R/W
Bit 3
PRDB3
R/W
Bit 2
PRDB2
R/W
Bit 1
PRDB1
R/W
Bit 0
PRDB0
R/W
Bits 7 ~ 0 (PRDB7 ~ 0): The contents of the register are the low byte of the PWMB
period.
6.1.76 Bank 1 R20: PRDBH (High Byte of PWMB Period)
Bit 7
PRDB15 PRDB14 PRDB13 PRDB12 PRDB11 PRDB10
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PRDB9
R/W
Bit 0
PRDB8
R/W
Bits 7 ~ 0 (PRDB15 ~ 8): The contents of the register are the high byte of PWMB
period.
6.1.77 Bank 1 R21: DTBL (Low Byte of PMWB Duty)
Bit 7
DTB7
R/W
Bit 6
DTB6
R/W
Bit 5
DTB5
R/W
Bit 4
DTB4
R/W
Bit 3
DTB3
R/W
Bit 2
DTB2
R/W
Bit 1
DTB1
R/W
Bit 0
DTB0
R/W
Bits 7 ~ 0 (DTB7 ~ 0): The contents of the register are the low byte of the PWMB
duty.
6.1.78 Bank 1 R22: DTBH (High Byte of PMWB Duty)
Bit 7
DTB15
R/W
Bit 6
DTB14
R/W
Bit 5
DTB13
R/W
Bit 4
DTB12
R/W
Bit 3
DTB11
R/W
Bit 2
DTB10
R/W
Bit 1
DTB9
R/W
Bit 0
DTB8
R/W
Bits 7 ~ 0 (DTB15 ~ 8): The contents of the register are the high byte of the PWMB
duty.
44
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.79 Bank 1 R23: TMRBL (Low Byte of Timer B)
Bit 7
TMRB7
R
Bit 6
TMRB6
R
Bit 5
TMRB5
R
Bit 4
TMRB4
R
Bit 3
TMRB3
R
Bit 2
TMRB2
R
Bit 1
TMRB1
R
Bit 0
TMRB0
R
Bits 7 ~ 0 (TMRB7 ~ 0): The contents of the register are the low byte of the PWMB
timer which is counting. This is read-only.
6.1.80 Bank 1 R24: TMRBH (High Byte of Timer B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TMRB9
R
Bit 0
TMRB8
R
TMRB15 TMRB14 TMRB13 TMRB12 TMRB11 TMRB10
R
R
R
R
R
R
Bits 7 ~ 0 (TMRB15 ~ 8): The contents of the register are the high byte of the PWMB
timer which is counting. This is read-only.
6.1.81 Bank 1 R25: PWMCCR (PWMC Control Register)
Bit 7
PWMCE IPWMCE
R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
TCEN
R/W
Bit 2
TCP2
R/W
Bit 1
TCP1
R/W
Bit 0
TCP0
R/W
-
-
-
-
Bit 7 (PWMCE): PWMC enable bit
0: Disable (default)
1: Enable
Bit 6 (IPWMCE): Inverse PWMC enable bit
0: Disable (default)
1: Enable
Bits 5 ~ 4:
Not used. Set to “0” all the time.
Bit 3 (TCEN):
TMRC enable bit. All PWM functions are valid only if this bit is set.
0: TMRC is off (default value)
1: TMRC is on
Bits 2~0 (TCP2~TCP0): TMRC clock prescale option bits
TCP2
TCP1
TCP0
Prescale
1:1 (default)
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:64
1:128
1:256
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
45
EM78P374N
8-bit Microcontroller
6.1.82 Bank 1 R26: PRDCL (Low Byte of PWMC Period)
Bit 7
Bit 6
PRDC6
R/W
Bit 5
PRDC5
R/W
Bit 4
PRDC4
R/W
Bit 3
PRDC3
R/W
Bit 2
PRDC2
R/W
Bit 1
PRDC1
R/W
Bit 0
PRDC0
R/W
PRDC7
R/W
Bits 7 ~ 0 (PRDC7 ~ 0): The contents of the register are the low byte of the PWMC
period.
6.1.83 Bank 1 R27: PRDCH (High Byte of PWMC Period)
Bit 7
PRDC15 PRDC14 PRDC13 PRDC12 PRDC11 PRDC10
R/W R/W R/W R/W R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PRDC9
R/W
Bit 0
PRDC8
R/W
Bits 7 ~ 0 (PRDC15 ~ 8):The contents of the register are the high byte of PWMC
period.
6.1.84 Bank 1 R28: DTCL (Low Byte of PMWC Duty)
Bit 7
DTC7
R/W
Bit 6
DTC6
R/W
Bit 5
DTC5
R/W
Bit 4
DTC4
R/W
Bit 3
DTC3
R/W
Bit 2
DTC2
R/W
Bit 1
DTC1
R/W
Bit 0
DTC0
R/W
Bits 7 ~ 0 (DTC7 ~ 0): The contents of the register are the low byte of the PWMC
duty.
6.1.85 Bank 1 R29: DTCH (High Byte of PMWC Duty)
Bit 7
DTC15
R/W
Bit 6
DTC14
R/W
Bit 5
DTC13
R/W
Bit 4
DTC12
R/W
Bit 3
DTC11
R/W
Bit 2
DTC10
R/W
Bit 1
DTC9
R/W
Bit 0
DTC8
R/W
Bits 7 ~ 0 (DTC15 ~ 8): The contents of the register are the high byte of the PWMC
duty.
6.1.86 Bank 1 R2A: TMRCL (Low Byte of Timer C)
Bit 7
TMRC7
R
Bit 6
TMRC6
R
Bit 5
TMRC5
R
Bit 4
TMRC4
R
Bit 3
TMRC3
R
Bit 2
TMRC2
R
Bit 1
TMRC1
R
Bit 0
TMRC0
R
Bits 7 ~ 0 (TMRC7 ~ 0): The contents of the register are the low byte of the PWMC
timer which is counting. This is read-only.
46
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.1.87 Bank 1 R2B: TMRCH (High Byte of Timer C)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMRC8
R
TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 TMRC9
R
R
R
R
R
R
R
Bits 7 ~ 0 (TMRC15 ~ 8):The contents of the register are the high byte of the PWMC
timer which is counting. This is read-only.
R2C ~ R3F: Not used. Set to “0” all the time.
6.1.88 Bank 1 R41 (Reserved)
6.1.89 Bank 1 R42 (Reserved)
6.1.90 Bank 1 R43 (Reserved)
6.1.91 Bank 1 R44 (Reserved)
6.1.92 Bank 1 R45: TBPTL (Table Pointer Low Register)
Bit 7
TB7
R/W
Bit 6
TB6
R/W
Bit 5
TB5
R/W
Bit 4
TB4
R/W
Bit 3
TB3
R/W
Bit 2
TB2
R/W
Bit 1
TB1
R/W
Bit 0
TB0
R/W
Bits 7 ~ 0 (TB7 ~ TB0): Table Pointer Address Bits 7~0.
6.1.93 Bank 1 R46: TBPTH (Table Pointer High Register)
Bit 7
HLB
R/W
Bit 6
Bit 5
Bit 4
Bit 3
TB11
R/W
Bit 2
TB10
R/W
Bit 1
TB9
R/W
Bit 0
TB8
R/W
-
-
-
-
-
-
Bit 7 (HLB): Take MLB or LSB at machine code
Bits 6 ~ 4: Not used. Set to “0” all the time.
Bits 3 ~ 0 (TB11 ~ TB8): Table Pointer Address Bits 11~8.
6.1.94 Bank 1 R48: PCH (Program Counter High)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PC11
R/W
Bit 2
PC10
R/W
Bit 1
PC9
R/W
Bit 0
PC8
R/W
-
-
-
-
-
-
-
-
Bits 7 ~ 4:
Not used. Set to “0” all the time.
Bits 3 ~ 0 (PC11 ~ PC8): The low byte of program counter
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
47
EM78P374N
8-bit Microcontroller
6.1.95 Bank 1 R49: LVDCR (Low Voltage Detector Control
Register)
Bit 7
LVDEN
R/W
Bit 6
Bit 5
LVDS1
R/W
Bit 4
LVDS0
R/W
Bit 3
LVDB
R
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bit 7 (LVDEN):
Low Voltage Detector Enable Bit
0: Disable low voltage detector
1: Enable low voltage detector
Bit 6:
Not used. Set to “0” all the time.
Bits 5 ~ 4 (LVDS1 ~ LVDS0): Low Voltage Detector Level bits.
LVDEN LVDS1, LVDS0 LVD Voltage Interrupt Level LVDB
VDD <2.2V
VDD >2.2V
VDD <3.3V
VDD >3.3V
VDD <4.0V
VDD >4.0V
VDD <4.5V
VDD >4.5V
NA
0
1
0
1
0
1
0
1
1
1
1
1
11
10
01
1
0
00
XX
Bit 3 (LVDB):
Low Voltage Detector State bit. This is a read only bit. When
the VDD pin voltage is lower than LVD voltage interrupt level
(selected by LVDS2 ~ LVDS0), this bit will be cleared.
0: The low voltage is detected.
1: The low voltage is not detected or LVD function is disabled.
6.1.96 Bank 1 R4A~R4C (Reserved)
6.1.97 Bank 1 R4D (Reserved)
6.1.98 Bank 1 R4E (Reserved)
6.1.99 Bank 1 R4F (Reserved)
48
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.2 TCC/WDT and Prescaler
Two 8-bit counters prescalers are available for the TCC and WDT respectively. The
TPSR0~ TPSR2 bits of the TCCCR register (Bank 0 R22) are used to determine the
ratio of the TCC prescaler. Likewise, the WPSR0~WPSR2 bits of the WDTCR register
(Bank0 R21) are used to determine the prescaler for the WDT. The prescaler counter is
cleared by the instructions each time they are written into TCC. The WDT and
prescaler are cleared by the “WDTC” and “SLEP” instructions. Figure 6-3 below
depicts the circuit diagram of TCC/WDT.
TCCD (Bank 0 R23) is an 8-bit timer/counter. The TCC clock source can be either
internal clock or external signal input (edge selectable from the TCC pin). As illustrated
below, if the TCC signal source is from internal clock, TCC will increase by 1 at every
instruction cycle (without prescaler). If the TCC signal source is from THE external
clock input, The TCC will be incremented by 1 at every falling edge or rising edge of the
TCC pin. The TCC pin input time length (kept in High or Low level) must be greater
than 1CLK. The TCC will stop running when Sleep mode occurs.
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even after the oscillator driver has been turned off (i.e., in Sleep mode). During
Normal operation or Sleep mode, a WDT time-out (if enabled) will cause the device to
reset. The WDT can be enabled or disabled at any time during Normal mode by
software programming (see WDTE bit of WDTCR register in Section 6.1.25). With no
prescaler, the WDT time-out period is approximately 16ms1 (one oscillator start-up
timer period).
CLOCK
0
Data Bus
8 Bit Counter
MUX
SYNC
2 cycles
1
TCC(R23)
TCC Pin
TE (R22)
8 to 1 MUX
Prescaler
TCC overflow
interrupt
TS (R22)
TPSR2~TPSR0
(R22)
WDT
8 Bit Counter
8 to 1 MUX
Prescaler
WDTE (R21)
WDT time out
WPSR2~WPSR0
(R21)
Figure 6-3 TCC and WDT Block Diagram
1 VDD=5V, 25oC WDT time-out period = 16ms ±3%.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
49
EM78P374N
8-bit Microcontroller
6.3 I/O Ports
The I/O registers, Port 5~Port 7 are bi-directional tri-state I/O ports. All ports can be
pulled high and pulled low internally by software. Furthermore, they can also be set as
open-drain output and high sink/drive by software. Port 5 and Port 6 feature wake-up
and interrupt functions, as well as input status change interrupt function. Each I/O pin
can be defined as "input" or "output" pin by the I/O Control registers (IOC5 ~ IOC7).
The I/O registers and I/O Control registers are both readable and writable. The I/O
interface circuits for Port 5 ~ Port 7 are shown in the subsequent Figures 6-4a to 6-4d.
The EM78P374N has three different types of packaging with different number of pins.
To achieve lowest power consumption, it is highly recommended to program the
“not-used” P52, P71, and P72 ~ P75 on the 18-pin DIP/SOP package, and P72 ~P75
on the 20-pin DIP/SOP package as follows:
1. When the “not-used” pins need to be defined as output ports, the pins should be set
as output high or pull low relative to its pull high/low status.
2. When the “not-used” pins need to be defined as input ports, the pins should be set as
input pull high or pull low.
PCRD
P
Q
D
R
PCWR
CLK
_
Q
C
L
P
R
IOD
PORT
Q
D
PDWR
CLK
_
Q
C
L
PDRD
0
1
M
U
X
Note: Pull-down is not shown in the figure.
Figure 6-4a I/O Port and I/O Control Register Circuit for Ports 5~7
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Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
PCRD
P
Q
D
R
_
Q
PCWR
PDWR
CLK
C
L
INT
IOD
P
R
Q
PORT
D
_
Q
CLK
C
L
0
1
P
D
R
Q
M
U
X
_
Q
CLK
C
L
T10
PDRD
P
R
D
Q
CLK
_
Q
C
L
INT
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-4b I/O Port and I/O Control Register Circuit for /INT
PCRD
P
Q
_
Q
D
D
R
CLK
PCWR
PDWR
C
L
P61~P67
PORT
IOD
P
R
Q
_
Q
CLK
C
L
0
1
M
U
X
TIN
PDRD
P
R
D
Q
CLK
_
Q
C
L
Note: Pull-high (down) and Open-drain are not shown in the figure.
Figure 6-4c I/O Port and I/O Control Register Circuit for Ports 5~7
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
51
EM78P374N
8-bit Microcontroller
IOCE.1
P
Q
D
R
CLK
Interrupt
_
Q
C
L
RE.
1
ENI Instruction
P
R
T10
T11
D
Q
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
C
L
T17
DISI Instruction
Interrupt
(Wake-up from SLEEP)
/SLEP
Next Instruction
(Wake-up from SLEEP)
Figure 6-4d I/O Port 5~6 with Input Change Interrupt/Wake-up Block Diagram
6.3.1 Usage of Ports 5~6 Input Change Wake-up/Interrupt Function
1. Wake-up
a) Before Sleep:
1) Disable WDT
2) Read I/O Port (MOV R6,R6)
3) Execute "ENI" or "DISI"
4) Enable Wake-up bit (Set WUE6H =1, WUE6L =1)
5) Execute "SLEP" instruction
b) After wake-up:
Next instruction
2. Wake-up and Interrupt
a) Before Sleep
1) Disable WDT
2) Read I/O Port (MOV R6, R6)
3) Execute "ENI" or "DISI"
4) Enable wake-up bit (Set WUE6H =1, WUE6L =1)
5) Enable interrupt (Set ICIE =1)
6) Execute "SLEP" instruction
b) After Wake-up
1) IF "ENI" Interrupt vector (0006H)
2) IF "DISI" Next instruction
52
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.4 Reset and Wake-up Operation
A reset is initiated by one of the following events:
1) Power on reset
2) /RESET pin input "low"
3) WDT time-out (if enabled)
4) LVR (if enabled)
The device is kept in a reset condition for a period of approximately 16ms (one
oscillator start-up timer period) after the Power-on reset is detected. And if the /RESET
pin goes “low” or WDT time-out is active, a reset is generated. In RC mode the reset
time is 8/32 clocks, and in XTAL mode; the reset time is 510 clocks. Once a reset
occurs, the following functions are performed:
The oscillator continues to run
The Program Counter (R2) is set to all "0".
The contents of the stack are cleared to all “0”.
All I/O port pins are configured at input mode (high-impedance state).
The Watchdog Timer and prescaler are cleared.
When power is switched on, R1 is cleared.
The control register bits are set according to the table shown in Section 6.4.3,
Summary of the Registers Initialized Values.
Executing the “SLEP” instruction will assert the Sleep (power down) mode. While
entering Sleep mode, the Oscillator, TCC, and Timer 1 are stopped. The WDT (if
enabled) is cleared but keeps on running. Wake-up is then generated (in RC mode,
Wake-up time is WSTO + 8 clocks; in High XTAL mode, Wake-up time is WSTO+ 510
clocks). The controller can be awakened by any of the following events:
1) External reset input on /RESET pin
2) WDT time-out (if enabled)
3) Port input status changes (if ICWE is enabled)
4) External Interrupt status changes (if INTWK is enabled)
5) Low Voltage Detector (if LVDWE is enabled)
6) A/D conversion completed (if ADWE is enabled)
7) I2C received data while acting as Slave device (if I2CWE is enabled)
8) Comparator output status changes (if the corresponding control bit is enabled)
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
53
EM78P374N
8-bit Microcontroller
The first two events (1 and 2) will cause the MCU to reset. The T and P flags of R3 can
be used to determine the source of the reset (Wake-up). Events 3~8 are considered
the continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) decides whether or not the controller branches to the interrupt vector
following Wake-up. If ENI is executed before SLEP, the instruction will begin to execute
from the Address 0x03~0x36 of each interrupt vector after Wake-up. If DISI is
executed before SLEP, the execution will restart from the instruction right next to SLEP
after Wake-up. From Sleep to Normal mode, Wake-up time is 510 clocks + warm-up
time with Crystal oscillator and 8 clocks (Fm) + warm-up time with IRC oscillator. From
Idle to Green mode, only warm-up time is needed. From Sleep to Green mode the
wake-up time is 8 clocks (Fs) + warm-up time.
One or more of Events 3 to 9 can be enabled before entering Sleep mode. That is:
a) If WDT is enabled before SLEP, all Wake-up bits are disabled. Hence, the MCU can
be awakened only by Events 1 or 2. Refer to Section 6.5, Interrupt; for further
details.
b) If Port Input Status Change is used to Wake-up the MCU, the Bank 0-0x12 register
must be enabled and the WDT disabled before SLEP. The MCU can then be
awakened by Event 3.
c) If External Interrupt Status Change is used to Wake-up the MCU, the INTWK bit must
be enabled and the WDT disabled before SLEP. The MCU can then be awakened
by Event 4
d) If Low Voltage Detector is used to Wake-up the MCU, the LVDWK bit of Bank 0-R10
register must be enabled and the WDT disabled before SLEP. The MCU can then
be awakened by Event 5.
e) If AD Conversion Completed is used to Wake-up the MCU, the ADWK bit of Bank
0-R10 register must be enabled and the WDT disabled before SLEP. The MCU can
then be awakened by Event 6.
f) When I2C is acting as Slave device and it is used to Wake-up the MCU after
receiving data, the I2CWK bit of Bank 0-R11 register must be enabled and the WDT
disabled by software before SLEP. The MCU can then be awakened by Event 7.
g) If Comparator Output Status Change is used to Wake-up the MCU, the CMP2WK bit
of Bank 0-0x10 register must be enabled and the WDT disabled before SLEP. The
MCU can then be awakened by Event 8.
54
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.4.1 Summary of Wake-up and Interrupt Modes
Sleep Mode
Idle Mode
DISI ENI
Green Mode
DISI ENI
Normal Mode
DISI ENI
Wake-up
Signal
Condition
Signal
DISI
ENI
TCIE = 0
TCIE = 1
TCIE = 0
TCIE = 1
Wake-up is invalid
Wake up Wake up
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
TCC (Used
as Timer)
Wake-up is invalid
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Wake-up is invalid Wake-up is invalid
Wake up Wake up Wake up Wake up
TCC (Used
as Counter)
+
+
+
+
Next
+
Next
+
Next
Interrupt
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Vector
PWMxPIE=0
PWMxPIE=1
PWMxDIE = 0
PWMxDIE = 1
Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
PWMA/B/C
When Timer
A/B/C
match
PRDA/B/C
Wake up Wake up
Wake-up is invalid
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Vector
Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
PWMA/B/C
(When
Timer A/B/C
match
Wake up
Wake-up is invalid
Wake-up is invalid
Wake up
+
Next
+
Next
+
+ Next
Instruction
Interrupt Instruction Interrupt Instruction Interrupt
Vector
DTA/B/C)
Vector
Vector
TC1/2/3IE = 0
TC1/2/3IE = 1
Wake-up is invalid
Wake up Wake up
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
TC1
Interrupt
(Used as
Timer)
+
+
Next
+
Next
+
Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
TC1/2/3IE = 0 Wake-up is invalid Wake-up is invalid
Wake up Wake up Wake up Wake up
TC1
Interrupt
(Used as
Counter)
+
Next
+
+
Next
+
Next
+
Next
+
TC1/2/3IE = 1
Interrupt
Interrupt Instruction Interrupt Instruction Interrupt
Instruction Vector Instruction Vector
Vector
Vector
INTWKx = 0,
EXIEx = 0
Wake-up is invalid Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
INTWKx = 0,
EXIEx = 1
Next
+
Next
+
Wake-up is invalid Wake-up is invalid
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
External
INT
Wake up
+
Next Instruction
Wake up
+
Next Instruction
INTWKx = 1,
EXIEx = 0
Wake up
+
Wake up Wake up
Wake up
+
+
INTWKx = 1,
EXIEx = 1
+
+
+
Next
Next
Next
Instruction
Interrupt
Vector
Interrupt
Vector
Next
Interrupt
Interrupt Instruction
Vector
Instruction
Instruction Vector
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
55
EM78P374N
8-bit Microcontroller
(Continuation)
Sleep Mode
DISI ENI
Idle Mode
DISI ENI
Green Mode
Normal Mode
DISI ENI
Wake-up
Signal
Condition
Signal
DISI
ENI
ICWKPx = 0
PxICIE = 0
Wake-up is invalid Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
ICWKPx = 0
PxICIE = 1
Next
+
Next
+
Wake-up is invalid Wake-up is invalid
Instruction Interrupt Instruction Interrupt
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
Pin change
Wake up
+
Wake up
+
ICWKPx = 1
PxICIE = 0
Next Instruction
Next Instruction
Wake
Wake up
up +
Interrupt
Instruction
Vector
Wake up
Wake up
+
ICWKPx = 1,
PxICIE = 1
Next
+
Next
+
+ Next
+ Next
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
CMPxWK=0
CMPxIE=0
Wake-up is invalid Wake-up is invalid
Wake-up is invalid Wake-up is invalid
CMPxWK=0
CMPxIE=1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
Comparator x
(Comparator
output status
change, x=2)
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
CMPxWK=1
CMPxIE=0
Wake up
+ Next Instruction
Wake up
+ Next Instruction
Wake
Wake up
up +
Wake up
Wake up
+
CMPxWK=1
CMPxIE=1
Next
+
Next
+
+ Next
+ Next
Interrupt
Instruction
Vector
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
ADWK = 0
ADIE = 0
Wake-up is invalid Wake-up is invalid
Wake-up is invalid Wake-up is invalid
Interrupt is invalid
Interrupt
Interrupt is invalid
Interrupt
ADWK = 0
ADIE = 1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
AD
Conversion
complete
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
ADWK = 1
ADIE = 0
Wake up
+ Next Instruction
Wake up
+ Next Instruction
Wake
Wake up
up +
Interrupt
ADWK = 1
ADIE = 1
Next
+
Next
+
Next
+
+ Next
Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
I2CWK=0
I2CRIE=0
Wake-up is invalid Wake-up is invalid
Wake-up is invalid Wake-up is invalid
I2CWK=0
I2CRIE=1
Next
+
Next
+
Instruction Interrupt Instruction Interrupt
I2C
(Slave mode)
Vector
Interrupt is invalid
Interrupt
Vector
Interrupt is invalid
Interrupt
I2CWK=1
I2CRIE=0
Wake up
+ Next Instruction
Wake up
+ Next Instruction
Wake
Wake up
up +
Wake up
Wake up
I2CWK=1
I2CRIE=1
+
Next
+
Next
+
+ Next
+ Next
Interrupt
Instruction
Vector
Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
56
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
Sleep Mode
DISI ENI
Idle Mode
DISI ENI
Green Mode
DISI ENI
Normal Mode
DISI ENI
Wake-up
Signal
Condition
Signal
LVDWK = 0
LVDIE = 0
Wake-up is invalid Wake-up is invalid
Interrupt is invalid Interrupt is invalid
Interrupt
+
Interrupt
+
LVDWK = 0
LVDIE = 1
Next
Next
Wake-up is invalid Wake-up is invalid
Instruction Interrupt Instruction Interrupt
Vector Vector
Low Voltage
Detector
LVDWK = 1
LVDIE = 0
Wake up
+ Next Instruction
Wake up
+ Next Instruction
Interrupt is invalid. Interrupt is invalid.
Wake
Wake up
up +
Interrupt
Interrupt
+
Interrupt
+
LVDWK = 1
LVDIE = 1
Next
+
Next
Next
+ Next
Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt
Instruction
Vector
Vector
Vector
Vector
Low Voltage
Reset
Wake up + Reset
Wake up + Reset
Wake up + Reset
Reset
Reset
WDT Timeout
Wake up + Reset
Reset
Reset
6.4.2 Status of RST, T, and P of Status Register
A reset condition is initiated by one of the following events:
1) Power-on condition,
2) High-low-high pulse on /RESET pin, and
3) Watchdog timer time-out.
4) LVR occur
The values of T and P, as listed in the following table are used to check how the MCU
wakes up. The next table shows the events that may affect the status of T and P.
Values of RST, T and P after Reset:
Reset Type
T
1
P
1
Power-on
/RESET during Operating mode
P
1
P
0
/RESET Wake-up during Sleep mode
WDT during Operating mode
0
P
0
WDT Wake-up during Sleep mode
Wake-up on pin change during Sleep mode
0
1
0
P: Previous status before reset
Status of T and P being affected by Events:
Event
T
P
Power-on
1
1
0
1
1
1
1
WDTC instruction
WDT time-out
P
0
SLEP instruction
Wake-up on pin change during Sleep mode
0
P: Previous value before reset
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
57
EM78P374N
8-bit Microcontroller
VDD
D
Q
CLK
Oscillator
CLK
CLR
Power-on Reset
Low Voltage Reset
Setup time
WDTE
WDT
WDT Timeout
Reset
/RESET
Figure 6-5 Controller Reset Block Diagram
6.4.3 Summary of Register Initial Values after Reset
Legend: U: Unknown or don’t care
C: Same with Code option
P: Previous value before reset
t: Check tables under Section 6.4.2
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
-
-
-
-
-
-
-
-
U
U
U
U
U
U
U
U
R0
(IAR)
/RESET and
WDT
0x00
0x01
0x02
0x03
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Wake-up from
Sleep/Idle
Bit Name
Power-on
-
-
-
SBS0
0
-
GBS2
0
GBS1
0
GBS0
0
0
0
0
0
R1
(BSR)
/RESET and
WDT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
Bit Name
Power-on
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
R2
(PCL)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
INT
0
-
-
T
1
P
1
Z
DC
U
C
U
0
0
U
R3
(SR)
/RESET and
WDT
0
0
0
0
0
t
t
t
t
P
P
P
P
P
P
Wake-up from
Sleep/Idle
P
58
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
RSR7
U
RSR6
U
RSR5
U
RSR4
U
RSR3
U
RSR2
U
RSR1
U
RSR0
U
R4
(RSR)
/RESET and
WDT
0x04
0X05
0x06
0x07
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Wake-up from
Sleep/Idle
Bit Name
Power-on
P57
0
P56
0
P55
0
P54
0
P53
0
P52
0
P51
0
P50
0
Bank 0, R5
(Port 5)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
P67
0
P66
0
P65
0
P64
0
P63
0
P62
0
P61
0
P60
0
Bank 0, R6
(Port 6)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
P75
0
P74
0
P73
0
P72
0
P71
0
P70
0
0
0
Bank 0, R7
(Port 7)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
IOC57 IOC56 IOC55 IOC54 IOC53 IOC52 IOC51 IOC50
1
1
1
1
1
1
1
1
Bank 0, RB
(IOCR5)
/RESET and
WDT
0X0B
0x0C
0X0D
0x0E
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60
1
1
1
1
1
1
1
1
Bank 0, RC
(IOCR6)
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
IOC75 IOC74 IOC73 IOC72 IOC71 IOC70
0
0
1
1
1
1
1
1
Bank 0, RD
(IOCR7)
/RESET and
WDT
0
0
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
CPUS
1
IDLE
1
-
-
-
-
RCM1 RCM0
0
0
0
0
C
C
Bank 0, RE
(OMCR)
/RESET and
WDT
1
1
0
0
0
0
C
C
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
59
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
EIES54
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
Bank 0, RF
(IESCR)
0x0F
0x10
0x11
/RESET and
WDT
0
0
1
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
Bit Name
Power-on
CMP2WK
0
-
LVDWK ADWK
-
-
-
-
0
0
0
0
0
0
0
0
0
Bank 0, R10
(WUCR1)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
I2CWK
0
-
-
0
0
0
0
0
0
0
Bank 0, R11
(WUCR2)
/RESET and
WDT
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
Bit Name
Power-on
-
-
ICWKP6 ICWKP5
-
-
INTWK5
0
-
0
0
0
0
0
0
0
0
0
/RESET and
WDT
Bank 0, R12
(WUCR3)
0
0
0
0
0
0
0x12
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0X13 Bank 0, R13 /RESET and
WDT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
Bit Name
CMP2SF
0
-
LVDSF ADSF
-
-
-
TCSF
0
Power-on
0
0
0
0
0
0
0
0
Bank 0, R14
(SFR1)
0X14
0X15
/RESET and
WDT
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
-
TC1DSF
0
0
0
0
0
0
0
0
Bank 0, R15
(SFR2)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
60
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWM
PWM
PWM PWMB PWM
PWM
-
-
CPSF CDSF BPSF
DSF
0
APSF ADSF
Power-on
0
0
0
0
0
0
0
0
0
Bank 0, R16
(SFR3)
0X16
/RESET and
WDT
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
P6ICSF P5ICSF
-
I2CSTPSF I2CRSF I2CTSF
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R17
(SFR4)
/RESET and
WDT
0X17
0X18
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
EXSF5
0
-
-
-
0
0
0
0
0
0
0
Bank 0, R18
(SFR5)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
CMP2IE
0
-
LVDIE
0
ADIE
0
-
-
-
TCIE
0
0
0
0
0
Bank 0, R1B
(IMR1)
/RESET and
WDT
0X1B
0X1C
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
-
TC1DIE
0
0
0
0
0
0
0
0
Bank 0, R1C
(IMR2)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
PWM
CPIE
PWM
CDIE
PWM
BPIE
PWM
BDIE
PWM
APIE
PWM
ADIE
Bit Name
Power-on
-
-
0
0
0
0
0
0
0
0
0
0
Bank 0, R1D
(IMR3)
0X1D
0X1E
/RESET and
WDT
0
0
0
0
0
0
Wake-up from
Sleep/Idle
0
0
P
P
P
P
P
P
Bit Name
Power-on
-
-
P6ICE P5ICE
-
I2CSTPIE I2CRIE I2CTIE
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R1E
(IMR4)
/RESET and
WDT
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
61
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
-
-
-
-
EXIE5
0
-
-
-
0
0
0
0
0
0
0
Bank 0, R1F
(IMR5)
/RESET and
WDT
0X1F
0X21
0X22
0X23
0X24
0X25
0X26
0X27
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
WDTE
0
-
-
-
PSWE WPSR2 WPSR1 WPSR0
0
0
0
0
0
0
0
Bank 0, R21
(WDTCR)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
TCCS
0
TS
0
TE
0
PSTE TPSR2 TPSR1 TPSR0
0
0
0
0
0
Bank 0, R22
(TCCCR)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
TCC7
0
TCC6
0
TCC5
0
TCC4
0
TCC3
0
TCC2
0
TCC1
0
TCC0
0
Bank 0, R23
(TCCD)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
TC1S TC1RC TC1SS1
-
TC1FF TC1OMS TC1IS1 TC1IS0
0
0
0
0
0
0
0
0
Bank 0, R24
(TC1CR1)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
TC1M2 TC1M1 TC1M0 TC1SS0 TC1CK3 TC1CK2 TC1CK1 TC1CK0
0
0
0
0
0
0
0
0
Bank 0, R25
(TC1CR2)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1 TC1DA0
0
0
0
0
0
0
0
0
Bank 0, R26
(TC1DA)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1 TC1DB0
0
0
0
0
0
0
0
0
Bank 0, R27
(TC1DB)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
62
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit Name
Bit 7
Bit 6
IMS
0
Bit 5
ISS
0
Bit 4
STOP
0
Bit 3
Bit 2
ACK
0
Bit 1
Bit 0
STROBE
/PEND
SAR_
EMPTY
FULL EMPTY
Power-on
0
0
0
0
0
0
Bank 0, R30
0X30
/RESET and
(I2CCR1)
0
0
0
0
0
0
WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
I2CBF GCEN
-
BBF
0
I2CTS1 I2CTS0 I2CCS I2CEN
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R31
(I2CCR2)
/RESET and
WDT
0X31
0X32
0X33
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
SA6
0
SA5
0
SA4
0
SA3
0
SA2
0
SA1
0
SA0
0
IRW
0
Bank 0, R32
(I2CSA)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
0
Bank 0, R33
(I2CDB)
/RESET and
WDT
0
0
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
Bit Name
Power-on
DA7
1
DA6
1
DA5
1
DA4
1
DA3
1
DA2
1
DA1
1
DA0
1
Bank 0, R34
(I2CDAL)
/RESET and
WDT
0X34
0X35
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
DA9
1
DA8
1
0
0
0
0
0
0
Bank 0, R35
(I2CDAH)
/RESET and
WDT
0
0
0
0
0
0
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
63
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
C2S0
0
Bit 3
Bit 2
Bit 1
Bit 0
SDPWMB
0
Bit Name
C2RS CP2OUT C2S1
-
-
-
Power-on
0
0
0
0
0
0
0
0
0
Bank 0, R3B
(CMP2CR)
/RESET and
WDT
0X3B
0X3C
0X3D
0X3E
0X3F
0X40
0X41
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
CIRL11 CIRL10
-
0
0
0
0
0
0
0
0
0
0
Bank 0, R3C
(CMP3CR)
/RESET and
WDT
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bank 0, R3D
(CMP4CR)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
CKR2
0
CKR1 CKR0 ADRUN
ADP
0
ADOM SHS1
SHS0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R3E
(ADCR1)
/RESET and
WDT
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
ADIM ADCMS VPIS1
VPIS0 VREFP
-
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R3F
(ADCR2)
/RESET and
WDT
0
0
0
Wake-Up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
ADIS4 ADIS3
ADIS2 ADIS1 ADIS0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R40
(ADISR)
/RESET and
WDT
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
ADE7
0
ADE6 ADE5 ADE4
ADE3
0
ADE2
0
ADE1
0
ADE0
0
0
0
0
0
0
0
Bank 0, R41
(ADER1)
/RESET and
WDT
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
64
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE8
0
Bit Name
-
-
ADE13 ADE12 ADE11 ADE10 ADE9
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
Bank 0, R42
(ADER2)
/RESET and
WDT
0X42
0X43
0X44
0X45
0X46
0X08
0X09
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
ADD7
U
ADD6
U
ADD5
U
ADD4
U
ADD3
U
ADD2
U
ADD1
U
ADD0
U
Bank 0, R43
(ADDL)
/RESET and
WDT
P
P
P
P
P
P
P
0
P
0
P
P
P
P
P
P
Wake-up from
Sleep/Idle
Bit Name
Power-on
ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9
ADD8
U
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Bank 0, R44
(ADDH)
/RESET and
WDT
P
P
Wake-up from
Sleep/Idle
0
0
0
P
P
P
P
Bit Name
Power-on
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
0
0
0
0
0
0
0
0
Bank 0, R45
(ADCVL)
/RESET and
WDT
P
P
P
P
P
P
P
P
Wake-up from
Sleep/Idle
0
0
0
P
P
P
P
P
Bit Name
Power-on
ADCV15 ADCV14 ADCV13 ADCV12 ADCV11 ADCV10 ADCV9 ADCV8
0
0
0
0
0
0
0
0
Bank 0, R46
(ADCVH)
/RESET and
WDT
P
P
P
P
P
P
P
P
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PH57
1
PH56
1
PH55
1
PH54
1
PH53
1
PH52
1
PH51
1
PH50
1
Bank 1, R8
(P5PHCR)
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
PH66
1
PH65
1
PH64
1
PH63
1
PH62
1
PH61
1
PH60
1
1
Bank 1, R9
(P6PHCR)
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
65
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
-
-
-
-
-
-
P7HPH P7LPH
1
1
1
1
1
1
1
1
1
1
Bank 1, RA
(P7PHCR)
/RESET and
WDT
0X0A
0X0B
0X0C
0X0D
0X0E
0X0F
0X10
0X11
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PL57
1
PL56
1
PL55
1
PL54
1
PL53
1
PL52
1
PL51
1
PL50
1
Bank 1, RB
(P5PLCR)
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PL67
1
PL66
1
PL65
1
PL64
1
PL63
1
PL62
1
PL61
1
PL60
1
Bank 1, RC
(P6PLCR)
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
P7HPL P7LPL
1
1
1
1
1
1
1
1
Bank 1, RD
(P7PLCR)
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
H57
1
H56
1
H55
1
H54
1
H53
1
H52
1
H51
1
H50
1
Bank 1, RE
(P5HDSCR)
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
H67
1
H66
1
H65
1
H64
1
H63
1
H62
1
H61
1
H60
1
Bank 1, RF
(P6HDSCR)
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
P7HHDS P7LHDS
1
1
1
1
1
1
1
1
Bank 1, R10
(P7HDSCR))
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
OD57
0
OD56
0
OD55
0
OD54
0
OD53
0
OD52
0
OD51
0
OD50
0
Bank 1, R11
(P5ODCR)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
66
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
-
OD66
0
OD65
0
OD64
0
OD63
0
OD62
0
OD61
0
OD60
0
0
Bank 1, R12
(P6ODCR)
/RESET and
WDT
0X12
0X13
0X16
0X17
0X18
0X19
0X1A
0X1B
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
P7HOD P7LOD
0
0
0
0
0
0
0
0
Bank 1, R13
(P7ODCR)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
PWMCS PWMBS PWMAS
0
0
0
0
0
0
0
0
Bank 1, R16
(PWMSCR)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PWMAE IPWMAE
-
-
TAEN
0
TAP2
0
TAP1
0
TAP0
0
0
0
0
0
Bank 1, R17
(PWMACR)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PRDA7 PRDA6 PRDA5 PRDA4 PRDA3 PRDA2 PRDA1 PRDA0
0
0
0
0
0
0
0
0
Bank 1, R18
(PRDAL)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PRDA15 PRDA14 PRDA13 PRDA12 PRDA11 PRDA10 PRDA9 PRDA8
0
0
0
0
0
0
0
0
Bank 1, R19
(PRDAH)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
DTA7
0
DTA6
0
DTA5
0
DTA4
0
DTA3
0
DTA2
0
DTA1
0
DTA0
0
Bank 1, R1A
(DTAL)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
DTA15 DTA14 DTA13 DTA12 DTA11 DTA10 DTA9
DTA8
0
0
0
0
0
0
0
0
Bank 1, R1B
(DTAH)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
0
0
P
P
P
P
P
P
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
67
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
TMRA7 TMRA6 TMRA5 TMRA4 TMRA3 TMRA2 TMRA1 TMRA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Bank 1, R1C
(TMRAL)
/RESET and
WDT
0X1C
0X1D
0X1E
0X1F
0X20
0X21
0X22
0X23
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
TMRA15 TMRA14 TMRA13 TMRA12 TMRA11 TMRA10 TMRA9 TMRA8
0
0
0
0
0
0
0
0
Bank 1, R1D
(TMRAH)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PWMBE IPWMBE
-
-
TBEN
0
TBP2
0
TBP1
0
TBP0
0
0
0
0
0
Bank 1, R1E
(PWMBCR)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-On
PRDB7 PRDB6 PRDB5 PRDB4 PRDB3 PRDB2 PRDB1 PRDB0
0
0
0
0
0
0
0
0
Bank 1, R1F
(PRDBL)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PRDB15 PRDB14 PRDB13 PRDB12 PRDB11 PRDB10 PRDB9 PRDB8
0
0
0
0
0
0
0
0
Bank 1, R20
(PRDBH)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
DTB7
0
DTB6
0
DTB5
0
DTB4
0
DTB3
0
DTB2
0
DTB1
0
DTB0
0
Bank 1, R21
(DTBL)
/RESET and
WDT
0
0
0
0
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
Bit Name
Power-on
DTB15 DTB14 DTB13 DTB12 DTB11 DTB10 DTB9
DTB8
0
0
0
0
0
0
0
0
Bank 1, R22
(DTBH)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
TMRB7 TMRB6 TMRB5 TMRB4 TMRB3 TMRB2 TMRB1 TMRB0
0
0
0
0
0
0
0
1
Bank 1, R23
(TMRBL)
/RESET and
WDT
0
0
0
0
0
0
0
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
68
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-on
TMRB15 TMRB14 TMRB13 TMRB12 TMRB11 TMRB10 TMRB9 TMRB8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bank 1, R24
(TMRBH)
/RESET and
WDT
0X24
0X25
0X26
0X27
0X28
0X29
0X2A
0X2B
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PWMCE IPWMCE
-
-
TCEN
0
TCP2
0
TCP1
0
TCP0
0
0
0
0
0
Bank 1, R25
(PWMCCR)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PRDC7 PRDC6 PRDC5 PRDC4 PRDC3 PRDC2 PRDC1 PRDC0
0
0
0
0
0
0
0
0
Bank 1, R26
(PRDCL)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
PRDC15 PRDC14 PRDC13 PRDC12 PRDC11 PRDC10 PRDC9 PRDC8
0
0
0
0
0
0
0
0
Bank 1, R27
(PRDCH)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
DTC7
0
DTC6
0
DTC5
0
DTC4
0
DTC3
0
DTC2
0
DTC1
0
DTC0
0
Bank 1, R28
(DTCL)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
DTC15 DTC14 DTC13 DTC12 DTC11 DTC10 DTC9
DTC8
0
0
0
0
0
0
0
0
Bank 1, R29
(DTCH)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
TMRC7 TMRC6 TMRC5 TMRC4 TMRC3 TMRC2 TMRC1 TMRC0
0
0
0
0
0
0
0
1
Bank 1, R2A
(TMRCL)
/RESET and
WDT
0
0
0
0
0
0
0
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 TMRC9 TMRC8
0
0
0
0
0
0
0
0
Bank 1, R2B
(TMRCH)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
69
EM78P374N
8-bit Microcontroller
(Continuation)
Addr. Bank Name Reset Type
Bit 7
TB7
0
Bit 6
TB6
0
Bit 5
TB5
0
Bit 4
TB4
0
Bit 3
TB3
0
Bit 2
TB2
0
Bit 1
TB1
0
Bit 0
TB0
0
Bit Name
Power-on
Bank 1, R45
/RESET and
0X45
0
0
0
0
0
0
0
0
(TBPTL)
WDT
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
HLB
0
-
-
-
TB11
0
TB10
0
TB9
0
TB8
0
0
0
0
Bank 1, R46
(TBPTH)
/RESET and
WDT
0X46
0X48
0X49
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
PC11
0
PC10
0
PC9
0
PC8
0
0
0
0
0
Bank 1, R48
(PCH)
/RESET and
WDT
0
0
0
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
LVDEN
0
-
LVDS1 LVDS0 LVDB
-
-
-
0
0
0
0
0
0
0
0
0
0
Bank 1, R49
(LVDCR)
/RESET and
WDT
0
0
0
0
0
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
/RESET and
WDT
0X4A Bank 1, R4A
0X4B Bank 1, R4B
0X4C Bank 1, R4C
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
/RESET and
WDT
1
1
1
1
1
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
P
P
Bit Name
Power-on
-
-
-
-
-
-
-
-
1
0
1
1
1
1
1
1
/RESET and
WDT
1
0
0
1
1
1
0
1
1
1
Wake-up from
Sleep/Idle
P
P
P
P
P
P
70
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.5 Interrupt
The EM78P374N has 16 interrupts as listed below:
Interrupt Source
Internal /
External
Enable Condition
Int. Flag
Int. Vector
Priority
Reset
-
-
0
High 0
External INT
ENI + EXIE=1
ENI +ICIE=1
ENI + TCIE=1
EXSF
2
4
6
1
2
3
External Pin change
ICSF
Internal
Internal
TCC
LVD
TCSF
ENI+LVDEN &
LVDIE=1
LVDSF
8
4
External Comparator 2
ENI+CMP2IE=1
ENI + ADIE=1
ENI + TC1IE=1
CMP2SF
ADSF
E
5
6
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
AD
10
12
14
16
1A
1C
1E
24
26
2A
2C
TC1 (TCXDA)
PWMPA
TC1SF
7
ENI+PWMPAIE=1 PWMPASF
ENI+PWMDAIE=1 PWMDASF
8
PWMDA
I2C Transmit
I2C Receive
I2CSTOP
PWMPB
9
ENI+ I2CTIE
ENI+ I2CRIE
ENI+ I2CSTPIE
I2CTSF
10
11
12
13
14
15
16
I2CRSF
I2CSTPSF
ENI+PWMPBIE=1 PWMPBSF
ENI+PWMDBIE=1 PWMDBSF
ENI+PWMPCIE=1 PWMPCSF
ENI+PWMDCIE=1 PWMDCSF
PWMDB
PWMPC
PWMDC
Bank 0 R14 ~ R1F are the interrupt status registers that record the interrupt requests in
the relative flags/bits. Bank 0 R1B ~ R1F are the Interrupt Mask registers. The global
interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When
one of the enabled interrupts occurs, the next instruction will be fetched from individual
address. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICSF bit delete) in the Interrupt Status Register is set regardless of the
status of its mask bit or the execution of ENI. The RETI instruction ends the interrupt
routine and enables the global interrupt (the execution of ENI).
External interrupt is equipped with digital noise rejection circuit (input pulse of less than
four system clock time is eliminated as noise if code option NRHL=0), but in Low
XTAL oscillator (LXT) mode, the noise rejection circuit is disabled. When an
interrupt (Falling edge) is generated by the External interrupt (if enabled), the next
instruction will be fetched from Address 003H.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
71
EM78P374N
8-bit Microcontroller
Before the interrupt subroutine is executed, the contents of ACC, R3, and R4 registers
are saved by hardware. If another interrupt occurs, the ACC, R3, and R4 registers will
be replaced by the new interrupt. After the interrupt service routine is finished, ACC,
R3, and R4 registers are restored.
When a reset (POR, LVR, WDT, and /RESET) occurs, the contents of the stack are
cleared to all “0”.
Interrupt
Interrupt sources
occurs
ACC
R1
STACKACC
ENI/DISI
STACKR1
STACKR3
STACKR4
R3
R4
RETI
Figure 6-6a Interrupt Backup Diagram
VCC
P
R
IRQn
Q
D
/IRQn
CLK
INT
_
Q
RFRD
IRQm
C
L
RF
ENI/DISI
IOD
P
R
Q
D
CLK
_
Q
C
L
IOCFWR
IOCF
/RESET
IOCFRD
RFWR
Figure 6-6b Interrupt Input Circuit
72
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.6 Analog-to-Digital Converter (ADC)
R_Bank Addr.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CKR2
CKR1
CKR0 ADRUN
ADP
ADOM
R/W
SHS1
R/W
SHS0
R/W
-
Bank 0 0x3E ADCR1
R/W
R/W
R/W
ADIM
R/W
-
R/W
R/W
-
-
ADCMS VPIS1
VPIS0
R/W
VREFP
R/W
Bank 0 0x3F
Bank 0 0x40
Bank 0 0x41
Bank 0 0x42
Bank 0 0x44
Bank 0 0x45
ADCR2
ADISR
ADER1
ADER2
ADDH
ADDL
-
-
R/W
ADIS4
R/W
R/W
ADIS3
R/W
-
-
-
ADIS2
R/W
ADIS1
R/W
ADIS0
R/W
ADE0
R/W
ADE8
R/W
ADD8
R
-
-
-
ADE7
ADE6
ADE5
R/W
ADE4
R/W
ADE3
R/W
ADE2
R/W
ADE1
R/W
R/W
R/W
-
-
-
-
ADE13 ADE12 ADE11 ADE10
R/W R/W R/W R/W
ADE9
R/W
ADD15 ADD14 ADD13 ADD12 ADD11 ADD10
ADD9
R
R
ADD7
R
R
ADD6
R
R
ADD5
R
R
ADD4
R
R
ADD3
R
R
ADD2
R
ADD1
R
ADD0
R
ADCD15 ADCD14 ADCD13 ADCD12 ADCD11 ADCD10 ADCD9 ADCD8
Bank 0 0x46 ADCDH
Bank 0 0x45 ADCDL
Bank 0 0x10 WUCR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADCD7 ADCD6 ADCD5 ADCD4 ADCD3 ADCD2 ADCD1 ADCD0
R/W
R/W
R/W
R/W
ADWK
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ADSF
R/W
Bank 0 0x15
Bank 0 0x1B
ISR1
IMR1
ADIE
R/W
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
73
EM78P374N
8-bit Microcontroller
OPA2
VDD
VREFP
¼ VDD PowerDet.
AD13
ADC
Power Down
(Successive Approximation)
Start to Convert
AD9
AD7
Fsub
Fmain/1
Fmain/2
Fmain/4
Fmain/8
8 to 1
MUX
Fmain/16
Fmain/32
Fmain/64
AD0
7 - 0
15 - 8
4~0
7
6
5
4
4
11 10 9 8 7 6 5 4 3 2 1 0
4
3
1 0
ADER1
ADER2
ADIS
ADCR1
IMR
ADDH
ADDL
ADCR1
ADCR2
ISR
DATA BUS
Figure 6-7 AD Converter Functional Block Diagram
This is a 12-bit successive approximation register analog to digital converter (SAR ADC)
with two reference voltages. The positive reference voltage can select either internal
AVDD internal voltage sources or external input pin by setting the VREFP and VPIS[1:0]
bits in ADCR2. Connecting to external positive reference voltage provides more
accuracy than using internal AVDD.
6.6.1 ADC Data Register
When the AD conversion is completed, the result is loaded into the ADDH and ADDL.
The ADSF is set if ADIE is enabled.
6.6.2 A/D Sampling Time
The accuracy, linearity, and speed of the successive approximation AD converter are
dependent on the properties of the ADC. The source impedance and the internal
sampling impedance directly affect the time required to charge the sample and hold
capacitor. The application program controls the length of the sample time to meet the
specified accuracy. The maximum recommended impedance for the analog source is
10 K at VDD=5V. After the analog input channel is selected; this acquisition time
must be done before AD conversion can be started.
74
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.6.3 A/D Conversion Time
CKR [2:0] select the conversion time, in terms of instruction cycles (TAD). This allows
the MCU to run at maximum frequency without sacrificing the accuracy of the AD
conversion. The following two tables are examples that show the relationship between
TAD and the maximum operating frequencies. The TAD is 0.5 µs for 3V~5.5V and TAD is
2 µs for 2.5V~3V.
Vdd = 3V ~ 5.5V
Conversion
Time
(SHS[1~0]=10)
System
Mode
CKR
[2:0]
Max. F MAIN
(Vdd=3V~5.5V)
FAD =1/TAD
000
001
010
011
100
101
FMain/16
FMain/8
FMain/4
FMain/2
FMain/64
FMain/32
-
16 MHz
8 MHz
4 MHz
-
-
10 s
10 s
10 s
-
Normal
Mode
-
-
110
111
xxx
FMain/1
FSub
FSub
2 MHz
10 s
-
-
-
-
Green Mode
Vdd = 2.5V ~ 3V
Conversion
Time
(SHS[1~0]=10)
System
Mode
CKR
[2:0]
Max. F MAIN
(Vdd=2.5V~3V)
FAD =1/TAD
000
001
010
011
100
101
110
111
xxx
FMain/16
FMain/8
FMain/4
FMain/2
FMain/64
FMain/32
FMain/1
FSub
8 MHz
4 MHz
2 MHz
1 MHz
-
40 s
40 s
40 s
40 s
-
Normal
Mode
16 MHz
0.5 MHz
-
40 s
40 s
-
Green Mode
FSub
-
-
6.6.4 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD
conversion remains operational during Sleep mode. While the SLEP instruction is
being executed, all the MCU operations will stop except for the Oscillator, TCC, TC1,
PWMA~C timers, and AD conversion.
The AD Conversion is considered completed as determined by:
1) The ADRUN bit of the Bank 0-R3E register is cleared to “0”.
2) The ADSF bit of the Bank 0-R15 register is set to “1”.
3) The ADWK bit of the Bank 0-R10 register is set to “1”. Wakes up from ADC
conversion (where it remains in operation during Sleep mode).
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
75
EM78P374N
8-bit Microcontroller
4) Wake up and execute the next instruction if the ADIE bit of the Bank 0-R1B is
enabled and the “DISI” instruction is executed.
5) Wake up and enter into Interrupt vector if the ADIE bit of the Bank 0-R1B is enabled
and the “ENI” instruction is executed.
6) Enter into an Interrupt vector if the ADIE bit of the Bank 0-R1B is enabled and the
“ENI” instruction is executed.
The results are fed into the ADDL and ADDH registers when the conversion is
completed. If the ADWK is enabled, the device will wake-up. Otherwise, AD
conversion is shut off, no matter what the status of the ADPD bit is.
6.6.5 Programming Process/Considerations
Follow these steps to obtain data from the ADC:
1) Write to the sixteen bits (ADE [13:0]) on the Bank0-R41~R42 (ADER1~2) register to
define the characteristics of P50~P57 and P71~P75 (digital I/O, analog channels, or
voltage reference pin)
2) Write to the Bank 0-R3E/ADCON register to configure the AD module:
a) Select the ADC input channel (ADIS[4:0))
b) Define the AD conversion clock rate (CKR [2:0])
c) Select the VREFS input source of the ADC
d) Set the ADPD bit to “1” to begin sampling
3) Set the ADWK bit, if the Wake-up function is employed
4) Set the ADIE bit, if the Interrupt function is employed
5) Write “ENI” instruction, if the Interrupt function is employed
6) Set the ADRUN bit to “1”
7) Write “SLEP” instruction or Polling
8) Wait for either Wake-up or for the ADRUN bit to be cleared (“0” value), whereby
Status flag (ADSF) is set to “1,” or ADC interrupt occurs.
9) Read the ADDL and ADDH conversion data registers. If the ADC input channel
changes at this time, the ADDL and ADDH values can be cleared to “0.”
10) Clear the status flag (ADSF)
11) For the next conversion, go to Step 1 or Step 2 as required. At least two TAD are
required before the next acquisition starts. On the other hand, the timing setting
ADRUN = 1 must be later than the timing setting ADPD=1, and the difference
between the two timing is also two TAD.
NOTE
In order to obtain accurate values, it is necessary to avoid any data transition on the
I/O pins during AD conversion
76
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
CO
External
Volt. Ref.
Int. VREF.
Internal
VDD
SW1
SW0
CIN+
CIN-
CMP &
OPAmp
Analog
MUX
Internal
VDD
Ref. In
3R
R
Signal
In
Analog
MUX
12 bits
ADC
To
Kernel
ADC[0:15]
Pins
Figure 6-8 ADC, CMP OPAmp, and VDD Detection Block Diagram.
6.7 Timer
There is one timer in the real chip. Timer 1 is an 8-bit up-counter.
R_BANK Addr.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1S TC1RC TC1SS1
R/W R/W R/W
-
-
TC1FF TC1OMS TC1IS1 TC1IS0
R/W R/W R/W
Bank 0 0x24 TC1CR1
Bank 0 0x25 TC1CR2
Bank 0 0x26 TC1DA
Bank 0 0x27 TC1DB
R
TC1M2 TC1M1 TC1M0 TC1SS0 TC1CK3 TC1CK2 TC1CK1TC1CK0
R/W R/W R/W R/W R/W R/W R/W R/W
TC1DA7 TC1DA6 TC1DA5 TC1DA4 TC1DA3 TC1DA2 TC1DA1TC1DA0
R/W R/W R/W R/W R/W R/W R/W R/W
TC1DB7 TC1DB6 TC1DB5 TC1DB4 TC1DB3 TC1DB2 TC1DB1TC1DB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TC1DIF
F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bank 0 0x16
Bank 0 0x1C
ISR2
IMR2
TC1DIE
R/W
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
77
EM78P374N
8-bit Microcontroller
6.7.1 Timer/Counter Mode
TC1M2~0
TC1M2~0=timer/counter mode
TC1 pin
M
fc/215
MUX
clear
8-bit up counter
fc/20
TC1S
TC1CK
Comparator
TC1
interrupt
4
TC1CR
TC1DB
TC1DA
Data Bus
Figure 6-9a Timer/Counter Mode Block Diagram
In the Timer/Counter mode, counting-up is performed by using internal clock or TC3 pin.
When the contents of up-counter match the TC1DA, the interrupt is then generated and
the counter is cleared. Counting-up resumes after the counter is cleared. The current
contents of up-counter are loaded into TC1DB by setting TC1RC to “1”.
Internal clock
Up-counter
TC1DA
n
5
n-2
0
1
2
3
4
n-3
n-1
0
1
2
3
n
match
counter clear
TC1 interrupt
TC1 Pin
1
2
3
n 0
4
n-2
Up-counter
TC1DA
0
n-1
1
2
3
n
match
counter clear
TC1 interrupt
Figure 6-9b Timer/Counter Mode Waveform
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(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
6.7.2 Window Mode
TC1 pin
fc/215
Window
clear
8-bit up counter
MUX
fc/20
Comparator
TC1 interrupt
TC1CK
TC1S
4
TCcCR2
TC1DA
Data Bus
Figure 6-10a Window Mode Block Diagram
In Window mode, counting-up is performed on rising edge of the pulse that is Logical
AND of an internal clock and the TC1 pin (Window pulse). When the contents of
up-counter match the TC1DA, interrupt is generated and the counter is cleared. The
frequency (Window pulse) must be slower than the selected internal clock.
TC1 pin
Internal clock
Up-counter
TC1DA
n-1
n
0
n-2
0
1
2
n-3
1
2
3
n
match
counter clear
TC1 interrupt
Figure 6-10b Window Mode Waveform
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(This specification is subject to change without prior notice)
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6.7.3 Capture Mode
Inhibit
Rising
Edge
detector
Capture
control
TC1
Falling
TC1M2~0
M
interrupt
TC3M2~0=010
TC1 pin
fc/215
Overflow
8-bit up counter
MUX
fc/20
TC1S
CAP
TC1CK
4
Capture
Capture
TC1CR
TC1DB
TC1DA
Data Bus
Figure 6-11a Capture Mode Block Diagram
In Capture mode, the pulse width, period, and duty of the TC1 input pin are measured
in this mode, and can be used to decode the remote control signal. The counter is free
running by the internal clock. On the rising (falling) edge of TC1 pin, the contents of
counter is loaded into TC1DA, then the counter is cleared and interrupt is generated.
On the falling (rising) edge of TC13 pin, the contents of counter are loaded into TC1DB,
while the counter is still counting. Once the next rising edge of TC1 pin triggers, the
contents of counter are loaded into TC1DA, the counter is cleared, and interrupt is
generated again. If overflow before the edge is detected, the FFH is loaded into
TC1DA and overflow interrupt is generated. During interrupt processing, it can be
determined whether or not there is an overflow by checking whether or not the TC1DA
value is FFH. After an interrupt (capture to TC1DA or overflow detection) is generated,
capture and overflow detection are halted until TC1DA is read out.
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8-bit Microcontroller
Clock source
Up-counter
m
m+1
1
m-1
n
0
1
2
3
FE FF0
1
2
3
K-2
K-1 K 0
n-1
TC1 pin input
K
n
FF (overflow)
overflow
TC1DA
TC1DB
m
FE
capture
capture
TC1 interrupt
Reading TC1DA
Figure 6-11b Capture Mode Waveform
6.7.4 Programmable Divider Output (PDO) Mode and
Pulse Width Modulation (PWM) Mode
TCxFF
TC1M2~0=101
TC1 interrupt
F/F
PWM1,PDO1 pin
Q
clear
TC1M2~0=10x
toggle
8-bit up counter
fc/215
fc/20
MUX
match
Comparator
TC1S
TC1CK2~0
match
Comparator
4
TC1CR
TC1DA_buffer2
TC1DA_buffer1
TC1DB_buffer2
TC1DB_buffer1
TC1DB
Write TC1DA[0]
TC1DA
Data Bus
Figure 6-12a PDO / PWM Mode Block Diagram
Programmable Divider Output (PDO)
In Programmable Divider Output (PDO) mode, counting-up is performed using internal
clock. The contents of TC1DA are compared with the contents of the up-counter. The
F/F output is toggled and the counter is cleared each time a match is found. The F/F
output is inverted and output to PDO pin. This mode can generate 50% duty pulse
output. The PDO pin is initialized to “0” during reset. A TC1 interrupt is generated each
time the PDO output is toggled.
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EM78P374N
8-bit Microcontroller
Clock source
Up-counter
0
1
3
n-1
n
0
1
2
2
n
0
1
n-1
n-1
n
0
1
n
TC1DA
PDO pin
TC1 interrupt
Figure 6-12b PDO Mode Waveform
Pulse Width Modulation (PWM)
In Pulse Width Modulation (PWM) Output mode, counting up is performed using the
internal clock with prescaler. The Duty of PWM1 is controlled by TC1DB, and the
period of PWM1 is controlled by TC1DA. The pulse at the PWM1 pin is held to high
level as long as TC1S=1 or TIMERX matches TC1DA, while the pulse is held to low
level as long as Timer x matches TC1DB. Once TC1FF is set to “1”, the PWM3 signal
is inverted. A TC1 interrupt is generated and defined by TC1IS. On the other hand, the
TC1DA and TC1DB can be written anytime, but the data of TC13DA and TC1DB are
latched only at writing TC1DA [0]. Therefore, the new duty and new period of PWM
appear at the PMW pin at the last period–match.
Clock source
Up-counter
n
p
p+2
p+1
p-1
q-1
q
0
1
n-1
n+1 n+2
m-1
m
0
n-1
n
m-1
m
0
n+1 n+2
1
n
p
duty
duty-match
period-match
duty-match
duty-match
period-match
period-match
Writing duty register
q
m
period
PWM
Writing period register
p
n
m
q
TC1 interrupt
Figure 6-12c PWM mode waveform
6.7.5 Buzzer Mode
The TC1 pin outputs the clock after dividing the frequency.
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8-bit Microcontroller
6.8 PWM Module
6.8.1 Overview
In PWM mode, PWMX and /PWMX produce up to 16-bit resolution PWM output (see
the functional block diagram below). A PWM output consists of a time period and a
duty cycle, and it keeps the output high. The PWM baud rate is the inverse of the time
period. Figure 6-13b (PWM Output Timing) depicts the relationships between a time
period and a duty cycle.
Data Bus
DTH+DTL
Writing PRDL
TXP2 TXP1 TXP0
Duty
Fosc
1:1
1:2
1:4
1:8
1:16
1:64
1:128
1:256
TMRX
prescaler
MUX
To
PWMXDIF
Comparator
Comparator
TMRX
TXEN
prescaler
PWMXE
IPWMXE
PWMX
IPWMX
R
S
Q
Q
Q
Q
S
R
TMRXH+TMRXL
Period
match
Reset
Comparator
Period
To PWMXPIF
Writing PRDL
PRDH + PRDL
Data Bus
Figure 6-13a PWM Functional Block Diagram
PWM and /PWM (inverted PWM) can be used individually or used as dual PWM. When
used individually, the definitions of active level between PWM and /PWM are somewhat
different.
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8-bit Microcontroller
For example, setting the period and duty cycle (period > duty) as PWMXE=1/0 and
IPWMXE=0/1, and finally setting TXEN = 1. The following figure shows the PWM
output timing.
PWMX
PWMXE=1 and
IPWMXE=0
/PWMX
PWMXE=0 and
IPWMXE=1
Period-duty
Period
Duty
Figure 6-13b PWM Output Timing (PWMXA=0 and /PWMXA=0)
6.8.2 Control Register
R_Bank Addr. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
PWMCPSF PWMCDSF PWMBPSF PWMBDSF PWMAPSF PWMADSF
0x17 ISR3
0x1D IMR3
0x16 PWMSCR
0x17 PWMACR
0x18 PRDAL
0x19 PRDAH
0x1A DTAL
0x1B DTAH
0x1C TMRAL
0x1D TMRAH
0x1E PWMBCR
0x1F PRDBL
Bank 0
Bank 0
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
F
F
F
F
F
F
PWMCPIE PWMCDIE PWMBPIE PWMBDIE PWMAPIE PWMADIE
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
PWMCS PWMBS PWMAS
R/W
TAP2
R/W
R/W
TAP1
R/W
R/W
TAP0
R/W
PWMAE IPWMAE
R/W R/W
TAEN
R/W
PRDA7 PRDA6 PRDA5 PRDA4 PRDA3 PRDA2 PRDA1 PRDA0
R/W R/W R/W R/W R/W R/W R/W R/W
PRDA15 PRDA14 PRDA13 PRDA12 PRDA11 PRDA10 PRDA9 PRDA8
R/W
DTA7
R/W
R/W
DTA6
R/W
R/W
DTA5
R/W
R/W
DTA4
R/W
R/W
DTA3
R/W
R/W
DTA2
R/W
R/W
DTA1
R/W
R/W
DTA0
R/W
DTA15
R/W
DTA14
R/W
DTA13
R/W
DTA12
R/W
DTA11
R/W
DTA10
R/W
DTA9
R/W
DTA8
R/W
TMRA7 TMRA6 TMRA5 TMRA4 TMRA3 TMRA2 TMRA1 TMRA0
R/W R/W R/W R/W R/W R/W R/W R/W
TMRA15 TMRA14 TMRA13 TMRA12 TMRA11 TMRA10 TMRA9 TMRA8
R/W
PWMBE IPWMBE
R/W R/W
R/W
R/W
R/W
R/W
TBEN
R/W
R/W
TBP2
R/W
R/W
TBP1
R/W
R/W
TBP0
R/W
-
-
-
-
PRDB7 PRDB6 PRDB5 PRDB4 PRDB3 PRDB2 PRDB1 PRDB0
R/W R/W R/W R/W R/W R/W R/W R/W
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8-bit Microcontroller
(Continuation)
R_Bank Addr. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRDB15 PRDB14 PRDB13 PRDB12 PRDB11 PRDB10 PRDB9 PRDB8
Bank 1 0x20 PRDBH
R/W
DTB7
R/W
R/W
DTB6
R/W
R/W
DTB5
R/W
R/W
DTB4
R/W
R/W
DTB3
R/W
R/W
DTB2
R/W
R/W
DTB1 DTB0
R/W R/W
R/W
Bank 1 0x21
Bank 1 0x22
DTBL
DTBH
DTB15
R/W
DTB14
R/W
DTB13 DTB12 DTB11 DTB10 DTB9 DTB8
R/W R/W R/W R/W R/W R/W
TMRB7 TMRB6 TMRB5 TMRB4 TMRB3 TMRB2 TMRB1 TMRB0
Bank 1 0x23 TMRBL
Bank 1 0x24 TMRBH
Bank 1 0x25 PWMCCR
Bank 1 0x26 PRDCL
Bank 1 0x27 PRDCH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMRB15 TMRB14 TMRB13 TMRB12 TMRB11 TMRB10 TMRB9 TMRB8
R/W
PWMCE IPWMCE
R/W R/W
R/W
R/W
R/W
R/W
TCEN
R/W
R/W
TCP2
R/W
R/W
TCP1 TCP0
R/W R/W
R/W
-
-
-
-
PRDC7 PRDC6 PRDC5 PRDC4 PRDC3 PRDC2 PRDC1 PRDC0
R/W R/W R/W R/W R/W R/W R/W R/W
PRDC15 PRDC14 PRDC13 PRDC12 PRDC11 PRDC10 PRDC9 PRDC8
R/W
DTC7
R/W
R/W
DTC6
R/W
R/W
DTC5
R/W
R/W
DTC4
R/W
R/W
DTC3
R/W
R/W
DTC2
R/W
R/W
DTC1 DTC0
R/W R/W
R/W
Bank 1 0x28
Bank 1 0x29
DTCL
DTCH
DTC15
R/W
DTC14
R/W
DTC13 DTC12 DTC11 DTC10 DTC9 DTC8
R/W R/W R/W R/W R/W R/W
TMRC7 TMRC6 TMRC5 TMRC4 TMRC3 TMRC2 TMRC1 TMRC0
R/W R/W R/W R/W R/W R/W R/W R/W
TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 TMRC9 TMRC8
R/W R/W R/W R/W R/W R/W R/W R/W
Bank 1 0x2A TMRCL
Bank 1 0x2B TMRCH
6.8.3 Increment Timer Counter (TMRX: TMRAH/TMRAL,
TMRBH/TMRBL, TMRCH/TMRCL, or TMRDH/TMRDL)
TMRX are 16-bit clock counters with programmable prescalers. They are designed for
the PWM module as baud rate clock generators. TMR can be read only. If employed,
they can be turned off for power saving by setting the TAEN bit [BANK1-R1A <3>],
TBEN bit [BANK1-R21<3>], TCEN bit [BANK1-R28<3>], or TDEN bit [BANK1-R2F
<3>] to “0.”
TMRA, TMRB, TMRC, and TMRD are internal designs and cannot be read.
6.8.4 PWM Time Period (PRDX: PRDAL/H, PRDBL/H, PRDCL/H,
or PRDDL/H)
The PWM time period is 16-bit resolution and is defined by writing to the PRDX register.
When TMRX is equal to PRDX, the following events occur on the next increment cycle:
TMRX is cleared.
The PWMX pin is set to “1”
The PWMXIF pin is set to “1”
Product Specification (V1.8) 03.15.2016
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EM78P374N
8-bit Microcontroller
NOTE
The PWM output cannot be set if the duty cycle is “0”.
The following formula describes how to calculate the PWM time period:
1
CLKS
Period
PRDX 1
TMRX prescale value
FOSC
2
Example: PRDX = 49;
Fosc = 4 MHz;
TMRX (0, 0, 0) = 1 : 1,
CLKS bit of the Code Option Register = 0 (two oscillator periods);
Then-
1
2
2
Period
49 1
1 12.5s
4M
6.8.5 PWM Duty Cycle (DTX: DTAH/DTAL, DTBH/DTBL,
DTCH/DTCL, or DTDH/DTDL)
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX
to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared.
DTX can be loaded anytime. However, it cannot be latched into DLX until the current
value of DLX is equal to TMRX.
The following formula describes how to calculate the PWM duty cycle:
1
CLKS
Duty cycle
DTX
TMRX prescale value
FOSC
2
Example: DTX = 10; Fosc = 4 MHz; TMRX (0, 0, 0) = 1 : 1,
CLKS bit of the Code Option Register = 0 (two oscillator periods);
Then-
1
2
2
Duty cycle
10
1 2.5s
4M
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EM78P374N
8-bit Microcontroller
6.8.6 Comparator X
Changing the output status while matching occurs will simultaneously set the TMRXIF
flag.
6.8.7 PWM Programming Process/Steps
1) Load the PWM duty cycle to DT
2) Load the PWM time period to PRD
4) Enable the interrupt function by writing Bank 0-R1D, if required.
5) Load a desired value for the timer prescaler
6) Set active level of duty of PWM
7) Enable PWMX function, i.e., enable PWMXE control bit (if using dual PWM function
enable also the PWMXE control bit)
8) Finally enable the TMRX function, i.e., enable TXEN control bit.
If the application needs to change the PWM duty and period at run time, refer to the
following programming steps:
1) Load the new duty (if using dual PWM function) at any time.
2) Load the new period cycle. You must take note of the order of loading the period
cycle. As the low byte of PWM period cycle is assigned a value, the new PWM cycle
is loaded into the circuit. The circuit will automatically update the new duty and
period to generate the new PWM waveform at the next PWM cycle.
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8-bit Microcontroller
6.9 Comparator
The MCU has four comparators comprising of two analog inputs and one output. All of
the comparators can be set as OP. The comparator can be utilized to wake up the
MCU from Sleep mode. The comparator circuit diagram is depicted in the following
figure.
CxA-
CxC-S
CxB-
-
CO
CMP/OP
Cx+
+
X:1
CxREF
CxRS
Vref1
Vref2
2V 3V 4V
2V 3V 4V
-
Cx
-
CO
CMP/OP
Cx+
+
X:2~4
CxREF
CxRS
Vref1
Vref2
2V 3V 4V
2V 3V 4V
10mV
Cx -
Cx +
10mV
CO
Figure 6-14b Comparator Circuit and Operating Mode
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8-bit Microcontroller
6.9.1 External Reference Signal
The analog signal presented at Cin– is compared to the signal at Cin+, and the digital
output (CO) of the comparator has to be adjusted accordingly by taking the following
notes into considerations:
NOTE
The reference signal must be between Vss and Vdd.
The non-inverting end of Comparator 2 can be connected to the internal reference
and the corresponding pin can be set as comparator I/O or general I/O.
The non-inverting end of Comparator 2 can be connected to Vref1.
There are three reference voltage levels for Vref1, i.e., 2V, 3V, and 4V.
The falling edge of CO2 can turn-off the PWMx only or both PWMx and /PWMx,
when the PWMxA and IPWMxA are in turned-on state.
Example: (falling edge of CO1 PWMA, or both PWMA and /PWMA)
6.9.2 Comparator Outputs
The compared result is stored in the CMPOUT2.
The function of Pin CO2 is defined by programming the Register <C2S [1:0]>.
To CO pin
From CMP out
CMRD
EN
EN
Q
Q
D
D
To CMPOUT
RESET
To
CMPIF
CMRD
Figure 6-15 Comparator Output Configuration
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6.9.3 Programming the Related Registers
R_Bank Addr. Name
Bit 7
CMP2WK
R/W
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bank 0 0x10 WUCR2
Bank 0 0x15 SFR1
Bank 0 0x1B IMR1
Bank 0 0x3B CMP2CR
-
CMP2SF
R/W
-
-
CMP2IE
R/W
-
-
C2RS CP2OUT C2S1 C2S0
R/W R/W R/W R/W
SDPWMB
R/W
6.9.4 Comparator Interrupt
CMP2IE must be enabled for the “ENI” instruction to take effect.
Interrupt is triggered whenever a change occurs on the comparator output pin.
The actual change on the pin can be determined by reading the Bit CP2OUT.
The comparator interrupt flag CMP2IF, can only be cleared by software.
6.9.5 Wake-up from Sleep Mode
The comparator and the interrupt remain active in Sleep mode when CMP2IE=1 and
CMPWK=1.
If a comparator output changes state, the interrupt will wake up the device from
Sleep mode.
The power consumption should be taken into consideration for the benefit of energy
conservation.
If the function is unemployed during Sleep mode, turn off the comparator before
entering into sleep mode.
6.10 I2C Function
R_Bank Address Name
Bit 7
Bit 6
Bit 5
ISS
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Strobe/Pend IMS
STOP SAR_EMPTY ACK
FULL EMPTY
Bank 0 0x30 I2CCR1
R/W
I2CBF
R
R/W
GCEN
R/W
SA5
R/W
DB6
R/W
DA6
R/W
-
R/W
R
BBF
R
R
I2CTS1
R/W
SA2
R/W
DB3
R/W
DA3
R/W
-
R
R
R
I2CTS0 I2CCS I2CEN
Bank 0 0x31 I2CCR2
R/W
SA1
R/W
DB2
R/W
DA2
R/W
-
R/W
SA0
R/W
DB1
R/W
DA1
R/W
DA9
R/W
R/W
IRW
R/W
DB0
R/W
DA0
R/W
DA8
R/W
SA6
R/W
DB7
R/W
DA7
R/W
-
SA4
R/W
DB5
R/W
DA5
R/W
-
SA3
R/W
DB4
R/W
DA4
R/W
-
Bank 0 0x32
Bank 0 0x33
I2CSA
I2CDB
Bank 0 0x34 I2CDAL
Bank 0 0x35 I2CDAH
-
-
-
-
-
-
-
-
-
-
-
I2CSTPIF I2CRSF I2CTSF
R/W R/W R/W
I2CSTPIE I2CRIE I2CTIE
R/W R/W R/W
Bank 0 0x18
Bank 0 0x1E
SFR4
IMR4
-
-
-
-
-
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EM78P374N
8-bit Microcontroller
Read
Write
FULL
I2CRIF
I2CTIF
I2CDB reg
Buffer Full Detector
Control and
Status reg
SCL
I2CSA reg
MSb
LSb
SDA
Add Match
Match Detect
I2CDA reg
Start and Stop
bit Detect
Figure 6-16a 12C Block Diagram
The EM78P374N supports a bidirectional, 2-wire bus, 7/10-bit addressing and data
transmission protocol. A device that sends data onto the bus is defined as Transmitter,
while a device receiving data is defined as a Receiver. The bus has to be controlled by
a master device which generates the Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions. Both Master and Slave can operate as
Transmitter or Receiver, but the Master device determines which mode is activated.
Both Serial Data (SDA) and SCL are bi-directional lines, connected to a positive supply
voltage via a pull-up resistor. When the bus is free, both lines are high. The output
stage of devices connected to the bus must have an open-drain or open-collector to
perform the wired-AND function. Data on the I2C-bus can be transferred at a rate of up
to 100kbit/s in Standard-mode or up to 400kbit/s in Fast-mode.
The data on the SDA line must be stable during HIGH period of the clock. The High or
Low state of the data line can only change when the clock signal on the SCL line is Low.
The I2C interrupt occurs as describe below:
Condition
Master/Slave Transmit Address Transmit Data
Stop
Master
Slave
Transmit interrupt Transmit interrupt Stop interrupt
Receive interrupt Receive interrupt Stop interrupt
Transmit interrupt Receive interrupt Stop interrupt
Master Transmitter
(transmits to
Slave-Receiver)
Master Receiver
(read Slave-
Transmitter)
Master
Slave
Transmit interrupt
Transmit interrupt Stop interrupt
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Within the procedure of the I2C bus, unique situations could arise which are defined as
START (S) and STOP (P) conditions.
A High to Low transition on the SDA line while SCL is High is one such unique case.
This condition indicates a START condition.
A Low to High transition on the SDA line while SCL is High defines a STOP condition.
SCL
SDA
data line change
stable;
data valid allowed
of data
START
STOP
Figure 6-16b I2C Transfer Condition
6.10.1 7-Bit Slave Address
The Master-transmitter transmits to the Slave-receiver. The transfer direction is not
changed.
The Master reads the Slave immediately after the first byte. At the moment of the first
acknowledgement, the Master-transmitter becomes a Master-receiver and the
Slave-Receiver becomes a Slave-transmitter. This first acknowledgement is still
generated by the Slave. The STOP condition is generated by the Master, which has
previously sent a Not-Acknowledge (A). The difference between Master-transmitter
and Master-receiver is only in the R//W bit. If the R//W bit is “0,” the Master device is
the Transmitter. Otherwise; the Master device is the Receiver (R//W bit is “1”). The
Master-Transmitter is illustrated in the following Figure 6-17a, and that of
Master-Receiver is shown in Figure 6-17b.
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8-bit Microcontroller
8-Bit
8-Bit
Data
8-Bit
Data
S
Slave Address
7-Bit
R//W
A
A
A//A
P
'0'
Write
Data transferred
(n byte + acknowledge)
A = acknowledge (SDA low)
/A = not acknowledge (SDA high)
S = Start
Master to Slave
Slave to Master
P = Stop
Figure 6-17a Master-Transmitter transmits to Slave-Receiver with 7-Bit Slave Address
8-Bit
S
Slave Address
7-Bit
R//W
A
Data
A
Data
/A
P
'1' Read
data transferred
(n byte + acknowledge)
Figure 6-17b Master-Receiver reads from Slave-Transmitter with 7-Bit Slave Address
6.10.2 10-Bit Slave Address
In 10-Bit slave address mode, using 10 Bits for addressing exploits the reserved
combination 11110XX for the first 7 bits of the first byte following a START(S) or
repeated START (Sr) condition. The first 7 bits of the first byte are the combination
11110XX of which the last two bits (XX) are the two most-significant bits of the 10-bit
address. If the R//W bit is “0”, the second byte after acknowledgement would be the
eight address bits of the 10-bit Slave address. Otherwise; the second byte would just
be the next transmitted data from a Slave to Master device. The first bytes 11110XX
are transmitted using the Slave address register (I2CSA), and the second bytes
XXXXXXXX are transmitted using the data buffer (I2CDB).
The following will explain the possible data transfer formats for 10-bit Slave address
mode:
Master-Transmitter Transmits to Slave-Receiver with a 10-bit Slave Address
When the Slave receives the first byte after START bit from Master, each Slave device
will compare the 7 bits of the first byte (11110XX) with their own address and the 8th bit
(R//W). If the R//W bit is “0” the Slave will return the Acknowledge (A1). It is possible
that more than one Slave devices will return the Acknowledge (A1). Then all Slave
devices will continue to compare the second address (XXXXXXXX). If a Slave device
finds a match, that particular Slave device will be the only one to return an
Acknowledge (A2).
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The matched Slave device will remain addressed by the Master until it receives the
STOP condition or a repeated START condition followed by a different Slave address.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A1
A2
A
A//A
R//W
Data
Data
P
Write
1st 7-Bit
2nd 8-Bit
Figure 6-18b Master-Transmitter transmits to Slave-Receiver with a 10-Bit Slave Address
Master-Receiver Reads Slave-Transmitter with a 10-bit Slave Address
Up to, and including Acknowledge Bit A2, the procedure is the same as that described
above for Master-Transmitter addressing a Slave-Receiver. After the Acknowledge A2,
a repeated START condition (Sr) condition takes place, followed by seven bits Slave
address (11110XX), but the 8th bit R//W is “1.” The addressed Slave device will then
return the Acknowledge A3. If the repeated START (Sr) condition occurs and the
seven bits of first byte (11110XX) are received by Slave device, all the Slave devices
will compare with their own address and test the 8th R//W. However, none of the Slave
devices can return an acknowledgement because R//W=1.
1 1 1 1 0 X X
0
1 1 1 1 0 X X
1
Slave
Address
Slave
Address
Slave
Address
S
DATA
A1
A2 Sr
A3
A
DATA /A
P
R//W
R//W
1st 7-Bit
2nd 8-Bit
1st 7-Bit
read
Write
Figure 6-18b Master-Receiver reads Slave-Transmitter with a 10-Bit Slave Address
Master Transmits and Receives Data to and from the Same Slave
Device with 10-Bit Addresses
The initial operation of this data transfer format is the same as explained in the above
paragraph on “Master-Transmitter transmits to Slave-Receiver with a 10-bit Slave
Address.” Then the Master device starts to transmit the data to the Slave device.
When the Slave device receives the Acknowledge or None-Acknowledge that is
followed by repeat START (Sr), the above operation under “Master-Receiver reads
Slave- Transmitter with a 10-Bit Slave Address” is repeatedly performed.
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8-bit Microcontroller
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
R//W
A
A
A
A//A
Data
Data
1st 7-Bit
Write
2nd 8-Bit
1 1 1 1 0 X X
1
Slave
Address
Sr
R//W
A
A
/A
Data
Data
P
1st 7-Bit
Read
Figure 6-18c Master Addresses a Slave with 10-Bit Address transmits and receives Data with
the Same Slave Device
Master Device Transmits Data to Two or More Slave Devices with 10
and 7 Bits Slave Address
For 10-bit address, the initial operation of this data transfer format is the same as
explained in the above paragraph on “Master-Transmitter Transmits to Slave-Receiver
with a 10-bit Slave Address,” which describes how to transmit data to Slave device.
After the Master device completes the initial transmittal, and wants to continue
transmitting data to another device, the Master needs to address each of the new Slave
devices by repeating the initial operation mentioned above. If the Master device wants
to transmit the data in 7-bit and 10-bit Slave address modes successively, this could be
done after the START or repeat START conditions as illustrated in the following figures.
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
S
A
A
A
A//A
R//W
Data
Data
1st 7-Bit
Write
2nd 8-Bit
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
R//W
A
A
A
A//A
Data
Data
P
1st 7-Bit
Write
2nd 8-Bit
Figure 6-18d Master transmitting to more than One Slave Devices with 10-Bit Slave Address
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8-bit Microcontroller
0
Slave
Address
S
A
A
A//A
R//W
Data
Data
7-Bit
Write
1 1 1 1 0 X X
0
Slave
Address
Slave
Address
Sr
R//W
A
A
A
A//A
Data
Data
P
1st 7-Bit
Write
2nd 8-Bit
Figure 6-18e Master successively transmitting to 7-Bit and 10-Bit Slave Address
6.10.3 Master Mode 12C Transmit
In transmitting (receiving) serial data, the I2C is carried on as follows:
1) Set I2CTS1~0, I2CCS, and ISS bits to select I2C transmit clock source.
2) Set I2CEN and IMS bits to enable the I2C Master function.
3) Write Slave address into the I2CSA register and IRW bit to select read or write.
4) Set strobe bit to start transmitting and then check I2CTSF (I2CTSF) bit.
5) Write 1st data into the I2CDB register, set strobe bit, and check I2CTSF (I2CRSF) bit.
6) Write 2nd data into the I2CDB register, set strobe bit, STOP bit, and check I2CTSF
(I2CRSF) bit.
6.10.4 Slave Mode 12C Transmit
In receiving (transmitting) serial data, the I2C is carried on as follows:
1) Set I2CTS1~0, I2CCS, and ISS bits to select I2C transmit clock source.
2) Set I2CEN and IMS bits to enable I2C Slave function.
3) Write device address into the I2CDA register.
4) Check I2CRSF (I2CTSF) bit, read I2CDB register (address), and then clear Pend bit.
5) Check I2CRSF (I2CTSF) bit, read I2CDB register (1st data), and then clear Pend bit.
6) Check I2CRSF (I2CTSF) bit, read I2CDB register (2nd data), and then clear Pend
bit.
7) Check I2CSTPSF bit, end transmission.
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8-bit Microcontroller
6.11 LVD (Low Voltage Detector)
Under unstable power source condition, such as external power noise interference or
EMS test condition, a violent power vibration could occur. At the time, the VDD could
become unstable as it could be operating below working voltage. When the system
supply voltage (VDD) is below the operating voltage, the IC kernel will automatically
keep all register status.
6.11.1 Low Voltage Reset (LVR)
The detailed LVR operation mode is as follows:
LVR1
LVR0
VDD Reset Level
4.0V
VDD Release Level
0
0
1
0
1
0
1
4.2V
3.7V
2.9V
3.5V
2.7V
1
NA ( Power-on Reset )
If VDD < 4.0V and is kept for 5 µs, the IC will be reset.
If VDD < 3.5V and is kept for 5 µs, the IC will be reset.
If VDD < 2.7V and is kept for 5 µs, the IC will be reset.
6.11.2 Low Voltage Detect
Registers for LVD Circuit
R_Bank Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
Bank 1
Bank 0
Bank 0
Bank 0
0X49 LVDCR LVDEN LVD2 LVD1 LVD0 /LVD
-
-
-
-
-
-
-
-
-
-
-
-
0X10 WUCR2
-
-
-
-
-
-
LVDWK
LVDIE
LVDSF
-
-
-
-
-
-
0x1B
0x15
IMR1
SFR1
Corresponding Bits for LVD
LVDEN
LVDS1, LVDS0
LVD Voltage Interrupt Level
VDD <2.2V
VDD >2.2V
VDD <3.3V
VDD >3.3V
VDD <4.0V
VDD >4.0V
VDD <4.5V
VDD >4.5V
NA
LVDB
0
1
0
1
0
1
0
1
1
1
11
1
1
10
01
1
0
00
XX
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LVD Programming Process
Follow the steps below to obtain data from the LVD:
1) Write to the two bits (LVDS1 ~ LVDS0) on the Bank1-R49 register to define the LVD
level (see Section 6.1.96 for details).
2) Set the LVDWK bit if the Wake-up function is in use.
3) Set the LVDIE bit if the interrupt function is in use.
4) Write “ENI” instruction if the interrupt function is in use.
5) Set LVDEN bit to “1.”
6) Write “SLEP” instruction or poll /LVD bit.
7) Clear the interrupt flag bit (LVDSF) when Low Voltage is detected.
NOTE
When the LVDEN bit is set to enable the LVD module, the current consumption will
increase to 10 µA.
During the Sleep mode, the LVD module continues to operate. If the device voltage
drop slowly and crosses the detect point, the LVDSF bit will be set and the device will
wake-up from Sleep mode.
When the system resets, the LVD flag will be cleared.
Figure below shows the LVD module detection point in an external voltage condition.
When VDD drops but remains above VLVD, the LVDSF remains at “0”.
When VDD drops but above VLVD, LVDSF remains at “0”. When VDD drops below
VLVD, LVDSF is set to “1.” If global ENI is enabled, the LVDSF is also set to “1”, and
the next instruction will branch to interrupt vector.
After the VDD rises above VLVD again, the LVDSF will be set to “1” again. When the
global ENI is enabled, the next instruction will be executed in the interrupt vector.
Then the LVD interrupt flag is cleared to “0” by software.
When VDD drops below VRESET in less than 1µs, the system will keep all the registers
status, and the system halts but with the oscillation remaining active.
When VDD drops below VRESET but in more than 1 µs, a system reset occurs (refer to
Section 6.1.15 for more details).
LVDSF clear by software
Vdd
VLVD
VRESET
LVDSF
Internal
Reset
18 ms
> LVR voltage drop time
< LVR voltage drop time
Vdd < Vreset not longer than 5us,system keep on going
System reset occurs
Figure 6-19 LVD Waveform Characteristics showing Detection Point in an External Voltage Condition
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8-bit Microcontroller
6.12 Oscillator
6.12.1 Oscillator Modes
The MCU can be operated in six different oscillator modes (Fm), such as:
High XTAL oscillator Mode 2 (HXT2)
High XTAL oscillator Mode 1 (HXT1)
XTAL oscillator mode (XT)
Low XTAL oscillator mode (LXT)
Internal RC oscillator mode (IRC)
User can select one of the modes by programming the Option pin. There are three
types of the clock source which is used for Fs. Fs can be determined by Fss1 and Fss0
options. The maximum operating frequency of crystal/resonator on the different VDDs,
are listed in the table below.
Summary of Maximum Operating Speeds
Conditions
VDD
1.8
Fxt Max. (MHz)
4
8
Two clocks
3.0
5.0
20
6.12.2 Crystal Oscillator/Ceramic Resonators (XTAL)
The EM78P374N can be
driven by an external
OSCI
Ext. Clock
clock signal through the
OSCI pin as shown in the
figure at right.
OSCO
Figure 6-20a External Clock Input Circuit
In most applications, Pin
OSCI and Pin OSCO can
be connected with a
crystal or ceramic
C1
OSC
I
XTAL
resonator to generate
oscillation as depicted in
the right figures. The
same applies to LXT
mode or HXT mode.
OSCO
C2
RS
Figure 6-20c Crystal/Resonator Circuit
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8-bit Microcontroller
The following table provides the recommended values of C1 and C2. Since each
resonator has its own attributes, you should refer to its specification for the appropriate
values of C1 and C2. The serial resistor, RS; may be necessary for AT strip cut crystal
or low frequency mode.
Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode Frequency
C1 (pF)
C2 (pF)
100kHz
60pF
60pF
40pF
30pF
30pF
30pF
20pF
60pF
60pF
40pF
30pF
30pF
30pF
20pF
30pF
30pF
20pF
30pF
30pF
20pF
15pF
60pF
60pF
40pF
30pF
30pF
30pF
20pF
60pF
60pF
40pF
30pF
30pF
30pF
20pF
30pF
30pF
20pF
30pF
30pF
20pF
15pF
200kHz
455kHz
LXT
(100K ~ 1 MHz)
Main-oscillator
1.0 MHz
1.0 MHz
2.0 MHz
4.0 MHz
100kHz
(Ceramic Resonators)
HXT2
(1M ~ 6 MHz)
200kHz
LXT
(100K ~ 1 MHz)
455kHz
1.0 MHz
1.0 MHz
2.0 MHz
4.0 MHz
6.0 MHz
6.0 MHz
8.0 MHz
12.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
XT
(1M ~ 6 MHz)
Main-oscillator
(Crystal Oscillator)
HXT2
(6M ~ 12 MHz)
HXT1
(12M ~ 20 MHz)
6.12.3 Internal RC Oscillator Mode
The EM78P374N offers a versatile Internal RC mode with a default frequency value of
4 MHz. Internal RC oscillator mode has other frequencies (16 MHz, 8 MHz, 4 MHz, and
1 MHz) that can be set with Code Option: RCM1 and RCM0. All these four main
frequencies can be calibrated by programming the Code Option bits: C5~C0. Table
below shows a typical drift rate of the calibration.
Internal RC Drift Rate (Ta=25C, VDD=5V±5%, VSS=0V)
Drift Rate
Internal RC
Frequency
Temperature
(-40C ~ +85C)
Voltage
Process
Total
(2.5V ~ 5.5V)
1 MHz
4 MHz
8 MHz
16 MHz
±2%
±2%
±2%
±2%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±4%
±4%
±4%
±4%
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8-bit Microcontroller
NOTE
These are theoretical values provided for reference only. Actual values may vary
depending on the actual process.
6.13 Power-on Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply stabilizes to a steady state. The EM78P374N is equipped with a built-in
Power-on Voltage Detector (POVD) with a detecting level of 2.0V. Power will work well
if Vdd rises fast enough (50 ms or less). However, under critical applications, extra
devices may still be required to assist in solving the power-up problems.
6.14 External Power-on Reset Circuit
The circuit shown in next figure
implements an external RC to
Vdd
generate the reset pulse. The pulse
R
/RESET
D
width (time constant) should be kept
long enough for Vdd to achieve
minimum operating voltage. Apply
this circuit when the power supply
has a slow rising time. Since the
current leakage from the /RESET pin
is 5 A, it is recommended that
Rin
C
Figure 6-21 External Power-up Reset Circuit
R should not be greater than 40 KΩ in order for the /RESET pin voltage to remain at
below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor (C) will discharge rapidly and fully. The current-limited resistor (Rin) will
prevent high current or ESD (electrostatic discharge) from flowing to Pin /RESET.
6.15 Residue-Voltage Protection
When the battery is replaced, device power (Vdd) is taken off but residue-voltage
remains. The residue-voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. The following figures show how to perform
and accomplish a proper residue-voltage protection circuit.
Vdd
Vdd
Vdd
Vdd
33K
R1
R2
Q1
10K
Q1
/RESET
/RESET
1N4684
40K
40K
Figure 6-22a Circuit 1 for Residue Voltage Protection
Figure 6-22b Circuit 2 for Residue Voltage Protection
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8-bit Microcontroller
6.16 Code Option
6.16.1 Code Option Register (Word 0)
Word 0
Bit
Bit 14Bit 13Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2Bit 1Bit 0
Mnemonic
-
-
-
-
-
-
-
-
HLFS HLP LVR1 LVR0 RESETEN ENWDT NRHL NRE PR2 PR1 PR0
1
0
Normal High High High
Green Low Low Low
P67
/RST
1
Disable 32/fc Enable
Enable 8/fc Disable
Disable
Enable
Disable
-
-
-
-
Default
0
1
0
0
1
0
1
1
1
1
1
Bit 14:
Bit 13:
Not used. Set to “0” all the time.
Not used. Set to “1” all the time.
Not used. Set to “0” all the time.
Bits 12 ~ 11:
Bit 10 (HLFS):
Reset to Normal or Green Mode Select bit
0: CPU is defined as Green mode when a Reset occurs.
1: CPU is defined as Normal mode when a Reset occurs (default).
Bit 9:
Power consumption selection
0: Low power consumption, applies to operating frequency equal to
or below 400kHz
1: Normal power consumption, applies to operating frequency
above 400kHz (default)
Bits 8 ~ 7 (LVR1 ~ LVR0): Low Voltage Reset Enable bits
LVR1
LVR0
VDD Reset Level
4.0V
VDD Release Level
0
0
1
0
1
0
1
4.2V
3.7V
2.9V
3.5V
2.7V
1
NA ( Power-on Reset )
If VDD < 4.0V and is kept for about 1 µs, the IC will be reset.
If VDD < 3.5V and is kept for about 1 µs, the IC will be reset.
If VDD < 2.7V and is kept for about 1 µs, the IC will be reset.
Bit 6 (RESETEN): P67//RST pin select bit
0: Enable, /RST pin
1: Disable, P67 pin (default)
Bit 5 (ENWDT): WDT enable bit
Bit 4 (NRHL):
Noise rejection high/low pulse define bit
NOTE
In Low XTAL oscillator (LXT) mode, the noise rejection high/low
pulses are always 8/Fm.
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8-bit Microcontroller
Bit 3 (NRE):
Noise Rejection Enable bit
0: Disable
1: Enable (default)
NOTE
In Green, Idle, and Sleep modes, the noise rejection circuit is
always disabled.
6.16.2 Code Option 1 (Word 1)
Word 1
Bit
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
-
-
FSS0 C5
C4
C3
C2
C1
C0 RCM1 RCM0
-
-
OSC2 OSC1 OSC0 RCOUT
1
0
16kHz High High High High High High High High
32kHz Low Low Low Low Low Low Low Low
High High High High
-
-
Low Low Low
Low
1
Default
1
1
1
1
1
1
1
1
1
1
0
0
1
1
Bit 14:
Not used. Set to “1” all the time.
Bit 13 (FSS0):
Sub-frequency selection
0: 32kHz
1: 16kHz (default)
Bits 12 ~ 7 (C5 ~ C0):IRC trim bits. These are automatically set by the writer.
Bits 6 ~ 5 (RCM1 ~ RCM0): IRC frequency selection bits
RCM1
RCM0
Frequency (MHz)
0
0
1
1
0
1
0
1
1
8
16
4 (default)
Bits 3 ~ 1 (OSC2 ~ OSC0): Oscillator modes selection bits
Mode
OSC2 OSC1 OSC0
HXT1 (High XTAL1 Oscillator mode)
Frequency range: 12 ~ 20 MHz
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
HXT2 (High XTAL2 Oscillator mode)
Frequency range: 6 ~ 12 MHz
XT (XTAL Oscillator mode)
Frequency range: 1 ~ 6MHz
LXT1 (Low XTAL1 Oscillator mode)
Frequency range: 100kHz ~ 1 MHz
IRC (Internal RC Oscillator mode)
OSCI pin acts as I/O (default)
IRC (Internal RC Oscillator mode)
OSCI pin acts RCOUT
Bit 0 (RCOUT):
System Clock Output Enable bit in IRC mode
0: OSCI pin output instruction cycle time in open drain
1: OSCI output instruction cycle time (default)
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6.16.3 Code Option 2 (Word 2)
Word 2
Bit
Bit 14 Bit 13Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
Bit 6
IRCIRS
Regulator
Bandgap
1
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic
-
-
-
-
-
-
SC3 SC2 SC1 SC0
High High High High
Low Low Low Low
-
-
-
I2COPT
High
Low
1
-
-
-
-
-
-
-
-
1
0
-
-
-
-
-
-
-
-
-
-
Default
0
0
0
1
1
1
1
1
1
0
0
0
1
Bit 14:
Not used. Set to “0” all the time.
Not used. Set to “0” all the time.
Bits 13 ~ 12:
Bits 11 ~ 8 (SC3 ~ SC0): Trim bits of sub-frequency IRC. These are automatically set
by the writer.
Bit 7:
Not used. Set to “1” all the time.
Bit 6 (IRCIRS): IRC internal reference selection
0: Bandgap
1: IRC regulator (default)
Bit 5:
Not used. Set to “1” all the time.
Bit 4 (I2COPT): I2C optional bit. It is used to switch the pin I2C function position
0: I2C Pins (SCL/SDA) are P72, P73 in the pin assignment figure
1: I2C Pins (SCL/SDA) are P61, P62 in the pin assignment figure
(Default)
Bits 3 ~ 1:
Bit 0:
Not used. Set to “0” all the time.
Not used. Set to “1” all the time.
6.16.4 Code Option 3 (Word 3)
Word 3
Bit
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic EFTIM
-
-
ADFM
-
-
-
-
-
ID5 ID4 ID3 ID2 ID1 ID0
1
0
Light
Heavy
1
-
-
High
-
-
-
-
-
-
-
Low
0
-
-
-
-
-
Customer ID
Default
1
1
1
1
0
0
0
Bit 14 (EFTIM): Low Pass Filter (0: Heavy, 1: Light)
0: Less than 10 MHz- pass (heavy LPS)
1: Less than 25 MHz- pass (light LPS, default)
Not used. Set to “1” all the time.
Bits 13 ~ 12:
104
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
Bit 11 (ADFM): These bits control the AD data buffer format (ADDH and ADDL).
Refer to the following table.
ADFM
ADDH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADD11ADD10 ADD9 ADD8
-
-
-
-
0
ADDL ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
ADDHADD11ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4
12
bits
1
ADDL
-
-
-
-
ADD3 ADD2 ADD1 ADD0
Bits 10~9:
Bits 8~6:
Bits 5~0:
Not used. Set to “1” all the time.
Not used. Set to “0” all the time.
Customer ID
6.17 Instruction Set
Each instruction in the instruction set is a 15-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6", "CLR R2", etc.). In this case,
the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try to modify the instruction as follows:
A) Change one instruction cycle to consist of four oscillator periods.
B) "JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip ("JBS", "JBC", "JZ",
"JZA", "DJZ", "DJZA") commands which were tested to be true, are executed within
two instruction cycles. The instructions that are written to the program counter also
take two instruction cycles.
Case A is selected by the Code Option bit, called CLK. One instruction cycle consists
of two oscillator clocks if CLK is low and four oscillator clocks if CLK is high.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
105
EM78P374N
8-bit Microcontroller
Additionally, the Instruction Set also offers the following features:
1) Every bit of any register can be set, cleared, or tested directly.
2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
The symbol "R" represents a register designator that specifies which one of the
registers (including operational registers and general purpose registers) is to be utilized
by the instruction. "b" represents a bit field designator that selects the value for the bit
which is located in the register "R", and affects operation. "k" represents an 8 or 10-bit
constant or literal value.
Instruction Set Table:
In the following Instruction Set table, the following symbols are used:
"R" represents a register designator that specifies which one of the registers (including
operational registers and general purpose registers) is to be utilized by the instruction.
"b" represents a bit field designator that selects the value for the bit which is located in the
register "R", and affects the operation.
"k" represents an 8 or 10-bit constant or literal value.
Status
Binary Instruction
HEX
Mnemonic
Operation
No operation
Affected
None
C
000 0000 0000 0000
000 0000 0000 0001
000 0000 0000 0011
000 0000 0000 0100
000 0000 0001 0000
000 0000 0001 0001
000 0000 0001 0010
0000
0001
0003
0004
0010
0011
0012
NOP
DAA
SLEP
WDTC
ENI
Decimal Adjust A
0 WDT, Stop oscillator
0 WDT
T,P
T,P
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
None
None
None
DISI
RET
[Top of Stack] PC,
Enable Interrupt
000 0000 0001 0011
0013
RETI
None
000 0001 rrrr rrrr
000 0010 0000 0000
000 0011 rrrr rrrr
000 0100 rrrr rrrr
000 0101 rrrr rrrr
000 0110 rrrr rrrr
000 0111 rrrr rrrr
000 1000 rrrr rrrr
01rr
0200
03rr
04rr
05rr
06rr
07rr
08rr
MOV R,A
CLRA
A R
None
0 A
Z
CLR R
0 R
Z
SUB A,R
SUB R,A
DECA R
DEC R
R-A A
R-A R
R-1 A
R-1 R
A R A
Z, C, DC
Z, C, DC
Z
Z
Z
OR A,R
106
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
(Continuation)
Status
Affected
Binary Instruction
HEX
Mnemonic
Operation
000 1001 rrrr rrrr
000 1010 rrrr rrrr
000 1011 rrrr rrrr
000 1100 rrrr rrrr
000 1101 rrrr rrrr
000 1110 rrrr rrrr
000 1111 rrrr rrrr
001 0000 rrrr rrrr
001 0001 rrrr rrrr
001 0010 rrrr rrrr
001 0011 rrrr rrrr
001 0100 rrrr rrrr
001 0101 rrrr rrrr
001 0110 rrrr rrrr
001 0111 rrrr rrrr
09rr
0Arr
0Brr
0Crr
0Drr
0Err
0Frr
10rr
11rr
12rr
13rr
14rr
15rr
16rr
17rr
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
A R R
A & R A
A & R R
A R A
A R R
A + R A
A + R R
R A
Z
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
R R
Z
Z
/R A
/R R
Z
INCA R
R+1 A
Z
INC R
R+1 R
Z
DJZA R
DJZ R
R-1 A, skip if zero
R-1 R, skip if zero
None
None
R(n) A(n-1),
R(0) C, C A(7)
001 1000 rrrr rrrr
001 1001 rrrr rrrr
001 1010 rrrr rrrr
001 1011 rrrr rrrr
001 1100 rrrr rrrr
18rr
19rr
1Arr
1Brr
1Crr
RRCA R
RRC R
C
C
R(n) R(n-1),
R(0) C, C R(7)
R(n) A(n+1),
R(7) C, C A(0)
RLCA R
RLC R
C
R(n) R(n+1),
R(7) C, C R(0)
C
R(0-3) A(4-7),
R(4-7) A(0-3)
SWAPA R
None
001 1101 rrrr rrrr
001 1110 rrrr rrrr
001 1111 rrrr rrrr
010 0bbb rrrr rrrr
010 1bbb rrrr rrrr
011 0bbb rrrr rrrr
011 1bbb rrrr rrrr
1Drr
1Err
1Frr
2xrr
2xrr
3xrr
3xrr
SWAP R
JZA R
R(0-3) R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 R(b)
None
None
None
None
None
None
None
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 [SP],
(Page, k) PC
100 kkkk kkkk kkkk
4kkk
CALL k
None
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
107
EM78P374N
8-bit Microcontroller
(Continuation)
Status
Affected
Binary Instruction
HEX
Mnemonic
Operation
(Page, k) PC
101 kkkk kkkk kkkk
110 0000 kkkk kkkk
110 0100 kkkk kkkk
110 1000 kkkk kkkk
110 1100 kkkk kkkk
5kkk
60kk
64kk
68kk
6Ckk
JMP k
None
MOV A,k
OR A,k
AND A,k
XOR A,k
k A
None
A k A
A & k A
A k A
Z
Z
Z
k A,
[Top of Stack] PC
111 0000 kkkk kkkk
70kk
RETL k
None
111 0100 kkkk kkkk
111 1100 kkkk kkkk
111 1010 0000 kkkk
111 1010 0100 kkkk
74kk
7Ckk
7A0k
7A4k
SUB A,k
ADD A,k
SBANK k
GBANK k
k-A A
k+A A
KR1(4)
KR1(0)
Z, C, DC
Z, C, DC
None
None
Next instruction:
k kkkk kkkk kkkk
111 1010 1000 kkkk
kkk kkkk kkkk kkkk
7A8k
kkkk
LCALL k
None
PC+1[SP], kPC
Next instruction:
k kkkk kkkk kkkk
111 1010 1100 kkkk
kkk kkkk kkkk kkkk
7ACk
kkkk
LJMP k
None
None
KPC
111 1011 rrrr rrrr
7Brr
TBRD R
ROM[(TABPTR)] R
7 Absolute Maximum Ratings
Items
Rating
Temperature under bias
Storage temperature
Input voltage
-40C
-65C
to
to
85C
150C
Vss-0.3V to
Vss-0.3V to
Vdd+0.5V
Vdd+0.5V
5.5V
Output voltage
Working Voltage
Working Frequency
2.1V
DC
to
to
20 MHz
108
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
8 DC Electrical Characteristics
Ta=25C, VDD=5.0V, VSS=0V
Symbol
Parameter
XTAL: VDD to 3V
Condition
Min.
DC
Typ.
8
Max.
Unit
MHz
MHz
kHz
Hz
-
Two cycles with two clocks
XTAL: VDD to 5V
DC
16
-
Fxt
ERIC: VDD to 5V
R: 2.2 M
F30 32.7
F30
IRC: VDD to 5V
4 MHz, 1 MHz, 8 MHz, 16 MHz
VIN = VDD, VSS
-
F
0
-
-1
-
-
1
-
Input Leakage Current for input pins
IIL
A
IRCE Internal RC Oscillator error per stage
±1
4
%
IRC1
IRC2
IRC3
IRC4
IRC: VDD to 5V
IRC: VDD to 5V
IRC: VDD to 5V
IRC: VDD to 5V
RCM0:RCM1=1:1
RCM0:RCM1=1:0
RCM0:RCM1=0:1
RCM0:RCM1=0:0
-
-
MHz
MHz
MHz
MHz
-
8
-
-
16
1
-
-
-
Input High Threshold Voltage
(Schmitt trigger)
VIHRC
OSCI in RC mode
3.9
21
4
4.1
23
V
mA
V
IERC1 Sink current
VI from low to high, VI=5V
OSCI in RC mode
22
1.8
Input Low Threshold Voltage
VILRC
1.7
1.9
(Schmitt trigger)
IERC2 Sink current
VI from high to low, VI=2V
16
-1
17
0
-
18
1
mA
A
V
IIL
Input Leakage Current for input pins VIN = VDD, VSS
Input High Voltage (Schmitt trigger) Ports 5, 6, 7,
VIH1
VIL1
0.7Vdd
-0.3V
Vdd+0.3V
0.3Vdd
Input Low Voltage (Schmitt trigger)
Ports 5, 6, 7
/RESET
-
V
Input High Threshold Voltage
(Schmitt trigger)
VIHT1
VILT1
VIHT2
VILT2
0.7Vdd
-0.3V
-
-
-
-
Vdd+0.3V
0.3Vdd
V
V
V
V
Input Low Threshold Voltage
(Schmitt trigger)
/RESET
Input High Threshold Voltage
(Schmitt trigger )
TCC, INT
TCC, INT
0.7Vdd
-0.3V
Vdd+0.3V
0.3Vdd
Input Low Threshold Voltage
(Schmitt trigger)
VIHX1 Clock Input High Voltage
VILX1 Clock Input Low Voltage
OSCI in crystal mode
OSCI in crystal mode
VOH = VDD-0.1VDD
2.9
1.7
-
3.0
1.8
3.1
1.9
-
V
V
IOH1
IOH2
Output High Voltage (Ports 5, 6, 7)
-4.8
mA
Output High Voltage (high drvie)
(Ports 5, 6, 7)
VOH = VDD-0.1VDD
-
-7.9
-
mA
IOL1
IOL2
Output Low Voltage (Ports 5, 6, 7)
Output Low Voltage (P67)
VOL = GND+0.1VDD
VOL = GND+0.1VDD
-
-
14
16
-
-
mA
mA
Output Low Voltage (high sink)
(Ports 5, 6, 7)
IOL3
IOL4
VOL = GND + 0.1VDD
-
-
27
39
-
-
mA
mA
Output Low Voltage (high sink) (P67) VOL = GND + 0.1VDD
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
109
EM78P374N
8-bit Microcontroller
(Continuation)
Symbol
Parameter
Condition
Min. Typ.
2.41 2.7
2.14 2.7
3.1 3.5
2.73 3.5
3.56 4.0
3.16 4.0
Max.
2.99
3.25
3.92
4.25
4.43
4.81
-
Unit
V
Ta= 25C
LVR1
Low voltage reset level
Low voltage reset level
Low voltage reset level
Ta= -40~85C
V
Ta= 25C
V
LVR2
LVR3
Ta= -40~85C
V
Ta= 25C
V
Ta= -40~85C
V
IPH
IPL
Pull-high current
Pull-low current
Pull-high active, input pin at VSS
Pull-low active, input pin at Vdd
-
-
-62
40
A
A
-
/RESET= 'High', Fm and Fs off
All input and I/O pins at VDD,
Output pin floating. WDT disabled
Power down current
(Sleep mode)
ISB1
ISB2
ISB3
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
-
-
-
-
-
-
-
-
-
-
1.2
-
-
-
-
-
-
-
-
-
-
A
A
/RESET= 'High', Fm and Fs off.
Power down current
(Sleep mode)
10.8
10.8
22.8
30
All input and I/O pins at VDD,
Output pin floating. WDT enabled
/RESET= 'High', Fm off.
Fs=32kHz (IRC type),
Output pin floating, WDT enabled
Power down current
(Idle mode)
A
/RESET= 'High', Fm off
Fs=16kHz (IRC type),
Output pin floating, WDT enabled
Operating supply current
(Green mode)
A
/RESET= 'High', Fm off
Fs=32kHz (IRC type),
Output pin floating, WDT enabled
Operating supply current
(Green mode)
A
/RESET= 'High',
Fm=4MHz (Crystal type), Fs on,
Output pin floating, WDT enabled
Operating supply current
(Normal mode)
1.44
1.32
2.8
mA
mA
mA
mA
mA
/RESET= 'High',
Fm=4MHz (IRC type), Fs on,
Output pin floating, WDT enabled
Operating supply current
(Normal mode)
/RESET= ‘High’,
Fm=10MHz (Crystal type), Fs on,
Output pin floating, WDT enabled
Operating supply current
(Normal mode)
/RESET= ‘High’,
Fm=16MHz (IRC type), Fs on,
Output pin floating, WDT enabled
Operating supply current
(Normal mode)
3.84
4.4
/RESET= ‘High’,
Fm=16MHz (Crystal type), Fs on,
Output pin floating, WDT enabled
Operating supply current
(Normal mode)
NOTE
The DC Characteristics parameters are theoretical values only and have not been
tested or verified.
Data under the “Min.”, “Typ.”, and "Max." columns are based on theoretical results at
25C. These data are for design reference only and have not been tested or
verified.
110
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
8.1 AD Converter Characteristics
Vdd=2.5V to 5.5V, Vss=0V, Ta= 25°C
Symbol
VAREF
VASS
Parameter
Condition
Min.
Typ. Max. Unit
2.5
Vss
VASS
-
Vdd
Vss
V
V
V
Analog reference
voltage
VAREF - VASS 2.5V
VAI
Analog input voltage
VAREF
Ivdd
IAI1
Ivref
VDD=VAREF=5.5V,
1400 µA
10 µA
Analog supply current VASS = 0.0V Fin = 100kHz
(V reference from Vdd)
Ivdd
VDD=VAREF=5.5V,
Analog supply current VASS = 0.0V Fin = 100kHz
(V reference from VREF)
900 µA
500 µA
IAI2
IVref
RN
Resolution
12
-
Bits
INL
Integral Nonlinearity
VAREF= Vdd=5.0V Ta=25°C
VAREF= Vdd=5.0V Ta=25°C
±4 LSB
±1 LSB
Differential nonlinear
error
DNL
GE
OE
Gain Error
Offset error
VAREF= Vdd=5.0V Ta=25°C
VAREF= Vdd=5.0V Ta=25°C
±8 LSB
±4 LSB
Recommended
ZAI
impedance of analog
voltage source
10
KΩ
VDD=3~5.5V,
VASS = 0.0V, Ta=25°C
0.5
2
-
-
-
-
-
µs
µs
µs
µs
s
TAD
ADC clock duration
VDD=2.5~3V,
VASS = 0.0V, Ta=25°C
VDD=3~5.5V,
VASS = 0.0V, Ta=25°C
4
-
Tsh
Sample and Hold Time
AD conversion time
VDD=2.5~3V,
VASS = 0.0V, Ta=25°C
16
-
VDD=2.5~5.5V,
VASS = 0.0V, Ta=25°C
Tsh+12
TAD
TCN
VAREF= 2.5V, VREF=Vdd,
Vdd=2.5V ~ 5.5V,
Vin=0V ~ 2.5V
Power supply
rejection ratio
PSRR
2
LSB
%
A1/4VDD Accuracy for 1/4 VDD
±3
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
111
EM78P374N
8-bit Microcontroller
8.2 Comparator Characteristics
Vdd = 5.0V, Vss=0V, Ta = 25°C
Symbol
Parameter
Condition
Min. Typ. Max. Unit
VOS
Input offset voltage
2
mV
V
Input common-mode
voltage range
Vcm
ICO
GND
VDD
Supply current of
comparator
Co=0V, Ta= -40~85C
150
2.5
µA
µs
ns
VREF=1.0V, VRL=5V,
RL=5.1k, CL=15p
TRS
TLRS
Response time
VREF=2.5V, VRL = 5V,
RL = 5.1k
Large signal response time
500
Vi(-) = 1V, Vi(+) = 0V,
Vo = GND+0.5V
IOL
Output sink current
12
mA
V
Vi(-)=1V, Vi(+)=0V,
IOL <= 4mA
VSAT Saturation voltage
0.2
0.4
These parameters are hypothetical (not tested) and provided for design reference use only.
The response time specified is a 0V~VDD input step with 1/2VDD overdrive.
The driving ability is decided by digital output block.
8.3 OP Characteristics
Vdd = 5.0V, Vss=0V, Ta= 25°C
Symbol
VOS
SR
Parameter
Input offset voltage
Slew rate
Condition
Vip=0.5V, 4.5V
Ta= -40~85C
Min. Typ. Max. Unit
0
2
1.5
5
mV
V/s
V
IVR
Input voltage range
Vip=0V, IL=1.0mA
200
4.7
mV
V
Ta= -40~85C
OVS
IOP
Output voltage swing
Supply current of OP
Vip=5V, IL=1.0mA
Ta= -40~85C
Ta= -40~85C
400
75
A
dB
PSRR Power supply rejection ratio Ta= -40~85C
CMRR Common mode reject ratio
GBP Gain bandwidth product
0V≦VCM≦VDD
90
dB
RL=1Meg, CL=100p
2.6
MHz
112
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
8.4 VREF 2V/3V/4V Characteristics
Vdd = 5.0V, Vss=0V, Ta=-40 to 85°C
Symbol
VDD
Parameter
Condition
Min.
2.1
Typ.
Max.
5.5
Unit
V
Power Supply
–
IVDD
DC Supply Current No load
250
µA
%
AVref
Accuracy for Vref Vref=2V, 3V, 4V
VDD = VDDmin - 5.5V
±1
±1.75
Warm up Time ready for
time
Cload = 19.2pf
Rload = 15.36K
30
50
µs
V
voltage reference
Minimum
Power Supply
VDDmin
Vref + 0.2
* VDDmin: Can also work at Vref+0.1V, but has a poor PSRR
9 AC Electrical Characteristics
Ta=25C, VDD=5V 5%, VSS=0V
Symbol
Dclk
Parameter
Conditions
Min.
Typ.
Max. Unit
Input CLK duty cycle
45
50
55
%
Tins
Instruction cycle time
Crystal type
16kHz
125
DC
ns
Delay time after
Tpor
16 3%
ms
µs
µs
Power-on-Reset release
Crystal type
HLFS=1
WSTO+510/Fm
WSTO + 8/Fm
Delay time after
Trstrl
IRC type
HLFS=1
/Reset, WDT, and LVR release
HLFS=0
WSTO + 8/Fs
µs
µs
µs
ms
ns
ns
Trsth1
Trsth2
Twdt
Tset
Hold time after /RESET pin reset
Hold time after LVR pin reset
Watchdog timer time-out
Input pin setup time
1 µs
1 µs
16kHz
16 3%
0
Thold
Input pin hold time
15
20
25
Cload=20pF
Tdelay
Output pin delay time
20
ns
Rload=1MΩ
* Tpor and Twdt are 16 10% ms at FSS0=1 (16kHz), Ta=-40~85C, and VDD=2.1~5.5V
** WSTO: Waiting time from Start-to-Oscillation
NOTE
The above parameters are theoretical values only and have not been tested or
verified.
Data under the “Min.”, “Typ.” and “Max.” columns are based on theoretical results at
25C. These data are for design reference only and have not been tested or
verified.
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
113
EM78P374N
8-bit Microcontroller
APPENDIX
A Ordering and Manufacturing Information
EM78P374ND20J
Material Type
J: RoHS complied
S: Sony SS-00259 complied
Contact Elan Sales for details
Pin Number
Package Type
D: DIP
SO: SOP
SS:SSOP
K:Skinny DIP
Check the following section for details
Specific Annotation
Product Number
Product Type
P: OTP
Elan 8-bit Product
For example:
EM78P374NSO18S
is EM78P374N with OTP program memory,
in 18-pin SOP 300mil package with Sony SS-00259 complied
IC Mark
‧‧‧‧‧‧‧
Elan Product Number / Package, Material Type
Batch Number
EM78Paaaaaa
1041c bbbbbb
Manufacture Date
“YYWW”
YY is year and WW is week
c is Alphabetical suffix code for Elan use only
‧‧‧‧‧‧‧
114
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
Ordering Code
EM78P374ND18J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
B Package Type
OTP MCU
EM78P374NSS24
Package Type
SSOP
Pin Count
Package Size
150 mil
24
24
24
20
20
20
18
18
EM78P374NSO24
EM78P374NK24
EM78P374NSS20
EM78P374NSO20
EM78P374ND20
EM78P374NSO18
EM78P374ND18
SOP
300 mil
Skinny DIP
SSOP
300 mil
209 mil
SOP
300 mil
PDIP
300 mil
SOP
300 mil
PDIP
300 mil
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
Pb content is less than 100ppm and complies with Sony specifications.
Part No.
EM78P374NxJ/xS
Pure Tin
Electroplate type
Ingredient (%)
Sn: 100%
Melting point (°C)
232°C
Electrical resistivity
(µ-cm)
11.4
Hardness (hv)
Elongation (%)
8~10
>50%
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
115
EM78P374N
8-bit Microcontroller
C Packaging Configuration
C.1 EM78P374NSS24 150 mil
Figure B-1 EM78P374N 24-Pin SSOP Package Type
116
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
C.2 EM78P374NSO24 300 mil
Symbol
Min.
2.350
0.102
Normal
Max.
2.650
0.300
A
A1
b
0.406 (TYP)
c
0.230
7.400
0.320
7.600
E
H
D
L
10.000
15.200
0.630
10.650
15.600
1.100
0.838
1.27 (TYP)
e
0
8
θ
b
e
c
TITLE:
SOP-24L(300MIL)
PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
SO24
Unit : mm
Scale: Free
Materia:l
Sheet: 1 of1
Figure B-2 EM78P372N 24-Pin SOP Package Type
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
117
EM78P374N
8-bit Microcontroller
C.3 EM78P374NK24 300 mil
13
24
Symbol
A
Min. Normal Max.
5.334
E
A1
A2
c
0.381
3.175
3.302
0.254
3.429
0.203 0.356
31.750 31.801 31.852
D
E1
E
6.426
7.370
8.380
0.356
6.628
7.620
8.950
0.457
1.520
3.302
6.830
7.870
9.520
0.559
12
1
eB
B
1.470
3.048
1.630
3.556
B1
L
e
2.540 (TYP.)
0
15
θ
e
TITLE :
PDIP-24L SKINNY 300 MIL
PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
K24
Unit: mm
Scale: Free
Materia:l
Sheet: 1 of1
Figure B-3 EM78P374N 24-Pin Skinny DIP Package Type
118
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
C.4 EM78P374NSS20 209 mil
Symbol
Min.
Normal
Max.
2.130
0.250
1.880
0.380
0.200
8.200
5.600
7.500
0.850
A
A1
A2
b
c
E
E1
D
L
0.050
1.620
0.220
0.090
1.750
7.400
5.000
6.900
0.650
7.800
5.300
7.200
0.750
L1
e
1.250 (REF )
0.650 (TYP)
4
0
8
θ
b
e
c
L1
:
TITLE
SSOP-20L (209MIL) PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
SSOP20
Unit: mm
Scale: Free
Material:
Sheet: 1 of1
Figure B-4 EM78P374N 20-Pin SSOP Package Type
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
119
EM78P374N
8-bit Microcontroller
C.5 EM78P374NSO20 300 mil
Symbol
Min.
2.350
0.102
Normal
Max.
2.650
0.300
A
A1
b
0.406 (TYP.)
c
0.230
7.400
0.320
7.600
E
H
D
L
10.000
12.600
0.630
10.650
12.900
1.100
0.838
1.27 (TYP.)
e
0
8
θ
b
e
c
TITLE:
SOP-20L(300MIL) PACKAGE
OUTLINE DIMENSION
:
File
Edtion: A
SO20
Unit : mm
Scale: Free
Materia:l
Sheet: 1 of1
Figure B-5 EM78P374N 20-Pin SOP Package Type
120
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
C.6 EM78P374ND20 300 mil
Symbol
Min. Normal Max.
4.450
E
A
A1
A2
c
0.381
3.175
3.302
3.429
0.203 0.254 0.356
25.883 26.060 26.237
D
E1
E
6.220
7.370
8.510
6.438
7.620
9.020
6.655
7.870
9.530
eB
B
0.356 0.457 0.559
1.143 1.524 1.778
B1
L
3.302 3.556
2.540 (TYP.)
3.048
e
θ
0
15
:
TITLE
PDIP-20L 300MIL PACKAGE
OUTLINE DIMENSION
:
File
Edtion :A
D20
Unit :mm
Scale: Free
Material:
Sheet:1 of1
Figure B-6 EM78P374N 20-Pin PDIP Package Type
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
121
EM78P374N
8-bit Microcontroller
C.7 EM78P374NSO18 300 mil
Symbol Min.
Normal
Max.
2.650
0.300
2.350
A
A1
b
0.102
0.406 (TYP.)
0.230
7.400
0.320
7.600
c
E
10.000
11.350
0.406
10.650
11.750
1.270
H
D
L
0.838
1.27 (TYP.)
e
θ
0
8
b
e
c
TITLE:
SOP-18L(300MIL) PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
SO18
Unit: mm
Scale: Free
Material:
Sheet: 1 of1
Figure B-7 EM78P374N 18-Pin SOP Package Type
122
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
EM78P374N
8-bit Microcontroller
C.8 EM78P374ND18
Symbol
Min. Normal Max.
4.450
A
A1
A2
c
0.381
3.175
3.302
3.429
0.203 0.254 0.356
22.610 22.860 23.110
D
6.220
7.370
8.510
6.438
7.620
9.020
6.655
7.870
9.530
E1
E
eB
B
B1
L
0.356 0.457 0.559
1.143 1.524 1.778
eB
3.302 3.556
3.048
2.540 (TYP.)
e
θ
0
15
θ
TITLE:
PDIP-18L 300 MIL PACKAGE OUTLINE
DIMENSION
File:
Edtion: A
D18
Unit: mm
Scale: Free
Material:
Sheet: 1 of1
Figure B-8 EM78P374N 18-Pin PDIP Package Type
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
123
EM78P374N
8-bit Microcontroller
D Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=245 5 C, for 5 seconds up to the
Solderability
stopper using a rosin-type flux
Step 1: TCT, 65 C (15 min)~150 C (15 min), 10 cycles
Step 2: Bake at 125 C, TD (durance)=24 hrs
Step 3: Soak at 30 C / 60% , TD (durance)=192 hrs
For SMD IC (such as
SOP, QFP, SOJ, etc)
Step 4: IR flow 3 cycles
Pre-condition
(Pkg thickness 2.5 mm or
3
Pkg volume 350 mm 225 5 C)
(Pkg thickness 2.5 mm or
Pkg volume 350 mm 240 5 C)
3
Temperature cycle test
Pressure cooker test
-65 (15 min)~150 C (15 min), 200 cycles
TA =121 C, RH=100%, pressure=2 atm,
TD (durance) = 96 hrs
High temperature /
High humidity test
TA=85 C , RH=85% , TD (durance)=168 , 500 hrs
High-temperature
storage life
TA=150 C, TD (durance)=500, 1000 hrs
High-temperature
operating life
TA=125 C, VCC=Max. operating voltage,
TD (durance) =168, 500, 1000 hrs
TA=25 C, VCC=Max. operating voltage, 800mA/40V
Latch-up
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
°
TA=25 C, ≥ | ± 4KV |
ESD (HBM)
°
TA=25 C, ≥ | ± 400V |
ESD (MM)
VDD-VSS(+),VDD_VSS
(-) mode
D.1 Address Trap Detect
The Address Trap Detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise-caused address error is detected, the MCU will repeat execution of the
program until the noise is eliminated. The MCU will then continue to execute the next
program.
124
Product Specification (V1.8) 03.15.2016
(This specification is subject to change without prior notice)
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