EM78P468BQ64 [ELAN]
8-Bit Microcontroller;
| 型号： | EM78P468BQ64 |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microcontroller 微控制器 |
| 文件： | 总80页 (文件大小：2534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P468B
8-Bit Microcontroller
Product
Specification
DOC. VERSION 1.3
ELAN MICROELECTRONICS CORP.
March 2016
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation.
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation.
Copyright © 2004~2016 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan, ROC
The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Hsinchu Science Park
Hsinchu, TAIWAN 308
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Elan Information
Technology Group
(U.S.A.)
P.O. Box 601
Cupertino, CA 95015
U.S.A.
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Fax: +852 2723-7780
elanhk@emc.com.hk
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
5
6
General Description ................................................................................................ 1
Features ................................................................................................................... 1
Pin Assignment ....................................................................................................... 2
Pin Description........................................................................................................ 6
Block Diagram ....................................................................................................... 11
Functional Description.......................................................................................... 12
6.1 Operational Registers .....................................................................................12
6.1.1 R0, IAR (Indirect Addressing Register).............................................................12
6.1.2 R1, TCC (Timer Clock Counter)........................................................................12
6.1.3 R2, PC (Program Counter) ...............................................................................12
6.1.4 R3, SR (Status Register)..................................................................................14
6.1.5 R4, RSR (RAM Select Register).......................................................................15
6.1.6 R5, Port 5 (Port 5 I/O Data and Page of Register Select..................................15
6.1.7 R6, Port 6 (Port 6 I/O Data Register)................................................................15
6.1.8 R7, Port 7 (Port 7 I/O Data Register)................................................................16
6.1.9 R8, Port 8 (Port 8 I/O Data Register)................................................................16
6.1.10 R9, LCDCR (LCD Control Register) .................................................................16
6.1.11 RA, LCD_ADDR (LCD Address).......................................................................17
6.1.12 RB, LCD_DB (LCD Data Buffer).......................................................................17
6.1.13 RC, CNTER (Counter Enable Register) ...........................................................18
6.1.14 RD, SBPCR (System, Booster and PLL Control Register)...............................18
6.1.15 RE, IRCR (IR and Port 5 Setting Control Register) ..........................................21
6.1.16 RF, ISR (Interrupt Status Register) ...................................................................22
6.1.17 Address: 10h~3Fh; R10~R3F (General Purpose Register)..............................22
6.2 Special Purpose Registers..............................................................................23
6.2.1 A (Accumulator).................................................................................................23
6.2.2 IOC50, P5CR (Port 5 I/O and Ports 7, 8 for LCD Segment Control Register) 23
6.2.3 IOC60, P6CR (Port 6 I/O Control Register) ......................................................24
6.2.4 IOC70, P7CR (Port 7 I/O Control Register) ......................................................24
6.2.5 IOC80, P8CR (Port 8 I/O Control Register) ......................................................24
6.2.6 IOC90, RAM_ADDR (128 Bytes RAM Address)...............................................24
6.2.7 IOCA0, RAM_DB (128 Bytes RAM Data Buffer)...............................................25
6.2.8 IOCB0, CNT1PR (Counter 1 Preset Register)..................................................25
6.2.9 IOCC0, CNT2PR (Counter 2 Preset Register) .................................................25
6.2.10 IOCD0, HPWTPR (High-Pulse Width Timer Preset Register) ..........................26
6.2.11 IOCE0, LPWTPR (Low-Pulse Width Timer Preset Register)............................26
6.2.12 IOCF0, IMR (Interrupt Mask Register)..............................................................26
6.2.13 IOC61, WUCR (Wake-up and Sink Current of P57/IROUT Control Register).27
6.2.14 IOC71, TCCCR (TCC Control Register) ...........................................................27
Product Specification (V1.3) 03.25.2016
iii
Contents
6.2.15 IOC81, WDTCR (WDT Control Register)..........................................................28
6.2.16 IOC91, CNT12CR (Counters 1, 2 Control Register).........................................29
6.2.17 IOCA1, HLPWTCR (High/Low Pulse Width Timer Control Register) ..............30
6.2.18 IOCB1, P6PH (Port 6 Pull-high Control Register).............................................31
6.2.19 IOCC1, P6OD (Port 6 Open Drain Control Register)........................................31
6.2.20 IOCD1, P8PH (Port 8 Pull High Control Register)............................................32
6.2.21 IOCE1, P6PL (Port 6 Pull Low Control Register)..............................................32
6.3 TCC and WDT Prescaler ................................................................................32
6.4 I/O Ports .........................................................................................................35
6.6 Oscillator.........................................................................................................40
6.6.1 Oscillator Modes ...............................................................................................40
6.6.2 Phase Lock Loop (PLL Mode)...........................................................................40
6.6.3 Crystal Oscillator/Ceramic Resonators (Crystal) ..............................................41
6.6.4 RC Oscillator Mode with Internal Capacitor......................................................42
6.7 Power-on Considerations................................................................................42
6.7.1 External Power-on Reset Circuit.......................................................................43
6.7.2 Residue-Voltage Protection ..............................................................................43
6.8 Interrupt ..........................................................................................................44
6.9 LCD Driver......................................................................................................45
6.9.1 R9/LCDCR (LCD Control Register) ..................................................................45
6.9.2 RA/LCD_ADDR (LCD Address)........................................................................46
6.9.3 RB/LCD_DB (LCD Data Buffer)........................................................................46
6.9.4 RD/SBPCR (System, Booster and PLL Control Registers) ..............................47
6.10 Infrared Remote Control Application/PWM Waveform Generation .................51
6.11 Code Options..................................................................................................55
6.12 Instruction Set................................................................................................56
6.13 Timing Diagram ..............................................................................................59
7
8
Absolute Maximum Ratings.................................................................................. 60
Electrical Characteristics...................................................................................... 60
8.1 DC Electrical Characteristics...........................................................................60
8.2 AC Electrical Characteristics...........................................................................62
iv
Product Specification (V1.3) 03.25.2016
Contents
APPENDIX
A
B
C
D
E
Ordering and Manufacturing Information............................................................ 63
Package Type......................................................................................................... 65
Package Information ............................................................................................. 66
EM78P468B Program Pin List............................................................................... 72
Quality Assurance and Reliability ........................................................................ 73
E.1 Address Trap Detect.......................................................................................73
Product Specification (V1.3) 03.25.2016
v
Contents
Specification Revision History
Doc. Version
Date
Revision Description
1.0
1.1
2013/05/08
2013/09/27
Preliminary version
Modified the Pin Description information
1. Modified the Features description
1.2
1.3
2015/06/02
2016/03/25
2. Added EM78P468BL48 (LQFP-48) package
Modified the package information
vi
Product Specification (V1.3) 03.25.2016
EM78P468B
8-Bit Microcontroller
1 General Description
The EM78P468B is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. Integrated onto a single chip are on chip Watchdog Timer (WDT), Data RAM, ROM,
Programmable Real Time Clock Counter, Internal/External Interrupt, Power-down mode, LCD driver,
Infrared Transmitter function, and tri-state I/O. The series has an on-chip 4K13-bit Electrical One Time
Programmable Read Only Memory (OTP-ROM). The EM78P468B provides multi-protection bits to prevent
intrusion of user’s OTP memory code. Seven Code option bits are available to meet user’s requirements.
Special 13 bits customer ID options are provided as well.
With its enhanced OTP-ROM feature, the EM78P468B provides a convenient way of developing and
verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program
updates, using development and programming tools. Users can avail of the ELAN Writer to easily program
their development code.
2 Features
Peripheral Configuration
CPU Configuration
8-bit real Time Clock/Counter (TCC)
4K13 bits on-chip OTP-ROM
144 bytes general purpose register
128 bytes on-chip data RAM
272 bytes SRAM
One infrared transmitter/PWM generator function
Four sets of 8 bits auto reload down-counting
timer can be used as interrupt sources
Counter 1: independent down-counting timer
Counter 2, High Pulse Width Timer (HPWT),
and Low Pulse Width Timer (LPWT) shared
with IR function.
144 bytes general purpose register
128 bytes on-chip data RAM
8-level stacks for subroutine nesting
Power-on voltage detector provided
(1.70.1V) for EM78P468B
Programmable free running on-chip Watchdog
Timer (WDT). This function can operate in
Normal, Green and Idle mode.
I/O Port Configuration
Typically, 12 bidirectional tri-state I/O ports.
Eight Interrupt Sources: 3 External and 5 Internal
Internal interrupt source: TCC; Counters 1 and 2
High/Low pulse width timer
16 bidirectional tri-state I/O ports shared with
LCD segment output pin.
Up to 28 bidirectional tri-state I/O ports
External interrupt source : INT0, INT1 and Pin
change wake-up (Port 6 and Port 8)
LCD Circuit
Common driver pins: 4
Segment driver pins: 32
LCD Bias: 1/3, 1/2 bias
LCD Duty: 1/4, 1/3, 1/2 duty
Package Type:
Operating Voltage and Temperature Range:
Commercial: 2.1V ~ 5.5V. (at 0 C ~+70 C)
Industrial: 2.3V ~ 5.5V. (at -40 C ~+85 C)
Operating Mode:
Normal mode: The CPU is operated on main
oscillator frequency (Fm)
Green mode: The CPU is operated on
sub-oscillator frequency (Fs) and main
oscillator (Fm) is stopped
Dice form: 59 pins
QFP-64 pin: EM78P468BQ64
(Body 14mm20mm)
LQFP-64 pin: EM78P468BL64
(Body 7mm7mm)
Idle mode: CPU idle, LCD display remains
working
Sleep mode: The whole chip stops working
Input port wake-up function (Port 6, Port 8).
LQFP-44 pin: EM78P468BL44
(Body 10mm10mm)
Works on Idle and Sleep mode.
Operation speed: DC ~ 10 MHz clock input
Dual clock operation
QFP-44 pin: EM78P468BQ44
(Body 10mm10mm)
QFP-64 pin: EM78P468BQ64B
(Body 14mm14mm)
Oscillation Mode
High frequency oscillator can select among
LQFP-48 pin: EM78P468BL48
(Body 7mm7mm)
Crystal, RC, or PLL (phase lock loop)
Low frequency oscillator can select between
Note: These are Green products which do not
Crystal or RC mode
contain hazardous substances
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
1
EM78P468B
8-Bit Microcontroller
3 Pin Assignment
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
SEG28/P84
SEG27/P83
SEG26/P82
SEG25/P81
SEG24/P80
SEG23/P77
SEG22/P76
SEG21/P75
SEG20/P74
SEG19/P73
SEG18/P72
SEG17/P71
SEG16/P70
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
P54/INT0
XOUT
XIN
VDD
OSCO
R-OSCI
GND
EM78P468BQ64
QFP64
/ RESET
VLCD3
VLCD2
VA
VB
COM0
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
1
2
3
4
5
6
7
8
9
Figure 3-1 64-pin QFP EM78P468BQ64 Pin Assignment
2
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
P54/INT0
NC
SEG30/P86
SEG29/P85
SEG28/P84
SEG27/P83
SEG26/P82
SEG25/P81
SEG24/P80
SEG23/P77
SEG22/P76
SEG21/P75
SEG20/P74
SEG19/P73
SEG18/P72
SEG17/P71
SEG16/P70
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
XOUT
XIN
VDD
OSCO
R-OSCI
GND
/RESET
VLCD3
VLCD2
VA
EM78P468BL64
EM78P468BQ64B
VB
COM0
COM1
COM2
COM3
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
2
3
4
5
6
7
8
9
Figure 3-2 64-Pin LQFP/QFP EM78P468BL64/EM78P468BQ64B Pin Assignment
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
3
EM78P468B
8-Bit Microcontroller
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
SEG27/P83
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P55/INT1
P54/INT0
XOUT
SEG26/P82
SEG25/P81
SEG24/P80
SEG23/P77
SEG22/P76
SEG21/P75
SEG20/P74
SEG19/P73
SEG18/P72
SEG17/P71
EM78P468BQ44
EM78P468BL44
XIN
VDD
OSCO
R-OSCI
GND
LQFP-44
QFP-44
/RESET
VLCD3
VLCD2
1
0
1
1
1
2
3
4
5
6
7
8
9
Figure 3-3 44-Pin LQFP/QFP EM78P468BQ44/EM78P468BL44 Pin Assignment
Input Pin
Output Pin
Input/Output Pin
Digital I/O Pin/LCD Output Pin
LCD Output Pin
4
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
R- OSCI
P65
P66
24
23
22
21
20
19
18
17
16
15
37
38
39
40
41
42
43
GND
/ RESET
VLCD3
P67
28/P 84
SEG
VLCD2
VA
SEG20/P 74
SEG19/P 73
EM78P468BL48
LQFP-48
VB
18 /P 72
SEG
COM0
COM1
SEG17/P 71
SEG16/P70
44
45
COM2
46
47
48
SEG15
SEG14
14
13
COM3
SEG 0
SEG13
1
2
1
0
1
1
1
2
3
4
5
6
7
8
9
Figure 3-4 48-Pin LQFP EM78P468BL48 Pin Assignment
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
5
EM78P468B
8-Bit Microcontroller
4 Pin Description
Input
Type
Output
Type
Symbol
Function
Description
P54
ST
CMOS Bidirectional I/O pin
External interrupt pin. The INT0 interrupt
source can be set to falling or rising edge by
IOC71 register Bit 7 (INT_EDGE).
P54/INT0
(ACLK)
INT0
ST
Wakes up from Sleep mode and Idle mode
when the pin status changes.
(ACLK)
P55
ST
ST
ACLK pin for Writer programming
Bidirectional I/O pin
CMOS
External interrupt pin
P55/INT1
(DINCK)
The Interrupt source is a falling edge signal.
INT1
ST
Wakes up from Sleep mode and Idle mode
when the pin status changes.
(DINCK)
P56
ST
ST
DINCK pin for Writer programming
Bidirectional I/O pin. This pin works in Normal/
Green/Idle mode.
CMOS
P56/TCC
(DATAIN)
TCC
ST
ST
TCC External input pin
(DATAIN)
DATAIN pin for Writer programming
Bidirectional I/O pin. This pin is capable of
sinking 20 mA / 5V.
P57
ST
ST
CMOS
P57/IROUT
IROUT
IR/PWM mode output pin
Programmable pull-high, pull-down and
P60
(PGMB)
P61
ST
ST
ST
ST
CMOS open-drain. All pins wake up from Sleep and
Idle modes when the pin status changes.
P60
(PGMB)
PGMB pin for Writer programming
Programmable pull-high, pull-down and
CMOS open-drain. All pins wake up from Sleep and
Idle modes when the pin status changes.
P61
(OEB)
(OEB)
OEB pin for Writer programming
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes.
P62
P63
P62
P63
ST
ST
CMOS
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes.
CMOS
6
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Input
Type
Output
Type
Symbol
Function
Description
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes.
P64
P64
ST
ST
ST
ST
CMOS
CMOS
CMOS
CMOS
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes.
P65
P66
P67
P65
P66
P67
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes.
Bidirectional I/O pin with programmable
pull-high, pull-down and open-drain. All pins
wake up from Sleep and Idle modes when the
pin status changes.
COM3~0
SEG0~15
COM3~0
SEG0~15
SEG16
AN
AN
AN
LCD common output pin
LCD segment output pin
LCD segment output pin
Bidirectional I/O pin. All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes.
SEG16/P70
SEG17/P71
SEG18/P72
SEG19/P73
SEG20/P74
SEG21/P75
P70
SEG17
P71
ST
AN
LCD segment output pin
Bidirectional I/O pin. All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes.
ST
SEG18
P73
AN
LCD segment output pin
Bidirectional I/O pin. All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes.
ST
SEG19
P73
AN
LCD segment output pin
Bidirectional I/O pin. All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes.
ST
SEG20
P74
AN
LCD segment output pin
Bidirectional I/O pin. All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes.
ST
SEG21
P75
AN
LCD segment output pin
Bidirectional I/O pin. All pins wake up from
CMOS Sleep and Idle modes when the pin status
changes.
ST
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
7
EM78P468B
8-Bit Microcontroller
Input
Type
Output
Type
Symbol
Function
Description
SEG22
ST
AN
LCD segment output pin
Bidirectional I/O pin. All pins wake up from
SEG22/P76
SEG23/P77
SEG24/P80
SEG25/P81
SEG26/P82
SEG27/P83
SEG28/P84
SEG29/P85
P76
SEG23
P77
CMOS Sleep and Idle modes when the pin status
changes.
AN
LCD segment output pin
Bidirectional I/O pin. All pins wake up from
ST
CMOS Sleep and Idle modes when the pin status
changes.
SEG24
P80
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes.
SEG25
P81
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes.
SEG26
P82
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes.
SEG27
P83
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes.
SEG28
P84
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes.
SEG29
P85
AN
LCD segment output pin
Bidirectional I/O pin with programmable
ST
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes.
SEG30
AN
LCD segment output pin
Bidirectional I/O pin with programmable
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes.
SEG30/P86
SEG31/P87
P86
SEG31
P87
ST
AN
LCD segment output pin
Bidirectional I/O pin with programmable
CMOS pull-high. All pins wake up from Sleep and Idle
modes when the pin status changes.
ST
8
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Input
Type
Output
Type
Symbol
VB
Function
Description
VB
AN
AN
AN
AN
Connects capacitors for LCD bias voltage
Connects capacitors for LCD bias voltage
One of LCD bias voltage
VA
VA
VLCD2
VLCD3
VLCD2
VLCD3
One of LCD bias voltage
General-purpose Input only
Low active. If it remains at logic low, the device
will reset.
/RESET
VPP
ST
ST
/RESET
(VPP)
/RESET pin for writer programming
Vpp pin for Writer programming
In Crystal mode: crystal input
In RC mode: resistor pull high
In PLL mode: connect a 0.01F capacitance to
R-OSCI
R-OSCI
AN
GND
Connect a 0.01 F capacitor to GND and code
option selects PLL mode when high oscillator
is not used.
In Crystal mode: crystal input
OSCO
Xin
OSCO
Xin
XTAL
In RC mode: instruction clock output
In Crystal mode: Input pin for sub-oscillator.
Connect to a 32.768kHz crystal.
XTAL
In Crystal mode: Connect to a 32.768kHz
crystal.
Xout
Xout
XTAL
In RC mode: instruction clock output
NC
NC
No connection
Power
VDD
GND
VDD
GND
Power
Power
Ground
Legend: ST: Schmitt Trigger input
AN: analog pin
CMOS: CMOS output
XTAL: oscillation pin for crystal / resonator
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
9
EM78P468B
8-Bit Microcontroller
Pin Status with Enabled Functions
I/O Status
Pin Control
Pull Low
Pin Function
Pin Change
I/O Direction
Pull High
O.D.
WK/Int.
General Input
General Output
TCC
Input
Output
Input
Input
Output
Input
Input
Input
Input
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
S/W
S/W
LCD Driver
TC-OUT
Reset
Disable
Initial: Enable
S/W
Disable
S/W
S/W
EX_INT
S/W
S/W
OSCI
Disable
Disable
Disable
Disable
OSCO
Disable It is always disabled
Enable It is always enabled
S/W It can be controlled by the register, the initial value is disabled.
1. If the pin is not working as general I/O, it is a must to disable the Pin Change
Wake-up/Interrupt function.
2. Priority: digital function output > digital function input > general I/O
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Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
5 Block Diagram
P8
Crystal
RC
PC
P80
ROM
P81
P82
P83
P84
P85
P86
P87
Oscillation
Generation
8-level stack
(13-bit)
Instruction
Register
P7
LCD
Rese
t
PLL
P70
P71
P72
P73
P74
Instruction
Decoder
WDT
PWM
TCC
PWM1/IR
(Timer 1,2)
P75
P76
P77
TCC
Mux.
ALU
CNTR1
CNTR2
CNTR 1
P6
CNTR 2
R4
P60
P61
P62
P63
P64
RAM
P65
P66
P67
Interrupt
Control
Register
R3 (Status
Reg.)
ACC
P5
Interrupt
Circuit
P54
P55
P56
P57
Ext INT
Figure 5 System Block Diagram
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
11
EM78P468B
8-Bit Microcontroller
6 Functional Description
6.1 Operational Registers
6.1.1 R0, IAR (Indirect Addressing Register)
(Address: 00h)
R0 is not a physically implemented register. Its major function is to perform as an
indirect address pointer. Any instruction using R0 as a register, actually accesses the
data pointed by the RAM Select Register (R4).
6.1.2 R1, TCC (Timer Clock Counter)
(Address: 01h)
The Timer Clock Counter is incremented by an external signal edge applied to TCC, or
by the instruction cycle clock. It is written and read by the program as any other
register.
6.1.3 R2, PC (Program Counter)
(Address: 02h)
R3
000H
Reset vector
003H
PC A11 A10 A9
CALL
A8
A7
~
A0
TCC overflow interrupt vector
006H
009H
00CH
00FH
012H
015H
018H
External INT0 pin interrupt vector
00 PAGE0 0000~03FF
External INT1 pin interrupt vector
RET
Counter 1 underflow interrupt vector
Counter 2 underflow interrupt vector
High pulse width timer underflow interrupt vector
Low pulse width timer underflow interrupt vector
Port 6/Port 8 pin change wake-up interrupt vector
RETL
RETI
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Stack 6
Stack 7
Stack 8
11 PAGE3 0C00~0FFF
On-chip Program Memory
FFFH
Figure 6-1 Program Counter Organization
The structure of R2 is depicted in Figure 6-1, Program Counter Organization.
The configuration structure generates 4K13 bits on-chip ROM addresses to the
relative programming instruction codes.
The contents of R2 are all set to "0"s when a Reset condition occurs.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows the PC to jump to any location within a page.
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(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
"CALL" instruction loads the lower 10 bits of the PC, and PC+1 are pushed onto the
stack. Thus, the subroutine entry address can be located anywhere within a page.
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
at the top of the stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increment progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.
The most significant bits (A10~A11) will be loaded with the content of PS0~PS1 in
the Status register (R3) upon execution of a "JMP" or "CALL" instruction.
SBANK0
ADDRESS
00
IOCPAGE0
IOCPAGE1
R0
01
R1 (TCC)
R2 (PC)
02
R3
03
(Status & ROM page)
04
R4 (RAM selection)
R5 (Port 5 & IOC page)
R6 (Port 6)
IOC50
(Port 5 IO control)
IOC60
05
IOC51 (unused)
IOC61
06
(Port 6 IO control)
IOC 70
(Port 7 IO control)
IOC80
(Port 8 IO control)
IOC90
(RAM Address)
IOCA0
(Wake-up register)
IOC71
(TCC control)
IOC81
(WDT control)
IOC91
(CNT1/2 control)
IOCA1
07
R7 (Port 7)
08
R8 (Port 8)
09
R9 (LCD control)
RA
0A
(LCD contrast & addr.)
(RAM Data)
(H/L pulse time control)
0B
RB (LCD data)
IOCB0 (CNT1 preset)
IOCB1 (Port 6 pull-high)
RC
IOCC1
(Port 6 open-drain)
0C
0D
0E
IOCC0 (CNT2 preset)
(Counter enable reg.)
RD
(System Clock control)
IOCD0 (High pulse timer
preset)
IOCE0
IOCD1 (Port 8 pull-high)
IOCE1
(Low pulse timer preset) (Port 6 pull down)
RE (IR control)
0F
RF (Interrupt status)
IOCF0 (interrupt mask ) IOCF1 (unused)
10
|
16 byte common register
1F
20
|
3F
Bank 0
Bank 1
Bank 2
Bank 3
32 byte common register 32 byte common register 32 byte common register 32 byte common register
Figure 6-2 Data Memory Configuration
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
13
EM78P468B
8-Bit Microcontroller
6.1.4 R3, SR (Status Register)
(Address: 03h)
Bit 7
Bit 6
Bit 5
PS0
R/W
Bit 4
T
Bit 3
P
Bit 2
Z
Bit 1
DC
Bit 0
C
PS1
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7: Not used
Bits 6 ~ 5 (PS1 ~ 0): Page Select bits
PS1
0
PS0
0
ROM Page (Address)
Page 0 (000H ~ 3FFH)
Page 1 (400H ~ 7FFH)
Page 2 (800H ~ BFFH)
Page 3 (C00H ~ FFFH)
0
1
1
0
1
1
PS0~PS1 are used to select a ROM page. User can use the PAGE instruction (e.g.
PAGE 1) or set PS1~PS0 bits to change the ROM page. When executing a "JMP",
"CALL", or other instructions which causes the program counter to be changed (e.g.
MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter
where it selects one of the available program memory pages. Note that RET (RETL,
RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be
to the page from where the subroutine was called, regardless of the current setting of
PS0~PS1 bits.
Bit 4 (T): Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during
power up and reset to “0” by WDT timeout.
Event
T
0
0
1
1
1
P
0
1
0
1
1
Remark
WDT wake up from sleep mode
WDT time out (not sleep mode)
/RESET wake up from sleep
Power up
Low pulse on /RESET
: don't care
Bit 3 (P): Power down bit. Set to “1” during power on or by a "WDTC" command and
reset to “0” by a "SLEP" command.
Bit 2 (Z): Zero flag
Bit 1 (DC): Auxiliary Carry flag
Bit 0 (C): Carry flag
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(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
6.1.5 R4, RSR (RAM Select Register)
(Address: 04h)
Bit 7
RBS1
R/W
Bit 6
RBS0
R/W
Bit 5
RSR5
R/W
Bit 4
RSR4
R/W
Bit 3
RSR3
R/W
Bit 2
RSR2
R/W
Bit 1
RSR1
R/W
Bit 0
RSR0
R/W
Bits 7 ~ 6 (RBS1 ~ RBS0): determine which bank is activated among the four banks.
See the data memory configuration in Figure 6-2. Use the Bank Instruction (e.g.
Bank 1) to change banks.
Bits 5 ~ 0 (RSR5 ~ RSR0): used to select up to 64 registers (Address: 00~3F) in
indirect addressing mode. If no indirect addressing is used, the RSR can be used
as an 8-bit general purpose read/writer register.
6.1.6 R5, Port 5 (Port 5 I/O Data and Page of Register Select
(Address: 05h)
Bit 7
R57
R/W
Bit 6
R56
R/W
Bit 5
R55
R/W
Bit 4
R54
R/W
Bit 3
Bit 2
Bit 1
Bit 0
IOCPAGE
R/W
-
-
-
Bits 7~4: Four bits I/O registers of Port 5
User can use the IOC50 register to define each bit either as input or output.
Bits 3~1: Not used
Bit 0 (IOCPAGE): change IOC5 ~ IOCF to another page
IOCPAGE = “0” : Page 0 (select register of IOC50 to IOC F0)
IOCPAGE = “1” : Page 1 (select register of IOC61 to IOC E1)
6.1.7 R6, Port 6 (Port 6 I/O Data Register)
(Address: 06h)
Bit 7
R67
R/W
Bit 6
R66
R/W
Bit 5
R65
R/W
Bit 4
R64
R/W
Bit 3
R63
R/W
Bit 2
R62
R/W
Bit 1
R61
R/W
Bit 0
R60
R/W
Bits 7~0: 8-bit I/O registers of Port 6
User can use the IOC60 register to define each bit either as input or output.
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
15
EM78P468B
8-Bit Microcontroller
6.1.8 R7, Port 7 (Port 7 I/O Data Register)
(Address: 07h)
Bit 7
R77
R/W
Bit 6
Bit 5
R75
R/W
Bit 4
R74
R/W
Bit 3
R73
R/W
Bit 2
R72
R/W
Bit 1
R71
R/W
Bit 0
R70
R/W
R76
R/W
Bits 7~0: 8-bit I/O registers of Port 7
User can use the IOC70 register to define each bit either as input or output.
6.1.9 R8, Port 8 (Port 8 I/O Data Register)
(Address: 08h)
Bit 7
R87
R/W
Bit 6
R86
R/W
Bit 5
R85
R/W
Bit 4
R84
R/W
Bit 3
R83
R/W
Bit 2
R82
R/W
Bit 1
R81
R/W
Bit 0
R80
R/W
Bits 7~0: 8-bit I/O registers of Port 8
User can use the IOC80 register to define each bit either as input or output.
6.1.10 R9, LCDCR (LCD Control Register)
(Address: 09h)
Bit 7
BS
Bit 6
DS1
R/W
Bit 5
DS0
R/W
Bit 4
LCDEN
R/W
Bit 3
Bit 2
LCDTYPE LCDF1
R/W R/W
Bit 1
Bit 0
LCDF0
R/W
-
-
R/W
Bit 7 (BS): LCD bias select bit
BS = "0": 1/2 bias
BS = "1": 1/3 bias
Bit 6 ~ 5 (DS1 ~ DS0): LCD duty select
DS1
DS0
LCD Duty
1/2 duty
1/3 duty
1/4 duty
0
0
1
0
1
Bit 4 (LCDEN): LCD enable bit
LCDEN = "0": LCD circuit disabled. All common/segment outputs are set to
ground (GND) level.
LCDEN = "1": LCD circuit enabled.
Bit 3: Not used
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Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Bit 2 (LCDTYPE): LCD drive waveform type select bit
LCDTYPE = "0": A type waveform
LCDTYPE = "1": B type waveform
Bits 1 ~ 0 (LCDF1~LCDF0): LCD frame frequency control bits
LCD Frame Frequency (e.g. Fs=32.768kHz)
LCDF1
LCDF0
1/2 Duty
1/3 Duty
1/4 Duty
0
0
1
1
0
1
0
1
Fs/(2562)=64.0
Fs/(2802)=58.5
Fs/(3042)=53.9
Fs/(2322)=70.6
Fs/(1723)=63.5
Fs/(1883)=58.0
Fs/(2043)=53.5
Fs/(1563)=70.0
Fs/(1284)=64.0
Fs/(1404)=58.5
Fs/(1524)=53.9
Fs/(1164)=70.6
Note: Fs: sub-oscillator frequency
6.1.11 RA, LCD_ADDR (LCD Address)
(Address: 0Ah)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
R/W
R/W
R/W
R/W
R/W
Bits 7~5: Not used, fixed at “0”
Bits 4~0 (LCDA4 ~ LCDA0): LCD RAM addresses
RB (LCD Data Buffer)
RA
Segment
Bit 3
Bit 2
Bit 1
Bit 0
(LCD Address)
Bits 7 ~4
(LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
00H
01H
SEG0
SEG1
SEG2
|
02H
|
|
1DH
1EH
SEG29
SEG30
SEG31
1FH
Common
COM3
COM2
COM1
COM0
6.1.12 RB, LCD_DB (LCD Data Buffer)
(Address: 0Bh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD_D3 LCD_D2 LCD_D1 LCD_D0
R/W R/W R/W R/W
-
-
-
-
Bits 7~4: Not used
Bits 3~0 (LCD_D3 ~ LCD_D0): LCD RAM data transfer register
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
17
EM78P468B
8-Bit Microcontroller
6.1.13 RC, CNTER (Counter Enable Register)
(Address: 0Ch)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
LPWTEN HPWTEN CNT2EN CNT1EN
R/W R/W R/W R/W
Bit 2
Bit 1
Bit 0
-
-
-
-
Bits 7, 5: Not used, must be fixed to “0”
Bits 6, 4: Not used
Bit 3 (LPWTEN): Low pulse width timer enable bit
LPWTEN = "0": Disable LPWT. Stop counting operation.
LPWTEN = "1": Enable LPWT. Start counting operation.
Bit 2 (HPWTEN): High pulse width timer enable bit
HPWTEN = "0": Disable HPWT. Stop counting operation.
HPWTEN = "1": Enable HPWT. Start counting operation.
Bit 1 (CNT2EN): Counter 2 enable bit
CNT2EN = "0": Disable Counter 2. Stop counting operation.
CNT2EN = "1": Enable Counter 2. Start counting operation.
Bit 0 (CNT1EN): Counter 1 enable bit
CNT1EN = "0": Disable Counter 1. Stop counting operation.
CNT1EN = "1": Enable Counter 1. Start counting operation.
6.1.14 RD, SBPCR (System, Booster and PLL Control Register)
(Address: 0Dh)
Bit 7
Bit 6
CLK2
R/W
Bit 5
CLK1
R/W
Bit 4
CLK0
R/W
Bit 3
IDLE
R/W
Bit 2
BF1
R/W
Bit 1
BF0
R/W
Bit 0
CPUS
R/W
Bit 7: Not used
Bits 6 ~ 4 (CLK2 ~ CLK0): Main clock select bits for PLL mode (Code Option Select)
CLK2
CLK1
CLK0
Main clock
Fs130
Fs65
Example Fs=32.768K
4.26 MHz
0
0
0
0
1
0
0
1
1
0
1
0
1
2.13 MHz
Fs65/2
Fs65/4
Fs244
1.065 MHz
532 kHz
8 MHz
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Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Bit 3 (IDLE): Idle mode enable bit. This bit will determine the intended mode of the
SLEP instruction.
Idle = ”0”+SLEP instruction Sleep mode
Idle = ”1”+SLEP instruction Idle mode
* NOP instruction must be added after SLEP instruction.
Example:
Idle mode: Idle bit = "1" +SLEP instruction + NOP instruction
Sleep mode: Idle bit = "0" +SLEP instruction + NOP instruction
Bits 2, 1 (BF1, 0): LCD booster frequency select bit to adjust VLCD 2, 3 driving.
BF1
0
BF0
0
Booster Frequency
Fs
0
1
Fs/4
Fs/8
Fs/16
1
0
1
1
Bit 0 (CPUS): CPU oscillator source select. When CPUS=0, the CPU oscillator select
sub-oscillator and the main oscillator is stopped.
CPUS = "0": sub-oscillator (Fs)
CPUS = "1": main oscillator (Fm)
CPU Operation Mode
Code option
HLFS=1
RESET
Normal Mode
Code option
HLFS=0
fm:oscillation
fs: oscillation
It must delay for some time for the main
oscillation to be stable while the system timing
control is precisely maintained.
CPU: using fosc
CPUS="0"
CPUS="1"
IDLE="0"
SLEP
IDLE="1"
SLEP
SLEEP Mode
Green Mode
IDLE Mode
Fm:stop
Fs: stop
fm:stop
fs: oscillation
fm:stop
fs: oscillation
Wake up
wake up
CPU: stop
CPU: using fs
CPU: stop
The wake up time from idle to green
mode is 16*1/fs
The wake up time from sleep to green mode is
approximately sub-oscillator setup time +18 ms +16*1/fs
Figure 6-3 CPU Operation Mode
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
19
EM78P468B
8-Bit Microcontroller
Note
(*) If the Watchdog function is enabled before going into Sleep mode, some circuits like
the Timer (its Clock Source is Fs) must stop counting.
If the Watchdog function is enabled before going into Sleep mode, some circuits like the
Timer (its Clock Source is the external pin) can still count and its interrupt flag can be active
at matching condition as corresponding interrupt is enabled. But the CPU cannot be
awakened by this event.
(**)
Switching Operation Mode at Sleep Normal,
Green Normal:
If the Timer Clock Source is Fm, the Timer/Counter must stop counting at Sleep or Green
mode. Then, the Timer can continue to count until the Clock Source is stable at Normal
mode. That the Clock Source is stable means the CPU starts to work at Normal mode.
Switching Operation Mode at Sleep Green:
If the Timer Clock Source is Fs, the Timer must stop counting at Sleep mode. Then, the
Timer can continue to count until the Clock Source is stable at Green mode. That the Clock
Source is stable means the CPU starts to work at Green mode.
Switching Operation Mode at Sleep Normal:
If the Timer Clock Source is Fs, the Timer must stop counting at Sleep mode. Then, the
Timer can continue to count until the Clock Source is stable at Normal mode. That the Clock
Source is stable means the CPU starts to work at Normal mode.
Pin-Reset
Power-on
WDT
Fmain Fsub
LVR
N / G / I
S
RC 18ms+WSTO+15*1/Fsub 18ms+WSTO+15*1/ Fsub 18ms+WSTO+15*1/ Fsub
XT 18ms+WSTO+15*1/Fsub 18ms+WSTO+15*1/ Fsub 18ms+WSTO+15*1/ Fsub
RC 18ms+WSTO+15*1/Fsub 18ms+WSTO+15*1/ Fsub 18ms+WSTO+15*1/ Fsub
XT 18ms+WSTO+15*1/Fsub 18ms+WSTO+15*1/Fsub 18ms+WSTO+15*1/Fsub
RC
XT
Fmain Fsub
G N
I N
S N
RC
XT
RC
XT
WSTO + 11*1/Fmain
WSTO + 11*1/Fmain
WSTO + 11*1/Fmain
WSTO + 11*1/Fmain
WSTO + 15*1/ Fsub
WSTO + 15*1/ Fsub
WSTO + 15*1/ Fsub
WSTO + 15*1/ Fsub
18ms + WSTO + 15*1/ Fsub
18ms + WSTO + 15*1/ Fsub
18ms + WSTO + 15*1/ Fsub
18ms + WSTO + 15*1/Fsub
RC
XT
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Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Fmain
Fsub
IRC
XT
I G
S G
WSTO + 15*1/Fsub
WSTO + 15*1/Fsub
18ms + WSTO + 15*1/ Fsub
18ms + WSTO + 15*1/ Fsub
IRC
IRC
XT
WSTO + 15*1/Fsub
WSTO + 15*1/Fsub
18ms + WSTO + 15*1/ Fsub
18ms + WSTO + 15*1/Fsub
XT
WSTO: Waiting Time from Start-to-Oscillation
N: Normal mode G: Green mode
I: Idle mode
S: Sleep mode
6.1.15 RE, IRCR (IR and Port 5 Setting Control Register)
(Address: 0Eh)
Bit 7
IRE
Bit 6
HF
Bit 5
LGP
R/W
Bit 4
Bit 3
IROUTE
R/W
Bit 2
TCCE
R/W
Bit 1
EINT1
R/W
Bit 0
EINT0
R/W
R/W
R/W
-
Bit 7 (IRE): Infrared Remote Enable bit
IRE = "0": Disable the IR/PWM function. The state of P57/IROUT pin is
determined by Bit 7 of IOC 50 if it is for IROUT.
IRE = "1": Enable IR or PWM function
Bit 6 (HF): High carry frequency
HF = "0": For PWM application, disable the H/W modulator function. The IROUT
waveform is generated according to high-pulse and low-pulse time as
determined by the respective high pulse and low pulse width timers.
Counter 2 is an independent auto reload timer.
HF = "1": For IR application mode, enable the H/W modulator function, the low
time sections of the generated pulse is modulated with the Fcarrier
frequency. The Fcarrier frequency is provided by Counter 2.
Bit 5 (LGP): IROUT for of low pulse width timer
LGP = "0": The high-pulse width timer register and low-pulse width timer is valid.
LGP = "1": The high-pulse width timer register is ignored. So the IROUT
waveform is dependent on the low-pulse width timer register only.
Bit 4: Not used
Bit 3 (IROUTE): Define the function of P57/IROUT pin
IROUTE = "0": for bidirectional general I/O pin
IROUTE = "1": for IR or PWM output pin, the control bit of P57 (Bit 7 of IOC50)
must be set to “0”
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
21
EM78P468B
8-Bit Microcontroller
Bit 2 (TCCE): Define the function of P56/TCC pin
TCCE = "0": for bidirectional general I/O pin
TCCE = "1": for external input pin of TCC, the control bit of P56 (Bit 6 of IOC50)
must be set to “1”
Bit 1 (EINT1): Define the function of P55/INT1 pin
EINT1 = "0": for bidirectional general I/O pin
EINT1 = "1": for external interrupt pin of INT1, the control bit of P55 (Bit 5 of
IOC50) must be set to “1”
Bit 0 (EINT0): Define the function of P54/INT0 pin
EINT0 = "0": for bidirectional general I/O pin
EINT0 = "1": for external interrupt pin of INT0, the control bit of P54 (Bit 4 of
IOC50) must be set to “1”
6.1.16 RF, ISR (Interrupt Status Register)
(Address: 0Fh)
Bit 7
ICIF
F
Bit 6
LPWTF
F
Bit 5
HPWTF
F
Bit 4
CNT2F
F
Bit 3
CNT1F
F
Bit 2
INT1F
F
Bit 1
INT0F
F
Bit 0
TCIF
F
These bits are set to “1” when interrupt occurs.
Bit 7 (ICIF): Port 6, Port 8, input status changed interrupt flag. Set when Port 6, Port 8
input changes.
Bit 6 (LPWTF): Interrupt Flag of the internal Low-Pulse Width Timer underflow.
Bit 5 (HPWTF): Interrupt Flag of the internal High-Pulse Width Timer underflow.
Bit 4 (CNT2F): Interrupt Flag of the internal Counter 2 underflow.
Bit 3 (CNT1F): Interrupt Flag of the internal Counter 1 underflow.
Bit 2 (INT1F): External INT1 pin Interrupt Flag
Bit 1 (INT0F): External INT0 pin Interrupt Flag
Bit 0 (TCIF): TCC timer overflow Interrupt Flag. Set when TCC timer overflows.
6.1.17 Address: 10h~3Fh; R10~R3F (General Purpose Register)
R10~R31F and R20~R3F (Banks 0~3) are general purpose registers.
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EM78P468B
8-Bit Microcontroller
6.2 Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
Registers of IOC Page 0 (IOC50 ~ IOCF0, Bit 0 of R5 = “0”)
6.2.2 IOC50, P5CR (Port 5 I/O and Ports 7, 8 for LCD Segment
Control Register)
(Address: 05h, Bit 0 of R5 = “0”)
Bit 7
IOC57
R/W
Bit 6
IOC56
R/W
Bit 5
IOC55
R/W
Bit 4
IOC54
R/W
Bit 3
P8HS
R/W
Bit 2
P8LS
R/W
Bit 1
P7HS
R/W
Bit 0
P7LS
R/W
Bits 7~4 (IOC57~54): Port 5 I/O direction control register
IOC5x = "0": set the relative P5x I/O pins as output
IOC5x = "1": set the relative P5x I/O pin into high impedance (input pin)
Bit 3 (P8HS): Switch to high nibble I/O of Port 8 or to LCD segment output while
sharing pins with SEGxx/P8x pins.
P8HS = "0": select high nibble of Port 8 as normal P84~P87
P8HS = "1": select LCD segment output as SEG 28~SEG 31 output
Bit 2 (P8LS): Switch to low nibble I/O of Port 8 or to LCD segment output while sharing
pins with SEGxx/P8x pins
P8LS = "0": select low nibble of Port 8 as normal P80~P83
P8LS = "1": select LCD Segment output as SEG 24~SEG 27 output
Bit 1 (P7HS): Switch to high nibble I/O of Port 7 or to LCD segment output while
sharing pins with SEGxx/P7x pins
P7HS = "0": select high nibble of Port 7 as normal P74~P77
P7HS = "1": select LCD Segment output as SEG 20~SEG 23 output
Bit 0 (P7LS): Switch to low nibble I/O of Port 7 or to LCD segment output while sharing
pins with SEGxx/P7x pins
P7LS = "0": select low nibble of Port 7 as normal P70~P73
P7LS = "1": select LCD segment output as SEG 16~SEG 19 output
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
23
EM78P468B
8-Bit Microcontroller
6.2.3 IOC60, P6CR (Port 6 I/O Control Register)
(Address: 06h, Bit 0 of R5 = “0”)
Bit 7
IOC67
R/W
Bit 6
IOC66
R/W
Bit 5
IOC65
R/W
Bit 4
IOC64
R/W
Bit 3
IOC63
R/W
Bit 2
IOC62
R/W
Bit 1
IOC61
R/W
Bit 0
IOC60
R/W
Bit 7 (IOC67) ~ Bit 0 (IOC60): Port 6 I/O direction control register
IOC6x ="0": set the relative Port 6x I/O pins as output
IOC6x ="1": set the relative Port 6x I/O pin into high impedance (input pin)
6.2.4 IOC70, P7CR (Port 7 I/O Control Register)
(Address: 07h, Bit 0 of R5 = “0”)
Bit 7
IOC77
R/W
Bit 6
IOC76
R/W
Bit 5
IOC75
R/W
Bit 4
IOC74
R/W
Bit 3
IOC73
R/W
Bit 2
IOC72
R/W
Bit 1
IOC71
R/W
Bit 0
IOC70
R/W
Bit 7 (IOC77) ~ Bit 0 (IOC70): Port 7 I/O direction control register
IOC7x = "0": set the relative Port 7x I/O pins as output
IOC7x = "1": set the relative Port 7x I/O pin into high impedance (input pin)
6.2.5 IOC80, P8CR (Port 8 I/O Control Register)
(Address: 08h, Bit 0 of R5 = “0”)
Bit 7
IOC87
R/W
Bit 6
IOC86
R/W
Bit 5
IOC85
R/W
Bit 4
IOC84
R/W
Bit 3
IOC83
R/W
Bit 2
IOC82
R/W
Bit 1
IOC81
R/W
Bit 0
IOC80
R/W
Bit 7 (IOC 87) ~ Bit 0 (IOC 80): Port 8 I/O direction control register
IOC8x = "0": set the relative Port 8x I/O pins as output
IOC8x = "1": set the relative Port 8x I/O pin into high impedance (input pin)
6.2.6 IOC90, RAM_ADDR (128 Bytes RAM Address)
(Address: 09h, Bit 0 of R5 = “0”)
Bit 7
Bit 6
RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
R/W R/W R/W R/W R/W R/W R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
Bit 7: Not used, fixed at “0”
Bits 6~0: 128 bytes RAM address
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EM78P468B
8-Bit Microcontroller
6.2.7 IOCA0, RAM_DB (128 Bytes RAM Data Buffer)
(Address: 0Ah, Bit 0 of R5 = “0”)
Bit 7 Bit 6 Bit 5
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7~0: 128 bytes RAM data transfer register
6.2.8 IOCB0, CNT1PR (Counter 1 Preset Register)
(Address: 0Bh, Bit 0 of R5 = “0”)
Bit 7
Bit 7
R/W
Bit 6
Bit 6
R/W
Bit 5
Bit 5
R/W
Bit 4
Bit 4
R/W
Bit 3
Bit 3
R/W
Bit 2
Bit 2
R/W
Bit 1
Bit 1
R/W
Bit 0
Bit 0
R/W
Bit 7 ~ Bit 0: These are Counter 1 buffers which user can read and write. Counter 1 is
an 8-bit down-count timer with 8-bit prescaler used to preset the counter and read the
preset value. The prescaler is set by the IOC91 register. After an interrupt, it will auto
reload the preset value.
6.2.9 IOCC0, CNT2PR (Counter 2 Preset Register)
(Address: 0Ch, Bit 0 of R5 = “0”)
Bit 7
Bit 7
R/W
Bit 6
Bit 6
R/W
Bit 5
Bit 5
R/W
Bit 4
Bit 4
R/W
Bit 3
Bit 3
R/W
Bit 2
Bit 2
R/W
Bit 1
Bit 1
R/W
Bit 0
Bit 0
R/W
Bit 7 ~ Bit 0: These are Counter 2 buffers which user can read and write. Counter 2 is
an 8-bit down-count timer with 8-bit prescaler used to preset the counter and read the
preset value. The prescaler is set by the IOC91 register. After an interrupt, it will
reload the preset value.
When IR output is enabled, this control register can obtain carrier frequency output.
If the Counter 2 clock source is equal to FT ,
then
FT
Carrier frequency (Fcarrier) =
2 * (preset _ value+1) * prescaler
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
25
EM78P468B
8-Bit Microcontroller
6.2.10 IOCD0, HPWTPR (High-Pulse Width Timer Preset Register)
(Address: 0Dh, Bit 0 of R5 = “0”)
Bit 7
Bit 7
R/W
Bit 6
Bit 6
R/W
Bit 5
Bit 5
R/W
Bit 4
Bit 4
R/W
Bit 3
Bit 3
R/W
Bit 2
Bit 2
R/W
Bit 1
Bit 1
R/W
Bit 0
Bit 0
R/W
Bit 7 ~ Bit 0: These are high-pulse width timer buffers which user can read and write.
High-pulse width timer preset register is an eight-bit down-counter with 8-bit prescaler
used as IOCD0 to preset the counter and read the preset value. The prescaler is set by
the IOCA1 register. After an interrupt, it will reload the preset value.
For PWM or IR application, this control register is set as high pulse width.
If the high-pulse width timer clock source is FT ,
then
prescaler * (preset _ value+1)
High pulse time =
FT
6.2.11 IOCE0, LPWTPR (Low-Pulse Width Timer Preset Register)
(Address: 0Eh, Bit 0 of R5 = “0”)
Bit 7
Bit 7
R/W
Bit 6
Bit 6
R/W
Bit 5
Bit 5
R/W
Bit 4
Bit 4
R/W
Bit 3
Bit 3
R/W
Bit 2
Bit 2
R/W
Bit 1
Bit 1
R/W
Bit 0
Bit 0
R/W
Bit 7 ~ Bit 0: All are low-pulse width timer buffer that user can read and write.
Low-pulse width timer preset is an eight-bit down-counter with 8-bit prescaler that is
used as IOCE0 to preset the counter and read preset value. The prescaler is set by
IOCA1 register. After an interrupt, it will reload the preset value.
For PWM or IR application, this control register is set as low pulse width.
If the low-pulse width timer clock source is FT ,
then
5
prescaler * (preset _ value+1)
FT
Low pulse time =
6.2.12 IOCF0, IMR (Interrupt Mask Register)
(Address: 0Fh, Bit 0 of R5 = “0”)
Bit 7
ICIE
R/W
Bit 6
LPWTE
R/W
Bit 5
HPWTE
R/W
Bit 4
CNT2E
R/W
Bit 3
CNT1E
R/W
Bit 2
INT1E
R/W
Bit 1
INT0E
R/W
Bit 0
TCIE
R/W
Bit 7 ~ Bit 0: interrupt enable bit. Enable the respective interrupt source.
0: disable interrupt
1: enable interrupt
The IOCF0 register is readable and writable.
26
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Registers of IOC Page 1 (IOC61 ~ IOCE1, Bit 0 of R5 = “1”)
6.2.13 IOC61, WUCR (Wake-up and Sink Current of P57/IROUT
Control Register)
(Address: 06h, Bit 0 of R5 = “1”)
Bit 7
IROCS
R/W
Bit 6
Bit 5
Bit 4
Bit 3
/WUE8H /WUE8L /WUE6H /WUE6L
R/W R/W R/W R/W
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
Bit 7: IROCS: IROUT/Port 57 output sink current set
P57/IROUT Sink Current
IROCS
VDD=5V
VDD=3V
6 mA
0
1
10 mA
20 mA
12 mA
Bits 6, 5, 4: Not used
Bit 3 (/WUE8H): 0/1 enable/disable P84~P87 pin change wake-up function
Bit 2 (/WUE8L): 0/1 enable/disable P80~P83 pin change wake-up function
Bit 1 (/WUE6H): 0/1 enable/disable P64~P67 pin change wake-up function
Bit 0 (/WUE6L): 0/1 enable/disable P60~P63 pin change wake-up function
* Port 6 and Port 8 must not be set as input floating when wake-up function is
enabled. “Enable” is the initial state of wake-up function.
6.2.14 IOC71, TCCCR (TCC Control Register)
(Address: 07h, Bit 0 of R5 = “1”)
Bit 7
INT_EDGE
R/W
Bit 6
INT
F
Bit 5
TS
Bit 4
TE
Bit 3
PSRE
R/W
Bit 2
TCCP2
R/W
Bit 1
TCCP1
R/W
Bit 0
TCCP0
R/W
R/W
R/W
Bit 7 (INT_EDGE):
INT_EDGE = "0": Interrupt on the rising edge of P54/INT0 pin
INT_EDGE = "1": Interrupt on the falling edge of P54/INT0 pin
Bit 6 (INT): INT enable flag, this bit is read only
INT = "0": interrupt masked by DISI or hardware interrupt
INT = "1": interrupt enabled by ENI/RETI instructions
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
27
EM78P468B
8-Bit Microcontroller
Bit 5 (TS): TCC signal source
TS = "0": internal instruction cycle clock
TS = "1": transition on TCC pin, TCC period > internal instruction clock period
Bit 4 (TE): TCC signal edge
TE = "0": incremented by TCC pin rising edge
TE = "1": incremented by TCC pin falling edge
Bits 3~0 (PSRE, TCCP2 ~ TCCP0): TCC prescaler bits
PSRE
TCCP2
TCCP1
TCCP0
TCC Rate
1:1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.2.15 IOC81, WDTCR (WDT Control Register)
(Address: 08h, Bit 0 of R5 = “1”)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WDTE
R/W
Bit 2
WDTP2
R/W
Bit 1
Bit 0
WDTP0
R/W
WDTP1
R/W
Bits 7 ~ 4: Not used
Bit 3 (WDTE): Watchdog timer enable. This control bit is used to enable the Watchdog
timer,
WDTE = "0": Disable WDT function
WDTE = "1": Enable WDT function
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Product Specification (V1.3) 03.25.2016
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EM78P468B
8-Bit Microcontroller
Bits 2 ~ 0 (WDTP2 ~ WDTP0): Watchdog Timer prescaler bits. The WDT clock source
is sub-oscillation frequency.
WDTP2
WDTP1
WDTP0
WDT Rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
6.2.16 IOC91, CNT12CR (Counters 1, 2 Control Register)
(Address: 09h, Bit 0 of R5 = “1”)
Bit 7
CNT2S
R/W
Bit 6
CNT2P2 CNT2P1 CNT2P0
R/W R/W R/W
Bit 5
Bit 4
Bit 3
CNT1S
R/W
Bit 2
CNT1P2 CNT1P1 CNT1P0
R/W R/W R/W
Bit 1
Bit 0
Bit 7 (CNT2S): Counter 2 clock source select
“0”: Fs (Fs: sub-oscillator clock)
“1”: Fm (Fm: main-oscillator clock)
Bits 6~4 (CNT2P2 ~ CNT2P0): Counter 2 prescaler select bits
CNT2P2
CNT2P1
CNT1P0
Counter 2 Scale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3 (CNT1S): Counter 1 Clock Source Select
“0”: Fs (Fs: sub-oscillator clock)
“1”: Fm (Fm: main-oscillator clock)
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
29
EM78P468B
8-Bit Microcontroller
Bits 2~0 (CNT1P2 ~ CNT1P20): Counter 1 prescaler select bits
CNT1P2
CNT1P1
CNT1P0
Counter 1 Scale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.2.17 IOCA1, HLPWTCR (High/Low Pulse Width Timer Control
Register)
(Addresss: 0Ah, Bit 0 of R5 = “1”)
Bit 7
LPWTS
R/W
Bit 6
LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0
R/W R/W R/W R/W R/W R/W R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7 (LPWTS): Low-Pulse Width Timer Clock Source Select
“0”: Fs (Fs: sub-oscillator clock)
“1”: Fm (Fm: main-oscillator clock)
Bits 6~4 (LPWTP2~ LPWTP0): Low-Pulse Width Timer Prescaler Select bits
LPWTP2
LPWTP1
LPWTP0
Low-pulse Width Timer Scale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3 (HPWTS): High-Pulse Width Timer Clock Source Select
“0”: Fs (Fs: sub-oscillator clock)
“1”: Fm (Fm: main-oscillator clock)
30
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EM78P468B
8-Bit Microcontroller
Bits 2~0 (HPWTP2~ HPWTP0): High-Pulse Width Timer Prescaler Select bits
HPWTP2
HPWTP1
HPWTP0
High-pulse Width Timer Scale
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
6.2.18 IOCB1, P6PH (Port 6 Pull-high Control Register)
Address: 0Bh, Bit 0 of R5 = “1”)
Bit 7
PH67
R/W
Bit 6
PH66
R/W
Bit 5
PH65
R/W
Bit 4
PH64
R/W
Bit 3
PH63
R/W
Bit 2
PH62
R/W
Bit 1
PH61
R/W
Bit 0
PH60
R/W
Bit 7 ~ Bit 0 (PH67 ~ PH60): These are the enable bits of Port 6 pull high function.
PH6x = "0": disable P6x pin internal pull-high resistor function
PH6x = "1": enable P6x pin internal pull-high resistor function
6.2.19 IOCC1, P6OD (Port 6 Open Drain Control Register)
(Address: 0Ch, Bit 0 of R5 = “1”)
Bit 7
OP67
R/W
Bit 6
OP66
R/W
Bit 5
OP65
R/W
Bit 4
OP64
R/W
Bit 3
OP63
R/W
Bit 2
OP62
R/W
Bit 1
OP61
R/W
Bit 0
OP60
R/W
Bit 7 ~ Bit 0: These are the enable bits of Port 6 open drain function.
OD6x = "0": disable pin P6x open drain function
OD6x = "1": enable pin P6x open drain function
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
31
EM78P468B
8-Bit Microcontroller
6.2.20 IOCD1, P8PH (Port 8 Pull High Control Register)
(Address: 0Dh, Bit 0 of R5 = “1”)
Bit 7
PH87
R/W
Bit 6
PH86
R/W
Bit 5
PH85
R/W
Bit 4
PH84
R/W
Bit 3
PH83
R/W
Bit 2
PH82
R/W
Bit 1
PH81
R/W
Bit 0
PH80
R/W
Bit 7 ~ Bit 0: These are the enable bits of Port 8 pull-high function.
PH8x = "0": disable P8x pin internal pull-high resistor function
PH8x = "1": enable P8x pin internal pull-high resistor function
6.2.21 IOCE1, P6PL (Port 6 Pull Low Control Register)
(Address: 0Eh, Bit 0 of R5 = “1”)
Bit 7
PL67
R/W
Bit 6
PL66
R/W
Bit 5
PL65
R/W
Bit 4
PL64
R/W
Bit 3
PL63
R/W
Bit 2
PL62
R/W
Bit 1
PL61
R/W
Bit 0
PL60
R/W
Bit 7 ~ Bit 0: These are the enable bits of Port 6 pull low function.
PL6x = "0": disable P6x pin internal pull-low resistor function
PL6x = "1": enable P6x pin internal pull-low resistor function
6.3 TCC and WDT Prescaler
Two 8-bit counters are available as prescalers for the TCC (Time Clock Counter) and
WDT (Watchdog Timer). The TCCP2~TCCP0 bits of the IOC71 register are used to
determine the ratio of the TCC prescaler. Likewise, the WDTP2~WDTP0 bits of the
IOC81 register are used to determine the WDT prescaler. The TCC prescaler
(TCCP2~TCCP0) is cleared by the instructions each time they are written into TCC,
while the WDT prescaler is cleared by the “WDTC” and “SLEP” instructions. Fig.7
depicts the circuit diagram of TCC and WDT.
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be selected by
internal instruction clock or external signal input (edge selectable from the TCC control
register). If the TCC signal source is from the internal instruction clock, the TCC will be
incremented by 1 at every instruction cycle (without prescaler). If the TCC signal
source is from an external clock input, the TCC will be incremented by 1 at every falling
edge or rising edge of the TCC pin.
The Watchdog Timer is free running on sub-oscillator. The WDT will keep on running
even after the oscillator driver has been turned off. During Normal mode, Green mode,
or Idle mode operation, a WDT time-out (if enabled) will cause the device to reset. The
WDT can be enabled or disabled at any time during the Normal mode and Green mode
by software programming. Refer to WDTE bit of IOC81 register. The WDT time-out
period is equal to (prescaler 256 / (Fs/2)).
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EM78P468B
8-Bit Microcontroller
Data Bus
TCC (R1)
Instruction Clock = Fosc /2
Fosc: CPU operate frequency
TCC
Pin
MUX
Prescaler
8 to 1 MUX
PSRE TCCP2~0
(IOC71) (IOC71)
TCCoverflow interrupt
TE (IOC71)
TS (IOC71)
Figure 6-4(a) Block Diagram of TCC
WDT
8 bit counter
Fs/2
WDTE (IOC81)
8 to 1 MUX
Prescaler
(Fs:Sub oscillator)
WDTP2~0
(IOC81)
WDT Time out
Figure 6-4(b) Block Diagram of WDT
WDT Setting Flowchart
START
N
Use WDT function ?
Y
Enable WDT function : set Bit 7 of
Code option Word 0 to "0"
Disable WDT function : set Bit 7 of
Code option Word 0 to "1"
WDTtime= prescaler*256/Fs
Fs: sub-oscillator frequency
Setting WDT prescaler
(IOC81 register)
Enable WDT
(Bit 3 of IOC81)
END
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
33
EM78P468B
8-Bit Microcontroller
TCC Setting Flowchart
START
TCC clock source?
From Instruction Cycle
External/ instruction cycle
From
External Input
*Set the clock source from external TCC pin
(Set Bit 4 of IOC71 to "1")
*Choose the TCC clock source from the instruction cycle
(Set Bit 4 of IOC71 to "0")
*Set P56/TCC for TCC input Pin
( Set Bit 2 of RE to "1" and set Bit 6 of IOC 50 to "1")
*Choose the TCC prescaler
(Set by Bit 0 to Bit 3 of IOC71)
*Choose TCC pin operation edge
(Set by Bit 4 of IOC71)
*Choose TCC prescaler
(Set by Bit 0 to Bit 3 of IOC71)
* Enable TCC interrupt Mask
(Set Bit 0 of IOCF0 to "1")
*Clear TCC interrupt Flag
(Set Bit 0 of RF to "0")
Enable TCC to start count
(Use ENI instruction)
END
34
Product Specification (V1.3) 03.25.2016
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EM78P468B
8-Bit Microcontroller
6.4 I/O Ports
The I/O registers, (Port 5, Port 6, Port 7 and Port 8), are bi-directional tri-state I/O ports.
Port 6 and Port 8 are pulled-high internally by software; Port 6 is also pulled-low internally
by software. Furthermore, Port 6 has its open-drain output also through software. Port 6
and Port 8 features an input status changed interrupt (or wake-up) function and is
pulled-high by software. Each I/O pin can be defined as "input" or "output" pin by the I/O
control register (IOC50 ~ IOC80). The I/O registers and I/O control registers are both
readable and writable. The I/O interface circuits are shown in Figure 6-5.
Note: Open-drain, pull-high, and pull down are not shown in the figure.
Figure 6-5 Circuit of I/O Port and I/O Control Register for Ports 5 ~ 8
6.5 Reset and Wake-up
A reset can be activated by
POR (Power-on Reset)
WDT timeout (if enabled)
/RESET pin goes to low
Note: The reset circuit is always enabled. It will reset the CPU at 1.9V.
Once a reset occurs, the following functions are performed
The oscillator is running, or will be started
The program counter (R2/PC) is set to all "0"
All I/O port pins are configured as input mode (high-impedance state)
The TCC/Watchdog timer and prescaler are cleared
When power is on, the Bits 5 and 6 of R3 and the upper two bits of R4 are
cleared.
Bits of the IOC71 register are set to all "1" except for Bit 6 (INT flag)
For other registers, see Table 2
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
35
EM78P468B
8-Bit Microcontroller
Table 2 Summary of Registers Initialized Values
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
IOC57 IOC56 IOC55 IOC54
P8HS
P8LS
P7HS
P7LS
Power-on
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
IOC50
0x05
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(P5CR)
P
P
P
P
P
P
P
P
IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOC60
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x06
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(P6CR)
P
P
P
P
P
P
P
P
IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOC70
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(P7CR)
P
P
P
P
P
P
P
P
IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81 IOC80
1
1
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IOC80
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(P8CR)
P
P
P
P
P
P
P
P
RAM_A0
RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1
X
0
0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOC90
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(RAM_ADDR)
P
P
P
P
P
P
P
P
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
IOCA0
/RESET & WDT
Wake-Up from
Pin Change
Bit Name
(RAM_DB)
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
Power-on
IOCB0
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(CNT1PR)
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
Power-on
IOCC0
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(CNT2PR)
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
Power-on
IOCD0
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(HPWTPR)
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
Power-on
IOCE0
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(LPWTPR)
P
P
P
P
P
P
P
P
ICIE LPWTE HPWTE CNT2E CNT1E INT1E
0
0
INT0E
0
0
TCIE
0
0
Power-on
0
0
0
0
0
0
0
0
0
0
IOCF0
(IMR)
/RESET & WDT
Wake-up from
Pin Change
Bit Name
P
P
P
P
P
P
P
P
IROCS
X
U
U
X
U
U
X
U
U
/WUE8H /WUE8L /WUE6H /WUE6L
Power-on
0
0
0
0
0
0
0
0
0
0
IOC61
/RESET & WDT
Wake-up from
Pin Change
(WUCR)
P
U
U
U
P
P
P
P
36
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT_EDGE
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
INT
0
0
TS
1
1
TE
1
1
PSRE TCCP2 TCCP1 TCCP0
1
1
1
1
1
1
1
1
1
1
IOC71
0x07
(TCCCR)
P
P
P
P
P
P
P
P
X
U
U
X
U
U
X
U
U
X
U
U
WDTE WDTP2 WDTP1 WDTP0
Power-on
0
0
1
1
1
1
1
1
IOC81
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x00
0x01
0x02
0x03
0x04
/RESET &WDT
Wake-up from
Pin Change
Bit Name
(WDTCR)
U
U
U
U
P
P
P
P
CNT2S CNT2P2 CNT2P1 CNT2P0 CNT1S CNT1P2 CNT1P1 CNT1P0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOC91
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(CNT12CR)
P
P
P
P
P
P
P
P
HPWTP2 HPWTP1 HPWTP0
LPWTS LPWTP2 LPWTP1 LPWTP0 HPWTS
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCA1
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(HLPWTCR)
P
P
P
P
P
P
P
P
PH67
PH66
PH65
PH64
PH63
PH62
PH61
PH60
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCB1
(P6PH)
/RESET & WDT
Wake-up from
Pin Change
Bit Name
P
P
P
P
P
P
P
P
OP67
OP66
OP65
OP64
OP63
OP62
OP61
OP60
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCC1
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(P6OD)
P
P
P
P
P
P
P
P
PH87
PH86
PH85
PH84
PH83
PH82
PH81
PH80
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCD1
(P8PH)
/RESET & WDT
Wake-up from
Pin Change
Bit Name
P
P
P
P
P
P
P
P
PL67
PL66
PL65
PL64
PL63
PL62
PL61
PL60
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IOCE1
(P6PL)
/RESET & WDT
Wake-up from
Pin Change
Bit Name
P
P
P
P
P
P
P
P
Bit 7
U
Bit 6
U
Bit 5
U
Bit 4
U
Bit 3
U
Bit 2
U
Bit 1
U
Bit 0
U
Power-on
R0
/RESET & WDT
Wake-up from
Pin Change
Bit Name
P
P
P
P
P
P
P
P
(IAR)
P
P
P
P
P
P
P
P
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(TCC)
P
P
P
P
P
P
P
P
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R2
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(PC)
Jump to Address 0x0018 or continue to execute next instruction.
X
U
U
PS1
0
0
PS0
0
0
T
1
t
P
1
t
Z
U
P
DC
U
P
C
U
P
Power-on
R3
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(SR)
U
P
P
t
t
P
P
P
RBS1
RBS0
RSR5
RSR4
RSR3
RSR2
RSR1
RSR0
Power-on
0
0
0
0
U
P
U
P
U
P
U
P
U
P
U
P
R4
/RESET & WDT
Wake-up from
Pin Change
(RSR)
P
P
P
P
P
P
P
P
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
37
EM78P468B
8-Bit Microcontroller
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOCPAGE
Bit Name
Power-on
/RESET & WDT
Wake-up from
Pin Change
Bit Name
R57
1
1
R56
1
1
R55
1
1
R54
1
1
X
U
U
X
U
U
X
U
U
0
0
R5
0x05
(Port 5)
P
P
P
P
U
U
U
P
R67
1
R66
1
R65
1
R64
1
R63
1
R62
1
R61
1
R60
1
Power-on
R6
0x06
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
/RESET & WDT
Wake-up from
Pin Change
Bit Name
1
1
1
1
1
1
1
1
(Port 6)
P
P
P
P
P
P
P
P
R77
1
1
R76
1
1
R75
1
1
R74
1
1
R73
1
1
R62
1
1
R71
1
1
R70
1
1
Power-on
R7
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(Port 7)
P
P
P
P
P
P
P
P
R87
1
1
R86
1
1
R85
1
1
R84
1
1
R83
1
1
R82
1
1
R81
1
1
R80
1
1
Power-on
R8
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(Port 8)
P
P
P
P
P
P
P
P
LCDTYPE
BS
1
1
DS1
1
1
DS0
0
0
LCDEN
X
U
U
LCDF1 LCDF0
Power-on
0
0
0
0
0
0
0
0
R9
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(LCDCR)
P
P
P
P
U
P
P
P
X
0
0
X
0
0
X
0
0
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
Power-on
0
0
0
0
0
0
0
0
0
0
RA
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(LCD_ADDR)
P
P
P
P
P
P
P
P
X
U
U
X
U
U
X
U
U
X
U
U
LCD_D3 LCD_D2 LCD_D1 LCD_D0
Power-on
U
P
U
P
U
P
U
P
RB
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(LCD_DB)
U
U
U
U
P
P
P
P
LPWTEN HPWTEN CNT2EN CNT1EN
X
0
0
X
1
1
X
0
0
X
0
0
Power-on
0
0
0
0
0
0
0
0
RC
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(CNTER)
P
P
0
P
P
P
P
P
X
U
U
CLK2
0
0
CLK1
0
0
CLK0
0
0
IDLE
1
1
BF1
0
0
BF0
0
0
CPUS
*1
*1
Power-on
RD
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(SBPCR)
U
P
P
P
P
P
P
P
IRE
0
0
HF
0
0
LGP
0
0
X
U
U
IROUTE TCCE
EINT1 EINT0
0
0
Power-on
0
0
0
0
0
0
RE
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(IRCR)
P
P
P
U
P
P
P
P
ICIF
0
0
LPWTF HPWTF CNT2F CNT1F INT1F
INT0F
0
0
TCIF
0
0
Power-on
0
0
0
0
0
0
0
0
0
0
RF
/RESET & WDT
Wake-up from
Pin Change
Bit Name
(ISR)
N
P
P
P
P
P
P
P
Bit 7
U
P
Bit 6
U
P
Bit 5
U
P
Bit 4
U
P
Bit 3
U
P
Bit 2
U
P
Bit 1
U
P
Bit 0
U
P
Power-on
0x10
~
0x3F
/RESET & WDT
Wake-up from
Pin Change
R10~R3F
P
P
P
P
P
P
P
P
Note: This bit is equal to the Code Option HLFS bit data
Legend: “” = not used
“” = Not defined
“P” = previous value before reset
“t” = check R3 register explanation
“u” = unknown or don’t care “N” = Monitors interrupt operation status
38
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
The controller can be awakened from sleep mode and idle mode. The wake-up signals
are listed as follows:
Wake-up Signal
Sleep Mode
Idle Mode
Green Mode Normal Mode
TCC time out
IOCF0 Bit 0=1
Interrupt
Interrupt
Interrupt
Interrupt
Wake-up
Wake-up
INT0 pin
+ interrupt
+ interrupt
IOCF0 Bit 1=1
+ next instruction
+ next instruction
Wake-up
Wake-up
INT1 pin
+ interrupt
+ interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
IOCF0 Bit 2=1
+ next instruction
+ next instruction
Wake-up
Counter 1
+ interrupt
IOCF0 Bit 3=1
+ next instruction
Wake-up
Counter 2
+ interrupt
IOCF0 Bit 4=1
+ next instruction
Wake-up
High-pulse timer
IOCF0 Bit 5=1
+ interrupt
+ next instruction
Wake-up
Low-pulse timer
IOCF0 Bit 6=1
+ interrupt
+ next instruction
Port 6, Port 8
Wake-up
Wake-up
(input status
change wake-up)
+ next instruction
+ next instruction
Bit 7 of IOCF0 = “0”
Port 6, Port 8
Wake-up
Wake-up
(input status
+ interrupt
+ interrupt
change wake-up)
+ next instruction
+ next instruction
Bit 7 of IOCF0 = “1”
WDT time out
RESET
RESET
RESET
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
39
EM78P468B
8-Bit Microcontroller
6.6 Oscillator
6.6.1 Oscillator Modes
The EM78P468B can operate in three different oscillator modes:
a.) Main oscillator (R-OSCI, OSCO), such as RC oscillator with external resistor and
Internal capacitor mode (ERIC)
b.) Crystal oscillator mode
c.) PLL operation mode (R-OSCI connected to 0.01F capacitor to Ground). User can
select which mode by programming FMMD1 and FMMD0 in the Code Options
Register. The sub-oscillator can be operated in Crystal mode and ERIC mode.
Table 3 below shows how these three modes are defined.
Table 3 Oscillator Modes as defined by FSMD, FMMD1, FMMD0
FSMD
FMMD1
FMMD0
Main Clock
RC type (ERIC)
Crystal type
PLL type
Sub-clock
RC type (ERIC)
RC type (ERIC)
RC type (ERIC)
Crystal type
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
1
RC type (ERIC)
Crystal type
PLL type
Crystal type
Crystal type
Table 4 Summary of Maximum Operating Speeds
Conditions
VDD
2.3
Fxt Max. (MHz)
4
8
Two clocks
3.0
5.0
10
6.6.2 Phase Lock Loop (PLL Mode)
When operate on PLL mode, the High frequency determined by sub-oscillator. We can
choose RD register to change high oscillator frequency. The relation between high
frequency (Fm) and sub-oscillator is shown on the table below:
R-OSCI
0.01μF
EM78P468B
Figure 6-6 PLL Mode Circuit
40
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Bits 6~4 (CLK2~0) of RD: Main clock selection bits for PLL mode (code option select)
CLK2
CLK1
CLK0
Main Clock
Example Fs=32.768kHz
0
0
0
0
1
0
0
1
1
0
1
0
1
Fs 130
Fs 65
Fs 65/2
Fs 65/4
Fs 244
4.26 MHz
2.13 MHz
1.065 MHz
532kHz
8 MHz
6.6.3 Crystal Oscillator/Ceramic Resonators (Crystal)
This LSI can be driven by an external clock signal through the R-OSCI pin as shown in
Fig. 6-7 below. In most applications, the R-OSCI pin and the OSCO pin can be
connected with a crystal or ceramic resonator to generate oscillation. Fig. 6-8 depicts
such circuit. Table 5 provides the recommended values of C1 and C2. Since each
resonator has its own attribute, user should refer to its specification for appropriate
values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or
low frequency mode.
R-OSCI
EM78P468B
OSCO
Figure 6-7 External Clock Input Circuit
Figure 6-8 Circuit for Crystal/Resonator
Table 5 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators
Oscillator Source
Oscillator Type
Frequency
455kHz
C1 (pF)
100~150
20~40
10~30
20~40
15~30
15
C2 (pF)
100~150
20~40
10~30
20~150
15~30
15
Ceramic Resonators
2.0 MHz
4.0 MHz
455kHz
Main oscillator
1.0 MHz
2.0 MHz
4.0 MHz
32.768kHz
Crystal Oscillator
Crystal Oscillator
15
15
Sub-oscillator
25
25
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
41
EM78P468B
8-Bit Microcontroller
6.6.4 RC Oscillator Mode with Internal Capacitor
If both precision and cost are taken into consideration, this LSI also offers a special
oscillation mode, which has an on-chip internal capacitor and an external resistor
connected to VDD. The internal capacitor functions as temperature compensator. In
order to obtain more accurate frequency, a precise resistor is recommended.
VDD
Rext
R-OSCI or Xin
EM78P468B
Figure 6-9 Circuit for Internal C Oscillator Mode
Table 6 RC Oscillator Frequencies
Pin
Rext
Average Fosc 5V, 25 C
Average Fosc 3V, 25 C
51k
2.2221 MHz
1.1345 MHz
381.36kHz
32.768kHz
2.1972 MHz
1.1203 MHz
374.77kHz
32.768kHz
R-OSCI
Xin
100k
300k
2.2M
Note: Measured from QFP packages with frequency drift of about 30%.
Values are provided for design reference only.
6.7 Power-on Considerations
Any microcontroller (as with this LSI) is not warranted to start operating properly before
the power supply stabilizes in a steady state. This LSI has an on-chip Power-on Reset
(POR) with detection level range as shown on the table below. The circuitry eliminates
the extra external reset circuit but will work well only if the VDD rises quickly enough
(50ms or less). However, under critical applications, extra devices are still required to
assist in solving power-on problems.
Power-on voltage detector provided
IC
Voltage Range
EM78P468B
1.7V to 1.9V
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(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
6.7.1 External Power-on Reset Circuit
This circuit implements an external RC to produce a reset pulse (see Figure 6-10). The
pulse width (time constant) should be kept long enough to allow VDD to reach minimum
operation voltage. This circuit is used when the power supply rise time is slow.
Because the current leakage from the /RESET pin is 5 A, it is recommended that R
should not be greater than 40K. In this way, the voltage at Pin /RESET is held below
0.2V. The diode (D) acts as a short circuit at power-down. The capacitor, C, is
discharged rapidly and fully. Rin, the current-limited resistor, prevents high current
discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
VDD
/RESET
R
C
D
EM78P468B
Rin
Figure 6-10 External Power-on Reset Circuit
6.7.2 Residue-Voltage Protection
When battery is replaced, device power (VDD) is disconnected but residue-voltage
remains. The residue-voltage may trips below minimum VDD, but above zero. This
condition may cause poor power on reset. Figure 6-11 and Figure 6-12 show how to
build a residue-voltage protection circuit.
VDD
VDD
33K
EM78P468B
Q1
10K
/RESET
100
K
1N4684
Figure 6-11 Residue Voltage Protection Circuit 1
VDD
VDD
EM78P468B
/RESET
R1
R2
Q1
R3
Figure 6-12 Residue Voltage Protection Circuit 2
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
43
EM78P468B
8-Bit Microcontroller
6.8 Interrupt
This LSI has eight interrupt sources as listed below:
TCC overflow interrupt
External interrupt P54/INT0 pin
External interrupt P55/INT1 pin
Counter 1 underflow interrupt
Counter 2 underflow interrupt
High-pulse width timer underflow interrupt
Low-pulse width timer underflow interrupt
Port 6, Port 8 input status change wake-up
This IC has internal interrupts which are falling edge triggered or as follows:
TCC timer overflow interrupt
Four 8-bit down counter/timer underflow interrupt
If these interrupt sources change signal from high to low, the RF register will generate a
“1” flag to the corresponding register if the IOCF0 register is enabled.
RF is the interrupt status register. It records the interrupt request in flag bit. IOCF0 is
the interrupt mask register. Global interrupt is enabled by ENI instruction and disabled
by DISI instruction. When one of the interrupts (when enabled) is generated, it will
cause the next instruction to be fetch from Address 0003H~0018H according to
interrupt source.
With this LSI, each individual interrupt source has its own interrupt vector as depicted in
Table 3. Before the interrupt subroutine is executed, the contents of the ACC and the
R3 register are initially saved by the hardware. After the interrupt service routine is
completed, the ACC and R3 are restored. The existing interrupt service routine does
not allow other interrupt service routine to be executed. Hence, if other interrupts occur
while an existing interrupt service routine is being executed, the hardware will save the
later interrupts. Only after the existing interrupt service routine is completed that the
next interrupt service routine is executed.
Interrupt
Interrupt Source
ENI / DISI
ACC
R3
STACKACC
STACKR3
Occurs
RETI
Fig. 6-13 Interrupt Back-up Diagram
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Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Table 3 Interrupt Vector
Interrupt Vector
0003H
Interrupt Status
TCC overflow interrupt.
0006H
External interrupt P5.4/INT0 pin
External interrupt P5.5/INT1 pin
Counter 1 underflow interrupt
0009H
000CH
000FH
Counter 2 underflow interrupt
0012H
High-pulse width timer underflow interrupt
Low-pulse width timer underflow interrupt
0015H
0018H
Port 6, Port 8 input status change wake up
6.9 LCD Driver
This LSI can drive an LCD of up to 32 segments and 4 commons that can drive a total
of 432 dots. The LCD block is made up of an LCD driver, display RAM, segment
output pins, common output pins, and LCD operating power supply pins. This circuit
works on normal mode, green mode and idle mode. The LCD duty; bias; the number of
segment; the number of common and frame frequency are determined by the LCD
controller register.
The basic structure contains a timing control that uses a subsystem clock to generate
the proper timing for different duty and display accesses. The R9 register is a
command register for the LCD driver which includes LCD enable/disable, bias (1/2 and
1/3), duty (1/2, 1/3, 1/4), and LCD frame frequency control. The register RA is an LCD
contrast and LCD RAM address control register. The register RB is an LCD RAM data
buffer. LCD booster circuit can change the operation frequency to improve VLCD2 and
VLCD3 drive capability. The control register is described as follows.
6.9.1 R9/LCDCR (LCD Control Register)
Bit 7
BS
Bit 6
DS1
R/W
Bit 5
DS0
R/W
Bit 4
LCDEN
R/W
Bit 3
Bit 2
LCDTYPE LCDF1
R/W R/W
Bit 1
Bit 0
LCDF0
R/W
R/W
-
Bit 7 (BS): LCD bias select bit, 0/1=> (1/2 bias) / (1/3 bias)
Bits 6 ~ 5 (DS1 ~ DS0): LCD duty select
DS1
DS0
LCD Duty
1/2 duty
1/3 duty
1/4 duty
0
0
1
0
1
Bit 4 (LCDEN): LCD enable bit
"0": disable the LCD circuit
"1": enable the LCD circuit
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(This specification is subject to change without prior notice)
45
EM78P468B
8-Bit Microcontroller
When the LCD function is disabled, all common/segment output is set to ground (GND)
level
Bit 3: Not used
Bit 2 (LCDTYPE): LCD drive waveform type select bit
LCDTYPE = "0": “A” type waveform
LCDTYPE = "1": “B” type waveform
Bits 1 ~ 0 (LCDF1 ~ LCDF0): LCD frame frequency control bits
LCD Frame Frequency (e.g. Fs=32.768kHz)
LCDF1
LCDF0
1/2 Duty
1/3 Duty
1/4 Duty
0
0
1
1
0
1
0
1
Fs/(2562)=64.0
Fs/(2802)=58.5
Fs/(3042)=53.9
Fs/(2322)=70.6
Fs/(1723)=63.5
Fs/(1883)=58.0
Fs/(2043)=53.5
Fs/(1563)=70.0
Fs/(1284)=64.0
Fs/(1404)=58.5
Fs/(1524)=53.9
Fs/(1164)=70.6
Note: Fs: sub-oscillator frequency
6.9.2 RA/LCD_ADDR (LCD Address)
Bit 7
Bit 6
Bit 5
Bit 4
LCD_A4
R/W
Bit 3
LCD_A3
R/W
Bit 2
LCD_A2
R/W
Bit 1
Bit 0
0
-
0
-
0
-
LCD_A1 LCD_A0
R/W
R/W
Bits 7 ~ 5: Not used, fixed to “0”
Bits 4 ~ 0 (LCDA4 ~ LCDA0): LCD RAM address
RB (LCD Data Buffer)
RA
Segment
Bit 3
Bit 2
Bit 1
Bit 0
(LCD Address)
Bits 7 ~4
(LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
00H
01H
SEG0
SEG1
SEG2
|
02H
|
|
1DH
1EH
SEG29
SEG30
SEG31
X
1FH
Common
COM3
COM2
COM1
COM0
6.9.3 RB/LCD_DB (LCD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD_D3 LCD_D2 LCD_D1 LCD_D0
R/W R/W R/W R/W
-
-
-
-
Bits 7 ~ 4: Not used
Bits 3 ~ 0 (LCD_D3 ~ LCD_D0): LCD RAM data transfer registers
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Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
6.9.4 RD/SBPCR (System, Booster and PLL Control Registers)
Bit 7
Bit 6
CLK2
R/W
Bit 5
CLK1
R/W
Bit 4
CLK0
R/W
Bit 3
IDLE
R/W
Bit 2
BF1
R/W
Bit 1
BF0
R/W
Bit 0
CPUS
R/W
Bits 2 ~ 1 (BF1 ~ 0): LCD booster frequency select bits
BF1
BF0
Booster Frequency
0
0
1
1
0
1
0
1
Fs
Fs/4
Fs/8
Fs/16
The initial setting flowchart for LCD function
IC RESET occur
*Set Port 7 snd Port 8 for general I/O or LCD segment (IOC50)
*it must be set to output port w hen the pin of port 7 and the pin of port 8 for LCD
segemnt (IOC70 and IOC80)
Set LCD Type, duty, bias, LCD frame frequency (R9)
Set LCD Booster Frequency (RD)
Clear all LCD RAM (RA and RB)
Enable LCD function (R9)
Use LCD address and LCD data buffer to implment user's applications. (RA and RB)
END
Figure 6-14 Initial Setting Flowchart for LCD Function
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
47
EM78P468B
8-Bit Microcontroller
Boosting circuits connection for LCD voltage
VDD
VLCD2(2*VDD/3)
VA
VLCD3(1*VDD/3)
VB
GND
External circuit for 1/3 Bias
VDD
VLCD2(VDD/2)
VA
VLCD3(VDD/2)
VB
GND
External circuit for 1/2 Bias
Figure 6-15 Charge Bump Circuit Connection (Cext=0.1f)
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(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
1frame
1frame
VDD
VDD
COM0
COM1
SEG N
VLCD2,3
GND
COM0
COM1
SEG N
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
SEG N- COM0
ON
SEG N- COM0
ON
-VLCD2,3
-VDD
-VLCD2,3
-VDD
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
SEG N- COM1
OFF
SEG N- COM1
OFF
-VLCD2,3
-VDD
-VLCD2,3
-VDD
1/2 bias, 1/2 duty
1/2 bias, 1/2 duty
B type
A type
Figure 6-16 LCD Waveform for 1/2 Bias, 1/2 Duty
1frame
1frame
VDD
VDD
COM0
COM1
COM2
SEG N
VLCD2,3
GND
COM0
COM1
COM2
SEG N
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
SEG N- COM0
ON
SEG N- COM0
ON
-VLCD2,3
-VDD
-VLCD2,3
-VDD
VDD
VDD
VLCD2,3
GND
VLCD2,3
GND
SEG N- COM1
OFF
SEG N- COM1
OFF
-VLCD2,3
-VDD
-VLCD2,3
-VDD
1/2 bias, 1/3 duty
B type
1/2 bias, 1/3 duty
A type
Figure 6-17 LCD Waveform for 1/2 Bias, 1/3 Duty
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
49
EM78P468B
8-Bit Microcontroller
1frame
1frame
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
COM0
COM0
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
COM1
COM2
COM1
COM2
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
SEG N
SEG N
VDD
VDD
SEG N- COM0
ON
VLCD3
GND
SEG N- COM0
ON
VLCD3
GND
-VLCD3
-VDD
VDD
-VLCD3
-VDD
VDD
SEG N- COM1
OFF
VLCD3
GND
SEG N- COM1
OFF
VLCD3
GND
-VLCD3
-VDD
-VLCD3
-VDD
1/3 bias, 1/3 duty
B type
1/3 bias, 1/3 duty
A type
Figure 6-18 LCD Waveform for 1/3 Bias, 1/3 Duty
1frame
1frame
VDD
VDD
VLCD2
COM0
VLCD3
VLCD2
VLCD3
GND
COM0
GND
VDD
VDD
VLCD2
COM1
VLCD3
VLCD2
VLCD3
GND
COM1
COM2
GND
VDD
VDD
VLCD2
VLCD3
GND
COM2
VLCD2
VLCD3
GND
VDD
VDD
VLCD2
VLCD3
GND
VLCD2
VLCD3
GND
SEG N
SEG N
VDD
VDD
SEG N-
COM0
SEG N-
COM0
VLCD3
GND
VLCD3
GND
ON
ON
-VLCD3
-VDD
-VLCD3
-VDD
VDD
VDD
SEG N-
COM1
SEG N-
COM1
VLCD3
GND
VLCD3
GND
OFF
OFF
-VLCD3
-VDD
-VLCD3
-VDD
1/3 bias, 1/4 duty
Atype
1/3 bias, 1/4 duty
B type
Figure 6-19 LCD Waveform for 1/3 Bias, 1/4 Duty
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Product Specification (V1.3) 03.25.2016
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EM78P468B
8-Bit Microcontroller
6.10 Infrared Remote Control Application/PWM Waveform
Generation
This LSI can output infrared carrier in user-friendly or in PWM standard waveform. The IR
and PWM waveform generated functions include an 8-bit down count timer/counter,
high-pulse width timer, low-pulse width timer, and IR control register. The IR system block
diagram is shown in Fig. 6-20. The IROUT pin waveform is determined by IR control
register (RE), IOC90 (Counters 1 and 2 control register), IOCA0 (high-pulse width timer,
low-pulse width timer control register), IOCC0 (Counter 2 preset), IOCD0 (high-pulse width
timer preset register), and IOCE0 (low-pulse width timer preset register). Details on
Fcarrier, high-pulse time, and low pulse time are explained as follows:
If Counter 2 clock source is FT (this clock source can be set by IOC91), then
FT
Fcarrier
2(1 decimal of Counter 2 presetvalue (IOCC0)) prescaler
If the high-pulse width timer clock source is FT (this clock source can be set by IOCA1), then
prescaler (1 decimal of high pulse width timer value (IOCD0))
Thigh
pulse time
FT
If the low-pulse width timer clock source is FT (this clock source can be set by IOCA1);
prescaler (1 decimal of low pulse width timer value (IOCE0))
T
low pulse time
FT
Pre-scaler
(IOCA1)
High-Pulse Width Timer
Low -Pulse Width Timer
( IOCE0)
Fs Fm
(IOCD0)
8
8
Auto-reloadbuffer
Auto-reloadbuffer
Pre-scaler
(IOC A1)
8
8
Pre-scaler
(IOC91)
8 bit dow n counter
8
8 bit dow n counter
8
Fcarrier
8 bit dow n counter
H/W Modulator Circuit
IROUTpin
8
Auto-reloadbuffer
8
HF
LGP
IRE
REregister
Counter 2
(IOCC0)
Fm: main oscillator frequency Fs: sub-oscillator frequency
Figure 6-20 IR/PWM System Block Diagram
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
51
EM78P468B
8-Bit Microcontroller
The IROUT output waveform is further explained in the following figures:
Figure 6-21 LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform
when in low-pulse width time.
Figure 6-22
LGP=0, HF=0, the IROUT waveform cannot modulate Fcarrier
waveform when in low-pulse width time. So IROUT waveform is determined
by high-pulse time and low-pulse time. This mode can produce standard
PWM waveform.
Figure 6-23
LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform
when in low-pulse width time. When IRE goes from high to low, the output
waveform of IROUT will keep on transmitting until high-pulse width timer
interrupt occurs.
Figure 6-24
LGP=0, HF=0, the IROUT waveform can not modulate Fcarrier
waveform when in low-pulse width time. So IROUT waveform is determined
by high-pulse time and low-pulse time. This mode can produce standard
PWM waveform. When IRE goes from high to low, the output waveform of
IROUT will keep on transmitting till high-pulse width timer interrupt occurs.
Figure6-25
LGP=1, when this bit is set to high level, the high-pulse width timer is
ignored. So IROUT waveform output from low-pulse width timer is
established.
Fcarrier
high-pulse width
low-pulse width
high-pulse width
low-pulse width
HF
IRE
start
IROUT
Figure 6-21 LGP=0, IROUT Pin Output Waveform
Fcarrier
high-pulse width
low-pulse width
high-pulse width
low-pulse width
HF
IRE
start
IROUT
Figure 6-22 LGP=0, IROUT Pin Output Waveform
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EM78P468B
8-Bit Microcontroller
Fcarrier
high-pulse width
low-pulse width
low-pulse width
low-pulse width
high-pulse width
low-pulse width
HF
start
start
start
IR disable
IRE
IROUT
Always high-level
Figure 6-23 LGP=0, IROUT Pin Output Waveform
Fcarrier
high-pulse width
high-pulse width
low-pulse width
HF
IRE
IR disable
IROUT
Always high-level
Figure 6-24 LGP=0, IROUT Pin Output Waveform
Fcarrier
high-pulse width
Low-pulse width
low-pulse width
HF
IR disable
IRE
IROUT
Always high-level
Figure 6-25 LGP=1, IROUT Pin Output Waveform
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
53
EM78P468B
8-Bit Microcontroller
IR/PWM Function Enable Flowchart
Start
Start
Set P57 to Output state (IOC 50)
Set P57 to Output state (IOC 50)
Set P57 for IR/PWM Function Output Pin (RE)
Set Counter 2 clock source and prescaler (IOC91)
Set P57 for IR/PWM Function Output Pin (RE)
Set High pulse width timer, Low pulse width timer
clock source and prescaler (IOCA1)
Set High pulse width timer, Low pulse width timer
clock source and prescaler (IOCA1)
(IOD0)
High pulse width timer
, Low pulse width timer
(IOCE0) preset value
(IOC0)
Set Counter 2
, High pulse width timer
(IOD0)
(IOCE0)
preset value
, Low pulse width timer
Enable IR (RE)
HF="0", and IRE="1"
(RE)
Enable IR
HF="1", and IRE="1"
Enable HPWT and LPWT Interrupt
IOCF0
Set
and ENI instruction
Enable HPWT and LPWT Interrupt
IOCF0
Set
and ENI instruction
Enable high pulse width timer and Low pulse width
Timer (RC)
Enable Counter 2, High pulse width timer and Low
(RC)
pulse width timer
END
END
(a) IR application
(b) PWM application
Figure 6-26 IR/PWM Function Enable Flowchart
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Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
6.11 Code Options
The EM78P468B has one Code Option word that is not a part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
Word 1 of the code options is for customer ID code application.
Word 1
Bit 12~Bit 0
Word 0 of Code Option is for IC function setting. The following are the settings for OTP
IC programming:
Mne-
Bits 12 ~ 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bits 2 ~ 0
monic
1
CYES HLFS ENWDTB FSMD FMMD1 FMMD0
0
PR2 ~ 0
Disable
Enable
1
1
0
High High Disable
High
Low
1
High
Low
1
High
Low
1
Low
1
Low
1
Enable
1
Default
Bits 12 ~ 10: Not used.
These bits are set to “1” all the time.
Bit 9 (CYES): Cycle select for JMP and CALL instructions
CYES = "0": only one instruction cycle (JMP or CALL) can be executed
CYES = "1": two instruction cycles (JMP and CALL) can be executed
Bit 8 (HLFS): main or sub-oscillator select
HLFS = "0": CPU is set to select sub-oscillator when reset occurs.
HLFS = "1": CPU is set to select main-oscillator when reset occurs.
Bit 7 (ENWDTB): Watchdog timer enable/disable bit.
ENWDTB = "0": Enable watchdog timer
ENWDTB = "1": Disable watchdog timer
Bit 6 (FSMD): Sub-oscillator type selection
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
55
EM78P468B
8-Bit Microcontroller
Bits 5, 4 (FMMD1, 0): Main Oscillator Type Selection
FSMD
FMMD1
FMMD0
Main Oscillator Type
RC type
Sub Oscillator Type
RC type
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
1
Crystal type
PLL type
RC type
RC type
RC type
Crystal type
Crystal type
Crystal type
Crystal type
PLL type
Bit 3: Not used
These bits are set to “0” all the time.
Bits 2~0 (PR2~PR0): Protect Bit
PR2~PR0 are protection bits. Each protect status is as follows:
PR2
0
PR1
0
PR0
0
Protect
Enable
Disable
1
1
1
6.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ). In this case, the
execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", and "RETI"
instructions, or the conditional skip instructions ("JBS", "JBC", "JZ", "JZA", "DJZ",
"DJZA") which were tested to be true. Also execute within two instruction cycles the
instructions that are written to the program counter.
Additionally, the instruction set offers the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
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EM78P468B
8-Bit Microcontroller
Convention:
R = Register designator that specifies which one of the registers (including operation and general
purpose registers) is to be utilized by the instruction.
b = Bit field designator that selects the value for the bit located in the register R and which affects
the operation.
k = 8 or 10-bit constant or literal value
Status
Affected
Mnemonic
Operation
No Operation
NOP
DAA
SLEP
WDTC
IOW
None
C
Decimal Adjust A
0 WDT, Stop oscillator
0 WDT
T, P
T, P
R
A IOCR
None1
None
None
None
ENI
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
[Top of Stack] PC,
Enable Interrupt
IOCR A
DISI
RET
RETI
None
IOR
R
None1
MOV
CLRA
CLR
SUB
SUB
DECA
DEC
OR
R,
A
A R
None
0 A
Z
R
0 R
Z
A,
R,
R
R
A
R-A A
Z,C,DC
R-A R
Z,C,DC
R-1 A
Z
R
R-1 R
Z
A,
R,
A,
R,
A,
R,
A,
R,
A,
R,
R
R
A
R
A
R
A
R
A
R
R
A R A
Z
OR
A R R
A & R A
A & R R
A R A
A R R
A + R A
Z
AND
AND
XOR
XOR
ADD
ADD
MOV
MOV
COMA
COM
INCA
INC
Z
Z
Z
Z
Z, C, DC
A + R R
Z, C, DC
R A
Z
R R
Z
Z
/R A
R
/R R
Z
R
R+1 A
Z
R
R+1 R
Z
DJZA
DJZ
R
R-1 A, skip if zero
R-1 R, skip if zero
None
None
R
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
57
EM78P468B
8-Bit Microcontroller
Status
Mnemonic
Operation
R(n) A(n-1),
Affected
RRCA
RRC
R
R
R
R
R
C
C
R(0) C, C A(7)
R(n) R(n-1),
R(0) C, C R(7)
R(n) A(n+1),
RLCA
RLC
C
R(7) C, C A(0)
R(n) R(n+1),
C
R(7) (C), C (R(0)
R(0-3) ( A(4-7),
R(4-7) ( A(0-3)
SWAPA
None
SWAP
JZA
JZ
R
R(0-3) ( R(4-7)
R+1 A, skip if zero
R+1 R, skip if zero
0 ( R(b)
None
None
None
None
None
None
None
R
R
BC
R,
R,
R,
R,
b
b
b
b
BS
1 ( R(b)
JBC
JBS
if R(b)=0, skip
if R(b)=1, skip
PC+1 [SP],
CALL
k
None
(Page, k) (PC)
JMP
MOV
OR
k
(Page, k) (PC)
k A
None
A,
A,
A,
A,
k
k
k
k
None
A v k A
A & k A
A k A
Z
Z
Z
AND
XOR
RETL
k
k A, [Top of Stack] PC
None
SUB
A,
A,
k
k
k
k-A A
Z, C, DC
Z, C, DC
None
ADD
k+A A
PAGE
BANK
KR3(5:6)
KR4(7:6)
k
None
Note: 1This instruction is applicable to IOC50~IOF0, IOC61~IOCE1.
58
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
6.13 Timing Diagram
AC Test Input/Output Waveform
2.4
2.0
0.8
2.0
0.8
TEST POINTS
0.4
Note: AC Testing: Input are driven at 2.4V for logic “1,” and 0.4V for logic “0”
Timing measurements are made at 2.0V for logic “1,” and 0.8V for logic “0”
Reset Timing (CLK="0")
Instruction 1
NOP
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
ins
CLK
TCC
tcc
Ttrf
Ttrr
90%
90%
10%
Port (n+1)
10%
Tiod
Port (n)
*n = 0 , 2 , 4 , 6
Figure 6-27 Timing Diagrams of EM78P468B
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
59
EM78P468B
8-Bit Microcontroller
7 Absolute Maximum Ratings
Rating
Items
Symbol
Condition
Unit
Min.
Max.
+7.0
Supply voltage
VDD
VI
GND-0.3
GND-0.3
GND-0.3
-40
V
V
Input voltage
Port 5 ~ Port 8
VDD+0.3
VDD+0.3
85
Output voltage
VO
Port 5 ~ Port 8
V
Operation temperature
Storage temperature
Power consumption
Operating Frequency
TOPR
TSTG
PD
C
C
mW
Hz
-65
150
500
32.768K
10M
8 Electrical Characteristics
8.1 DC Electrical Characteristics
Ta= -40C ~85 C, VDD=5.0V, GND=0V
Symbol
Parameter
Crystal: VDD to 5V
Sub-oscillator
Condition
Min.
Typ. Max. Unit
10M kHz
kHz
FXT
Fs
Two cycles with two clocks
Two cycles with two clocks
32.768 8M
32.768
External R, Internal C for
Sub-oscillator
270
384
500 kHz
R: 300K, internal capacitance
R: 2.2M, internal capacitance
VIN = VDD, GND
ERIC
External R, Internal C for
Sub-oscillator
22.9 32.768 42.6 kHz
Input Leakage Current for
Input pins
IIL
-1
2.0
0
1
A
V
Input High Threshold
Voltage (Schmitt Trigger)
VIH1
VIL1
Ports 5, 6, 7, 8
Input High Threshold
Voltage (Schmitt Trigger)
Ports 5, 6, 7, 8
0.8
V
Input High Threshold
Voltage (Schmitt Trigger)
VIHT1
VILT1
VIHT2
VILT2
IOH1
IOL1
IOH2
IOL2
/RESET
2.0
V
Input Low Threshold Voltage
(Schmitt Trigger)
/RESET
0.8
V
Input High Threshold
Voltage (Schmitt Trigger)
TCC, INT0, INT1
2.0
V
Input Low Threshold Voltage
(Schmitt Trigger)
TCC, INT0, INT1
0.8
V
High Drive Current
(Ports 5 ~ 8)
VOH = 2.4V (IROCS=”0”)
VOL = 0.4V (IROCS=”0”)
VOH = 2.4V (IROCS=”1”)
VOL = 0.4V (IROCS=”1”)
-10
10
20
20
mA
mA
mA
mA
Low Sink Current
(Ports 5 and 6)
High Drive Current
(Ports 5 ~ 8)
Low Sink Current
(Ports 5 and 6)
60
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
Ta= -40C ~85C, VDD=5.0V, GND=0V
Symbol
IPH
Parameter
Pull-high current
Condition
Min. Typ. Max. Unit
Pull-high active, input pin at GND -55
-75
75
-95
95
A
A
IPL
Pull-low current
Pull-low active, input pin at VDD
55
All input and I/O pins at VDD,
Output pin floating,
WDT disabled
ISB
Sleep mode current
0.5
14
1.5
18
A
/RESET= 'High', CPU OFF,
Sub-oscillator clock (32.768kHz)
ON, output pin floating,
ICC1
Idle mode current
A
LCD enabled, no load
/RESET= 'High', CPU ON,
Sub-oscillator clock (32.768kHz),
Output pin floating,
ICC2
Green mode current
22
30
A
WDT enabled, LCD enabled
/RESET= 'High', Fosc = 4 MHz
(Crystal type, CLKS="0"),
Output pin floating
ICC3
ICC4
Normal mode
Normal mode
2.2
3.1
3
4
mA
mA
/RESET= 'High', Fosc = 10 MHz
(Crystal type, CLKS="0"),
Output pin floating
Ta= -40C ~85C, VDD=3.0V, GND=0V
Symbol
FXT
Parameter
Crystal: VDD to 5V
Sub-oscillator
Condition
Min.
Typ. Max. Unit
10M kHz
32.768 kHz
Two cycles with two clocks
Two cycles with two clocks
32.768 8M
Fs
External R, Internal C for
Sub-oscillator
270
384
500 kHz
R: 300K, internal capacitance
R: 2.2M, internal capacitance
VIN = VDD, GND
Ports 5, 6, 7, 8
ERIC
External R, Internal C for
Sub-oscillator
22.9 32.768 42.6 kHz
Input Leakage Current for
Input pins
IIL
-1
1.8
0
1
A
V
Input High Threshold
Voltage (Schmitt Trigger)
VIH1
VIL1
Input High Threshold
Voltage (Schmitt Trigger)
Ports 5, 6, 7, 8
0.6
V
Input High Threshold
Voltage (Schmitt Trigger)
VIHT1
VILT1
VIHT2
VILT2
IOH1
IOL1
/RESET
1.8
V
Input Low Threshold
Voltage (Schmitt Trigger)
/RESET
0.6
V
Input High Threshold
Voltage (Schmitt Trigger)
TCC, INT0, INT1
1.8
V
Input Low Threshold
Voltage (Schmitt Trigger)
TCC, INT0, INT1
0.6
V
Output High Voltage
(Ports 5~8)
VOH = 2.4V, IROCS=”0”
VOL = 0.4V, IROCS=”0”
-1.8
6
mA
mA
Output Low Voltage
(Ports 5~8)
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
61
EM78P468B
8-Bit Microcontroller
Ta= -40C ~85C, VDD=3.0V, GND=0V
Symbol
Parameter
Condition
Min.
Typ. Max. Unit
Output high voltage
(P57/IROUT pin)
IOH2
VOH = 2.4V, IROCS=”1”
-3.5
12
mA
mA
Output Low Voltage
(P57/IR OUT pin)
IOL2
VOL = 0.4V, IROCS=”1”
Pull-high current
Pull-low current
Pull-high active, input pin at GND
Pull-low active, input pin at VDD
IPH
IPL
-16
16
-23
23
-30
30
A
A
All input and I/O pins at VDD, Output
pin floating, WDT disabled
ISB
Sleep mode current
0.1
1
A
/RESET= 'High', CPU OFF,
Sub-oscillator clock (32.768kHz) ON,
Output pin floating,
ICC1
Idle mode current
4
8
A
LCD enabled, no load
/RESET= 'High', CPU ON,
Sub-oscillator clock (32.768kHz),
Output pin floating,
ICC2
ICC3
Green mode current
Normal mode
10
20
A
WDT enabled, LCD enabled
/RESET= 'High', Fosc = 4 MHz
(Crystal type, CLKS="0"),
Output pin floating
0.73
1.2
mA
8.2 AC Electrical Characteristics
Ta=- 40C ~ 85 C, VDD=5V5%, GND=0V
Symbol
Parameter
Conditions
Min
45
Typ
Max
Unit
%
Input CLK duty cycle
Dclk
Crystal type
RC type
50
55
DC
DC
100
500
ns
Instruction cycle time
(CLKS="0")
Tins
ns
TCC input period
Ttcc
Tdrh
(Tins+20)/N*
ns
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
Output pin delay time
Ta = 25 C
11.3
2000
11.3
16.2
21.6
ms
ns
Trst
Ta = 25 C
Twdt
Tset
Ta = 25 C
16.2
0
21.6
ms
ns
Thold
Tdelay
20
50
ns
Cload=20pF
ns
*N= selected prescaler ratio
62
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
APPENDIX
A Ordering and Manufacturing Information
EM78P468BQ64J
Material Type
J: RoHS complied
S: Sony SS-00259 complied
Contact Elan Sales for details
Pin Number
Package Type
D: DIP
SO: SOP
SS: SSOP
Specific Annotation
Product Number
Product Type
P: OTP
Elan 8- bit Product
For example:
EM78P468BQ64
is EM78P468B with OTP program memory,
package
in64-pin QFP
‧‧‧‧‧‧‧
Elan Product Number
Batch Number
EM78Paaaa
1041 bbbbbb
Manufacture Date
“YYWW”
YY is year and WW is week
‧‧‧‧‧‧‧
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
63
EM78P468B
8-Bit Microcontroller
Ordering Code
EM78P468BQ64J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
64
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
B Package Type
Name
Package Type
Dice
Pin Count
Package Size
EM78P468BH
59
64
64
44
44
64
48
EM78P468BQ64
EM78P468BL64
EM78P468BL44
EM78P468BQ44
EM78P468BQ64B
EM78P468BL48
QFP
14 mm 20 mm
7 mm 7 mm
10 mm 10 mm
10 mm 10 mm
14 mm 14 mm
7 mm 7 mm
LQFP
LQFP
QFP
QFP
LQFP
Note: These are Green products that do not contain hazardous substances.
These are compatible with the third edition of Sony SS-00259 standard.
The Pb content should be less than 100ppm, and should meet Sony specifications or
requirements.
Part No.
Electroplate type
EM78P468BxS/xJ
Pure Tin
Sn:100%
232C
Ingredient (%)
Melting point (C)
Electrical resistivity (-cm)
Hardness (hv)
11.4
8~10
Elongation (%)
>50%
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
65
EM78P468B
8-Bit Microcontroller
C Package Information
QFP – 64
Symbol
Min.
一
Normal
一
Max.
3.40
一
A
A1
A2
D
0.25
2.55
一
A1
2.72
3.05
25.00 BASIC
20.00 BASIC
19.00 BASIC
14.00 BASIC
3.5
D1
E
E1
θ
0°
7°
c
0.11
1.15
0.15
0.23
1.45
L
1.3
L1
b
2.50 REF
0.4
0.35
0.50
e
1.00 BSC
/
TITLE:
QFP-64 L(14*20 MM) FOOTPRINT 5.0mm
PACKAGE OUTLINE DIMENSION
File :
QFP 64L
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
66
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
QFP – 64
DETAIL " A
"
Package Type : QFP-64L
EMC
D1
Symbol
Min.
Normal
Max.
2.45
0.25
2.2
D
A
A1
A2
D
1.8
2.0
14.00
17.2
L
D1
E
L1
14.00
17.2
E1
c
0.11
0.73
0.23
1.03
L
0.88
1.6
L1
b
0.29
0
0.45
7
64
e
0.8 BASIC
θ
1
e
b
TITLE:
QFP 64L ( 14*14 MM ) FOOTPRINT 3.2 mm
PACKAGE OUTLINE DIMENSION
A1
File :
Edtion: A
DETAIL " B "
QFP 64L
Unit : mm
Scale: Free
c
Material:
b
Sheet:1 of 1
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
67
EM78P468B
8-Bit Microcontroller
LQFP – 64
DETAIL " A
"
Symbol
A
Min.
-
Normal
-
Max.
1.60
0.15
1.45
9.10
7.10
9.10
7.100
D
D1
A1
A2
D
0.05
1.35
8.90
6.90
8.90
6.900
-
1.40
9.00
7.00
9.00
7.00
0.4 BSC
-
D1
E
L
L1
E1
e
c
0.09
0.09
0.13
0.13
0.45
0.20
0.16
0.23
0.19
0.75
c1
b
-
0.18
0.16
0.60
1.00 REF.
3.5°
b1
L
64
L1
θ
1
0°
7°
e
b
TITLE:
LQFP 64L ( 7*7 MM ) FOOTPRINT 2.0 mm
PACKAGE OUTLINE DIMENSION
A1
File :
Edtion: A
DETAIL " B "
LQFP 64L
Unit : mm
Scale: Free
c1
c
b
Material:
b1
Sheet:1 of 1
68
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
LQFP – 44
Symbol
Min .
Normal
Max .
1.600
0.150
1.450
0.450
0.200
A
A1
A2
b
0.050
1.350
0.300
0.090
1.400
0.370
c
12.00 BASIC
10.00 BASIC
0.600
E1
E
c
L
0.450
0
0.750
7
L1
e
1.0 (BASIC)
0.8 (BASIC)
3.5
θ
TITLE:
LQFP-44L (10*10 MM) FOOTPRINT 2.0mm
PACKAGE OUTLINE DIMENSION
File :
LQFP44
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
69
EM78P468B
8-Bit Microcontroller
QFP – 44
Symbol
A
Min.
Normal
Max.
2.70
0.50
2.20
A1
A2
b
0.15
1.80
2.00
0.30(TYP)
0.15(TYP)
13.20
c
E1
E
13.00
9.90
0.73
1.50
13.40
10.10
1.03
c
10.00
L
0.88
L1
e
1.60
1.70
0.80(TYP)
θ
0
7
TITLE:
QFP-44L(10*10 MM) FOOTPRINT 3.2mm
PACKAGE OUTLINE DIMENSION
File :
QFP44
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
70
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
LQFP – 48
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
71
EM78P468B
8-Bit Microcontroller
D EM78P468B Program Pin List
L/QFP-64
LQFP-48
L/QFP-44
Program Pin Name
IC Pin Name
Pin Number
Pin Number
Pin Number
VPP
ACLK
DINCLK
DATAIN
/PGMB
/OEB
/RESET
P54/INT0
P55/INT1
P56/TCC
P60
25
32
33
34
38
39
29
26
22
28
29
30
32
33
25
23
14
21
22
23
25
26
18
15
P61
VDD
VDD
GND
GND
72
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
EM78P468B
8-Bit Microcontroller
E Quality Assurance and Reliability
Test Category
Solderability
Test Conditions
Remarks
Solder temperature=2455°C, for 5 seconds up to the
stopper using a rosin-type flux
–
Step 1: TCT, 65°C (15 min)~150°C (15mins), 10 cycles
Step 2: Bake at 125°C, TD (endurance)=24 hrs
Step 3: Soak at 30°C/60%，TD (endurance)=192 hrs
Step 4: IR flow 3 cycles
For SMD IC (such as
SOP, QFP, SOJ, etc)
Pre-condition
(Pkg thickness 2.5 mm or
Pkg volume 350 mm3 ----225 5°C)
(Pkg thickness 2.5 mm or
Pkg volume 350 mm3 ----240 5°C)
Temperature cycle test -65°C (15mins)~150°C (15 min), 200 cycles
–
–
TA =121°C, RH=100%, pressure=2 atm,
Pressure cooker test
TD (endurance)= 96 hrs
High temperature /
TA=85°C, RH=85%，TD (endurance) = 168, 500 hrs
High humidity test
–
–
High-temperature
TA=150°C, TD (endurance) = 500, 1000 hrs
storage life
High-temperature
operating life
TA=125°C, VCC = Max. operating voltage,
TD (endurance) = 168, 500, 1000 hrs
–
–
Latch-up
TA=25°C, VCC = Max. operating voltage, 150mA/20V
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (HBM)
TA=25°C, ∣± 3KV∣
ESD (MM)
TA=25°C, ∣± 300V∣
VDD-VSS(+),VDD_VSS
(-) mode
E.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise-caused address error is detected, the MCU will repeat execution of the
program until the noise is eliminated. The MCU will then continue to execute the next
program.
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
73
EM78P468B
8-Bit Microcontroller
74
Product Specification (V1.3) 03.25.2016
(This specification is subject to change without prior notice)
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