EM78P520N [ELAN]
8-Bit Microprocessor with OTP ROM;
| 型号： | EM78P520N |
| 厂家： | 
ELAN MICROELECTRONICS CORP |
| 描述： | 8-Bit Microprocessor with OTP ROM OTP只读存储器 |
| 文件： | 总124页 (文件大小：3405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM78P520N
8-Bit Microprocessor
with OTP ROM
Product
Specification
DOC. VERSION 1.4
ELAN MICROELECTRONICS CORP.
April 2016
Trademark Acknowledgments:
IBM is a registered trademark and PS/2 is a trademark of IBM.
Windows is a trademark of Microsoft Corporation
ELAN and ELAN logo
are trademarks of ELAN Microelectronics Corporation
Copyright © 2016 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no
responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics
makes no commitment to update, or to keep current the information and material contained in this specification.
Such information and material may change to conform to each confirmed order.
In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or
other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not
be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information
or material.
The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and
may be used or copied only in accordance with the terms of such agreement.
ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of
ELAN Microelectronics product in such applications is not supported and is prohibited.
NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY
ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters:
Hong Kong:
USA:
No. 12, Innovation Road 1
Hsinchu Science Park
Hsinchu, TAIWAN 308
Tel: +886 3 563-9977
Fax: +886 3 563-9966
webmaster@emc.com.tw
http://www.emc.com.tw
Elan (HK) Microelectronics
Corporation, Ltd.
Flat A, 19F., World Tech Centre
95 How Ming Street, Kwun Tong
Kowloon, HONG KONG
Tel: +852 2723-3376
Elan Information
Technology Group (U.S.A.)
PO Box 601
Cupertino, CA 95015
U.S.A.
Tel: +1 408 366-8225
Fax: +1 408 366-8225
Fax: +852 2723-7780
Shenzhen:
Shanghai:
Elan Microelectronics
Shenzhen, Ltd.
Elan Microelectronics
Shanghai, Ltd.
8A Floor, Microprofit Building
Gaoxin South Road 6
6F, Ke Yuan Building
No. 5 Bibo Road
Shenzhen Hi-tech Industrial Park
South Area, Shenzhen
CHINA 518057
Tel: +86 755 2601-0565
Fax: +86 755 2601-0500
elan-sz@elanic.com.cn
Zhangjiang Hi-Tech Park
Shanghai, CHINA 201203
Tel: +86 21 5080-3866
Fax: +86 21 5080-0273
elan-sh@elanic.com.cn
Contents
Contents
1
2
3
4
5
6
General Description ................................................................................................ 1
Features ................................................................................................................... 1
Pin Assignment ....................................................................................................... 2
Pin Description........................................................................................................ 4
Block Diagram ......................................................................................................... 9
Function Description............................................................................................. 10
6.1 Register Configuration ....................................................................................10
6.1.1 R PAGE Register Configuration........................................................................10
6.2 Register Operations........................................................................................10
6.2.1 R0 (Indirect Addressing Register).....................................................................10
6.2.2 R1 (TCC)...........................................................................................................10
6.2.3 R2 (Program Counter) ...................................................................................... 11
6.2.4 R3 (LVD Control and Status).............................................................................12
6.2.5 R4 (RAM Select Register).................................................................................13
6.2.6 Bank 0 R5 (RAM Bank Select Register) ...........................................................13
6.2.7 Bank 0 R7 (Port 7) ............................................................................................13
6.2.8 Bank 0 R8 (Port 8) ............................................................................................13
6.2.9 Bank 0 R9 (Port 9) ............................................................................................14
6.2.10 Bank 0 RA (Port A)............................................................................................14
6.2.11 Bank 0 RB (Port B) ...........................................................................................14
6.2.12 Bank 0 RC SCCR (System Clock Control Register).........................................14
6.2.13 Bank 0 RD TWTCR (TCC and WDT Timer Control Register) ..........................15
6.2.14 Bank 0 RE IMR (Interrupt Mask Register) ........................................................16
6.2.15 Bank 0 RF ISR (Interrupt Status Register)........................................................16
6.2.16 Bank 1 R5 LCDCR (LCD Control Register) ......................................................17
6.2.17 Bank 1 R6 LCDAR (LCD Address Register).....................................................17
6.2.18 Bank 1 R7 LCDBR (LCD Data Buffer) ..............................................................18
6.2.19 Bank 1 R8 LCDVCR (LCD Voltage Control Register).......................................18
6.2.20 Bank 1 R9 LCDCCR (LCD COM Control Register 3).......................................19
6.2.21 Bank 1 RA LCDSCR0 (LCD Segment Control Register 0)...............................19
6.2.22 Bank 1 RB LCDSCR1 (LCD Segment Control Register 1)...............................19
6.2.23 Bank 1 RC LCDSCR2 (LCD Segment Control Register 2) ..............................20
6.2.24 Bank 1 RE EIMR (External Interrupt Mask Register)........................................20
6.2.25 Bank 1 RF EISR (External Interrupt Status Register).......................................20
6.2.26 Bank 2 R5 T1CR (Timer 1 Control Register) ....................................................21
6.2.27 Bank 2 R6 TSR (Timer Status Register) ...........................................................22
6.2.28 Bank 2 R7 T1PD (Timer 1 Period Buffer)..........................................................23
6.2.29 Bank 2 R8 T1TD (Timer 1 Duty Buffer).............................................................23
6.2.30 Bank 2 R9 T2CR (Timer 2 Control Register) ....................................................23
Product Specification (V1.4) 04.08.2016
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Contents
6.2.31 Bank 2 RA T2PD (Timer 2 Period Buffer) .........................................................24
6.2.32 Bank 2 RB T2TD (Timer 2 Duty Buffer) ............................................................24
6.2.33 Bank 2 RC SPIS (SPI Status Register).............................................................24
6.2.34 Bank 2 RD SPIC (SPI Control Register)...........................................................25
6.2.35 Bank 2 RE SPIR (SPI Read Buffer)..................................................................26
6.2.36 Bank 2 RF SPIW (SPI Write Buffer)..................................................................26
6.2.37 Bank 3 R5 URC (UART Control Register) ........................................................27
6.2.38 Bank 3 R6 URS (UART Status).........................................................................28
6.2.39 Bank 3 R7 URRD (UART_RD Data Buffer) ......................................................28
6.2.40 Bank 3 R8 URTD (UART_TD Data Buffer) .......................................................29
6.2.41 Bank 3 R9 ADCR (A/D Control Register)..........................................................29
6.2.42 Bank 3 RAADICH (A/D Input Control Register) ...............................................30
6.2.43 Bank 3 RB ADICL (A/D Input Control Register)................................................30
6.2.44 Bank 3 RC ADDH (AD High 8-bit Data Buffer)..................................................30
6.2.45 Bank 3 RD ADDL (AD Low 4-bit Data Buffer)...................................................30
6.2.46 Bank 3 RE EIESH (External Interrupt Edge Select High Byte
Control Register) ..............................................................................................31
6.2.47 Bank 3 RF EIESL (External Interrupt Edge Select Low Byte
Control Register) ..............................................................................................31
6.2.48 Bank 4 R5 LEDDCR (LED Drive Control Register) ..........................................32
6.2.49 Bank 4 R6 WBCR (Watch Timer and Buzzer Control Register) ......................32
6.2.50 Bank 4 R7 P7IOCR (Port 7 I/O Control Register).............................................33
6.2.51 Bank 4 R8 P8IOCR (Port 8 I/O Control Register).............................................33
6.2.52 Bank 4 R9 P9IOCR (Port 9 I/O Control Register).............................................33
6.2.53 Bank 4 RA PAIOCR (Port A I/O Control Register) ............................................33
6.2.54 Bank 4 RB PBIOCR (Port B I/O Control Register)............................................34
6.2.55 Bank 4 RC PCIOCR (Port C I/O Control Register)...........................................34
6.2.56 Bank 4 RF WKCR (Wake-up Control Register) ................................................34
6.2.57 Bank 5 R6 UARC2 (UART Control Register 2).................................................34
6.2.58 Bank 5 R7 P7PHCR (Port 7 Pull-high Control Register) ..................................35
6.2.59 Bank 5 R8 P8PHCR (Port 8 Pull-high Control Register) ..................................35
6.2.60 Bank 5 R9 P9PHCR (Port 9 Pull-high Control Register) ..................................35
6.2.61 Bank 5 RA PAPHCR (Port A Pull-high Control Register)..................................35
6.2.62 Bank 5 RB PBPHCR (Port B Pull-high Control Register).................................36
6.2.63 Bank 5 RC PCPHCR (Port C Pull High Control Register) ................................36
6.2.64 Bank 6 R6 LVRCR (Low Voltage Reset Control Register)................................36
6.2.65 Bank 6 R7 P7ODCR (Port 7 Open Drain Control Register) .............................36
6.2.66 Bank 6 R8 P8ODCR (Port 8 Open Drain Control Register) .............................37
6.2.67 Bank 6 R9 P9ODCR (Port 9 Open Drain Control Register) .............................37
6.2.68 Bank 6 RA PAODCR (Port A Open Drain Control Register) .............................37
6.2.69 Bank 6 RB PBODCR (Port B Open Drain Control Register) ............................37
6.2.70 Bank 6 RC (Port C) ...........................................................................................37
6.2.71 R10~R3F (General Purpose Register) .............................................................37
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Product Specification (V1.4) 04.08.2016
Contents
6.3 TCC/WDT Prescaler .......................................................................................38
6.4 I/O Port...........................................................................................................39
6.5 Reset and Wake-up ........................................................................................40
6.6 Oscillator.........................................................................................................50
6.6.1 Oscillator Modes ...............................................................................................50
6.6.2 Crystal Oscillator/Ceramic Resonators (Crystal) ..............................................50
6.6.3 RC Oscillator Mode with Internal Capacitor......................................................53
6.6.4 Phase Lock Loop (PLL Mode)...........................................................................53
6.7 Power-on Considerations................................................................................55
6.7.1 External Power-on Reset Circuit.......................................................................55
6.7.2 Residue-Voltage Protection ..............................................................................56
6.8 Interrupt ..........................................................................................................57
6.9 LCD Driver......................................................................................................58
6.9.1 R5 LCDCR ( LCD Control Register) .................................................................59
6.9.2 R6 LCDADDR (LCD Address Register)............................................................60
6.9.3 R7 LCDBR (LCD Data Buffer) ..........................................................................61
6.9.4 R8 LCDVCR (LCD Voltage Control Register)...................................................61
6.10 A/D Converter.................................................................................................69
6.10.1 ADC Data Register............................................................................................70
6.10.2 A/D Sampling Time ...........................................................................................70
6.10.3 A/D Conversion Time........................................................................................70
6.11 UART (Universal Asynchronous Receiver/Transmitter)...................................71
6.11.1 UART Mode.......................................................................................................72
6.11.2 Transmitting.......................................................................................................73
6.11.3 Receiving ..........................................................................................................73
6.11.4 Baud Rate Generator........................................................................................74
6.11.5 UART Timing.....................................................................................................74
6.12 SPI (Serial Peripheral Interface) .....................................................................75
6.12.1 Overview and Features.....................................................................................75
6.12.2 SPI Function Description ..................................................................................77
6.12.3 SPI Signal and Pin Description.........................................................................78
6.12.4 Programming the Related Registers.................................................................80
6.12.5 SPI Mode Timing...............................................................................................83
6.13 Timer/Counter 1..............................................................................................84
6.13.1 Timer Mode .......................................................................................................85
6.13.2 T1OUT Mode ....................................................................................................85
6.13.3 Capture Mode ...................................................................................................85
6.13.4 PWM Mode .......................................................................................................86
6.13.5 16-Bit Mode.......................................................................................................86
Product Specification (V1.4) 04.08.2016
v
Contents
6.14 Timer 2 ...........................................................................................................87
6.14.1 Timer Mode .......................................................................................................88
6.14.2 PWM Mode .......................................................................................................88
6.15 Code Options..................................................................................................89
6.16 Instruction Set.................................................................................................91
7
8
Absolute Maximum Ratings.................................................................................. 94
DC Electrical Characteristics................................................................................ 94
8.1 DC Electrical Characteristics...........................................................................94
8.2 A/D Converter Characteristics.........................................................................96
8.3 Phase Lock Loop Characteristics....................................................................97
8.3.1 PLL DC Electrical Characteristics .....................................................................97
8.3.2 AC Electrical Characteristics.............................................................................97
8.4 Device Characteristics ....................................................................................97
9
AC Electrical Characteristics.............................................................................. 106
10 Timing Diagrams ................................................................................................. 107
APPENDIX
A
B
C
Ordering and Manufacturing Information .......................................................... 108
Package Type....................................................................................................... 109
Package Information ........................................................................................... 110
C.1 EM78P520NQ44........................................................................................... 110
C.2 EM78P520NL44 ........................................................................................... 111
C.3 EM78P520NL48 ........................................................................................... 112
D
Quality Assurance and Reliability ...................................................................... 113
D.1 Address Trap Detect..................................................................................... 113
EM78P520N Program Pin List............................................................................. 114
ICE 520 Oscillator Circuit (JP4) .......................................................................... 114
E
F
F.1 Mode 1 ......................................................................................................... 114
F.2 Mode 2 ......................................................................................................... 115
F.3 Mode 3 ......................................................................................................... 115
F.4 Mode 4 ......................................................................................................... 115
F.5 Mode 5 ......................................................................................................... 116
F.6 Mode 6 ......................................................................................................... 116
F.7 Mode 7 ......................................................................................................... 116
vi
Product Specification (V1.4) 04.08.2016
Contents
Specification Revision History
Doc. Version
Revision Description
Date
1.0
1.1
1.2
1.3
Initial released version
2009/04/01
2011/03/23
2013/04/09
2014/02/05
Modified the PLL mode that is used.
Added LVR specifications
Deleted the 32-pin Package Type
1. Added User Application Note
2. Modified the package type in the Features section
1.4
2016/04/08
3. Modified Appendix A “Ordering and Manufacturing
Information”
Product Specification (V1.4) 04.08.2016
vii
Contents
User Application Note
(Before using this chip, take a look at the following description note, it includes important messages.)
1.
2.
3.
The internal TCC will stop running when in sleep mode. However, during AD conversion, when
TCC is set to “SLEP” instruction, if the ADWE bit of the RE register is enabled, the TCC will keep
on running.
During ADC conversion, do not perform output instruction to maintain precision for all of the pins.
In order to obtain accurate values, it is necessary to avoid any data transition on I/O pins during
AD conversion
The noise rejection function is turned off in the LXT2 and sleep mode
viii
Product Specification (V1.4) 04.08.2016
EM78P520N
8-Bit Microprocessor with OTP ROM
1 General Description
The EM78P520N is an 8-bit RISC type microprocessor with low power, high speed CMOS technology. Integrated
onto a single chip are on-chip Watchdog Timer (WDT), LCD Data RAM, ROM, programmable real time clock
counter, internal/external interrupt, power down mode, 12 bits A/D Converter, UART, SPI, 8-channel LED driver,
LCD driver and tri-state I/O.
2 Features
CPU Configuration
Peripheral Configuration
8K13 bits on-chip ROM
Serial peripheral interface (SPI) available
8-bit real Time Clock/Counter (TCC)
2728 bits on-chip registers (SRAM)
8-level stacks for subroutine nesting
Dual clock operation or PLL operation mode
Four operation mode: Normal, Green, Idle, Sleep
Less than 2.1 mA at 5V/4MHz
12-channels Analog-to-Digital Converter with
12-bit resolution in Vref mode
LCD: 823 dots, bias (1/2, 1/3, 1/4),
duty (static, 1/3, 1/4, 1/8)
Two 8-bit timers
Typically 22 A, at 3V/32kHz
Typically 8 A, during sleep mode
Single Instruction Cycle Commands
8-bit Timer 1, auto reload counter/timer which
can be an interrupt source. Function mode;
Timer, Toggle output, UART baud rate generator,
Capture, PWM
I/O Port Configuration
8-bit Timer 2, auto reload timer which can be an
interrupt source. Function mode; Timer, SPI
baud rate generator, PWM
Two sets of 8-bit auto reload counter/timer which
can be cascaded to one 16-bit counter/timer
Six bidirectional I/O ports : P7, P8, P9, PA, PB, PC
43 I/O pins
8-pin Direct Drive LED
39 Programmable open-drain I/O pins
43 programmable pull-high I/O pins
External interrupt : P74~P77, PB0~PB3, P82~P83
Universal asynchronous receiver / transmitter
(UART) available
Operating voltage range:
OTP version:
Four programmable watch timer: 1.0 sec,
0.5 sec, 0.25sec, 3.91ms
Four programmable buzzer output: 0.5kHz,
1kHz, 2kHz, 4kHz
Operating voltage range : 2.3V~5.5V
Operating temperature range : -40~85 C
Operating frequency range:
Four programmable Level Voltage Detector
(LVD) : 3.9V, 3.3V, 2.7V, 2.4V
Crystal/RC oscillation circuit selected by code option
for system clock
Power-on reset and three Programmable Level
Voltage Reset POR: 2.1V (Default)
LVR: 3.9V, 3.3V, 2.6V
32.768kHz crystal/RC oscillation circuit selected by
code option for sub-oscillation
Eighteen available interrupts:
Main Clock
TCC overflow interrupt
Crystal mode:
Ten External interrupts
(wake-up from sleep mode)
DC~20MHz/2 clks @ 5V; DC~100ns inst. cycle @ 5V
DC~8MHz/2 clks @ 3V; DC~250ns inst. Cycle @ 3V
DC~4MHz/2 clks @ 2.3V; DC~500ns inst. Cycle @ 2.3V
ERIC mode:
ADC completion interrupt
Two timer interrupt
Watch timer interrupt
Two serial I/O interrupt
Low voltage detect (LVD)
DC~2.2MHz/2 clks @ 2.3V; DC~909ns inst. cycle @ 2.3V
PLL mode:
DC~16MHz/2 clks @ 5V; DC~125ns inst Cycle @ 5V
Package Type:
Sub Clock
44 pin QFP 1010mm : EM78P520NQ44
44 pin LQFP 1010mm : EM78P520NL44
48 pin LQFP 77mm : EM78P520NL48
Crystal mode: 32.768kHz
ERIC mode: 33kHz (2.2M)
Special Features
Note: These are Green Products which do not contain
Programmable free running watchdog timer
High ESD immunity
High EFT immunity
Power saving Sleep mode
Selectable Oscillation mode
hazardous substances.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
1
EM78P520N
8-Bit Microprocessor with OTP ROM
3 Pin Assignment
44 43 42 41 40 39 38 37 36 35 34
1
2
33
32
31
30
29
28
27
26
25
24
23
P74/SEG18/INT0
PA6/SEG6/SCK
PA5/SEG5/SO
PA4/SEG4/SI
PA3/SEG3
P75/INT1/T1OUT/PWM1
P76/INT2/T1CK
P77/INT3/T1CAP
VDD
3
4
5
PA2/SEG2
6
VSS
PA1/SEG1
EM78P520N-44Pin
7
OSCO
PA0/SEG0
8
OSCI
P97/COM0
P96/COM1
P95/COM2
P94/COM3
9
Test
10
11
PC2/Xin
PC3/Xout
12 13 14 15 16 17 18 19 20 21 22
Figure 3-2 EM78P520NQ44/L44
2
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
P74/SEG18/INT0
P75/INT1/T1OUT/PWM1
P76/INT2/T1CK
P77/INT3/T1CAP
VDD
PB1/SEG9/INT5/AD10
PB0/SEG8/INT4/AD9
PA7/SEG7//SS
PA6/SEG6/SCK
PA5/SEG5/SO
PA4/SEG4/SI
PA3/SEG3
3
4
5
EM78P520N-48Pin
6
VSS
7
OSCO
8
OSCI
PA2/SEG2
9
Test
PA1/SEG1
10
11
12
PC2/Xin
PA0/SEG0
PC3/Xout
P97/COM0
P81//RESET
P96/COM1
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3-3 EM78P520NL48
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
3
EM78P520N
8-Bit Microprocessor with OTP ROM
4 Pin Description
Input Output
Name
Function
Description
Type
ST
-
Type
Bidirectional I/O pin with programmable pull-high and
open-drain.
P70
SEG12
P71
CMOS
P70/SEG12
AN
CMOS
AN
LCD Segment 12 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
-
P71/SEG13
P72/SEG14
P73/SEG15
SEG13
P72
LCD Segment 13 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
-
CMOS
AN
SEG14
P73
LCD Segment 14 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
-
CMOS
AN
SEG15
P74
LCD Segment 15 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
CMOS
P74/SEG18/INT0
-
SEG18
INT0
AN
-
LCD Segment 18 output
External interrupt pin
ST
Bidirectional I/O pin with programmable pull-high and
open-drain.
P75
ST
CMOS
-
P75/INT1/T1OUT/
PWM1
INT1
ST
External interrupt pin
T1OUT
PWM1
-
-
CMOS Timer 1 T1OUT mode
CMOS Timer 1 PWM mode
Bidirectional I/O pin with programmable pull-high and
open-drain.
P76
ST
CMOS
P76/INT2/T1CK
P77/INT3/T1CAP
INT2
ST
ST
-
-
External interrupt pin
Timer 1 Counter mode
T1CK
Bidirectional I/O pin with programmable pull-high and
open-drain.
P77
ST
CMOS
INT3
ST
ST
-
-
External Interrupt pin
Timer 1 Capture mode
T1CAP
Bidirectional I/O pin with programmable pull-high and
open-drain.
P81
/RESET
P82
ST
ST
ST
CMOS
-
P81/
/RESET
Internal pull-high (set P57 pull-high) reset pin
Bidirectional I/O pin with programmable pull-high and
open-drain.
CMOS
P82/INT8/AD8
INT8
AD8
ST
AN
-
-
External interrupt pin
ADC Input 8
4
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
(Continuation)
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable pull-high and
open-drain.
P83
ST
CMOS
P83/COM7/INT9/
AD7
-
COM7
INT9
AD7
AN
LCD Common 7 output
External interrupt pin
ADC Input 7
-
-
ST
AN
Bidirectional I/O pin with programmable pull-high and
open-drain.
P84
VREF
P85
ST
AN
ST
CMOS
-
P84/VREF
Voltage reference for ADC
Bidirectional I/O pin with programmable pull-high and
open-drain.
CMOS
P85/COM6/AD6
-
COM6
AD6
AN
-
LCD Common 6 output
ADC Input 6
AN
Bidirectional I/O pin with programmable pull-high and
open-drain.
P86
ST
CMOS
P86/COM5/AD5
P87/COM4/AD4
P90/AD3/PWM2
P91/AD2/BUZ
-
COM5
AD5
AN
-
LCD Common 5 output
ADC Input 5
AN
Bidirectional I/O pin with programmable pull-high and
open-drain.
P87
ST
CMOS
-
COM4
AD4
AN
-
LCD Common 4 output
ADC Input 4
AN
Bidirectional I/O pin with programmable pull-high, open-drain
and LED drive.
P90
ST
CMOS
-
AD3
AN
-
ADC Input 3
PWM2
CMOS
Timer 2 PWM mode
Bidirectional I/O pin with programmable pull-high, open-drain
and LED drive.
P91
ST
CMOS
-
AD2
BUZ
AN
-
ADC Input 2
CMOS
Buzzer Timer output
Bidirectional I/O pin with programmable pull-high, open-drain
and LED drive.
P92
AD1
P93
ST
AN
ST
AN
ST
-
CMOS
-
P92/AD1
P93/AD0
P94/COM3
ADC Input 1
Bidirectional I/O pin with programmable pull-high, open-drain
and LED drive.
CMOS
-
AD0
P94
ADC Input 0
Bidirectional I/O pin with programmable pull-high, open-drain
and LED drive.
CMOS
AN
COM3
LCD Common 3 output
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
5
EM78P520N
8-Bit Microprocessor with OTP ROM
(Continuation)
Input Output
Name
Function
Description
Type
ST
-
Type
Bidirectional I/O pin with programmable pull-high, open-drain
and LED drive.
P95
COM2
P96
CMOS
P95/COM2
AN
CMOS
AN
LCD Common 2 output
Bidirectional I/O pin with programmable pull-high, open-drain
and LED drive.
ST
-
P96/COM1
P97/COM0
PA0/SEG0
PA1/SEG1
PA2/SEG2
PA3/SEG3
COM1
P97
LCD Common 1 output
Bidirectional I/O pin with programmable pull-high, open-drain
and LED drive.
ST
-
CMOS
AN
COM0
PA0
LCD Common 0 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
-
CMOS
AN
SEG0
PA1
LCD Segment 0 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
-
CMOS
AN
SEG1
PA2
LCD Segment 1 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
-
CMOS
AN
SEG2
PA3
LCD Segment 2 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
-
CMOS
AN
SEG3
PA4
LCD Segment 3 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
CMOS
PA4/SEG4/SI
PA5/SEG5/SO
PA6/SEG6/SCK
PA7/SEG7//SS
-
SEG4
SI
AN
-
LCD Segment 4 output
SPI serial data input
ST
Bidirectional I/O pin with programmable pull-high and
open-drain.
PA5
ST
CMOS
AN
-
-
SEG5
SO
LCD Segment 5 output
CMOS SPI serial data output
Bidirectional I/O pin with programmable pull-high and
open-drain.
PA6
ST
CMOS
AN
-
SEG6
SCK
LCD Segment 6 output
ST
CMOS SPI serial clock input/output
Bidirectional I/O pin with programmable pull-high and
open-drain.
PA7
ST
CMOS
-
SEG7
/SS
AN
-
LCD Segment 7 output
SPI Slave select pin
ST
6
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
(Continuation)
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable pull-high and
open-drain.
PB0
ST
CMOS
PB0/SEG8/INT4/
AD9
-
SEG8
INT4
AD9
AN
LCD Segment 8 output
External interrupt pin
ADC Input 9
-
-
ST
AN
Bidirectional I/O pin with programmable pull-high and
open-drain.
PB1
ST
CMOS
PB1/SEG9/INT5/
AD10
-
SEG9
INT5
AN
LCD Segment 9 output
External interrupt pin
ADC Input 10
-
-
ST
AN
AD10
Bidirectional I/O pin with programmable pull-high and
open-drain.
PB2
ST
CMOS
PB2/SEG10/INT6/
AD11
-
SEG10
INT6
AN
LCD Segment 10 output
External interrupt pin
ADC Input 11
-
-
ST
AN
AD11
Bidirectional I/O pin with programmable pull-high and
open-drain.
PB3
ST
CMOS
PB3/SEG11/INT7
PB4/SEG16/RX
-
SEG11
INT7
AN
-
LCD Segment 11 output
External interrupt pin
ST
Bidirectional I/O pin with programmable pull-high and
open-drain.
PB4
ST
CMOS
-
SEG16
RX
AN
-
LCD Segment 16 output
UART RX input
ST
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
7
EM78P520N
8-Bit Microprocessor with OTP ROM
(Continuation)
Input Output
Name
Function
Description
Type
Type
Bidirectional I/O pin with programmable pull-high and
open-drain.
PB5
ST
CMOS
PB5/SEG17/TX
-
-
SEG17
TX
AN
LCD Segment 17 output
CMOS UART TX output
Bidirectional I/O pin with programmable pull-high and
open-drain.
PB6
SEG19
PB7
ST
-
CMOS
AN
PB6/SEG19
PB7/SEG20
LCD Segment 19 output
Bidirectional I/O pin with programmable pull-high and
open-drain.
ST
-
CMOS
AN
SEG20
PC0
LCD Segment 20 output
ST
-
CMOS Bidirectional I/O pin with programmable pull-high.
AN LCD Segment 21 output
CMOS Bidirectional I/O pin with programmable pull-high.
AN LCD Segment 22 output
CMOS Bidirectional I/O pin with programmable pull-high.
Clock input of crystal/resonator oscillator only for 32.768kHz
PC0/SEG21
PC1/SEG22
PC2/Xin
SEG21
PC1
ST
-
SEG22
PC2
ST
XTAL
ST
Xin
-
PC3
CMOS Bidirectional I/O pin with programmable pull-high.
XTAL Clock output of crystal/resonator oscillator only for 32.768kHz
XTAL Clock output of crystal/resonator oscillator
PC3/Xout
Xout
-
OSCO
OSCI
VDD
VSS
OSCO
OSCI
VDD
VSS
-
XTAL
Power
Power
Power
-
-
-
-
Clock input of crystal/resonator oscillator
Power
Ground
Test
Test
Test signal import pin (must be connected to VDD)
Legend: ST : Schmitt Trigger input
AN : Analog pin
XTAL : Oscillation pin for crystal/resonator
CMOS : CMOS output
8
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
5 Block Diagram
P7
Start-up
T1CK
Ext.
OSC.
PC
PLL ERIC
ROM
timer
WDT
P70
P71
P72
P73
P74
P75
P76
P77
T1CAP
PWM1
Timer1
Oscillation
Generation
(PWM1)
8-level
stack
(13 bit)
Instruction
Register
PWM2
Timer2
(PWM2)
Buzzy
Sub
OSC ERIC
Sub
P8
Reset
Instruction
Decoder
Watch
Timer
P80
P81
P82
P83
P84
P85
P86
P87
TCC
LVD
SCK,
SDO,
SDI, /SS
Mux.
ALU
SPI
Tx, Rx
P9
UART
ADC
R4
P90
P91
ADin0~11
P92
P93
P94
P95
P96
P97
LCD
8 x 23
RAM
LCD
Interrupt
control
circuit
R3(Status
Reg.)
ACC
LVR
PA
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Ext INT0~9
Figure 5 EM78P520N Block Diagram
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
9
EM78P520N
8-Bit Microprocessor with OTP ROM
6 Function Description
6.1 Register Configuration
6.1.1 R PAGE Register Configuration
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
R0 (IAR)
R1 (TCC)
R2 (PC)
R3 (SR)
R4 (RSR)
RBSR
URC
URS
Reserve
URC2
Reserve
LVRCR
LCDCR
LCDAR
T1CR
TSR
LEDDCR
WBCR
IOC7
Reserve
Port 7
P7PHCR
P7ODCR
LCDBR
T1PD
T1TD
T2CR
T2PD
T2TD
SPIS
SPIC
SPIR
SPIW
URRD
URTD
ADCR
ADICH
ADICL
ADDH
ADDL
EIESH
EIESL
Port 8
Port 9
LCDVCR
LCDCCR
LCDSCR0
LCDSCR1
IOC8
P8PHCR
P9PHCR
PAPHCR
PBPHCR
PCPHCR
Reserve
Reserve
P8ODCR
P9ODCR
PAODCR
PBODCR
Port C
IOC9
IOCA
Port A
Port B
SCCR
TWTCR
IMR
IOCB
IOCC
LCDSCR2
Reserve
EIMR
Reserve
Reserve
Reserve
Reserve
Reserve
WKCR
Reserve
ISR
EISR
R10
‧
‧
Bank 1
.
.
.
.
.
.
Bank 7
R1F
R20
R20
General Purpose RAM
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
‧
R3F
R3F
Figure 6-1 Data Memory Configuration
6.2 Register Operations
6.2.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer.
Any instruction using R0 as register actually accesses data pointed by the RAM Select
Register (R4).
6.2.2 R1 (TCC)
R1 is incremented by the main oscillator clock (Fm) or sub oscillator clock (Fs)
(controlled by TWTCR register). It is written and read by the program as any other
register.
10
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.3 R2 (Program Counter)
The structure is depicted in Figure 6-2. Generates 8K13 on-chip ROM addresses to
the relative programming instruction codes.
"JMP" instruction allows the direct loading of the low 10 program counter bits.
"CALL" instruction loads the low 10 bits of the PC and PC+1, and push onto the stack.
"RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the
top of the stack level.
"MOV R2, A" allows the loading of an address from the A register to the PC, and
contents of the ninth and tenth bits remain unchanged.
"ADD R2, A" allows a relative address to be added to the current PC, and the contents
of the ninth and tenth bits remain unchanged.
CALL
Stack 1
PC
A12 A11 A10
A9
A8
A7 ~ A0
Stack 2
Stack 3
Stack 4
Stack 5
Stack 6
Stack 7
Stack 8
RETI
RETL
000 PAGE0 0000~03FF
001 PAGE1 0400~07FF
010 PAGE2 0800~0BFF
RETI
:
:
:
:
:
:
:
:
:
:
:
:
111 PAGE7 1000~1F FF
Figure 6-2 Program Counter Organization
User can use the Long jump (LJMP) or long call (LCALL) instructions to program user's
code. And the program page is maintained by ELAN's compiler. It will change the
user's program by inserting instructions within the program.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
11
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.4 R3 (LVD Control and Status)
Status Flag, Page Select Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LVDEN
LVDS1
LVDS0
T
P
Z
DC
C
Bit 7 (LVDEN): Voltage Detect Enable Bit
0 : No action
1 : Voltage detect enabled
Bits 6~5 (LVDS1~LVDS0): Detect Voltage Select Bits
LVDS1
LVDS0
Detect Voltage
2.4V
0
0
1
1
0
1
0
1
2.7V
3.3V
3.9V
Bit 4 (T): Time-out bit
Set to “1” by the "SLEP" and "WDTC" commands, or during power up and
reset to “0” by WDT timeout.
Bit 3 (P): Power down bit
Set to “1” during power-on or by a "WDTC" command and reset to “0” by a
"SLEP" command.
Event
T
0
0
1
1
P
0
1
0
1
Remarks
WDT wakes up from sleep mode
WDT time out (not in sleep mode)
/RESET wakes up from sleep
Power up
Low pulse on /RESET
= don't care
Bit 2 (Z): Zero flag
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
12
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.5 R4 (RAM Select Register)
Bit 7 (VDB): Voltage Detector. This is a read only bit. When VDD pin voltage is lower
then Vdet (select by LVDS0~LVDS1) this bit will be cleared.
0 : low voltage is detected
1 : low voltage is not detected or LVD function is disabled
Bit 6 (BNC): Bank Control Register
0 : allow to access only Bank 0 registers
1 : Allow to access all registers of any Bank
Bits 5~0: are used to select up to 64 registers in the indirect addressing mode.
See the the data memory configuration. User can use BANK instruction to
change bank.
6.2.6 Bank 0 R5 (RAM Bank Select Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
BS2
BS1
BS0
Bits 7~3: Reserved
Bits 2~0 (BS2~BS0): RAM Bank Select Register
BS2
BS1
BS0
RAM Bank
0
0
:
0
0
:
0
1
:
Bank 0
Bank 1
:
:
:
:
:
1
1
1
Bank 7
6.2.7 Bank 0 R7 (Port 7)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
R73
Bit 2
Bit 1
Bit 0
R77
R76
R75
R74
R72
R71
R70
Bits 7~0 (R77~R70): 8-bit I/O Registers of Port 7.
6.2.8 Bank 0 R8 (Port 8)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R87
R86
R85
R84
R83
R82
R81
0
Bits 7~1 (R87~R81): 7-bit I/O Registers of Port 8.
Bit 0: Reserved
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
13
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.9 Bank 0 R9 (Port 9)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R97
R96
R95
R94
R93
R92
R91
R90
Bits 7~0 (R97~R90): Port 9 8-bit I/O Registers.
6.2.10 Bank 0 RA (Port A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
Bits 7~0 (RA7~RA0): Port A 8-bit I/O Registers
6.2.11 Bank 0 RB (Port B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
Bits 7~0 (RB7~RB0): Port B 8-bit I/O Registers
6.2.12 Bank 0 RC SCCR (System Clock Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
CLK2
CLK1
CLK0
IDLE
0
0
CPUS
Bit 7: Reserved, fixed to “0”
Bits 6~4 (CLK2~CLK0): Main Clock Select Bit for PLL Mode (code option select)
CLK2
CLK1
CLK0
Main Clock
Reserved
Reserved
Fs488
Example Fs = 32.768kHz
0
1
1
X
0
1
X
X
X
-
-
15.99 MHz
Bit 3 (IDLE): Idle Mode Enable Bit. This bit will determine as to which mode to
activate after SLEP instruction.
IDLE=”0”+SLEP instruction sleep mode
IDLE=”1”+SLEP instruction idle mode
Bits 2~1: Reserved, fixed to “0”
Bit 0 (CPUS): CPU Oscillator Source Select
0 : sub-oscillator (fs)
1 : main oscillator (fosc)
When CPUS=0, the CPU oscillator selects the sub-oscillator and the main
oscillator is stopped.
14
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
CPU Operation Mode
Code option
HLFS=1
RESET
Normal mode
Fm: oscillation
Fs: oscillation
CPU: using Fm
Code option
HLFS=0
Wake-up
Interrupt or
wake-up
CPUS=0
IDLE=0
+ SLEP
CPUS=1
IDLE=1
+ SLEP
IDLE=1
+ SLEP
Wake-up
Sleep mode
Fm: stop
Fs: stop
Green mode
Fm: stop
Idle mode
Fm: stop
Fs: oscillation
CPU: stop
Fs: oscillation
CPU: using Fs
CPU: stop
IDLE=0
+ SLEP
Interrupt or
wake-up
Figure 6-3 CPU Operation Mode
6.2.13 Bank 0 RD TWTCR (TCC and WDT Timer Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
WPSR2
WPSR1
WPSR0
TCCS
TPSR2
TPSR1
TPSR0
Bit 7 (WDTE): Watchdog Timer Enable. This control bit is used to enable the watchdog
timer.
0 : Disable WDT function
1 : Enable WDT function
Bits 6~4 (WPSR2~WPSR0): WDT Prescaler Bits
WPSR2
WPSR1
WPSR0
Prescaler
1:1 (Default)
1 : 2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit 3 (TCCS): TCC Clock Source Select Bit
0 : Fm (main clock)
1 : Fs (sub clock: 32.768kHz)
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
15
EM78P520N
8-Bit Microprocessor with OTP ROM
Bits 2~0 (TPSR2~TPSR0): TCC Prescaler Bits
TPSR2
TPSR1
TPSR0
Prescaler
1:2 (Default)
1 : 4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
6.2.14 Bank 0 RE IMR (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1IE
LVDIE
ADIE
SPIIE
URTIE
EXIE9
EXIE8
TCIE
Bits 7~0 (T1IE~TCIE): Interrupt Enable Bit. Enable the interrupt source.
0 : Disable interrupt
1 : Enable interrupt
External Interrupt
Secondary
Function Pin
Digital Noise
Reject
INT Pin
Enable Condition
Edge
INT8
INT9
P82, AD8
ENI+EXIE8 (IMR1)
ENI+EXIE9 (IMR2)
Rising or Falling
Rising or Falling
2/Fc
2/Fc
P83, COM7, AD7
INT8~INT9: Pulse less than 2/Fc is eliminated as noise. Pulse more than 4/Fc is
treated as a trigger signal.
6.2.15 Bank 0 RF ISR (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1IF
LVDIF
ADIF
SPIIF
URTIF
EXIF9
EXIF8
TCIF
These bits are set to “1” when interrupt occurs.
Bit 7 (T1IF): Interrupt Flag of Timer 1 Interrupt
Bit 6 (LVDIF): Interrupt Flag of Low Voltage Detector Interrupt
Bit 5 (ADIF): Interrupt Flag of A/D Conversion Completed
Bit 4 (SPIIF): Interrupt Flag of SPI Transfer Completed
Bit 3 (URTIF): Interrupt Flag of UART Transfer Completed
Bit 2 (EXIF9): Interrupt Flag of External Interrupt 9 occurs
Bit 1 (EXIF8): Interrupt Flag of External Interrupt 8 occurs
Bit 0 (TCIF): Interrupt Flag of TCC overflow
16
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.16 Bank 1 R5 LCDCR (LCD Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCDEN LCDTYPE
BS1
BS0
DS1
DS0
LCDF1
LCDF0
Bit 7 (LCDEN): LCD Enable Select Bit
0 : LCD disabled. All common/segment outputs are set to VDD level.
1 : LCD enabled
Bit 6 (LCDTYPE): LCD Drive Waveform Type Select Bit
0 : A type wave
1 : B type wave
Bits 5~4 (BS1~BS0): LCD Bias Select Bits
BS1
BS0
LCD Bias Select
1/2 Bias
0
0
1
0
1
1/3 Bias
1/4 Bias
Bits 3~2 (DS1~DS0): LCD Duty Select Bits
DS1
DS0
LCD Duty
Static
0
0
1
1
0
1
0
1
1/3 Duty
1/4 Duty
1/8 Duty
Bits 1~0 (LCDF1~LCDF0): LCD Frame Frequency Control Bits
LCD Frame Frequency (e.q. Fs=32.768K)
LCDF1 LCDF0
Static
Fs/(5121) = 64.0 Fs/(1723) =63.5 Fs/(1284) = 64
Fs/(5601) = 58.5 Fs/(1883) = 58
Fs/(6081) = 53.9 Fs/(2043) = 53.5 Fs/(1524) = 53.9 Fs/(768) = 53.9
Fs/(4641) = 70.6 Fs/(1563) = 70 Fs/(1164) = 70.6 Fs/(588) = 70.6
1/3 Duty
1/4 Duty
1/8 Duty
0
0
1
1
0
1
0
1
Fs/(648) = 64.0
Fs/(1404) = 58.5 Fs/(708) = 58.5
6.2.17 Bank 1 R6 LCDAR (LCD Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
Bits 7~5: Reserved
Bits 4~0 (LCD_A4~LCD_A0): LCD RAM Address
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
17
EM78P520N
8-Bit Microprocessor with OTP ROM
R7 (LCD Data Buffer)
Bit 4 Bit 3
(LCD_D7) (LCD_D6) (LCD_D5) (LCD_D4) (LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
R6
Segment
(LCD
Address)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
00H
01H
02H
|
SEG0
SEG1
SEG2
|
14H
15H
16H
SEG20
SEG21
SEG22
Common COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
6.2.18 Bank 1 R7 LCDBR (LCD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0
Bits 7~0 (LCD_D7~LCD_D0): LCD RAM Data Transfer Register
6.2.19 Bank 1 R8 LCDVCR (LCD Voltage Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
LCDC1
LCDC0
LCDVC2 LCDVC1 LCDVC0
Bits 7~5: Reserved
Bits 4~3 (LCDC1~LCDC0): LCD Clock
LCDC1
LCDC0
Fm
FLCD
Fc/29
Fc/28
Fc/27
Fc/26
0
0
1
1
0
1
0
1
16M
8M
4M
2M
When the main oscillator operates in crystal mode and the sub-oscillator does
not, it is a must to set these two bits for the LCD clock.
18
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Bits 2~0 (LCDVC2~LCDVC0): LCD Voltage Control Bits
LCDVC2
LCDVC1
LCDVC0
Output
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.4VDD ~ VDD
0.34VDD ~ VDD
0.26VDD ~ VDD
0.18VDD ~ VDD
0.13VDD ~ VDD
0.07VDD ~ VDD
0.04VDD ~ VDD
0V ~ VDD
6.2.20 Bank 1 R9 LCDCCR (LCD COM Control Register 3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Bits 7~0 (COM7~COM0): LCD Com 7~0 Control Bits
0 : Disable, functions as normal I/O or other functions
1 : Enable, functions as LCD common driver pins
6.2.21 Bank 1 RA LCDSCR0 (LCD Segment Control Register 0)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
Bits 7~0 (SEG7~SEG0): LCD Segments 7~0 Control Bits
0 : Disable, functions as normal I/O or other functions
1 : Enable, functions as LCD common driver pins
6.2.22 Bank 1 RB LCDSCR1 (LCD Segment Control Register 1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
Bits 7~0 (SEG15~SEG8): LCD Segments 15~8 Control Bits
0 : Disable, functions as normal I/O or other functions
1 : Enable, functions as LCD common driver pins
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
19
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.23 Bank 1 RC LCDSCR2 (LCD Segment Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
Bit 7: Reserved
Bits 6~0 (SEG22~SEG16): LCD Segment 22~16 Control Bits
0 : Disable, functions as normal I/O or other functions
1 : Enable, functions as LCD common driver pins
6.2.24 Bank 1 RE EIMR (External Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXIE7
EXIE6
EXIE5
EXIE4
EXIE3
EXIE2
EXIE1
EXIE0
Bits 7~0 (EXIE7~EXIE0): Interrupt Enable Bit. Enable interrupt source respectively.
External interrupt
INT Pin Secondary Function Pin
Digital Noise
Enable Condition
Edge
Reject
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
PB3, SEG11
ENI+EXIE7 (EIMR7)
ENI+EXIE6 (EIMR6)
ENI+EXIE5 (EIMR5)
ENI+EXIE4 (EIMR4)
ENI+EXIE3 (EIMR3)
ENI+EXIE2 (EIMR2)
ENI+EXIE1 (EIMR1)
ENI+EXIE0 (EIMR0)
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
PB2, SEG10, AD11
PB1, SEG9, AD10
PB0, SEG8, AD9
P77, T1CAP
P76, T1CK
P75, T1OUT, PWM1
P74, SEG18
INT7~INT0: Pulse less than 2/Fc is eliminated as noise. Pulse more than 4/Fc is
treated as a trigger signal.
6.2.25 Bank 1 RF EISR (External Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXIF7
EXIF6
EXIF5
EXIF4
EXIF3
EXIF2
EXIF1
EXIF0
These bits are set to “1” when interrupt occurs.
Bits 7~0 (EXIF7~EXIF0): Interrupt Flag when External Interrupt 7~0 occur
20
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.26 Bank 2 R5 T1CR (Timer 1 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIS1
TIS0
T1MS2
T1MS1
T1MS0
T1P2
T1P1
T1P0
Bits 7~6 (TIS1~ TIS0): Timer 1 and Timer 2 Interrupt Type Select Bits. These two bits
are used when the Timer operates in PWM mode.
TIS1
TIS0
Timer 1 and Timer 2 Interrupt Type Select
TXPD underflow
0
0
1
0
1
TXTD underflow
TXPD and TXTD underflow
Bits 5~3 (T1MS2~T1MS0): Timer 1 Operation Mode Select Bits
T1MS2
T1MS1
T1MS0
Timer 1 Mode Select
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Timer 1
T1OUT Mode
Capture Mode Rising Edge
Capture Mode Falling Edge
UART Baud Rate Generator
PWM 1
Bits 2~0 (T1P2~T1P0): Timer 1 Prescaler Bits
T1P2
T1P1
T1P0
Prescaler
1:2 (Default)
1 : 4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
21
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.27 Bank 2 R6 TSR (Timer Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1MOD
TRCB
T1CSS1 T1CSS0
T2CSS
T1S
T1OMS
T1OC
Bit 7 (T1MOD): Timer Operation Mode Select Bit
0 : Two 8-bit Timers
1 : Timer 1 and Timer 2 cascaded to one 16-bit Timer
NOTE
By setting T1MOD to “1”, Timer can cascade to one 16-bit Timer. This 16-bit Timer is
controlled by Timer 1, including enable, clock source and prescaler. Timer 1 is MSB
and Timer 2 is LSB in value of period and duty.
Bit 6 (TRCB): Timers 1, 2 Read Control Bit
0 : When this bit is set to 0, read data from T1PD or T2PD.
1 : When this bit is set to 1, read data from T1PD or T2PD, but this is a
value of the timer counter.
Bits 5~4 (T1CSS1~T1CSS0): Timer 1 Clock Source Select Bits
T1CSS1
T1CSS0
Timer 1 Clock Source Select
0
0
1
0
1
Fm
Fs
T1CK
Bit 3 (T2CSS): Timer 2 Clock Source Select Bit
0 : Main clock with prescaler
1 : Sub clock with prescaler
Bit 2 (T1S):
Timer 1 Start Bit
0 : Timer 1 stop
1 : Timer 1 start
Bit 1 (T1OMS): Timer 1 Output Mode Select Bit
0 : Repeating mode
1 : One–shot mode
NOTE
One-shot mode is only used in Timer 1, Capture and PWM1 modes.
22
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Mode Selected
Description
Down-counter will underflow once and cannot auto reload from
T1PD.
Timer 1
In this mode, period and duty of the T1CAP input pin are measured
once. This moment free running counter stop and can’t detect a
change of T1CAP edge.
Capture
PWM1
In this mode the microcontroller device will generate one set of
PWM1’s duty and period, and then free running counter will stop.
Bit 0 (T1OC): Timer 1 Output Flip-Flop Control Bit
0 : T-FF is low
1 : T-FF is high
6.2.28 Bank 2 R7 T1PD (Timer 1 Period Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0]
Bits 7~0 (PRD1 [7]~PRD1 [0]): The content of this register is a period of Timer 1.
6.2.29 Bank 2 R8 T1TD (Timer 1 Duty Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TD1[7]
TD1[6]
TD1[5]
TD1[4]
TD1[3]
TD1[2]
TD1[1]
TD1[0]
Bits 7~0 (TD1 [7]~TD1 [0]): The content of this register is a duty of Timer 1.
6.2.30 Bank 2 R9 T2CR (Timer 2 Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T2IF
T2IE
T2S
T2MS1
T2MS0
T2P2
T2P1
T2P0
Bit 7 (T2IF): Interrupt Flag of Timer 2 Interrupt
Bit 6 (T2IE): Timer 2 Interrupt Mask Bit
0 : Disable Timer 2 interrupt
1 : Enable Timer 2 interrupt
Bit 5 (T2S): Timer 2 Start Bit
0 : Timer 2 stop
1 : Timer 2 start
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
23
EM78P520N
8-Bit Microprocessor with OTP ROM
Bits 4~3 (T2MS1~T2MS0): Timer 2 Operation Mode Select Bits
T2MS1
T2MS0
Timer 2 Mode Select
0
0
1
1
0
1
0
1
Timer 2
SPI Baud Rate Generator
PWM 2
Bits 2~0 (T2P2~T2P0): Timer 2 Prescaler Bits
T2P2
T2P1
T2P0
Prescaler
1:2 (Default)
1 : 4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
6.2.31 Bank 2 RA T2PD (Timer 2 Period Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0]
Bits 7~0 (PRD2 [7]~PRD2 [0]): The content of this register is a period of Timer 2.
6.2.32 Bank 2 RB T2TD (Timer 2 Duty Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TD2[7]
TD2[6]
TD2[5]
TD2[4]
TD2[3]
TD2[2]
TD2[1]
TD2[0]
Bits 7~0 (TD2 [7]~TD2 [0]): The content of this register is a duty of Timer 2.
6.2.33 Bank 2 RC SPIS (SPI Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DORD
TD1
TD0
0
OD3
OD4
0
RBF
Bit 7 (DORD): Data Shift Control Bit
0 : Shift left (MSB first)
1 : Shift right (LSB first)
24
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Bits 6~5 (TD1~TD0): SDO Status Output Delay Times Options
TD1
0
TD0
0
Delay Time
8 CLK
0
1
16 CLK
24 CLK
32 CLK
1
0
1
1
Bit 4:
Bit 3 (OD3): Open-Drain Control Bit
0 : Open-drain disable for SDO
1 : Open-drain enable for SDO
Bit 2 (OD4): Open-Drain Control bit
Reserved
0 : Open-drain disable for SCK
1 : Open-drain enable for SCK
Bit 1:
Reserved
Bit 0 (RBF): Read Buffer Full Flag
0 : Receiving not completed, and SPIRB has not fully exchanged.
1 : Receiving completed, and SPIRB is fully exchanged.
6.2.34 Bank 2 RD SPIC (SPI Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CES
SPIE
SRO
SSE
SDOC
SBRS2
SBRS1
SBRS0
Bit 7 (CES): Clock Edge Select Bit
0 : Data shift out on rising edge, and shifts in on a falling edge. Data is on
hold during low-level.
1 : Data shift out falling edge, and shift in on a rising edge. Data is on hold
during high-level.
Bit 6 (SPIE): SPI Enable Bit
0 : Disable SPI mode
1 : Enable SPI mode
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
25
EM78P520N
8-Bit Microprocessor with OTP ROM
Bit 5 (SRO): SPI Read Overflow Bit
0 : No overflow
1 : A new data is received while the previous data is still being held in the
SPIRB register. In this situation, the data in SPIS register will be
destroyed. To avoid setting this bit, user is required to read the SPIRB
register although only transmission is implemented. This can only
occur in slave mode.
Bit 4 (SSE): SPI Shift Enable Bit
0 : Reset as soon as the shift is complete, and the next byte is read to
shift.
1 : Start to shift, and remain on “1” while the current byte is still being
transmitted.
Bit 3 (SDOC): SDO Output Status Control Bit
0 : After a serial data output, the SDO remains high.
1 : After a serial data output, the SDO remains low.
Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select Bits
SBRS2
SBRS1
SBRS0
Mode
Master
Master
Master
Master
Master
Master
Slave
SPI Baud Rate
Fosc/2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Timer 2
/SS enable
/SS disable
Slave
6.2.35 Bank 2 RE SPIR (SPI Read Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
Bits 7~0 (SRB7~SRB0): SPI Read Data Buffer
6.2.36 Bank 2 RF SPIW (SPI Write Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
Bits 7~0 (SWB7~SWB0): SPI Write Data Buffer
26
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.37 Bank 3 R5 URC (UART Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0
UTBE
TXE
Bit 7 (URTD8): Transmission Data Bit 8
Bits 6~5 (UMODE1~UMODE0): UART Transmission Mode Select Bit
UMODE1 UMODE0
UART Mode
Mode 1 : 7-Bit
Mode 2 : 8-Bit
Mode 3 : 9-Bit
Reserved
0
0
1
1
0
1
0
1
Bits 4~2 (BRATE2~BRATE0): Transmit Baud Rate Select (TUART=Fc/16)
BRATE2 BRATE1 BRATE0
Baud Rate
TUART/13
e.g. Fc = 8 MHz
38400
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TUART/26
19200
TUART/52
9600
TUART/104
TUART/208
TUART/416
4800
2400
1200
Timer 1
Reserved
Bit 1 (UTBE): UART transfer buffer empty flag. Set to 1 when transfer buffer is empty.
Reset to 0 automatically when writing to the URTD register. The UTBE
bit will be cleared by hardware when transmission is enabled. The
UTBE bit is read-only. Hence, writing to the URTD register is
necessary to start transmit shifting.
Bit 0 (TXE):
Enable transmission
0 : Disable
1 : Enable
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
27
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.38 Bank 3 R6 URS (UART Status)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD8
EVEN
PRE
PRERR
OVERR
FMERR
URBF
RXE
Bit 7 (URRD8): Receiving Data Bit 8
Bit 6 (EVEN): Select Parity Check
0 : Odd parity
1 : Even parity
Bit 5 (PRE):
Enable Parity Addition
0 : Disable
1 : Enable
Bit 4 (PRERR): Parity Error Flag
Set to “1” when parity error occurs and clear to “0” by software.
Bit 3 (OVERR): Over Running Error Flag
Set to ”1” when overrun error occurs and clear to “0” by software.
Bit 2 (FMERR): Framing Error Flag
Set to “1” when framing error occurs and clear to “0” by software.
Bit 1 (URBF): UART Read Buffer Full Flag
Set to “1” when one character is received. Reset to “0” automatically
when read from URS register. The URBF will be cleared by hardware
when enabling receiving. The URBF bit is read-only. Therefore,
reading the URS register is necessary to avoid overrun error.
Bit 0 (RXE):
Enable Receiving
0 : Disable
1 : Enable
6.2.39 Bank 3 R7 URRD (UART_RD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URRD7
URRD6
URRD5
URRD4
URRD3
URRD2
URRD1
URRD0
Bits 7~0 (URRD7~URRD0): UART Receive Data Buffer. Read only.
28
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.40 Bank 3 R8 URTD (UART_TD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
URTD7
URTD6
URTD5
URTD4
URTD3
URTD2
URTD1
URTD0
Bits 7~0 (URTD7~URTD0): UART Transmit Data Buffer. Write only.
6.2.41 Bank 3 R9 ADCR (A/D Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADRUN
ADP
ADCK1
ADCK0
ADIS3
ADIS2
ADIS1
ADIS0
Bit 7 (ADRUN): AD Conversion Start
0 : Reset on completion of the conversion by hardware, this bit cannot
be reset by software.
1 : Conversion starts
Bit 6 (ADP):
A/D Power Control
Bits 5~4 (ADCK1~ADCK0): AD Conversion Time Select Bits
ADCK1 ADCK0
Clock Source
Fc/4
Max. Operating Frequency (Fc)
0
0
1
1
0
1
0
1
1 MHz
4 MHz
8 MHz
16 MHz
Fc/16
Fc/32
Fc/64
Bits 3~0 (ADIS3~ADIS0): A/D Input Select Bits
ADIS3
ADIS2
ADIS1
ADIS0
Analog Input Pin
AD0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
29
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.42 Bank 3 RA ADICH (A/D Input Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALI
ADREF
0
0
ADE11
ADE10
ADE9
ADE8
Bit 7 (CALI): Calibration Enable Bit for A/D Offset
0 : Disable Calibration
1 : Enable Calibration
Bit 6 (ADREF): AD Reference Voltage Input Select
0 : Internal VDD, P84 is used as I/O.
1 : External reference pin, P84 is used as reference input pin.
External VREF is accuracy better than internal VDD.
Reserved
Bits 5~4:
Bits 3~0 (ADE11~ADE8): AD Input Pin Enable Control
0 : Functions as I/O pin
1 : Functions as analog input pin
6.2.43 Bank 3 RB ADICL (A/D Input Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Bits 7~0 (ADE7~ADE0): AD input pin enable control
0 : Functions as I/O pin
1 : Functions as analog input pin
6.2.44 Bank 3 RC ADDH (AD High 8-bit Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADD11
ADD10
ADD9
ADD8
ADD7
ADD6
ADD5
ADD4
Bits 7~0 (ADD11~ADD4): AD High 8-Bit Data Buffer
6.2.45 Bank 3 RD ADDL (AD Low 4-bit Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIGN
VOF[2]
VOF[1]
VOF[0]
ADD3
ADD2
ADD1
ADD0
Bit 7 (SIGN): Polarity Bit of Offset Voltage
0 : Negative voltage
1 : Positive voltage
30
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Bits 6~4 (VOF[2]~VOF[0]): Offset Voltage Bits
VOF[2]
VOF[1]
VOF[0]
EM78P520N
0LSB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2LSB
4LSB
6LSB
8LSB
10LSB
12LSB
14LSB
Bits 3~0 (ADD3~ADD0): AD Low 4-Bit Data Buffer
6.2.46 Bank 3 RE EIESH (External Interrupt Edge Select High Byte
Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EIES7
EIES6
EIES5
EIES4
EIES3
EIES2
EIES1
EIES0
Bits 7~0 (EIES7~EIES0): External Interrupt 7~0 Edge Select Bit
0 : Falling edge interrupt
1 : Rising edge interrupt
6.2.47 Bank 3 RF EIESL (External Interrupt Edge Select Low Byte
Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
ADWK
INTWK9 INTWK8
EIES9
EIES8
Bits 7~5:
Reserved
Bit 4 (ADWK): A/D Converter Wake-up Function Enable Bit
0 : Disable
1 : Enable
Bits 3~2 (INTWK9~INTWK8): External Interrupt 9~8 Wake-up Function Enable Bit
0 : Disable
1 : Enable
Bits 1~0 (EIES9~EIES8): External Interrupt 9~8 Edge Select Bit
0 : Falling edge interrupt
1 : Rising edge interrupt
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
31
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.48 Bank 4 R5 LEDDCR (LED Drive Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LEDD7
LEDD6
LEDD5
LEDD4
LEDD3
LEDD2
LEDD1
LEDD0
Bits 7~0 (LEDD7~LEDD0): 8-bit LED Drive Control Registers
0 : Port 9 functions as normal I/O
1 : Port 9 functions as LED direct drive I/O
6.2.49 Bank 4 R6 WBCR (Watch Timer and Buzzer Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WTCS
WTIE
WTIF
WTSSB1 WTSSB0
BUZE
BSSB1
BSSB0
Bit 7 (WTCS): Watch Timer and Buzzer Clock Source Select Bit
0 : Main Clock divided by 256
1 : Sub clock
Bit 6 (WTIE): Watch Timer Enable Bit and Interrupt Mask
0 : Disable
1 : Enable
Bit 5 (WTIF): Watch Timer Interrupt Flag
Bits 4~3 (WTSSB1~ WTSSB0): Watch Timer Interval Select Bits
Timer Interval Select
WTSSB1 WTSSB0
Fm=8 MHz (WTCS=0)
(WTCS=1)
0
0
1
1
0
1
0
1
1.0S
1.0S
0.5S
0.5S
0.25S
0.25S
3.91ms
3.91ms
Bit 2 (BUZE): Buzzer Enable and Port 91 as Buzzer Output Pin
0 : No action
1 : Enable buzzer output
Bits 1~0 (BSSB1~BSSB0): Buzzer Output Frequency Select Bits
Buzzer Signal Select
BSSB1
BSSB0
Fm=8 MHz (WTCS=0)
(WTCS=1)
0.5kHz
1kHz
0
0
1
1
0
1
0
1
0.5kHz
1kHz
2kHz
4kHz
2kHz
4kHz
32
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.50 Bank 4 R7 P7IOCR (Port 7 I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOC77
IOC76
IOC75
IOC74
IOC73
IOC72
IOC71
IOC70
Bits 7~0 (IOC77~IOC70): Port 7 8-Bit I/O Direction Control Registers
0 : Define Port 7 as output port
1 : Define Port 7 as input port
6.2.51 Bank 4 R8 P8IOCR (Port 8 I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOC87
IOC86
IOC85
IOC84
IOC83
IOC82
IOC81
0
Bits 7~1 (IOC87~IOC81): Port 8 7-Bit I/O Direction Control Registers
0 : Define Port 8 as output port
1 : Define Port 8 as input port
Bit 0: Reserved
6.2.52 Bank 4 R9 P9IOCR (Port 9 I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOC97
IOC96
IOC95
IOC94
IOC93
IOC92
IOC91
IOC90
Bits 7~0 (IOC97~IOC90): Port 9 8-Bit I/O Direction Control Registers
0 : Define Port 9 as output port
1 : Define Port 9 as input port
6.2.53 Bank 4 RA PAIOCR (Port A I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOCA7
IOCA6
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
Bits 7~0 (IOCA7~IOCA0): Port A 8-Bit I/O Direction Control Registers
0 : Define Port A as output port
1 : Define Port A as input port
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
33
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.54 Bank 4 RB PBIOCR (Port B I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
Bits 7~0 (IOCB7~IOCB0): Port B 8-Bit I/O Direction Control Registers
0 : Define Port B as output port
1 : Define Port B as input port
6.2.55 Bank 4 RC PCIOCR (Port C I/O Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
IOCC3
IOCC2
IOCC1
IOCC0
Bits 7~4: Reserved
Bits 3~0 (IOCC3~IOCC0): Port C 4-Bit I/O Direction Control Registers
0 : Define Port C as output port
1 : Define Port C as input port
6.2.56 Bank 4 RF WKCR (Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTWK7 INTWK6 INTWK5 INTWK4 INTWK3 INTWK2 INTWK1 INTWK0
Bits 7~0 (INTWK7~INTWK0): External Interrupt 7~0 Wake-up Function Enable Bit
0 : Disable
1 : Enable
6.2.57 Bank 5 R6 UARC2 (UART Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
UARTE
0
UINVEN
0
0
0
Bits 7~6: Reserved
Bit 5 (UARTE): UART Function Enable
0 : UART functions disable. PB4, PB5 as general I/O
1 : UART functions enable. PB4, PB5 as UART Rx, Tx pin
Bit 4: Reserved
Bit 3 (UINVEN): Enable UART TX and Rx Port Inverse Output
0 : Disable Tx and Rx port inverse output
1 : Enable Tx and Rx port inverse output
Bits 2~0: Reserved
34
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.58 Bank 5 R7 P7PHCR (Port 7 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH77
PH76
PH75
PH74
PH73
PH72
PH71
PH70
Bits 7~0 (PH77~PH70): Port 7 8-Bit I/O Pull High Control Registers
0 : Disable Pull-high
1 : Enable Pull-high
6.2.59 Bank 5 R8 P8PHCR (Port 8 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH87
PH86
PH85
PH84
PH83
PH82
PH81
0
Bits 7~1 (PH87~PH81): PORT 8 7-Bit I/O Pull High Control Registers
0 : Disable Pull-high
1 : Enable Pull-high
Bit 0: Reserved
6.2.60 Bank 5 R9 P9PHCR (Port 9 Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PH97
PH96
PH95
PH94
PH93
PH92
PH91
PH90
Bits 7~0 (PH97~PH90): Port 9 8-bit I/O Pull-high Control Registers
0 : Disable Pull-high
1 : Enable Pull-high
6.2.61 Bank 5 RA PAPHCR (Port A Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PHA7
PHA6
PHA5
PHA4
PHA3
PHA2
PHA1
PHA0
Bits 7~0 (PHA7~PHA0): Port A 8-bit I/O Pull-high Control Registers
0 : Disable Pull-high
1 : Enable Pull-high
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
35
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.62 Bank 5 RB PBPHCR (Port B Pull-high Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PHB7
PHB6
PHB5
PHB4
PHB3
PHB2
PHB1
PHB0
Bits 7~0 (PHB7~PHB0): Port B 8-Bit I/O Pull-high Control Registers
0 : Disable Pull-high
1 : Enable Pull-high
6.2.63 Bank 5 RC PCPHCR (Port C Pull High Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
PHC3
PHC2
PHC1
PHC0
Bits 7~4: Reserved
Bits 3~0 (PHC3~PHC0): Port C 4-Bit I/O Pull-high Control Registers
0 : Disable Pull-high
1 : Enable Pull-high
6.2.64 Bank 6 R6 LVRCR (Low Voltage Reset Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
LVREN
LVRS1
LVRS0
R6 uses only ICE520 simulator.
Bits 7~3: Reserved
Bit 2 (LVREN): Low Voltage Reset Enable Bit
0 : Disable
1 : Enable
Bits 1~0 (LVRS1~LVRS0): Low Voltage Reset Voltage Select Bits
LVRS1
LVRS0
Reset Voltage
2.6V
0
0
1
0
1
0
3.3V
3.9V
6.2.65 Bank 6 R7 P7ODCR (Port 7 Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD77
OD76
OD75
OD74
OD73
OD72
OD71
OD70
Bits 7~0 (OD77~OD70): Port 7 8-Bit I/O Open Drain Control Registers
0 : Disable Open drain
1 : Enable Open drain
36
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.2.66 Bank 6 R8 P8ODCR (Port 8 Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD87
OD86
OD85
OD84
OD83
OD82
OD81
0
Bits 7~1 (OD87~OD80): Port 8 7-bit I/O Open Drain Control Registers
0 : Disable Open drain
1 : Enable Open drain
Bit 0: Reserved
6.2.67 Bank 6 R9 P9ODCR (Port 9 Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OD97
OD96
OD95
OD94
OD93
OD92
OD91
OD90
Bits 7~0 (OD97~OD90): Port 9 8-Bit I/O Open Drain Control Registers
0 : Disable Open drain
1 : Enable Open drain
6.2.68 Bank 6 RA PAODCR (Port A Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ODA7
ODA6
ODA5
ODA4
ODA3
ODA2
ODA1
ODA0
Bits 7~0 (ODA7~ODA0): Port A 8-Bit I/O Open Drain Control Registers
0 : Disable Open drain
1 : Enable Open drain
6.2.69 Bank 6 RB PBODCR (Port B Open Drain Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
Bits 7~0 (ODB7~ODB0): Port B 8-Bit I/O Open Drain Control Registers
0 : Disable Open drain
1 : Enable Open drain
6.2.70 Bank 6 RC (Port C)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
RC3
RC2
RC1
RC0
Bits 7~4: Reserved
Bits 3~0 (RC3~RC0): Port C 4-Bit I/O Registers
6.2.71 R10~R3F (General Purpose Register)
R10~R1F and R20~R3F (Banks 0~7) are general purpose registers.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
37
EM78P520N
8-Bit Microprocessor with OTP ROM
6.3 TCC/WDT Prescaler
Registers for the TCC/WDT Circuit
R_BANK Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WDTE WPSR2 WPSR1 WPSR0 TCCS TPSR2 TPSR1 TPSR0
Bank 0
Bank 0
Bank 0
0X0D
0x0E
0x0F
TWTCR
R/W
T1IE LVDIE ADIE SPIIE URTIE EXIE9 EXIE8 TCIE
R/W R/W R/W R/W R/W R/W R/W R/W
T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IMR
ISR
There are two 8-bit counters available as prescalers for the TCC and WDT, respectively.
The TPSR0~TPSR2 bits of the Bank 0 RD (TWTCR) register are used to determine the
ratio of the TCC prescaler. Likewise, the WPSR0~WPSR2 bits of the Bank 0 RD
(TWTCR) register are used to determine the WDT prescaler. The prescaler counter will
be cleared by the instructions each time they are written into TCC. The WDT and
prescaler will be cleared by the “WDTC” and “SLEP” instructions. Figure 6-4 depicts the
circuit diagram of TCC/WDT.
R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be internal clock main
clock or sub clock (32.768kHz). If TCC signal source is from the internal clock, TCC will
be incremented by 1 at every instruction cycle (without prescaler). As illustrated in
Figure 6-4. The watchdog timer is a free running on-chip RC oscillator. The WDT will
continue running even after the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled at any time during the normal
mode by software programming. Refer to WDTE bit of Bank 0 RD (TWTCR) register.
With no prescaler, the WDT time-out period is approximately 18 ms1.
1 Note: VDD=5V, Setup time period = 16.5ms ± 30%
VDD=3V, Setup time period = 18ms ± 30%
Setup time form the WDT.
38
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Figure 6-4 TCC/WDT Block Diagram
6.4 I/O Port
Registers for I/O Circuit
R_BANK Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
Bank 4 0X07~0X0C PIOCR
R/W
PH7
R/W
R/W
PH6
R/W
R/W
PH5
R/W
R/W
PH4
R/W
R/W
PH3
R/W
R/W
PH2
R/W
R/W
PH1
R/W
R/W
PH0
R/W
Bank 5 0X07~0X0C PHCR
Bank 6 0X07~0X0B ODCR
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
R/W R/W R/W R/W R/W R/W R/W R/W
The I/O registers, (Port 7, Port 8, Port 9, Port A, Port B and Port C), are bidirectional
tri-state I/O ports. All pins are pulled-high internally by software. Likewise, Port 7,
Port 8, Port 9, Port A, Port B and Port C, can also have open-drain output through
software. Port 7 [7:4], Port B [3:0] and Port 8 [3:2] provides an input status changed
interrupt (or wake-up) function and is pulled-high by software. Each I/O pin can be
defined as "input" or "output" pin by the I/O control register Bank 4 R7 ~ RC. The I/O
registers and I/O control registers are both readable and writeable. The I/O interface
circuits are shown in Figure 6-5.
The I/O cannot be set to pull-high and output low at the same time. It can relatively
increase the power consumption.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
39
EM78P520N
8-Bit Microprocessor with OTP ROM
Note: Open-drain is not shown in the figure.
Figure 6-5 Circuits of I/O Port and I/O Control Register for Ports 7~9, and Ports A~C
6.5 Reset and Wake-up
A reset can be caused by:
Power-on reset
WDT timeout (if enabled)
LVR Reset (if enabled)
RESET pin pulling low
NOTE
The power-on reset circuit is always enabled, it will reset the CPU at 2.3V and power
consumption is 0.5 µA.
Once a reset occurs, the following functions are performed:
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The TCC/Watchdog timer and prescaler are cleared.
When power is on, all bits of R5 and R6 are cleared.
The other registers are described in Table 2
40
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Table 2 Summary of the Registers Initial Values
Address Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Power-on
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
R0
000
/RESET and WDT
IAR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1
001
/RESET and WDT
TCC
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R2
002
/RESET and WDT
PC
Wake-up from Sleep and
Idle mode
Continue to execute next instruction
Bit Name
Power-on
LVDEN LVDS1 LVDS0
T
1
t
P
1
t
Z
U
P
DC
U
C
U
P
R3
0
0
0
0
0
0
003
004
005
007
008
LVD & /RESET and WDT
P
SR
Wake-up from Sleep and
Idle mode
P
P
P
t
t
P
P
P
Bit Name
VDB
BNC
X
U
P
X
U
P
X
U
P
X
U
P
X
U
P
X
U
P
Power-on
1
1
1
1
R4
/RESET and WDT
RSR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BS2
0
BS1
0
BS0
0
Bank 0
R5
Power-on
/RESET and WDT
0
0
0
Wake-up from Sleep and
Idle mode
RBSR
P
P
P
P
P
P
P
P
Bit Name
R77
1
R76
1
R75
1
R74
1
R73
1
R62
1
R71
1
R70
1
Bank 0
R7
Power-on
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-up from Sleep and
Idle mode
Port 7
P
P
P
P
P
P
P
P
Bit Name
R87
1
R86
1
R85
1
R84
1
R83
1
R82
1
R81
1
0
0
0
Bank 0
R8
Power-on
/RESET and WDT
1
1
1
1
1
1
1
Wake-up from Sleep and
Idle mode
Port 8
P
P
P
P
P
P
P
0
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
41
EM78P520N
8-Bit Microprocessor with OTP ROM
Address Name
Reset Type
Bit Name
Bit 7
R97
1
Bit 6
R96
1
Bit 5
R95
1
Bit 4
R94
1
Bit 3
R93
1
Bit 2
R92
1
Bit 1
R91
1
Bit 0
R90
1
Bank 0
Power-on
R9
009
00A
00B
00C
00D
00E
00F
005
006
/RESET and WDT
1
1
1
1
1
1
1
1
Port 9
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
RA7
1
RA6
1
RA5
1
RA4
1
RA3
1
RA2
1
RA1
1
RA0
1
Bank 0
RA
Power-on
/RESET and WDT
1
1
1
1
1
1
1
1
Port A
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
RB7
1
RB6
1
RB5
1
RB4
1
RB3
1
RB2
1
RB1
1
RB0
1
Bank 0
RB
Power-on
/RESET and WDT
1
1
1
1
1
1
1
1
Port B
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
CLK2 CKL1 CLK0 IDLE
0
0
0
0
0
0
CPUS
Bank 0
RC
Power-on
0
0
0
0
0
0
1
1
1
1
/RESET and WDT
SCCR
Wake-up from Sleepand
Idlemode
P
P
P
P
P
P
P
P
Bit Name
WDTE WPSR2 WPSR1 WPSR0 TCCS TPSR2 TPSR1 TPSR0
Bank 0
RD
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
TWTCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
T1IE LVDIE ADIE SPIIE URTIE EXIE9 EXIE8 TCIE
Bank 0
RE
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
IMR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF
Bank 0
RF
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
ISR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
LCDEN LCDPYTE BS1
BS0
0
DS1
0
DS0 LCDF1 LCDF0
Bank 1
R5
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
LCDCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
Bank 1
R6
Power-on
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
LCDAR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
42
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Address Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0
Bank 1
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R7
007
/RESET and WDT
LCDBR
Bank 1
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
LCDC1 LCDC0 LCDVC2 LCDVC1 LCDVC0
Power-on
1
1
1
1
1
1
1
1
1
1
R8
008
009
00A
00B
00C
00E
00F
005
/RESET and WDT
(LCDVCR)
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
Bank 1
R9
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
LCDCCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
Bank 1
RA
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
(LCDSCR0)
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8
Bank 1
RB
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
LCDSCR1
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16
Bank 1
RC
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
LCDSCR
2
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
EXIE7 EXIE6 EXIE5 EXIE4 EXIE3 EXIE2 EXIE1 EXIE0
Bank 1
RE
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
EIMR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
EXIF7 EXIF6 EXIF5 EXIF4 EXIF3 EXIF2 EXIF1 EXIF0
Bank 1
RF
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
EISR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
TIS1
TIS0 T1MS2 T1MS1 TIMS0 T1P2 T1P1 T1P0
Bank 2
R5
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
T1CR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
43
EM78P520N
8-Bit Microprocessor with OTP ROM
Address Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
T1MOD TCRB T1CSS1 T1CSS0 T2CSS T1S T1OMS T1OC
Bank 2
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R6
006
007
008
009
00A
00B
00C
00D
00E
/RESET and WDT
TSR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0]
Bank 2
R7
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
T1PD
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
TD1[7] TD1[6] TD1[5] TD1[4] TD1[3] TD1[2] TD1[1] TD1[0]
Bank 2
R8
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
T1TD
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
T2IF
T2IE
T2S
0
T2MS1 T2MS0 T2P2 T2P1 T2P0
Bank 2
R9
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
0
T2CR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0]
Bank 2
RA
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
T2PD
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
TD2[7] TD2[6] TD2[5] TD2[4] TD2[3] TD2[2] TD2[1] TD2[0]
Bank 2
RB
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
T2TD
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
DORD TD1
TD0
0
0
0
0
OD3
OD4
0
0
0
RBF
Bank 2
RC
Power-on
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
0
SPIS
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
CES
SPIE
SRO
SSE SDOC SBRS2 SBRS1 SBRS0
Bank 2
RD
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
SPIC
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
Bank 2
RE
Power-on
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
/RESET and WDT
SPIR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
44
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Address Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
Bank 2
Power-on
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
RF
00F
005
006
007
008
009
00A
00B
00C
/RESET and WDT
SPIW
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE
TXE
0
Bank 3
R5
Power-on
U
P
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
0
URC
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
URRD8 EVEN
PRE PRERR OVERR FMERR URBF RXE
Bank 3
R6
Power-on
U
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
URS
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0
Bank 3
R7
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
P
P
P
P
P
P
P
P
URRD
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
URTD7 URTD6 URTD5 URTD4 URTD3 URTD2 URTD1 URTD0
Bank 3
R8
Power-on
0
0
0
0
0
0
0
0
/RESET and WDT
P
P
P
P
P
P
P
P
(URTD)
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
ADRUN ADP ADCK1 ADCK0 ADIS3 ADIS2 ADIS1 ADIS0
Bank 3
R9
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
ADCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
CALI ADREF
0
0
0
0
0
0
ADE11 ADE10 ADE9 ADE8
Bank 3
RA
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
ADICH
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Bank 3
RB
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
(ADICL)
Wake-upfromSleepand
Idlemode
P
P
P
P
P
P
P
P
Bit Name
ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4
Bank 3
RC
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
ADDH
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
45
EM78P520N
8-Bit Microprocessor with OTP ROM
Address Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIGN VOF[2] VOF[1] VOF[0] ADD3 ADD2 ADD1 ADD0
Bank 3
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RD
00D
00E
/RESET and WDT
ADDL
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
EIES7 EIES6 EIES5 EIES4 EIES3 EIES2 EIES1 EIES0
Bank 3
RE
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
EIESH
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
0
0
0
ADWK INTWK9 INTWK8 EIES9 EIES8
Bank 3
RF
Power-on
0
0
0
0
0
0
0
0
0
0
00F
/RESET and WDT
EIESL
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
LEDD7 LEDD6 LEDD5 LEDD4 LEDD3 LEDD2 LEDD1 LEDD0
Bank 4
R5
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
005
006
007
008
009
00A
/RESET and WDT
LEDDCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
WTCS WTIE WTIF WTSSB1 WTSSB0 BUZE BSSB1 BSSB0
Bank 4
R6
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
WBCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 IOC71 IOC70
Bank 4
R7
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
P7IOCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 IOC81
0
0
0
Bank 4
R8
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
P8IOCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 IOC91 IOC90
Bank 4
R9
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
P9IOCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0
Bank 4
RA
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
PAIOCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
46
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Address Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0
Bank 4
Power-on
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RB
00B
00C
00F
006
007
008
009
00A
00B
/RESET and WDT
PBIOCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
1
1
1
1
1
1
1
1
1
1
1
1
IOCC3 IOCC2 IOCC1 IOCC0
Bank 4
RC
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
PCIOCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
INTWK7 INTWK6 INTWK5 INTWK4 INTWK3 INTWK2 INTWK1 INTWK0
Bank 4
RF
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
WKCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
0
0
0
0
0
0
UARTE
0
0
0
UINVEN
0
0
0
0
0
0
0
0
0
Bank 5
R6
Power-on
0
0
0
0
/RESET and WDT
UARC2
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
PH77 PH76 PH75 PH74 PH73 PH72 PH71 PH70
Bank 5
R7
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
P7PHCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
PH87 PH86 PH85 PH84 PH83 PH82 PH81
0
0
0
Bank 5
R8
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
P8PHCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
PH97 PH96 PH95 PH94 PH93 PH92 PH91 PH90
Bank 5
R9
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
P9PHCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
PHA7 PHA6 PHA5 PHA4 PHA3 PHA2 PHA1 PHA0
Bank 5
RA
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
PAPHCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
PHB7 PHB6 PHB5 PHB4 PHB3 PHB2 PHB1 PHB0
Bank 5
RB
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
PBPHCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
47
EM78P520N
8-Bit Microprocessor with OTP ROM
Address Name
Reset Type
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
PHC3 PHC2 PHC1 PHC0
Bank 5
Power-on
0
0
0
0
0
0
0
0
RC
00C
/RESET and WDT
PCPHCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
OD77 OD76 OD75 OD74 OD73 OD72 OD71 OD70
Bank 6
R7
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
007
008
009
00A
00B
00C
/RESET and WDT
P7ODCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
OD87 OD86 OD85 OD84 OD83 OD82 OD81
0
0
0
Bank 6
R8
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
P8ODCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
OD97 OD96 OD95 OD94 OD93 OD92 OD91 OD90
Bank 6
R9
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
P9ODCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0
Bank 6
RA
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
PAODCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0
Bank 6
RB
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/RESET and WDT
PBODCR
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
1
1
1
1
1
1
1
1
1
1
1
1
RC3
RC2
RC1
RC0
Bank 6
RC
Power-on
1
1
1
1
1
1
1
1
/RESET and WDT
Port C
Wake-up from Sleep and
Idle mode
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Bank 0
~
Power-on
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
010
~
/RESET and WDT
Bank 7
03F
Wake-up from Sleep and
Idle mode
R10~R3F
P
P
P
P
P
P
P
P
Legend: “” = not used
“u” = unknown or don’t care
“P” = previous value before Wake-up or reset
48
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
The controller can be awakened from sleep mode and idle mode. The wake-up signals list as
following.
Wake-up Signal
Sleep Mode
Idle Mode
Wake-up
Green Mode Normal Mode
TCC time out
+ interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
+ next instruction
Wake-up
Wake-up
INT pin
Timer 1
Timer 2
UART
SPI
+ interrupt (if enabled) + interrupt(if enabled)
+ next instruction
+ next instruction
Wake-up
+ interrupt
+ next instruction
Wake-up
+ interrupt
+ next instruction
Wake-up
+ interrupt
+ next instruction
Wake-up
+ interrupt
+ next instruction
Wake-up
LVD
+ interrupt
+ next instruction
Wake-up
Wake-up
+ interrupt (if interrupt
is enabled)
A/D
+ interrupt(if enabled)
+ next instruction
Interrupt
Interrupt
+ next instruction
Wake-up
Watch Timer
WDT time out
+ interrupt
Interrupt
RESET
Interrupt
RESET
+ next instruction
RESET
RESET
Note: User must set the wake-up register (Bank 3 RF (EIESL) Bits 2~4 and Bank 4 RF(WKCR)
Bits 0~7. Wake up from INT pin or A/D in sleep and idle mode
After wake up:
1. If interrupt is enabled → interrupt + next instruction
2. If interrupt is disabled → next instruction
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
49
EM78P520N
8-Bit Microprocessor with OTP ROM
6.6 Oscillator
6.6.1 Oscillator Modes
The EM78P520N can be operated in the three different oscillator modes for the main
oscillator (OSCI, OSCO), namely, RC oscillator with external resistor and Internal
capacitor mode (IC), crystal oscillator mode, and PLL operation mode. User can select
one of those three modes by programming FMMD1 and FMMD0 in the Code Option
register, the sub-oscillator can be operated in crystal mode and ERIC mode. Table 3
shows how these three modes are defined.
Table 3 Oscillator Modes Defined by FSMD, FMMD1, FMMD0
FSMD
FMMD1
FMMD0
Main Clock
RC type (ERIC)
Crystal type
PLL type
Sub-clock
RC type (ERIC)
RC type (ERIC)
RC type (ERIC)
RC type (ERIC)
Crystal type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PLL type
RC type (ERIC)
Crystal type
PLL type
Crystal type
Crystal type
Crystal
None
Table 4 Summary of Maximum Operating Speeds
Conditions
VDD
2.0
Fxt max. (MHz)
4
8
Two clocks
3.0
5.0
16
6.6.2 Crystal Oscillator/Ceramic Resonators (Crystal)
EM78P520N can be driven by an external clock signal through the OSCO pin as shown
in Figure 6-6 below.
Figure 6-6 External Clock Input Circuit
50
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Figure 6-7 depicts such circuitry. Table 5
provides the recommended values of C1 and C2. Since each resonator has its own
attribute, user should refer to its specification for appropriate values of C1 and C2. RS,
a serial resistor, may be necessary for AT strip cut crystal or low frequency mode.
Figure 6-7-1 Circuit for Crystal/Resonator
Table 5 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators
Oscillator Source
Oscillator Type
Frequency
455kHz
C1 (pF)
30
C2 (pF)
30
2.0 MHz
4.0 MHz
100kHz
Ceramic Resonators
30
30
30
30
68
68
200kHz
100K~1 MHz
1M~6 MHz
30
30
455kHz
30
30
1.0 MHz
2.0 MHz
4.0 MHz
6.0 MHz
8.0 MHz
10.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
30
30
Main Oscillator
30
30
30
30
Crystal
Oscillator
30
30
6M~12 MHz
30
30
30
30
30
30
12M~20 MHz
20
20
15
15
Sub-oscillator
Crystal Oscillator
32.768kHz
40
40
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
51
EM78P520N
8-Bit Microprocessor with OTP ROM
If the oscillator fails to start, the loading capacitors may need some adjustments, a
higher gain oscillator mode may be selected and a resistor may be required between
the OSC1 and OSC2 pins. The resistance for the feedback resistor RF, is typically
within the 1~10 M range. This varies with device voltage, temperature, and process
variations. Be sure to also take into consideration the device’s operating voltage and
manufacturing process when determining resistor requirements.
C1
C1
Xin
OSCI
RF
RF
XTAL
C2
XTAL
C2
Xout
OSCO
Figure 6-7-2 Circuit for Crystal/Resonator-Feedback Mode
330
330
C
OSCI
7404
7404
7404
Crystal
Figure 6-8 Circuit for Crystal/Resonator-Series Mode
Figure 6-9 Circuit for Crystal/Resonator-Parallel Mode
52
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.6.3 RC Oscillator Mode with Internal Capacitor
If both precision and cost are taken into consideration, the EM78P520N also offers a
special oscillation mode, which has a built-in internal capacitor and an external resistor
connected to VDD. The internal capacitor functions as temperature compensator. In
order to obtain more accurate frequency, a precise resistor is recommended.
VDD
Rext
OSCI or Xin
Figure 6-10 Circuit for Internal Capacitor Oscillator Mode
Table 6 Oscillator Frequencies
Pin
Rext
51k
Average Fosc 5V, 25C
2.2221 MHz
Average Fosc 3V, 25C
2.1972 MHz
OSCI
100k
300k
2.2M
1.1345 MHz
1.1203 MHz
381.36kHz
374.77kHz
Xin
32.768kHz
32.768kHz
1
Note: : Measured based on DIP packages.
2: The values are for design reference only.
6.6.4 Phase Lock Loop (PLL Mode)
When operating in PLL mode, the High frequency is determined by the sub-oscillator.
RC (Bank 0) register can be chosen to change to high oscillator frequency. The relation
between high frequency (Fm) and sub-oscillator is shown on the table below:
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
53
EM78P520N
8-Bit Microprocessor with OTP ROM
Figure 6-11 Circuit for PLL Mode
Bits 4~6 (CLK0~CLK2) of RC (Bank 0): Main Clock Selection Bits for PLL Mode
(Code Option Select)
CLK2
CLK1
CLK0
Main Clock
Reserve
Example Fs = 32.768kHz
0
1
1
X
0
1
X
X
X
-
Reserve
-
Fs 488
15.99 MHz
54
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.7 Power-on Considerations
Any microcontroller is not warranted to start operating properly before the power supply
stabilizes in its steady state. The EM78P520N has a built-in Power-on Reset (POR)
with detection level range of 1.9V to 2.1V. The circuitry eliminates the extra external
reset circuit. It will work well if VDD rises quickly enough (50 ms or less). However,
under critical applications, extra devices are still required to assist in solving power-on
problems.
6.7.1 External Power-on Reset Circuit
The circuit shown in Figure 6-12 implements an external RC to produce a reset pulse.
The pulse width (time constant) should be kept long enough to allow Vdd to reach
minimum operation voltage. This circuit is used when the power supply has a slow rise
time. Because the current leakage from the /RESET pin is 5 A, it is recommended
that R should not be greater than 40K. In this way, the voltage at Pin /RESET is held
below 0.2V. The diode (D) acts as a short circuit at power-down. The capacitor, C, is
discharged rapidly and fully. The current-limited resistor Rin, prevents high current
discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
VDD
/RESET
R
C
D
Rin
Figure 6-12 External Power-on Reset Circuit
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
55
EM78P520N
8-Bit Microprocessor with OTP ROM
6.7.2 Residue-Voltage Protection
When battery is replaced, device power (VDD) is taken off but residue-voltage remains.
The residue-voltage may trip below Vdd minimum, but not to zero. This condition may
cause a poor power-on reset. Figure 6-13 and Figure 6-14 show how to build a
residue-voltage protection circuit.
VDD
VDD
33K
Q1
10K
/RESET
100K
1N4684
Figure 6-13 Residue Voltage Protection Circuit 1
VDD
VDD
R1
R2
Q1
R3
/RESET
Figure 6-14 Residue Voltage Protection Circuit 2
56
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.8 Interrupt
Registers for Interrupt
R_BANK Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T1IE LVDIE ADIE SPIIE URTIE EXIE9 EXIE8 TCIE
Bank 0
Bank 0
0x0E
0x0F
IMR
ISR
R/W
T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF
R/W R/W R/W R/W R/W R/W R/W R/W
EXIE7 EXIE6 EXIE5 EXIE4 EXIE3 EXIE2 EXIE1 EXIE0
R/W R/W R/W R/W R/W R/W R/W R/W
EXIF7 EXIF6 EXIF5 EXIF4 EXIF3 EXIF2 EXIF1 EXIF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bank 1
Bank 1
Bank 2
0X0E
0X0F
0X09
EIMR
EISR
T2CR
R/W
T2IF
R/W
R/W
T2IE
R/W
R/W
T2S
R/W
R/W
T2MS1 T2MS0 T2P2
R/W R/W R/W
R/W
R/W
R/W
T2P1
R/W
R/W
T2P0
R/W
The EM78P520N has ten interrupt sources as listed below:
TCC overflow interrupt
External interrupt pin
Watch timer interrupt
Timer 1 overflow interrupt
Timer 2 overflow interrupt
A/D conversion complete interrupt
UART transmit/receive/error interrupt
SPI transmit/receive interrupt
Low voltage detector
This IC has internal interrupts which are falling edge triggered, namely: TCC timer
overflow interrupt, and two 8-bit upper counter/timer overflow interrupt. If these
interrupt sources change signal from high to low, the RF register will generate a “1” flag
to the corresponding register if RE register is enabled.
RF is the interrupt status register which records the interrupt request in flag bit. RE is
the interrupt mask register. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (when enabled) is generated,
it will cause the next instruction to be fetched from Address 0003H~001BH according to
the interrupt source.
For EM78P520N, each individual interrupt source has its own interrupt vector as
depicted in Table 7.
Before the interrupt subroutine is executed, the contents of ACC, R3[4:0] and the R5
register will be saved by hardware. After the interrupt service routine is finished, ACC,
R3[4:0] and R5 will be pushed back. While in interrupt service routine, other interrupt
service routine should not be allowed to be executed, so if other interrupts occur in an
interrupt service routine, the hardware will save this interrupt, after which when interrupt
service routine is completed, the next interrupt service routine will be executed.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
57
EM78P520N
8-Bit Microprocessor with OTP ROM
Interrupt
occurs
Interrupt sources
ENI/DISI
ACC
R3[4:0]
R5
STACKACC
STACKR3
STACKR5
RETI
Figure 6-15 Interrupt Backup Diagram
Table 7 Interrupt Vector
Interrupt Vector
0003H
Interrupt Status
TCC overflow interrupt
External interrupt
0006H
0009H
Watch timer interrupt
000CH
Timer 1 overflow interrupt
Timer 2 overflow interrupt
A/D conversion complete interrupt
000FH
0012H
0015H
UART transmit/receive/error complete interrupt
SPI transmit/receive complete interrupt
Low voltage detector interrupt
0018H
001BH
6.9 LCD Driver
Registers for LCD Driver Circuit
R_BANK Address
Name
Bit 7
Bit 6
Bit 5
BS1
R/W
Bit 4
BS0
R/W
Bit 3
DS1
R/W
Bit 2
DS0
R/W
Bit 1
LCDF1 LCDF0
R/W R/W
Bit 0
LCDEN LCDTYPE
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
005
006
007
008
009
LCDCR
R/W
R/W
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
R/W R/W R/W R/W R/W
LCDAR
LCDBR
LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCDC1 LCDC0 LCDVC2 LCDVC1 LCDVC0
LCDVCR
LCDCCR
R/W
R/W
R/W
R/W
R/W
CON7
CON6
CON5
CON4
CON3
CON2
CON1
CON0
R/W
SEG
R/W
R/W
SEG
R/W
R/W
SEG
R/W
R/W
SEG
R/W
R/W
SEG
R/W
R/W
SEG
R/W
R/W
SEG
R/W
R/W
SEG
R/W
Bank 1 00A~00C LCDSCR0~2
58
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
The EM78P520N can drive an LCD with up to 23 segments and 8 commons that can
drive a total of 823 dots. LCD block is made up of LCD driver, display RAM, segment
output pins, common output pins and LCD operating power supply pins. This circuit
can work in normal mode, green mode and idle mode.
The LCD duty, bias, the number of segment, the number of common and frame
frequency are determined by the LCD controller register.
The basic structure contains a timing control which use the main system clock or
subsystem clock to generate the proper timing for different duty and display access.
The R5 register is a command register for LCD driver that include LCD enable/disable,
bias (1/2, 1/3 and 1/4), duty (Static, 1/3, 1/4, 1/8) and LCD frame frequency control.
The register Bank 1 R6 is an LCD RAM address control register. The register Bank 1
R7 is an LCD RAM data buffer. The register Bank 1 R8 is an LCD contrast control and
LCD clock register. The control register is explained below.
6.9.1 R5 LCDCR ( LCD Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCDEN LCDTYPE
BS1
BS0
DS1
DS0
LCDF1
LCDF0
Bit 7 (LCDEN): LCD Enable Select Bit
0 : Disable LCD Circuit. All common/segment outputs are set to VDD
Level.
1 : Enable LCD circuit
Bit 6 (LCDTYPE): LCD Drive Waveform Type Select Bit
0 : A type wave
1 : B type wave
Bits 5~4 (BS1~BS0): LCD Bias Select Bits
BS1
BS0
LCD Bias Select
1/2 Bias
0
0
1
0
1
1/3 Bias
1/4 Bias
Bits 3~2 (DS1~DS0): LCD Duty Select Bits
DS1
DS0
LCD Duty
Static
0
0
1
1
0
1
0
1
1/3 Duty
1/4 Duty
1/8 Duty
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
59
EM78P520N
8-Bit Microprocessor with OTP ROM
Bits 1~0 (LCDF1~LCDF0): LCD Frame Frequency Control Bits
LCD Frame Frequency (e.q. Fs =32.768K)
1/3 Duty 1/4 Duty
Fs/(5121) = 64.0 Fs/(1723) =63.5 Fs/(1284) = 64
Fs/(5601) = 58.5 Fs/(1883) = 58
Fs/(6081) = 53.9 Fs/(2043) = 53.5 Fs/(1524) = 53.9 Fs/(768) = 53.9
Fs/(4641) = 70.6 Fs/(1563) = 70 Fs/(1164) = 70.6 Fs/(588) = 70.6
LCDF1 LCDF0
Static
1/8 Duty
0
0
1
1
0
1
0
1
Fs/(648) = 64.0
Fs/(1404) = 58.5 Fs/(708) = 58.5
6.9.2 R6 LCDADDR (LCD Address Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
Bits 7~5: Reserved
Bits 4~0 (LCD_A4~LCD_A0): LCD RAM Address
R7 (LCD Data Buffer)
Segment
R6
(LCD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Address)
(LCD_D7) (LCD_D6) (LCD_D5) (LCD_D4) (LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
00H
01H
02H
|
SEG0
SEG1
SEG2
|
14H
15H
16H
SEG20
SEG21
SEG22
Common COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
60
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.9.3 R7 LCDBR (LCD Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0
Bits 7~0 (LCD_D7~LCD_D0): LCD RAM Data Transfer Register
* When the value of the display segment is “1”, the LCD display is turned on; when the
bit value is “0”, the LCD display is turned off.
VDD
R
VLCD1
6R
R
R
R
VLCD2
VLCD3
MUX
0.6 R
0.8 R
BS0 ~ BS1
0.8 R
0.5 R
0.6R
VLCD
MUX
LCDVC0 ~ LCDVC2
0.3 R
0.4 R
VSS
6.9.4 R8 LCDVCR (LCD Voltage Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
LCDC1
LCDC0
LCDVC2 LCDVC1 LCDVC0
Bits 7~5: Reserved
Bits 4~3 (LCDC1~LCDC0): LCD Clock
LCDC1
LCDC0
Fm
FLCD
Fc/29
Fc/28
Fc/27
Fc/26
0
0
1
1
0
1
0
1
16 MHz
8 MHz
4 MHz
2 MHz
When the main oscillator operates in crystal mode and there is no sub-oscillator, it is a
must to set these two bits used for LCD clock.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
61
EM78P520N
8-Bit Microprocessor with OTP ROM
Bits 2~0 (LCDVC2~LCDVC0): LCD Voltage Control Bits
LCDVC2
LCDVC1
LCDVC0
Output
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.4VDD ~ VDD
0.34VDD ~ VDD
0.26VDD ~ VDD
0.18VDD ~ VDD
0.13VDD ~ VDD
0.07VDD ~ VDD
0.04VDD ~ VDD
0V ~ VDD
Non-
Select
Select
LCD Clock
Frame
VDD
COM
SEG
VLCD
VDD
VLCD
VDD
COM-SEG
VLCD
-VDD
Static
62
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
1frame
VDD
COM 0
COM 1
COM 2
SEG N
VLCD3
VLCD
VDD
VLCD3
VLCD
VDD
VLCD3
VLCD
VDD
VLCD3
VLCD
VDD
VLCD3
VLCD
-VLCD3
-VDD
SEG N - COM0
ON
VDD
VLCD3
VLCD
-VLCD3
-VDD
SEG N - COM1
OFF
1/2 bias, 1/3 duty
B type
1frame
VDD
COM 0
COM 1
COM 2
SEG N
VLCD3
VLCD
VDD
VLCD3
VLCD
VDD
VLCD3
VLCD
VDD
VLCD3
VLCD
VDD
VLCD3
VLCD
-VLCD3
-VDD
SEG N - COM0
ON
VDD
VLCD3
VLCD
-VLCD3
-VDD
SEG N - COM1
OFF
1/2 bias, 1/4 duty
B type
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
63
EM78P520N
8-Bit Microprocessor with OTP ROM
1frame
VDD
COM 0
VLCD3
VLCD
VDD
COM 1
COM 2
SEG N
VLCD3
VLCD
VDD
VLCD3
VLCD
VDD
VLCD3
VLCD
VDD
VLCD3
VLCD
-VLCD3
-VDD
SEG N - COM0
ON
VDD
VLCD3
VLCD
-VLCD3
-VDD
SEG N - COM1
OFF
1/2 bias, 1/8 duty
B type
1frame
VDD
VLCD2
VLCD3
VLCD
VDD
COM 0
VLCD2
VLCD3
VLCD
VDD
COM 1
VLCD2
VLCD3
VLCD
VDD
COM 2
SEG N
VLCD2
VLCD3
VLCD
VDD
SEG N - COM0
ON
VLCD3
VLCD
-VLCD3
-VDD
VDD
SEG N - COM1
OFF
VLCD3
VLCD
-VLCD3
-VDD
1/3 bias, 1/3 duty
B type
64
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
1 frame
VDD
VLCD2
VLCD3
VLCD
VDD
COM 0
COM 1
VLCD2
VLCD3
VLCD
VDD
VLCD2
COM 2
SEG N
VLCD3
VLCD
VDD
VLCD2
VLCD3
VLCD
VDD
SEG N - COM0
ON
VLCD3
VLCD
-VLCD3
-VDD
VDD
SEG N - COM1
OFF
VLCD3
VLCD
-VLCD3
-VDD
1/3 bias, 1/4 duty
B type
1 frame
VDD
VLCD2
VLCD3
VLCD
VDD
COM 0
VLCD2
VLCD3
VLCD
VDD
COM 1
COM 2
VLCD2
VLCD3
VLCD
VDD
VLCD2
VLCD3
VLCD
VDD
SEG N
SEG N - COM0
ON
VLCD3
VLCD2
VLCD
-VLCD2
-VLCD3
-VDD
SEG N - COM1
OFF
VDD
VLCD3
VLCD2
VLCD
-VLCD2
-VLCD3
-VDD
1/3 bias, 1/8 duty
B type
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
65
EM78P520N
8-Bit Microprocessor with OTP ROM
Select
Frame
VDD
VLCD1
VLCD2
VLCD3
COM 0
COM 1
VLCD
VDD
VLCD1
VLCD2
VLCD3
VLCD
VDD
VLCD1
VLCD2
VLCD3
COM 2
SEGN
VLCD
VDD
VLCD1
VLCD2
VLCD3
VLCD
VDD
VLCD1
VLCD2
VLCD3
VLCD
SEGN-COM0
-VLCD3
-VLCD2
-VLCD1
-VDD
VDD
VLCD1
VLCD2
VLCD3
VLCD
SEGN-COM1
-VLCD3
-VLCD2
-VLCD1
-VDD
1/4 Bias 1/3 Duty
66
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Select
Frame
VDD
VLCD1
VLCD2
VLCD3
COM 0
COM 1
VLCD
VDD
VLCD1
VLCD2
VLCD3
VLCD
VDD
VLCD1
VLCD2
VLCD3
COM 2
SEGN
VLCD
VDD
VLCD1
VLCD2
VLCD3
VLCD
VDD
VLCD1
VLCD2
VLCD3
VLCD
SEGN-COM0
-VLCD3
-VLCD2
-VLCD1
-VDD
VDD
VLCD1
VLCD2
VLCD3
VLCD
SEGN-COM1
-VLCD3
-VLCD2
-VLCD1
-VDD
1/4 Bias 1/4 Duty
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
67
EM78P520N
8-Bit Microprocessor with OTP ROM
Select
Frame
VDD
VLCD1
VLCD2
VLCD3
VLCD
VDD
COM 0
VLCD1
VLCD2
VLCD3
VLCD
COM 1
VDD
VLCD1
VLCD2
VLCD3
VLCD
COM 2
SEGN
VDD
VLCD1
VLCD2
VLCD3
VLCD
VDD
VLCD1
VLCD2
VLCD3
SEGN-COM0
VLCD
-VLCD3
-VLCD2
-VLCD1
-VDD
VDD
VLCD1
VLCD2
VLCD3
VLCD
SEGN-COM1
-VLCD3
-VLCD2
-VLCD1
-VDD
1/4 Bias 1/8 Duty
68
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.10 A/D Converter
Registers for AD Converter Circuit
R_BANK Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADRUN ADP ADCK1 ADCK0 ADIS3 ADIS2 ADIS1 ADIS0
Bank 3
Bank 3
Bank 3
Bank 3
Bank 3
0X09
0x0A
0X0B
0X0C
0X0D
ADCR
ADICH
ADICL
ADDH
ADDL
R/W
CALI ADREF
R/W R/W
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
R/W R/W R/W R/W R/W R/W R/W R/W
ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4
R/W
R/W
R/W
R/W
ADE11 ADE10 ADE9 ADE8
R/W R/W R/W R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
SIGN VOF[2] VOF[1] VOF[0] ADD3 ADD2 ADD1 ADD0
R/W R/W R/W R/W
ADWK INTWK INTWK EIES9 EIES8
R/W R/W R/W R/W R/W
T1IE LVDIE ADIE SPIIE URTIE EXIE9 EXIE8 TCIE
R/W R/W R/W R/W R/W R/W R/W R/W
T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF
R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
Bank 0
Bank 0
Bank 0
0x0F
0x0E
0x0F
EIESL
IMR
ISR
Figure 6-16 AD Converter
This is a 12-bit successive approximation type AD converter. The upper side of analog
reference voltage can select either internal VDD or external input pin P84 (VREF) by
setting the ADREF bit in ADICH. Connecting to the external VREF is more accurate
than connecting to the internal VDD.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
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EM78P520N
8-Bit Microprocessor with OTP ROM
6.10.1 ADC Data Register
When A/D conversion is completed, the result is loaded to the ADDH (8-bit) and ADDL
(4-bit). The START/END bit is cleared, and the ADIF is set.
6.10.2 A/D Sampling Time
The accuracy, linearity, and speed of the successive approximation A/D converter are
dependent on the properties of the ADC. The source impedance and the internal
sampling impedance directly affect the time required to charge the sample holding
capacitor. The application program controls the length of the sample time to meet the
specified accuracy. Generally speaking, the program should wait for 2 µs for each K
of the analog source impedance and at least 2 µs for the low-impedance source. The
maximum recommended impedance for the analog source is 10K at VDD =5V. After
the analog input channel is selected, this acquisition time must be done before A/D
conversion can be started.
6.10.3 A/D Conversion Time
ADCK0 and ADCK1 select the conversion time (Tct), in terms of instruction cycles.
This allows the MCU to run at maximum frequency without sacrificing accuracy of A/D
conversion. For the EM78P520N, the conversion time per bit is about 4 µs. Table 8
shows the relationship between Tct and the maximum operating frequencies.
Table 8
Max. Frequency
(Fc)
Max. Conversion
Rate per Bit
Max. Conversion
Rate
ADCK1:0 Operation Mode
0 0
0 1
1 0
1 1
Fc/4
Fc/16
Fc/32
Fc/64
1 MHz
4 MHz
8 MHz
16 MHz
250kHz (4 µs)
250kHz (4 µs)
250kHz (4 µs)
250kHz (4 µs)
60 µs (16.66kHz)
60 µs (16.66kHz)
60 µs (16.66kHz)
60 µs (16.66kHz)
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EM78P520N
8-Bit Microprocessor with OTP ROM
6.11 UART (Universal Asynchronous Receiver/Transmitter)
Registers for UART Circuit
R_BANK Address Name Bit 7
URTD8 UMODE1 UMODE0 BRATE2 BRATE1 BRATE0 UTBE
R/W R/W R/W R/W R/W
URRD8 EVEN PRE PRERR OVERR FMERR URBF
R/W R/W
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
TXE
R/W
RXE
R/W
Bank 3
Bank 3
Bank 3
Bank 3
Bank 5
0X05
0X06
0X07
0X08
0x06
URC
URS
W
R
R
R
R
R
R
URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0
URRD
URTD
UARC2
R
R
R
R
R
R
R
R
URTD 7 URTD 6 URTD 5 URTD 4 URTD 3 URTD 2 URTD 1 URTD0
W
W
W
W
W
W
W
W
UARTE
R/W
UINVEN
R/W
T1IE LVDIE ADIE SPIIE URTIE EXIE9 EXIE8 TCIE
R/W R/W R/W R/W R/W R/W R/W R/W
T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF
R/W R/W R/W R/W R/W R/W R/W
R/W
Bank 0
Bank 0
0x0E
0x0F
IMR
ISR
Figure 6-17 Functional Block Diagram
In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received
character is individually synchronized by framing it with a start bit and stop bit.
Full duplex data transfer is possible since the UART has independent transmit and
receive sections. Double buffering for both sections allows the UART to be
programmed for continuous data transfer.
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EM78P520N
8-Bit Microprocessor with OTP ROM
The figure below shows the general format of one character sent or received. The
communication channel is normally held in the marked state (high). Character
transmission or reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits, in
which the Least Significant Bit (LSB) comes first. The data bits are followed by the
parity bit. If present, then the stop bit or bits (high) confirm the end of the frame.
In receiving, the UART synchronizes on the falling edge of the start bit. When two or
three “0” are detected during three samples, it is recognized as normal start bit and the
receiving operation is started.
Idle state
(mark)
START
bit
Parity STOP
D0
D1
D2
Dn
bit
bit
1 bit
7 or 8 bits
One character or frame
1 bit
1 bits
Figure 6-18 Data Format in UART
6.11.1 UART Mode
There are three UART modes. Mode 1 (7 bits data) and Mode 2 (8 bits data) allow the
addition of a parity bit. The parity bit addition is not available in Mode 3. Figure 6-19
below shows the data format in each mode.
1
2
3
4
5
6
7
8
9
10 11
UMODE PRE
7 bits DATA
7 bits DATA
STOP
0
0
0
START
Mode 1
0
0
1
Parity STOP
STOP
START
8 bits DATA
8 bits DATA
0
0
1
1
0
1
START
START
Mode 2
Mode 3
Parity STOP
9 bits DATA
STOP
1
0
X
START
Figure 6-19 UART Model
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Product Specification (V1.4) 04.08.2016
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EM78P520N
8-Bit Microprocessor with OTP ROM
6.11.2 Transmitting
In transmitting serial data, the UART operates as follows:
1. Set the TXE bit of the URC register to enable the UART transmission function.
2. Write data into the URTD register and the UTBE bit of the URC register will be set
by hardware.
3. Then start transmitting.
4. Serially transmitted data are transmitted in the following order from the TX pin.
5. Start bit: one “0” bit is output.
6. Transmit data: 7, 8 or 9 bits data are output from the LSB to the MSB.
7. Parity bit: one parity bit (odd or even selectable) is output.
8. Stop bit: one “1” bit (stop bit) is output.
Mark state: output “1” continues until the start bit of the next transmitted data.
After transmitting the stop bit, the UART generates a TBEF interrupt (if enabled).
6.11.3 Receiving
In receiving, the UART operates as follows:
1. Set RXE bit of the URS register to enable the UART receiving function. The UART
monitors the RX pin and synchronizes internally when it detects a start bit.
2. Receive data is shifted into the URRD register in the order from LSB to MSB.
3. The parity bit and the stop bit are received. After one character is received, the
URBF bit of the URS register will be set to “1”.
4. The UART makes the following checks:
(a) Parity check: The number 1 of the received data must match the even or odd
parity setting of the EVEN bit in the URS register.
(b) Frame check: The start bit must be “0” and the stop bit must be “1”.
(c) Overrun check: The URBF bit of the URS register must be cleared (that means
the URRD register should be read out) before the next received data is loaded
into the URRD register.
If any checks failed, the URTIF interrupt will be generated (if enabled), and an error
flag is indicated in PRERR, OVERR or FMERR bit. The error flag should be
cleared by software otherwise, URTIF interrupt will occur when the next byte is
received.
5. Read received data from the URRD register. The URBF bit will be cleared by
hardware.
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EM78P520N
8-Bit Microprocessor with OTP ROM
6.11.4 Baud Rate Generator
The baud rate generator is comprised of a circuit that generates a clock pulse to
determine the transfer speed for transmission/reception in the UART.
The BRATE2~BRATE0 bits of the URC register can determine the desired baud rate.
6.11.5 UART Timing
1. Transmission Counter Timing
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
TSYSTEM/16
One bit cycle
Start bit
Bit 0
TXD pin
2. Receiving Counter Timing
Synchronization
(Reset counter)
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15
16
1
2
3
4
12 13
TSYSTEM /16
One bit cycle
Start bit
Bit 0
Stop bit
RXD pin
Sampling
Timing
3. UART Transmit operation (8 bits data with parity bit)
START
bit
Parity STOP
bit bit
START
bit
D0
D1
D2
Dn
D0
D1
D2
TXD
pin
Clear by hardware when
write data into UARTTx .
And start transmitting.
UTBE
Clear by
software
URTIF
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EM78P520N
8-Bit Microprocessor with OTP ROM
4. UART Receive operation (8 bits data with parity and stop bit):
START
bit
Parity STOP START
bit bit bit
D0
D2
D1
D1
Dn
D0
D2
RXD
pin
Synchronization
Sample
Timing
Clear by hardware when
read data fromUARTRx
URBF
Clear by
software
URTIF
PRERR
OVERR
FMERR
6.12 SPI (Serial Peripheral Interface)
6.12.1 Overview and Features
Overview:
Figures 6-20 and 6-21 shows how the EM78P520N communicates with other devices
through SPI module. If the EM78P520N is a master controller, it sends clock through
the SCK pin. A couple of 8-bit data are transmitted and received at the same time.
However, if the EM78P520N is defined as a slave, its SCK pin could be programmed as
an input pin. Data will continue to be shifted based on both the clock rate and the
selected edge. The SPIS Bit 7 (DORD) can also set to determine the SPI transmission
order, SPIC Bit 3 (SDOC) to control the SO pin after serial data output status and SPIS
Bit 6 (TD1), Bit 5 (TD0) determines the SO status output delay times.
Features:
Operation in either Master mode or Slave mode
Full duplex, three-wire synchronous communication
Programmable baud rates of communication
Programming clock polarity, (RD Bit 7)
Interrupt flag available for the read buffer full
SPI transmission order
After serial data output SDO status select
SDO status output delay times
Up to 8 MHz (maximum) bit frequency
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(This specification is subject to change without prior notice)
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EM78P520N
8-Bit Microprocessor with OTP ROM
SO
SPIW Reg
SPIW Reg
SPIR Reg
SPIR Reg
/SS
SI
SPI Module
SPIS Reg
SCK
Master Device
Slave Device
Figure 6-20 SPI Master/Slave Communication
Figure 6-21 SPI Configuration of Single-Master and Multi-Slave
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Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.12.2 SPI Function Description
Read
Write
RBF
SPIIF
SSE
SPIW
SPIR reg
reg
Set to 1
Buffer Full Detector
shift right
SPIS reg
PA4/SEG4/SI
SPIC reg
PA5/SEG5/SO
Edge
Select
SBR0 ~SBR2
Noise
Filter
PA7/SEG7//SS
SBR2~SBR0
/ SS
Clock Select
Prescaler
2, 4, 8, 16, 32
Fosc
Edge
Select
PA6/SEG6/SCK
TMR2
CES
Figure 6-22 SPI Block Diagram
Figure 6-23 Function Block Diagram of SPI Transmission
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(This specification is subject to change without prior notice)
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EM78P520N
8-Bit Microprocessor with OTP ROM
Below are the functions of each block and explanations on how to carry out the SPI
communication with the signals depicted in Figure 6-22 and Figure 6-23.
PA4/SEG4/SI: Serial Data In
PA5/SEG5/SO: Serial Data Out
PA6/SEG6/SCK: Serial Clock
PA7/SEG7//SS: /Slave Select (Option). This pin (/SS) may be required in slave
mode
RBF: Set by Buffer Full Detector
Buffer Full Detector: Set to 1 when an 8-bit shifting is completed.
SSE: Loads the data in SPIS register, and begin to shift
SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIR and the
SPIW registers are shift at the same time. Once data are written, SPIS starts
transmitting / receiving. The data received will be moved to the SPIR register as
the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the
SPIIF (SPI Interrupt) flags are then set.
SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is
completed. The data must be read before the next reception is completed. The
RBF flag is cleared as the SPIR register reads.
SPIW reg.: Write buffer. The buffer will deny any attempts to write until the 8-bit
shifting is completed.
The SSE bit will be kept in “1“ if the communication is still undergoing. This flag
must be cleared as the shifting is completed. Users can determine if the next write
attempt is available.
SBRS2~SBRS0: Programming the clock frequency/rates and sources.
Clock Select: Selecting either the internal or the external clock as the shifting
clock.
Edge Select: Selecting the appropriate clock edges by programming the CES bit
6.12.3 SPI Signal and Pin Description
The detailed functions of the four pins, SI, SO, SCK, and /SS are as follows:
PA4/SEG4/SI:
Serial Data In
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
last
Defined as high-impedance, if not selected
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EM78P520N
8-Bit Microprocessor with OTP ROM
Program the same clock rate and clock edge to latch on both the master and slave
devices.
The byte received will update the transmitted byte.
The RBF (located in Register 0x0C) will be set as the SPI operation is completed.
Timing is shown in Figure 6-23 and 6-24.
PA5/SEG5/SO:
Serial Data Out
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last
Program the same clock rate and clock edge to latch on both the master and slave
devices.
The received byte will update the transmitted byte.
The CES (located in Register 0x0D) bit will be reset, as the SPI operation is
completed.
Timing is shown in Figure 6-23 and 6-24.
PA6/SEG6/SCK:
Serial Clock
Generated by a master device
Synchronize the data communication on both the SI and SO pins
The CES (located in Register 0x0D) is used to select the edge to communicate.
The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of
communication
The CES, SBR0, SBR1, and SBR2 bits have no effect in slave mode
Timing is shown in Figure 6-23 and 6-24
PA7/SEG7//SS:
Slave Select; negative logic
Generated by a master device to signify the slave(s) to receive data
Goes low before the first cycle of SCK appears, and remains low until the last 8th
cycle is completed.
Ignores the data on the SI and SO pins while /SS is high, because SO is no longer
driven.
Timing is shown in Figure 6-23 and 6-24.
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(This specification is subject to change without prior notice)
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EM78P520N
8-Bit Microprocessor with OTP ROM
Note:
1. The Priority of PA4/SEG4/SI Pin
PA4/SEG4/SI Pin Priority
High
Medium
Low
SI
SEG4
PA4
2. The Priority of PA5/SEG5/SO Pin
PA5/SEG5/SO Pin Priority
High
Medium
Low
SO
SEG5
PA5
3. The Priority of PA6/SEG6/SCK Pin
PA6/SEG6/SCK Pin Priority
High
Medium
Low
SCK
SEG6
PA6
4. The Priority of PA7/SEG7//SS Pin
PA7/SEG7//SS Pin Priority
High
Medium
Low
/SS
SEG7
PA7
6.12.4 Programming the Related Registers
Registers for the SPI Circuit
R_BANK Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DORD
TD1
TD0
-
OD3
OD4
-
RBF
Bank 2
Bank 2
0X0C
0X0D
SPIS
SPIC
R/W
R/W
R/W
-
R/W
R/W
-
R
CES
SPIE
SRO
SSE
SDOC SBRS2 SBRS1 SBRS0
R/W R/W R/W R/W
R/W
R/W
R/W
R/W
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
R/W R/W R/W R/W R/W R/W R/W R/W
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
Bank 2
Bank 2
0X0E
0X0F
SPIR
SPIW
R/W
T1IE
R/W
T1IF
R/W
R/W
LVDIE ADIE
R/W R/W
LVDIF ADIF
R/W R/W
R/W
R/W
SPIIE URTIE EXIE9 EXIE8 TCIE
R/W R/W R/W R/W R/W
SPIIF URTIF EXIF9 EXIF8 TCIF
R/W
R/W
R/W
R/W
Bank 0
Bank 0
0X0E
0X0F
IMR
ISR
R/W
R/W
R/W
R/W
R/W
As the SPI mode is defined, the related registers of this operation are shown.
Related Control Registers of the SPI Mode
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
0x0D
SPIC
CES
SPIE
SRO
SSE
SDOC
SBR2
SBR1
SBR0
Bank 0
0x0E
IMR
T1IE
LVDIE ADIE
SPIIE URTIE EXIE9 EXIE8 TCIE
SPIC: SPI Control Register
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EM78P520N
8-Bit Microprocessor with OTP ROM
Bit 7 (CES): Clock Edge Select Bit
0 : Data shifts out on a rising edge, and shifts in on a falling edge. Data is
on hold during a low-level.
1 : Data shifts out on a falling edge, and shifts in on a rising edge. Data is
on hold during a high-level.
Bit 6 (SPIE): SPI Enable Bit
0 : Disable SPI mode
1 : Enable SPI mode
Bit 5 (SRO): SPI Read Overflow Bit
0 : No overflow
1 : A new data is received while the previous data is still being held in the
SPIRB register. In such situation, the data in the SPIS register will be
destroyed. To avoid setting this bit, users are required to read the
SPIRB register although only transmission is implemented. This can
only occur in slave mode.
Bit 4 (SSE): SPI Shift Enable Bit
0 : Resets as soon as the shift is completed, and the next byte is read to
shift.
1 : Starts to shift, and remained on “1” while the current byte is still being
transmitted.
Bit 3 (SDOC): SDO Output Status Control Bit
0 : After the serial data output, the SDO remain high.
1 : After the serial data output, the SDO remain low.
Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select Bits
SBRS2
SBRS1
SBRS0
Mode
Master
Master
Master
Master
Master
Master
Slave
SPI Baud Rate
Fosc/2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Timer 2
/SS enable
/SS disable
Slave
IMR:
Interrupt Mask Register
Product Specification (V1.4) 04.08.2016
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EM78P520N
8-Bit Microprocessor with OTP ROM
Bit 4 (SPIIE): Interrupt Enable Bit
0 : Disable SPIIF interrupt
1 : Enable SPIIF interrupt
Related Status/Data Registers of the SPI Mode
Address
0X0C
0x0E
Name
SPIS
SPIR
SPIW
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DORD
TD1
TD0
-
OD3
OD4
-
RBF
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
0x0F
SPIS:
SPI Status Register
Bit 7 (DORD): Data Shift Control Bit
0 : Shift left (MSB first)
1 : Shift right (LSB first).
Bits 6~5 (TD1~TD0): SDO Status Output Delay Times Options
TD1
0
TD0
0
Delay Time
8 CLK
0
1
16 CLK
24 CLK
32 CLK
1
0
1
1
Bit 4:
Bit 3 (OD3): Open-Drain Control Bit
0 : Open-drain disable for SDO.
1 : Open-drain enable for SDO
Bit 2 (OD4): Open-Drain Control Bit
Reserved
0 : Open-drain disable for SCK
1 : Open-drain enable for SCK
Bit 1:
Reserved
Bit 0 (RBF): Read Buffer Full Flag
0 : Receiving not completed, and SPIRB has not fully exchanged.
1 : Receiving completed, and SPIRB is fully exchanged.
SPIRB:
SPIWB:
SPI Read Buffer. Once the serial data is received completely, it will load to
SPIRB from SPIS register. The RBF bit in the SPIS register will also be set.
SPI Write Buffer. As a transmitted data is loaded, the SPIS register
stands by and start to shift the data when sensing SCK edge with SSE set
to “1”.
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EM78P520N
8-Bit Microprocessor with OTP ROM
6.12.5 SPI Mode Timing
Figure 6-24 SPI Mode with /SS Disabled
The SCK edge is selected by programming bit CES. The waveform shown in Figure
6-24 is applicable regardless of whether the EM78P520N is in master or slave mode
with /SS disabled. However, the waveform in Figure 6-25 can only be implemented in
slave mode with /SS enabled.
Figure 6-25 SPI Mode with /SS Enabled
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
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EM78P520N
8-Bit Microprocessor with OTP ROM
6.13 Timer/Counter 1
Registers for Timer/Counter 1 Circuit
R_BANK Address Name Bit 7
TIS1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
TIS0
T1MS2 T1MS1 T1MS0 T1P2
T1P1
T1P0
Bank 2
Bank 2
Bank 2
Bank 2
Bank 0
Bank 0
0X05
0X06
0X07
0X08
0x0E
0x0F
T1CR
TSR
T1PD
T1TD
IMR
W
W
W
W
W
W
W
W
T1MOD TRCB T1CSS1 T1CSS0 T2CSS
R/W R/W R/W R/W R/W
PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0]
R/W R/W R/W R/W R/W R/W R/W R/W
TD1[7] TD1[6] TD1[5] TD1[4] TD1[3] TD1[2] TD1[1] TD1[0]
R/W R/W R/W R/W R/W R/W R/W R/W
T1IE LVDIE ADIE SPIIE URTIE EXIE9 EXIE8 TCIE
R/W R/W R/W R/W R/W R/W R/W R/W
T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF
R/W R/W R/W R/W R/W R/W R/W R/W
T1S T1OMS T1OC
R/W R/W R/W
ISR
Figure 6-26 Timer/Counter 1 Configuration
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Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.13.1 Timer Mode
In Timer mode, counting down is performed using the internal clock. The down-counter
value auto reloads from T1PD. When the content of the down-counter underflows, an
interrupt is generated and the counter is cleared. Counting down resumes after the
counter is cleared.
6.13.2 T1OUT Mode
In Timer 1 underflow Output mode, counting down is performed using the internal clock
with prescaler or external clock through T1CLK Pin or Sub Frequency with prescaler.
The counter value is loaded from T1PD, when the counter underflows. The F/F output
is toggled and the counter is auto-reloaded from T1PD, each time an overflow is found.
The F/F output is inverted and output to /T1OUT pin. This mode can generate 50%
duty pulse output. The program can initialize the F/F and it is initialized to “0” during a
reset. A T1OUT interrupt is generated each time the /T1OUT output is toggled.
Clock Source
Down-counter
n
n-2 n-3
n
n-1
n-1
n
n-1
1
0
1
0
n
1
0
n-1 n-2
T1PD
n
F/F
T1OUT Pin
Timer 1 Interrupt
Figure 6-27 T1OUT Mode Timing Diagram
6.13.3 Capture Mode
In Capture mode, the pulse width, period and duty of the T1CAP input pin are
measured, which can be used in decoding the remote control signal. The counter is
free running by the internal clock. On the rising (falling) edge of T1CAP pin input, the
contents of the counter is loaded into T1PD, then the counter is cleared and interrupt is
generated. On the falling (rising) edge of T1CAP pin input, the contents of the counter
are loaded into T1TD. The counter is still counting, on the next rising edge of the
T1CAP pin input, the contents of the counter are loaded into T1PD, the counter is
cleared and interrupt is generated again. If an overflow occurs before the edge is
detected, 00H is loaded into T1PD and an underflow interrupt is generated. During
interrupt processing, it can be determined whether or not there is an overflow by
checking whether the T1PD value is 00H. After an interrupt (capture to T1PD or
overflow detection) is generated, capture and underflow detection are halted until
T1PD is read out.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
85
EM78P520N
8-Bit Microprocessor with OTP ROM
Clock Source
FF
m+1
n-1 n
FF
Down-counter
K
m
m-1
FE
FF
FE
FE
FE FD
1
0
FF FD FC
T1CAP Pin Input
T1PD
K
n
0 (underflow)
1
m
T1TD
Capture
underflow
Capture
Timer 1 Interrupt
Reading T1PD
Figure 6-28 Capture Mode Timing Diagram
6.13.4 PWM Mode
In Pulse Width Modulation (PWM) Output mode, counting down is performed using the
internal clock with prescaler or external clock through T1CLK Pin or Sub Frequency
with prescaler. The Duty of PWM1 is controlled by T1TD, and the period of PWM1 is
controlled by T1PD. The pulse at the PWM1 pin is held to a high level as long as the
counter value of T1TD is greater than or equal to zero, while the pulse is held to a low
level until the counter value of T1PD underflows. The F/F is toggled when underflow
occurs. While the counter is still counting, the F/F is toggled again when the counter
underflows, then the counter is auto reloaded from T1PD. The F/F output is inverted
and output to the /PWM pin. A Timer 1 interrupt is generated each time an underflow
occurs. T1PD is configured as a 2-stage shift register and during output, will not switch
until one output cycle is completed even if T1PD is overwritten. Therefore, the output
can be changed continuously. T1PD is also shifted the first time by setting T1S to “1”
after data is loaded to T1PD.
Figure 6-29 PWM Mode Timing Diagram
6.13.5 16-Bit Mode
In 16-bit timer mode, all function in Timer 1 resolution become 16 bits.
86
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.14 Timer 2
Registers for Timer 2 Circuit
R_BANK Address Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
T1MOD TRCB T1CSS1 T1CSS0 T2CSS
T1S T1OMS T1OC
Bank 2
Bank 2
Bank 2
Bank 2
0X06
0X09
0X0A
0X0B
TSR
T2CR
T2PD
T2TD
R/W
R/W
R/W
R/W
T2MS1 T2MS0 T2P2
R/W R/W R/W
R/W
R/W
R/W
R/W
T2IF
T2IE
T2S
T2P1
T2P0
R/W
R/W
R/W
R/W
R/W
PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0]
R/W R/W R/W R/W R/W R/W R/W R/W
TD2[7] TD2[6] TD2[5] TD2[4] TD2[3] TD2[2] TD2[1] TD2[0]
R/W R/W R/W R/W R/W R/W R/W R/W
Figure 6-30 Timer 2 Configuration
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
87
EM78P520N
8-Bit Microprocessor with OTP ROM
6.14.1 Timer Mode
In Timer mode, counting down is performed using the internal clock with prescaler.
When the counter value from T2PD underflows, interrupt is then generated and the
counter is cleared. Counting down resumes after the counter is cleared. The counter
value will automatically reload from T2PD.
Internal Clock
n-4
n
n
n-1 n-2 n-3
3
2
1
0
n-1 n-2 n-3
clear counter
Down-counter
T2PD
n-5
n
underflow
Timer 2 Interrupt
Figure 6-31 Timer Mode Timing Diagram
6.14.2 PWM Mode
In Pulse Width Modulation (PWM) Output mode, counting down is performed using the
internal clock with prescaler or Fsub with frequency. The PWM2 duty cycle is controlled
by T2TD, and the PWM2 period is controlled by T2PD. The pulse at the PWM2 pin is
held to high level as long as the T2TD counter value is greater than or equal to zero while
the pulse is held to low level until the T2PD counter value underflows.
Figure 6-32 PWM Mode Timing Diagram
88
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.15 Code Options
The EM78P520N has one Code Option word that is not part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
Word 0
Word 1
Word 2
Bit 12~Bit 0
Bit 12~Bit 0
Bit 12~Bit 0
1. Code Option Register (Word 0)
Word 0
Bit 7
Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 6 Bit 5
Bit 4 Bit 3 Bit2 Bit1 Bit0
Mne
monic
TYPE1 TYPE0 LVREN LVR1 LVR0 ENWDTB FSMD FMMD1 FMMD0 HLP
Protect
1
High High Enable High High Disable High High
Low Low Disable Low Low Enable Low Low
High High
Low Low
Disable
Enable
0
Bits 12~11 (TYPE1~TYPE0): Type Selection for 48 pins or 44 pins.
TYPE1
TYPE0
Type Selection
0
0
1
1
0
1
0
1
Reserved
Reserved
EM78P520N (44-pin LQFP/QFP)
EM78P520N (48-pin LQFP) (default)
Bit 10 (LVREN): Low Voltage Reset Enable Bit
0 : Disable
1 : Enable
Bits 9~8 (LVR1~LVR0): Low Voltage Reset Voltage Select Bits
LVR1
LVR0
Reset Voltage
2.6V
0
0
1
0
1
0
3.3V
3.9V
Bit 7 (ENWDTB): Watchdog Timer Enable Bit
0 : Enable
1 : Disable
Bits 6~4 (FSMD, FMMD1~FMMD0): Oscillator Modes Selection Bits
FSMD
FMMD1
FMMD0
Main Oscillator
RC type (ERIC)
Crystal type
PLL type
Sub Oscillator
RC type (ERIC)
RC type (ERIC)
RC type (ERIC)
RC type (ERIC)
Crystal type
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PLL type
RC type (ERIC)
Crystal type
PLL type
Crystal type
Crystal type
Crystal
None
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
89
EM78P520N
8-Bit Microprocessor with OTP ROM
Bit 3 (HLP): Power Consumption Select Bit
0 : Low power consumption, applyto working frequencyat 4 MHzor below
4 MHz.
1 : High power consumption, apply to working frequency above 4 MHz.
Bits 2~0 (Protect): Protect Bit
Protect are protect bits, protect type are as follows:
0 : Enable
1 : Disable
2. Code Option Register (Word 1)
Word 1
Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
Bit 5
Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
Mne
monic
RESE
TENB
HLFS
FCB0 FCB1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Main
Oscillator
High
Low
High
Low
P81
1
0
Sub
Oscillator
/RE
SET
Bits 12~7: Not used, but must be cleared to “1” all the time to avoid possible error.
Bit 6: Not used, but must be cleared to “0” all the time to avoid possible error.
Bit 5 (HLFS): Main or Sub Oscillator Select Bit
0 : CPU is selected as sub-oscillator when a reset occurs
1 : CPU is selected as main-oscillator when a reset occurs
Bits 4~3:
Not used, but must be cleared to “1” all the time to avoid possible error.
Bits 2~1 (FCB0~FCB1): Frequency for Crystal (main oscillator) Select Bit
FCB1
FCB0
Operation Frequency
100k~1M
0
0
1
1
0
1
0
1
1M~6M
6M~12M
12M~20M
Bit 0 (RESETENB): Reset Pin Enable Bit
0 : Enable, P81//RESET /RESET pin
1 : Disable, P81//RESET P81
3. Customer ID Register (Word 2)
Word 2
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Customer ID
90
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
6.16 Instruction Set
Each instruction in the Instruction Set is a 13-bit word divided into an OP code and one
or more operand. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2",). In this case, the
execution takes two instruction cycles.
The following are executed within two instruction cycles; "LJMP", "LCALL", or
conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") instructions which were
tested to be true. Instructions written to the program counter are also executed within
two instruction cycles.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on the I/O register.
Convention:
r = Register designator that specifies which one of the registers (including operation and
general purpose registers) is to be utilized by the instruction.
Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects
the operation.
k = 8 or 10-bit constant or literal value
Mnemonic
NOP
Operation
Status Affected
No Operation
None
C
DAA
Decimal Adjust A
0 WDT, Stop oscillator
0 WDT
SLEP
WDTC
ENI
T, P
T, P
None
None
None
None
None
Z
Enable Interrupt
Disable Interrupt
[Top of Stack] PC
[Top of Stack] PC, Enable Interrupt
A R
DISI
RET
RETI
MOV R,A
CLRA
CLR R
0 A
0 R
Z
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
91
EM78P520N
8-Bit Microprocessor with OTP ROM
Mnemonic
Operation
Status Affected
SUB A,R
SUB R,A
DECA R
DEC R
R-A A
R-A R
R-1A
Z, C, DC
Z, C, DC
Z
R-1 R
Z
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
A R A
A R R
A & R A
A & R R
A R A
A R R
A + R A
A + R R
R A
Z
Z
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
Z
R R
/R A
Z
/R R
Z
INCA R
INC R
R+1 A
R+1 R
Z
Z
DJZA R
DJZ R
R-1 A, skip if zero
None
None
C
R-1 R, skip if zero
RRCA R
RRC R
R(n) A(n-1), R(0) C, C A(7)
R(n) R(n-1), R(0) C, C R(7)
R(n) A(n+1), R(7) C, C A(0)
R(n) R(n+1), R(7) C, C R(0)
R(0-3) A(4-7), R(4-7) A(0-3)
R(0-3) R(4-7)
C
RLCA R
RLC R
C
C
SWAPA R
SWAP R
JZA R
None
None
None
R+1 A, skip if zero
92
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Mnemonic
JZ R
Operation
R+1 R, skip if zero
Status Affected
None
None
None1
None
None
None
None
None
None
None
Z
BC R,b
BS R,b
0 R(b)
1 R(b)
JBC R,b
JBS R,b
CALL k
LCALL k
JMP k
if R(b)=0, skip
if R(b)=1, skip
PC+1 [Stack], (Page, k) PC
PC+1 [Stack], K PC
(Page, k) PC
K PC
LJMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
BANK k
ADD A,k
k A
A k A
A & k A
Z
A k A
Z
k A, [Top of Stack] PC
k-A A
None
Z, C, DC
None
Z, C, DC
kR5(2:0)
k+A A
Note: 1 This instruction cannot operate under interrupt status register.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
93
EM78P520N
8-Bit Microprocessor with OTP ROM
7 Absolute Maximum Ratings
Rating
Items
Symbol
Condition
Unit
Min.
Max.
5.5
Supply voltage
VDD
VI
2.3
V
V
Input voltage
Port 7 ~ Port 9, Port A ~ Port C GND-0.3
Port 7 ~ Port 9, Port A ~ Port C GND-0.3
VDD+0.3
VDD+0.3
85
Output voltage
VO
V
Operation temperature
Storage temperature
Power dissipation
Operating Frequency (2clk)
TOPR
TSTG
PD
-40
-65
C
C
mW
Hz
150
500
32.768K
16M
8 DC Electrical Characteristics
8.1 DC Electrical Characteristics
Ta= 25C, VDD= 5.0V5%, VSS= 0V
Symbol
Parameter
Condition
Two cycles with two clocks
R: 51K
Min.
Typ.
Max.
Unit
MHz
MHz
Fc
Crystal: VDD to 5V
0.1
16
ERIC ERIC: VDD to 5V
F-20% 2.2221 F+20%
Input Leakage Current
for input pins
IIL
VIN = VDD, VSS
Ports 7, 8, 9, A, B, C
Ports 7, 8, 9, A, B, C
/RESET, INT
-1
0
1
A
V
Input High Voltage
VIH1
0.75VDD
-0.3V
VDD+0.3V
0.25VDD
VDD+0.3V
0.25VDD
(Schmitt Trigger)
Input Low Voltage
VIL1
V
(Schmitt Trigger)
Input High Threshold
VIHT1
0.75VDD
-0.3V
V
Voltage (Schmitt Trigger)
Input Low Threshold
VILT1
/RESET, INT
V
Voltage (Schmitt Trigger)
VIHX1 Clock Input High Voltage OSCI in crystal mode
VILX1 Clock Input Low Voltage OSCI in crystal mode
High Drive Current 1
0.75VDD
-0.3V
VDD+0.3V
0.25VDD
V
V
IOH1
IOH2
IOL1
IOL2
VOH = VSS+2.1V
VOH = VDD-0.1VDD
VOL = VDD-2.1
8
7
10
9
15
12
15
21
mA
mA
mA
mA
(Port 9) LED enabled
High Drive Current 2
(Ports 7, 8, 9, A, B, C)
Low Sink Current 1
(Port 9) LED enabled
8
10
18
Low Sink Current 2
(Ports 7, 8, 9, A, B, C)
VOL = VSS+0.1VDD
16
94
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Symbol
Parameter
Condition
Min. Typ. Max. Unit
IPH1 Pull-high current
Pull-high active, input pin at VSS
Ta = 25C
-70
2.31
2.04
2.9
-75
2.6
2.6
3.3
3.3
3.9
3.9
-80
A
V
2.89
3.15
3.72
4.05
4.33
4.71
Low Voltage Reset Level
LVR1
LVR2
LVR3
1 (2.6V)
Ta = -40C ~ 85C
Ta = 25C
V
V
Low Voltage Reset Level
2 (3.3V)
Ta = -40C ~ 85C
Ta = 25C
2.53
3.46
3.06
V
V
Low Voltage Reset Level
3 (3.9V)
Ta = -40C ~ 85C
V
Stop mode
ISB1
ISB2
WDT disabled
1.1
6.6
A
A
A
A
Power down current
All input and I/O pins
at VDD
Output pin floating
Stop mode
WDT enabled
Power down current
/RESET= 'High', CPU OFF,
Sub-oscillator clock (32.768kHz) ON,
Output pin floating, WDT disabled
ICC1 Idle mode current
ICC2 Idle mode current
4.7
/RESET= 'High', CPU OFF,
Sub-oscillator clock (32.768kHz) ON,
Output pin floating, WDT enabled,
10.3
/RESET= 'High', CPU OFF,
Sub-oscillator clock (32.768kHz) ON,
Output pin floating, WDT disabled,
LCD enabled
ICC3 Idle mode current
23.7
A
/RESET= 'High', CPU ON, used
Sub-oscillator clock (32.768kHz),
Output pin floating, WDT enabled,
ICC4 Green mode current
ICC5 Normal mode
21.4
1.48
3.45
A
mA
mA
/RESET= 'High', Fosc=4 MHz
(Crystal type, CLKS="0"),
Output pin floating, WDT enabled
/RESET= 'High', Fosc=16 MHz
(Crystal type, CLKS="0"),
ICC6 Normal mode
Output pin floating, WDT enabled
LCD Voltage
RLCD
Ta = 25C
80
KΩ
A
A
Dividing Resistor
VLCD=5V, exclude CPU core
operation current (not panel)
ILCD1 All LCD lighting
ILCD2 All LCD lighting
23.3
12.9
VLCD=3V, exclude CPU core
operation current (not panel)
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference use only.
2. Data under minimum, typical, and maximum (Min., Typ., and Max.) columns are based on
hypothetical results at 25°C. These data are for design reference only.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
95
EM78P520N
8-Bit Microprocessor with OTP ROM
8.2 A/D Converter Characteristics
VDD=2.5V to 5.5V, Vss=0V, Ta=-40 to 85 C
Parameter Condition
Analog reference voltage VREF – VSS ≥ 2.5V
Symbol
VREF
VSS
Min.
2.5
Typ.
Max.
VDD
VSS
VREF
1000
+10
Unit
V
VSS
VSS
750
-10
V
VAI
Analog input voltage
Analog supply current
V
Ivdd
IAI1
850
0
µA
µA
µA
µA
VDD=VREF=5.0V, VSS = 0.0V
(V reference from VDD)
Ivref
Ivdd
IAI2
500
200
600
250
820
VDD=VREF=5.0V, VSS = 0.0V
(V reference from VREF)
Analog supply current
Ivref
300
ADREF=0, Internal VDD
VDD=5.0V, VSS = 0.0V
RN1
RN2
Resolution
Resolution
9
10
12
Bits
Bits
ADREF=1, External VREF
11
VDD=VREF=5.0V, VSS = 0.0V
LN1
LN2
Linearity error
Linearity error
VDD= 2.5 to 5.5V Ta=25C
VDD= 2.5 to 5.5V Ta=25C
0
0
±4
±2
±8
±4
LSB
LSB
Differential non-linear
error
DNL
VDD= 2.5 to 5.5V Ta=25C
0
±0.5
±0.9
LSB
FSE1
FSE2
OE
Full scale error
Full scale error
Offset error
VDD=5.0V, VASS = 0.0V
±0
±0
±0
±4
±2
±2
±8
±4
±4
LSB
LSB
LSB
VDD=VREF=5.0V, VSS = 0.0V
VDD=VREF=5.0V, VSS = 0.0V
Recommended
ZAI
impedance of analog
voltage source
0
8
10
KΩ
ADIV
A/D input voltage range VDD =VREF=5.0V, VSS = 0.0V
0
0
0.2
4.8
VREF
0.3
5
V
V
VDD =VREF=5.0V, VSS = 0.0V,
RL=10K
ADOV
A/D output voltage swing
4.7
4
TAD
TCN
PSR
A/D clock period
VDD=VREF=5.0V, VSS = 0.0V
VDD=VREF=5.0V, VSS = 0.0V
µs
A/D conversion time
15
±0
15
TAD
LSB
Power Supply Rejection VDD=5.0V±0.5V
±2
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference only.
2. There is no current consumption when ADC is off other than minor leakage current.
3. AD conversion result will not decrease when the input voltage is increased, and no missing code
will result.
96
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
8.3 Phase Lock Loop Characteristics
8.3.1 PLL DC Electrical Characteristics
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VD
Digital Supply Voltage
4.5
5.5
V
8.3.2 AC Electrical Characteristics
Parameter
Input Clock
Condition
Min
Typ
Max
Unit
kHz
32.768
CLK2 CLK1 CLK0
Output Clock
1
1
X
15.99
MHz
μA
Normal
3
600
1
Current Consumption
Power Down Mode
μA
Lock Up Time
Settling Time
200
5
μs
ms
Note: 1. These parameters are hypothetical (not tested) and are provided for design reference
only.
2. These parameters are subject to change without further notice.
8.4 Device Characteristics
The graphs provided in the following pages were derived based on a limited number of
samples and are shown here for reference only. The device characteristics illustrated
herein are not guaranteed for its accuracy. In some graphs, the data may be out of the
specified warranted operating range.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
97
EM78P520N
8-Bit Microprocessor with OTP ROM
Vih/Vil (Input Pins with Inverter)
5
Vih max (-40°C to 85°C)
4.5
Vih typ 25°C
4
Vih min (-40°C to 85°C)
3.5
3
2.5
2
1.5
1
Vil max (-40°C to 85°C)
Vil typ 25°C
0.5
0
Vil min (-40°C to 85°C)
2
2.5
3
3.5
4
4.5
5
5.5
Vdd (Volt)
Figure 8-1 Vih, Vil vs. VDD
Voh_Ioh(VDD=5V)
0.00
-5.00
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
-40.00
-45.00
-40°C
25°C
85°C
0
0.5
1
1.5
2
2.5
Voh (Volt)
3
3.5
4
4.5
5
Figure 8-2 Voh vs. Ioh, VDD=5V
Voh_IOh(VDD=3V)
0.00
-2.00
-4.00
-6.00
-8.00
-40°C
25°C
85°C
-10.00
-12.00
-14.00
-16.00
0
0.5
1
1.5
Voh(Volt)
2
2.5
3
Figure 8-3 Voh vs. Ioh, VDD=3V
98
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Vol/Iol(5V)
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
-40°C
25°C
85°C
0
0.5
1
1.5
2 2.5 3
Vol(Volt)
3.5
4
4.5
5
Figure 8-4 Vol vs. Iol, VDD=5V
Vol/Iol(3V)
40.00
35.00
30.00
25.00
20.00
15.00
10.00
5.00
-40°C
25°C
85°C
0.00
0
0.5
1
1.5
2
2.5
3
Vol(Volt)
Figure 8-5 Vol vs. Iol, VDD=3V
WDT Time out
35.00
30.00
25.00
20.00
15.00
10.00
-40°C
25°C
85°C
2
2.5
3
3.5 4
VDD(Volt)
4.5
5
5.5
Figure 8-6 WDT Time out Period vs. VDD, with Prescaler set to 1:1
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
99
EM78P520N
8-Bit Microprocessor with OTP ROM
ERIC FOR MAIN OSC
2.5
2.0
1.5
1.0
0.5
0.0
51K
100K
300K
2.1
2.5
3
3.5
4
4.5
5
5.5
VDD(volt)
Figure 8-7 ERIC fosc vs. VDD
ERIC FOR SUB OSC
35.0
34.5
34.0
33.5
33.0
32.5
2.2M
2.1
2.5
3
3.5
4
4.5
5
5.5
VDD(Volt)
Figure 8-8 ERIC fs vs. VDD
ERC OSC Frequency vs Temp. (Cext=100pF, Rext=5.1K)
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
3V
5V
-40 -30 -20 -10
0
10
Temperature (°C)
Figure 8-9 ERIC fosc vs. Temperature
20
30
40
50
60
70
80
100
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
There are two conditions with the Standby Current ISB1 and ISB2. These conditions
are as follows:
ISB1: WDT disable (Sleep mode)
ISB2: WDT enable (Sleep mode)
Typical ISB1 and ISB2 VS Temperature (VDD=3V)
4
3
ISB2
ISB1
2
1
0
-40
-20
0
25
50
70
85
Temperature (°C)
Figure 8-11 Typical Standby Current (VDD=3V) vs. Temperature
Maximum ISB1 and ISB2 VS Temperature (VDD=3V)
4
3
2
1
0
ISB2
ISB1
-40
-20
0
25
50
70
85
Temperature (°C)
Figure 8-12 Maximum Standby Current (VDD=3V) vs. Temperature
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
101
EM78P520N
8-Bit Microprocessor with OTP ROM
Typical ISB1 and ISB2 VS. Temperature(VDD=5V)
8
6
4
2
0
ISB2
ISB1
-40
-20
0
25
50
70
85
Temperature (°C)
Figure 8-13 Typical Standby Current (VDD=5V) vs. Temperature
Maximum ISB1 and ISB2 VS. Temperature (VDD=5V)
8
6
4
2
0
ISB2
ISB1
-40
-20
0
25
50
70
85
Temperature (°C)
Figure 8-14 Maximum Standby Current (VDD=5V) vs. Temperature
Four conditions exist with the Operating Current ICC1 to ICC6. These conditions are
as follows:
ICC1: Fosc = 32.768kHz, 2 clocks, WDT disable (Idle mode)
ICC2: Fosc = 32.768kHz, 2 clocks, WDT enable (Idle mode)
ICC4: Fosc = 32.768kHz, 2 clocks, WDT enable (Green mode)
ICC5: Fosc = 4 MHz, 2 clocks, WDT enable (Normal mode)
102
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Typical ICC1 and ICC2 VS Temperature (VDD=3V)
7
6
5
4
3
ICC2
ICC1
-40
-20
0
25
50
70
85
Temperature (°C)
Figure 8-15 Typical Operating Current (VDD=3V) vs. Temperature
Maximum ICC1 and ICC2 VS. Temperature (VDD=3V)
7
6
5
4
3
ICC2
ICC1
-40
-20
0
25
50
70
85
Temperature (°C)
Figure 8-16 Maximum Operating Current (VDD=3V) vs. Temperature
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
103
EM78P520N
8-Bit Microprocessor with OTP ROM
Typical ICC1 and ICC2 VS. Temperature (VDD=5V)
14
12
10
ICC2
ICC1
8
6
4
-40
-20
0
25
50
70
85
Temperature (°C)
Figure 8-17 Typical Operating Current (VDD=5V) vs. Temperature
Maximum ICC1 and ICC2 VS. Temperature (VDD=5V)
14
12
10
ICC2
ICC1
8
6
4
-40
-20
0
25
50
70
85
Temperature (°C)
Figure 8-18 Maximum Operating Current (VDD=5V) vs. Temperature
Typical ICC4 vs. Temperature
30
25
20
15
10
3V
5V
-40
-20
0
20
40
60
80
Temperature (°C)
Figure 8-19 Typical Operating Current vs. Temperature
104
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Maximum ICC4 vs. Temperature
35
30
25
20
15
3V
5V
-40
-20
0
20
40
60
80
80
80
Temperature (°C)
Figure 8-20 Maximum Operating Current vs. Temperature
Typical ICC5 vs. Temperature
3
3V
5V
2
1
0
-40
-20
0
20
40
60
Temperature (°C)
Figure 8-21 Typical Operating Current vs. Temperature
Maximum ICC5 vs. Temperature
3
2
1
0
3V
5V
-40
-20
0
20
40
60
Temperature (°C)
Figure 8-22 Maximum Operating Current vs. Temperature
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
105
EM78P520N
8-Bit Microprocessor with OTP ROM
9 AC Electrical Characteristics
(Ta=- 40C ~ 85 C, VDD=5V5%, GND=0V)
Symbol
Parameter
Conditions
Min.
45
Typ.
50
Max.
55
DC
DC
21.6
Unit
%
Dclk
Input CLK duty cycle
Crystal type
RC type
100
500
11.3
2000
11.3
ns
Instruction cycle time
(CLKS="0")
Tins
ns
Tdrh
Trst
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
Ta = 25 C
16.2
ms
ns
Ta = 25 C
Twdt
Tset
Ta = 25 C
16.2
0
21.6
ms
ns
Thold
Tdelay
Tiod
20
50
5
ns
Output pin delay time
I/O delay for EMI enable
Cload=20pF
Cload=150pF
ns
4
6
ns
Note: These parameters are theoretical values and have not been tested.
106
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
10 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5
0.75VDD
TEST POINTS
0.75VDD
0.25VDD
0.25VDD
GND+0.5
Note: AC Testing: Input are driven at VDD-0.5V for logic “1,” and VSS+0.5V for logic “0”
Timing measurements are made at 0.75VDD for logic “1,” and 0.25VDD for logic “0”
Figure 10-1a AC Test Input/Output Waveform Timing Diagram
Reset Timing (CLK="0")
Instruction 1
NOP
Executed
CLK
/RESET
Tdrh
Figure 10-1b Reset Timing Diagram
TCC Input Timing (CLKS="0")
ins
CLK
TCC
tcc
* n = 0, 2, 4, 6
Figure 10-1c TCC Input Timing Diagram
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
107
EM78P520N
8-Bit Microprocessor with OTP ROM
APPENDIX
A Ordering and Manufacturing Information
EM78P520NL48J
Material Type
J: RoHS complied
Pin Number
Package Type
K A: SKDIP
SO: SOP
Q: QFP
L: LQFP
Specific Annotation
Product Number
Product Type
P: OTP
Elan 8-bit Product
For example:
EM78P520NL48J
is EM78P520N with OTP program memory, industrial grade product,
in 48-pin LQFP 7x7mm package with RoHS complied
‧‧‧‧‧‧‧
Elan Product Number
EM78Paaaa
1041 bbbbbb
Batch Number
Manufacture Date
“YYWW”
YY is year and WW is week
‧‧‧‧‧‧‧
108
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
Ordering Code
EM78P520NL44J
Material Type
Contact Elan Sales for details
Package Type / Pin Number
Check the following section
Elan IC Product Number
B Package Type
OTP MCU
EM78P520NQ44
Package Type
Pin Count
Package Size
QFP
LQFP
LQFP
44
44
48
10mm 10mm
10mm 10mm
7mm 7mm
EM78P520NL44
EM78P520NL48
These are Green products which do not contain hazardous substances and comply
with the third edition of Sony SS-00259 standard.
Pb content is less than 100ppm and complies with Sony specifications.
Part No.
EM78P520NxJ/xS
Pure Tin
Electroplate type
Ingredient (%)
Melting point (°C)
Sn:100%
°
232 C
Electrical resistivity
11.4
( μΩ-cm )
Hardness (hv)
Elongation (%)
8~10
>50%
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
109
EM78P520N
8-Bit Microprocessor with OTP ROM
C Package Information
C.1 EM78P520NQ44
Symbol
A
Min.
Normal
Max.
2.70
0.50
2.20
A1
A2
b
0.15
1.80
2.00
0.30(TYP)
0.15(TYP)
13.20
c
E1
E
13.00
9.90
0.73
1.50
13.40
10.10
1.03
c
10.00
L
0.88
L1
e
1.60
1.70
0.80(TYP)
θ
0
7
TITLE:
QFP-44L(10*10 MM) FOOTPRINT 3.2mm
PACKAGE OUTLINE DIMENSION
F
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-3 EM78P520N 44-pin QFP Package Type
110
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
C.2 EM78P520NL44
Symbol
Min .
Normal
Max .
1.600
0.150
1.450
0.450
0.200
A
A1
A2
b
0.050
1.350
0.300
0.090
1.400
0.370
c
12.00 BASIC
10.00 BASIC
0.600
E1
E
c
L
0.450
0
0.750
7
L1
e
1.0 (BASIC)
0.8 (BASIC)
3.5
θ
TITLE:
LQFP-44L (10*10 MM) FOOTPRINT 2.0mm
PACKAGE OUTLINE DIMENSION
File :
LQFP44
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-4 EM78P520N 44-pin LQFP Package Type
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
111
EM78P520N
8-Bit Microprocessor with OTP ROM
C.3 EM78P520NL48
Symbol
A
Min.
Normal
Max.
1.60
0.15
1.45
0.27
0.23
0.20
0.160
D1
D
A1
A2
b
0.05
1.35
0.17
0.17
0.09
0.09
1.40
0.22
0.20
b1
c
c
c1
D
9.00BCS
7.00BSC
9.00BSC
7.00BSC
0.50BSC
0.60
D1
E
E1
e
0.45
0°
0.75
7°
L
L1
θ
1.00 REF
3.5°
TITLE:
LQFP-48L(7*7 MM) FOOTPRINT 2.0mm
PACKAGE OUTLINE DIMENSION
File :
LQFP48
Edtion: A
Unit : mm
Scale: Free
Material:
Sheet:1 of 1
Figure B-5 EM78P520N 48-pin LQFP Package Type
112
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
D Quality Assurance and Reliability
Test Category
Test Conditions
Remarks
Solder temperature=2455C, for 5 seconds up to the
stopper using a rosin-type flux
Solderability
Step 1: TCT, 65C (15mins)~150C (15min), 10 cycles
Step 2: Bake at 125C, TD (endurance) = 24 hrs
Step 3: Soak at 30C/60% , TD (endurance) = 192 hrs
Step 4: IR flow 3 cycles
For SMD IC (such as
SOP, QFP, SOJ, etc)
Pre-condition
(Pkg thickness 2.5mm or
Pkg volume 350mm3 ----2255C)
(Pkg thickness 2.5mm or
Pkg volume 350mm3 ----2405C )
-65C (15min)~150C (15min), 200 cycles
Temperature cycle test
Pressure cooker test
TA =121C, RH=100%, pressure = 2 atm,
TD (endurance)= 96 hrs
High temperature /
High humidity test
TA=85C , RH=85% , TD (endurance) = 168 , 500 hrs
TA=150C, TD (endurance) = 500, 1000 hrs
High-temperature
storage life
High-temperature
operating life
TA=125C, VDD=Max. operating voltage,
TD (endurance) =168, 500, 1000 hrs
Latch-up
TA=25C, VDD=Max. operating voltage, 150mA/20V
TA=25C, | ± 3KV |
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
ESD (HBM)
ESD (MM)
TA=25C, | ± 300V |
VDD-VSS(+),VDD_VSS
(-) mode
D.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects
MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an
instruction from a certain section of ROM, an internal recovery circuit is auto started. If
a noise caused address error is detected, the MCU will repeat execution of the program
until the noise is eliminated. The MCU will then continue to execute the next program.
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
113
EM78P520N
8-Bit Microprocessor with OTP ROM
E EM78P520N Program Pin List
DWTR is used to program the EM78P520N IC’s. The connector of DWTR is selected
by CON3 (EM78P447). The software is selected by EM78P520N.
LQFP-48
L/QFP-44
Program Pin Name
IC Pin Name
Pin Number Pin Number
Pin #31
Pin #30
Pin #28
Pin #8
P75
P76
2
3
2
3
P77
4
4
VDD
VSS
TEST
PC2
PC3
5
5
Pin #10
Pin #34
Pin #29
Pin #32
6
6
9
9
10
11
10
11
F ICE 520 Oscillator Circuit (JP4)
F.1 Mode 1
Main oscillator: Crystal mode, Sub oscillator: Crystal mode
Crystal
GND
GND
Xin
Xout
GND
GND
VDD
VDD
Xin
Sub oscillator
Main oscillator
JP4
OSCI
OSCI
OSCO
Crystal
114
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
EM78P520N
8-Bit Microprocessor with OTP ROM
F.2 Mode 2
Main oscillator: PLL mode, Sub oscillator: Crystal mode
Crystal
GND
GND
Xin
Xout
GND
GND
VDD
VDD
Xin
Sub oscillator
Main oscillator
JP4
OSCI
OSCI
OSCO
PLL
F.3 Mode 3
Main oscillator: ERIC mode, Sub oscillator: Crystal mode
Crystal
GND
GND
Xin
Xout
GND
GND
VDD
VDD
Xin
Sub oscillator
Main oscillator
JP4
OSCI
OSCI
OSCO
ERIC
F.4 Mode 4
Main oscillator: Crystal mode, Sub oscillator: ERIC mode
ERIC
GND
GND
Xin
Xout
GND
GND
VDD
VDD
Xin
Sub oscillator
Main oscillator
JP4
OSCI
OSCI
OSCO
Crystal
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
115
EM78P520N
8-Bit Microprocessor with OTP ROM
F.5 Mode 5
Main oscillator: PLL mode, Sub oscillator: RC mode
ERIC
GND
GND
Xin
Xout
GND
GND
VDD
VDD
Xin
Sub oscillator
Main oscillator
JP4
OSCI
OSCI
OSCO
PLL
F.6 Mode 6
Main oscillator: RC mode, Sub oscillator: RC mode
ERIC
GND
GND
Xin
Xout
GND
GND
VDD
VDD
Xin
Sub oscillator
Main oscillator
JP4
OSCI
OSCI
OSCO
ERIC
F.7 Mode 7
Main oscillator: Crystal mode, Sub oscillator: None
None
GND
GND
Xin
Xout
GND
GND
VDD
VDD
Xin
Sub oscillator
Main oscillator
JP4
OSCI
OSCI
OSCO
Crystal
116
Product Specification (V1.4) 04.08.2016
(This specification is subject to change without prior notice)
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