EM6161V32AT-10S [EMLSI]
64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM; 64K X16位超低功耗和低电压全CMOS静态RAM
| 型号： | EM6161V32AT-10S |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM |
| 文件： | 总11页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Document Title
Low Power, 64Kx16 SRAM
64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
0.1
InitialDraft
2’ nd Draft
May 9 , 2003
February 13 , 2004
Add Pb-free part number
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
FEATURES
GENERAL DESCRIPTION
• Process Technology : 0.18mm Full CMOS
• Organization : 64K x 16 bit
• Power Supply Voltage : 2.7V ~ 3.6V
• Low Data Retention Voltage : 1.5V(Min.)
• Three state output and TTL Compatible
• Package Type : 48-FPBGA 6.0x7.0
The EM610FV16 families are fabricated by EMLSI’ s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami-
lies also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc Range
Speed
PKG Type
Standby
(ISB1, Typ.)
Operating
(ICC1.Max.)
Industrial (-40 ~ 85oC)
551) /70ns
0.5mA2)
EM610FV16
2.7V~3.6V
3 mA
48-FPBGA
1. The parameter is measured with 30pF test load.
2. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Pre-charge Circuit
A
B
C
D
E
LB
I/O9
OE
UB
A0
A3
A1
A4
A6
A2
CS2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
VCC
VSS
CS1 I/O1
I/O2 I/O3
I/O4 VCC
Memory Array
I/O10 I/O11 A5
1024 x 1024
VSS I/O12 DNU A7
VCC I/O13 DNU DNU I/O5 VSS
Data
Cont
I/O1 ~ I/O8
I/O Circuit
Data
Cont
I/O9 ~ I/O16
Column Select
F
I/O15 I/O14 A14
I/O16 DNU A12
A15
A13
A10
I/O6 I/O7
WE I/O8
A11 DNU
G
H
A
10
A11
A
12
A13 A14 A15
DNU A8
A9
48-FPBGA : Top view (ball down)
WE
OE
UB
LB
Control Logic
CS
1
Name
Function
Name
Function
CS
2
CS ,CS
Chip select inputs
Vcc Power Supply
1
2
OE
WE
Output Enable input
Write Enable input
Vss Ground
UB Upper Byte (I/O
)
9~16
A ~A
Address Inputs
LB
Lower Byte (I/O
)
1~8
0
15
I/O ~I/O
Data Inputs/outputs
DNU Do Not Use
1
16
2
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
Unit
V
-0.2 to Vcc+0.3(Max. 4.0V)
-0.2 to 4.0V
1.0
V
PD
W
oC
Operating Temperature
TA
-40 to 85
* Stresses greater than those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
LB
UB
I/O1-8
I/O9-16
Mode
Power
H
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
H
H
L
X
X
X
H
H
H
H
H
L
X
X
H
L
X
X
H
X
L
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
Deselected
Deselected
Stand by
Stand by
Stand by
Active
X
H
H
H
H
H
H
H
H
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X
L
Active
H
L
Active
L
H
L
Active
L
L
Data Out Data Out
Active
X
X
X
L
H
L
Data In
High-Z
Data In
High-Z
Data In
Data In
Lower Byte Write
Upper Byte Write
Word Write
Active
L
H
L
Active
L
L
Active
Note: X means don’ t care. (Must be low or high state)
3
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Parameter
Supply voltage
Symbol
Min
2.7
0
Typ
3.3
0
Max
3.6
0
Unit
V
VCC
VSS
VIH
VIL
Ground
V
VCC + 0.22)
0.6
Input high voltage
Input low voltage
2.2
-
-
V
V
-0.23)
1. TA= -40 to 85oC, otherwise specified
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width< 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Input capacitance
Symbol
Test Condition
Min
Max
Unit
CIN
VIN=0V
-
-
8
pF
pF
Input/Ouput capacitance
CIO
VIO=0V
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ Max Unit
Input leakage current
ILI
V
=V
to V
SS CC
-1
-
-
-
1
1
3
mA
mA
IN
CS =V
or CS =V or OE=V or WE=V or LB=UB =V
2 IL IH IL IH
1
IH
ILO
ICC
Output leakage current
Operating power supply
-1
-
V
=V
to V
SS CC
IO
I
=0mA, CS =V , CS =WE=V , V =V or V
IL
mA
IO
1
IL
2
IH
IN
IH
Cycle time=1ms, 100% duty, I =0mA,
IO
ICC1
CS <0.2V, LB<0.2V or/and UB <0.2V, CS >V -0.2V,
-
-
3
mA
mA
1
2
CC
Average operating current
V
<0.2V or V >V -0.2V
IN IN CC
Cycle time = Min, I =0mA, 100% duty,
55ns
70ns
-
-
-
-
26
20
IO
ICC2
CS =V , CS =V LB=V or/and UB=V
1
IL
2
IH,
IL
IL ,
V
=V or V
IN
IL
IH
I
= 2.1mA
Output low voltage
Output high voltage
Standby Current (TTL)
VOL
VOH
ISB
-
2.4
-
-
-
-
0.4
-
V
V
OL
I
= -1.0mA
OH
CS =V , CS =V , Other inputs=V or V
1
IH
2
IL
IH
IL
0.3
mA
CS >V -0.2V, CS >V -0.2V (CS controlled)
1
CC
2
CC
1
or 0V<CS <0.2V (CS controlled),
2
2
LL
LF
Other inputs = 0~V
0.51)
CC
ISB1
Standby Current (CMOS)
-
5
mA
o
(Typ. condition : V =3.3V @ 25 C)
CC
o
(Max. condition : V =3.6V @ 85 C)
CC
NOTES
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
4
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
3)
VTM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
2)
R1
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
2)
R2
CL1)
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1=3070W,
R2=3150W
3. VTM=2.8V
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Unit
Symbol
Parameter
Read cycle time
Min
Max
Min
Max
tRC
tAA
tco1, tco2
tOE
55
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
-
55
55
25
55
-
-
-
-
70
70
35
70
-
Chip select to output
Output enable to valid output
UB, LB acess time
tBA
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
tLZ1, tLZ2
tBLZ
10
10
5
10
10
5
-
-
tOLZ
-
-
tHZ1, tHZ2
tBHZ
0
20
20
20
-
0
25
25
25
-
0
0
tOHZ
0
0
tOH
10
10
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Unit
Symbol
Parameter
Write cycle time
Min
Max
Min
Max
tWC
tCW1, tCW2
tAs
55
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
-
-
60
0
-
Address valid to end of write
UB, LB valid to end of write
Write pulse width
tAW
45
45
40
0
-
60
60
50
0
-
tBW
-
-
tWP
-
-
Write recovery time
tWR
-
-
Write to ouput high-Z
tWHZ
tDW
0
20
0
20
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
30
0
tDH
-
-
-
-
tOW
5
5
5
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL
)
tRC
Address
Data Out
tAA
tOH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO
CS1
CS2
tHZ
tBA
UB,LB
tBHZ
tOE
OE
tOHZ
tOLZ
High-Z
Data Out
Data Valid
tBLZ
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC
Address
tCW (2)
tWR(4)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
WE
tDH
tAS(3)
High-Z
tDW
High-Z
Data in
Data Valid
tWHZ
tOW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
7
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
tWC
Address
tCW(2)
tW R(4)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
tAS(3)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS1 goes high and WE goes high. The tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1
or WE going high.
8
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention
Symbol
VDR
Test Condition
Min
Typ2)
Max
Unit
ISB1 Test Condition
1.5
-
3.6
V
1)
(Chip Disabled)
VCC=1.5V, ISB1 Test Condition
(Chip Disabled) 1)
IDR
Data Retention Current
-
0.25
-
mA
Chip Deselect to Data Retention Time
Operation Recovery Time
tSDR
tRDR
0
-
-
-
-
See data retention wave form
ns
tRC
NOTES
1. See the ISB1 measurement condition of datasheet page 4.
2.Typical values are measured at TA=25oC and not 100% tested.
DATA RETENTION WAVE FORM
tRDR
tSDR
Data Retention Mode
Vcc
2.7V
2.2V
VDR
CS > Vcc-0.2V
1
CS1
GND
Data Retention Mode
Vcc
2.7V
CS2
tRDR
tSDR
VDR
0.4V
CS < 0.2V
2
GND
9
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
Unit: millimeters
PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch)
Bottom View
Top View
B
A1 index Mark
B
B1
0.5
6 5 4 3 2 1
A
B
C
D
E
F
#A1
G
H
B/2
Side View
D
Detail A
A
Y
C
Min
Typ
0.75
6.00
3.75
7.00
5.25
0.35
1.04
0.79
0.25
-
Max
A
B
-
-
5.93
6.03
-
NOTES.
B1
C
-
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75x0.75) (typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
6.93
7.03
-
C1
D
-
0.30
0.40
1.10
-
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
E
1.00
E1
E2
Y
-
-
-
-
0.08
10
EM610FV16 Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
11. Power
10. Speed
4. Option
9. Packages
8. Version
5. Technology
6. Operating Voltage
7. Orgainzation
1. Memory Component
8. Version
Blank ----------------- Mother Die
2. Device Type
A ----------------------- First revision
B ----------------------- Second revision
C ----------------------- Third revision
D ----------------------- Fourth revision
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ---------------------- FPBGA
S ---------------------------- 32 sTSOP1
T ---------------------------- 32 TSOP1
U ---------------------------- 44 TSOP2
W ---------------------------- Wafer
10. Speed
4. Option
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
0 ----------------------- Dual CS
1 ----------------------- Single CS
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
11. Power
6. Operating Voltage
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power (Pb-free)
L ---------------------- Low Power
S ---------------------- Standard Power
Blank ------------------ 5.0V
V ------------------------- 2.7V~3.6V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
11
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