EM680FP16FV-85L [EMLSI]

256K x8 bit Low Power and Low Voltage Full CMOS Static RAM; 256K ×8位低功耗和低电压全CMOS静态RAM


型号：	EM680FP16FV-85L
厂家：	Emerging Memory & Logic Solutions Inc
描述：	256K x8 bit Low Power and Low Voltage Full CMOS Static RAM 256K ×8位低功耗和低电压全CMOS静态RAM
文件：	总11页 (文件大小：433K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EM620FV8BS Series

Low Power, 256Kx8 SRAM

Document Title

256K x8 bit Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No.

History

Initial Draft

0.1 Revision

Draft Date

June 28, 2007

July 2, 2007

Remark

0.0

0.1

Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns),

tOE-55(30ns to 25ns), tWP-55(45ns to 40ns),

tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns),

ICC(2mA to 3mA), ICC1(2mA to 3mA)

0.2

0.3

0.2 Revision

0.3 Revision

_IHlevel change from 2.0V to 2.2V

Aug. 16, 2007

Nov. 13, 2007

Fix typo error

Emerging Memory & Logic Solutions Inc.

4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719

Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com

The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your

questions about device. If you have any questions, please contact the EMLSI office.

EM620FV8BS Series

Low Power, 256Kx8 SRAM

256K x8 Bit Low Power and Low Voltage CMOS Static RAM

GENERAL DESCRIPTION

FEATURES

The EM620FV8BS series are fabricated by EMLSI’s

advanced full CMOS process technology. The families

support industrial temperature range and Chip Scale Pack-

age for user flexibility of system design. The families also

supports low data retention voltage for battery back-up

operation with low data retention current.

- Process Technology : 0.15mm Full CMOS

- Organization :256K x8

- Power Supply Voltage

=> EM620FV8BS Series : 2.7V~3.6V

- Low Data Retention Voltage : 1.5V (MIN)

- Three state output and TTL Compatible

- Packaged product designed for 45/55/70ns

- Package Type: 32-sTSOP1

The EM620FV8BS series are available in KGD, JEDEC

standard 32 pin 8mm x 13.4mm sTSOP package.

PRODUCT FAMILY

Power Dissipation

Product

Family

Operating

Temperature

Vcc Range

Speed

PKG Type

Standby

Operating

(I_CC1.Max)

(I_SB1, Typ.)

Industrial (-40 ~ 85^oC)

EM620FV8BS-45LF

EM620FV8BS-55LF

EM620FV8BS-70LF

2.7V~3.6V

45ns

55ns

70ns

1 µA

3mA

32-sTSOP

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

Pre-charge Circuit

A11

A10

CS1

I/O 7

I/O 6

I/O 5

I/O 4

I/O 3

VSS

I/O 2

I/O 1

A13

CS2

A15

VCC

A17

A16

A14

A12

Memory Array

1024 x 2048

EM620FV8BS-45LF

Data

Cont

I/O0 ~ I/O7

I/O Circuit

I/O 0

Column Select

15 16

10 11 12 13

Name

Function

Name

Vcc

Vss

Function

CS1,CS2

Chip select inputs

Output Enable input

Write Enable input

Address Inputs

Power Supply

Ground

Control Logic

CS1

CS2

No Connection

A0~A17

I/O0~I/O7

Data Inputs/Outputs

EM620FV8BS Series

Low Power, 256Kx8 SRAM

ABSOLUTE MAXIMUM RATINGS *

Parameter

Voltage on Any Pin Relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

Symbol

V_IN, V_OUT

V_CC

Minimum

-0.2 to 4.0V

1.0

Unit

P_D

^oC

Operating Temperature

T_A

-40 to 85

Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-

ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods

may affect reliability.

FUNCTIONAL DESCRIPTION

CS1

CS2

I/O_0-7

Mode

Power

High-Z

Deselected

Output Disabled

Read

Stand by

Active

High-Z

Data Out

Data In

Active

Write

Active

Note: X means don’t care. (Must be low or high state)

EM620FV8BS Series

Low Power, 256Kx8 SRAM

RECOMMENDED DC OPERATING CONDITIONS

Parameter

Supply voltage

Symbol

Min

2.7

Typ

3.3

Max

3.6

Unit

V_CC

Ground

V_SS

V_IH

V_CC+ 0.2²⁾

0.6

Input high voltage

2.2

-0.2³⁾

Input low voltage

V_IL

1. T_A= -40 to 85^oC, otherwise specified

2. Overshoot: VCC +2.0 V in case of pulse width < 20ns

3. Undershoot: -2.0 V in case of pulse width < 20ns

4. Overshoot and undershoot are sampled, not 100% tested

CAPACITANCE (f =1MHz, T =25 C)

Item

Input capacitance

Symbol

Test Condition

Min

Max

Unit

C_IN

C_IO

V_IN=0V

Input/Ouput capacitance

V_IO=0V

1. Capacitance is sampled, not 100% tested.

DC AND OPERATING CHARACTERISTICS

Parameter

Symbol

Test Conditions

Min

Typ Max

Unit

I_LI

=V to V

SS CC

Input leakage current

-1

CS1=V or CS2=V or OE=V or WE=V

I_LO

I_CC

Output leakage current

Operating power supply

=V to V

SS CC

=0mA, CS1=V , CS2=WE=V , V =V or V

Cycle time=1µs, 100% duty, I =0mA,

I_CC1

CS1<0.2V, CS2>V -0.2V,

<0.2V or V >V -0.2V

IN CC

45ns

55ns

70ns

0.4

Average operating current

Cycle time = Min, I =0mA, 100% duty,

I_CC2

CS1=V , CS2=V

IH,

=V or V

V_OL

V_OH

I_SB

= 2.1mA

Output low voltage

Output high voltage

Standby Current (TTL)

= -1.0mA

2.4

CS1=V , CS2=V , Other inputs=V or V

0.3

CS1>V -0.2V, CS2>V -0.2V (CS1 controlled)

or 0V<CS2<0.2V (CS2 controlled),

Other inputs = 0~V

1¹⁾

I_SB1

Standby Current (CMOS)

(Typ. condition : V =3.3V @ 25 C)

(Max. condition : V =3.6V @ 85 C)

NOTES

1. Typical values are measured at Vcc=3.3V, T_A=25^oC and not 100% tested.

EM620FV8BS Series

Low Power, 256Kx8 SRAM

AC OPERATING CONDITIONS

Test Conditions (Test Load and Test Input/Output Reference)

V_TM

R₁

Input Pulse Level : 0.4 to 2.2V

Input Rise and Fall Time : 5ns

Input and Output reference Voltage : 1.5V

Output Load (See right) : CL¹⁾= 100pF + 1 TTL (70ns)

R₂

CL¹⁾

CL¹⁾= 30pF + 1 TTL (45ns/55ns)

1. Including scope and Jig capacitance

2. R₁=3070 ohm

3. V_TM=2.8V

R₂=3150 ohm

4. CL = 5pF + 1 TTL (measurement with t_LZ1,2, t_HZ1,2, t_OLZ, t_OHZ, t_WHZ

)

READ CYCLE (V = 2.7V to 3.6V, Gnd = 0V, T = -40 C to +85 C)

45ns

55ns

70ns

Max

Symbol

Parameter

Unit

Min

Max

Min

Max

Min

Read cycle time

t_RC

t_AA

t_CO1,t_CO2

t_OE

t_LZ1,t_LZ2

t_OLZ

t_HZ1,t_HZ2

t_OHZ

Address access time

Chip select to output

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

t_OH

WRITE CYCLE (V = 2.7V to 3.6V, Gnd = 0V, T = -40 C to +85 C)

Parameter

Write cycle time

45ns

55ns

70ns

Unit

Symbol

Min

Max

Min

Max

Min

Max

t_WC

t_CW1,t_CW2

t_AS

Chip select to end of write

Address setup time

Address valid to end of write

Write pulse width

t_AW

t_WP

Write recovery time

t_WR

Write to ouput high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

t_WHZ

t_DW

t_DH

t_OW

EM620FV8BS Series

Low Power, 256Kx8 SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=V , CS2=WE=V )

t_RC

Address

Data Out

t_AA

t_OH

Previous Data Valid

Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE = V )

t_RC

Address

t_AA

t_CO1,2

t_OH

CS1

CS2

t_HZ1,2

t_OE

t_OHZ

t_OLZ

High-Z

Data Out

Data Valid

t_WHZ

t_LZ1,2

NOTES (READ CYCLE)

1. t_HZ1,2and t_OHZare defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, t_HZ1,2(Max.) is less than t_LZ1,2(Min.) both for a given device and from device to

device interconnection.

EM620FV8BS Series

Low Power, 256Kx8 SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)

t_WC

Address

t_CW1,2(2)

t_WR(4)

CS1

CS2

t_AW

t_WP(1)

t_DH

t_AS(3)

t_DW

High-Z

Data in

High-Z

Data Valid

t_WHZ

t_OW

Data out

Data Undefined

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)

t_WC

Address

tAS(3)

t_CW1,2(2)

t_WR(4)

CS1

CS2

t_AW

t_WP(1)

t_DH

t_DW

Data in

Data out

Data Valid

High-Z

EM620FV8BS Series

Low Power, 256Kx8 SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED)

t_WC

Address

t_CW1,2(2)

_WR(4)

CS1

tAS(3)

CS2

t_AW

t_WP(1)

t_DH

t_DW

Data in

Data Valid

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(t_WP) of low CS1, a high CS2 and low WE. A write begins at the latest

transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition

among CS1 goes high, CS2 goes low and WE goes high. The t_WPis measured from the beginning of write

to the end of write.

2. t_CWis measured from the CS1 going low or CS2 going high to end of write.

3. t_ASis measured from the address valid to the beginning of write.

4. t_WRis measured from the end or write to the address change. t_WRapplied in case a write ends as CS1

or WE going high or CS2 going low.

EM620FV8BS Series

Low Power, 256Kx8 SRAM

DATA RETENTION CHARACTERISTICS

Parameter

V_CCfor Data Retention

Symbol

V_DR

Test Condition

Min

Typ²⁾Max

Unit

I_SB1Test Condition

(Chip Disabled) ¹⁾

1.5

3.6

5.0

V_CC=1.5V, I_SB1Test Condition

(Chip Disabled) ¹⁾

I_DR

Data Retention Current

0.5

µA

Chip Deselect to Data Retention Time

Operation Recovery Time

t_SDR

t_RDR

See data retention wave form

t_RC

NOTES

1. See the I_SB1measurement condition of data sheet page 4.

2. Typical value is measured at T_A=25^oC and not 100% tested.

DATA RETENTION WAVE FORM

t_RDR

t_SDR

Data Retention Mode

V_cc

3.0V

2.2V

V_DR

CS1 > Vcc-0.2V

CS1

GND

Data Retention Mode

V_cc

3.0V

CS2

t_RDR

t_SDR

V_DR

0.4V

CS2 < 0.2V

GND

EM620FV8BS Series

Low Power, 256Kx8 SRAM

PACKAGE DIMENSIONS

32Pin - sTSOP Type1

Unit : millimeters/Inches

+/-0.20

13.40

0.528

+/- 0.008

0.10

MAX

0.004

+0.10

0.20

- 0.05

+0.004

0.008

- 0.002

#32

0.25

0.010

(

)

8.00

8.40

MAX

0.331

0.315

0.50

0.0197

#16

#17

+/-0.10

1.00

0.039 _{+/- 0.004}

0.05

MIN

0.25

0.010

11.80

+/-0.10

0.465 _{+/- 0.004}

0.002

TYP

+0.10

- 0.05

0.15

1.20

MAX

0.047

+0.004

0.006

- 0.002

0~8

0.50

0.020

0.45~0.75

)

(

0.018~0.030

EM620FV8BS Series

Low Power, 256Kx8 SRAM

SRAM PART CODING SYSTEM

EM X XX X X X XX X X - XX XX

1. EMLSI Memory

2. Product Type

3. Density

11. Power

10. Speed

4. Function

9. Package

8. Generation

7. Organization

5. Technology

6. Operating Voltage

1. Memory Component

7. Organization

EM --------------------- Memory

8 ---------------------- x8 bit

16 ---------------------- x16 bit

2. Product Type

6 ------------------------ SRAM

8. Generation

Blank ----------------- 1st generation

A ----------------------- 2nd generation

B ----------------------- 3rd generation

C ----------------------- 4th generation

D ----------------------- 5th generation

E ----------------------- 6th generation

F ----------------------- 7th generation

G ---------------------- 8th generation

3. Density

1 ------------------------- 1M

2 ------------------------- 2M

4 ------------------------- 4M

8 ------------------------- 8M

4. Function

0 ----------------------- Dual CS

1 ----------------------- Single CS

9. Package

2 ----------------------- Multiplexed

Blank ---------------- KGD, 48&36FpBGA

S ---------------------- 32 sTSOP1

T ---------------------- 32 TSOP1

U ---------------------- 44 TSOP2

V ---------------------- 32 SOP

3 ------------- Single CS / LBB, UBB(tBA=tOE)

4 ------------- Single CS / LBB, UBB(tBA=tCO)

5 ------------- Dual CS / LBB, UBB(tBA=tOE)

6 ------------- Dual CS / LBB, UBB(tBA=tCO)

5. Technology

F ------------------------- Full CMOS

10. Speed

45 ---------------------- 45ns

55 ---------------------- 55ns

70 ---------------------- 70ns

85 ---------------------- 85ns

10 ---------------------- 100ns

12 ---------------------- 120ns

6. Operating Voltage

T ------------------------- 5.0V

V ------------------------- 3.3V

U ------------------------- 3.0V

S ------------------------- 2.5V

R ------------------------- 2.0V

P ------------------------- 1.8V

11. Power

LL ---------------------- Low Low Power

LF ---------------------- Low Low Power(Pb-Free & Green)

L ---------------------- Low Power

S ---------------------- Standard Power

EM680FP16FV-85L [EMLSI]

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