EM685FU16FU-10S
更新时间：2024-10-29 05:34:29
品牌：EMLSI
描述：256K x8 bit Low Power and Low Voltage Full CMOS Static RAM
概述
数据手册EM685FU16FU-10S 概述
256K x8 bit Low Power and Low Voltage Full CMOS Static RAM 256K ×8位低功耗和低电压全CMOS静态RAM
EM685FU16FU-10S 数据手册
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PDF下载EM620FU8BS Series
Low Power, 256Kx8 SRAM
Document Title
256K x8 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
History
Draft Date
Remark
0.0
0.1
Initial Draft
Oct. 31, 2007
Nov. 16, 2007
0.1 Revision
Fix typo error
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM620FU8BS Series
Low Power, 256Kx8 SRAM
256K x8 Bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
The EM620FU8BS-45LF is fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale Pack-
age for user flexibility of system design. The families also
supports low data retention voltage for battery back-up
operation with low data retention current.
- Process Technology : 0.15mm Full CMOS
- Organization :256K x8
- Power Supply Voltage
=> EM620FU8BS-45LF : 2.7~3.3V
- Low Data Retention Voltage : 1.5V (MIN)
- Three state output and TTL Compatible
- Packaged product designed for 45/55/70ns
- Package Type: 32-sTSOP1
The EM620FU8BS is available in KGD, JEDEC standard
32 pin 8mm x 13.4mm sTSOP
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc Range
Speed
PKG Type
Standby
(ISB1, Typ.)
Operating
(ICC1.Max)
Industrial (-40 ~ 85oC)
Industrial (-40 ~ 85oC)
Industrial (-40 ~ 85oC)
EM620FU8BS-45LF
EM620FU8BS-55LF
EM620FU8BS-70LF
2.7V~3.3V
2.7V~3.3V
2.7V~3.3V
45ns
55ns
70ns
1 µA
1 µA
1 µA
3mA
3mA
3mA
32-sTSOP
32-sTSOP
32-sTSOP
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Pre-charge Circuit
A11
A9
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
OE
A10
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CS1
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
VSS
I/O 2
I/O 1
I/O 0
A0
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
VCC
VSS
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
Memory Array
1024 x 2048
EM620FU8BS-45LF
Data
Cont
I/O0 ~ I/O7
I/O Circuit
Column Select
A6
A5
A4
A14
A15
A16
A11
A13
A10
A12
A17
Name
Function
Name
Vcc
Vss
Function
WE
OE
CS1,CS2
OE
Chip select inputs
Output Enable input
Write Enable input
Address Inputs
Power Supply
Ground
Control Logic
CS1
CS2
WE
NC
No Connection
A0~A17
I/O0~I/O7
Data Inputs/Outputs
2
EM620FU8BS Series
Low Power, 256Kx8 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Minimum
-0.2 to 4.0V
-0.2 to 4.0V
1.0
Unit
V
V , V
IN
OUT
V
V
CC
P
W
D
o
Operating Temperature
T
-40 to 85
A
C
* Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
I/O
Mode
Power
0-7
H
X
L
L
L
X
L
X
X
H
L
X
X
H
H
L
High-Z
High-Z
Deselected
Deselected
Output Disabled
Read
Stand by
Stand by
Active
H
H
H
High-Z
Data Out
Data In
Active
X
Write
Active
Note: X means don’t care. (Must be low or high state)
3
EM620FU8BS Series
Low Power, 256Kx8 SRAM
1)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply voltage
Symbol
Min
2.7
0
Typ
3.0
0
Max
3.3
0
Unit
V
V
CC
Ground
V
V
V
SS
2)
Input high voltage
V
2.0
-
-
IH
V
+ 0.2
CC
3)
Input low voltage
V
0.6
V
IL
-0.2
1. TA= -40 to 85oC, otherwise specified
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
1)
o
CAPACITANCE (f =1MHz, T =25 C)
A
Item
Input capacitance
Symbol
Test Condition
V =0V
Min
Max
Unit
C
-
8
pF
IN
IO
IN
Input/Ouput capacitance
C
V =0V
-
10
pF
IO
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ Max
Unit
ILI
VIN=VSS to VCC
Input leakage current
-1
-1
-
-
-
-
1
1
3
uA
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL
VIO=VSS to VCC
ILO
ICC
Output leakage current
Operating power supply
uA
IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL
mA
Cycle time=1µs, 100% duty, IIO=0mA,
CS1<0.2V, CS2>VCC-0.2V,
ICC1
-
-
3
mA
mA
VIN<0.2V or VIN>VCC-0.2V
45ns
55ns
70ns
-
-
-
-
-
-
-
-
35
30
25
0.4
Average operating current
Cycle time = Min, IIO=0mA, 100% duty,
CS1=VIL, CS2=VIH,
ICC2
VIN=VIL or VIH
VOL
VOH
ISB
IOL = 2.1mA
Output low voltage
Output high voltage
Standby Current (TTL)
V
V
IOH = -1.0mA
2.4
-
-
-
-
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled)
0.3
mA
or 0V<CS2<0.2V (CS2 controlled),
Other inputs = 0~VCC
11)
ISB1
Standby Current (CMOS)
LF
-
10
uA
o
(Typ. condition : VCC=3.0V @ 25 C)
o
(Max. condition : VCC=3.3V @ 85 C)
NOTES
1. Typical values are measured at Vcc=3.0V, T =25oC and not 100% tested.
A
4
EM620FU8BS Series
Low Power, 256Kx8 SRAM
3)
VTM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
2)
R1
Input Pulse Level : 0.4V to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
1)
Output Load (See right) : CL = 100pF + 1 TTL (55ns)
2)
R2
1)
1)
CL
CL = 30pF + 1 TTL (45ns/55ns)
1. Including scope and Jig capacitance
2. R =3070 ohm,
R =3150 ohm
2
1
3. V =2.8V
TM
4. CL = 5pF + 1 TTL (measurement with t
, t
, t
, t
, t
)
LZ1,2 HZ1,2 OLZ OHZ WHZ
o
o
READ CYCLE (V = 2.7V to 3.3V, Gnd = 0V, T = -40 C to +85 C)
cc
A
45ns
Max
55ns
Max
70ns
Min Max
Symbol
Parameter
Unit
Min
Min
Read cycle time
tRC
tAA
tCO1, tCO2
tOE
tLZ1, tLZ2
tOLZ
tHZ1, tHZ2
tOHZ
45
-
55
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
45
45
25
-
-
-
55
55
25
-
70
70
35
-
Chip select to output
-
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
-
-
-
10
5
10
5
10
5
-
-
-
0
20
15
-
0
20
20
-
0
25
25
-
0
0
0
tOH
10
10
10
o
o
WRITE CYCLE (V = 2.7V to 3.3V, Gnd = 0V, T = -40 C to +85 C)
cc
Parameter
Write cycle time
A
45ns
Max
55ns
Max
70ns
Unit
Symbol
Min
Min
Min
Max
tWC
tCW1, tCW2
tAS
45
-
-
55
-
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
45
0
60
0
-
-
-
-
Address valid to end of write
Write pulse width
tAW
45
35
0
-
45
40
0
-
60
50
0
-
tWP
-
-
-
Write recovery time
tWR
-
-
-
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
tWHZ
tDW
0
15
0
20
0
20
25
0
25
0
30
0
tDH
-
-
-
-
-
-
tOW
5
5
5
5
EM620FU8BS Series
Low Power, 256Kx8 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
t
RC
Address
Data Out
t
AA
t
OH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
t
RC
Address
t
AA
t
OH
t
CO1,2
CS1
CS2
t
HZ1,2
t
OE
OE
t
t
OHZ
OLZ
High-Z
Data Out
Data Valid
t
LZ1,2
NOTES (READ CYCLE)
1. tHZ1,2 and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to
device interconnection.
6
EM620FU8BS Series
Low Power, 256Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
t
WC
Address
t
(2)
t
(4)
CW1,2
WR
CS1
CS2
t
AW
t
(1)
WP
WE
t
DH
t
(3)
t
AS
DW
High-Z
High-Z
Data in
Data Valid
t
WHZ
t
OW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
t
WC
Address
tAS(3)
t
(2)
t
(4)
WR
CW1,2
CS1
CS2
t
AW
t
(1)
WP
WE
t
DH
t
DW
Data in
Data out
Data Valid
High-Z
High-Z
7
EM620FU8BS Series
Low Power, 256Kx8 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED)
t
WC
Address
t
(2)
t
(4)
CW1,2
WR
CS1
CS2
tAS(3)
t
AW
t
(1)
WP
WE
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest
transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition
among CS1 goes high, CS2 goes low and WE goes high. The tWP is measured from the beginning of write
to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1
or WE going high or CS2 going low.
8
EM620FU8BS Series
Low Power, 256Kx8 SRAM
DATA RETENTION CHARACTERISTICS
2)
Parameter
VCC for Data Retention
Symbol
VDR
Test Condition
Min
Typ
Max
Unit
ISB1 Test Condition
(Chip Disabled) 1)
1.5
-
3.3
V
VCC=1.5V, ISB1 Test Condition
(Chip Disabled) 1)
IDR
Data Retention Current
-
0.5
5.0
µA
Chip Deselect to Data Retention Time
Operation Recovery Time
tSDR
tRDR
0
-
-
-
-
See data retention wave form
ns
tRC
NOTES
1. See the I
measurement condition of data sheet page 4.
SB1
o
2. Typical value is measured at T =25 C and not 100% tested.
A
DATA RETENTION WAVE FORM
t
t
RDR
Data Retention Mode
SDR
V
cc
3.0V
2.2V
V
DR
CS1 > Vcc-0.2V
CS1
GND
Data Retention Mode
V
cc
3.0V
CS2
t
t
RDR
SDR
V
DR
0.4V
CS2 < 0.2V
GND
9
EM620FU8BS Series
Low Power, 256Kx8 SRAM
PACKAGE DIMENSIONS
32Pin - sTSOP Type1
Unit : millimeters/Inches
13.40 +/-0.20
0.528+/- 0.008
0.10
MAX
0.004
+0.10
0.20
0.008- 0.002
#1
- 0.05
+0.004
#32
0.25
0.010
(
)
8.40
8.00
0.315
MAX
0.331
0.50
0.0197
#16
#17
1.00 +/-0.10
0.039+/- 0.004
0.05
MI N
0.002
0.25
TYP
11.80 +/-0.10
0.465+/- 0.004
0.010
+0.10
- 0.05
+0.004
0.15
1.20
0.006- 0.002 0.047
MAX
0~8
0.50
0.020
0.45~0.75
0.018~0.030
)
(
10
EM620FU8BS Series
Low Power, 256Kx8 SRAM
SRAM PART CODING SYSTEM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Product Type
3. Density
11. Power
10. Speed
4. Function
9. Package
8. Generation
7. Organization
5. Technology
6. Operating Voltage
1. Memory Component
7. Organization
EM --------------------- Memory
8 ---------------------- x8 bit
16 ---------------------- x16 bit
2. Product Type
6 ------------------------ SRAM
8. Generation
Blank ----------------- 1st generation
A ----------------------- 2nd generation
B ----------------------- 3rd generation
C ----------------------- 4th generation
D ----------------------- 5th generation
E ----------------------- 6th generation
F ----------------------- 7th generation
G ---------------------- 8th generation
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
9. Package
2 ----------------------- Multiplexed
Blank ---------------- KGD, 48&36FpBGA
S ---------------------- 32 sTSOP1
T ---------------------- 32 TSOP1
U ---------------------- 44 TSOP2
V ---------------------- 32 TSOP
3 ------------- Single CS / LBB, UBB(tBA=tOE)
4 ------------- Single CS / LBB, UBB(tBA=tCO)
5 ------------- Dual CS / LBB, UBB(tBA=tOE)
6 ------------- Dual CS / LBB, UBB(tBA=tCO)
5. Technology
10. Speed
F ------------------------- Full CMOS
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 ---------------------- 100ns
12 ---------------------- 120ns
6. Operating Voltage
T ------------------------- 5.0V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free & Green)
L ---------------------- Low Power
S ---------------------- Standard Power
11
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