EM685FU16FU-12S [EMLSI]

256K x8 bit Low Power and Low Voltage Full CMOS Static RAM; 256K ×8位低功耗和低电压全CMOS静态RAM


型号：	EM685FU16FU-12S
厂家：	Emerging Memory & Logic Solutions Inc
描述：	256K x8 bit Low Power and Low Voltage Full CMOS Static RAM 256K ×8位低功耗和低电压全CMOS静态RAM
文件：	总11页 (文件大小：349K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EM620FU8BS Series

Low Power, 256Kx8 SRAM

Document Title

256K x8 bit Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No.

History

Draft Date

Remark

0.0

0.1

Initial Draft

Oct. 31, 2007

Nov. 16, 2007

0.1 Revision

Fix typo error

Emerging Memory & Logic Solutions Inc.

4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719

Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com

The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your

questions about device. If you have any questions, please contact the EMLSI office.

EM620FU8BS Series

Low Power, 256Kx8 SRAM

256K x8 Bit Low Power and Low Voltage CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

The EM620FU8BS-45LF is fabricated by EMLSI’s

advanced full CMOS process technology. The families

support industrial temperature range and Chip Scale Pack-

age for user flexibility of system design. The families also

supports low data retention voltage for battery back-up

operation with low data retention current.

- Process Technology : 0.15mm Full CMOS

- Organization :256K x8

- Power Supply Voltage

=> EM620FU8BS-45LF : 2.7~3.3V

- Low Data Retention Voltage : 1.5V (MIN)

- Three state output and TTL Compatible

- Packaged product designed for 45/55/70ns

- Package Type: 32-sTSOP1

The EM620FU8BS is available in KGD, JEDEC standard

32 pin 8mm x 13.4mm sTSOP

PRODUCT FAMILY

Power Dissipation

Product

Family

Operating

Temperature

Vcc Range

Speed

PKG Type

Standby

(I_SB1, Typ.)

Operating

(I_CC1.Max)

Industrial (-40 ~ 85^oC)

EM620FU8BS-45LF

EM620FU8BS-55LF

EM620FU8BS-70LF

2.7V~3.3V

45ns

55ns

70ns

1 µA

3mA

32-sTSOP

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

Pre-charge Circuit

A11

A10

CS1

I/O 7

I/O 6

I/O 5

I/O 4

I/O 3

VSS

I/O 2

I/O 1

I/O 0

A₀

A₁

A₂

A₃

A₄

A₅

A₆

A₇

A₈

A₉

V_CC

V_SS

A13

CS2

A15

VCC

A17

A16

A14

A12

Memory Array

1024 x 2048

EM620FU8BS-45LF

Data

Cont

I/O0 ~ I/O7

I/O Circuit

Column Select

A₁₄

A₁₅

A₁₆

A₁₁

A₁₃

A₁₀

A₁₂

A₁₇

Name

Function

Name

Vcc

Vss

Function

CS1,CS2

Chip select inputs

Output Enable input

Write Enable input

Address Inputs

Power Supply

Ground

Control Logic

CS1

CS2

No Connection

A0~A17

I/O0~I/O7

Data Inputs/Outputs

EM620FU8BS Series

Low Power, 256Kx8 SRAM

ABSOLUTE MAXIMUM RATINGS *

Parameter

Voltage on Any Pin Relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

Symbol

Minimum

-0.2 to 4.0V

1.0

Unit

V , V

OUT

Operating Temperature

-40 to 85

* Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-

ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods

may affect reliability.

FUNCTIONAL DESCRIPTION

CS1

CS2

I/O

Mode

Power

0-7

High-Z

Deselected

Output Disabled

Read

Stand by

Active

High-Z

Data Out

Data In

Active

Write

Active

Note: X means don’t care. (Must be low or high state)

EM620FU8BS Series

Low Power, 256Kx8 SRAM

RECOMMENDED DC OPERATING CONDITIONS

Parameter

Supply voltage

Symbol

Min

2.7

Typ

3.0

Max

3.3

Unit

Ground

Input high voltage

2.0

+ 0.2

Input low voltage

0.6

-0.2

1. TA= -40 to 85^oC, otherwise specified

2. Overshoot: VCC +2.0 V in case of pulse width < 20ns

3. Undershoot: -2.0 V in case of pulse width < 20ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE (f =1MHz, T =25 C)

Item

Input capacitance

Symbol

Test Condition

V =0V

Min

Max

Unit

Input/Ouput capacitance

V =0V

1. Capacitance is sampled, not 100% tested.

DC AND OPERATING CHARACTERISTICS

Parameter

Symbol

Test Conditions

Min

Typ Max

Unit

I_LI

V_IN=V_SSto V_CC

Input leakage current

-1

CS1=V_IHor CS2=V_ILor OE=V_IHor WE=V_IL

V_IO=V_SSto V_CC

I_LO

I_CC

Output leakage current

Operating power supply

I_IO=0mA, CS1=V_IL, CS2=WE=V_IH, V_IN=V_IHor V_IL

Cycle time=1µs, 100% duty, I_IO=0mA,

CS1<0.2V, CS2>V_CC-0.2V,

I_CC1

V_IN<0.2V or V_IN>V_CC-0.2V

45ns

55ns

70ns

0.4

Average operating current

Cycle time = Min, I_IO=0mA, 100% duty,

CS1=V_IL, CS2=V_IH,

I_CC2

V_IN=V_ILor V_IH

V_OL

V_OH

I_SB

I_OL= 2.1mA

Output low voltage

Output high voltage

Standby Current (TTL)

I_OH= -1.0mA

2.4

CS1=V_IH, CS2=V_IL, Other inputs=V_IHor V_IL

CS1>V_CC-0.2V, CS2>V_CC-0.2V (CS1 controlled)

0.3

or 0V<CS2<0.2V (CS2 controlled),

Other inputs = 0~V_CC

1¹⁾

I_SB1

Standby Current (CMOS)

(Typ. condition : V_CC=3.0V @ 25 C)

(Max. condition : V_CC=3.3V @ 85 C)

NOTES

1. Typical values are measured at Vcc=3.0V, T =25^oC and not 100% tested.

EM620FU8BS Series

Low Power, 256Kx8 SRAM

V_TM

AC OPERATING CONDITIONS

Test Conditions (Test Load and Test Input/Output Reference)

R₁

Input Pulse Level : 0.4V to 2.2V

Input Rise and Fall Time : 5ns

Input and Output reference Voltage : 1.5V

Output Load (See right) : CL = 100pF + 1 TTL (55ns)

R₂

CL = 30pF + 1 TTL (45ns/55ns)

1. Including scope and Jig capacitance

2. R =3070 ohm,

R =3150 ohm

3. V =2.8V

4. CL = 5pF + 1 TTL (measurement with t

, t

)

LZ1,2 HZ1,2 OLZ OHZ WHZ

READ CYCLE (V = 2.7V to 3.3V, Gnd = 0V, T = -40 C to +85 C)

45ns

Max

55ns

Max

70ns

Min Max

Symbol

Parameter

Unit

Min

Read cycle time

t_RC

t_AA

t_CO1,t_CO2

t_OE

t_LZ1,t_LZ2

t_OLZ

t_HZ1,t_HZ2

t_OHZ

Address access time

Chip select to output

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

t_OH

WRITE CYCLE (V = 2.7V to 3.3V, Gnd = 0V, T = -40 C to +85 C)

Parameter

Write cycle time

45ns

Max

55ns

Max

70ns

Unit

Symbol

Min

Max

t_WC

t_CW1,t_CW2

t_AS

Chip select to end of write

Address setup time

Address valid to end of write

Write pulse width

t_AW

t_WP

Write recovery time

t_WR

Write to ouput high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

t_WHZ

t_DW

t_DH

t_OW

EM620FU8BS Series

Low Power, 256Kx8 SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=V_IL, CS2=WE=V_IH)

Address

Data Out

Previous Data Valid

Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE = V_IH)

Address

CO1,2

CS1

CS2

HZ1,2

OHZ

OLZ

High-Z

Data Out

Data Valid

LZ1,2

NOTES (READ CYCLE)

1. t_HZ1,2and t_OHZare defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, t_HZ1,2(Max.) is less than t_LZ1,2(Min.) both for a given device and from device to

device interconnection.

EM620FU8BS Series

Low Power, 256Kx8 SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)

Address

(2)

(4)

CW1,2

CS1

CS2

(1)

(3)

High-Z

Data in

Data Valid

WHZ

Data out

Data Undefined

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)

Address

tAS(3)

(2)

(4)

CW1,2

CS1

CS2

(1)

Data in

Data out

Data Valid

High-Z

EM620FU8BS Series

Low Power, 256Kx8 SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED)

Address

(2)

(4)

CW1,2

CS1

CS2

tAS(3)

(1)

Data in

Data Valid

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(t_WP) of low CS1, a high CS2 and low WE. A write begins at the latest

transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition

among CS1 goes high, CS2 goes low and WE goes high. The t_WPis measured from the beginning of write

to the end of write.

2. t_CWis measured from the CS1 going low or CS2 going high to end of write.

3. t_ASis measured from the address valid to the beginning of write.

4. t_WRis measured from the end or write to the address change. t_WRapplied in case a write ends as CS1

or WE going high or CS2 going low.

EM620FU8BS Series

Low Power, 256Kx8 SRAM

DATA RETENTION CHARACTERISTICS

Parameter

V_CCfor Data Retention

Symbol

V_DR

Test Condition

Min

Typ

Max

Unit

I_SB1Test Condition

(Chip Disabled) ¹⁾

1.5

3.3

V_CC=1.5V, I_SB1Test Condition

(Chip Disabled) ¹⁾

I_DR

Data Retention Current

0.5

5.0

µA

Chip Deselect to Data Retention Time

Operation Recovery Time

t_SDR

t_RDR

See data retention wave form

t_RC

NOTES

1. See the I

measurement condition of data sheet page 4.

SB1

2. Typical value is measured at T =25 C and not 100% tested.

DATA RETENTION WAVE FORM

RDR

Data Retention Mode

SDR

3.0V

2.2V

CS1 > Vcc-0.2V

CS1

GND

Data Retention Mode

3.0V

CS2

RDR

SDR

0.4V

CS2 < 0.2V

GND

EM620FU8BS Series

Low Power, 256Kx8 SRAM

PACKAGE DIMENSIONS

32Pin - sTSOP Type1

Unit : millimeters/Inches

13.40 _+/-0.20

0.528_{+/- 0.008}

0.10

MAX

0.004

+0.10

0.20

0.008_{- 0.002}

- 0.05

+0.004

#32

0.25

0.010

(

)

8.40

8.00

0.315

MAX

0.331

0.50

0.0197

#16

#17

1.00 _+/-0.10

0.039_{+/- 0.004}

0.05

MI N

0.002

0.25

TYP

11.80 _+/-0.10

0.465_{+/- 0.004}

0.010

+0.10

- 0.05

+0.004

0.15

1.20

0.006_{- 0.002}0.047

MAX

0~8

0.50

0.020

0.45~0.75

0.018~0.030

)

(

EM620FU8BS Series

Low Power, 256Kx8 SRAM

SRAM PART CODING SYSTEM

EM X XX X X X XX X X - XX XX

1. EMLSI Memory

2. Product Type

3. Density

11. Power

10. Speed

4. Function

9. Package

8. Generation

7. Organization

5. Technology

6. Operating Voltage

1. Memory Component

7. Organization

EM --------------------- Memory

8 ---------------------- x8 bit

16 ---------------------- x16 bit

2. Product Type

6 ------------------------ SRAM

8. Generation

Blank ----------------- 1st generation

A ----------------------- 2nd generation

B ----------------------- 3rd generation

C ----------------------- 4th generation

D ----------------------- 5th generation

E ----------------------- 6th generation

F ----------------------- 7th generation

G ---------------------- 8th generation

3. Density

1 ------------------------- 1M

2 ------------------------- 2M

4 ------------------------- 4M

8 ------------------------- 8M

4. Function

0 ----------------------- Dual CS

1 ----------------------- Single CS

9. Package

2 ----------------------- Multiplexed

Blank ---------------- KGD, 48&36FpBGA

S ---------------------- 32 sTSOP1

T ---------------------- 32 TSOP1

U ---------------------- 44 TSOP2

V ---------------------- 32 TSOP

3 ------------- Single CS / LBB, UBB(tBA=tOE)

4 ------------- Single CS / LBB, UBB(tBA=tCO)

5 ------------- Dual CS / LBB, UBB(tBA=tOE)

6 ------------- Dual CS / LBB, UBB(tBA=tCO)

5. Technology

10. Speed

F ------------------------- Full CMOS

45 ---------------------- 45ns

55 ---------------------- 55ns

70 ---------------------- 70ns

85 ---------------------- 85ns

10 ---------------------- 100ns

12 ---------------------- 120ns

6. Operating Voltage

T ------------------------- 5.0V

V ------------------------- 3.3V

U ------------------------- 3.0V

S ------------------------- 2.5V

R ------------------------- 2.0V

P ------------------------- 1.8V

11. Power

LL ---------------------- Low Low Power

LF ---------------------- Low Low Power(Pb-Free & Green)

L ---------------------- Low Power

S ---------------------- Standard Power

EM685FU16FU-12S [EMLSI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E