EM710FS32DW-12LL [EMLSI]

512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM; 512K ×8位超低功耗和低电压全CMOS静态RAM


型号：	EM710FS32DW-12LL
厂家：	Emerging Memory & Logic Solutions Inc
描述：	512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM 512K ×8位超低功耗和低电压全CMOS静态RAM
文件：	总11页 (文件大小：71K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Document Title

Low Power, 512Kx8 SRAM

512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM

Revision History

Revision No.

History

Draft Date

Remark

0.0

Initial Draft

October 24,2002

Preliminary

0.1

0.2

2’ nd Draft

3’rd Draft

Changed Icc, Icc1 value

November 11 , 2002

December 23 , 2002

Changed I_SB1test conditions,

Changed VDR & IDR

measurement condition

0.3

4’ th Draft

Add Pb-free part number

February 13 , 2004

Emerging Memory & Logic Solutions Inc.

IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160

Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com

The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your

questions about device. If you have any questions, please contact the EMLSI office.

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

FEATURES

GENERAL DESCRIPTION

• Process Technology : 0.18mm Full CMOS

• Organization : 512K x 8 bit

• Power Supply Voltage : 1.65V ~ 2.2V

• Low Data Retention Voltage : 1.0V(Min)

• Three state outputs

The EM640FP8 families are fabricated by EMLSI’ s

advanced full CMOS process technology. The families

support industrial temperature range and Chip Scale

Package for user flexibility of system design. The fami-

lies also supports low data retention voltage for battery

back-up operation with low data retention current.

• Package Type : 36-FPBGA 6.0x7.0

PRODUCT FAMILY

Power Dissipation

Product

Family

Operating

Temperature

Vcc Range

Speed

PKG Type

Standby

(I_SB1, Typ)

Operating

(I_CC1.Max)

36 FPBGA

(6.0x7.0)

Industrial (-40 ~ 85^oC)

1.65~2.2V

70ns¹⁾

EM640FP8

1 mA

2 mA

1. The parameter is measured with 30pF test load.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Pre-charge Circuit

A₀

A₁

A₂

CS₂

A₃

A₄

A₆

A₇

A₈

A₀

A₁

A₂

A₃

A₄

A₅

A₆

A₇

A₈

A₉

A₁₀

V_CC

V_SS

I/O₅

I/O₆

V_SS

V_CC

I/O₇

I/O₈

A₉

I/O₁

I/O₂

V_CC

V_SS

I/O₃

I/O₄

A₁₄

Memory Array

DNU A₅

2048 x 2048

Data

Cont

I/O1 ~ I/O4

I/O Circuit

Data

Cont

I/O5 ~ I/O8

Column Select

A₁₈

CS₁

A₁₁

A₁₇

A₁₆

A₁₂

A₁₅

A₁₃

₁₁A₁₂A₁₃A₁₄A₁₅A₁₆A₁₇A

A₁₀

36-FPBGA : Top view (ball down)

Control Logic

Name

Function

Name

Function

CS ,CS

Chip select inputs

WE Write Enable input

Output Enable input

Address Inputs

Vcc Power Supply

Vss Ground

A ~A

I/O ~I/O

Data Inputs/outputs

DNU Do Not Use

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

ABSOLUTE MAXIMUM RATINGS *

Parameter

Symbol

V_IN, V_OUT

V_CC

Ratings

Unit

Voltage on Any Pin Relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

-0.5V to VCC+0.3V (Max.2.5V)

-0.3V to 2.5V

1.0

P_D

^oC

T_A

Operating Temperature

-40 to 85

* Stresses greater than those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

FUNCTIONAL DESCRIPTION

CS₁

CS₂

I/O

Mode

Deselected

Output Disabled

Read

Power

Stand by

Active

High-Z

Data Out

Data In

Active

Write

Active

Note: X means don’ t care. (Must be low or high state)

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

RECOMMENDED DC OPERATING CONDITIONS ¹⁾

Parameter

Supply voltage

Symbol

Min

1.65

Typ

1.8

Max

2.2

Unit

V_CC

V_SS

V_IH

V_IL

Ground

V_CC+ 0.3²⁾

0.4

Input high voltage

Input low voltage

1.4

-0.3³⁾

1. TA= -40 to 85^oC, otherwise specified

2. Overshoot: VCC +1.0 V in case of pulse width < 20ns

3. Undershoot: -1.0 V in case of pulse width < 20ns

4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE¹⁾(f =1MHz, T_A=25^oC)

Item

Input capacitance

Symbol

Test Condition

Min

Max

Unit

C_IN

V_IN=0V

V_IO=0V

Input/Ouput capacitance

C_IO

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Parameter

Symbol

Test Conditions

Min

-1

Typ Max

Unit

=V to V

SS CC

I_LI

Input leakage current

Output leakage current

Operating power supply

I_LO

CS =V , CS =V or OE=V or WE=V , V =V

to V

SS CC

=0mA, CS =V , CS =WE=V , V =V or V

1 IL 2 IH IN IH IL

I_CC

Cycle time=1ms, 100% duty, I =0mA,

I_CC1

CS <0.2V, CS >V -0.2V,

<0.2V or V >V -0.2V

IN CC

Average operating current

Cycle time = Min, I =0mA, 100% duty,

I_CC2

CS =V , CS =V

=V or V

70ns

IH, IN

= 0.1mA

V_OL

V_OH

Output low voltage

Output high voltage

0.2

= -0.1mA

1.4

CS >V -0.2V, CS >V -0.2V (CS controlled)

or 0V<CS <0.2V (CS controlled),

Other inputs=0 ~ V

I_SB1

Standby Current (CMOS)

(Typ. condition : V =1.8V @ 25 C)

(Max. condition : V =2.2V @ 85 C)

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

V_TM

AC OPERATING CONDITIONS

Test Conditions (Test Load and Test Input/Output Reference)

R₁

Input Pulse Level : 0.2V to VCC-0.2V

Input Rise and Fall Time : 5ns

Input and Output reference Voltage : 0.9V

Output Load (See right) : CL = 100pF+ 1 TTL

R₂

CL¹⁾

CL¹⁾= 30pF + 1 TTL

1. Including scope and Jig capacitance

2. R₁=3070W,

R₂=3150W

3. V_TM=1.8V

READ CYCLE (V_cc=1.65 to 2.2V, Gnd = 0V, T_A= -40^oC to +85^oC)

70ns

Symbol

Parameter

Read cycle time

Unit

Max

Min

t_RC

t_AA

t_co1,t_co2

t_OE

t_LZ1,t_LZ2

t_OLZ

t_HZ1,t_HZ2

t_OHZ

Address access time

Chip select to output

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

t_OH

WRITE CYCLE (V_cc=1.65 to 2.2V, Gnd = 0V, T_A= -40^oC to +85^oC)

70ns

Unit

Symbol

Parameter

Write cycle time

Min

Max

t_WC

t_CW1,t_CW2

t_As

Chip select to end of write

Address setup time

Address valid to end of write

Write pulse width

t_AW

t_WP

Write recovery time

t_WR

Write to ouput high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

t_WHZ

t_DW

t_DH

t_OW

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS₁=OE=V_IL, CS₂=WE=V_IH

)

t_RC

Address

t_AA

t_OH

Previous Data Valid

Data Valid

Data Out

TIMING WAVEFORM OF READ CYCLE(2) (WE = V_IH)

t_RC

Address

t_AA

t_OH

t_CO

CS₁

CS₂

t_HZ

t_OE

t_OHZ

t_OLZ

High-Z

Data Out

Data Valid

t_LZ

NOTES (READ CYCLE)

1. t_HZand t_OHZare defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.

2. At any given temperature and voltage condition, t_HZ(Max.) is less than t_LZ(Min.) both for a given device and from device to device

interconnection.

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)

t_WC

Address

t_CW(2)

t_WR(4)

CS₁

CS₂

t_AW

t_WP(1)

t_DH

t_AS(3)

High-Z

t_DW

High-Z

t_OW

Data in

Data Valid

t_WHZ

Data out

Data Undefined

TIMING WAVEFORM OF WRITE CYCLE(2) (CS₁CONTROLLED)

t_WC

Address

tAS(3)

t_CW(2)

t_WR(4)

CS₁

CS₂

t_AW

t_WP(1)

t_DH

t_DW

Data in

Data Valid

High-Z

Data out

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

TIMING WAVEFORM OF WRITE CYCLE(3) ( CS₂CONTROLLED)

t_WC

Address

t_CW(2)

t_{W R}(4)

CS₁

t_AS(3)

CS₂

t_AW

t_WP(1)

t_DH

t_DW

Data in

Data Valid

High-Z

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(t_WP) of low CS₁, a high CS₂and low WE. A write begins at the latest

transition among CS₁goes low, CS₂goes high and WE goes low. A write ends at the earliest transition

when CS₁goes high, CS₂goes hagh and WE goes high. The t_WPis measured from the beginning of write

to the end of write.

2. t_CWis measured from the CS₁going low to end of write.

3. t_ASis measured from the address valid to the beginning of write.

4. t_WRis measured from the end or write to the address change. t_WRapplied in case a write ends as CS₁or WE

going high.

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

DATA RETENTION CHARACTERISTICS

Parameter

V_CCfor Data Retention

Symbol

V_DR

Test Condition

Min

Typ

Max

Unit

I_SB1Test Condition

1.0

2.2

(Chip Disabled)

V_CC=1.2V, I_SB1Test Condition

(Chip Disabled) ¹⁾

I_DR

Data Retention Current

0.5

t_SDR

t_RDR

Chip Deselect to Data Retention Time

Operation Recovery Time

See data retention wave form

t_RC

NOTES

1. See the I_SB1measurement condition of datasheet page 4.

DATA RETENTION WAVE FORM

CS₁Controlled

t_RDR

t_SDR

Data Retention Mode

V_cc

1.65V

1.4V

V_DR

CS > Vcc-0.2V

CS₁

GND

CS₂Controlled

Data Retention Mode

V_cc

1.65V

CS₂

t_RDR

t_SDR

V_DR

0.4V

CS < 0.2V

GND

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

Unit: millimeters

PACKAGE DIMENSION

36 Ball Fine Pitch BGA (0.75mm ball pitch)

Bottom View

Top View

A1 index Mark

0.5

6 5 4 3 2 1

#A1

B/2

Side View

Detail A

Min

Typ

0.75

6.00

3.75

7.00

5.25

0.35

1.04

0.79

0.25

Max

5.95

6.05

NOTES.

1. Bump counts : 36(8row x 6column)

2. Bump pitch : (x,y)=(0.75x0.75) (typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

6.95

7.05

0.30

0.40

1.10

4. Typ : Typical

5. Y is coplanarity : 0.08(Max)

1.00

0.08

EM640FP8 Series

merging Memory & Logic Solutions Inc.

Low Power, 512Kx8 SRAM

MEMORY FUNCTION GUIDE

EM X XX X X X XX X X - XX XX

1. EMLSI Memory

2. Device Type

3. Density

11. Power

10. Speed

4. Option

9. Packages

8. Version

5. Technology

6. Operating Voltage

7. Orgainzation

1. Memory Component

8. Version

Blank ----------------- Mother Die

2. Device Type

A ----------------------- First revision

B ----------------------- Second revision

C ----------------------- Third revision

D ----------------------- Fourth revision

6 ------------------------ Low Power SRAM

7 ------------------------ STRAM

3. Density

1 ------------------------- 1M

2 ------------------------- 2M

4 ------------------------- 4M

8 ------------------------- 8M

16 ----------------------- 16M

32 ----------------------- 32M

64 ----------------------- 64M

9. Package

Blank ---------------------- Package

W --------------------- Wafer

10. Speed

45 ---------------------- 45ns

55 ---------------------- 55ns

70 ---------------------- 70ns

85 ---------------------- 85ns

10 --------------------- 100ns

12 --------------------- 120ns

4. Option

0 ----------------------- Dual CS

1 ----------------------- Single CS

5. Technology

11. Power

Blank ------------------ CMOS

F ------------------------ Full CMOS

LL ---------------------- Low Low Power

LF ---------------------- Low Low Power(Pb-Free)

L ---------------------- Low Power

S ---------------------- Standard Power

6. Operating Voltage

Blank ------------------- 5V

V ------------------------- 3.3V

U ------------------------- 3.0V

S ------------------------- 2.5V

R ------------------------- 2.0V

P ------------------------- 1.8V

7. Orginzation

8 ---------------------- x8 bit

16 ---------------------- x16 bit

32 ---------------------- x32 bit

EM710FS32DW-12LL [EMLSI]

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