EM710FV16BW-12L [EMLSI]
64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM; 64K X16位超低功耗和低电压全CMOS静态RAM
| 型号： | EM710FV16BW-12L |
| 厂家： | 
Emerging Memory & Logic Solutions Inc |
| 描述： | 64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM |
| 文件： | 总11页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Document Title
Low Power, 64Kx16 SRAM
64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
0.1
InitialDraft
2’ nd Draft
May 9 , 2003
February 13 , 2004
Add Pb-free part number
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
FEATURES
GENERAL DESCRIPTION
• Process Technology : 0.18mm Full CMOS
• Organization : 64K x 16 bit
• Power Supply Voltage : 2.7V ~ 3.6V
• Low Data Retention Voltage : 1.5V(Min.)
• Three state output and TTL Compatible
• Package Type : 44-TSOP2
The EM611FV16U families are fabricated by EMLSI’ s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami-
lies also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc Range
Speed
PKG Type
Standby
(ISB1, Typ.)
Operating
(ICC1.Max.)
Industrial (-40 ~ 85oC)
551) /70ns
0.5 mA2)
EM611FV16U
2.7V~3.6V
3 mA
44 TSOP2
1. The parameter is measured with 30pF test load.
2. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
Pre-charge Circuit
A4
A3
A2
A1
A0
44
43
42
41
A5
A6
A7
OE
2
3
4
5
40
39
UB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
6
VCC
VSS
CS
LB
7
I/O1
38
I/O16
8
9
I/O2
I/O3
37
36
I/O15
Memory Array
I/O14
10
11
I/O4
VCC
VSS
35
34
33
I/O13
VSS
1024 x 1024
44 - TSOP2
12
13
VCC
I/O5
I/O6
32
31
I/O12
I/O11
14
15
I/O7
I/O8
30
I/O10
16
17
29
28
I/O9
NC
Data
Cont
I/O1 ~ I/O8
WE
I/O Circuit
18
19
20
Data
Cont
A15
27
26
25
A8
I/O9 ~ I/O16
Column Select
A14
A13
A9
A10
21
22
A12
NC
24
A11
NC
23
A
10
A11
A
12
A13 A14 A15
WE
OE
UB
LB
Control Logic
Name
Function
Name
Function
CS
CS
OE
WE
Chip select input
Vcc Power Supply
Vss Ground
Output Enable input
Write Enable input
UB Upper Byte (I/O
)
9~16
A ~A
Address Inputs
LB
Lower Byte (I/O
)
1~8
0
15
I/O ~I/O
Data Inputs/outputs
16
NC No Connection
1
2
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
VIN, VOUT
VCC
Ratings
Unit
V
-0.2 to Vcc+0.3(Max. 4.0V)
-0.2 to 4.0V
1.0
V
PD
W
oC
Operating Temperature
TA
-40 to 85
* Stresses greater than those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS
OE
WE
LB
UB
I/O1-8
I/O9-16
Mode
Power
H
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
H
H
L
X
X
H
L
X
X
H
H
L
High-Z
High-Z
High-Z
Data Out
High-Z
High-Z
High-Z
High-Z
High-Z
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Stand by
Active
Active
Active
Active
Active
Active
Active
Active
L
H
L
Data Out Upper Byte Read
L
L
Data Out Data Out
Word Read
Lower Byte Write
Upper Byte Write
Word Write
X
X
X
L
H
L
Data In
High-Z
Data In
High-Z
Data In
Data In
L
H
L
L
L
Note: X means don’ t care. (Must be low or high state)
3
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
VCC
2.7
3.3
3.6
V
Ground
VSS
VIH
0
0
-
0
V
V
VCC + 0.22)
0.6
Input high voltage
2.2
-0.23)
Input low voltage
VIL
-
V
1. TA= -40 to 85oC, otherwise specified
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Input capacitance
Symbol
Test Condition
Min
Max
Unit
CIN
VIN=0V
VIO=0V
-
8
pF
pF
Input/Ouput capacitance
CIO
-
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
-1
-1
-
Typ Max Unit
Input leakage current
ILI
VIN=VSS to VCC
-
-
-
1
1
3
mA
mA
mA
ILO
ICC
CS=VIH or OE=VIH or WE=VIL, VIO=VSS to VCC
IIO=0mA, CS=VIL, VIN=VIH or VIL
Output leakage current
Operating power supply
Cycle time=1ms, 100% duty, IIO=0mA,
ICC1
-
-
3
mA
mA
CS<0.2V, VIN <0.2V or VIN>VCC-0.2V
Average operating current
55ns
70ns
-
-
-
-
-
-
26
20
0.4
-
Cycle time = Min, IIO=0mA, 100% duty,
CS=VIL , VIN=VIL or VIH
ICC2
Output low voltage
Output high voltage
Standby Current (TTL)
VOL
VOH
ISB
IOL = 2.1mA
-
V
V
IOH = -1.0mA
2.4
CS=VIH, Other inputs=VIH or VIL
-
-
0.3
mA
CS>VCC-0.2V Other inputs=0~VCC
(Typ. condition : VCC=3.3V @ 25oC)
(Max. condition : VCC=3.6V @ 85oC)
LL
LF
0.51)
ISB1
Standby Current (CMOS)
-
5
mA
NOTES
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.
4
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
3)
VTM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
2)
R1
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
2)
R2
CL1)
CL1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1=3070W,
R2=3150W
3. VTM=2.8V
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Symbol
Parameter
Read cycle time
Unit
Min
Max
Min
Max
tRC
tAA
55
-
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
-
-
-
55
55
25
30
-
-
-
-
70
70
35
35
-
Chip select to output
tco
Output enable to valid output
UB, LB acess time
tOE
tBA
Chip select to low-Z output
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
tLZ
10
5
10
5
tBLZ
tOLZ
tHZ
-
-
5
-
5
-
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
0
0
0
0
10
10
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
55ns
70ns
Unit
Symbol
Parameter
Write cycle time
Min
Max
Min
Max
tWC
tCW
tAs
55
-
70
60
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
-
-
-
Address valid to end of write
UB, LB valid to end of write
Write pulse width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
40
0
-
60
60
50
0
-
-
-
-
-
Write recovery time
-
-
Write to ouput high-Z
0
25
0
30
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
30
0
-
-
-
-
tOW
5
5
5
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS=OE=VIL, WE=VIH, UB or/andLB=VIL
)
tRC
Address
tAA
tOH
Previous Data Valid
Data Valid
Data Out
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO
CS
tHZ
tBA
UB,LB
tBHZ
tOE
OE
tOHZ
tOLZ
High-Z
Data Out
Data Valid
tBLZ
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC
Address
tCW (2)
tWR(4)
CS
tAW
tBW
UB,LB
tWP(1)
WE
tDH
tAS(3)
High-Z
tDW
High-Z
Data in
Data Valid
tWHZ
tOW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB,LB
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
7
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
tWC
Address
tCW(2)
tW R(4)
CS
tAW
tBW
UB,LB
tWP(1)
tAS(3)
WE
tDH
tDW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS
or WE going high.
8
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention
Symbol
VDR
Test Condition
Min
Typ2) Max
Unit
ISB1 Test Condition
1.5
-
3.6
-
V
1)
(Chip Disabled)
VCC=1.5V, ISB1 Test Condition
(Chip Disabled) 1)
IDR
Data Retention Current
-
0.25
mA
Chip Deselect to Data Retention Time
Operation Recovery Time
tSDR
tRDR
0
-
-
-
-
See data retention wave form
ns
tRC
NOTES
1. See the ISB1 measurement condition of datasheet page 4.
2.Typical values are measured at TA=25oC and not 100% tested.
DATA RETENTION WAVE FORM
tRDR
tSDR
Data Retention Mode
Vcc
2.7V
2.2V
VDR
CS > Vcc-0.2V
CS
GND
9
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
Unit: millimeters
PACKAGE DIMENSION
10
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Device Type
3. Density
11. Power
10. Speed
4. Option
9. Packages
8. Version
5. Technology
6. Operating Voltage
7. Orgainzation
1. Memory Component
8. Version
Blank ----------------- Mother Die
2. Device Type
A ----------------------- First revision
B ----------------------- Second revision
C ----------------------- Third revision
D ----------------------- Fourth revision
E ----------------------- Fifth revision
F ----------------------- Sixth revision
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ---------------------- FPBGA
S ---------------------------- 32 sTSOP1
T ---------------------------- 32 TSOP1
U ---------------------------- 44 TSOP2
W ---------------------------- Wafer
4. Option
0 ----------------------- Dual CS
1 ----------------------- Single CS
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
6. Operating Voltage
Blank ------------------ 5.0V
V ------------------------- 2.7V~3.6V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free)
L ---------------------- Low Power
S ---------------------- Standard Power
7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
11
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