A6250X16W_技术文档

EM MICROELECTRONIC-MARIN SA

A6250

High Efficiency Linear Power Supply with Accurate

Power Surveillance and Software Monitoring

Features

software clears the watchdog too quickly (incorrect cycle

time) or too slowly (incorrect execution) it will cause the

system to be reset. The system enable output prevents

critical control functions being activated until software has

successfully cleared the watchdog three times. Such a se-

curity could be used to prevent motor controls being ener-

gized on repeated resets of a faulty system.

n Highly accurate 5 V, 250 mA guaranteed output

n Low dropout voltage, typically 260 mV at 250 mA

n Low quiescent current, typically 175 µA

n Standby mode, maximum current 340 µA (with

100 µA load on OUTPUT)

n Unregulated DC input can withstand -20 V reverse

battery and +60 V power transients

n Fully operational for unregulated DC input voltage up

to 40 V and regulated output voltage down to 3.0 V

n Reset output guaranteed for regulated output voltage

down to 1.2 V

Applications

n Industrial electronics

n Cellular telephones

n Security systems

n Battery powered products

n High efficiency linear power supplies

n Automotive electronics

n No reverse output current

n Very low temperature coefficient for the regulated

output

n Current limiting

n Comparator for voltage monitoring, voltage reference

1.52 V

Typical Operating Configuration

n Programmable reset voltage monitoring

n Programmable power on reset (POR) delay

n Watchdog with programmable time windows

guarantees a minimum time and a maximum time

between software clearing of the watchdog

n Time base accuracy ±10%

n System enable output offers added security

n TTL/CMOS compatible

A6250

n -40 to +125°C temperature range

n PSOP2-16 package

Description

The A6250 offers a high level of integration by combining

voltage regulation, voltage monitoring and software moni-

toring in a 16 lead package. The voltage regulator has a

low dropout voltage (typ. 260 mV at 250 mA) and a low

quiescent current (175 µA). The quiescent current in-

creases only slightly in dropout prolonging battery life.

Built-in protection includes a positive transient absorber

for up to 60 V (load dump) and the ability to survive an un-

regulated input voltage of -20 V (reverse battery). The in-

put may be connected to ground or a reverse voltage

without reverse current flow from the output to the input. A

comparator monitors the voltage applied at the V_INinput

comparing it with an internal 1.52 V reference. The

power-on reset function is initialized after V_INreaches 1.52

V and takes the reset output inactive after T_PORdepending

of external resistance. The reset output goes active low

when the V_INvoltage is less than 1.52 V. The RES and EN

outputs are guaranteed to be in a correct state for a regu-

lated output voltage as low as 1.2 V. The watchdog func-

tion monitors software cycle time and execution. If

Fig. 1

Pin Assignment

A6250

Fig. 2

1

A6250

Absolute Maximum Ratings

Operating Conditions

Parameter

Symbol Conditions

Parameter

Symbol Min. Max. Units

Continuous voltage at INPUT to

V_SS

Transients on INPUT for

t< 100 ms and duty cycle 1%

Operating junction

temperature¹⁾

V_INPUT

V_TRANS

-0.3 to +45 V

T_J

VI_NPUT

V_OUTPUT1.2

I_OUTPUT

V_IN

R

-40 +125

°C

V

mA

V

INPUT voltage ²⁾

2.3

40

up to +60 V

-20 V

OUTPUT+0.3V

V_SS-0.3V

-65 to +150°C

max. 150 °C

OUTPUT voltage ^{2) 3)}

RES & EN guaranteed ⁴⁾

OUTPUT current ⁵⁾

Comparator input voltage

RC-oscillator programming ⁶⁾

Thermal resistance from

junction to ambient ⁷⁾

- PSOP2-16

Reverse supply voltage on INPUT V_REV

Max. voltage at any signal pin

Min. voltage at any signal pin

Storage temperature

Operating junction temperature T_J

Electrostatic discharge max. To

MIL-STD-883C method 3015

Max. soldering conditions

Max. Output current

V_MAX

V_MIN

T_STO

250

V_OUTPUT

1000

0

10

kW

V_Smax

T_Smax

I_OUTPUTmax

1000V

250°C x 10 s

300 mA

R_th(j-a)

30

90

°C/W

Table 2

¹⁾The maximum operating temperature is confirmed by

sampling at initial device qualification. In production, all

devices are tested at +125°C.

Table 1

Stresses above these listed maximum ratings may cause

permanent damage to the device. Exposure beyond

specified operating conditions may affect device reliability

or cause malfunction.

²⁾Full operation guaranteed. To achieve the load regulation

specified in Table 3 a 22 µF capacitor or greater is required

on the INPUT, see Fig. 8. The 22 µF must have an effective

resistance £ 5 W and a resonant frequency above 500 kHz.

³⁾A 10 µF load capacitor and a 100 nF decoupling capacitor

are required on the regulator OUTPUT for stability. The 10 µF

must have an effective series resistance of £ 5 W and a

resonant frequency above 500 kHz.

Decoupling Methods

The input capacitor is necessary to compensate the line

influences. A resistor of approx. 1 W connected in series

with the input capacitor may be used to damp the oscilla-

tion of the input capacitor and input inductivity. The ESR

value of the capacitor plays a major role regarding the effi-

ciency of the decoupling. It is recommended also to con-

nect a ceramic capacitor (100 nF) directly at the IC’s pins.

In general the user must assure that pulses on the input

line have slew rates lower than 1 V/µs. On the output side,

the capacitor is necessary for the stability of the regulation

circuit. The stability is guaranteed for values of 22 µF or

bigger. It is specially important to choose a capacitor with

a low ESR value. Tantal capacitors are recommended.

See the notes related to Table 2. Special care must be

taken in disturbed environments (automotive, proximity of

motors and relays, etc.).

⁴⁾RES must be pulled up externally to V_OUTPUTeven if it is

unused. (Note: RES and EN are used as inputs by EM test.)

⁵⁾The OUTPUT current will not apply for all possible

combinations of input voltage and output current.

Combinations that would require the A6250 to work above

the maximum junction temperature (+125 °C) must be

avoided.

⁶⁾Resistor values close to 1000 kW are not recommended for

applications working at 125 °C.

⁷⁾The thermal resistance specified assumes the package is

soldered to a PCB. The termal resistance’s value depends on

the PCB’s structure. A typical value of 51 °C/W has been

obtained with a dual layer board, with the slug soldered to

the heat-sink area of the PCB (see Fig. 22).

Handling Procedures

This device has built-in protection against high static volt-

ages or electric fields; however, anti-static precautions

must be taken as for any other CMOS component. Unless

otherwise specified, proper operation can only occur

when all terminal voltages are kept within the supply volt-

age range. Unused inputs must always be tied to a de-

fined logic voltage level.

2

A6250

Electrical Characteristics

V_INPUT= 6.0 V, C_L= 10 µF + 100 nF, C_INPUT= 22 µF, T_J= -40 to +125°C, unless otherwise specified

Parameter

Symbol Test Conditions

Min.

Typ.

Max.

Unit

Supply current in standby mode

I_SS

R_EXT= don’t care, TCL = V_OUTPUT,

V_IN= 0 V, I_L= 100 µA

R_EXT= 100 kW, I/Ps at V_OUTPUT,

140

175

340

400

µA

Supply current ¹⁾

O/Ps 1 MW to V_OUTPUT, I_L= 100 µA

R_EXT= 100 kW, I/Ps at V_OUTPUT

,

V_INPUT= 8.0 V, O/Ps 1MW to V_OUTPUT

I_L= 100 mA

I_L= 250 mA

I_L= 100 µA

,

1.7

7

4.2

15

5.15

mA

V

Output voltage

V_OUTPUT

4.85

100 µA £ I_L£ 250 mA,

V

Output voltage temperature

coefficient ²⁾

V_th(coeff)

V_LINE

100

ppm/°C

Line regulation ³⁾

6 V £ V_INPUT£ 35 V, I_L= 1 mA,

T_J= +125°C

100 µA £ I_L£ 100 mA

5 mA £ I_L£ 250 mA

I_L= 100 µA

I_L= 100 mA

I_L= 250 mA

V_INPUT= 4.5 V, I_L= 100 µA,

R_EXT= 100 kW, O/Ps 1 MW to

V_OUTPUT, I/Ps at V_OUTPUT

OUTPUT tied to V_SS

0.2

0.9

40

160

260

0.8

0.7

1.45

170

380⁵⁾

650

%

mV

Load regulation³⁾

Load regulation ³⁾

Dropout voltage ⁴⁾

Dropout supply current

V_L

V_DROPOUT

I_SS

1.2

450

200

1.8

mA

µV rms

Current limit

OUTPUT noise, 10 Hz to 100 kHz

I_Lmax

V_NOISE

4.5 £ V_OUTPUT£ 5.5 V, I_L= 100 µA. C_L= 10 µF + 100 nF, C_INPUT= 22 µF, T_J= -40 to +125°C, unless otherwise specified

RES and EN

Output Low Voltage

V_OL

V_OUTPUT= 4.5 V, I_OL= 20 mA

V_OUTPUT= 4.5 V, I_OL= 8 mA

V_OUTPUT= 2.0 V, I_OL= 4 mA

V_OUTPUT= 1.2 V, I_OL= 0.5 mA

0.4

0.2

V

0.4

0.2

0.06

EN

Output High Voltage

V_OH

V_OUTPUT= 4.5 V, I_OH= -1 mA

V_OUTPUT= 2.0 V, I_OH= -100 µA

V_OUTPUT= 1.2 V, I_OH= -30 µA

3.5

1.8

1.0

4.1

1.9

1.1

V

TCL and V_IN

TCL Input Low Level

TCL Input High Level

Leakage current TCL input

V_INinput resistance

Comparator reference ^{6) 7)}

V_IL

V_IH

I_LI

R_VIN

V_REF

V_HY

V_SS

2.0

0.8

V_OUTPUT

1

V

µA

MW

V

V_SS£ V_TCL£ V_OUTPUT

T_J= +25°C

0.05

100

1.52

1.474

1.436

1.420

1.566

1.620

-40°C £ T_J£ +125°C

Comparator hysteresis ⁷⁾

2

mV

Table 3

¹⁾If INPUT is connected to V_SS, no reverse current will flow from the OUTPUT to the INPUT, however the supply current specified

will be sank by the OUTPUT to supply the A6250.

²⁾The OUTPUT voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range.

³⁾Regulation is measured at constant junction temperature using pulse testing with a low duty cycle. Changes in OUTPUT voltage

due to heating effects are covered in the specification for thermal regulation.

^{4 )}The dropout voltage is defined as the INPUT to OUTPUT differential, measured with the input voltage equal to 5.0 V.

^{5 )}Not tested.

⁶⁾The comparator and the voltage regulator have separate voltage references (see Block Diag ram Fig. 7).

⁷⁾The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference

voltage plus the comparator hysteresis (see Fig. 4).

3

A6250

Timing Characteristics

V_INPUT= 6.0 V, I_L= 100 µA, C_L= 10 µF + 100 nF, C_INPUT= 22 µF, T_J= -40 to +125°C, unless otherwise specified

Parameter

Symbol Test Conditions

Min.

Typ.

Max.

Units

Propagation delays:

TCL to Output Pins

V_INsensitivity

T_DIDO

T_SEN

250

5

500

20

ns

µs

1

Logic Transition Times on all

Output Pins

Power-on Reset delay

Watchdog Time

T_TR

T_POR

T_WD

Load 10 kW, 50 pF

R_EXT= 123 kW, ± 1%

30

100

110

ns

ms

90

Open Window Percentage

Closed Window Time

OWP

T_CW

T_OW

T_WDR

T_TCL

±0.2 T_WD

0.8 T_WD

80

0.4 T_WD

40

T_WD/ 40

2.5

R_EXT= 123 kW, ± 1%

72

36

88

44

ms

Open Window Time

Watchdog Reset Pulse

T_CLInput Pulse Width

ms

ns

150

Table 4

Timing Waveforms

Watchdog Timeout Period

Condition:

R_EXT= 123 kW

Fig. 3

Voltage Monitoring

Fig. 4

4

A6250

Timer Reaction

Fig. 5

Combined Voltage and Timer Reaction

Fig. 6

Block Diagram

Fig. 7

5

A6250

assumes a constant load (ie. ³ 100 s). The transient ther-

mal resistance for a single pulse is much lower than the

continuous value.

Pin Description

Name

Function

2

3

EN

RES

Push-pull active low enable output

Open drain active low reset output.

RES must be pulled up to V_OUTPUT

even if unused

Watchdog timer clear input signal

GND terminal

Voltage regulator input

Voltage regulator output

R_EXTinput for RC oscillator tuning

Voltage comparator input

V_INMonitoring

The power-on reset and the power-down reset are gener-

ated as a response to the external voltage level on the V_IN

input. The external voltage level is typically obtained from

a voltage divider as shown in Fig. 8. The user uses the ex-

ternal voltage divider to set the desired threshold level for

power-on reset and power-down reset in his system. The

internal comparator reference voltage is typically 1.52 V.

At power-up the reset output (RES) is held low (see Fig. 4).

After INPUT reaches 3.36 V (and so OUTPUT reaches at

least 3 V) and V_INbecomes greater than V_REF, the RES out-

put is held low for an additional power-on-reset (POR) de-

lay which is equal to the watchdog time T_WD(typically 100

ms with an external resistor of 123 kW connected at R pin).

The POR delay prevents repeated toggling of RES even if

V_INand the INPUT voltage drops out and recovers. The

POR delay allows the microprocessor’s crystal oscillator

time to start and stabilize and ensures correct recognition

of the reset signal to the microprocessor.

4

5

12

13

14

15

TCL

V_SS

INPUT

OUTPUT

R

V_IN

Table 5

Functional Description

Voltage Regulator

The A6250 has a 5 V ± 3%, 250 mA, low dropout voltage

regulator. The low supply current (typ. 175 µA) makes the

A6250 particularly suited to automotive systems then re-

main energized 24 hours a day. The input voltage range is

2.3 V to 40 V for operation and the input protection in-

cludes both reverse battery (20 V below ground) and load

dump (positive transients up to 60 V). There is no reverse

current flow from the OUTPUT to the INPUT when the

INPUT equals V_SS. This feature is important for systems

which need to implement (with capacitance) a minimum

power supply hold-up time in the event of power failure. To

achieve good load regulation a 22 µF capacitor (or

greater) is needed on the INPUT (see Fig. 8). Tantalum or

aluminium electrolytics are adequate for the 22 µF capaci-

tor; film types will work but are relatively expensive. Many

aluminium electrolytics have electrolytes that freeze at

about -30°C, so tantalums are recommended for opera-

tion below -25°C. The important parameters of the 22 µF

capacitor are an effective series resistance of £ 5 W and a

resonant frequency above 500 kHz.

The RES output goes active low generating the

power-down reset whenever V_INfalls below V_REF. The sen-

sitivity or reaction time of the internal comparator to the

voltage level on V_INis typically 5 µs.

Timer Programming

The on-chip oscillator with an external resistor R_EXTcon-

nected between the R pin and V_SS(see Fig. 8) allows the

user to adjust the power-on reset (POR) delay, watchdog

time T_WDand with this also the closed and open time win-

dows as well as the watchdog reset pulse width (T_WD/ 40).

With R_EXT= 123 kW typical values are:

- Power-on reset delay: T_POR= 100 ms

- Watchdog time:

- Closed window:

- Open window:

- Watchdog reset:

T_WD= 100 ms

T_CW= 80 ms

T_OW= 40 ms

T_WDR= 2.5 ms

A 10 µF capacitor (or greater) and a 100 nF capacitor are

required on the OUTPUT to prevent oscillations due to in-

stability. The specification of the 10 µF capacitor is as per

the 22 µF capacitor on the INPUT (see previous para-

graph).

Note the current consumption increases as the frequency

increases.

The A6250 will remain stable and in regulation with no ex-

ternal load and the dropout voltage is typically constant as

the input voltage fall to below its minimum level (see Table

2). These features are especially important in CMOS RAM

keep-alive applications.

Care must be taken not to exceed the maximum junction

temperature (+125°C). The power dissipation within the

A6250 is given by the formula:

P_TOTAL= (V_INPUT- V_OUTPUT) . I_OUTPUT+ (V_INPUT) . I_SS

The maximum continuous power dissipation at a given

temperature can be calculated using the formula:

P_MAX= (125°C - T_A) / Rth(j-a)

where Rth(j-a) is the thermal resistance from the junction

to the ambient and is specified in Table 2. Note the R_th(j-a)

given in Table 2 assumes that the package is soldered to a

PCB. The above formula for maximum power dissipation

6

A6250

Watchdog Timeout Period Description

120 ms after the timer reset. However as the time base is

±10% accurate, software must use the following calcula-

tion for servicing signal TCL during the open window:

Related to curves (Fig. 10 to Fig. 20), especially Fig. 19

and Fig. 20, the relation between T_WDand R_EXTcould easily

be defined. Let us take an example describing the varia-

tions due to production and temperature:

1. Choice, T_WD= 26 ms.

2. Related to Fig. 20, the coefficient (T_WDto R_EXT) is 1.125

where R_EXTis in kW and T_WDin ms.

The watchdog timeout period is divided into two parts, a

“closed" window and an “open" window (see Fig. 3) and is

defined by two parameters, T_WDand the Open Window

Percentage (OWP).The closed window starts just after the

watchdog timer resets and is defined by T_CW= T_WD

-

OWP(T_WD).The open window starts after the closed time

window finishes and lasts till T_WD+ OWP(T_WD). The open

window time is defined by T_OW= 2 x OWP(T_WD).

3. R_EXT(typ.) = 26 x 1.155 = 30.0 kW.

4. The ratio between T_WD= 26 ms and the (TCL period)

= 25.4 ms is 0.975. Then the relation over the

Production and the full temperature range is,

TCL period = 0.975 x T_WD0.975 x R_EXTor

0.975 x REXT

, as typical value.

TCL period =

1.155

a) ±10 % while PRODUCTION value unknown for the

customer when R_EXT¹ 123 kW.

b) ±5 % while operating TEMPERATURE range

-40°C £ T_J£ +125°C.

5. If you fixed a TCL period = 26 ms

26 x 1.155

= 30.8 kW.

Þ R_EXT

0.975

For example if T_WD= 100 ms (actual value) and OWP = ±

20% this means the closed window lasts during first the

80 ms (T_CW= 80 ms = 100 ms - 0.2 (100 ms)) and the

open window the next 40 ms (T_OW= 2 x 0.2 (100 ms) = 40

ms). The watchdog can be serviced between 80 ms and

If during your production the T_WDtime can be measured

at T_J= +25°C and the µC can adjust the TCL period,

then the TCL period range will be much larger for the

full operating temperature.

T_WDversus V_OUTPUTat T_J= +25 °C

T_WDversus R at T_J= +25 °C

Fig. 8

Fig. 9

7

A6250

T_WDversus R at T_J= +25 °C

R [kW]

Fig. 10

8

A6250

T_WDversus V_OUTPUTatT_J= +85 °C

T_WDversus R at T_J= +85 °C

Fig. 11

Fig. 12

T_WDversus V_OUTPUTat T_J= -40 °C

T_WDversus R at T_J= -40°C

Fig. 14

9

Fig. 13

A6250

T_WDversus Temperature at 5 V

T_WDversus R at 5 V

Fig. 16

Fig. 15

Maximum OUTPUT Current versus INPUT Voltage

Fig. 17

10

A6250

Timer Clearing and RES Action

of the POR delay. A TCL pulse will have no effect until this

power-on-reset delay is completed. After the POR delay

has elapsed, RES goes inactive and the watchdog timer

starts acting. If no TCL pulse occurs, RES goes active low

for a short time T_WDRafter each closed and open window

period. A TCL pulse coming during the open window

clears the watchdog timer. When the TCL pulse occurs

too early (during the closed window), RES goes active

and a new timeout sequence starts. A voltage drop below

the V_REFlevel for longer than typically 5 µs overrides the

timer and immediately forces RES active and EN inactive.

Any further TCL pulse has no effect until the next

power-up sequence has completed.

The watchdog circuit monitors the activity of the proces-

sor. If the user’s software does not send a pulse to the TCL

input within the programmed open window timeout period

a short watchdog RES pulse is generated which is equal

to T_WD/ 40 = 2.5 ms typically (see Fig. 5). With the open

window constraint new security is added to conventional

watchdogs by monitoring both software cycle time and

execution. Should software clear the watchdog too

quickly (incorrect cycle time) or too slowly (incorrect exe-

cution) it will cause the system to be reset. If software is

stuck in a loop which includes the routine to clear the

watchdog then a conventional watchdog would not make

a system reset even though software is malfunctioning;

the A6250 would make a system reset because the watch-

dog would be cleared too quickly. If no TCL signal is ap-

plied before the closed and open windows expire, RES

Enable - EN Output

The system enable output, EN, is inactive always when

RES is active and remains inactive after a RES pulse until

the watchdog is serviced correctly 3 consecutive times

(ie. the TCL pulse must come in the open window). After

three consecutive services of the watchdog with TCL dur-

ing the open window, the EN goes active low. A malfunc-

tioning system would be repeatedly reset by the

watchdog. In a conventional system critical motor con-

trols could be energized each time reset goes inactive

(time allowed for the system to restart) and in this way the

electrical motors driven by the system could function out

of control. The A6250 prevents the above failure mode by

using the EN output to disable the motor controls until

software has successfully cleared the watchdog three

times (ie. the system has correctly restarted after a reset

condition).

will start to generate square waves of period (T_CW+ T_OW

+

T_WDR). The watchdog will remain in this state until the next

TCL falling edge appears during an open window, or until

a fresh power-up sequence. The system enable output,

EN, can be used to prevent critical control functions being

activated in the event of the system going into this failure

mode (see section “Enable - EN Output"). The RES output

must be pulled up to V_OUTPUTeven if the output is not used

by the system (see Fig. 8).

Combined Voltage and Timer Action

The combination of voltage and timer actions is illustrated

by the sequence of events shown in Fig. 6. On power-up,

when the voltage at V_INreaches V_REF, the power-on-reset,

POR, delay is initialized and holds RES active for the time

Typical Application

A6250

Fig. 18

11

A6250

T_WDCoefficient versus R_EXTat T_J= +25 °C

Fig. 19

R_EXTCoefficient versus T_WDat T_J= +25 °C

Fig. 20

12

A6250

Package and Ordering Information

Dimensions of PSOP2-16 Package

Fig. 21

Dimensions in mm

Dual Layer PCB

Dimensions in mm

Fig. 22

Ordering Information

The A6250 is available in the following package:

Type

Package

A6250 X 16W PSOP2-16

When ordering please specify complete part number.

EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely

embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the

circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has

not been superseded by a more up-to-date version.

E. & O.E. Printed in Switzerland, Th

EM MICROELECTRONIC-MARIN SA, CH-2074 Marin, Switzerland, Tel. 032 - 755 51 11, Fax 032 - 755 54 03

13


型号：	A6250X16W
厂家：	EM MICROELECTRONIC - MARIN SA
描述：	High Efficiency Linear Power Supply with Accurate Power Surveillance and Software Monitoring 高效率线性电源供应器，提供精确的电源监控和监视软件监控
文件：	总13页 (文件大小：586K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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