V3025SO28A [EMMICRO]
17Very Low Power 8-Bit 32 kHz RTC Module with Digital Trimming, User RAM and Battery Switch-over; 17Very低功耗的8位32千赫的RTC模块与数字微调，用户内存和电池开关切换
| 型号： | V3025SO28A |
| 厂家： | 
EM MICROELECTRONIC - MARIN SA |
| 描述： | 17Very Low Power 8-Bit 32 kHz RTC Module with Digital Trimming, User RAM and Battery Switch-over |
| 文件： | 总17页 (文件大小：748K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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EM MICROELECTRONIC - MARIN SA
V3025
Very Low Power 8-Bit 32 kHz RTC Module with Digital
Trimming, User RAM and Battery Switch-over
Description
Features
ꢀ Built-in quartz with digital trimming and
temperature compensation facilities
The V3025 is a low power CMOS real time clock with an
integrated battery switch-over. The standby current is
typically 2.5 µA and the access time is 50 ns. The
interface is a multiplexed address and data 8 bits bus.
Multiplexing of address and data is handled by the input
ꢀ INTEL and MOTOROLA interface compatibility
ꢀ 15 ns typical access time at 5.0V
ꢀ 1.2 µA typical standby current at 3.0V
ꢀ Wide supply voltage range, 2.0 ≤ VDD ≤ 5.5V
ꢀ Integrated battery switch-over
ꢀ Battery voltage range, 2.0 ≤ VBAT ≤ 4.0V
ꢀ No busy state
line A /D. There are no busy flags in the V3025, internal
time update cycles are invisible to the user's software.
Time data can be read from the V3025 in 12 or 24 hour
data formats. An external signal puts the V3025 in
standby mode. Even in standby, the V3025 pulls the IRQ
pin active low on an internal alarm interrupt. Calendar
functions include leap year correction and week number
calculation. The V3025 can be synchronized to an
external 50 Hz signal or to the nearest second or minute.
The integrated battery switch-over supply the real time
ꢀ No external components required
ꢀ BCD format
ꢀ Frequency measurements
ꢀ Time set lock mode
ꢀ Week number calculation
clock part by VDD as long as VDD is higher than VBAT
.
ꢀ Clock counts up to 99 years
When VDD decreases under VBAT, the output PFO comes
active and the real clock is supplied by the battery or the
supercap.
ꢀ Leap year correction
ꢀ 12 or 24 hour data format
ꢀ Output programmable interrupts
ꢀ Alarm interrupt, programmable up to one month
ꢀ Timer interrupt, programmable up to 24 hours
ꢀ Time to 1/100 of a second
Applications
ꢀ Industrial controllers
ꢀ Alarm systems with periodic wake up
ꢀ PABX and telephone systems
ꢀ Point of sale terminals
ꢀ Automotive electronics
ꢀ Personal computers
ꢀ To external time reference synchronisation
ꢀ 50 Hz or nearest s/min synchronisation
ꢀ Power fail input PFI
ꢀ Power fail output or Reset output PFO
ꢀ Tri-state bus capability when power fail (PFI = 0)
ꢀ User RAM
ꢀ Temperature range -40 to +85°C
ꢀ Package SO28
Typical Operating Configuration
Pin Assignment
SO28
VBAT
AD7
AD6
AD5
AD4
RD
SYNC
PFI
AD0
AD1
AD2
AD3
WR
CS
A/D
IRQ
VOUT
VSS
V3025
PFO
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
Fig. 2
Fig. 1
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V3025
Absolute Maximum Ratings
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when
all terminal voltages are kept within the voltage range.
Unused inputs must always be tied to a defined logic
voltage level.
Parameter
Maximum voltage at VDD and
VBAT
Max. voltage at remaining pins VSUP
Min. voltage on all pins Vmin
Maximum storage temperature TSTOmax
Minimum storage temperature TSTOmin
Maximum electrostatic
Symbol
Conditions
VSUPmax
VSS + 7.0V
VDD + 0.3V
VSS – 0.3V
+125°C
-55°C
Operating Conditions
discharge to MIL-STD-883C
method 3015.7 with ref. to VSS
Maximum soldering conditions TSmax
VSmax
1000V
Parameter
Symbol Min Typ Max Unit
Operating temperature
Main supply voltage
Battery supply voltage
Logic supply voltage
TA
-40
2
+85
5.5
4
°C
V
250°C x 10s
5000 g.
0.3ms, ½ sine
Table 1
VDD
Shock resistance
VBAT
VSUP
dv/dt
2
V
2.0
5.0
5.5
6
V
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device reliability
or cause malfunction.
Supply voltage dv/dt
(power-up & down)
V/µs
Decoupling capacitor
100
nF
Table 2
Electrical Characteristics
VDD = 5.0V ±10%, VBAT = 3V, TA = -40 to +85°C, unless otherwise specified
Parameter
Standby current (note 1)
Symbol
IDD1
Test Conditions
DD = 3 V, VBAT = 0V, PFI = 0
VDD = 5.5 V, PFI = 0
DD = 0 V, PFI = 0
Min
Typ
1.2
2.5
1.3
Max
Unit
10
15
10
1.5
µA
µA
µA
mA
V
IDD2
IBAT
IDYN
Standby current (note 1)
Dynamic current (note 2)
V
CS = 4 MHz, RD = VSS
WR = VDD
IRQ (open drain)
Output low voltage
Output low voltage
Inputs and Outputs
Input logic low
Input logic high
Output logic low
Output logic high
VOL
VOL
IOL = 6 mA
IOL = 1 mA, VDD = 2 V
0.4
0.4
V
V
VIL
VIH
VOL
VOH
VPFL
TA = +25°C
TA = +25°C
IOL = 6 mA
IOH = 6 mA
0.2 VSUP
0.4
V
V
V
V
V
0.8 VSUP
2.4
0.5 VDD
100
PFI activation voltage
PFI hysteresis
VH
ILS
TA = +25°C
VILS = 0.8 V
VSS < VIN < VDD
CS = 1
mV
µA
20
40
Pullup on SYNC
Input leakage
Output tri-state leakage
IIN
ITS
5
5
1000
1000
nA
nA
Oscillator Characteristics
Starting voltage
VSTA
VSTA
TA ≥ +25°C
2
V
V
2.5
1
Frequency Characteristics
Start-up time
TSTA
s
TA = +25°C addr. 10 hex = 00
hex
∆f/f
Frequency tolerance
150
210
(note 4)
1
251
5
ppm
Frequency stability
Temperature stability
Aging
Accuracy versus switch-
over
fsta
tsta
tag
2.0 ≤ VDD ≤ 5.5 V (note 3)
addr. 10 hex = 00 hex
TA = +25°C, first year
VBAT = 3V, 10 pulses of VDD
switching between 2 to 5V in
70ms
ppm/V
ppm
ppm/year
ppm
see Fig.6
±5
ASW
0.2
Table 3
Note 1: With PFO = 0 (VSS) all I/O pads can be tri-state, tested.
With PFO = 1 (VSUP), CS = 1 (VDD) and all other I/O pads fixed to VSUP or VSS: same standby current, not tested.
Note 2: All other inputs to VDD and all outputs open.
Note 3: At a given temperature.
Note 4: See Fig. 5
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V3025
Switch-over Electrical Characteristics
TA = -40 to +85°C, inputs to VDD, outputs not connected, unless otherwise specified
Parameter
Symbol
RVDD
RBAT
Test Conditions
Min
Typ
4
24
Max
8
40
Unit
Ω
Ω
V
ON resistance of VDD to VOUT
ON resistance of VBAT to VOUT
VDD voltage over VBAT for
switching
VDD voltage under VBAT for
switching
VDD = 3V, VBAT = 0V, IOUT = 100mA
VDD = 0V, VBAT = 3V, IOUT = 20mA
VBAT = 3V, VOUT open
VSVDD
3.00
2.98
3.21
3.45
VSBAT
TRDD
VBAT = 3V, VOUT open
3.08
14
3.18
100
V
VDD rising edge switching
VBAT = 3V, VDD rise from 2.8V to 3.5V
µs
delay to PFO and VOUT
VDD falling edge switching
delay to PFO and VOUT
TFDD
VBAT = 3V, VDD falling from 3.5V to
2.8V
8
60
µs
Table 4
Timing Characteristics
VDD = 5.0V ±10%, VBAT = 0V, VSS = 0V and TA = -40 to +85°C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Chip select duration, write cycle
tCS
50
ns
Write pulse duration
tWR
tW
tACC
tDF
50
ns
ns
ns
ns
Time between two transfers
RAM access time (note 1)
100
CLOAD = 50pF
50
30
60
40
Data valid to Hi-impedance (note
2)
10
Write data settle time (note 3)
Data hold time (note 4)
Advance write time
tDW
tDH
tADW
tPF
50
10
10
ns
ns
ns
ns
100
PF response delay
Rise time (all inputs)
Fall time (all inputs)
tR
tF
200
200
ns
ns
ns
5
t
t
CS delay after A /D (note 5)
CS delay to A /D
/Ds
A
A
10
ns
/Dt
Table 4
Note 1: tACC starts from RD (DS ) or CS , whichever activates last
Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF
Note 2: tDF starts from RD (DS ) or CS , whichever deactivates first
Note 3: tDW ends at WR (R/ W ) or CS , whichever deactivates first
Note 4: tDH starts from WR (R/ W ) or CS , whichever deactivates first
Note 5: A /D must come before a CS and RD or a CS and WR combination. The user has to guarantee this.
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V3025
Typical VDD Current vs. Temperature
Fig. 3
Typical VBAT Current vs. Temperature
Fig. 4
Typical Frequency on IRQ
Fig. 5
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V3025
Module Characteristic
∆F
FO
ppm
°C2
= -0.038
(T – TO)2 ± 10%
∆F/FO
=
the ratio of the change in frequency to the
nominal value expressed in ppm (it can be
thought of as the frequency deviation at any
temperature)
T
TO
=
=
the temperature of interest in °C
the turnover temperature (25 ± 5°C)
To determine the clock error (accuracy) at a given
temperature, add the frequency tolerance at 25°C to the
value obtained from the formula above.
Fig. 6
Typical VDD Switch Resistance vs. Temperature
Fig. 7
Typical Battery Switch Resistance vs. Temperature
Fig. 8
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V3025
Timing Waveforms
Read Timing for Intel (RD and WR Pulse) and Motorola (DS or RD pin tied to CS and R/ W )
Fig. 9a
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V3025
Intel Interface
Write Timing
Fig. 9b
Write
Fig. 9c
Read
Fig. 9d
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V3025
Motorola Interface
Motorola Write
Fig. 9e
Write
Fig. 9f
Read
Fig. 9g
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V3025
General Block Diagram
Fig. 10
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V3025
Pin Description
SO28 Package
Initialisation
When power is first applied to the V3025 all registers have
a random value.
Pin
1
Name
SYNC
PFI
Description
To initialise the V3025, software must first write a 1 to the
initialisation bit (addr. 2 bit 4) and then a 0. This sets the
Frequency Tuning bit and clears all other status bits.
The time and date parameters should then be loaded into
the RAM (addr. 20 to 28 hex) and then transferred to the
reserved clock area using the clock command followed by
a write.
The digital trimming register must then be initialised
by writing 210 (D2 hex) to it, if Frequency Tuning is
not required. After having written a value to the
digital trimming register the frequency tuning mode
bit can be cleared.
Time synchronization
Power fail
Bit 0 from MUX address /
data bus
Bit 1 from MUX address /
data bus
Bit 2 from MUX address /
data bus
Bit 3 from MUX address /
data bus
Address / data decode
Interrupt request
I
I
2
3
4
5
6
AD0
AD1
AD2
I/O
I/O
I/O
I/O
AD3
A /D
7
8
9
I
O
IRQ
VOUT
RAM Configuration
Switch-over output
Supply ground (substrate)
Positive supply terminal
O
GND
PWR
The RAM area of the V3025 has a reserved clock and
time area, a data space, user RAM and an address
command space (see Table 10 or Fig. 10). The reserved
clock and timer area is not directly accessible to the user,
it is used for internal time keeping and contains the
current time and date plus the timer parameters.
10-14 VSS
15-19 VDD
20
21
Power fail output
Chip select
O
I
PFO
CS
WR (Intel) or R/ W
(Motorola)
22
23
24
I
I
WR
Data Space
All locations in the data space are Read/Write. The data
space is directly accessible to the user and is divided into
five areas:
Status Registers – three registers used for status and
control data for the device (see Table 7, 8 and 9).
Reserved bits must be set to 0.
RD (Intel) or DS (Motorola)
Bit 4 from MUX address /
data bus
Bit 5 from MUX address /
data bus
Bit 6 from MUX address /
data bus
Bit 7 from MUX address /
data bus
Battery supply
RD
AD4
I/O
25
26
AD5
AD6
I/O
I/O
I/O
Digital Trimming Register – a special function described
under "Frequency Tuning".
Time and Date Registers – 9 time and date locations
which are loaded with, either the current time and date
parameters from the reserved clock area or the time and
date parameters to be transferred to the reserved clock
area.
Alarm Registers – 5 locations used for setting the alarm
parameters.
Timer Registers – 4 locations which are loaded with
either the timer parameters from the reserved timer area
or the timer parameters to be transferred to the reserved
timer area.
27
28
AD7
VBAT
PWR
Table 5
Functional Description
Power Supply, Data Retention and Standby
The V3025 is put in standby mode by activating the PFI
input. When pulled logic low, PFI will disable the input
lines, and immediately take to high impedance the lines
AD 0-7. Input states must be under control whenever
PFI is deactivated. If no specific power fail signal can be
provided, PFI can be tied to the system RESET . Even
User RAM
The V3025 has 16 bytes of general purpose RAM
available for the users applications. This RAM block is
located at addresses 50 to 5F hex and is maintained even
in standby the interrupt request pin IRQ will pull to ground
upon an unmasked alarm interrupt occurring.
in the standby mode (PFI active). The commands, or the
time set lock bit, have no effect on the user RAM block.
Reading or writing to the user RAM is similar to reading or
writing to any system RAM address.
Switch-over
The switch-over supplies the core of the RTC. The I/O
pads are supplied by VDD, except for IRQ and SYNC .
The SYNC input is internally pulled-up to VOUT, IRQ can
be externally pulled-up between 2 and 5.5V. The switch-
over circuitry works in recovery mode. During switching,
both transistors (VDD to VOUT and VBAT to VOUT) are ON.
This is to guarantee that the RTC is always supplied. The
power fail signal becomes active (PFO = 0) when VDD
VBAT (see Table 4).
<
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V3025
Status Words
RAM Map
Address
Dec
Parameter
Data Space
Range
Hex
Status
00
01
00
01
02
status 0
status 1
status 2
02
Special purpose
16
10
digital trimming
0-255
Clock
32
33
34
35
36
37
38
39
20
21
22
23
24
25
26
27
28
1/100 second
seconds
minutes
hours (note 1)
date
month
year
week day
week number
00-99
00-59
00-59
00-23
01-31
01-12
00-99
01-07
00-53
Table 7
Table 8
Table 9
40
Alarm
48
49
50
51
52
Timer
64
65
30
31
32
33
34
1/100 second
seconds
minutes
hours (note 1 & 2)
date
00-99
00-59
00-59
00-23
01-31
40
41
42
43
1/100 second
seconds
minutes
00-99
00-59
00-59
00-23
66
67
hours
User RAM
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
user RAM, byte 0
user RAM, byte 1
user RAM, byte 2
user RAM, byte 3
user RAM, byte 4
user RAM, byte 5
user RAM, byte 6
user RAM, byte 7
user RAM, byte 8
user RAM, byte 9
user RAM, byte 10
user RAM, byte 11
user RAM, byte 12
user RAM, byte 13
user RAM, byte 14
user RAM, byte 15
Address Command Space
This space contains the three commands used for
carrying out the transfers between the Time and Data
Register and / or the Timer Registers and the reserved
clock and timer area.
Address Command Space
240
241
242
F0
F1
F2
clock and timer transfer
clock transfer
timer transfer
Table 10
Note 1: The MSB (bit 7) of the hours byte (addr. 23 hex
for the clock and 33 hex for the alarm) are used
as AM/PM indicators in the 12 hour time data
format and reading of the hours byte must be
preceded by masking of the AM/PM bit. A set
AM/PM bit indicates PM. In the 24 hour time
data format the bit will always be zero.
Note 2: The alarm hours, addr. 33 hex, must always be
rewritten after a change between 12 and 24 hour
modes.
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V3025
Communication
locations is transferred to the reserved clock and/or timer
area.
Data transfer is in 8 bit parallel form. All time data is in
packed BCD format with tens data on lines AD7-4 and
units on lines AD3-0. To access information within the
RAM (see Fig.10) first write the RAM address, then read
or write from or to this location. Fig.11 shows the two
steps needed.
Clock and Calendar
The time and date locations in RAM (see Table 10)
provide access to the 1/100 seconds, seconds, minutes,
hours, date, month, year, week day and week number.
These parameters have the ranges indicated in Table 10.
The V3025 may be programmed for 12 or 24 hour time
format (see section "12/24 Data Format"). If a parameter
is found to be out of range, it will be cleared when the
units value on its being next incremented is equal to or
greater than 9 eg. B2 will be set to 00 after the units have
incremented to 9 (ie. B9 to 00). The device incorporates
leap year correction and week number calculation at the
beginning of a year. If the first day of the year is day 05,
06 or 07 of the week, then it is given a zero week number,
otherwise it becomes week 1. Week days are numbered
from 1 to 7 with Monday as day 1.
The lines AD0-7 will be treated as an address when pin
A /D is low, and as data when A /D is high. Pin A /D
must not change state during any single read or write
access. One line of the address bus (e.g. A0) can be used
to implement the A /D signal (see "Typical Operating
Configuration", Fig.1). Until a new address is written, data
accesses ( A /D high) will always be to the same RAM
address.
Communication Sequence
Reading of the current time and date must be preceded
by a clock command. The time and date from the last
clock command is held unchanged in RAM.
When transferring data to the reserved clock and
timer area remember to clear the time set lock bit first.
A/D =0
A/D =1
Timer
The timer can be used either for counting elapsed time, or
for giving an interrupt (IRQ ) on being incremented from
23:59:59:99 to 00:00:00:00. The timer counts up with a
resolution of 1/100 second in the timer reserved areas.
The timer enable/disable bit (addr. 00 hex, bit 3) must be
set by software to allow the timer to be incremented. The
timer is incremented in the reserved timer area, every
internal time update (10 ms). The timer flag (addr. 01
hex, bit 6) is set when the timer rolls over from
Fig. 11
Access Considerations
The communication sequence shown in Fig.11 is re-
entrant. When the address is written to the V3025 (ie. first
step of the communication sequence) it is stored in an
internal address latch. Software can read the internal
address latch at any time by holding the A /D line low
during a read from the V3025. So, for example, an
interrupt routine can read the address latch and push it on
to a stack, popping it when finished to restore the V3025.
N.B. Alarm and timer interrupt routines can reprogram the
alarm and timer without it being necessary to read or
reprogram the clock.
23:59:59:99 to 00:00:00:00 and the IRQ becomes active
if the timer mask bit (addr. 01, bit 2) is set. The IRQ will
remain active until software acknowledges the interrupt by
clearing the timer flag. The timer is incremented in the
standby mode, however it will not cause IRQ to become
active until power (VDD) has been restored.
Commands
Note: The user should ensure that a time lapse of at least
The commands allow software to transfer the clock and
timer parameters in a sequence (eg. seconds, minutes,
hours, etc.) without any danger of an internal time update
with carry over corrupting the data. They also avoid
delaying internal time updates while using the V3025, as
updates occurring in the reserved clock and timer area
are invisible to software. Software writes or reads
parameters to or from the RAM only.
60 microseconds exists between the falling edge of the
IRQ and the clearing of the timer flag.
There are three commands that occupy the command
address space in the RAM. The function of these
commands is to transfer data from the reserved clock and
timer area to the RAM or to transfer data in the opposite
direction, from the RAM to the reserved clock and timer
area.
The commands take place in two steps as do all other
communications. The command address is sent with
A /D low. This is followed by either a read (RD ) or a
write ( WR ) , with A /D high, to determine the direction of
the transfer. If the second step is a read then the data is
transferred from the reserved clock and timer area to the
RAM and if the second step is a write then the data that
has already been loaded into the RAM clock and/or timer
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V3025
Reading the Clock
Setting the Timer (Time Set Lock Bit = 0)
Start
Start
[Pin 7 = A/D]
A/D = 0
[Pin 7 = A/D]
A/D = 0
Write clock command
(addr. F1 hex) to the V3025
Write 1/100 sec. address
(40 hex) to the V3025
Write 1/100 sec. data to the
RAM
Read data from the V3025 to
copy the timer parameters from
the reserved clock area to the
RAM.
A/D = 1
A/D = 0
A/D = 1
A/D = 1
Write sec. address (41 hex) to
the V3025
Write 1/100 sec. address
(20 hex) to the V3025
A/D = 0
A/D = 1
Write sec. data to the RAM
Read 1/100 sec. data from the
RAM
Write min. address (42 hex) to
the V3025
A/D = 0
A/D = 1
Write sec. address (21 hex) to
the V3025
A/D = 0
A/D = 1
Write min. data to the RAM
Read sec. data from the RAM
Write hours address (43 hex) to
the V3025
A/D = 0
A/D = 1
A/D = 0
Write min. address (22 hex) to
the V3025
A/D = 0
A/D = 1
Write hours data to the RAM
Read min. data from the RAM
End
Write timer command
(addr. F2 hex) to the V3025
Write F2 hex to the V3025 to
copy the timer parameters from
RAM to the reversed timer area
A/D = 1
Fig. 12
End
Fig. 13
Note: Commands are only valid as commands when the
A /D line is low. Writing F2 hex with the A /D line high,
as in the last box of Fig. 11, serves only to activate the
V3025 write pin which determines the direction of transfer.
Alarm
parameter. Thus it is possible to achieve a repeat feature
where an alarm occurs every programmed number of
seconds, or seconds and minutes, or seconds, minutes
An alarm date and time may be preset in RAM addresses
30 to 34 hex. The alarm function can be activated by
setting the alarm enable / disable bit (addr. 00 hex, bit 2).
Once enabled the preset alarm time and date are
compared, every internal time update cycle (10 ms), with
the clock parameters in the reserved clock area. When
the clock parameters equal the alarm parameters the
alarm flag (addr. 01 hex, bit 5) is set. If the alarm mask bit
and hours. The V3025 pulls the open drain IRQ line
active low during standby when an alarm interrupt occurs.
If the 12/24 hour mode is changed then the alarm
hours must be re-initialised.
Note: The user should ensure that a time lapse of at least
60 microseconds exists between the falling edge of the
(addr. 01 hex, bit 1) is set, the IRQ pin goes active. The
alarm flag indicates to software the source of the interrupt.
IRQ and the clearing of the alarm flag.
IRQ will remain active until software acknowledges the
interrupt by clearing the alarm flag. If the alarm is
enabled, and an alarm address set to FF hex, this
parameters is not compared with the associated clock
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V3025
while in standby. Upon power restoration the pulse
feature is enabled if enabled prior to standby. See also
the section "Frequency Tuning".
Note: The user should ensure that a time lapse of at least
60 microseconds exists between the falling edge of the
IRQ
The IRQ output is used by 4 of the V3025's features.
These are:
1. Pulse, to provide periodic interrupts to the
microprocessors at pre-programmed intervals;
2. Alarm to provide an interrupt to the microprocessor at
a pre-programmed time and date;
3. Timer, to provide an interrupt to the microprocessor
when the time rolls over from 23:59:59:99 to
00:00:00:00; and
4. Frequency trimming (see section "Frequency
Trimming").
The first 3 features listed are similar in the way they
provide interrupts to the microprocessor. Each of the 3
has an enable / disable bit, a flag bit, and an interrupt
mask bit. The enable / disable bit allows software to
select a feature or not. A set flag bit indicates that an
enable feature has reached its interrupt condition.
Software must clear the flag bit. The interrupt mask bit
IRQ and the clearing of the pulse flag.
Time Set Lock
The time set lock control bit is located at address 00 hex,
bit 5 (see Table 7). When set by software, this bit
disables any transfer from the RAM to the reserved clock
and timer area as well as inhibiting any write to the digital
trimming register at address 10 hex. When the time set
lock bit is set the following transfer operations are
disabled:
The clock command followed by write,
the timer command followed by write,
the clock and timer command followed by write, and
writing to the digital trimming register
allows or disallows the IRQ output to become active
when the flag bit is se. The IRQ output becomes active
whenever any interrupt flag is set which also has its mask
bit set. For all sources of maskable interrupts within the
A set bit prevents unauthorized overwriting of the
reserved clock and timer area. Reading of the reserved
clock and timer area, using the commands, is not affected
by the time set lock bit. Clearing the time set lock bit by
software will re-enable the above listed commands. On
initialisation the time set lock bit is cleared. The time set
lock bit does not affect the user RAM (addr. 50 to 5F hex).
V3025, the IRQ output will remain active until software
clears the interrupt flag. The IRQ output is the logical OR
of all the unmasked interrupt flags. The IRQ output is
open drain so an external pullup to VDD is needed. In
Frequency Tuning
standby (PF active) the IRQ output will be active if the
alarm mask bit (addr, 01 hex, bit 1) is set and the alarm
flag is also set. The timer or the pulse feature cannot
The V3025 offers a key feature called "Digital Trimming",
which is used for the clock accuracy adjustment. Unlike
the traditional capacitor trimming method which tunes the
crystal oscillator, the digital trimming acts on the divider
chain, allowing the clock adjustment by software. The
oscillator frequency itself is not affected.
cause the IRQ output to become active while in standby.
Snychronization
There are 3 ways to synchronize the V3025. It can be
synchronized to 50 Hz, the nearest second, or the nearest
minute. Synchronization mode is selected by setting one
of the bits 5 to 7 at addr. 02 hex, in accordance with Table
8. If more than one bit is set then all the synchronization
The Principle of Digital Trimming
With the digital trimming disabled (ie. digital trimming
register set to 00 hex), the oscillator and the first stages of
the divider chain will run slightly too fast (typ. 210 ppm:
ppm = parts per million), and will generate a 100 Hz signal
with a frequency of typically 100.021 Hz. To correct this
frequency, the digital trimming logic will inhibit every 31
seconds, a number of clock pulses, as set in the digital
trimming register. Since the duration of 31 seconds
corresponds to 1'015'808 oscillator cycles, the digital
trimming has a resolution of 0.984 ppm. In other words
every increment by 1 of the digital trimming value will slow
down the clock by 0.984 ppm, which permits the accuracy
of ± 0.5 ppm to be reached. Note that a 1 ppm error will
result in a 1 second difference after 11.5 days, or a 1
minute difference after 694 days ! The trimming range of
the V3025 is from 0 to 251 ppm. The 251 ppm correction
is obtained by writing 255 (FFhex) into the digital trimming
register.
bits are disabled. If the SYNC input is set low for longer
than 200 µs, while in the synchronization mode, the clock
will synchronize to the falling edge of the signal.
Synchronization to the nearest second implies that the
1/100 seconds are cleared to zero and if the contents
were
> 50, the seconds register is incremented.
Synchronization to the nearest minute implies that the
seconds are cleared to zero and if the contents were > 30,
the minutes register is incremented. Fractions of seconds
are cleared.
Pulse
There are 4 programmable pulse frequencies available on
the V3025, these are every 10 ms, 100 ms, second or
minute. The pulse feature is activated by setting the pulse
enable / disable bit at address 00, bit 1. The pulse
frequency is selected by setting one of the bit 0 to 3 at
address 02 hex (see Table 9). If more than one of the
pulse bits is set then the feature is disabled. At the
selected interval the pulse flag bit (addr. 01 hex, bit 4) is
set. If the pulse mask bit (addr. 01 hex, bit 0) is set then
the IRQ pin goes active. The pulse flag indicates to
software the source of the interrupt. IRQ will remain
active until software acknowledges the interrupt by
clearing the pulse flag. The pulse feature is disabled
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V3025
How to Determine the Digital Trimming Value
The value to write into the digital trimming register has to
be determined by the following procedure:
12 / 24 Hour Data Format
The V3025 can run in 12 hour data format.
On
initialisation the 12/24 hour bit addr. 00 bit 4 is cleared
putting the V3025 in 24 hour data format. If the 12 hour
data format is required then bit 4 at addr. 00 must be set.
In the 12 hour data format the AM/PM indicator is the
MSB of the hours register addr. 23 bit 7. A set bit
indicates PM. When reading the hours in the 12 hour
data format software should mask the MSB of the hours
register. In the 24 hour data format the MSB is always
zero.
1. Initialise the V3025 by writing a 1 and then a 0 into the
"Initialisation Bit" of the status register 2 (addr. 02 hex,
bit 4). This activates the frequency tuning mode in
status register 0 (addr. 00 hex, bit 1) and clears the
other status bits.
2. Write the value 00 hex into the digital trimming register
(addr 10 hex). From now, the IRQ output (open
drain) will deliver the 100 Hz signal, which has a 20%
duty cycle.
The internal clock registers change automatically between
12 and 24 hour mode when the 24/12 hour bit is changed.
The alarm hours however must be rewritten.
3. Measure the duration of 21 pulses at the IRQ output,
with the trigger set for the falling edge. It is possible
Test
also to divide the IRQ frequency by 21, using a TTL
or CMOS external circuit.
4. Compute the frequency error in ppm:
From the various test features added to the V3025 some
may be activated by the user. Table 7 shows the test bits.
Table 11 shows the three available modes and how they
may be activated.
The first accelerates the incrementing of the parameters
in the reserved clock and timer area by 32.
The second causes all clock and timer parameters, in the
reserved clock and timer area, to be incremented in
parallel at 100 Hz with no carry over, ie. independently of
each other.
210ms − measured value inms
freq. error =
x 106
210ms
5. Compute the corrective value to write into the digital
trimming register.
Digital trimming value = frequency error / 0.984
6. Write this value into the digital trimming register.
7. Switch off the frequency tuning mode in status 0 (addr.
00 hex, bit 0 set to 0).
The third test mode combines the previous two resulting
in parallel incrementing at 3.2 kHz.
While test bit 1 is set (addr. 00 hex, bit 7) the digital
trimming action is disabled and no pulses are removed
from the divider chain. Test bit 0 (addr. 00 hex, bit 6) can
be combined with digital trimming (see section "Frequency
Tuning").
To leave test, the test bits (addr 00 hex, bits 6 and 7) must
be cleared by software. Test corrupts the clock and timer
parameters and so all parameters should be re-initialised
after a test session.
The Real Time Clock circuit will now run accurately at an
operating temperature equal to the calibration
temperature. If the operating temperature differs from the
one at calibration time, the graphs shown on Fig. 5 and 6
will help in determining the definitive value. If the mean
operating temperature of the equipment is not known at
calibration time, the equipment user will do the final
correction with a software provided by the system
designer. To avoid the calibration procedure, it is possible
also to set the digital trimming register to 210 (D2 hex) as
a standard starting value, and let the final equipment user
perform the final adjustment on site, which will take the
real temperature into account.
Test Modes
Addr.
00hex bit 7
Addr.
00hex bit 6
Function
0
0
1
0
1
0
Normal operation
Acceleration by 32
Time Correction at Room Temperature
Let us consider that the duration of 21 pulses of the IRQ
signal is 209.97 ms at room temperature.
Parallel increment of all clock
and timer parameters at 100
Hz with no carry over;
dependent on the status of bit
3 at address 00 hex
Parallel increment of all clock
and timer parameters at 3.2
kHz with no carry over;
dependent on the status of bit
3 at address 00 hex
The frequency error is:
(210 – 209.97) / 210 x 1E + 06 = 142.857 ppm
1
1
The value for the digital trimming register is:
142.857 / 0.984 = 145.18, rounded up to 145 ppm (91
hex)
Table 11
Time Correction with Change of Temperature
If the mean temperature on site is known to be 45°C, the
frequency error determined at room temperature has to be
modified using the graphs or the equation of Fig. 6
∆f/f = -0.038 x (45-25)2 = 15.2 ppm
The trimming value for 45°C will be:
(142.857 ppm – 15.2 ppm) / 0.984 = 129.73, rounded to
130 (82 hex)
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V3025
Typical Operating Configuration
Fig. 14
Process Application
•
The formula in Fig. 5 is used by software to continually
update the digital trimming register and so compensate
the V3025 for the ambient temperature.
Temperature
sensor
•
•
The timer is used to measure the duration the valve is
on.
The alarm feature is used to turn the controller power
on and off at the time programmed by software. The
Controller
Solenoid
valve
V3025 pulls IRQ active low on an alarm even in
standby and thus can control the power on/off switch for
the controller.
Fig. 15
Typical Applications
V3025 Interfaced with Intel CPU (RD and WR pulse)
Fig. 16
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V3025
V3025 Interfaced with Motorola CPU (DS or RD pin tied to CS , and R/ W )
Fig. 17
Ordering and Package Information
Dimensions of 28-pin SOIC Package
Fig. 18
Ordering Information
When ordering, please specify the complete part number.
Part Number
Package
Delivery Form
Package Marking
(first line)
V3025SO28B
V3025SO28A
28-pin SOIC
28-pin SOIC
Tape & Reel
Stick
V3025 28SI
V3025 28SI
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely
embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the
circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has
not been superseded by a more up-to-date version.
© EM Microelectronic-Marin SA, 09/04, Rev. F
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