EN29F002AT-90JIP [EON]
2 Megabit (256K x 8-bit) Flash Memory; 2兆位（ 256K ×8位）快闪记忆体
| 型号： | EN29F002AT-90JIP |
| 厂家： | 
EON SILICON SOLUTION INC. |
| 描述： | 2 Megabit (256K x 8-bit) Flash Memory |
| 文件： | 总35页 (文件大小：430K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EN29F002A / EN29F002AN
EN29F002A / EN29F002AN
2 Megabit (256K x 8-bit) Flash Memory
FEATURES
• 5.0V ± 10% for both read/write operation
• JEDEC standard
polling and toggle
DATA
bits feature
• Hardware
• Read Access Time
Pin (n/a on EN29F002AN)
RESET
- 45ns, 55ns, 70ns, and 90ns
• Single Sector and Chip Erase
• Fast Read Access Time
- 70ns with Cload = 100pF
- 45ns, 55ns with Cload = 30pF
• Sector Protection / Temporary Sector
Unprotect (
= VID)
RESET
• Sector Architecture:
• Sector Unprotect Mode
One 16K byte Boot Sector, Two 8K byte
Parameter Sectors, one 32K byte and
three 64K byte main Sectors
• Embedded Erase and Program Algorithms
• Erase Suspend / Resume modes:
Read and program another sector during
Erase Suspend Mode
• Boot Block Top/Bottom Programming
Architecture
• 0.23 µm triple-metal double-poly
• High performance program/erase speed
- Byte program time: 10µs typical
- Sector erase time: 500ms typical
- Chip erase time: 3.5s typical
triple-well CMOS Flash Technology
• Low Vcc write inhibit < 3.2V
• 100K endurance cycle
• Package Options
- 32-pin PDIP
• Low Standby Current
- 1µA CMOS standby current-typical
- 1mA TTL standby current
- 32-pin PLCC
• Low Power Active Current
- 30mA active read current
- 30mA program / erase current
- 32-pin TSOP (Type 1)
• Commercial and Industrial Temperature
Ranges
• JEDEC Standard program and erase
commands
GENERAL DESCRIPTION
The EN29F002A / EN29F002AN is a 2-Megabit, electrically erasable, read/write non-volatile flash memory.
Organized into 256K words with 8 bits per word, the 2M of memory is arranged in seven sectors (with
top/bottom configuration), including one 16K Byte Boot Sector, two 8K Byte Parameter sectors, and four main
sectors (one 32K Byte and three 64K Byte). Any byte can be programmed typically at 10µs. The EN29F002A /
EN29F002AN features 5.0V voltage read and write operation. The access times are as fast as 45ns to
eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29F002A / EN29F002AN has separate Output Enable (
), Chip Enable (
), and Write
CE
OE
Enable (
) controls which eliminate bus contention issues. This device is designed to allow
W E
either single sector or full chip erase operation, where each sector can be individually protected
against program/erase operations or temporarily unprotected to erase or program. The device can
sustain
a
minimum
of
100K
program/erase
cycles
on
each
sector.
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/03/26
1
or modifications due to changes in technical specifications.
EN29F002A / EN29F002AN
TABLE 1. PIN DESCRIPTION
FIGURE 1. LOGIC DIAGRAM
Pin Name
A0-A17
Function
Addresses
Vcc
DQ0-DQ7
Data Input/Outputs
Chip Enable
Output Enable
Write Enable
Hardware Reset
Sector Unprotect
18
8
CE
OE
W E
A0 - A17
DQ0 - DQ7
EN29F002AT/B
CE
OE
WE
RESET
(n/a for
EN29F002AN)
RESET
N/A on EN29F002AN
Vcc
Supply Voltage
(5V ± 10% )
Ground
Vss
Vss
TABLE 2. BLOCK ARCHITECTURE
TOP BOOT BLOCK
BOTTOM BOOT BLOCK
SIZE (Kbytes)
SIZE (Kbytes)
SECTOR
ADDRESSES
3C000h - 3FFFFh
3A000h - 3BFFFh
38000h - 39FFFh
30000h - 37FFFh
20000h - 2FFFFh
10000h - 1FFFFh
00000h - 0FFFFh
ADDRESSES
30000h - 3FFFFh
20000h - 2FFFFh
10000h - 1FFFFh
08000h - 0FFFFh
06000h - 07FFFh
04000h - 05FFFh
00000h - 03FFFh
6
5
4
3
2
1
0
16
8
64
64
64
32
8
8
32
64
64
64
8
16
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/03/26
2
or modifications due to changes in technical specifications.
EN29F002A / EN29F002AN
BLOCK DIAGRAM
DQ0-DQ7
Vcc
Vss
Block Protect
RESET
N/A on EN29F002AN
Erase Voltage Generator
Input/Output Buffers
State
Control
WE
Program Voltage
Generator
Command
Register
STB
Chip Enable
Output Enable
Logic
Data Latch
CE
OE
Y-Decoder
Y-Gating
STB
Vcc Detector
Timer
X-Decoder
Cell Matrix
A0-A17
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/03/26
3
or modifications due to changes in technical specifications.
EN29F002A / EN29F002AN
FIGURE 2. PDIP
PDIP Top View
NC on EN29F002AN
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
RESET
A16
A15
A12
A7
2
WE
A17
3
4
A14
A13
A8
5
A6
A5
6
7
A9
A4
A3
8
A11
OE
9
A2
A1
10
11
12
13
14
15
16
A10
CE
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
VSS
FIGURE 3. TSOP
WE
NC on EN29F002AN
RESET
EN29F002A
FIGURE 4. PLCC
PLCC Top View
V
A15 RESET WE
A12
A16
A17
CC
NC on EN29F002AN at RESET pin
4
2
32
30
A7
A6
A5
A4
A3
5
6
7
8
9
29 A14
28 A13
27 A8
3
1
31
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ7
A2 10
A1 11
A0 12
DQ0 13
15
17
19
14
16
18
20
DQ2 DQ3 DQ5
DQ1 VSS DQ4 DQ6
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/03/26
4
or modifications due to changes in technical specifications.
EN29F002A / EN29F002AN
TABLE 3. OPERATING MODES
2M FLASH USER MODE TABLE
USER MODE
RESET A9
A8 A6 A1
A0 Ax/y
DQ(0-7)
C E
X
WE
X
OE
X
L
X
X
X
X
X
X
HI-Z
RESET
(n/a on EN29F002AN)
STANDBY
H
L
L
L
X
H
H
H
X
L
H
L
H
H
H
H
X
A9
X
X
A8
X
X
A6
X
X
A1
X
X
A0
X
X
Ax/y
X
HI-Z
DQ(0-7)
HI-Z
READ
OUTPUT DISABLE
READ
VID
L/H
L
L
L
X
MANUFACTURER
ID
MANUFACTURER ID
READ DEVICE ID
VERIFY SECTOR
PROTECT
L
L
H
H
L
L
H
H
VID
VID
L/H
X
L
L
L
H
H
L
X
X
DEVICE ID(T/B)
01h(protected)
00h(unprotected)
X
ENABLE SECTOR
PROTECT
L
L
VID
H
VID
X
L
X
X
X
SECTOR UNPROTECT
WRITE
L
L
X
L
L
X
VID
H
X
H
H
VID
VID
A9
X
X
A8
X
H
A6
X
H
A1
X
L
A0
X
X
Ax/y
X
X
DIN(0-7)
X
TEMPORARY SECTOR
UNPROTECT
NOTES:
1) L = VIL, H = VIH, VID = 11.0V ± 0.5V
2) X = Don’t care, either VIH or VIL
TABLE 4. DEVICE IDENTIFICTION
2M FLASH MANUFACTURER/DEVICE ID TABLE
A8
A6
A1
A0
DQ(7-0)
HEX
READ
L
L
L
L
CONTINUATION MANUFACTURER ID
MANUFACTURER ID
READ
MANUFACTURER ID
READ DEVICE ID
7F
MANUFACTURER ID
1C
H
L
L
L
*
L
L
L
L
L
H
H
CONTINUATION DEVICE ID
(Top Architecture)
7F
DEVICE ID
92
*
H
READ DEVICE ID
(Top Architecture)
READ DEVICE ID
(Bottom Architecture)
L
L
L
L
L
H
H
CONTINUATION DEVICE ID
7F
DEVICE ID
97
*
H
READ DEVICE ID
(Bottom Architecture)
NOTES:
These modes (A8=H) are recommended for Manufacture/Device ID check.
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/03/26
5
or modifications due to changes in technical specifications.
EN29F002A / EN29F002AN
USER MODE DEFINITIONS
Reset Mode
EN29F002A features a Reset mode that resets the program and erase operation immediately to
read mode. If reset (
= L) is executed when program or erase operation were in progress, the
RESET
program or erase which was terminated should be repeated since data will be corrupted. This pin is
not available for EN29F002AN.
Standby Mode
The EN29F002A / EN29F002AN has a CMOS-compatible standby mode which reduces the current
to < 1µA (typical). It is placed in CMOS-compatible standby when
and the
pins are at
RESET
CE
VCC ± 0.5 V (
pin only, for EN29F002AN). The device also has a TTL-compatible standby mode
CE
which reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when
CE
pin
and
pins are at VIH. Another method of entering standby mode uses only the
RESET
RESET
(n/a for EN29F002AN). When
pin is at VSS ± 0.3V, the device enters CMOS-compatible
RESET
standby with current typically reduced to < 1 µA. When
compatible standby with current reduced to < 1mA. When in standby modes, the outputs are in a
pin is at VIL, the device enters TTL-
RESET
high-impedance state independent of the
input.
OE
Read Mode
The EN29F002A / EN29F002AN has two control functions which must be satisfied in order to obtain
data at the outputs. Chip Enable ( ) is the power control and should be used for device selection.
CE
) is the output control and should be used to gate data to the output pins,
Output Enable (
OE
provided the device is selected. Read is selected when both
and
pins are held at VIL with
OE
CE
the
pin held at VIH. Address access time (tACC) is equal to the delay from stable addresses to
W E
valid output data. Assuming that addresses are stable, chip enable access time (tCE) is equal to the
delay from stable to valid data at output pins. Data is available at the outputs after output
CE
enable access time (tOE) from the falling edge of
, assuming the
has been LOW and
CE
OE
addresses have been stable for at least tACC - tOE.
Output Disable Mode
When the
or
pin is at a logic high level (VIH), the output from the EN29F002A /
OE
CE
EN29F002AN is disabled. The output pins are placed in a high impedance state.
Auto Select Identification Mode
The manufacturer and device type can be identified by hardware or software operations. This mode
allows applications or programming equipment automatically matching the device with its
corresponding interface characteristics.
To activate the Auto Select Identification mode, the programming equipment must force 11.0 V ±
0.5V on address line A9 of the EN29F002AT/B. Two identifier bytes can then be sequenced from the
device outputs by toggling address lines A0 and A8 from VIL to VIH.
The manufacturer and device identification may also be read via the command register. By following
the command sequence referenced in the Command Definition Table (Table 5). This method is
desirable for in-system identification (using only + 5.0V).
When A0 = A1 = A6 = VIL and by toggling A8 from VIL to VIH, the Manufacturer ID can be read as Eon
= 7F, 1C (hex) to identify EON . When A0 = VIH, A1 = A6 = VIL, and by toggling A8 from VIL to VIH,
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/03/26
6
or modifications due to changes in technical specifications.
EN29F002A / EN29F002AN
the Device Code can be read as 7F, 92 (hex) for EN29F002AT or as 7F, 97 (hex) for EN29F002AB
(See Table 4). All identifiers for manufacturer and device codes possess odd parity with the DQ7
defined as the parity bit.
Write Mode
Write is used for device programming and erase through the command register. This mode is
selected with
=
= L and
= H. The contents of the command register are the inputs to
OE
CE
W E
the internal state machine. The command register is a set of latches used to store the commands
along with the addresses and data information needed to execute that command. Address latching
occurs on the falling edge of
rising edge of
or
(whichever occurs later) and data latching occurs on the
CE
W E
(whichever occurs first).
or
CE
W E
Temporary Sector Unprotect Mode
EN29F002A allows protected sectors to be temporarily unprotected for making changes to data
stored in a protected sector in system (n/a for EN29F002AN). To activate the temporary sector
unprotect, the
pin must be set to a high voltage of VID (11V). In this mode, protected sectors
RESET
can be programmed or erased by selecting the sector addresses. Once the high voltage, VID, is
removed from pin, all previously protected sectors will revert to their protected state.
RESET
RESET Hardware Reset Mode (not available on EN29F002AN)
Resetting the EN29F002A device is performed when the
pin is set to VIL and kept low for at
RESET
least 500ns. The internal state machine will be reset to the read mode. Any program/erase
operation in progress during hardware reset will be terminated and data may be corrupted.
If the
pin is tied to the system reset command, the device will be automatically reset to the
RESET
read mode and enable the system’s microprocessor to read the boot-up firmware from the FLASH
memory.
COMMAND DEFINITIONS
The operations of the EN29F002A are selected by one or more commands written into the
command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program,
Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data
sequences written at specific addresses via the command register. The sequences for the
specified operation are defined in the Command Table (Table 5). Incorrect addresses, incorrect
data values or improper sequences will reset the device to the read mode.
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/03/26
7
or modifications due to changes in technical specifications.
EN29F002A / EN29F002AN
Table 5. EN29F002A Command Definitions
1st
2nd
3rd
4th
5th
6th
Write
Cycles
Req’d
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Command
Sequence
Read/Reset
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
XXXh F0h RA RD
555h AAh AAAh 55h 555h F0h
1
4
4
Read/Reset
Read/Reset
AutoSelect
RA
RD
555h AAh AAAh 55h 555h 90h 000h/ 7Fh/
100h 1Ch
Manufacturer ID
4
4
4
555h AAh AAAh 55h 555h 90h 001h/ 7Fh/
101h 92h
AutoSelect Device ID
(Top Boot)
555h AAh AAAh 55h 555h 90h 001h/ 7Fh/
101h 97h
AutoSelect Device ID
(Bottom Boot)
555h AAh AAAh 55h 555h 90h SA & 00h/
AutoSelect Sector
Protect Verify
02h
PA
01h
PD
4
6
6
1
1
555h AAh AAAh 55h 555h A0h
Byte Program
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
555h AAh AAAh 55h 555h 80h 555h AAh AAAh 55h 555h 10h
555h AAh AAAh 55h 555h 80h 555h AAh AAAh 55h
SA
30h
xxxh B0h
xxxh 30h
Notes:
RA = Read Address: address of the memory location to be read. This one is a read cycle.
RD = Read Data: data read from location RA during Read operation. This one is a read cycle.
PA = Program Address: address of the memory location to be programmed
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the sector to be erased. Address bits A17-A13 uniquely select any sector.
The data is 00h for an unprotected sector and 01h for a protected sector.
Byte Programming Command
Programming the EN29F002A is performed on a byte-by-byte basis using a four bus-cycle operation
(two unlock write cycles followed by the Program Setup command and Program Data Write cycle).
When the program command is executed, no additional CPU controls or timings are necessary. The
program operation is terminated automatically by an internal timer. Address is latched on the falling
edge of
or
, whichever is last; data is latched on the rising edge of
or
CE
, whichever
W E
CE
W E
is first. The program operation is completed when EN29F002A returns the equivalent data to the
programmed location.
Programming status may be checked by sampling data on DQ7 (
polling) or on DQ6 (toggle
DATA
bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is
exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read
mode.
EN29F002A ignores commands written during Byte Programming. If a hardware
occurs
RESET
during Byte Programming, data at the programmed location may get corrupted. Programming is
allowed in any sequence and across any sector boundary.
Chip Erase Command
An auto Chip Erase algorithm is employed when the Chip Erase command sequence is performed.
Although the Chip Erase command requires six bus cycles: two unlock write cycles, a setup
command, two additional unlock write cycles and the chip erase command, the user does not need
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
8
or modifications due to changes in technical specifications.
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
to do anything else after that, except check to see if the operation has completed. The Auto Chip
Erase algorithm automatically programs and verifies the entire memory array for an all “0” pattern
prior to the erase. Then the EN29F002A will automatically time the erase pulse width, verify the
erase, return the sequence count, provide a erase status through
POLLING (data on DQ7 is
DATA
“0” during the operation and “1” when completed, provided the status is not read from a protected
sector), and returns to the READ mode after completion of Chip Erase.
Sector Erase Command
Sector Erase requires six bus cycles: two unlock write cycles, a setup command, two additional
unlock write cycles, and the Sector Erase command. Any sector may be erased by latching any
address within the desired sector on the falling edge of
while the Erase Command (30H) is
W E
latched on the rising edge of
. This device does not support multiple sector erase commands.
W E
Sector Erase operation will commence immediately after the first 30h command is written. The first
sector erase operation must finish before another sector erase command can be given.
The EN29F002A device automatically programs and verifies all memory locations in the selected
sector for an all “0” pattern prior to the erase. Unselected sectors are unaffected by the Sector
Erase command. The EN29F002A requires no timing signals during sector erase. Erase is
completed when data on DQ7 becomes “1”, and the device returns to the READ mode after
completion of Sector Erase.
Erase Suspend / Resume Command
Erase suspend allows interruption of sector erase operations to perform data reads from sector not
being erased. Erase suspend applies only to Sector Erase operations.
EN29F002A ignores any commands during erase suspend other than the assertion of the
RESET
pin (n/a for EN29F002AN) or Erase Resume commands. Writing erase resume continues erase
operations. Addresses are DON’T CARE when writing Erase Suspend or Erase Resume
commands.
EN29F002A takes 0.1 - 15 µs to suspend erase operations after receiving Erase Suspend command.
Check completion of erase suspend by polling DQ7 and/or DQ6. EN29F002A ignores redundant
writes of erase suspend command.
EN29F0002 defaults to erase-suspend-read mode while an erase operation has been suspended.
While in erase-suspend-read mode, EN29F002A allows reading data in any sector not undergoing
sector erase, which is treated as standard read mode.
Write the Resume command 30h to continue operation of Sector erase. EN29F002A ignores
redundant writes of the Resume command. EN29F002A permits multiple suspend/resume
operations during sector erase.
Sector Protect and Unprotect
The hardware sector protection feature disables both program and erase operations in any sector.
The hardware sector unprotection feature re-enables both program and erase operation in
previously protected sectors.
Sector protection/unprotection must be implemented using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the control pins. Contact Eon Silicon Solution,
Inc. for an additional supplement on this feature.
This Data Sheet may be revised by subsequent versions
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2003/03/26
9
or modifications due to changes in technical specifications.
EN29F002A / EN29F002AN
WRITE OPERATION STATUS
DQ7
Polling
The EN29F002A provides
Polling on DQ7 to indicate to the host system the status of the
DATA
embedded operations. The
Polling feature is active during the Byte Programming, Sector
DATA
Erase, Chip Erase, Erase Suspend. (See Table 6)
When the Byte Programming is in progress, an attempt to read the device will produce the
complement of the data last written to DQ7. Upon the completion of the Byte Programming, an
attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,
polling is valid after the rising edge of the fourth
or
WE
pulse in the four-cycle sequence.
CE
DATA
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the
DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7
output during the read. For Chip Erase, the
polling is valid after the rising edge of the sixth
DATA
pulse in the six-cycle sequence. For Sector Erase, polling is valid after the last
DATA
or
W E
CE
rising edge of the sector erase
or
pulse.
CE
W E
Polling must be performed at any address within a sector that is being programmed or
DATA
erased and not a protected sector. Otherwise,
polling may give an inaccurate result if the
DATA
address used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when
the output enable (
) is low. This means that the device is driving status information on DQ7 at
OE
one instant of time and valid data at the next instant of time. Depending on when the system
samples the DQ7 output, it may read the status of valid data. Even if the device has completed the
embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid.
The valid data on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for
Polling (DQ7) is shown on Flowchart 5. The
Polling (DQ7) timing
DATA
DATA
diagram is shown in Figure 8.
DQ6
Toggle Bit I
The EN29F002A provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)
During an embedded Program or Erase operation, successive attempts to read data from the device
at any address (by toggling
or
) will result in DQ6 toggling between “zero” and “one”. Once
CE
OE
the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be
read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the
rising edge of the fourth
pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is
WE
valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after
the last rising edge of the Sector Erase Command (30h)
pulse.
W E
In Byte Programming, if the sector being written to is protected, DQ6 will toggle for about
2µs, then stop toggling without the data in the sector having changed. In Sector Erase or Chip
Erase, if all selected sectors are protected, DQ6 will toggle for about 100 µs. The chip will then
return to the read mode without changing data in all protected sectors.
Toggling either
or
will cause DQ6 to toggle.
OE
CE
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
10
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse
count). Under these conditions DQ5 will produce a “1”. (The Toggle Bit (DQ6) should also be
checked at this time to make sure that the DQ5 is not a “1” due to the device having returned to read
mode.) This is a failure condition which indicates that the program or erase cycle was not
successfully completed.
function under this condition. Setting the
Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still
to VIH will partially power down the device under those
CE
pins will control the output disable functions as described in Table 3.
DATA
conditions. The
and
WE
OE
The DQ5 failure condition will also appear if the user tries to program a “1” to a location that was
previously programmed to a “0”. In this case, the device goes into Hang or Error mode out and
never completes the Embedded Program Algorithm. Hence, the system never reads valid data on
DQ7 and DQ6 never stops toggling. Once the device exceeds the timing limits, DQ5 will indicate a
“1”. Please note that this is not a device failure condition since the device was used incorrectly. If
timing limits are exceeded, reset the device. (See Table 6)
DQ3
Sector Erase Command Timeout
This device does not support multiple sector erase commands. DQ3 will go high immediately after
the first 30h command (the sixth write cycle). Any extra 30h commands will be ignored (or taken as
a resume command if erase suspended).
DQ2
Erase Toggle Bit II
In the sector erase operation, DQ2 will toggle with
or
when a read is attempted within the
CE
OE
sector that is being erased. DQ2 will not toggle if the read address is not within the sector that is
selected to be erased. In the chip erase operation, however, DQ2 will toggle with
or
CE
OE
regardless of the address given by the user. This is because all sectors are to be erased. (See
Table 6)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
11
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Table 6. Status Register Bits
DQ
Name
Logic Level
Definition
‘1’
Erase Complete or
erase sector in Erase suspend
Erase On-Going
‘0’
Program Complete or
data of non-erase sector
during Erase Suspend
DATA
7
DQ7
POLLING
DQ7
‘-1-0-1-0-1-0-1-’
DQ6
Program On-Going
Erase or Program On-going
Read during Erase Suspend
TOGGLE
BIT
6
5
‘-1-1-1-1-1-1-1-‘
Erase Complete
ERROR BIT
‘1’
‘0’
‘1’
Program or Erase Error
Program or Erase On-going
Erase operation start
ERASE
3
TIME BIT
‘0’
Erase timeout period on-going
Chip Erase, Erase or Erase
suspend on currently
addressed
‘-1-0-1-0-1-0-1-’
sector. (When DQ5=1, Erase
Error due to currently
addressed sector. Program
during Erase Suspend on-
going at current address
2
TOGGLE
BIT
Erase Suspend read on
DQ2
non Erase Suspend Sector
Notes:
DQ7
Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5
DATA
for Program or Erase Success.
DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.
Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5 Error Bit: set to “1’ if failure in programming or erase
DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased sector.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
12
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
DATA PROTECTION
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with
W E
= V ,
= VIL and
= VIH, the device will not accept commands on the rising edge of
OE
CE
.
WE
IL
Low VCC Write Inhibit
During VCC power-up or power-down, the EN29F002A locks out write cycles to protect against any
unintentional writes. If VCC < VLKO, the command register is disabled and all internal program or
erase circuits are disabled. Under this condition, the device will reset to the READ mode.
Subsequent writes will be ignored until VCC > VLKO.
Write “Noise” Pulse Protection
Noise pulses less than 5ns on
command register.
,
or
will neither initiate a write cycle nor change the
WE
OE CE
Logical Inhibit
If
=V or
=V , writing is inhibited. To initiate a write cycle,
and
must be a logical
W E
CE
WE
,
CE
are all logical zero (not recommended usage), it will be considered a
IH
IH
“zero”. If
, and
CE
OE
W E
write.
Sector Protection/Unprotection
When the device is shipped, all sectors are unprotected. Each sector can be separately protected
against data changes. Using hardware protection circuitry enabled at user’s site with external
programming equipment, both program and erase operations may be disabled for any specified
sector or combination of sectors.
Verification of write protection for a specific sector can be achieved with an Auto Select ID read
command at location 02h where the address bits A17 - A13 select the defined sector (see Table 5).
A logical “1” at DQ0 means a protected sector and a logical “0” means an unprotected sector.
The Sector Unprotect disables sector protection in all sectors in one operation to implement code
changes. All sectors must be placed in protection mode using the protection algorithm mentioned
above before unprotection can be executed.
Additional details on this feature are provided in a supplement, which can be obtained by contacting
a representative of Eon Silicon Solution, Inc.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
13
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program
Command Sequence
(shown below)
Data Poll Device
Last
Increment
Address
No
Address?
Yes
Programming Done
Flowchart 2. Embedded Program Command Sequence
See the Command Definitions section for more information.
5555H / AAH
2AAAH / 55H
5555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
14
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Flowchart 3. Embedded Erase
START
Write Erase
Command Sequence
(shown below)
Data Polling Device or Toggle Bit
Successfully Completed
ERASE Done
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
15
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Flowchart 4. Embedded Erase Command Sequence
See the Command Definitions section for more information.
Chip Erase
5555H/AAH
Sector Erase
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
Sector Address/30H
5555H/10H
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
16
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Flowchart 5. Polling Algorithm
Start
Read Data
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read Data
Yes
DQ7 = Data?
No
Fail
Pass
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
17
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Flowchart 6. Toggle Bit Algorithm
Start
Read Data
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Data
No
DQ6 = Toggle?
Yes
Fail
Pass
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
18
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Flowchart 7. Temporary Sector Unprotect Algorithm
(Not available for EN29F002AN)
Start
RESET = VID
(Note 1)
Perform Erase or Program Operations
RESET = VIH
Temporary Block Unprotect Done
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previous protected sectors are protected once again.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
19
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
V
CC (Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7.0 V
A9, OE# (Note 2) . . . . . . . . . . . . . . . –0.5 V to 11.5 V
All other pins (Note 1) . . . . . . . . . . . . –0.5 V to Vcc+0.5V
Output Short Circuit Current (Note 3) . . . . . . . . . 200 mA
Notes:
1.
2.
3.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot
VSS to –1.0V for periods of up to 50 ns and to –2.0 V for periods of up to 20 ns. See Left Figure below.
Maximum DC voltage on input and I/O pins is V CC + 0.5 V. During voltage transitions, input and I/O
pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Right Figure below.
Minimum DC input voltage on A9 pin is –0.5 V. During voltage transitions, A9 and OE# may
undershoot VSS to –1.0V for periods of up to 50 ns and to –2.0 V for periods of up to 20 ns. See Left
Figure. Maximum DC input voltage on A9 and OE# is 11.5 V which may overshoot to 12.5 V for
periods up to 20 ns.
No more than one output shorted to ground at a time. Duration of the short circuit should not be greater
than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may
affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T A ) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (T A ). . . . . . . . . . -40°C to +85°C
VCC Supply Voltages
V
CC for ± 5% devices . . . . . . . . . . . . +4.75 V to +5.25 V
V
CC for ± 10% devices . . . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Maximum Negative Overshoot
Waveform
Maximum Positive Overshoot
Waveform
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
20
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Table 7. DC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 5.0V ± 10%)
Symbol
Parameter
Input Leakage Current
Test Conditions
0V≤ V ≤ Vcc
Min
Max
±5
Unit
µA
I
LI
IN
Output Leakage Current
±5
µA
I
0V≤ V
≤ Vcc
OUT
LO
Supply Current (read) TTL Byte
30
mA
I
CE# = V ; OE# = V ;
IL IH
CC1
f = 6MHz
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
1.0
5.0
mA
µA
I
I
I
CE# = V
IH
RESET# = CE# = Vcc ± 0.2V
CC2
CC3
CC4
(1)
mA
CE# = V ; OE# = V
;
IH
IL
Supply Current (Program or Erase)
30
Byte program, Sector or Chip
Erase in progress
Input Low Voltage
-0.5
2
0.8
Vcc ± 0.5
0.45
V
V
V
V
V
V
V
IL
Input High Voltage
V
IH
Output Low Voltage
V
I
= 2 mA
OL
OL
OH
Output High Voltage TTL
Output High Voltage CMOS
2.4
Vcc - 0.4V
10.5
V
I
I
= -2.5 mA
= -100 µA
OH
OH
A9 Voltage (Electronic Signature)
and RESET# Voltage (Temporary
Sector Unprotect)
11.5
V
ID
A9 and RESET# Current (Electronic
Signature)
A9, RESET# = VID
100
4.2
µA
V
I
LIT
Supply voltage (Erase and
Program lock-out)
V
3.2
LKO
Notes:
(1) RESET# pin input buffer is always enabled so that it draws power if not at full CMOS supply voltages
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
21
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options
Description
Read Cycle Time
JEDEC
Standard
Test Setup
-45
45
-55
-70
70
-90
90
Unit
ns
Min
55
tAVAV
tRC
Max
45
55
70
90
ns
Address to Output Delay
tAVQV
tACC
CE = VIL
= VIL
OE
Max
Max
Max
Max
Min
45
25
10
10
0
55
30
15
15
0
70
30
20
20
0
90
35
20
20
0
ns
ns
ns
ns
ns
Chip Enable To Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tCE
tOE
tDF
tDF
tOH
OE = VIL
Output Enable to Output High Z
Output Hold Time from
Addresses,
or ,
CE OE
whichever occurs first
Max
20
20
20
20
µs
tReady
Pin Low to Read
RESET
Mode (n/a for EN29F002AN)
Notes:
For -45,-55
Vcc = 5.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
For all others:
Vcc = 5.0V ± 10%
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
22
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Table 9. AC CHARACTERISTICS
Write (Erase/Program) Operations
Parameter
Symbols
Speed Options
Description
JEDEC
Standard
-45
45
-55
55
-70
70
-90
90
Unit
ns
Min
Min
Min
Min
Min
Min
Write Cycle Time
tAVAV
tWC
0
35
20
0
0
45
25
0
0
45
30
0
0
45
45
0
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tAVWL
tWLAX
tDVWH
tWHDX
tAS
tAH
tDS
tDH
tOES
Data Hold Time
0
0
0
0
Output Enable Setup Time
MIn
Min
0
0
0
0
ns
ns
Output Enable Read
tOEH
Hold Time
Toggle and
Polling
10
10
10
10
DATA
Read Recovery Time before
Write ( High to Low)
Min
0
0
0
0
ns
tGHWL
tGHWL
OE
W E
Min
Min
Min
Min
Typ
Max
Typ
Max
Typ
Max
Min
Min
0
0
0
0
0
0
0
0
ns
ns
ns
ns
µs
µs
s
tELWL
tWHEH
tWLWH tWP
tWHDL
tCS
tCH
SetupTime
CE
CE
Hold Time
25
20
7
30
20
7
35
20
7
45
20
7
Write Pulse Width
tWPH
Write Pulse Width High
Programming Operation
tWHWH1 tWHWH1
200
0.3
5
200
0.3
5
200
0.3
5
200
0.3
5
tWHWH2 tWHWH2
tWHWH3 tWHWH3
Sector Erase Operation
Chip Erase Operation
Vcc Setup Time
s
3
3
3
3
s
35
50
500
35
50
500
35
50
500
35
50
500
s
µs
ns
tVCS
tVIDR
Rise Time to V
ID
Min
500
500
500
500
ns
tRP
Pulse Width
RESET
(n/a for EN29F002AN)
Min
4
4
4
4
µs
tRSP
Setup Time
RESET
(n/a for EN29F002AN)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
23
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Table 10. AC CHARACTERISTICS
Write (Erase/Program) Operations
Alternate CE Controlled Writes
Parameter
Symbols
Speed Options
Description
JEDEC
Standard
-45
45
-55
55
-70
70
-90
90
Unit
ns
Min
Min
Min
Min
Min
Min
Write Cycle Time
tAVAV
tWC
0
35
20
0
0
45
25
0
0
45
30
0
0
45
45
0
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tAVEL
tELAX
tDVEH
tEHDX
tAS
tAH
tDS
tDH
tOES
Data Hold Time
0
0
0
0
Output Enable Setup Time
0
0
0
0
0
ns
ns
Output Enable Read
tOEH
Hold Time
Toggle and
Data Polling
10
Min
10
10
10
10
Read Recovery Time before
Write (
0
0
0
0
ns
tGHEL
tGHEL
High to
Low)
CE
OE
Min
Min
Min
Min
Typ
Max
Typ
Max
Typ
Max
Min
Min
0
0
0
0
0
0
0
0
ns
ns
ns
ns
µs
µs
s
tWLEL
tEHWH
tELEH
tEHEL
tWHWH1 tWHWH1
tWHWH2 tWHWH2
tWHWH3 tWHWH3
tWS
tWH
tCP
SetupTime
Hold Time
W E
W E
25
20
7
30
20
7
35
20
7
45
20
7
Write Pulse Width
Write Pulse Width High
tCPH
Programming Operation
Sector Erase Operation
Chip Erase Operation
Vcc Setup Time
200
0.3
5
200
0.3
5
200
0.3
5
200
0.3
5
s
3
3
3
3
s
35
50
500
35
50
500
35
50
500
35
50
500
s
µs
ns
tVCS
tVIDR
Rise Time to V
ID
Min
500
500
500
500
ns
tRP
RESET Pulse Width
(n/a for EN29F002AN)
Min
4
4
4
4
µs
tRSP
Setup Time
RESET
(n/a for EN29F002AN)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
24
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Table 11. ERASE AND PROGRAMMING PERFORMANCE
Limits
Max
Parameter
Typ
Unit
Comments
Sector Erase Time
0.3
5
35
200
5
sec
Excludes 00H programming prior to
erasure
Chip Erase Time
3
7
sec
µs
Byte Programming Time
Chip Programming Time
Erase/Program Endurance
Excludes system level overhead
Minimum 100K cycles guaranteed
2
sec
100K
cycles
Table 12. LATCH UP CHARACTERISTICS
Parameter Description
Input voltage with respect to Vss on A9 and
Min
Max
, and
RESET
OE
-1.0 V
12.0 V
Input voltage with respect to Vss on all other pins
Vcc Current
-1.0 V
Vcc + 1.0 V
100 mA
-100 mA
Note : These are latch up characteristics and the device should never be put under
these conditions. Refer to Absolute Maximum ratings for the actual operating limits.
Table 13. 32-PIN PLCC PIN CAPACITANCE @ 25°C, 1.0MHz
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
Max
Unit
C
IN
V
IN
Input Capacitance
4
6
pF
C
V
= 0
OUT
OUT
Output Capacitance
8
8
12
12
pF
pF
C
V
= 0
IN2
IN
Control Pin Capacitance
Table 14. 32-PIN TSOP PIN CAPACITANCE @ 25°C, 1.0MHz
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
Max
Unit
C
IN
V
IN
Input Capacitance
6
7.5
pF
C
V
= 0
OUT
OUT
Output Capacitance
8.5
7.5
12
9
pF
pF
C
V
= 0
IN2
IN
Control Pin Capacitance
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
25
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Table 15. DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150°C
10
Years
125°C
20
Years
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
26
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
SWITCHING WAVEFORMS
Figure 5. AC Waveforms for READ Operations
Figure 6. AC Waveforms for Chip/Sector Erase Operations
Notes:
1. SA is the sector address for sector erase.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
27
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
SWITCHING WAVEFORMS (continued)
Figure 7. Program Operation Timings
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. /DQ7 is the output of the complement of the data written to the device.
4.
DOUT is the output of data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations
Notes:
*DQ7 = Valid Data (The device has completed the embedded operation).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
28
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm
Operations
Notes:
DQ stops toggling (The device has completed the embedded operation).
*
6
Figure 10. Temporary Sector Unprotect Timing Diagram
11V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
29
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
SWITCHING WAVEFORMS (continued)
Figure 11. /RESET Timing Diagram
Figure 12. Alternate /CE Controlled Write Operation Timings
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. /DQ7 is the output of the complement of the data written to the device.
4.
DOUT is the output of data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
30
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
ORDERING INFORMATION
EN29F002A
T
- 45
P
C
P
PACKAGING CONTENT
Blank= Conventional
P=Pb free
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
PACKAGE
P = 32 Plastic DIP
J = 32 Plastic PLCC
T = 32 Plastic TSOP
SPEED
45 = 45ns
55 = 55ns
70 = 70ns
90 = 90ns
BOOT BLOCK ARCHITECTURE
T = Top Block
B = Bottom Block
BASE PART NUMBER
EN = EON Silicon Solution
29F = FLASH, 5V
002 = 256K x 8
A = Version A
(Blank) = with
function
RESET
N = without
function
RESET
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
31
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
PHYSICAL DIMENSIONS
PL 032 — 32-Pin Plastic Leaded Chip Carrier
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
32
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
PHYSICAL DIMENSIONS (continued)
PD 032 — 32-Pin Plastic DIP
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
33
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
PHYSICAL DIMENSIONS (continued)
TS 032 — 32-Pin Standard Thin Small
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
34
Rev. A, Issue Date: 2003/03/26
EN29F002A / EN29F002AN
Revisions List
Revision No Description
Date
A
Initial draft
3/26/2003
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
35
Rev. A, Issue Date: 2003/03/26
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