EN29F512-55PI_技术文档

EN29F512

512 Kbit (64K x 8-bit) 5V Flash Memory

FEATURES

• JEDEC Standard program and erase

• 5.0V operation for read/write/erase

commands

operations

• JEDEC standard

polling and toggle

DATA

• Fast Read Access Time

bits feature

- 45ns, 55ns, 70ns, and 90ns

• Single Sector and Chip Erase

• Sector Unprotect Mode

• Sector Architecture:

- 4 uniform sectors of 16Kbytes each

- Supports full chip erase

• Embedded Erase and Program Algorithms

- Individual sector erase supported

- Sector protection:

• Erase Suspend / Resume modes:

Read and program another Sector during

Erase Suspend Mode

Hardware locking of sectors to prevent

program or erase operations within

individual sectors

• 0.23 µm triple-metal double-poly

triple-well CMOS Flash Technology

• High performance program/erase speed

- Byte program time: 7µs typical

- Sector erase time: 300ms typical

- Chip erase time: 1.5s typical

• Low Vcc write inhibit < 3.2V

• 100K endurance cycle

• Package Options

• Low Standby Current

- 32-pin PDIP

- 1µA CMOS standby current-typical

- 1mA TTL standby current

- 32-pin PLCC

• Low Power Active Current

- 32-pin 8mm x 20mm TSOP (Type 1)

- 32-pin 8mm x 14mm TSOP (Type 1)

- 12mA typical active read current

- 30mA program/erase current

• Commercial and Industrial Temperature

Ranges

GENERAL DESCRIPTION

The EN29F512 is a 512-Kbit, electrically erasable, read/write non-volatile flash memory. Organized

into 64K bytes with 8 bits per byte, the 512K of memory is arranged in four uniform sectors of

16Kbytes each. Any byte can be programmed typically in 7µs. The EN29F512 features 5.0V

voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT

states in high-performance microprocessor systems.

The EN29F512 has separate Output Enable (

), Chip Enable (

), and Write Enable (

)

W E

OE

CE

controls, which eliminate bus contention issues. This device is designed to allow either single

Sector or full chip erase operation, where each Sector can be individually protected against

program/erase operations or temporarily unprotected to erase or program. The device can sustain a

minimum of 100K program/erase cycles on each Sector.

This Data Sheet may be revised by subsequent versions

Rev. A, Issue Date: 2003/10/20

1

or modifications due to changes in technical specifications.

EN29F512

TABLE 1. PIN DESCRIPTION

FIGURE 1. LOGIC DIAGRAM

Vcc

Pin Name

A0-A16

Function

Addresses

16

8

A0 - A15

DQ0 - DQ7

DQ0-DQ7

Data Inputs/Outputs

Chip Enable

EN29F512

CE

OE

W E

Vcc

Vss

CE

OE

Output Enable

WE

Write Enable

Supply Voltage

(5V ± 10% )

Vss

Ground

TABLE 2. SECTOR ARCHITECTURE

SIZE (Kbytes)

A15

1

A14

Sector

ADDRESSES

0C000h – 0FFFFh

08000h – 0BFFFh

04000h - 07FFFh

00000h - 03FFFh

3

2

1

0

16

1

0

1

0

1

0

This Data Sheet may be revised by subsequent versions

Rev. A, Issue Date: 2003/10/20

2

or modifications due to changes in technical specifications.

EN29F512

BLOCK DIAGRAM

DQ0-DQ7

Vcc

Vss

Block Protect Switches

Erase Voltage Generator

Input/Output Buffers

State

Control

WE

Program Voltage

Generator

Command

Register

STB

Chip Enable

Output Enable

Logic

Data Latch

CE

OE

Y-Decoder

Y-Gating

STB

Vcc Detector

A0-A15

Timer

X-Decoder

Cell Matrix

This Data Sheet may be revised by subsequent versions

Rev. A, Issue Date: 2003/10/20

3

or modifications due to changes in technical specifications.

EN29F512

FIGURE 2. PDIP

FIGURE 3. PLCC

FIGURE 4. TSOP

This Data Sheet may be revised by subsequent versions

Rev. A, Issue Date: 2003/10/20

4

or modifications due to changes in technical specifications.

EN29F512

TABLE 3. OPERATING MODES

512K FLASH USER MODE TABLE

USER MODE

A9

A8

A6

A1

A0

Ax/y

DQ(0-7)

C E

WE

OE

STANDBY

READ

H

L

X

H

X

L

X

A9

X

A8

X

A6

X

A1

X

A0

X

HI-Z

DQ (0-7)

HI-Z

Ax/y

X

OUTPUT DISABLE

READ

H

L

VID

L/H

L

MANUFACTURE

ID

MANUFACTURE ID

READ DEVICE ID

VERIFY SECTOR

PROTECTION

SECTOR

L

H

L

VID

X

L

H

L

X

DEVICE ID

CODE

L

Pulse

VID

L

VID

A9

X

L

H

X

H

X

L

X

CODE

X

PROTECTION

VERIFY SECTOR

UNPROTECTION

SECTOR

L

H

Pulse

VID

H

X

H

L

X

UNPROTECTION

WRITE

L

A8

A6

A1

A0

Ax/y

DIN (0-7)

NOTES:

1) L = V_IL, H = V_IH, V_ID= 11.0V ± 0.5V

2) X = Don’t care, either V_IHor V_IL

3) Ax/y: Ax = Addr(x), Ay = Addr(y)

TABLE 4. DEVICE IDENTIFICTION

512K FLASH MANUFACTURER/DEVICE ID TABLE

DQ(7-0)

A8

H⁽¹⁾

X⁽²⁾

A6

L

A1

L

A0

L

HEX

READ

MANUFACTURER ID

READ

MANUFACTURER ID

1C

DEVICE ID

21

L

H

DEVICE ID

NOTES:

1) If a Manufacturing ID is read with A8 = L, the chip will output a configuration code 7Fh. A further

Manufacturing ID must be read with A8 = H.

2) X = Don’t care

This Data Sheet may be revised by subsequent versions

Rev. A, Issue Date: 2003/10/20

5

or modifications due to changes in technical specifications.

EN29F512

USER MODE DEFINITIONS

Standby Mode

The EN29F512 has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical).

It is placed in CMOS-compatible standby when the pin is at V_CC± 0.5. The device also has a

CE

TTL-compatible standby mode, which reduces the maximum V_CCcurrent to < 1mA. It is placed in

TTL-compatible standby when the

pin is at V_IH. When in standby modes, the outputs are in a

CE

high-impedance state independent of the

input.

OE

Read Mode

The device is automatically set to reading array data after device power-up. No commands are

required to retrieve data. The device is also ready to read array data after completing an Embedded

Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode.

The system can read array data using the standard read timings, except that if it reads at an address

within erase-suspended sectors, the device outputs status data. After completing a programming

operation in the Erase Suspend mode, the system may once again read array data with the same

exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode.

The system must issue the reset command to re-enable the device for reading array data if DQ5

goes high, or while in the autoselect mode. See “Reset Command” section.

See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more

information. The Read Operations table provides the read parameters, and Read Operation Timings

diagram shows the timing diagram.

Output Disable Mode

When the

pin is at a logic high level (V_IH), the output from the EN29F512 is disabled. The

OE

output pins are placed in a high impedance state.

Auto Select Identification Mode

The autoselect mode provides manufacturer and device identification, and sector protection

verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for

programming equipment to automatically match a device to be programmed with its corresponding

programming algorithm. However, the autoselect codes can also be accessed in-system through the

command register.

When using programming equipment, the autoselect mode requires VID (10.5 V to 11.5 V) on

address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage

Method) table. In addition, when verifying sector protection, the sector address must appear on the

appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The

Command Definitions table shows the remaining address bits that are don’t care. When all

necessary bits have been set as required, the programming equipment may then read the

corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system; the host system can issue the autoselect command via

the command register, as shown in the Command Definitions table. This method does not require

VID. See “Command Definitions” for details on using the autoselect mode.

This Data Sheet may be revised by subsequent versions

Rev. A, Issue Date: 2003/10/20

6

or modifications due to changes in technical specifications.

EN29F512

Reset Command

Writing the reset command to the device resets the device to reading array data. Address bits are

don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence

before erasing begins. This resets the device to reading array data. Once erasure begins, however,

the device ignores reset commands until the operation is complete. The reset command may be

written between the sequence cycles in a program command sequence before programming begins.

This resets the device to reading array data (also applies to programming in Erase Suspend mode).

Once programming begins, however, the device ignores reset commands until the operation is

complete.

The reset command may be written between the sequence cycles in an autoselect command

sequence. Once in the autoselect mode, the reset command must be written to return to reading

array data (also applies to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command returns the device

to reading array data (also applies during Erase Suspend).

Write Mode

Programming is a four-bus-cycle operation. The program command sequence is initiated by writing

two unlock write cycles, followed by the program set-up command. The program address and data

are written next, which in turn initiate the Embedded Program algorithm. The system is not required

to provide further controls or timings. The device automatically provides internally generated

program pulses and verifies the programmed cell margin. Table 5 (Command Definitions) shows the

address and data requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the device then returns to reading array data

and addresses are no longer latched. The system can determine the status of the program operation

by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm are ignored.

Programming is allowed in any sequence and across sector boundaries. A bit cannot be

programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to

“1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a

succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

COMMAND DEFINITIONS

The operations of the EN29F512 are selected by one or more commands written into the

command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program,

Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data

sequences written at specific addresses via the command register. The sequences for the

specified operation are defined in the Command Table (Table 5). Incorrect addresses, incorrect

data values or improper sequences will reset the device to the read mode.

This Data Sheet may be revised by subsequent versions

Rev. A, Issue Date: 2003/10/20

7

or modifications due to changes in technical specifications.

EN29F512

Table 5. EN29F512 Command Definitions

1^st

2^nd

3^rd

4^th

5^th

6^th

Command

Write

Write Cycle

Sequence

Write Cycle

Write Cycle Write Cycle

Cycles

Req’d

Read/Reset

Addr Data

RA RD

XXXh F0h

555h AAh 2AAh 55h 555h F0h

555h AAh 2AAh 55h 555h 90h

555h AAh 2AAh 55h 555h A0h

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h

xxxh B0h

xxxh 30h

Addr

Data Addr Data Addr Data Addr Data Addr Data

1

4

Read

Reset

Read/Reset

RA

RD

000h/ 7Fh/

AutoSelect

Manufacturer ID

AutoSelect Device ID

4

100h 1Ch

01h

21h

BA & 00h/

AutoSelect Sector

Protect Verify

02h

PA

01h

PD

4

6

1

Byte Program

Chip Erase

Sector Erase

BA

30h

Sector Erase Suspend

Sector Erase Resume

Notes:

RA = Read Address: address of the memory location to be read. This one is a read cycle.

RD = Read Data: data read from location RA during Read operation. This one is a read cycle.

PA = Program Address: address of the memory location to be programmed

PD = Program Data: data to be programmed at location PA

BA = Sector Address: address of the Sector to be erased. Address bits A15-A14 uniquely select any Sector.

The data is 00h for an unprotected sector and 01h for a protected sector.

Byte Programming Command

Programming the EN29F512 is performed on a byte-by-byte basis using a four bus-cycle operation

(two unlock write cycles followed by the Program Setup command and Program Data Write cycle).

When the program command is executed, no additional CPU controls or timings are necessary. An

internal timer terminates the program operation automatically. Address is latched on the falling edge

of

or

, whichever is last; data is latched on the rising edge of

or

CE

, whichever is first.

W E

CE

W E

The program operation is completed when EN29F512 returns the equivalent data to the

programmed location.

Programming status may be checked by sampling data on DQ7 (

polling) or on DQ6 (toggle

DATA

bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is

exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read

mode.

Chip Erase Command

Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the

chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required

to provide any controls or timings during these operations. The Command Definitions table shows the

address and data requirements for the chip erase command sequence.

This Data Sheet may be revised by subsequent versions

Rev. A, Issue Date: 2003/10/20

8

or modifications due to changes in technical specifications.

EN29F512

Any commands written to the chip during the Embedded Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,

the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in

“AC Characteristics” for parameters, and Chip/Sector Erase Operation Timings for timing waveforms.

Sector Erase Command

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two

un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector erase command. The Command Definitions table

shows the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram the memory prior to erase. The Embedded Erase

algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical

erase. The system is not required to provide any controls or timings during these operations.

This device does not support multiple sector erase commands. Sector Erase operation will

commence immediately after the first 30h command is written. The first sector erase operation must

finish before another sector erase command can be given.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other

commands are ignored.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses

are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or

DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the

algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC

Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing

waveforms.

Erase Suspend / Resume Command

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for erasure. This command is valid only during the

sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation

or Embedded Program algorithm. Addresses are “don’t-cares” when writing the Erase Suspend command.

When the Erase Suspend command is written during a sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to

any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)

Normal read and write timings and command definitions apply. Reading at any address within erase-

suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”

for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data

within non-suspended sectors. The system can determine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more

information.

This Data Sheet may be revised by subsequent versions

Rev. A, Issue Date: 2003/10/20

9

or modifications due to changes in technical specifications.

EN29F512

The system must write the Erase Resume command (address bits are “don’t care”) to exit the

erase suspend mode and continue the sector erase operation. Further writes of the Resume command

are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase operations in any sector. The

hardware sector unprotection feature re-enables both program and erase operations in previously

protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure re-

quires a high voltage (VID) on address pin A9 and the control pins. Contact Eon Silicon Solution, Inc. for

an additional supplement on this feature.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

10

Rev. A, Issue Date: 2003/10/20

EN29F512

WRITE OPERATION STATUS

DQ7

DATA

Polling

The EN29F512 provides

Polling on DQ7 to indicate to the host system the status of the

DATA

embedded operations. The

Polling feature is active during the Byte Programming, Sector

DATA

Erase, Chip Erase, and Erase Suspend. (See Table 6)

When the Byte Programming is in progress, an attempt to read the device will produce the

complement of the data last written to DQ7. Upon the completion of the Byte Programming, an

attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,

polling is valid after the rising edge of the fourth

or

WE

pulse in the four-cycle sequence.

CE

DATA

When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the

DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7

output during the read. For Chip Erase, the

polling is valid after the rising edge of the sixth

DATA

pulse in the six-cycle sequence. For Sector Erase, polling is valid after the last

DATA

or

W E

CE

rising edge of the sector erase

or

pulse.

CE

W E

Polling must be performed at any address within a sector that is being programmed or

DATA

erased and not a protected sector. Otherwise,

polling may give an inaccurate result if the

DATA

address used is in a protected sector.

Just prior to the completion of the embedded operations, DQ7 may change asynchronously when

the output enable (

) is low. This means that the device is driving status information on DQ7 at

OE

one instant of time and valid data at the next instant of time. Depending on when the system

samples the DQ7 output, it may read the status of valid data. Even if the device has completed the

embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid.

The valid data on DQ0-DQ7 will be read on the subsequent read attempts.

The flowchart for

Polling (DQ7) is shown on Flowchart 5. The

Polling (DQ7) timing

DATA

diagram is shown in Figure 8.

DQ6

Toggle Bit I

The EN29F512 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the

embedded programming and erase operations. (See Table 6)

During an embedded Program or Erase operation, successive attempts to read data from the device

at any address (by toggling

or

) will result in DQ6 toggling between “zero” and “one”. Once

CE

OE

the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be

read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the

rising edge of the fourth

pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is

WE

valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after

the last rising edge of the Sector Erase

erase time-out window.

pulse. The Toggle Bit is also active during the sector

W E

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

11

Rev. A, Issue Date: 2003/10/20

EN29F512

In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then

stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all

selected sectors are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read

mode without changing data in all protected sectors.

Toggling either

or

will cause DQ6 to toggle.

OE

CE

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is

shown in Figure 9.

DQ5 Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.

Under these conditions DQ5 produces a “1.” (The Toggle Bit (DQ6) should also be checked at this

time to make sure that the DQ5 is not a “1” due to the device having returned to read mode.) This is

a failure condition that indicates the program or erase cycle was not successfully completed. .

DATA

Polling (DQ7), Toggle Bit (DQ6) and Erase Toggle Bit (DQ2) still function under this condition.

Setting the to V_IHwill partially power down the device under those conditions.

CE

The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue the reset command to return the device to reading

array data.

DQ2 Erase Toggle Bit II

The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle

Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the

system reads at addresses within those sectors that have been selected for erasure. (The system may

use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both

status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and

DQ6.

Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See

also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing

diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.

Typically, a system would note and store the value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or erase operation. The system can read array data on

DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped

toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

12

Rev. A, Issue Date: 2003/10/20

EN29F512

completed the program or erase operation. If it is still toggling, the device did not complete the operation

successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read

cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to

perform other system tasks. In this case, the system must start at the beginning of the algorithm when it

returns to determine the status of the operation (top of Flowchart 6).

Table 6. Status Register Bits

DQ

Name

Logic Level

Definition

Erase Complete or

erase Sector in Erase suspend

Erase On-Going

‘1’

‘0’

DATA

Program Complete or

7

POLLING

DQ7

data of non-erase Sector during Erase Suspend

DQ7

‘-1-0-1-0-1-0-1-’

DQ6

Program On-Going

Erase or Program On-going

Read during Erase Suspend

TOGGLE

BIT

6

5

Erase Complete

‘-1-1-1-1-1-1-1-‘

‘1’

‘0’

Program or Erase Error

ERROR BIT

Program or Erase On-going

Chip Erase, Erase or Erase suspend on

currently addressed

‘-1-0-1-0-1-0-1-’

DQ2

Sector. (When DQ5=1, Erase Error due to

currently addressed Sector. Program during

Erase Suspend on-going at current address

TOGGLE

BIT

2

Erase Suspend read on

non Erase Suspend Sector

Notes:

DQ7

Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5

DATA

for Program or Erase Success.

DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.

Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5 Error Bit: set to “1” if failure in programming or erase

DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

13

Rev. A, Issue Date: 2003/10/20

EN29F512

DATA PROTECTION

Power-up Write Inhibit

During power-up, the device automatically resets to READ mode and locks out write cycles. Even

with

W E

= V ,

= V_ILand

= V_IH, the device will not accept commands on the rising edge of

OE

CE

.

WE

IL

Low V_CCWrite Inhibit

During V_CCpower-up or power-down_,the EN29F512 locks out write cycles to protect against any

unintentional writes. If V_CC< V_LOK, the command register is disabled and all internal program or

erase circuits are disabled. Under this condition, the device will reset to the READ mode.

Subsequent writes will be ignored until V_CC> V_LKO.

Write “Noise” Pulse Protection

Noise pulses less than 5ns on

command register.

,

or

will neither initiate a write cycle nor change the

WE

OE CE

Logical Inhibit

If

=V or

=V , writing is inhibited. To initiate a write cycle,

and

must be a logical

W E

CE

WE

,

CE

are all logical zero (not recommended usage), it will be considered a

IH

“zero”. If

, and

CE

OE

W E

write.

Sector Protect and Unprotect

The hardware sector protection feature disables both program and erase operations in any sector.

The hardware sector unprotection feature re-enables both program and erase operation in

previously protected sectors.

Sector protection/unprotection must be implemented using programming equipment. The procedure

requires a high voltage (V_ID) on address pin A9 and the control pins. Contact Eon Silicon Solution,

Inc. for an additional supplement on this feature.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

14

Rev. A, Issue Date: 2003/10/20

EN29F512

EMBEDDED ALGORITHMS

Flowchart 1. Embedded Program

START

Write Program

Command Sequence

(shown below)

Data Poll Device

Last

Increment

Address

No

Address?

Yes

Programming Done

Flowchart 2. Embedded Program Command Sequence

See the Command Definitions section for more information.

555H / AAH

2AAH / 55H

555H / A0H

PROGRAM ADDRESS / PROGRAM DATA

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

15

Rev. A, Issue Date: 2003/10/20

EN29F512

Flowchart 3. Embedded Erase

START

Write Erase

Command Sequence

(shown below)

Data Polling Device or Toggle Bit

Successfully Completed

ERASE Done

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

16

Rev. A, Issue Date: 2003/10/20

EN29F512

Flowchart 4. Embedded Erase Command Sequence

See the Command Definitions section for more information.

Chip Erase

555H/AAH

Sector Erase

555H/AAH

2AAH/55H

555H/80H

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H

555H/AAH

2AAH/55H

Sector Address/30H

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

17

Rev. A, Issue Date: 2003/10/20

EN29F512

Flowchart 5.

DATA

Polling Algorithm

Start

Read Data

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Data

Yes

DQ7 = Data?

No

Fail

Pass

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

18

Rev. A, Issue Date: 2003/10/20

EN29F512

Flowchart 6. Toggle Bit Algorithm

Start

Read Data

No

DQ6 = Toggle?

Yes

No

DQ5 = 1?

Yes

Read Data

No

DQ6 = Toggle?

Yes

Fail

Pass

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

19

Rev. A, Issue Date: 2003/10/20

EN29F512

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

V

_CC(Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7.0 V

A9, OE# (Note 2) . . . . . . . . . . . . . . . –0.5 V to 11.5 V

All other pins (Note 1) . . . . . . . . . . . . –0.5 V to Vcc+0.5V

Output Short Circuit Current (Note 3) . . . . . . . . . 200 mA

Notes:

1.

2.

3.

Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot

VSS to –1.0V for periods of up to 50 ns and to –2.0 V for periods of up to 20 ns. See Left Figure below.

Maximum DC voltage on input and I/O pins is V CC + 0.5 V. During voltage transitions, input and I/O

pins may overshoot to VCC + 2.0 V for periods up to 20 ns. See Right Figure below.

Minimum DC input voltage on A9 pin is –0.5 V. During voltage transitions, A9 and OE# may

undershoot VSS to –1.0V for periods of up to 20 ns and to –2.0 V for periods of up to 20 ns. See Left

Figure. Maximum DC input voltage on A9 and OE# is 11.5 V which may overshoot to 12.5 V for

periods up to 20 ns.

No more than one output shorted to ground at a time. Duration of the short circuit should not be greater

than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the operational sections of this specification is

not implied. Exposure of the device to absolute maximum rating conditions for extended periods may

affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T A ) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T A ). . . . . . . . . . -40°C to +85°C

V_CCSupply Voltages

V_CCfor ± 5% devices . . . . . . . . . . . . +4.75 V to +5.25 V

V

_CCfor ± 10% devices . . . . . . . . . . . +4.50 V to +5.50 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

Maximum Negative Overshoot

Waveform

Maximum Positive Overshoot

Waveform

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

20

Rev. A, Issue Date: 2003/10/20

EN29F512

Table 7. DC Characteristics

(T_a= 0°C to 70°C or - 40°C to 85°C; V_CC= 5.0V ± 10%)

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Conditions

0V≤ V ≤ Vcc

Min

Max

±5

Unit

µA

I

LI

IN

±5

µA

I

0V≤ V

≤ Vcc

LO

OUT

= V ;

= V

;

IH

CE

OE

IL

f = 6MHz

Supply Current (read) TTL Byte

30

mA

I

CC1

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

1.0

5.0

MA

µA

I

= V

CE

CC2

CC3

IH

= Vcc ± 0.3V

Byte program, Sector or Chip

Erase in progress

mA

V

I

CC4

Supply Current (Program or Erase)

Input Low Voltage

30

-0.5

2

0.8

V

IL

Vcc +

Input High Voltage

V

IH

0.5

Output Low Voltage

0.45

V

I

= 2 mA

OL

Output High Voltage TTL

2.4

V

I

= -2.5 mA

OH

Vcc -

Output High Voltage CMOS

V

= -100 µA

OH

0.4V

A9 Voltage (Electronic Signature)

A9 Current (Electronic Signature)

10.5

3.2

11.5

100

V

ID

A9 = V_ID

µA

I

LIT

Supply voltage (Erase and

V

LKO

4.2

V

Program lock-out)

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

21

Rev. A, Issue Date: 2003/10/20

EN29F512

Table 8. AC CHARACTERISTICS

Read-only Operations Characteristics

Parameter

Symbols

Speed Options

JEDEC

Standard

-45

-55

-70

-90

90

Unit

Description

Test Setup

Min

45

55

70

ns

t_AVAV

t_RC

Read Cycle Time

= V

CE

OE

IL

Max

45

55

70

90

ns

Address to Output Delay

t_AVQV

t_ACC

IL

Max

45

25

10

55

30

15

70

30

20

90

35

20

ns

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable To Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z

= V

OE

Output Enable to Output High Z

Output Hold Time from

Min

0

ns

t_AXQX

t_OH

Addresses,

or ,

CE OE

whichever occurs first

Notes:

For -45, -55

Vcc = 5.0V ± 5%

Output Load : 1 TTL gate and 30pF

Input Rise and Fall Times: 5ns

Input Rise Levels: 0.0 V to 3.0 V

Timing Measurement Reference Level, Input and Output: 1.5 V

For all others:

Vcc = 5.0V ± 10%

Output Load: 1 TTL gate and 100 pF

Input Rise and Fall Times: 20 ns

Input Pulse Levels: 0.45 V to 2.4 V

Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

22

Rev. A, Issue Date: 2003/10/20

EN29F512

Table 9. AC CHARACTERISTICS

Write (Erase/Program) Operations

Parameter

Symbols

Speed Options

JEDEC

Standard

Description

-45

-55

-70

-90

Unit

Min

45

55

70

90

ns

t_AVAV

t_WC

Write Cycle Time

0

35

20

0

45

25

0

45

30

0

45

0

ns

t_AVWL

t_WLAX

t_DVWH

t_WHDX

t_AS

t_AH

Address Setup Time

Address Hold Time

Data Setup Time

t_DS

t_DH

t_OES

Data Hold Time

Min

MIn

Min

0

ns

Output Enable Setup Time

Read

Output Enable

Toggle and

t_OEH

Hold Time

10

Polling

DATA

Read Recovery Time before

Min

0

ns

t_GHWL

Write (

High to

Low)

W E

OE

CE

Min

Typ

Max

Typ

Max

Typ

Max

Min

0

ns

µs

s

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

t_WP

t_WPH

SetupTime

Hold Time

25

20

7

30

20

7

35

20

7

45

20

7

Write Pulse Width

Write Pulse Width High

t_WHWH1t_WHWH1

t_WHWH2t_WHWH2

t_WHWH3t_WHWH3

Programming Operation

200

0.3

5

200

0.3

5

200

0.3

5

200

0.3

5

Sector Erase Operation

s

1.5

17.5

50

1.5

17.5

50

1.5

17.5

50

1.5

17.5

50

s

Chip Erase Operation

Vcc Setup Time

s

µs

t_VCS

Min

500

ns

t_VIDR

Rise Time to V

ID

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

23

Rev. A, Issue Date: 2003/10/20

EN29F512

Table 10. AC CHARACTERISTICS

Write (Erase/Program) Operations

Alternate CE Controlled Writes

Parameter

Symbols

Speed Options

JEDEC

Standard

Description

-45

-55

-70

-90

Unit

Min

45

55

70

90

ns

Write Cycle Time

t_AVAV

t_WC

0

35

20

0

45

25

0

45

30

0

45

0

ns

Address Setup Time

Address Hold Time

Data Setup Time

t_AVEL

t_ELAX

t_DVEH

t_EHDX

t_AS

t_AH

t_DS

t_DH

t_OES

Data Hold Time

Min

0

ns

Output Enable Setup Time

Output

Enable

Read

Toggle and

Data Polling

t_OEH

10

Hold Time

Read Recovery Time before

Min

0

ns

t_GHEL

Write (

High to

Low)

CE

OE

Min

Typ

Max

Typ

Max

Typ

Max

Min

0

ns

µs

s

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

SetupTime

Hold Time

W E

25

20

7

30

20

7

35

20

7

45

20

7

Write Pulse Width

t_CPH

Write Pulse Width High

t_WHWH

t_WHWH1

t_WHWH2

t_WHWH3

Programming Operation

1

200

0.3

5

200

0.3

5

200

0.3

5

200

0.3

5

t_WHWH

Sector Erase Operation

2

s

1.5

17.5

50

1.5

17.5

50

1.5

17.5

50

1.5

17.5

50

s

t_WHWH

Chip Erase Operation

Vcc Setup Time

3

s

µs

t_VCS

Min

500

ns

t_VIDR

Rise Time to V

ID

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

24

Rev. A, Issue Date: 2003/10/20

EN29F512

Table 11. ERASE AND PROGRAMMING PERFORMANCE

Limits

Max

Parameter

Comments

Typ

Unit

Sector Erase Time

Chip Erase Time

0.3

5

sec

Excludes 00H programming prior to

erasure

1.5

7

17.5

200

sec

µs

Byte Programming Time

Chip Programming Time

Erase/Program Endurance

Excludes system level overhead

Minimum 100K cycles guaranteed

0.5

1.25

sec

100K

cycles

Table 12. LATCH UP CHARACTERISTICS

Parameter Description

Min

Max

Input voltage with respect to Vss on all pins except I/O pins

-1.0 V

12.0 V

(including A9 and

)

OE

Input voltage with respect to Vss on all I/O Pins

-1.0 V

Vcc + 1.0 V

100 mA

Vcc Current

-100 mA

Note : These are latch up characteristics and the device should never be put under

these conditions. Refer to Absolute Maximum ratings for the actual operating limits.

Table 13. 32-PIN PLCC PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol

Parameter Description

Test Setup

= 0

Typ

Max

Unit

C

IN

V

IN

Input Capacitance

4

6

pF

C

V

= 0

OUT

Output Capacitance

8

12

pF

C

V

= 0

IN2

IN

Control Pin Capacitance

Table 14. 32-PIN TSOP PIN CAPACITANCE @ 25°C, 1.0MHz

Parameter Symbol

Parameter Description

Test Setup

= 0

Typ

Max

Unit

C

IN

V

IN

Input Capacitance

6

7.5

pF

C

V

= 0

OUT

Output Capacitance

8.5

7.5

12

9

pF

C

V

= 0

IN2

IN

Control Pin Capacitance

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

25

Rev. A, Issue Date: 2003/10/20

EN29F512

Table 15. DATA RETENTION

Parameter Description

Test Conditions

Min

Unit

150°C

10

Years

Minimum Pattern Data Retention Time

125°C

20

Years

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

26

Rev. A, Issue Date: 2003/10/20

EN29F512

SWITCHING WAVEFORMS

Figure 5. AC Waveforms for READ Operations

Figure 6. AC Waveforms for Chip/Sector Erase Operations

Notes:

1. SA is the Sector address for Sector erase.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

27

Rev. A, Issue Date: 2003/10/20

EN29F512

SWITCHING WAVEFORMS (continued)

Figure 7. Program Operation Timings

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. /DQ7 is the output of the complement of the data written to the device.

4.

D_OUTis the output of data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

28

Rev. A, Issue Date: 2003/10/20

EN29F512

Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm

Operations

Notes:

*DQ₇= Valid Data (The device has completed the embedded operation).

Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm

Operations

Notes:

*DQ₆stops toggling (The device has completed the embedded operation).

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

29

Rev. A, Issue Date: 2003/10/20

EN29F512

SWITCHING WAVEFORMS (continued)

Figure 10. Alternate /CE Controlled Write Operation Timings

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. /DQ7 is the output of the complement of the data written to the device.

4.

D_OUTis the output of data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

30

Rev. A, Issue Date: 2003/10/20

EN29F512

ORDERING INFORMATION

EN29F512

- 45

J

C

P

PACKAGING CONTENT

Blank= Conventional

P=Pb free

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (-40°C to +85°C)

PACKAGE

P = 32 Plastic DIP

J = 32 Plastic PLCC

T = 32 Plastic 8mm x 20mm TSOP

S = 32 Plastic 8mm x 14mm TSOP

SPEED

45 = 45ns

55 = 55ns

70 = 70ns

90 = 90ns

BASE PART NUMBER

EN = Eon Silicon Solution Inc.

29F = FLASH, 5V

512 = 64K x 8

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

31

Rev. A, Issue Date: 2003/10/20

EN29F512

PHYSICAL DIMENSIONS

PL 032 — 32-Pin Plastic Leaded Chip Carrier

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

32

Rev. A, Issue Date: 2003/10/20

EN29F512

PHYSICAL DIMENSIONS (continued)

PD 032 — 32-Pin Plastic DIP

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

33

Rev. A, Issue Date: 2003/10/20

EN29F512

PHYSICAL DIMENSIONS (continued)

TS 032 — 32-Pin Standard Thin Small

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

34

Rev. A, Issue Date: 2003/10/20

EN29F512

Revisions List

Description

Date

Revision No

A

Initial draft

10/20/2003

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

35

Rev. A, Issue Date: 2003/10/20


型号：	EN29F512-55PI
厂家：	EON SILICON SOLUTION INC.
描述：	512 Kbit (64K x 8-bit) 5V Flash Memory 512千位（ 64K ×8位）， 5V闪存闪存存储内存集成电路光电二极管
文件：	总35页 (文件大小：427K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EN29F512-55PI [EON]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E