EN29NS128B0-7DW [EON]
Stacked Multi-Chip Product (MCP) Flash Memory and RAM; 堆叠式多芯片产品（ MCP ）闪存和RAM
| 型号： | EN29NS128B0-7DW |
| 厂家： | 
EON SILICON SOLUTION INC. |
| 描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 文件： | 总8页 (文件大小：637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EN71NS128B0
EN71NS128B0 Base MCP
Stacked Multi-Chip Product (MCP) Flash Memory and RAM
128 Megabit (8M x 16-bit) CMOS 1.8 Volt-only Simultaneous
Operation Burst Mode Flash Memory and
32 Megabit (2M x 16-bit) Pseudo Static RAM
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7V to 1.95V
Operating Temperature
- 25°C to +85°C
High performance
- 70 ns @ random access
- 7 ns @ burst access (108MHz)
Package
- 8 x 9.2mm 56 ball FBGA
General Description
The EN71NS series is a product line of stacked Multi-Chip Product (MCP) packages and consists of:
E29NS128 (Burst mode) Flash memory die.
Pseudo SRAM.
For detailed specifications, Please refer to the individual datasheets listed in the following table.
Device
Document
EN29NS128
ENPSS32
NOR Flash
Pseudo SRAM
Product Selector Guide
128 Mb Flash Memories
Device-Model#
EN71NS128B0
pSRAM density
32M pSRAM
70ns at Async. Mode
7ns at Burst Read
70ns at Async. Mode
7ns at Burst Read
Flash Access time
pSRAM Access time
pSRAM Burst mode
max frequency
pSRAM Burst mode
max frequency
108MHz
108MHz
Package
56-ball FBGA
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
1
Rev. A, Issue Date: 2009/7/24
EN71NS128B0
MCP Block Diagram
NOR FLASH + PSRAM DIAGRAM
Note: Amax = A22
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
2
Rev. A, Issue Date: 2009/7/24
EN71NS128B0
Connection Diagram
MCP
Flash-only Addresses
A22 – A21
Shared Addresses
Shared ADQ Pins
EN71NS128B0
A20 – A16
ADQ15 – ADQ0
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
3
Rev. A, Issue Date: 2009/7/24
EN71NS128B0
Pin Description
Signal
Description
A22–A16
Address Inputs
A/DQ15–A/DQ0 Multiplexed Address / Data input / output
CE#
OE#
Chip Enable Input. Asynchronous relative to CLK for the Burst mode.
Output Enable Input. Asynchronous relative to CLK for the Burst mode.
WE#
Write Enable Input.
VCCQ/VCC
VSSQ/GND
NC
Device Power Supply (1.65 V–1.95 V).
Ground
No Connect; not connected internally
RDY
Ready output; indicates the status of the Burst read. VOL = data invalid, VOH = data valid.
The first rising edge of CLK in conjunction with AVD# low latches address input and
activates burst mode operation. After the initial word is output, subsequent rising edges
of CLK increment the internal address counter. CLK should remain low during
asynchronous access.
CLK
Address Valid input. Indicates to device that the valid address is present on the address
inputs (address bits A15–A0 are multiplexed, address bits A21–A16 are address only).
VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched on rising edge of CLK.
AVD#
VIH = device ignores address inputs
RESET#
WP#
Hardware reset input. VIL = device resets and returns to reading array data
Hardware write protect input. VIL = disables writes to SA129-130. Should be at VIH for all
other conditions.
At 11 V, accelerates programming; automatically places device in Accelerated Program
mode. At VIL, disables program and erase functions. Should be at VIH for all other
conditions. (Applying high voltage on MCP package is prohibited; otherwise, internal
RAM may be damaged easily!)
ACC
CRE
Control register enable: when CRE is high, WRITE operations laod the RCR or BCR,
and READ operations access the RCR, BCR, or DIDR.
Lower byte enable. DQ7~DQ0
LB#
UB#
Upper byte enable. DQ8~DQ15
Provides data-valid feedback during burst READ and WRITE operations, WAIT is used
to arbitrate collisions between refresh and wrapping within the burst length. WAIT should
be ignored during asynchronous operation. WAIT is High-Z when CE# is HIGH
WAIT
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
4
Rev. A, Issue Date: 2009/7/24
EN71NS128B0
Operating Mode (For Asynchronous mode)
Operating Mode (For Synchronous Burst mode)
Note: X=don’t care. H=logic high. L=logic low. V= Valid data
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
5
Rev. A, Issue Date: 2009/7/24
EN71NS128B0
ORDERING INFORMATION
EN29NS 128
B0 -
7
D
W
P
PACKAGING CONTENT
(Blank) = Conventional
P = RoHS compliant
TEMPERATURE RANGE
W = Wireless (-25°C to +85°C)
PACKAGE
D = 56-Ball Very Thin Fine Pitch BGA (VFBGA)
0.50mm pitch, 9.2mm x 8mm package
BURST READ ACCESS TIME
7 = 7ns
Pseudo SRAM density
B0 = 32Mb
DENSITY
128 = 128Megabit (8M x 16 Bit)
BASE PART NUMBER
EN = Eon Silicon Solution Inc.
29NS = Simultaneous Read/Write, Burst Mode Flash Memory with Multiplexed I/O 1.8V
Operation
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
6
Rev. A, Issue Date: 2009/7/24
EN71NS128B0
PACKAGE MECHANICAL
56-ball Thin Fine-Pitch Ball Grid Array (TFBGA) 8 x 9.2 mm Package
DIMENSION IN MM
SYMBOL
MIN.
- - -
NOR
- - -
MAX
1.20
0.26
0.94
8.10
9.30
- - -
A
A1
A2
D
0.16
0.84
7.90
9.10
- - -
0.21
0.89
8.00
9.20
6.50
4.50
0.50
0.30
E
D1
E1
e
- - -
- - -
- - -
- - -
b
0.25
0.35
Note : 1. Coplanarity: 0.1 mm
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
7
Rev. A, Issue Date: 2009/7/24
EN71NS128B0
Revisions List
Revision No
Description
Date
A
Initial Release
2009/07/24
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
8
Rev. A, Issue Date: 2009/7/24
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