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EM428M1644RTA-5F [EOREX]

128Mb (2M】4Bank】16) Double DATA RATE SDRAM; 128MB （ 2M 】 4Bank 】 16 ），双倍数据速率SDRAM
EM428M1644RTA-5F
型号： EM428M1644RTA-5F
厂家： EOREX CORPORATION    EOREX CORPORATION
描述：

128Mb (2M】4Bank】16) Double DATA RATE SDRAM
128MB （ 2M 】 4Bank 】 16 ），双倍数据速率SDRAM

动态存储器 双倍数据速率
文件： 总20页 (文件大小：338K)
中文：  中文翻译
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eorex  
EM428M1644RTA  
128Mb (2M×4Bank×16)  
Double DATA RATE SDRAM  
Features  
Description  
• Internal Double-Date-Rate architecture with 2  
Accesses per clock cycle.  
The EM428M1644RTA is high speed Synchronous  
graphic RAM fabricated with ultra high performance  
CMOS process containing 134,217,728 bits which  
organized as 2Meg words x 4 banks by 16 bits.  
The 128Mb DDR SDRAM uses a double data rate  
architecture to accomplish high-speed operation.  
The data path internally prefetches multiple bits and  
It transfers the datafor both rising and falling edges  
of the system clock.It means the doubled data  
bandwidth can be achieved at the I/O pins.  
• VDD/VDDQ= 2.5V 0.2V for (-75 and -6)  
• VDD/VDDQ= 2.6V 0.1V for (-5 )  
• 2.5V SSTL-2 compatible I/O  
• Burst Length (B/L) of 2, 4, 8  
• 2,2.5,3 Clock read latency  
• Bi-directional,intermittent data strobe(DQS)  
• All inputs except data and DM are sampled  
at the positive edge of the system clock.  
• Data Mask (DM) for write data  
Available packages:TSOPII 66P 400mil.  
• Sequential & Interleaved Burst type available  
• Auto Precharge option for each burst accesses  
• DQS edge-aligned with data for Read cycles  
• DQS center-aligned with data for Write cycles  
• DLL aligns DQ & DQS transitions with CLK’s  
• Auto Refresh and Self Refresh  
• 4,096 Refresh Cycles / 64ms  
Ordering Information  
Part No  
Organization  
Max. Freq  
Package  
Grade  
Pb  
EM428M1644RTA-75F  
8M X 16  
133MHz @CL2.5  
66pin TSOP(ll) Commercial Free  
66pin TSOP(ll) Commercial Free  
EM428M1644RTA-6F  
EM428M1644RTA-5F  
8M X 16  
8M X 16  
166MHz @CL2.5  
200MHz @CL3  
66pin TSOP(ll)  
Commercial Free  
EM 42 8M 16 4 4 R T A - X F E  
EOREX Memory  
DDR SDRAM  
Grade  
E: extended temp.  
Package  
Density  
F: Pb-free  
BM: 32 Mega  
AM: 16 Mega  
8M: 8 Mega  
4M: 4 Mega  
2M: 2 Mega  
1M: 1 Mega  
Min Cycle Time (Max Freq.)  
-5: 5ns (200MHz)  
-6: 6ns (166MHz)  
-75: 7.5ns (133MHz)  
Organization  
16: x16  
Refresh  
4: 4K  
Revision  
A: 1st  
Package  
T: TSOP  
Interface  
R: 2.5V  
Bank  
4: 4Bank  
Apr. 2007  
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1/20  
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EM428M1644RTA  
* EOREX reserves the right to change products or specification without notice.  
Apr. 2007  
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eorex  
EM428M1644RTA  
Pin Assignment  
66pin TSOP-II / (400mil × 875mil) / (0.65mm Pin pitch)  
Apr. 2007  
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3/20  
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EM428M1644RTA  
Pin Description (Simplified)  
Pin  
Name  
Function  
(System Clock)  
Clock input active on the Positive rising edge except for DQ and  
DM are active on both edge of the DQS.  
CLK and /CLK are differential clock inputs.  
(Chip Select)  
45,46  
CLK,/CLK  
/CS enables the command decoder when ”L” and disable the  
command decoder when “H”.The new command are over-  
Looked when the command decoder is disabled but previous  
operation will still continue.  
24  
/CS  
(Clock Enable)  
Activates the CLK when “H” and deactivates when “L”.  
When deactivate the clock,CKE low signifies the power down or  
self refresh mode.  
44  
CKE  
(Address)  
Row address (A0 to A11) and Calumn address (CA0 to CA8) are  
multiplexed on the same pin.  
28~32,35~41  
A0~A11  
CA10 defines auto precharge at Calumn address.  
(Bank Address)  
26, 27  
23  
BA0, BA1  
/RAS  
Selects which bank is to be active.  
(Row Address Strobe)  
Latches Row Addresses on the positive rising edge of the CLK with  
/RAS “L”. Enables row access & pre-charge.  
(Column Address Strobe)  
22  
/CAS  
Latches Column Addresses on the positive rising edge of the CLK  
with /CAS low. Enables column access.  
(Write Enable)  
21  
/WE  
Latches Column Addresses on the positive rising edge of the CLK  
with /CAS low. Enables column access.  
(Data Input/Output)  
16/51  
20/47  
LDQS/UDQS  
LDM/UDM  
Data Inputs and Outputs are synchronized with both edge of DQS.  
(Data Input/Output Mask)  
DM controls data inputs.LDM corresponds to the data on  
DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15.  
2, 4, 5, 7, 8, 10,  
11, 13, 54, 56, 57,  
59, 60, 62, 63, 65  
1,18,33/  
(Data Input/Output)  
DQ0~DQ15  
Data inputs and outputs are multiplexed on the same pin.  
(Power Supply/Ground)  
VDD/VSS  
VDDQ/VSSQ  
NC/RFU  
VREF  
34,48,66  
VDD and VSS are power supply pins for internal circuits.  
(Power Supply/Ground)  
3, 9, 15, 55.61/  
6, 12, 52, 58,64  
14,17,19,25,42,  
43,50,53  
VDDQ and VSSQ are power supply pins for the output buffers.  
(No Connection/Reserved for Future Use)  
This pin is recommended to be left No Connection on the device.  
(Input)  
49  
SSTL-2 Reference voltage for input buffer.  
Apr. 2007  
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EM428M1644RTA  
Absolute Maximum Rating  
Symbol  
VIN, VOUT  
VDD, VDDQ  
Item  
Rating  
Units  
V
Input, Output Voltage  
Power Supply Voltage  
-0.3 ~ +3.6  
-0.3 ~ +3.6  
V
Commercial  
Extended  
0 ~ +70  
-25 ~ +85  
TOP  
Operating Temperature Range  
°C  
TSTG  
PD  
Storage Temperature Range  
Power Dissipation  
-55 ~ +150  
°C  
W
1
IOS  
Short Circuit Current  
50  
mA  
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could  
cause permanent damage. The device is not meant to be operated under conditions outside the  
limits described in the operational section of this specification. Exposure to Absolute Maximum  
Rating conditions for extended periods may affect device reliability.  
Capacitance (VCC=2.5V, f=1MHz, TA=25°C)  
Symbol  
CCLK  
Parameter  
Min.  
2.5  
Typ.  
Max.  
4.0  
Units  
pF  
Clock Capacitance(CLK,/CLK)  
Input Capacitance for CKE, Address, /CS,  
/RAS, /CAS, /WE  
CI  
2.5  
4.0  
4.5  
6.5  
pF  
pF  
CO  
DM,Data&DQS Input/Output Capacitance  
Recommended DC Operating Conditions (TA=-0°C ~+70°C)  
Symbol  
Parameter  
Power Supply Voltage  
Min.  
Typ.  
Max.  
Units  
VDD  
VDDQ  
VREF  
2.3  
2.3  
2.5  
2.5  
2.7  
2.7  
V
V
V
Power Supply Voltage (for I/O Buffer)  
I/O Logic high Voltage  
1.15  
1.25  
1.35  
VTT  
VIH  
VIL  
I/O Termination Voltage  
Input Logic High Voltage  
Input Logic Low Voltage  
VREF-0.04  
VREF+0.18  
-0.3  
VREF+0.04  
VDDQ+0.3  
VREF-0.18  
V
V
V
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Recommended DC Operating Conditions  
(VDD=2.5V 0.2V, TA=0°C ~ 70°C)  
Symbol  
IDD1  
Parameter  
Test Conditions  
Max.  
120  
20  
Units  
mA  
Burst length=2,  
tRC≥tRC(min.), IOL=0mA,  
One bank active  
(Note 1)  
Operating Current  
Precharge Standby Current in  
Power Down Mode  
IDD2P  
IDD2N  
IDD3P  
IDD3N  
mA  
mA  
mA  
mA  
CKE≤VIL(max.), tCK=min  
CKE≥VIL(min.), tCK=min,  
/CS≥VIH(min.)  
Input signals are changed one time  
during 2 clks  
Precharge Standby Current in  
Non-power Down Mode  
45  
20  
Active Standby Current in  
Power Down Mode  
CKE≤VIL(max.), tCK=min  
CKE≥VIH(min.), tCK=min,  
/CS≥VIH(min.)  
Input signals are changed one time  
during 2 clks  
Active Standby Current in  
Non-power Down Mode  
75  
Operating Current (Burst  
(Note 2)  
Mode)  
tCK ≥ tCK(min.), IOL=0mA,  
All banks active  
IDD4  
IDD5  
IDD6  
200  
mA  
mA  
mA  
(Note 3)  
195  
Refresh Current  
tRC≥ tRFC (min.), All banks active  
(Note 4)  
Self Refresh Current  
CKE≤0.2V  
3
*All voltages referenced to VSS.  
Note 1: IDD1 depends on output loading and cycle rates.  
Specified values are obtained with the output open.  
Input signals are changed only one time during tCK (min.)  
Note 2: IDD4 depends on output loading and cycle rates.  
Specified values are obtained with the output open.  
Input signals are changed only one time during tCK (min.)  
Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics.  
Note 4: Standard power version.  
Recommended DC Operating Conditions (Continued)  
Symbol  
IIL  
Parameter  
Test Conditions  
Min.  
-5  
Max.  
+5  
Units  
uA  
0≤VI≤VDDQ, VDDQ=VDD  
All other pins not under test=0V  
Input Leakage Current  
IOL  
VOH  
VOL  
Output Leakage Current  
High Level Output Voltage  
Low Level Output Voltage  
-5  
+5  
uA  
V
0≤VO≤VDDQ, DOUT is disabled  
IO=-16.8mA  
VTT+0.76  
IO=+16.8mA  
VTT-0.76  
V
Apr. 2007  
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EM428M1644RTA  
Block Diagram  
Auto/Self  
Refresh Counter  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
DM  
Memory  
Array  
Write DQM  
Control  
Data In  
DOi  
S/ A &I/ O Gating  
Col. Decoder  
Data Out  
BA0  
BA1  
Col. Add. Buffer  
Mode Register Set  
Col Add. Counter  
Burst Counter  
Timing Register  
CLK  
CKE  
/CS  
/RAS  
/CAS  
/WE  
/CLK  
DM  
DQS  
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EM428M1644RTA  
AC Operating Test Conditions  
(VDD=2.5V 0.2V, TA=0°C ~70°C)  
Item  
Conditions  
1.25V/1.25V  
Output Reference Level  
Output Load  
See diagram as below  
VREF+0.31V/ VREF-0.31V  
1ns  
Input Signal Level  
Transition Time of Input Signals  
Input Reference Level  
VDDQ/2  
AC Operating Test Characteristics  
(VDD=2.5V 0.2V, TA=0°C ~70°C)  
-5  
-6  
-7.5  
Min. Max.  
Symbol  
Parameter  
Units  
Min.  
-0.65  
-0.55  
0.45  
-
Max.  
0.65  
0.55  
0.55  
-
Min.  
-0.7  
-0.6  
0.45  
7.5  
6
Max.  
0.7  
0.6  
0.55  
12  
tDQCK  
tDQSCK  
tCL,tCH  
DQ output access from CLK,/CLK  
DQS output access from CLK,/CLK  
CL low/high level width  
CL=2  
-0.75 0.75  
-0.75 0.75  
ns  
ns  
tCK  
ns  
ns  
ns  
ns  
0.45  
10  
0.55  
12  
12  
-
tCK  
Clock Cycle Time  
CL=2.5  
CL=3  
6
12  
12  
7.5  
-
5
8
-
-
tDH,tDS DQ and DM hold/setup time  
0.4  
0.45  
0.5  
DQ and DM input pulse width for  
each input  
Data out high/low impedance time  
from CLK,/CLK  
DQS-DQ skew for associated DQ  
signal  
Write command to first latching DQS  
transition  
tDIPW  
tHZ,tLZ  
tDQSQ  
tDQSS  
1.75  
-0.7  
1.75  
-0.7  
1.75  
ns  
ns  
ns  
tCK  
tCK  
tCK  
0.7  
0.7  
-0.75 0.75  
0.5  
0.4  
0.45  
0.75 1.25  
0.7  
1.25  
0.75  
1.25  
tDSL,tDS  
DQS input valid window  
0.35  
0.35  
0.35  
H
Mode Register Set command cycle  
time  
tMRD  
2
0
21  
0
2
0
tWPRES Write Preamble setup time  
ns  
tWPST  
tIH,tIS  
tRPRE  
Write Preamble  
0.4  
0.9  
0.6  
1.1  
0.4  
0.9  
0.6  
1.1  
0.4  
0.9  
0.6  
1.1  
tCK  
Address/control input hold/setup  
time  
0.7  
0.8  
1.0  
ns  
Read Preamble  
tCK  
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AC Operating Test Characteristics (Continued)  
(VDD=2.5V 0.2V, TA=0°C ~70°C)  
-5  
-6  
-75  
Symbol  
Parameter  
Read Postamble  
Units  
Min.  
0.4  
Max.  
0.6  
Min.  
0.4  
Max.  
0.6  
Min.  
0.4  
Max.  
0.6  
tRPST  
tRAS  
tCK  
ns  
Active to Precharge command  
period  
40  
70k  
42  
70k  
45  
70k  
tRC  
tRFC  
tRCD  
tRP  
Active to Active command period  
Auto Refresh Row Cycle Time  
Active to Read or Write delay  
Precharge command period  
55  
70  
15  
15  
60  
72  
18  
18  
65  
75  
20  
20  
ns  
ns  
ns  
ns  
tRRD  
tCCD  
Active bank A to B command period  
10  
1
12  
1
15  
1
ns  
Column address to column address  
delay  
tCK  
tCDLR  
tCDLW  
tDPL  
Last data in to Read command  
Last data in to Write command  
Last data in to Precharge command  
2.5 tCK- tDQSS  
2.5 tCK- tDQSS  
2.5 tCK- tDQSS  
tCK  
tCK  
tCK  
0
2
0
2
0
2
Exit self Refresh to non-read  
command  
tXSNR  
75  
75  
75  
ns  
tXSRD  
tREFI  
Exit self Refresh to read command  
Average periodic refresh interval  
200  
200  
200  
ns  
us  
15.6  
15.6  
15.6  
Apr. 2007  
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Simplified State Diagram  
Apr. 2007  
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EM428M1644RTA  
1. Command Truth Table  
CKE  
n-1  
BA0,  
BA1  
Command  
Symbol  
/CS /RAS /CAS /WE  
A10 A12~A0  
n
X
X
X
X
X
X
X
X
X
X
X
Ignore Command  
No Operation  
Burst Stop  
DESL  
NOP  
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
H
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
L
X
X
X
V
V
V
V
V
X
X
V
X
BSTH  
READ  
X
Read  
H
H
L
V
Read with Auto Pre-charge READA  
Write WRIT  
Write with Auto Pre-charge WRITA  
L
V
H
L
L
V
H
H
H
H
L
H
H
L
V
H
V
L
Bank Activate  
ACT  
PRE  
PALL  
MRS  
L
V
Pre-charge Select Bank  
Pre-charge All Banks  
Mode Register Set  
L
V
L
L
X
H
L
L
L
L
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input  
2. CKE Truth Table  
CKE  
Item  
Command  
Symbol  
/CS /RAS /CAS /WE Addr.  
n-1  
H
n
H
L
Idle  
Idle  
CBR Refresh Command  
Self Refresh Entry  
REF  
L
L
L
L
L
L
H
H
H
X
X
X
X
X
X
X
X
X
SELF  
H
L
H
H
L
L
H
X
X
X
H
X
X
X
Self Refresh  
Self Refresh Exit  
L
H
L
H
X
X
Idle  
Power Down Entry  
Power Down Exit  
Power Down  
H
Remark H = High level, L = Low level, X = High or Low level (Don't care)  
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3. Operative Command Table  
Current  
State  
/CS /R /C /W  
Addr.  
Command  
Action  
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
X
X
DESL  
NOP  
NOP  
NOP  
NOP  
TERM  
(Note 1)  
X
BA/CA/A10 READ/WRIT/BW  
ILLEGAL  
Idle  
L
L
L
L
L
L
H
H
L
H
L
BA/RA  
BA, A10  
X
ACT  
PRE/PREA  
REFA  
Bank active,Latch RA  
(Note 3)  
NOP  
(Note 4)  
H
Auto refresh  
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
Mode register  
H
L
X
H
X
H
X
H
X
X
DESL  
NOP  
NOP  
NOP  
Begin read,Latch CA,  
Determine auto-precharge  
L
L
H
H
H
L
L
L
BA/CA/A10  
BA/CA/A10  
READ/READA  
WRIT/WRITA  
Begin write,Latch CA,  
Determine auto-precharge  
(Note 1)  
Row  
Active  
L
L
L
L
L
L
H
H
L
H
L
BA/RA  
BA/A10  
X
ACT  
PRE/PREA  
REFA  
ILLEGAL  
Precharge/Precharge all  
ILLEGAL  
H
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL  
NOP  
NOP(Continue burst to end)  
NOP(Continue burst to end)  
Terminal burst  
TERM  
Terminate burst,Latch CA,  
Begin new read,  
L
H
L
H
H
BA/CA/A10  
READ/READA  
Read  
Determine Auto-precharge  
(Note 1)  
ILLEGAL  
L
L
H
BA/RA  
ACT  
L
L
L
L
H
L
L
BA, A10  
PRE/PREA  
REFA  
Terminate burst, PrecharE  
ILLEGAL  
H
X
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL  
NOP  
NOP(Continue burst to end)  
NOP(Continue burst to end)  
ILLEGAL  
TERM  
Terminate burst with DM=”H”,Latch  
L
L
H
H
L
L
H
L
BA/CA/A10  
BA/CA/A10  
READ/READA  
WRIT/WRITA  
CA,Begin read,Determine  
(Note 2)  
auto-precharge  
Terminate burst,Latch CA,Begin  
new write, Determine  
(Note 2)  
Write  
auto-precharge  
(Note 1)  
L
L
L
L
H
H
H
L
BA/RA  
ACT  
ILLEGAL  
Terminate burst with DM=”H”,  
BA, A10  
PRE/PREA  
Precharge  
ILLEGAL  
ILLEGAL  
L
L
L
L
L
L
H
L
X
REFA  
MRS  
Op-Code,  
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3. Operative Command Table (Continued)  
Current  
State  
/CS /R /C /W  
Addr.  
Command  
Action  
H
L
L
X
H
H
X
H
H
X
H
L
X
X
DESL  
NOP  
NOP(Continue burst to end)  
NOP(Continue burst to end)  
ILLEGAL  
BA/CA/A10  
TERM  
(Note 1)  
L
L
H
L
L
X
H
BA/RA  
BA/A10  
X
READ/WRITE  
ACT  
ILLEGAL  
Read with  
AP  
(Note 1)  
H
ILLEGAL  
(Note 1)  
L
L
L
L
H
L
L
PRE/PREA  
REFA  
ILLEGAL  
H
X
Op-Code,  
Mode-Add  
ILLEGAL  
L
L
L
L
MRS  
ILLEGAL  
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL  
NOP  
NOP(Continue burst to end)  
NOP(Continue burst to end)  
ILLEGAL  
TERM  
(Note 1)  
L
L
H
L
L
X
H
BA/CA/A10 READ/WRITE  
ILLEGAL  
(Note 1)  
Write with AP  
H
BA/RA  
ACT  
ILLEGAL  
(Note 1)  
L
L
L
L
H
L
L
BA/A10  
PRE/PREA  
REFA  
ILLEGAL  
H
X
Op-Code,  
Mode-Add  
ILLEGAL  
L
L
L
L
MRS  
ILLEGAL  
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL  
NOP  
NOP(idle after tRP  
NOP(idle after tRP  
NOP  
)
)
TERM  
(Note 1)  
L
L
H
L
L
X
H
BA/CA/A10 READ/WRITE  
ILLEGAL  
(Note 1)  
Pre-charging  
H
BA/RA  
ACT  
ILLEGAL  
(Note 3)  
L
L
L
L
H
L
L
BA/A10  
PRE/PREA  
REFA  
NOP(idle after tRP  
ILLEGAL  
)
H
X
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL  
NOP  
NOP(Row active after tRCD  
NOP(Row active after tRCD  
NOP  
)
)
TERM  
(Note 1)  
L
L
H
L
L
X
H
BA/CA/A10 READ/WRITE  
ILLEGAL  
Row  
Activating  
(Note 1)  
H
BA/RA  
ACT  
ILLEGAL  
(Note 1)  
L
L
L
L
H
L
L
BA/A10  
PRE/PREA  
REFA  
ILLEGAL  
H
X
ILLEGAL  
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge  
Apr. 2007  
www.eorex.com  
13/20  
eorex  
EM428M1644RTA  
3. Operative Command Table (Continued)  
Current State /CS /R /C /W  
Addr.  
Command  
Action  
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESL  
NOP  
NOP  
NOP  
NOP  
X
X
TERM  
READ  
(Note 1)  
H
BA/CA/A10  
ILLEGAL  
L
L
H
L
L
L
BA/CA/A10 WRIT/WRITA New write, Determine AP  
(Note 1)  
ILLEGAL  
Write  
Recovering  
H
H
BA/RA  
ACT  
(Note 1)  
L
L
L
L
H
L
L
BA/A10  
PRE/PREA  
REFA  
ILLEGAL  
ILLEGAL  
H
X
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESL  
NOP  
NOP(idle after tRP)  
NOP(idle after tRP)  
NOP  
TERM  
X
H
L
BA/CA/A10 READ/WRIT ILLEGAL  
Refreshing  
H
H
L
BA/RA  
BA/A10  
X
ACT  
PRE/PREA  
REFA  
ILLEGAL  
NOP(idle after tRP)  
ILLEGAL  
L
L
H
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge  
Note 1: ILLEGAL to bank in specified states;  
Function may be legal in the bank indicated by Bank Address (BA), depending on the state of  
that bank.  
Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements.  
Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA.  
Note 4: ILLEGAL of any bank is not idle.  
Apr. 2007  
www.eorex.com  
14/20  
eorex  
EM428M1644RTA  
4. Command Truth Table for CKE  
CKE  
n-1  
Current State  
/CS /R /C /W  
Addr.  
Action  
n
X
H
H
H
H
H
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID  
Exist Self-Refresh  
Exist Self-Refresh  
ILLEGAL  
Self Refresh  
L
L
X
X
X
X
X
H
L
ILLEGAL  
ILLEGAL  
L
X
X
X
X
H
H
L
X
X
H
L
X
X
X
H
H
H
L
NOP(Maintain self refresh)  
INVALID  
Exist Power down  
Exist Power down  
ILLEGAL  
X
H
H
H
H
H
L
Both bank  
precharge  
power down  
L
L
X
X
X
X
X
ILLEGAL  
ILLEGAL  
L
X
X
X
X
X
X
H
X
X
X
NOP(Maintain Power down)  
Refer to function true table  
H
L
(Note 3)  
Enter power down mode  
(Note 3)  
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
H
L
H
L
X
X
Enter power down mode  
ILLEGAL  
ILLEGAL  
X
H
H
L
X
All Banks  
Idle  
H
L
RA  
X
Row active/Bank active  
(Note 3)  
Enter self-refresh  
L
L
L
L
L
Op-Code Mode register access  
Op-Code Special mode register access  
H
L
L
L
L
L
X
H
X
X
X
X
X
X
Refer to current state  
Any State Other  
than Listed above  
H
X
X
X
X
Refer to command truth table  
Remark: H = High level, L = Low level, X = High or Low level (Don't care)  
Notes 1: After CKE’s low to high transition to exist self refresh mode.And a time of tRC(min) has to be  
Elapse after CKE’s low to high transition to issue a new command.  
Notes 2:CKE low to high transition is asynchronous as if restarts internal clock.  
Notes 3:Power down and self refresh can be entered only from the idle state of all banks.  
Apr. 2007  
www.eorex.com  
15/20  
eorex  
EM428M1644RTA  
Mode Register Definition  
Mode Register Set  
The mode register stores the data for controlling the various operating modes of DDR SDRAM which  
contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendor’s specific  
opinions. The defaults values of the register is not defined, so the mode register must be written after EMRS  
setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS,  
/WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into  
the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and  
BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation  
in the mode register. The mode register contents can be changed using the same command and clock cycle  
requirements during operating as long as all banks are in the idle state. The mode register is divided into  
various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS  
latency ( read latency from column address ) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset.  
A7 must be set to low for normal MRS operation.  
Apr. 2007  
www.eorex.com  
16/20  
eorex  
EM428M1644RTA  
Address input for Mode Register Set  
Apr. 2007  
www.eorex.com  
17/20  
eorex  
EM428M1644RTA  
Burst Type (A3)  
Burst Length  
2
A2  
X
X
X
X
X
X
0
A1  
X
X
0
A0  
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Sequential Addressing  
Interleave Addressing  
0 1  
0 1  
1 0  
1 0  
0 1 2 3  
0 1 2 3  
0
1 2 3 0  
1 0 3 2  
4
1
2 3 0 1  
2 3 0 1  
1
3 0 1 2  
3 2 1 0  
0
0 1 2 3 4 5 6 7  
1 2 3 4 5 6 7 0  
2 3 4 5 6 7 0 1  
3 4 5 6 7 0 1 2  
4 5 6 7 0 1 2 3  
5 6 7 0 1 2 3 4  
6 7 0 1 2 3 4 5  
7 0 1 2 3 4 5 6  
0 1 2 3 4 5 6 7  
1 0 3 2 5 4 7 6  
2 3 0 1 6 7 4 5  
3 2 1 0 7 6 5 4  
4 5 6 7 0 1 2 3  
5 4 7 6 1 0 3 2  
6 7 4 5 2 3 0 1  
7 6 5 4 3 2 1 0  
0
0
0
1
0
1
8
1
0
1
0
1
1
1
1
*Page length is a function of I/O organization and column addressing  
DLL Enable / Disable  
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and  
upon returning to normal operation after having disable the DLL for the purpose of debug or evaluation  
( upon existing Self Refresh Mode, the DLL is enable automatically. ) Any time the DLL is enabled, 200  
clock cycles must occur before a READ command can be issued.  
Output Drive Strength  
The normal drive strength got all outputs is specified to be SSTL-2, Class II. Some vendors might also  
support a weak drive strength option, intended for lighter load and/or point to point environments.  
Apr. 2007  
www.eorex.com  
18/20  
eorex  
EM428M1644RTA  
Extended Mode Register Set ( EMRS )  
The Extended mode register stores the data enabling or disabling DLL. The value of the extended mode  
register is not defined, so the extended mode register must be written after power up for enabling or  
disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on  
BA0 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended  
mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE  
going low is written in the extended mode register. The mode register contents can be changed using the  
same command and clock cycle requirements during operation as long as all banks are in the idle state. A0  
is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and  
BA0 must be set to low for proper EMRS operation.  
Apr. 2007  
www.eorex.com  
19/20  
eorex  
EM428M1644RTA  
Package Description  
Apr. 2007  
www.eorex.com  
20/20  

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