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EM6112K800TTA-55IF [EOREX]

512Kx8 LP SRAM; 512Kx8 LP SRAM
EM6112K800TTA-55IF
型号： EM6112K800TTA-55IF
厂家： EOREX CORPORATION    EOREX CORPORATION
描述：

512Kx8 LP SRAM
512Kx8 LP SRAM

静态存储器
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512Kx8 LP SRAM EM6112K800V Series  
GENERAL DESCRIPTION  
The EM6112K800V is a 4,194,304-bit low power CMOS static random access memory organized as  
524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology.  
Its standby current is stable within the range of operating temperature.  
The EM6112K800V is well designed for low power application, and particularly well suited for battery  
back-up nonvolatile memory application.  
The EM6112K800V operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are  
fully TTL compatible  
FEATURES  
z
z
Fast access time: 45/55/70ns  
Low power consumption:  
Operating current:  
z
z
z
z
Fully static operation  
Tri-state output  
Data retention voltage: 1.5V (MIN.)  
Package:  
40/30/20mA (TYP.)  
Standby current: -L/-LL version  
20/2µA (TYP.)  
Single 2.7V ~ 3.6V power supply  
All inputs and outputs TTL compatible  
32-pin 450 mil SOP  
32-pin 8mm x 20mm TSOP-I  
32-pin 8mm x 13.4mm STSOP  
36-ball 6mm x 8mm TFBGA  
z
z
FUNCTIONAL BLOCK DIAGRAM  
Vcc  
Vss  
512Kx8  
MEMORY  
ARRAY  
A0-A18  
DECODER  
I/O DATA  
CURCUIT  
COLUMN I/O  
DQ0-DQ7  
CE#  
WE#  
OE#  
CONTROL  
CIRCUIT  
PIN DESCRIPTION  
SYMBOL  
A0 - A18  
DQ0 – DQ7  
CE#  
DESCRIPTION  
Address Inputs  
Data Inputs/Outputs  
Enable Input  
WE#  
OE#  
Vcc  
Write Enable Input  
Output Enable Input  
Power Supply  
Vss  
Ground  
1
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
PIN CONFIGURATION  
SOP  
A18  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Vcc  
A15  
A17  
WE#  
A13  
A8  
A16  
A14  
A12  
A7  
2
3
4
5
A6  
6
A5  
7
A9  
A4  
8
A11  
OE#  
A10  
CE#  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
A3  
9
A2  
10  
11  
12  
13  
14  
15  
16  
A1  
A0  
DQ0  
DQ1  
DQ2  
Vss  
TSOP-I/STSOP  
A11  
A9  
A8  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
OE#  
A10  
CE#  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
Vss  
DQ2  
DQ1  
DQ0  
A0  
A13  
WE#  
A17  
A15  
Vcc  
A18  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A1  
A2  
A3  
2
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
TFBGA  
A
B
C
D
E
F
A0  
DQ4  
DQ5  
Vss  
Vcc  
DQ6  
DQ7  
A9  
A1  
A2  
NC  
WE#  
NC  
A3  
A4  
A5  
A6  
A7  
A8  
DQ0  
DQ1  
Vcc  
Vss  
DQ2  
DQ3  
A14  
6
A17  
CE#  
A11  
3
A18  
A16  
A12  
4
G
H
OE#  
A10  
2
A15  
A13  
5
1
3
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
RATING  
-0.5 to 4.6  
0 to 70(C grade)  
-20 to 80(E grade)  
-40 to 85(I grade)  
-65 to 150  
1
UNIT  
Terminal Voltage with Respect to Vss  
VTERM  
V
Operating Temperature  
TA  
°C  
Storage Temperature  
TSTG  
PD  
°C  
W
Power Dissipation  
DC Output Current  
IOUT  
50  
mA  
°C  
Soldering Temperature (under 10 sec)  
TSOLDER  
260  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a  
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections  
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device  
reliability.  
TRUTH TABLE  
MODE  
Standby  
CE#  
H
OE#  
X
WE#  
X
I/O OPERATION  
High-Z  
SUPPLY CURRENT  
ISB,ISB1  
Output Disable  
Read  
L
L
H
L
H
H
High-Z  
DOUT  
ICC,ICC1  
ICC,ICC1  
Write  
L
X
L
DIN  
ICC,ICC1  
Note: H = VIH, L = VIL, X = Don't care.  
DC ELECTRICAL CHARACTERISTICS  
PARAMETER  
SYMBOL TEST CONDITION  
MIN.  
TYP. *5 MAX.  
UNIT  
Supply Voltage  
Vcc  
2.7  
3.0  
3.6  
V
Input High Voltage  
VIH*1  
2.0  
-
Vcc+  
0.3  
V
Input Low Voltage  
VIL*2  
-0.2  
-1  
-
-
0.6  
V
Input Leakage  
Current  
ILI  
Vcc ≧ VIN ≧ Vss  
+1  
µA  
Output Leakage  
Current  
Output High  
Voltage  
Output Low  
Voltage  
Average Operating  
Power supply  
Current  
ILO  
VCC ≧ VOUT ≧ VSS,  
Output Disabled  
IOH = -1mA  
-1  
2.2  
-
-
2.7  
-
1
µA  
V
VOH  
VOL  
ICC  
-
IOL = 2mA  
0.4  
V
Cycle time = Min.  
CE# = VIL , II/O = 0mA  
-45  
-55  
-70  
-
-
-
-
40  
30  
20  
4
50  
40  
30  
5
mA  
mA  
mA  
mA  
ICC1  
Cycle time = 1µs  
CE#≦0.2V and II/O = 0mA  
other pins at 0.2V or VCC-0.2V  
Standby Power  
Supply Current  
ISB  
CE# = VIH  
-
-
0.3  
0.5  
mA  
ISB1  
CE# V ≧ VCC - 0.2V  
-L  
-LL  
20  
2
80  
15  
µA  
µA  
Notes:  
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.  
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.  
3. Over/Undershoot specifications are characterized, not 100% tested.  
4. 10µA for special request  
5. Typical values are included for reference only and are not guaranteed or tested.  
Typical valued are measured at VCC = VCC(TYP.) and TA = 25°C  
4
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
CAPACITANCE (TA = 25°C , f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
MIN.  
-
-
MAX.  
6
UNIT  
pF  
CIN  
CI/O  
8
pF  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA  
AC ELECTRICAL CHARACTERISTICS  
READ CYCLE  
PARAMETER  
SYM.  
-45  
-55  
70  
UNIT  
MIN. MAX. MIN. MAX. MIN. MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z tOHZ*  
Output Hold from Address Change tOH  
tRC  
tAA  
45  
-
-
-
10  
5
-
-
10  
-
55  
-
-
-
10  
5
-
-
10  
-
70  
-
-
-
10  
5
-
-
10  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
45  
45  
25  
-
55  
55  
30  
-
70  
70  
35  
-
tACE  
tOE  
tCLZ*  
tOLZ*  
tCHZ*  
-
-
-
15  
15  
-
20  
20  
-
25  
25  
-
WRITE CYCLE  
PARAMETER  
SYM.  
-45  
-55  
70  
UNIT  
MIN. MAX. MIN. MAX. MIN. MAX.  
Write Cycle Time  
tWC  
tAW  
tCW  
tAS  
tWP  
twr  
tDW  
tDH  
tOW*  
tWHZ*  
45  
40  
40  
0
35  
0
20  
0
5
-
-
-
-
-
-
-
-
-
55  
50  
50  
0
45  
0
25  
0
5
-
-
-
-
-
-
-
-
-
70  
60  
60  
0
55  
0
30  
0
5
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
-
15  
-
20  
-
25  
*These parameters are guaranteed by device characterization, but not production tested.  
5
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
tAA  
tOH  
Dout  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE#, CE2 and OE# controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
OE#  
tOH  
tOHZ  
tOE  
tOLZ  
tCHZ  
tCLZ  
Dout  
Valid Data  
High-Z  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low.  
3.Address must be valid prior to or coincident with CE# = low; otherwise tAA is the limiting parameter.  
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.  
6
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
CE#  
tAW  
tCW  
tWP  
tAS  
tWR  
tOW  
WE#  
tWHZ  
Dout  
(4)  
(4)  
tDW  
tDH  
High-Z  
Din  
Valid Data  
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
tAS  
tWR  
tCW  
tWP  
WE#  
Dout  
tWHZ  
High-Z  
tDW  
tDH  
High-Z  
Din  
Valid Data  
Notes :  
1. WE#, CE# must be high during all address transitions.  
2. A write occurs during the overlap of a low CE#, low WE#.  
3. During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and  
data to be placed on the bus.  
4. During this period, I/O pins are in the output state, and input signals must not be applied.  
5. If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.  
6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
7
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
VCC for Data  
SYMBOL  
VDR  
TEST CONDITION  
CE# V ≧ VCC - 0.2V  
MIN.  
1.5  
TYP. MAX. UNIT  
-
3.6  
V
Retention  
Data Retention  
Current  
IDR  
VCC = 1.5V  
CE# V ≧ VCC - 0.2V  
-L  
-
-
1
0.5  
0.5  
50  
8
12  
µA  
µA  
µA  
-LL  
-LLE  
-LLI  
Chip Disable to Data  
Retention Time  
Recovery Time  
tCDR  
tR  
See Data Retention  
Waveforms (below)  
0
-
-
-
-
ns  
ns  
tRC*  
tRC* = Read Cycle Time  
DATA RETENTION WAVEFORM  
VDR ≧ 1.5V  
Vcc(min.)  
Vcc(min.)  
tR  
Vcc  
tCDR  
CE# ≧ Vcc-0.2V  
VIH  
VIH  
CE#  
8
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
PACKAGE OUTLINE DIMENSION  
32 pin 450 mil SOP Package Outline Dimension  
32 pin 8mm x 20mm TSOP-I Package Outline Dimension  
9
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
32 pin 8mm x 13.4mm STSOP Package Outline Dimension  
10  
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
36-ball 6mm × 8mm TFBGA Package Outline Dimension  
11  
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
Product ID Information  
EM  
61  
12K  
8
0
0
V
B
A – 45  
IF*  
Version  
SRAM  
Family  
Option  
Speed:  
45ns  
61: Standard  
Configuration: Option  
55ns  
70ns  
8: x8  
16: x16  
Voltage:  
V: 3V  
W: 2.7V  
~5.5V  
T: 5V  
Address Density  
12K: 512K  
TEMP:  
Blank: Normal  
I: Industrial  
EOREX  
Manufactured  
Memory  
Package:  
S: STSOP  
P: PDIP  
Pb-Free PKG:  
Blank: Normal  
F: Pb-free  
F: SOP  
B: TFBGA  
T: TSOP  
I: TSOP-I  
* Product ID example  
12  
DCC-SR-041005-A  
512Kx8 LP SRAM EM6112K800V Series  
©COPYRIGHT 2004 EOREX CORPORATION  
Printed in Canada  
The information in this document is subject to change without notice.  
EOREX makes no commitment to update or keep current the information contained in this document. No part of this document  
may be copied or reproduced in any form or by any means without the prior written consent of EOREX.  
EOREX subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high  
quality products suitable for usual commercial applications.  
EOREX CORPORATION  
http://www.eorex.com  
sales@eorex.com  
2F., No. 301-3, Guang-Ming 6th Rd., Chu-Pei City, Hsinchu County, Taiwan 302, ROC  
TEL: +886-3-5585138  
FAX: +886-3-5585139  
13  
DCC-SR-041005-A  

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