S1L58152 [EPSON]
HIGH DENSITY GATE ARRAY; 高密度门阵列
| 型号： | S1L58152 |
| 厂家： | 
EPSON COMPANY |
| 描述： | HIGH DENSITY GATE ARRAY |
| 文件： | 总12页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
ASIC
S1L50000
S1L50000 SERIES HIGH DENSITY GATE ARRAY
DESCRIPTION
EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS
gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V
tolerant I/O buffers.
•
•
•
Ultra-high-speed, high density and low power consumption
Low voltage operation: 3.3V and 2.0V
Number of raw gates: 28,710 ~ 815,468 gates
FEATURES
•
•
•
Process
0.35µm 2/3/4 layer metalization CMOS process
Integration
A maximum of 815,468 gates (2 input NAND gate equivalent)
Operating Speed
Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ)
(2-input pair NAND, F/O = 2, Typical wire load)
Input buffer: 380 ps (5.0V Typ) Built-in level shifter is used.
400 ps (3.3V Typ), 1.30 ns (2.0V Typ)
(F/O = 2, Typical wire load)
Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used.
2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ)
(CL = 15 pF)
•
•
I/F Levels
Input/Output TTL/CMOS/LVTTL compatible
Input Modes
TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI
Built-in pull-up and pull-down resistors can be usable.
(2 types for each resistor value)
•
•
Output Modes
Output Drive
Normal, 3-state, bi-directional, PCI
IOL = 0.1, 1, 3, 8, 12, 24 mA selectable
(Built-in level shifter is used at 5.0V)
IOL = 0.1, 1, 2, 6, 12 mA selectable (at 3.3V)
I
OL = 0.05, 0.3, 0.6, 2, 4 mA selectable (at 2.0V)
•
•
RAM
Asynchronous 1-port, asynchronous 2-port
Dual Power
Operation supported by using level-shifter circuit
Internal logic: Operation supported by low voltage
I/O Buffer:
Built-in interfaces of both high and low voltages possible
•
Operation possible at VDD = 2.0 ± 0.2V
EPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
1
DATA SHEET
ASIC
S1L50000
LINE UP
The S1L50000 Series comprises 11 types of masters, from which the customer is able to select
the master most suitable.
Total
BC
Number
of
Number
of
Number
of
Cell Utilization Ratio (U)*1
2-layer 3-layer 4-layer
Master
(Raw Gates)
Pads
88
Columns (X) Rows (Y)
metal
50%
47%
47%
45%
45%
45%
43%
40%
40%
40%
40%
metal
88%
85%
85%
80%
75%
75%
75%
70%
70%
70%
70%
metal
95%
95%
95%
95%
95%
95%
95%
90%
90%
90%
90%
S1L50282/283/284
S1L50752/753/754
S1L50992/993/994
S1L51252/253/254
S1L51772/773/774
S1L52502/503/504
S1L53352/353/354
S1L54422/423/424
S1L55062/063/064
S1L56682/683/684
S1L58152/153/154
28710
75774
99198
319
519
90
144
168
188
224
264
308
352
376
432
480
146
167
188
223
265
307
352
377
433
478
594
669
125772
177062
250160
335858
442112
506688
668552
815468
794
944
1094
1256
1344
1544
1706
NOTE: *1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of
the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only
as an estimate
2
EPSON ELECTRONICS AMERICA, INC.
150 River Oaks Pkwy
San Jose, CA 95134
Tel: (408) 922-0200
Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
ELECTRICAL CHARACTERISTICS AND SPECIFICATIONS
Absolute Maximum Ratings (For Single Power Supply):
(Vss = 0V)
Item
Power Supply Voltage
Input Voltage
Output Voltage
Output Current/Pin
Storage Temperature
Symbol
Limits
Unit
VDD
VI
VO
-0.3 to 4.0
V
V
V
mA
-0.3 to VDD + 0.5*1
-0.3 to VDD + 0.5*1
± 30
IOUT
TSTG
-65 to 150
°C
*1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH
systems.
Absolute Maximum Ratings (For Dual Power Supplies):
(Vss = 0V)
Item
Symbol
Limits
Unit
Power Supply Voltage
HVDD
-0.3 to 7.0
V
V
V
V
V
V
LVDD
HVI
-0.3 to 4.0
Input Voltage
-0.3 to HVDD + 0.5*1
-0.3 to LVDD + 0.5*1
-0.3 to HVDD + 0.5*1
-0.3 to LVDD + 0.5*1
LVI
Output Voltage
HVO
LVO
± 30 (± 50 *2)
Output Current/Pin
IOUT
mA
Storage Temperature
TSTG
-65 to 150
°C
**1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH
systems.
*2: Possible to use for 24mA of output buffer.
EPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
3
DATA SHEET
ASIC
S1L50000
Recommended Operating Conditions (For Single Power Supplies):
Item
Power Supply Voltage
Input Voltage
Symbol
Min
3.00
VSS
Typ
3.30
Max
Unit
VDD
VI
Ta
3.60
V
V
°C
*1
--
VDD
70*2
85*3
50
50
5
Ambient Temperature
0
25
25
--
--
--
-40
--
Normal Input for Rising Edge Input
Normal Input for Falling Edge Input
Schmitt Input for Rising Edge Input
Schmitt Input for Falling Edge Input
tri
tfi
tri
tfi
ns
ns
ms
ms
--
--
--
--
5
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the IDC and IDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
Recommended Operating Conditions (For Single Power Supplies):
Item
Power Supply Voltage
Input Voltage
Symbol
Min
1.80
VSS
0
-40
Typ
2.00
Max
Unit
VDD
VI
Ta
2.20
V
V
°C
*1
--
VDD
70*2
85*3
100
100
10
Ambient Temperature
25
25
--
--
--
Normal Input for Rising Edge Input
Normal Input for Falling Edge Input
Schmitt Input for Rising Edge Input
Schmitt Input for Falling Edge Input
tri
tfi
tri
tfi
--
--
--
--
ns
ns
ms
ms
--
10
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the IDC and IDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
4
EPSON ELECTRONICS AMERICA, INC.
150 River Oaks Pkwy
San Jose, CA 95134
Tel: (408) 922-0200
Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
Recommended Operating Conditions (For Dual Power Supplies):
Item
Symbol
Min
Typ
Max
Unit
Power Supply Voltage (High Voltage)
HVDD
4.75
5.00
5.25
V
4.50
5.00
3.30
--
5.50
3.60
HVDD
LVDD
70*2
85*3
50
Power Supply Voltage (Low Voltage)
Input Voltage
LVDD
HVI
LVI
Ta
3.00
VSS
VSS
0
-40
--
V
V
*1
--
Ambient Temperature
25
25
--
°C
Normal Input for Rising Edge Input
Normal Input for Falling Edge Input
Schmitt Input for Rising Edge Input
Schmitt Input for Falling Edge Input
tri
tri
tri
tri
ns
ns
ms
ms
--
--
--
--
--
--
50
5
5
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the LIDC and LIDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
Recommended Operating Conditions (For Dual Power Supplies):
Item
Symbol
Min
Typ
Max
Unit
Power Supply Voltage (High Voltage)
Power Supply Voltage (Low Voltage)
Input Voltage
HVDD
3.00
3.30
2.00
--
3.60
V
V
V
LVDD
HVI
LVI
Ta
1.80
VSS
VSS
0
-40
--
--
--
--
--
2.20
HVDD
LVDD
70*1
85*2
50
100
50
100
5
--
Ambient Temperature
25
25
--
--
--
--
--
--
--
°C
ns
Normal Input for Rising Edge Input
Normal Input for Falling Edge Input
Schmitt Input for Rising Edge Input
Schmitt Input for Falling Edge Input
Htri
Ltri
Htfi
Ltfi
Htri
Ltri
Htfi
Ltfi
ns
ms
ms
--
--
--
10
5
10
--
*1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the LIDC and LIDH systems or HIDC and
HIDH systems.
*2: The ambient temperature range is recommended for Tj = 0 to 80°C
*3: The ambient temperature range is recommended for Tj = -40 to 125°C
EPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
5
DATA SHEET
ASIC
S1L50000
Electrical Characteristics of the S1L50000 Series:
(VDD = 5.0V, VSS = 0V, Ta = -40 to 85°C)
Item
Symbol
Conditions
Min Typ Max Unit
Input Leakage Current
Off State Leakage Current
High Level Output Voltage
ILI
--
--
-1
--
--
--
1
1
--
µA
µA
V
IOZ
VOH
-1
IOH = -0.1mA (Type S), -1mA (Type M), HVDD
-3mA (Type 1), -8mA (Type 2), -12mA
(Type 3, Type 4)
-0.4
VDD = Min
Low Level Output Voltage
VOL
IOL = 0.1mA (Type S), 1mA (Type M),
3mA (Type 1), 8mA (Type 2), 12mA
(Type 3), 24mA (Type 4)
VDD = Min
--
--
0.4
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
VIH1
VIL1
VT1+
VT1-
VH1
VIH2
VIL2
VT2+
VT2-
VH2
CMOS Level, HVDD = Max
CMOS Level, HVDD = Min
CMOS Schmitt
CMOS Schmitt
CMOS Schmitt
TTL Level, HVDD = Max
TTL Level, HVDD = Min
TTL Schmitt
TTL Schmitt
TTL Schmitt
3.5
--
--
--
--
--
--
--
--
--
--
--
--
--
--
V
V
V
V
V
V
V
V
V
V
V
V
1.0
4.0
3.1
--
2.0
0.8
0.3
2.0
--
1.2
0.6
0.1
2.0
--
--
0.8
2.4
1.8
--
--
0.8
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
VIH3
VIL3
IOH3
PCI Level, HVDD = Max
PCI Level, HVDD = Min
PCI Response,
VOH = 1.4V, HVDD = Min
VOH = 3.1V, HVDD = Max
PCI Response
VOH = 2.20V, HVDD = Min
VOL = 0.71V, HVDD = Max
-44
--
--
--
--
-142
mA
mA
Low Level Output Current
Pull-up Resistance*
IOL3
95
--
30
--
--
60
--
mA
mA
206
(120)
144
(240)
288
(120)
144
(240)
288
-80
RPU
VI = 0V
Type 1
Type 2
Type 1
Type 2
KΩ
60
30
60
--
120
60
120
--
Pull-down Resistance*
RPD
VI = VDD
KΩ
High Level Maintenance Current
Low Level Maintenance Current
High Level Reversal Current
Low Level Reversal Current
IBHH
Bus Hold Response, VIN = 2.0V
(TTL) HVDD = Min
Bus Hold Response, VIN = 0.8V
(TTL) HVDD = Min
Bus Hold Response, VIN = 0.8V
(TTL) HVDD = Max
Bus Hold Response, VIN = 2.0V
µA
µA
µA
µA
IBHL
--
--
33
--
IBHHO
IBHLO
-550
330
--
--
--
(TTL)
HVDD = Max
Input Terminal Capacitance
Output Terminal Capacitance
Input/Output Terminal
Capacitance
CI
CO
CIO
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
--
--
--
--
--
--
10
10
10
pF
pF
pF
*
The values in parentheses are for the case of Ta = 0 to 70°C.
6
EPSON ELECTRONICS AMERICA, INC.
150 River Oaks Pkwy
San Jose, CA 95134
Tel: (408) 922-0200
Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
Electrical Characteristics of the S1L50000 Series:
(VDD = 3.3V ± 0.3V, VSS = 0V, Ta = -40 to 85°C)
Item
Symbol
IDDS
ILI
IOZ
VOH
Conditions
Quiescent Conditions
Min Typ Max Unit
Quiescent Current*
--
--
--
--
--
170
µA
µA
µA
V
Input Leakage Current
Off State Leakage Current
High Level Output Voltage
--
--
-1
-1
1
1
IOH = -0.1mA (Type S), -1mA (Type VDD
M), -2mA (Type 1), -6mA (Type 2), -0.4
-12mA (Type 3, Type 4)
--
VDD = Min
Low Level Output Voltage
VOL
IOL = 0.1mA (Type S), 1mA (Type
M), 2mA (Type 1), 6mA (Type 2),
12mA (Type 3), 24mA (Type 4)
--
--
0.4
V
VDD = Min
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
VIH1
VIL1
VT1+
VT1-
VH1
VIH3
VIL3
IOH3
LVTTL Level, VDD = Max
LVTTL Level, VDD = Min
LVTTL Schmitt
LVTTL Schmitt
LVTTL Schmitt
PCI Level, VDD = Max
PCI Level, VDD = Min
PCI Response,
2.0
--
1.1
0.6
0.1
--
--
--
--
--
--
V
V
V
V
V
V
V
0.8
2.4
1.8
--
--
0.98
1.71 --
--
--
V
V
OH = 0.90V, VDD = Min
OH = 2.52V, VDD = Max
-36
--
--
--
--
-115
mA
mA
Low Level Output Current
Pull-up Resistance**
IOL3
PCI Response
V
V
OH = 1.80V, VDD = Min
OL = 2.52V, VDD = Max
48
--
20
--
--
50
--
mA
mA
137
(100)
120
(200)
240
(100)
120
(200)
240
-20
RPU
VI = 0V
Type 1
Type 2
Type 1
Type 2
KΩ
40
20
40
--
100
50
100
--
Pull-down Resistance**
RPD
VI = VDD
KΩ
High Level Maintenance
Current
Low Level Maintenance
Current
IBHH
Bus Hold Response,
IN = 2.0V, VDD = Min
Bus Hold Response,
IN = 0.8V, VDD = Min
Bus Hold Response,
IN = 0.8V, VDD = Max
Bus Hold Response,
IN = 2.0V, VDD = Max
µA
µA
µA
µA
V
IBHL
--
--
17
--
V
High Level Reversal Current
IBHHO
IBHLO
-350 --
210 --
V
Low Level Reversal Current
--
V
Input Terminal Capacitance
Output Terminal Capacitance
Input/Output Terminal
Capacitance
CI
CO
CIO
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
--
--
--
--
--
--
10
10
10
pF
pF
pF
*
The quiescent current is a typical value (Tj=85°C) for each master.
** The values in parentheses are for the case of Ta = 0 to 70°C.
EPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
7
DATA SHEET
ASIC
S1L50000
Electrical Characteristics of the S1L50000 Series:
(VDD = 2.0V ± 0.2V, VSS = 0V, Ta = -40 to 85°C)
Item
Symbol
IDDS
ILI
IOZ
VOH
Conditions
Quiescent Conditions
Min Typ Max Unit
Quiescent Current*
--
--
--
--
--
150
µA
µA
µA
V
Input Leakage Current
Off State Leakage Current
High Level Output Voltage
--
--
-1
1
-1
1
IOH = -0.05mA (Type S), -0.3mA
(Type M), -0.6mA (Type 1), -2mA
(Type 2), -4mA (Type 3, Type 4)
VDD
-0.2
--
VDD = Min
Low Level Output Voltage
VOL
IOL = 0.05mA (Type S), 0.3mA
(Type M), 0.6mA (Type 1), 2mA
(Type 2), 4mA (Type 3), 8mA
(Type 4)
--
--
0.2
V
VDD = Min
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
Hysteresis Voltage
VIH1
VIL1
VT1+
VT1-
VH1
CMOS Level, VDD = Max
CMOS Level, VDD = Min
CMOS Schmitt
CMOS Schmitt
CMOS Schmitt
1.6
--
0.4
0.3
0
--
--
--
--
--
V
V
V
V
V
0.3
1.6
1.4
--
--
Pull-up Resistance
RPU
VI = 0V
Type 1
30
60
30
60
--
120
240
120
240
--
300
Type 2
Type 1
Type 2
600
300
600
KΩ
Pull-down Resistance
RPD
VI = VDD
KΩ
µA
High Level Maintenance
Current
Low Level Maintenance
Current
IBHH
IBHL
IBHHO
IBHLO
Bus Hold Response,
IN = 1.6V, VDD = Min
Bus Hold Response,
IN = 0.3V, VDD = Min
-2
V
--
--
2
µA
µA
µA
V
High Level Reversal Current
Bus Hold Response,
VIN = 0.3V, VDD = Max
Bus Hold Response,
VIN = 1.6V, VDD = Max
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
f = 1Mhz, VDD = 0V
-100 --
100 --
--
--
Low Level Reversal Current
Input Terminal Capacitance
Output Terminal Capacitance
Input/Output Terminal
Capacitance
CI
CO
CIO
--
--
--
--
--
--
10
10
10
pF
pF
pF
*
The quiescent current is a typical value (Tj=85°C) for each master.
8
EPSON ELECTRONICS AMERICA, INC.
150 River Oaks Pkwy
San Jose, CA 95134
Tel: (408) 922-0200
Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
GATE ARRAY DEVELOPMENT FLOW
CUSTOMER
EEA
Product Plan
Functional Spec.
Logical Check
(Simulation)
G/A Development
Request
Schematic Pin
Assignment
NG
Verification
OK
*
Circuit Design
Test Pattern Design
• Test pattern (timing chart)
• Timing wave form
• Marking diagram
• P/O
1
Logical Check
(Simulation)
Timing Check
(Simulation)
2
Delay Analyzing
G/A Development
Refer to Note
NG
NG
EWS
OK
Verification
Verification
OK
*
• Schematic
• Pin assignment
Simulation
File
• Timing wave form
• Marking diagram
• P/O
Place & Route
Delay Analyzing
Post Simulation
Simulation List
NG
Verification
OK
Make Masks
Customer Spec.
(Sign Off)
TS (Test Sample)
Fabrication
NG
Check
OK
ES (Engr. Sample)
Fabrication
NG
OK
ES(TS) Proto.
Approval
MP Setup
ET(TS) Approve
the Prototype
Delivery Spec.
Publication
Delivery Spec.
Approve Delivery
Spec.
Delivery Spec.
Approval
* Jobs are done by customer and EEA engineer. Steps in shadowed boxes are based on customer’s requirement.
NOTE:
When the customer performs all tasks to the point of logical simulations and delay simulations on engineering workstations, etc.,
the route taken is (2, Joint Design). When EEA performs the logical simulations, the route taken is (1, Turnkey Design).
EPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
9
DATA SHEET
ASIC
S1L50000
EEA CUSTOMER ENGINEERING
To help customers implement their design of EEA ASIC’s, we offer training at our design centers
and at customer sites when required.
When a design is started, an EEA engineer is assigned to the project and will remain with the
project through its completion. EEA engineers will work with the customer on design, software and
other technical issues. When the design files are transferred to EEA, the assigned engineer will
verify the design’s integrity and prepare it for place and route. The EEA Customer Engineering
Group provides all technical customer-support services including:
•
•
•
•
•
•
•
Pre-Sale Technical Support
Customer Training
Design Assistance
Custom Cell Development
Place and Route
Scan Insertion and ATPG
Netlist Conversion and Synthesis
•
•
•
•
•
•
•
Software Documentation
Simulation Support
Turnkey Design
Design Verification
Static Timing Analysis
JTAG Insertion
Test Vector Conversion
EDA/CAE SUPPORT
•
Schematic Capture
Viewlogic (Synopsys): Viewdraw
EEA: Auklet (ECS)
•
Synthesis
Synopsys: DesignCompiler
Exemplar Logic: Leonardo
•
•
Simulation
Cadence: Verilog-XL
Synopsys: VSS (VHDL)
Avant!: Polaris (Purespeed)
Viewlogic (Synopsys): Viewsim
Modeltech: V-System (VHDL)
DFT
Synopsys: TestCompiler+
Viewlogic (Synopsys): TestGen (Sunrise)
•
•
Place & Route
Cadence: GateEnsemble
Avant!: Aquarius-GA (Apollo)
Delay Calculation (Post-Route)
EEA: Peacock (EXDT)
10
EPSON ELECTRONICS AMERICA, INC.
150 River Oaks Pkwy
San Jose, CA 95134
Tel: (408) 922-0200
Fax: (408) 922-0238
DATA SHEET
ASIC
S1L50000
EDA/CAE SUPPORT (continued)
•
Static Timing
Synopsys: PrimeTime (DesignTime)
Viewlogic (Synopsys): Motive
•
Layout Verification
Cadence: Dracula/LVS
EPSON ELECTRONICS AMERICA, INC. 150 River Oaks Pkwy San Jose, CA 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
11
DATA SHEET
ASIC
S1L50000
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of EPSON
ELECTRONICS AMERICA, INC.. EEA reserves the right to make changes to this material without notice. EEA does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there
is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license
to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in
accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions there of may
contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of
Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government
agency.
EPSON implies SEIKO EPSON CORPORATION and EPSON affiliated company.
EPSON ELECTRONICS AMERICA, INC. 1999 All Rights Reserved, Rev. 2.3
Trademark & Company Name
XNF is registered trademark of Synopsys Inc. All other product names mentioned herein are trademarks and/or registered trademarks of their
respective owners.
For additional information about EEA ASIC products and services, or to discuss a solution tailored to your specific requirements, call your local
EEA sales office or contact the factory.
Northwest Regional
Sales Office & Design Center Sales Office & Design Center Sales Office
Northeast Regional
Southeast Regional
Central Regional
Sales Office
http://www.eea.epson.com
12
EPSON ELECTRONICS AMERICA, INC.
150 River Oaks Pkwy
San Jose, CA 95134
Tel: (408) 922-0200
Fax: (408) 922-0238
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