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F50L1G41LB [ESMT]

3.3V 1 Gbit SPI-NAND Flash Memory;
F50L1G41LB
型号： F50L1G41LB
厂家： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.    ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
描述：

3.3V 1 Gbit SPI-NAND Flash Memory
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ESMT  
F50L1G41LB (2M)  
3.3V 1 Gbit  
SPI-NAND Flash Memory  
Flash  
PRODUCT LIST  
Parameters  
Values  
3.3V  
VCC  
Width  
x1, x21, x4  
104MHz  
1-bit  
Frequency  
Internal ECC Correction  
Transfer Rate  
9.6ns  
Loading Throughput  
Power-up Ready Time  
Max Reset Busy Time  
Note: 1. x2 PROGRAM operation is not defined.  
104MT/s  
1ms (maximum value)  
1ms (maximum value)  
FEATURES  
Voltage Supply: 3.3V (2.7V~3.6V)  
Organization  
- Memory Cell Array: (128M + 4M) x 8bit  
- Data Register: (2K + 64) x 8bit  
Automatic Program and Erase  
- Page Program: (2K + 64) Byte  
- Block Erase: (128K + 4K) Byte  
Page Read Operation  
- Page Size: (2K + 64) Byte  
- Read from Cell to Register with Internal ECC: 100us  
Hardware Data Protection  
- Program/Erase Lockout During Power Transitions  
Reliable CMOS Floating Gate Technology  
- Internal ECC Requirement: 1bit/512Byte  
- Endurance: 100K Program/Erase cycles  
- Data Retention: 10 years  
Command Register Operation  
NOP: 4 cycles  
OTP Operation  
Bad-Block-Protect  
Boot Read  
Memory Cell: 1bit/Memory Cell  
Support SPI-Mode 0 and SPI-Mode 31  
Fast Write Cycle Time  
- Program time:400us  
- Block Erase time: 4ms  
Note: 1. Mode 0: CPOL = 0, CPHA = 0; Mode 3: CPOL = 1, CPHA = 1  
ORDERING INFORMATION  
Product ID  
Speed  
104MHz  
104MHz  
Package  
Comments  
F50L1G41LB-104YG2M  
F50L1G41LB-104YG2ME  
8-contact WSON  
8-contact WSON (without expose metal pad)  
8x6mm  
8x6mm  
Pb-free  
Pb-free  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 1/49  
ESMT  
F50L1G41LB (2M)  
GENERAL DESCRIPTION  
The serial electrical interface follows the industry-standard serial  
peripheral interface (SPI), providing a cost-effective non-volatile  
memory storage solution in systems where pin count must be  
kept to a minimum. The device is a 1Gb SLC SPI-NAND Flash  
memory device based on the standard parallel NAND Flash, but  
new command protocols and registers are defined for SPI  
operation. It is also an alternative to SPI-NOR, offering superior  
write performance and cost per bit over SPI-NOR.  
The memory is divided into blocks that can be erased  
independently so it is possible to preserve valid data while old  
data is erased. The device contains 1024 blocks, composed by  
64 pages consisting in two NAND structures of 32 series  
connected Flash cells. Each page consists 2112-Byte and is  
further divided into a 2048-Byte data storage area with a  
separate 64-Byte spare area. The 64-Byte area is typically used  
for memory and error management.  
The command set resembles common SPI-NOR command set,  
modified to handle NAND-specific functions and new features.  
New features include user-selectable internal ECC. With internal  
ECC enabled, ECC code is generated internally when a page is  
written to the memory array. The ECC code is stored in the  
spare area of each page. When a page is read to the cache  
register, the ECC code is calculated again and compared with  
the stored value. Errors are corrected if necessary. The device  
either outputs corrected data or returns an ECC error status.  
The pins serve as the ports for signals. The device has six signal  
lines plus VCC and ground (GND, VSS). The signal lines are SCK  
(serial clock), SI (command and data input), SO (response and  
data output), and control signals CS#, HOLD#, WP#.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2  
2/49  
ESMT  
F50L1G41LB (2M)  
PIN CONFIGURATION (TOP VIEW)  
8-Contact WSON  
(WSON 8C, 8mmx6 mm Body, 1.27mm Contact Pitch)  
1
2
3
4
8
7
6
5
VCC  
CS#  
SO (IO1)  
WP# (IO2)  
VSS  
HOLD# (IO3)  
SCK  
SI (IO0)  
Pin Description  
Pin Name  
Functions  
Chip Select (Input)  
The device is activated(1)/deactivated(2) as CS# is driven LOW/HIGH.  
After power-on, the device requires a falling-edge on CS# before any command can be written. The device  
goes to standby mode when no PROGRAM, ERASE, or WRITE STATUS REGISTER operation is in  
progress.  
CS#  
Hold (Input) / IO3 (Input/Output)  
Hold pauses any serial communication with the device without deselecting it (3). When driven LOW, SO is at  
high impedance (Hi-Z), and all inputs in SI and SCK are ignored; CS# also should be driven LOW.  
HOLD# / IO3  
HOLD# must not be driven during x4 operation; it means HOLD function is only available for standard and  
x2 SPI.  
Write Protect (Input) / IO2 (Input/Output)  
WP# is driven LOW to prevent writing the Feature Registers. The WP-E bit in Protection Register controls  
the function of WP#, and the other bits in Register can protect a specific portion by hardware. When  
WP-E=1, the device is in the Hardware-protection mode that WP# functions as a dedicated active low input  
pin for the Write Protect of the device. If WP-E=1 and WP# goes LOW, the device will become READ-only.  
When WP-E=0, the device is in the Software-protection mode that only Protection Register can be  
protected. WP# functions as a data I/O pin.  
WP# / IO2  
WP# must not be driven during x4 operation; it means Write Protect function is only available for standard  
and x2 SPI.  
Serial Clock (Input)  
SCK provides serial interface timing.  
Address, commands, and data in SI are latched on the rising edge of SCK.  
SCK  
Output (data in SO) is triggered after the falling-edge of SCK.  
The clock is valid only when the device is active.(4)  
Serial Data Input (Input) / IO0 (Input/Output)  
SI transfers data serially into the device. Device latches addresses, commands, and program data in SI on  
the rising-edge of SCK.  
SI / IO0  
SI must not be driven during x2 or x4 READ operation.  
Serial Data Output (Output) / IO1 (Input/Output)  
SO transfers data serially out of the device on the falling-edge of SCK.  
SO / IO1  
SO must not be driven during x2 or x4 PROGRAM operation.  
Power VCC is the power supply for device.  
Ground  
(5)  
VCC  
(5)  
VSS  
No Connection Not internally connected.  
NC  
Note:  
1. CS# places the device in active power mode.  
2. CS# deselects the device and places SO at high impedance.  
3. It means HOLD# input doesn’t terminate any READ, PROGRAM, or ERASE operation currently in progress.  
4. SI and SO can be triggered only when the clock is valid.  
5. Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 3/49  
ESMT  
F50L1G41LB (2M)  
BLOCK DIAGRAM  
ARRAY ORGANIZATION  
Array Address  
Data Bits  
1st byte  
2nd byte  
3rd byte  
4th byte  
5th byte  
0
1
2
3
4
A4  
X
5
A5  
X
6
A6  
X
7
Address  
Column Address  
Column Address  
Row Address  
A0  
A8  
A12  
A20  
X
A1  
A9  
A13  
A21  
X
A2  
A3  
A7  
X
A10  
A14  
A22  
X
A11  
A15  
A23  
X
A16  
A24  
X
A17  
A25  
X
A18  
A26  
X
A19  
A27  
X
Row Address  
Dummy Address  
Note:  
Column Address: Starting Address of the Register.  
X = don’t care.  
The device ignores any additional input of address cycles than required.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 4/49  
ESMT  
F50L1G41LB (2M)  
COMMAND SET  
Function  
Op Code  
D8h  
Address Byte  
Dummy Byte  
Data Bytes  
BLOCK ERASE  
(1)  
GET FEATURE  
3
1
0
0
0
1
0Fh  
SET FEATURE  
WRITE DISABLE  
WRITE ENABLE  
PROGRAM LOAD  
1Fh  
04h  
06h  
02h  
1
0
0
2
0
0
0
0
1
0
0
1 to 2112  
(2)  
32h  
2
0
1 to 2112  
PROGRAM LOAD x4  
PROGRAM LOAD RANDOM  
DATA  
84h  
2
0
1 to 2112  
PROGRAM LOAD RANDOM  
(2)  
34h  
2
0
1 to 2112  
DATA x4  
PROGRAM EXECUTE  
PAGE READ  
10h  
13h  
3
3
2
0
0
1
0
0
READ FROM CACHE  
03h, 0Bh  
1 to 2112  
READ FROM CACHE with  
4Byte Address  
0Ch  
3Bh  
3Ch  
2
2
2
3
1
3
1 to 2112  
1 to 2112  
1 to 2112  
READ FROM CACHE x2  
READ FROM CACHE x2 with  
4Byte Address  
(2)  
6Bh  
6Ch  
2
2
1
3
1 to 2112  
1 to 2112  
READ FROM CACHE x4  
READ FROM CACHE x4 with  
(2)  
4Byte Address  
FAST READ X2 IO  
BBh  
BCh  
EBh  
ECh  
2
2
2
2
1
3
2
5
1 to 2112  
1 to 2112  
1 to 2112  
1 to 2112  
FAST READ X2 IO with 4Byte  
Address  
FAST READ X4 IO  
FAST READ X4 IO with 4Byte  
Address  
(3)  
9Fh  
FFh  
1
0
0
0
2
0
READ ID  
RESET  
Note:  
1. Refer to Feature Register.  
2. Command/Address is 1-bit input per clock period, data is 4-bit input/output per clock period.  
3. Address is 00h to get JEDEC ID  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 5/49  
ESMT  
F50L1G41LB (2M)  
Absolute Maximum Ratings  
Parameter  
Symbol  
VCC  
Rating  
-0.6 to +4.6  
Unit  
Voltage on any pin relative to VSS  
VIN  
-0.6 to +4.6  
V
VI/O  
-0.6 to VCC + 0.3 (< 4.6)  
-40 to +125  
Temperature Under Bias  
Storage Temperature  
Short Circuit Current  
Note:  
TBIAS  
TSTG  
℃
℃
-65 to +150  
IOS  
5
mA  
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to  
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended  
periods may affect reliability.  
Recommended Operating Conditions  
(Voltage reference to GND, TA = 0 to 70℃)  
Parameter  
Supply Voltage  
Symbol  
VCC  
Min.  
2.7  
0
Typ.  
3.3  
0
Max.  
3.6  
0
Unit  
V
Supply Voltage  
VSS  
V
DC and Operation Conditions  
(Recommended operating conditions otherwise noted)  
Parameter  
Page Read with  
Symbol  
Test Conditions  
Min.  
Typ.2  
Max.  
Unit  
fC=104MHz, CS#=VIL,  
IOUT=0mA  
ICC1  
-
16  
Serial Access  
Program  
Erase  
Operating  
Current  
20  
mA  
ICC2  
ICC3  
ISB1  
-
-
-
-
16  
16  
CS#=VIH,  
Stand-by Current (TTL)  
-
-
1
mA  
WP#=0V/VCC  
CS#= VCC -0.2,  
WP#=0V/ VCC  
Stand-by Current (CMOS)  
ISB2  
-
-
10  
-
50  
uA  
uA  
±10  
±10  
Input Leakage Current  
Output Leakage Current  
Input High Voltage  
ILI  
VIN=0 to VCC (max)  
ILO  
VOUT=0 to VCC (max)  
-
-
-
-
-
-
uA  
V
1
VIH  
-
0.7 x VCC  
-0.3  
VCC +0.3  
0.2 x VCC  
-
1
Input Low Voltage, All inputs  
Output High Voltage Level  
Output Low Voltage Level  
VIL  
-
V
VOH  
VOL  
IOH=-20uA  
IOL=1mA  
0.7 x VCC  
-
V
0.15 x VCC  
V
Note:  
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less.  
2. Typical value are measured at VCC =3.3V, TA=25℃. Not 100% tested.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 6/49  
ESMT  
F50L1G41LB (2M)  
Valid Block and Error Management  
Description  
Minimum / Maximum number of valid block number of block  
Bad block mark  
Requirement  
1004 / 1024  
Non FFh  
Mark location  
Column 2048 of page 0 and page 1  
Note:  
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The  
number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain  
one or more bad bits which cause status failure during program and erase operation. Do not erase or program factory-marked bad  
blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.  
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment and is guaranteed to  
be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 7/49  
ESMT  
F50L1G41LB (2M)  
AC Test Condition  
(TA=0 to 70℃, VCC=2.7V~3.6V)  
Parameter  
Input Pulse Levels  
Condition  
0.2VCC to 0.8VCC  
Max: 2.4ns  
Input Rise and Fall Times  
Input and Output Timing Levels  
Output Load  
VCC /2  
1 TTL Gate and CL=15pF  
Capacitance  
(TA=25℃, VCC=3.3V, f=1.0MHz)  
Item  
Input / Output Capacitance  
Input Capacitance  
Symbol  
Test Condition  
VIL = 0V  
Min.  
Max.  
Unit  
pF  
CI/O  
CIN  
-
-
8
8
VIN = 0V  
pF  
Note: Capacitance is periodically sampled and not 100% tested.  
Read / Program / Erase Timing Characteristics  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Unit  
Average Program Time  
tPROG  
-
400  
900  
us  
Number of Partial Program Cycles in the  
Same Page  
NOP  
tBERS  
tRD  
-
-
-
-
4
-
4
Cycle  
ms  
Block Erase Time  
10  
Data Transfer from Cell to Register with  
Internal ECC  
100  
us  
General Timing Characteristic  
Parameter  
Clock frequency  
Symbol  
fC  
tCD  
Min.  
Max.  
104MHz  
Hold# non-active hold time relative to SCK  
Hold# hold time relative to SCK  
Command deselect time  
CS# Setup Time  
4.5ns  
4.5ns  
80ns  
5ns  
tCH  
tCS  
tCSS  
tCSH  
tCSCL  
tDIS  
tHC  
CS# Hold Time  
5ns  
The last valid Clock low to CS# high  
Output disable time  
5ns  
20ns  
Hold# non-active setup time relative to SCK  
Hold# setup time relative to SCK  
Data input setup time  
4.5ns  
4.5ns  
2ns  
tHD  
tSUDAT  
tHDDAT  
tHO  
Data input hold time  
3ns  
Output hold time  
1.5ns  
Hold# to output Hi-Z  
tHZ  
7ns  
7ns  
8ns  
Hold# to output Low-Z  
Clock low to output valid  
Clock high time  
tLZ  
tV  
tWH  
tWL  
4.5ns  
4.5ns  
Clock low time  
Clock rise time (slew rate)  
Clock fall time (slew rate)  
WP# setup time  
tCRT  
tCFT  
tWPS  
tWPH  
tRST  
0.1V/ns  
0.1V/ns  
20ns  
WP# hold time  
100ns  
Resetting time during Idle/Read/Program/Erase  
5/5/10/500us  
Note: For first RESET condition after power up, tRST will be 1ms MAX.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2  
8/49  
ESMT  
F50L1G41LB (2M)  
Technical Notes  
Bus Operation  
SPI NAND supports two SPI modes:  
(Mode 0) CPOL (clock polarity) = 0, CPHA (clock phase) = 0  
(Mode 3) CPOL=1, CPHA=1  
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes.  
When CS# is high, keep SCK at VCC (Mode 0) or VSS (Mode 3). Do not begin toggling SCK until after CS# is driven LOW.  
SPI Modes Timing  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 9/49  
ESMT  
F50L1G41LB (2M)  
Feature Operations  
The GET FEATURE (0Fh) and SET FEATURE (1Fh) commands are used to alter the device behavior from the default power-on  
behavior. These commands use a 1-Byte feature address to determine which feature is to be read or modified.  
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise specified in  
Feature Setting Table, once the device is set, it remains set, even if a RESET (FFh) command is issued.  
Feature Settings Table  
Data Bits  
Register  
Acronym Address  
7
6
5
4
3
2
1
0
Protection  
Register  
PR  
CR  
A0h  
B0h  
C0h  
D0h  
PRP0  
BP3  
BP2  
BP1  
BP0  
T/BP  
WPE  
PRP1  
Configuration  
Register  
Reserved  
P_Fail  
Reserved  
E_Fail  
Reserved  
WEL  
Reserved  
OIP  
OTP-P  
Reserved  
Reserved  
OTP-E  
PR-L  
ECC-E  
Status  
Register  
Reserved  
SR  
ECC_S1 ECC_S0  
Output Driver  
Register  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
ODR  
DRV_S1 DRV_S0  
GET FEATURE (0Fh) Timing  
SET FEATURE (1Fh) Timing  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 10/49  
ESMT  
F50L1G41LB (2M)  
Protection Register  
Protection Register Setting Table  
Data Bits  
A0h  
Bit  
7
6
5
4
3
2
1
0
Protection  
Register  
Protect 0  
Protection  
Register  
Protect 1  
Block Protect Block Protect Block Protect Block Protect Top / Bottom  
Definition  
WP# Enable  
3
2
1
0
Protect  
Shipment  
default  
0
1
1
1
1
1
0
0
Note:  
1. All bits in A0h are volatile writable.  
2. Once BP[3:0], T/B-P, and WPE bits are set correctly, PRP0 and PRP1 should both be set to “1” as well to allow PR-L bit being  
set to “1” to lock the protection in the PR (Protection Register) until next Power cycle.  
Related Protection Bits of Protection Register Table  
Software Protection (Controller, X4 Program/ Read is enable)  
PRP0  
(7)  
WPE  
(1)  
PRP1  
(0)  
WP#  
IO2  
Description  
0
1
1
0
0
0
0
0
0
0
0
1
X
0
1
X
No WP# functionality, and WP# pin will always function as IO2  
PR cannot be changed, and WP# pin will function as IO2 for X4 operation  
PR can be changed, and WP# pin will function as IO2 for X4 operation  
Power Lock Down PR, and WP# pin will always function as IO2  
Set PR-L=1 is allowed, and PR is locked until next Power cycle, and WP# pin will always  
function as IO2  
1
0
1
X
Hardware Protection (System Circuit/ PCB layout, X4 Program/ Read is disable)  
PRP0  
(7)  
WPE  
(1)  
PRP1  
(0)  
WP#  
IO2  
Description  
X
0
1
1
1
1
0
VCC  
VCC  
VCC  
PR can be changed  
Power Lock Down(1) PR  
1
1
Set PR-L=1 is allowed, and PR is locked until next Power cycle  
All Write operations are blocked, and entire device (Register, Array, and OTP area) is  
Read-only  
X
1
X
GND  
Note:  
1. PR means Protection Register.  
2. When PRP1 = “1” and PRP0 = “0”, a cycle of power-down to power-up will change the state to PRP1 = “0” and PRP0 = “0”  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 11/49  
ESMT  
F50L1G41LB (2M)  
Block Protect Bits of Protection Register Table  
BP3 (6)  
BP2 (5)  
BP1 (4)  
BP0 (3)  
T/BP (2)  
Protected Rows  
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
X
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
X
X
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
X
X
None; all unlocked  
Upper 1/512 locked (BLK1022 & 1023)  
Upper 1/256 locked  
Upper 1/128 locked  
Upper 1/64 locked  
Upper 1/32 locked  
Upper 1/16 locked  
Upper 1/8 locked  
Upper 1/4 locked  
Upper 1/2 locked  
Lower 1/512 locked (BLK0 & 1)  
Lower 1/256 locked  
Lower 1/128 locked  
Lower 1/64 locked  
Lower 1/32 locked  
Lower 1/16 locked  
Lower 1/8 locked  
Lower 1/4 locked  
Lower 1/2 locked  
All locked  
All locked  
Note:  
1. X = don’t care  
2. Any Erase or Program command for the protected area will be ignored.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 12/49  
ESMT  
F50L1G41LB (2M)  
Configuration Register  
Configuration Register Setting Table  
Data Bits  
B0h  
Bit  
7
6
5
4
3
2
1
0
OTP Pages OTP Pages  
Protect  
Protection  
Register Lock  
ECC  
Definition  
Reserved  
Reserved  
Reserved  
Reserved  
Enable(1)  
Enable(2)  
Shipment  
default  
0
0
0
1
0
0
0
0
Note:  
1. To Program/ Read OTP area, and Read Unique ID and Parameter Page, OTP-E must be set to “1”.  
2. 1-bit internal ECC for all READ and PROGRAM operations can be enabled (ECC enable = 1) or disabled (ECC enable = 0).  
3. Once BP[3:0], T/B-P, and WP-E bits are set correctly, PRP0 and PRP1 should both be set to “1” as well to allow PR-L bit being  
set to “1” to lock the protection in the PR (Protection Register) until next Power cycle.  
4. Bit6 and bit4 are volatile writable.  
OTP State Bits of Configuration Register Table  
OTP Protect Bit (7)  
OTP Enable Bit (6)  
State  
0
0
1
1
0
1
0
1
Normal operation (read array)  
Access OTP space  
Not applicable  
Lock the OTP area  
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ESMT  
F50L1G41LB (2M)  
Status Register  
Software can read status register during the NAND device operation by issuing GET FEATURE (0Fh) command, followed by the  
feature address C0h. The status register will output the status of the operation, refer to Status Register Setting Table, Bits of Status  
Register Table and ECC Status Bits of Status Register Table.  
Status Register Setting Table  
C0h  
Bit  
Data Bits  
7
6
5
4
3
2
1
0
Write Enable Operation In  
Definition  
Reserved  
Reserved ECC_Status1 ECC_Status0 Program_Fail Erase_Fail  
Latch  
Progress  
Shipment  
default  
0
0
0
0
0
0
0
0
Bits of Status Register Table  
Description  
Bit Name  
Mode  
P_Fail is set to 1 as a program failure has occurred. P_Fail = 1 will also be set if  
the user attempts to program an invalid address or a locked region.  
P_Fail is set to 0 during the PROGRAM EXECUTE command sequence or the  
RESET command.  
Program fail (Bit 3)  
Erase fail (Bit 2)  
R
E_Fail is set to 1 as an erase failure has occurred. E_Fail = 1 will also be set if  
the user attempts to erase a locked region, or if ERASE operation fails.  
E_Fail is set to 0 at the start of the BLOCK ERASE command sequence or the  
RESET command.  
R
WEL must be set to 1 to indicate the current status of the write enable latch,  
prior to issuing PROGRAM EXECUTE or BLOCK ERASE command. It is set  
by issuing WRITE ENABLE command.  
Write enable latch (Bit 1)  
Operation in progress (Bit 0)  
W
R
WEL is disabled (WEL=0) by issuing the WRITE DISABLE command.  
OIP is set to 1 when the device is busy; it means a PROGRAM EXECUTE,  
PAGE READ, BLOCK ERASE, or RESET command is executing.  
OIP is cleared to 0 as the interface is in ready state.  
ECC Status Bits of Status Register Table shows the ECCS definitions.  
ECC_S is set to 00h either following a RESET, or at the beginning of the  
READ. It is then updated after the device completes a valid READ operation.  
ECC_S is invalid if ECC is disabled (via a SET FEATURE command to Bit 4 in  
OTP register).  
ECC_status1 (Bit 5)  
ECC_status0 (Bit 4)  
R
After power-up RESET, ECC_S is set to reflect the contents of block 0, page 0.  
ECC Status Bits of Status Register Table  
ECCS0 (4) Description  
ECCS1 (5)  
0
0
1
1
0
1
0
1
No errors  
1-bit error detected and corrected  
2-bit or more than 2-bit errors detected and not corrected  
Reserved  
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ESMT  
F50L1G41LB (2M)  
Output Driver Register  
Output Driver Register Setting Table  
Data Bits  
D0h  
Bit  
7
6
5
4
3
2
1
0
Definition  
Reserved Driver_Strength1 Deiver_Strength0 Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Shipment  
default  
0
0
1
0
0
0
0
0
Driver Strength Bits of Output Driver Register Table  
DRV_S1 (6)  
DRV_S0 (5)  
Driver Strength  
0
0
1
1
0
1
0
1
100 %  
75 %  
50 %  
25%  
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ESMT  
F50L1G41LB (2M)  
Array Write Enable / Disable  
The WRITE ENABLE (06h) command sets the WEL bit (in status register) to 1. This is required in the following WRITE operations that  
change the contents of the memory array: PAGE PROGRAM, BLOCK ERASE, and OTP PROGRAM.  
Contrarily, the WRITE DISABLE (04h) command sets the WEL bit to 0. This disables PAGE PROGRAM, BLOCK ERASE, and OTP  
PROGRAM.  
WRITE ENABLE (06h) Timing  
WRITE DISABLE (04h) Timing  
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ESMT  
F50L1G41LB (2M)  
Error Management  
Mask Out Initial Invalid Blocks  
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by ESMT. The  
information regarding the initial invalid blocks is called the initial invalid block information. Devices with initial invalid blocks have the  
same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block does not affect  
the performance of valid blocks because it is isolated from the bit line and the common source line by a select transistor. The system  
design must be able to mask out the initial invalid blocks via address mapping.  
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte  
ECC.  
Identifying Initial invalid Blocks  
All device locations are erased (FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial  
invalid block(s) status is defined by the 1st byte in the spare area. ESMT makes sure that either the 1st or 2nd page of every initial  
invalid block has non-FFh data at the 1st byte column address in the spare area.  
Do not erase or program factory-marked bad blocks. The host controller must be able to recognize the initial invalid block information  
and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop  
with Flash memory usage.  
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ESMT  
F50L1G41LB (2M)  
Algorithm for Bad Block Scanning  
Check “FFh” at the 1st Byte column  
address in the spare area of the 1st and  
2nd page in the block.  
For (i=0; i<Num_of_LUs; i++)  
{
For (j=0; j<Blocks_Per_LU; j++)  
{
Defect_Block_Found=False;  
Read_Page(lu=i, block=j, page=0);  
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;  
Read_Page(lu=i, block=j, page=1);  
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;  
If (Defect_Block_Found)  
Mark_Block_as_Defective(lu=i, block=j);  
}
}
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ESMT  
F50L1G41LB (2M)  
Block Replacement  
Within its lifetime, number of invalid blocks may increase with NAND Flash memory. Refer to the qualification report for the actual data.  
The following possible failure modes should be considered to implement a highly reliable system. In the case of failure after ERASE or  
PROGRAM in status register, block replacement should be done. Because PROGRAM status fail during a page program does not  
affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased  
empty block and reprogramming the current target data and copying the rest of the replaced block.  
In case of READ, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification  
failure due to single bit error be reclaimed by ECC without any block replacement. The additional block failure rate does not include  
those reclaimed blocks.  
Block A  
1st  
~
(n-1) th  
n th  
An error occurs.  
page  
1
Block B  
Buffer memory of the  
controller  
1st  
~
2
(n-1) th  
n th  
An error occurs.  
* Step 1  
When an error happens in the nth page of the Block 'A' during erase or program  
operation.  
* Step 2  
page  
Copy the data in the 1st ~ (n-1)th page to the same location of another free  
block. (Block 'B')  
* Step 3  
Then, copy the nth page data of the Block 'A' in the buffer memory to the nth  
page of the Block 'B'  
* Step 4  
Do not erase or program to Block 'A' by creating an 'invalid block' table or  
other appropriate scheme.  
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F50L1G41LB (2M)  
ECC Protection  
ECC is enabled after device power-up, so the default PROGRAM and READ commands operate with internal ECC in the active state.  
During a PROGRAM operation, the device calculates an ECC code on the 2KB page in the cache register, before the page is written to  
the NAND Flash array. The ECC code is stored in the spare area of the page in array.  
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated and compared  
with the ECC code value read from the array. If a single-bit data error is discovered, the error is corrected in the cache register and only  
the corrected data is on the output bus.  
ECC Protection Table  
Max Byte Address  
1FFh (511)  
3FFh (1023)  
5FFh (1535)  
7FFh (2047)  
801h (2049)  
803h (2051)  
807h (2055)  
80Dh (2061)  
80Fh (2063)  
811h  
Min Byte Address  
000h (0)  
ECC Protected  
Yes  
Yes  
Yes  
Yes  
No  
Area  
Description  
User data 01  
User data 11  
User data 21  
User data 31  
Main 0  
Main 1  
Main 2  
Main 3  
200h (512)  
400h (1024)  
600h (1536)  
800h (2048)  
802h (2050)  
804h (2052)  
808h (2056)  
80Eh (2062)  
Reserved (Bad Block Marker)  
User Data II  
No  
Spare 0  
Spare 0  
Yes  
Yes  
No  
User Data I  
ECC for Main 0  
ECC for Spare 0  
Reserved  
No  
810h  
812h  
814h  
818h  
81Eh  
820h  
822h  
824h  
828h  
82Eh  
830h  
832h  
834h  
838h  
83Eh  
No  
Spare 1  
Spare 1  
User Data II  
813h  
Yes  
Yes  
No  
User Data I  
817h  
ECC for Main 1  
ECC for Spare 1  
Reserved  
81Dh  
81Fh  
No  
821h  
No  
Spare 2  
Spare 2  
User Data II  
823h  
Yes  
Yes  
No  
User Data I  
827h  
ECC for Main 2  
ECC for Spare 2  
Reserved  
82Dh  
82Fh  
No  
831h  
No  
Spare 3  
Spare 3  
User Data II  
833h  
Yes  
Yes  
No  
User Data I  
837h  
ECC for Main 3  
ECC for Spare 3  
83Dh  
83Fh  
Note:  
1. The user areas must be programmed within a single partial-page programming operation so the NAND Flash device can calculate  
the proper ECC bytes.  
2. When internal ECC is enabled, these areas are prohibited to be programming.  
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ESMT  
F50L1G41LB (2M)  
Addressing for Program Operation  
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most  
significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB  
among the pages to be programmed. Therefore, LSB page doesn’t need to be page 0.  
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ESMT  
F50L1G41LB (2M)  
Operations and Timing Diagrams  
Read Operations and Serial Output  
The command sequence is follows:  
13h (PAGE READ to cache)  
0Fh (GET FEATURE command to read the status)  
0Bh or 03h (READ FROM CACHE x1); 0Ch (x1) / 3Bh (x2); 3Ch (x2) / 6Bh (x4); 6Ch (x4)  
BBh (x2) TBD; BCh (x2) / EBh (x4) TBD; ECh (x4)  
PAGE READ command requires 24-bit address with 8 dummy and a 16-bit row address. After row address is registered, the device  
starts the transfer from the main array to the cache register, and is busy for tR time. During this time, GET FEATURE command can be  
issued to monitor the status of the operation. Following a status of successful completion, READ FROM CACHE command must be  
issued to read the data out of the cache.  
READ FROM CACHE command requires 16-bit address with 4 dummy bits and a 12-bit column address for the starting byte. The  
starting byte can be 0 to 2011, but after the end of the cache register is reached, the data does not wrap around and SO goes to a Hi-Z  
state.  
BBh and BCh command allow for improved random access while maintaining two IO pins: SI and SO. It is similar to 3Bh command but  
with the capability to input Column Address or dummy clocks two bits per clock.  
The data output sequence will start from the location specified by the Column Address input and continue to the end of the Page. Once  
the last byte of data is output, both SI (SO0) and SO (SO1) will become Hi-Z.  
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F50L1G41LB (2M)  
PAGE READ (13h) Timing  
Serial Output Timing  
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READ FROM CACHE (03h or 0Bh) Timing  
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READ FROM CACHE with 4-Byte Address (0Ch) Timing  
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READ FROM CACHE x2 (3Bh) Timing  
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READ FROM CACHE x2 with 4-Byte Address (3Ch) Timing  
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READ FROM CACHE x4 (6Bh) Timing  
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READ FROM CACHE x4 with 4-Byte Address (6Ch) Timing  
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F50L1G41LB (2M)  
Fast Read X2 IO (BBh) Timing  
Fast Read X2 IO with 4Byte Address (BCh) Timing  
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F50L1G41LB (2M)  
Fast Read X4IO (EBh) Timing  
Fast Read X4IO with 4Byte Address (ECh) Timing  
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ESMT  
F50L1G41LB (2M)  
Program Operations and Serial Input  
Page Program  
The command sequence is follows:  
06h (WRITE ENABLE)  
02h (PROGRAM LOAD x1) / 32h (x4)  
10h (PROGRAM EXECUTE)  
0Fh (GET FEATURE command to read the status)  
The page program operation sequence programs 1 byte to 2112 bytes of data within a page. If WRITE ENABLE command is not  
issued (WEL bit is not set), then the rest of the program sequence is ignored. PROGRAM LOAD command requires 16-bit address with  
4 dummy and a 12-bit column address, then the data bytes to be loaded into cache register. Only four partial page programs are  
allowed on a single page. If more than 2112 bytes are loaded, then those additional bytes are ignored by the cache register.  
After the data is loaded, PROGRAM EXECUTE command must be issued to transfer the data from cache register to main array, and is  
busy for tPROG time. PROGRAM EXECUTE command requires 24-bit address with 8 dummy bits and a 16-bit row address.  
PROGRAM LOAD (02h) Timing  
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PROGRAM LOAD x4 (32h) Timing  
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PROGRAM EXECUTE (10h) Timing  
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Random Data Program  
The command sequence is follows:  
06h (WRITE ENABLE)  
84h (PROGRAM LOAD RANDOM DATA x1) / 34h (x4)  
10h (PROGRAM EXECUTE)  
0Fh (GET FEATURE command to read the status)  
The random data program operation sequence programs or replaces data in a page with existing data. PROGRAM LOAD RANDOM  
DATA command requires 16-bit address with 4 dummy bits and a 12-bit column address. New data is loaded in the column address  
provided. If the random data is not sequential, then another PROGRAM LOAD RANDOM DATA command must be issued with a new  
column address. After the data is loaded, PROGRAM EXECUTE command can be issued to start the programming operation.  
PROGRAM LOAD RANDOM DATA (84h) Timing  
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PROGRAM LOAD RANDOM DATA x4 (34h) Timing  
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F50L1G41LB (2M)  
Serial Input and tCSCL Timing  
Internal Data Move  
The command sequence is follows:  
13h (PAGE READ to cache)  
06h (WRITE ENABLE)  
84h (PROGRAM LOAD RANDOM DATA x1) / 34h (x4); this is OPTIONAL in sequence.  
10h (PROGRAM EXECUTE)  
0Fh (GET FEATURE command to read the status)  
The INTERNAL DATA MOVE operation sequence programs or replaces data in a page with existing data. Prior to performing an  
INTERNAL DATA MOVE operation, the target page content must be read into the cache register. PAGE READ command must be  
followed with a WRITE ENABLE command to change the contents of memory array.  
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ESMT  
F50L1G41LB (2M)  
Erase Operation  
The command sequence is follows:  
06h (WRITE ENABLE)  
D8h (BLOCK ERASE)  
0Fh (GET FEATURE command to read the status)  
BLOCK ERASE command requires 24-bit address with 8 dummy bits and a 16-bit row address. If WRITE ENABLE command is not  
issued (WEL bit is not set), then the rest of the erase sequence is ignored. After the row address is registered, the control logic  
automatically controls the timing and the erase-verify operations, and the device is busy for tBERS time. BLOCK ERASE command  
operates on one block at a time.  
BLOCK ERASE (D8h) Timing  
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F50L1G41LB (2M)  
Read ID  
The device contains a product identification mode, initiated by writing 9Fh to the command register, followed by an address input of  
00h. Five read cycles sequentially output the manufacturer code (C8h), and the device code and 3rd, 4th, 5 th cycle ID respectively. The  
command register remains in Read ID mode until further commands are issued to it.  
READ ID Timing  
ID Definition Table  
2nd Cycle  
(Device  
Code)  
1st Cycle  
(Maker Code)  
Product ID  
3rd Cycle  
4th Cycle  
5th Cycle  
F50L1G41LB(2M)  
C8h  
01h  
7Fh  
7Fh  
7Fh  
Description  
1st Byte  
Maker Code  
Device Code  
2nd Byte  
3rd Byte  
4th Byte  
5th Byte  
JEDEC Maker Code Continuation Code, 7Fh  
JEDEC Maker Code Continuation Code, 7Fh  
JEDEC Maker Code Continuation Code, 7Fh  
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ESMT  
F50L1G41LB (2M)  
WP# Timing  
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F50L1G41LB (2M)  
HOLD# Timing  
HOLD# input provides a method to pause serial communication with the device but doesn’t terminate any READ, PROGRAM, or  
ERASE operation currently in progress.  
Hold mode starts at the falling edge of HOLD# provided SCK is also Low. If SCK is High when HOLD# goes Low, hold mode begins  
after the next falling edge of SCK. Similarly, hold mode is exited at the rising edge of HOLD# provided SCK is also Low. If SCK is High,  
hold mode ends after the next falling edge of SCK.  
During hold mode, SO is Hi-Z, and SI and SCK inputs are ignored.  
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ESMT  
F50L1G41LB (2M)  
Power-Up  
During power transitions, VCC is internally monitored. 250us after VCC has reached 2.5V, WP# is taken High, the device automatically  
performs the RESET command. The first access to the SPI NAND device can occur 1ms after WP# goes High, and then CS# can be  
driven Low, SCK can start, and the required command can be issued to the device.  
Power-Up and RESET Timing  
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ESMT  
F50L1G41LB (2M)  
Read Unique ID Page / Read Parameter Page / OTP Operations  
In addition to the main memory array, F50L1G41LB (2M) is also equipped with one Unique ID Page, and twenty-eight  
One-Time-Programmable Pages. The Unique ID Page contains 16 identical copies of the 32-Byte data. The Parameter Page contains  
3 identical copies of the 256-Byte data. Both pages are Read only.  
This flash device also offers one-time programmable memory area. 28 full pages of OTP data are available on the device, and the  
entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands. Regarding OTP Read, Read  
Unique ID Page, and Read Parameter Page, please refer to the specific Page addresses defined in OTP Area Details Table.  
The OTP area leaves the factory in an unwritten state. The OTP area cannot be erased, whether it is protected or not. Protecting the  
OTP area prevents further programming of that area. It means the OTP area becomes read-only after being locked.  
The OTP area is only accessible while the OTP enable bit is set to 1. To set the device to OTP operation mode, issue the Set Feature  
(1Fh) command. When the device is in OTP operation mode, subsequent Read and/or Page Program (both X1 and X4) are applied to  
the OTP area. Please refer to relative command sequences defined in datasheet. When you want to come back to normal operation,  
you need to set OTP enable bit to 0. Otherwise, device will stay in OTP mode.  
OTP/ Read / Read Unique ID / Read Parameter Page:  
Issue the Set Feature (1Fh) command.  
Issue the feature address (B0h).  
Set the OTP enable bit to 1.  
Issue the Page Read (13h) command with a specific Page address.  
OTP Program:  
Issue the Set Feature (1Fh) command.  
Issue the feature address (A0h).  
Set Protection bit to 0.  
Issue the feature address (B0h).  
Set the OTP enable bit to 1.  
Issue the Write Enable (06h) command.  
Issue the Program Load (02h) and Program Execute (10h) commands.  
OTP Lock:  
Issue the Set Feature (1Fh) command.  
Issue the feature address (A0h).  
Set Protection bit to 0.  
Issue the feature address (B0h).  
Set both the OTP enable and OTP protect bits to 1.  
Issue the Write Enable (06h) command.  
Issue the Program Execute (10h) command.  
OTP Modes and Commands Table  
Set Feature  
Read  
1Fh - B0h(1) - 40h or 50h(2)  
1Fh - B0h - 40h or 50h  
1Fh - B0h - C0h or D0h  
1Fh - B0h - 00h or 10h  
OTP Operation mode  
Page Program  
Program Protect  
Leave OTP mode  
OTP Protection mode  
OTP Release mode  
NOTE:  
1. B0h is Configuration Register address.  
2. 50h, D0h, and 10h are Configuration Register data values as ECC enabled.  
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F50L1G41LB (2M)  
OTP Area Details Table  
Value Description  
Item  
Data Length  
Unique ID Page address  
Parameter Page address  
Number of OTP pages  
00h  
01h  
28  
Factory programmed, Read only  
Factory programmed, Read only  
One Time Program and OTP lockable  
One Time Program and OTP lockable  
32-Byte x 16  
256-Byte x 3  
2112-Byte  
2112-Byte  
OTP page address  
02h – 1Dh  
Number of partial page programs for  
each page in the OTP area  
One Time Program and OTP lockable  
2112-Byte  
1
Parameter Page Data Table  
Description  
Byte  
Value  
0-3  
4-5  
Parameter page signature ("O", "N", "F", "I")  
Revision number  
4Fh, 4Eh, 46h, 49h  
00h, 00h  
6-7  
8-9  
Features supported  
Optional commands supported  
Reserved  
00h, 00h  
2Ch, 00h  
All 00h  
10-31  
50h, 4Fh, 57h, 45h, 52h, 43h, 48h, 49h, 50h, 20h, 20h,  
20h  
32-43  
44-63  
Device manufacturer  
50h, 53h, 55h, 31h, 47h, 53h, 32h, 30h, 44h, 58h, 20h,  
20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h  
Device model  
64  
Manufacturer ID  
Date code  
C8h  
65-66  
67-79  
80-83  
00h, 00h  
All 00h  
Reserved  
Number of data bytes per page  
00h, 08h, 00h, 00h  
84-85  
Number of spare bytes per page  
40h, 00h  
86-91  
92-95  
96-99  
100  
Reserved  
All 00h  
Number of pages per block  
Number of blocks per unit  
Number of logical units  
40h, 00h, 00h, 00h  
00h, 04h, 00h, 00h  
01h  
101  
Number of address cycles  
00h  
102  
Number of bits per cell  
01h  
103-104  
105-106  
Number of maximum bad blocks per unit  
Block endurance  
14h, 00h  
01h, 05h  
107  
108-109  
110  
Guaranteed valid blocks at beginning of target  
Block endurance of guaranteed valid blocks  
Number of partial programs per page  
Reserved  
01h  
00h, 00h  
04h  
111  
00h  
112  
Number of bits ECC  
00h  
113  
114  
Number of Interleaved address bits  
Interleaved operation attributes  
00h  
00h  
115-127  
128  
Reserved  
All 00h  
08h  
I/O pin capacitance  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2  
44/49  
ESMT  
F50L1G41LB (2M)  
129-132  
133-134  
Reserved  
All 00h  
tPROG (max)  
tBERS (max)  
tR (max)  
84h, 03h  
135-136  
137-138  
139-163  
10h, 27h  
64h, 00h  
All 00h  
Reserved  
164-165  
166-253  
Vendor-specific revision number  
Reserved  
00h, 00h  
All 00h  
254-255  
256-511  
Integrity CRC  
Set at test  
Values of bytes 0-255  
Values of bytes 0-255  
Values of bytes 0-255  
512-767  
768+  
Values of bytes 0-255  
Additional redundant parameter pages  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 45/49  
ESMT  
F50L1G41LB (2M)  
PACKING DIMENSIONS  
8-Contact WSON ( 8x6 mm )  
MILLIMETERS  
INCHES  
SYMBOL  
Min  
0.70  
0.00  
0.35  
0.19  
7.90  
3.35  
5.90  
4.25  
Normal  
0.75  
0.035  
0.40  
0.20  
8.0  
Max  
0.8  
Min  
Normal  
0.03  
Max  
A
A1  
b
0.028  
0.000  
0.014  
0.007  
0.311  
0.132  
0.232  
0.167  
0.031  
0.002  
0.018  
0.010  
0.319  
0.136  
0.240  
0.171  
0.05  
0.45  
0.25  
8.10  
3.45  
6.10  
4.35  
0.001  
0.016  
0.008  
0.315  
0.134  
0.236  
0.168  
0.05BSC  
0.020  
…
C
D
D2  
E
3.40  
6.0  
E2  
e
4.30  
1.27BSC  
0.50  
…
L
0.45  
0.00  
0.55  
0.08  
0.018  
0.000  
0.022  
0.003  
y
NOTE: BSC, Basic lead spacing between centers.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 46/49  
ESMT  
F50L1G41LB (2M)  
PACKING DIMENSIONS  
8-Contact WSON ( 8x6 mm ) without expose metal pad  
Pin# 1 index side  
D
L
DETAIL A  
"A"  
e
DETAIL B  
"B"  
Symbol  
Dimension in mm  
Dimension in inch  
Norm  
Min  
0.70  
0.00  
0.35  
7.90  
5.90  
Min  
0.75  
0.02  
0.40  
8.00  
Min  
0.80  
0.05  
0.45  
8.10  
6.10  
Min  
Max  
A
A1  
b
D
E
0.028  
0.000  
0.014  
0.311  
0.232  
0.030  
0.001  
0.016  
0.315  
0.031  
0.002  
0.018  
0.319  
0.240  
6.00  
0.236  
e
L
1.27 BSC  
0.50  
0.050 BSC  
0.020  
0.40  
0.60  
0.016  
0.024  
Controlling dimension : millimeter  
(Revision date : Apr 25 2018)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 47/49  
ESMT  
F50L1G41LB (2M)  
Revision History  
Revision  
0.1  
Date  
Description  
2016.11.21  
2017.01.03  
Original  
Modify title and product ID  
0.2  
Add Read Unique ID Page / Read Parameter Page / OTP  
Operations  
0.3  
0.4  
2017.08.29  
2018.01.02  
Modify 8-Contact WSON ( 8x6 mm ) PACKING  
DIMENSIONS  
1.0  
1.1  
2018.08.06  
2018.12.03  
Delete Preliminary  
Modify the packing dimension of WSON package  
1. Restore the packing dimension of WSON package  
1.2  
2019.01.31  
2. Add the product ID and packing dimension of WSON  
package without expose metal pad  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 48/49  
ESMT  
F50L1G41LB (2M)  
Important Notice  
All rights reserved.  
No part of this document may be reproduced or duplicated in any form or  
by any means without the prior permission of ESMT.  
The contents contained in this document are believed to be accurate at  
the time of publication. ESMT assumes no responsibility for any error in  
this document, and reserves the right to change the products or  
specification in this document without notice.  
The information contained herein is presented only as a guide or  
examples for the application of our products. No responsibility is  
assumed by ESMT for any infringement of patents, copyrights, or other  
intellectual property rights of third parties which may result from its use.  
No license, either express , implied or otherwise, is granted under any  
patents, copyrights or other intellectual property rights of ESMT or  
others.  
Any semiconductor devices may have inherently a certain rate of failure.  
To minimize risks associated with customer's application, adequate  
design and operating safeguards against injury, damage, or loss from  
such failure, should be provided by the customer when making  
application designs.  
ESMT's products are not authorized for use in critical applications such  
as, but not limited to, life support devices or system, where failure or  
abnormal operation may directly affect human lives or cause physical  
injury or property damage. If products described here are to be used for  
such kinds of application, purchaser must do its own quality assurance  
testing appropriate to such applications.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jan. 2019  
Revision: 1.2 49/49  

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