F59D4G81KA-45BCG2R [ESMT]
4 Gbit (512M x 8) 1.8V NAND Flash Memory;
| 型号： | F59D4G81KA-45BCG2R |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | 4 Gbit (512M x 8) 1.8V NAND Flash Memory |
| 文件： | 总50页 (文件大小：1319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
(Preliminary)
F59D4G81KA (2R)
Flash
4 Gbit (512M x 8)
1.8V NAND Flash Memory
FEATURES
Voltage Supply
1bit/cell
Command/Address/Data Multiplexed DQ Port
Hardware Data Protection
Program/Erase Lockout During Power Transitions
Reliable CMOS Floating Gate Technology
VCC: 1.8V (1.7 V ~ 1.95V)
Organization
Page Size: (4K + 256) bytes
Data Register: (4K + 256) bytes
Block Size: 64Pages = (256K + 16K) bytes
Number of Planes: 1
Compliant to JESD47K Specifications
ECC Requirement: 8bit / 512Byte
Endurance: 60K-P/E Cycle Times
Number of Block per Die (LUN)= 2048
Automatic Program and Erase
Uncycled Data Retention: 10year of real time use at 55°C
Command Register Operation
Number of partial program cycles in the same page (NOP): 4
Automatic Page 0 Read at Power-Up Option
Page Program: (4K + 256) bytes
Block Erase: (256K + 16K) bytes
ONFI 1.0 compliant
Page Read Operation
Boot from NAND support
Automatic Memory Download
Random Read: 25us (Max.)
Read Cycle: 45ns
Cache Program Operation for High Performance Program
Cache Read Operation
Copy-Back Operation
EDO mode
Write Cycle Time
Page Program Time: 400us (Typ.)
700us (Max.)
Block Erase Time: 3.5 ms (Typ.)
10ms (Max.)
Page copy
ORDERING INFORMATION
Product ID
Speed
45 ns
45 ns
45 ns
Package
48 pin TSOPI
63 ball BGA
67 ball BGA
Comments
Pb-free
F59D4G81KA -45TG2R
F59D4G81KA -45BG2R
F59D4G81KA -45BCG2R
Pb-free
Pb-free
GENERAL DESCRIPTION
The device has 4352-byte static registers which allow program and read data to be transferred between the register and the memory
cell array in 4352-byte increments. The Erase operation is implemented in a single block unit (256Kbytes + 16Kbytes).
The device is a memory device which utilizes the I/O pins for both address and data input/output as well as command inputs. The
Erase and Program operations are automatically executed making the device most suitable for applications such as solid state file
storage, voice recording, image file memory for still cameras and other systems which require high density non-volatile memory data
storage.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 1/50
ESMT
(Preliminary)
F59D4G81KA (2R)
PIN CONFIGURATION (TOP VIEW)
(TSOPI 48L, 12mm X 20mm Body, 0.5mm Pin Pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 2/50
ESMT
(Preliminary)
F59D4G81KA (2R)
BALL CONFIGURATION (x8) (TOP VIEW)
(BGA 63 BALL, 9mm X 11mm Body, 0.8 Ball Pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1
3/50
ESMT
(Preliminary)
F59D4G81KA (2R)
BALL CONFIGURATION (TOP VIEW)
(BGA 67 Ball, 6.5mmx8mmx1.0mm Body, 0.8mm Ball Pitch)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 4/50
ESMT
(Preliminary)
F59D4G81KA (2R)
PIN /BALL NAMES
Pin/Ball Name
Type
Function
VCC
VSS
Supply
Supply
NAND Power Supply
Ground
Data inputs/outputs: The I/O pins are used to input command, address and data, and to
output data during read operations. The I/O pins float to high-z when the chip is deselected or
when the outputs are disabled.
I/O0 to I/O7
Input/output
Address latch enable: The ALE input controls the activating path for addresses sent to the
internal address registers. Addresses are latched into the address register through the I/O
ports on the rising edge of WE# with ALE high.
ALE
CLE
Input
Input
Command latch enable: The CLE input controls the activating path for commands sent to the
internal command registers. Commands are latched into the command register through the I/O
ports on the rising edge of the WE# signal with CLE high.
Chip enable: The CE# input is the device selection control. When the device is in the Busy
state, CE# high is ignored, and the device does not return to standby mode in program or
erase operation. Regarding CE# control during read operation, refer to ’Page read’ section of
Device operation.
CE#
Input
Read enable: The RE# input is the serial data-out control, and when active low, it drives the
data onto the I/O bus. Data is valid after tREA of rising edge & falling edge of RE# which also
increments the internal column address counter by one.
RE#
Input
Input
Write enable: The WE# input controls writes to the I/O ports. Commands, address and data
are latched on the rising edge of the WE# pulse.
WE#
Write protect: The WP# pin provides inadvertent write/erase protection during power
transitions. The internal high voltage generator is reset when the WP# pin is active low.
WP#
Input
Ready/busy: The R/B# output indicates the status of the device operation. When low, it
indicates that a program, erase or random read operation is in progress and returns to high
state upon completion. It is an open drain output and does not float to high-z condition when
the chip is deselected or when outputs are disabled.
R/B#
NC
Output
-
No connect: Lead is not internally connected.
NOTE: Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 5/50
ESMT
(Preliminary)
F59D4G81KA (2R)
Block Diagram
Vcc Vss
Status register
Address register
Command register
Column buffer
Column decoder
Data register
Sense amp
I/O0
to
I/O
Control circuit
I/O7
CE#
CLE
ALE
WE#
RE#
Memory cell array
Control circuit
Logic control
WP#
R/B#
HV generator
R/B#
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1
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ESMT
(Preliminary)
F59D4G81KA (2R)
Definitions and Abbreviations
LSB
Acronym for the least significant bit.
Address
The address is comprised of a column address 2 cycles and a row address with 3 cycles. The row address identifies the
page, block, and LUN to be accessed. The column address identifies the byte within a page to access.
Column
The byte location within the page register.
Row
Refer to the block and page to be accessed.
Page
The smallest addressable unit for the Read and the Program operations.
Block
Consists of multiple pages and is the smallest unit for the Erase operation.
Page register
Register used to transfer data to and from the Flash Array.
Cache register
Register used to transfer data to and from the Host.
Defect area
The defect area is where the factory defects are marked by the manufacturer. It is a reference for initial invalid block(s).
Device
The packaged NAND unit. A device may contain more than a target.
LUN (Logical Unit Number)
The minimum unit that can independently execute commands and report status. There are one or more LUNs per CE#.
Target
An independent NAND Flash component with its own CE# signal.
SR[x] (Status Read)
SR refers to the status register contained within a particular LUN. SR[x] refers to bit x in the status register for the
associated LUN.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 7/50
ESMT
(Preliminary)
F59D4G81KA (2R)
Absolute Maximum Rating
Parameter
Symbol
VCC
Rating
Unit
V
-0.6 to +2.5
-0.6 to +2.5
Voltage on any pin relative to VSS
Short Circuit Current
VIN
VI/O
-0.6 to Vcc+0.3(<2.5V)
5
IOS
mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Operating Temperature Condition
Parameter
Operating Temperature Range
Soldering Temperature (10s)
Storage Temperature
Symbol
TOPER
Rating
0 to +70
260
Unit
°C
TSOLDER
TSTG
°C
-55 to +125
°C
Note:
1.
2.
Operating Temperature TOPER is the case surface temperature on the center/top side of the NAND.
Operating Temperature Range specifies the temperatures where all NAND specifications will be supported. During operation, the
NAND case temperature must be maintained between the range specified in the table under all operating conditions.
Recommended Operating Conditions
(Voltage reference to GND, TA= 0 to 70°C)
Parameter
Supply Voltage
Symbol
VCC
Min
1.7
Typ.
Max
1.95
Unit
1.8
V
High Level Input Voltage
Low Level Input Voltage
Ground Voltage
VIH
0.8 VCC
-0.3
-
-
VCC + 0.3
0.2 VCC
0
VIL
VSS
0
0
V
Valid Blocks
Parameter
Symbol
Min
Typ.
Max
Unit
F59D4G81KA (2R)
NVB
2,008
-
2,048
Block
Note:
1.
The device may include initial invalid blocks when first shipped. The number of valid blocks is presented as first shipped. Invalid
blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation.
Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial
invalid blocks.
2.
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 8/50
ESMT
(Preliminary)
F59D4G81KA (2R)
DC Operation Characteristics
(Recommended operating conditions otherwise noted)
Parameter
Symbol
Test Conditions
Min
Typ.
Max
Unit
Page Read
ICC1
CE#= VIL, Iout= 0, tRC= tRC(min)
-
15
with Serial Access
Operating
Current
30
Program
Erase
ICC2
ICC3
-
-
-
15
15
-
mA
-
Stand-by Current (TTL)
Stand-by Current (CMOS)
Input Leakage Current
ISB1
CE#= VIH, WP#= 0V/VCC
CE#= VCC-0.2, WP#= 0V/VCC
VIN= 0 to VCC (max)
VOUT= 0 to VCC (max)
IOH= -0.1mA
-
1
50
ISB2
-
10
-
ILI
-
+/-10
+/-10
-
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Output Low Current (R/B#)
ILO
-
-
uA
VOH
VCC – 0.2
-
VOL
IOL= 0.1mA
-
-
-
0.2
-
IOL (R/B#)
mA
VOL= 0.2V
4
Note :
1.
2.
3.
Typical value are measured at VCC= 1.8V, TA= 25°C. Not 100% tested.
ICC1 and ICC2 are without data cache.
ICC1, ICC2, ICC3, and ISB2 are the values of one chip.
Capacitance
(TA= 25°C, VCC= 1.8V, f= 1.0MHz)
Symbol
CDQ
Test Condition
VOUT= 0V
Min
Max
Unit
pF
Item
Input/Output Capacitance
Input Capacitance
-
-
10
10
CIN
VIN= 0V
pF
Note: Capacitance is periodically sampled and not 100% tested.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 9/50
ESMT
(Preliminary)
F59D4G81KA (2R)
Write Protect
When WP# is enabled, Flash array is blocked from any program and erase operations. This signal shall only transitioned when a target
is idle. The host shall be allowed to issue a new command after tWW once WP# is enabled. Figures below describes the tWW timing
requirement, shown with the start of a Program command and the start of a Erase command.
Write Protect timing requirements of the Program operation
Write Protect timing requirements of the Erase operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
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ESMT
(Preliminary)
F59D4G81KA (2R)
Memory Organization
Addressing
There are two address types used: the column address and the row address. The column address is used to access bytes within a
page, i.e. the column address is the byte offset into the page. The row address is used to address pages, blocks, and LUNs.
When both the column and row addresses are required to be issued, the column address is always issued first in one or more 8-bit
address cycles. The row addresses follow in one or more 8-bit address cycles. There are some functions that may require only row
addresses, such as Block Erase. In this case the column addresses shall not be issued.
For both column and row addresses, the first address cycle always contains the least significant bits and the last cycle always contains
the most significant bits. If there are bits in the most significant cycles of the column and row addresses that are not used, then they are
required to be cleared to zero.
1 Block = 64 Pages
2048 Blocks
8 bits
256 Byte
4096 Byte
4352 Byte
I/O0 ~ I/O7
Page Register
Array Address
I/O0
A0
I/O1
A1
I/O2
A2
I/O3
A3
I/O4
I/O5
A5
I/O6
A6
I/O7
A7
Address
1st cycle
2nd cycle
3rd cycle
4th cycle
5th cycle
Note:
A4
A12
A17
A25
*L
Column Address
Column Address
Row Address
Row Address
Row Address
A8
A9
A10
A15
A23
*L
A11
A16
A24
*L
*L
*L
*L
A13
A21
A29
A14
A22
*L
A18
A26
*L
A19
A27
*L
A20
A28
*L
1. Column address: Starting Address of the Register.
2. *L must be set to ‘Low’
3. The device ignores any additional input of address cycles than required.
4. A13~A18 are for Page Address, A19~A29 are for Block Address.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 11/50
ESMT
(Preliminary)
F59D4G81KA (2R)
Addressing for Program Operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most
significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB
among the pages to be programmed. Therefore, LSB page doesn’t need to be page 0.
Page 63
Page 31
Page 63
Page 31
(64)
(32)
(64)
(1)
Page 2
Page 1
Page 0
Page 2
Page 1
Page 0
(3)
(2)
(1)
(3)
(32)
(2)
Data register
Data register
From the LSB page to MSB page
Ex.) Random page program (Prohibition)
DATA IN: Data (1) → Data (64)
DATA IN: Data (1) → Data (64)
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Publication Date: Jan. 2020
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ESMT
(Preliminary)
F59D4G81KA (2R)
Factory Defect Mapping and Error Management
Mask Out Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed. The information
regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same
quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the
performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system
design must be able to mask out the initial invalid block(s) via address mapping.
Identifying Initial Invalid Block(s) and Block Replacement Management
If a block is defective, the manufacturer shall mark as defective by setting the Defective Block Marking, as shown in figure, of the first or
second page of the defective block to a value of non-FFh. The Defective Block Marking is located on the first byte of spare data area in
the pages within a block.
The host shall not erase or program blocks marked as defective by the manufacturer, and any attempt to do so yields indeterminate
results. Figure below outlines the flow chart how to create an initial invalid block table. It should be performed by the host to create the
initial invalid block table prior to performing any erase or programming operations on the target. All pages in non-defective blocks are
read FFh with ECC enabled on the controller. A defective block is indicated by the majority of bits being read non-FFh in the Defective
Block Marking location of either the first page or second page of the block. The host shall check the Defective Block Marking location of
both the first and second page of each block to verify the block is valid prior to any erase or program operations on that block.
Over the lifetime use of a NAND device, the Defective Block Marking of defective blocks may encounter read disturbs that cause bit
changes. The initial defect marks by the manufacturer may change value over the lifetime of the device, and are expected to be read
by the host and used to create a bad block table during initial use of the part.
Elite Semiconductor Memory Technology Inc.
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ESMT
(Preliminary)
F59D4G81KA (2R)
Start
Set Block Address=0
Increase
Block
Address
Create Initial
Invalid Block
Table
n
Check “FFh” at the 1st Byte column address in
the spare area of the 1st and 2nd page in the
block.
Check
”FFh”?
yes
n
Last Block?
yes
End
Algorithm for Bad Block Scanning
For (i=0; i<Num_of_LUs; i++)
{
For (j=0; j<Blocks_Per_LU; j++)
{
Defect_Block_Found=False;
Read_Page(lu=i, block=j, page=0);
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;
Read_Page(lu=i, block=j, page=1);
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;
If (Defect_Block_Found) Mark_Block_as_Defective(lu=i, block=j);
}
}
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
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ESMT
(Preliminary)
F59D4G81KA (2R)
Errors in Write or Read Operation
Within its lifetime, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.
The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after
erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of
the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and
reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve
the efficiency of memory space, it is recommended that the read or verification failure due to bit error(less than 8bits/512bytes) be
reclaimed by ECC without any block replacement. The additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Detection and Countermeasure Sequence
Read Status after Erase Block Replacement
Read Status after Program Block Replacement
Verify ECC ECC Correction
Erase failure
Program failure
Read
Up to 8 bits failure
Note: Error Correcting Code RS Code or BCH Code etc.
Example: 8bit correction / 512Byte
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Publication Date: Jan. 2020
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ESMT
(Preliminary)
F59D4G81KA (2R)
Start
Write
80h
No
I/O6=1? or
R/B#=1?
Write
Address
Yes
Write
Data
No
I/O0=0?
Program Error
Yes
Write
10h
Mark Bad Block
& Replace Block
Program
Completed
Read Status
Register
Program Flow Chart
Start
No
I/O6=1?
or
Write
60h
R/B#=1?
Yes
Write Block
Address
No
I/O0=0?
Erase Error
Write
D0h
Yes
Read
Status
Register
Erase
Completed
Mark Bad Block
Erase Flow Chart
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ESMT
(Preliminary)
F59D4G81KA (2R)
Start
Write
00h
ECC Generation
Yes
Yes
Write
Address
No
Verify
ECC
Reclaim the Error
Write
30h
Read
Data
Page Read
Completed
Read Flow Chart
Block A
1st
~
(n-1)th
n th
An error occurs.
page
1
Block B
Buffer memory of the controller
* Step 1
2
1st
~
(n-1)th
When an error happens in the nth page of the Block 'A' during erase or program
operation.
* Step 2
Copy the data in the 1st ~ (n-1)th page to the same location of another free
block. (Block 'B')
An error occurs.
n th
* Step 3
Then, copy the nth page data of the Block 'A' in the buffer memory to the nth
page of the Block 'B'
page
* Step 4
Do not erase or program to Block 'A' by creating an 'invalid block' table or other
appropriate scheme.
Block Replacement
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(Preliminary)
F59D4G81KA (2R)
Function Description
Discovery and Initialization
The device is designed to offer protection from any involuntary program/erase during power transitions. An internal voltage detector
disables all functions whenever VCC is below about 1.5V. Max busy time is 5ms after Power-On Reset. During busy time of resetting,
the acceptable command is the Read Status (70h).
WP# provides hardware protection and is recommended to be kept at VIL during power up and power down. The two step command
sequence for program/erase provides additional protection. Figure below defines the Initialization behavior and timings.
Data Protection and Power On Sequence
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the
initialization the device R/B# signal indicates the Busy state as shown in the figure below. In this time period, the acceptable commands
are 70h.
The WP# signal is useful for protecting against data corruption at power on/off.
AC Waveforms for Power Transition
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ESMT
(Preliminary)
F59D4G81KA (2R)
Mode Selection
SDR
CLE
ALE
CE#
WE#
RE#
WP#
Mode
H
L
H
L
L
H
X
X
H
H
H
X
Command Input
Read Mode
Write Mode
L
H
L
L
L
L
L
L
L
L
H
H
H
H
Address Input (5 clock)
Command Input
H
L
Address Input (5 clock)
Data Input
L
H
Data Output
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
X
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
H
H
X
X(1)
L
(2)
X
0V/VCC
Stand-by
Note :
1. X can be VIL or VIH.
2. WP# should be biased to CMOS high or CMOS low for standby.
AC Test Condition
(TA= 0 to 70°C, VCC= 1.7V ~ 1.95V)
Parameter
Single-ended signaling
Input Pulse
0 to VCC
3ns
Input Rise and Fall Times
Input and Output Timing Levels
Output Load*
VCC/2
CL(30pF) and 1TTL
Note: Refer to Ready/Busy, R/B# output’s Busy to Ready time is decided by the pull-up resistor (Rp) tied to the R/B# pin.
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ESMT
(Preliminary)
F59D4G81KA (2R)
Read / Program / Erase Characteristics
(TA= 0 to 70°C, VCC= 1.7V ~ 1.95V)
Parameter
Symbol
tR
Min
Typ
-
Max
25
Unit
us
Data Transfer from Cell to Register
Program Time
-
-
tPROG
tLPROG
tCBSY
400
800
3
700
1400
750
4
us
Last Page Program Time
us
Dummy Busy Time for Cache Operation
-
-
-
-
us
Number of Partial Program Cycles in the Same Page
Block Erase Time
NOP
-
cycle
ms
us
tBERS
3.5
-
10
tDCBSYW2
700
Data Cache Busy Time in Write Cache (following 15h)
Note:
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V Vcc and
25°C temperature.
2. tCBSY max. time depends on timing between internal program completion and data-in.
3. tDCBSYW2 depends on the timing between internal programming time and data in time.
4. tLPROG=tPROG(last page) + tPROG(last-1 page) – Command load time(last page) – Address load time(last page)-Data load time(last
page)
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ESMT
(Preliminary)
F59D4G81KA (2R)
AC Timing Characteristics
SDR (VCC = 1.7~1.95V)
Parameter
Symbol
Min
12
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
(1)
CLE Setup Time
tCLS
-
-
CLE Hold Time
tCLH
(1)
CE# Setup Time
tCS
20
5
-
CE# Hold Time
tCH
tWP
-
WE# Pulse Width
12
12
5
-
(1)
ALE Setup Time
tALS
-
ALE Hold Time
tALH
-
(1)
Data Setup Time
tDS
12
5
-
Data Hold Time
tDH
tWC
tWH
-
Write Cycle Time
45
10
70
-
-
WE# High Hold Time
Address to Data Loading Time
Data Transfer from Cell to Register
ALE to RE# Delay
-
(2)
tADL
-
tR
25
-
tAR
tCLR
tRR
tRW
tRP
tWB
10
10
20
20
12
-
CLE to RE# Delay
-
Ready to RE# Low
-
Ready to WE# Falling Edge
RE# Pulse Width
-
WE# High to Busy
100
WP# Low to WE# Low (disable mode)
WP# High to WE# Low (enable mode)
Read Cycle Time
tWW
100
-
ns
tRC
tCR
45
9
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE# Low to RE# Low
RE# Access Time
tREA
tCEA
tRHZ
tCHZ
tCLHZ
tRHOH
tRLOH
tCOH
tREH
tIR
-
20
25
100
30
30
-
CE# Access Time
-
RE# High to Output Hi-Z
CE# High to Output Hi-Z
CLE High to Output Hi-Z
RE# High to Output Hold
RE# Low to Output Hold
CE# High to Output Hold
RE# High Hold Time
Output Hi-Z to RE# Low
RE# High to WE# Low
WE# High to CE# Low
-
-
-
15
5
-
15
10
0
-
-
-
tRHW
tWHC
100
30
-
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ESMT
(Preliminary)
F59D4G81KA (2R)
SDR (VCC = 1.7~1.95V)- continued
Parameter
Symbol
tWHR1
Min
Max
-
Unit
ns
ns
us
us
us
us
us
us
us
WE# High to RE# Low (Read Status)
60
60
-
tWHR2
WE# High to RE# Low (Column Address Change in Read)
Ready
-
5
Read
-
5
Device Resetting
Time during…
tRST
Program
-
10
250
30
30
1
Erase
-
Data Cache Busy in Read Cache (following 31h and 3Fh)
Data Cache Busy in Page Copy (following 3Ah)
Busy time for Set OTP
tDCBSYR1
tDCBSYR2
tFEAT
-
-
-
Note:
1. The transition of the corresponding control pins must occur only once while WE# is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE# rising edge of first data cycle.
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ESMT
(Preliminary)
F59D4G81KA (2R)
General Timing
CE bar = CE#
WE bar = WE#
RE bar = RE#
R/ B bar = R/B#
Command/Address/Data Latch Timing
CLE
ALE
CE#
Setup Time
Hold Time
WE#
I/O
tDH
tDS
: VIH or VIL
Command/Address/Data Latch Timing
Command Input Cycle
tCLS
tCS
tCLH
tCH
CLE
CE#
WE#
tWP
tALS
tALH
ALE
I/O
tDS
tDH
: VIH or VIL
Command Input Cycle Timing
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ESMT
(Preliminary)
F59D4G81KA (2R)
Address Input Cycle
tCLH
tCLS
CLE
CE#
WE#
ALE
I/Ox
tCS
tCH
tWC
tWC
tWC
tWC
tWP
tWP
tWP
tWP
tWP
tWH
tWH
tALH
tWH
tALH
tWH
tALH
tALH
tALH
tALS
tALS
tALS
tALS
tALS
t
tDS
tDH
DS tDH
tDH
tDS
tDS t
DH
tDS
tDH
Col.Add1
Row.Add1
Row.Add3
Col.Add2
Row.Add2
Address Input Cycle Timing
Data Input Cycle
tCLS
tCLH
CLE
CE#
tCH
tCS
tCS
tCH
tALS
tALH
tWC
ALE
tWP
tWH
tWP
tWP
WE#
tDH
tDH
tDS
tDS
tDS tDH
I/O
DIN1
DINF
DIN0
Note: DINF means the Final Data Input.
Data Input Cycle Timing
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ESMT
(Preliminary)
F59D4G81KA (2R)
Data Output Cycle
tRC
tCR
CE#
RE#
tCHZ
tRHZ
tRP
tREH
tRHZ
tRHOH
tRP
tRP
tRHZ
tREA
tCEA
tREA
tRHOH
tREA
tRHOH
tCEA
I/O
tRR
R/B#
: VIH or VIL
Data Output Cycle Timing
Basic Data Output
CLE
tCLH
tCH
tCLS2
tCS2
tCR
CE#
WE#
ALE
tCHZ
tCLHZ
tALH
tREA
tRC
tRHZ
tRHOH
tRP
tREH
tRP
tRP
RE#
I/O
tDH
tDS
tRLOH
tREA
tREA
tRLOH
Command
Dout
tRHOH
Dout
Comma
tRP
R/B#
Basic Data Output Timing
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ESMT
(Preliminary)
F59D4G81KA (2R)
Read ID
tCLS
tCLS
tCS
CLE
CE#
tCR
tCH
tCS
tWHR1
tCH
WE#
tALH
tALS
tALH
tAR
ALE
RE#
tDH
tREA
tREA
tREA
tREA
tREA
tDS
90h
I/O
00h
Address
Device code
Maker code
Read ID Operation Timing
Status Read Cycle
tCLR
tCLS
CLE
tCLH
tCS
tCR
CE#
tCHZ
tWP
tCH
tCEA
WE#
tWHC
tRHZ
tWHR1
RE#
tIR
tDS tDH
tRHOH
tREA
Status
output
I/O
70h
R/B#
: VIH or VIL
Status Read Cycle Timing
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ESMT
(Preliminary)
F59D4G81KA (2R)
Page Read Operation
tCLR
CLE
CE#
tCLS
tCLS
tCLH
tCH
tCLH
tCH
tCS
tCS
tWC
WE#
tALH
tALS
tALH
tALS
ALE
RE#
tR
tRC
tWB
tCEA
tDS tDH
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA
RA
Column Address
tDS tDH
30h
tRR
tREA
Dout
N+1
Dout
N
I/O
CA
RA
RA
Data out from
Col. Add. N
R/B#
Page Read Operation Timing
Page Program Operation
CLE
CE#
tWC
tWC
tWC
WE#
tADL
tPROG
tWB
tWHR
ALE
RE#
Row
Add3
Row
Add2
Col
Add2
Row
Col
Add1
Din
N
Din
M
80h
70h
IO0
10h
I/OX
Program
Command
1 up to m Byte
Serial input
Read Status
Command
Serial data
Input Command
Column
Address
Row Address
R/B#
I/O0=0 Successful Program
I/O0=1 Error in Program
Page Program Operation
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ESMT
(Preliminary)
F59D4G81KA (2R)
Command Description and Device Operation
Command Sets
Function
1st Cycle
2nd Cycle
Acceptable Command during Busy
Read
00h
00h
90h
FFh
80h
85h
60h
85h
05h
70h
80h
31h
3Fh
00h
8Ch
8Ch
ECh
EDh
30h
35h
-
Read for Copy-Back
Read ID
Reset
-
O
Page Program
Copy-Back Program
Block Erase
Random Data Input(1)
Random Data Output(1)
10h
10h
D0h
-
E0h
-
Read Status
O
Cache Program
15h
-
Cache Read
Read Start for Last Page Cache Read
Read for Page Copy with Data Out
Auto Program with Data Cache during Page Copy
Auto Program for last page during Page Copy
Read Parameter Page
-
3Ah
15h
10h
-
Read Unique ID
-
Note:
1. Random Data Input/Output can be executed in a page.
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ESMT
(Preliminary)
F59D4G81KA (2R)
Operations
Page Read Operation
The Page Read function reads a page of data identified by row address for the selected LUN. The page of data is made available to be
read from the page register starting at the specified column address. Figure below defines the Page Read behavior and timings.
Reading beyond the end of a page results in indeterminate values being returned to the host.
CE#
CLE
ALE
WE#
RE#
tR
R/B#
I/Ox
Data Output( Serial Access)
00h Address(5cycles) 30h
Col.Add.1,2 & Row Add.1,2,3
(00h Command)
Data Field
Spare Field
Page Read Operation Timing
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ESMT
(Preliminary)
F59D4G81KA (2R)
The Random Data Output function changes the column address from which data is being read in the page register for the selected LUN.
The Random Data Output command shall only be issued when LUN is in a read idle condition. Figure below defines the Random Data
Output behavior and timings. The host shall not read data from the LUN until tWHR(ns) after the second command (i.e. E0h) is written to
the LUN.
RE#
tR
R/B#
I/Ox
Data Output( Serial Access)
Address 5 cycles
30h
00h
Col.Add.1,2 & Row Add.1,2,3
1
Data Field
Spare Field
RE#
R/B#
I/Ox
Data Output( Serial Access)
Col.2
Col.1
E0h
05h
Col.Add.1,2
1
Data Field
Spare Field
Random Data Output in a Page Timing
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ESMT
(Preliminary)
F59D4G81KA (2R)
Cache Read Operation
Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read command (00h-30h) is always
issued before invoking Cache Read. After issuing the Cache Read command (31h), read data of the designated page (page N) are
transferred from data registers to cache registers in a short time period of tDCBSYR1, and then data of the next page (page N+1) is
transferred to data registers while the data in the cache registers are being read out. Host controller can retrieve continuous data and
achieve fast read performance by iterating Cache Read operation. The Read Start for Last Page Cache Read command (3Fh) is used
to complete data transfer from memory cells to data registers.
CLE
CE#
WE#
ALE
RE#
tR
1
tDCBSYR1
2
tDCBSYR1
tDCBSYR1
R/B#
I/O
7
5
3
4
6
00h
31h
31h
3Fh
30h
0
2
3
1
Col.M
Page N
the Final Col.Dout
Page N
Column 0 Dout
Page Address N +1
Page Address N +2
Page N + 2
Page Address N
Page N + 1
Page N + 2
Data Cache
Page Buffer
2
1
Page N + 1
Page N
7
3
5
4
6
Cell
Array
Page N
Page N +1
1
Page N + 2
3
5
3Fh & #RE clock
30h
31h & #RE clock
31h & #RE clock
Cache Read Operation Timing
If the 31h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out
from the Data Cache, and therefore the tR (Data transfer from memory cell to data register) will be reduced.
1.
2.
3.
4.
Normal read. Data is transferred from Page N to Data cache through Page Buffer. During this time period, the device outputs
Busy state for tR max.
After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again.
This data transfer takes tDCBSYR1 max and the completion of this time period can be deleted by Ready/Busy signal.
Data of Page N + 1 is transferred to Page Buffer from cell while the data of Page N in Data Cache can be read out by /RE clock
simultaneously.
The 31h command makes data of Page N + 1 transfer to Data Cache from Page Buffer after the completion of the transfer from
cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max.. This Busy period depends on the combination of the internal
data transfer time from cell to Page Buffer and the serial data out time.
5.
6.
Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data Cache can be read out by /RE
clock simultaneously.
The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the
transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max.. This Busy period depends on the combination
of the internal data transfer time from cell to Page Buffer and the serial data out time.
7.
Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command dose not transfer the data from the memory cell
to Page Buffer, the device can accept new command input immediately after the completion of serial data out.
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ESMT
(Preliminary)
F59D4G81KA (2R)
Page Program Operation
The device is programmed basically on a page basis, and each page shall be programmed only one before being erased. The
addressing order shall be sequential within a block. The contents of the page register are programmed into the Flash array specified by
row address. After tPROG program time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after
10h.Figure below defines the Page Program behavior and timings. Writing beyond the end of the page register is undefined.
R/B#
tPROG
“0”
80h
Address & Data Input
10h
70h
I/O0
Fail
I/Ox
Pass
Col. Add. 1,2 & Row Add.1,2,3
Data
“1”
Program & Read Status Operation Timing
The device supports random data input in a page. The column address for the next data, which will be written, may be changed to the
address using Random Data Input command (i.e. 85h). Random data input may be operated multiple times without limitation.
R/B#
tPROG
“0”
Address &
Data Input
Address &
Data Input
85h
10h
I/Ox
70h
I/O0
“1”
Fail
80h
Pass
Col. Add. 1,2 & Row Add.1,2,3
Data
Col. Add. 1,2
Data
Random Data Input in a Page Timing
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ESMT
(Preliminary)
F59D4G81KA (2R)
Cache Program Operation
The Cache Program function allows the host to write the next data for another page to the page register while a page of data to be
programmed to the Flash array for the selected LUN. When command 15h is issued, R/B# returns high (i.e. ready) when a cache
register is ready to be written after data in the cache register is transferred to a page register. However, when command 10h is issued
for the final page, R/B# turns to high after outstanding program operation performed by previous Cache Program command and the
program operation for the final page is completed. SR[0] is valid for this command after SR[5] transitions from zero to one until the next
transition. SR[1] is valid for this command after SR[6] transitions from zero to one, and it is invalid after the first Cache Program
command completion since there is no previous Cache Program operation. Cache Program operation shall work only within a block.
Figure below defines the Cache Program behavior and timings. Note that tLPROG at the end of the caching operation may be longer than
typical as this time also includes completing the programming operation for the previous page. Writing beyond the end of the page
register is undefined.
tCBSY
tCBSY
R/B#
I/Ox
Address & Data Input
15h
80h
15h
Address & Data Input
80h
Col. Add. 1,2 & Row Add.1,2,3
Data
Col. Add. 1,2 & Row Add.1,2,3
Data
1
Max.63 times repeatable
R/B#
I/Ox
tLPROG
80h
10h
70h
Address & Data Input
I/O0
“0”
Pass
Col. Add. 1,2 & Row Add.1,2,3
Data
“1”
Fail
1
Last Page Input and Program
Cache Program Operation Timing
Block Erase Operation
The Block Erase operation is done on a block basis. Only three cycles of row addresses are required for Block Erase operation and a
page address within the cycles is ignored while block address are valid. After Block Erase operation passes, all bits in the block shall be
set to one. SR[0] is valid for this command after SR[6] transitions from zero to one (i.e. the selected LUN is ready) until the LUN goes in
busy state by a next command. Figure below defines the Block Erase behavior and timings.
I/Ox
tBERS
60h
D0h
70h
Address Input
Row Add.1,2,3
I/O0
“0”
“1”
Pass
Fail
Block Erase Operation Timing
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ESMT
(Preliminary)
F59D4G81KA (2R)
Copy-Back Program Operation
The Copy-Back Program with Read for Copy-Back is configured to efficiently rewrite data stored in a page without data re-loading
when no error within the page is found. Since the time consuming re-loading cycles are removed, copy-back operation helps the
system performance improve. The benefit is especially obvious when a part of a block is updated and the rest of the block also needs
to be copied to the newly assigned free block. A read operation with "35h" command and the address of the source page moves the
whole 4,352-byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there
is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy
Data-Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command
(10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status
Register. When the Copy-Back Program is complete, the Write Status bit(I/O 0) may be checked. The Copy-Back operation consists of
Read for Copy-Back and Copy-Back Program. A host reads a page of data from a source page using Read for Copy-Back and copies
read data back to a destination page on the same LUN by Copy-Back Program command.
tPROG
tR
R/B#
I/Ox
Address
5Cycles
Address
5Cycles
00h
10h
70h
Data output
35h
85h
I/O0
“0”
Col. Add. 1,2 & Row Add. 1,2,3
Source Address
Col. Add. 1,2 & Row Add. 1,2,3
Destination Address
Pass
“1”
Fail
Page Copy-Back Program Operation Timing
After a host completes to read data from a page register, the host may modify data using Random Data Input command if required.
Figure below defines Copy-Back Program with Random Data Input behavior and timings.
tR
R/B#
I/Ox
Address
5Cycles
Address
5Cycles
00h
Data Input
Data output
35h
85h
Col. Add. 1,2 & Row Add. 1,2,3
Source Address
Col. Add. 1,2 & Row Add. 1,2,3
Destination Address
1
R/B#
I/Ox
tPROG
Address
Data Input
70h
10h
I/O0
85h
2Cycles
“0”
Pass
Col. Add.1,2
“1”
Fail
1
There is no limitation for the
Number of repetition
Page Copy-Back Program Operation with Random Data Input
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ESMT
(Preliminary)
F59D4G81KA (2R)
Read ID
CE#
CLE
tAR
WE#
tREA
tRC
RE#
I/Ox
3rd cyc.
4th cyc.
5th cyc.
2nd cyc.
1st cyc.
Maker Code.
90h
00h
Address 1cycle
Read ID Command
Device Code.
Read ID Timing
Read ID (00h Address ID Cycle)
Users can read five bytes of ID containing manufacturer code, device code and architecture information of the target by command 90h
followed by 00h address. The command register remains in Read ID mode until another command is issued.
Description
X8 device
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
Maker Code
C8h
5Ch
80h
19h
30h
Device Code
Internal Chip Number, Cell Type, etc
Page Size, Block Size, etc
Plane Number, ECC Level
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ESMT
(Preliminary)
F59D4G81KA (2R)
2nd ID Data
Item
Description
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
1Gb
2Gb
4Gb
8Gb
16Gb
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
Density
1.8V
3.3V
0
1
1
0
Voltage
SPI
X8
0
0
1
0
1
0
Interface
X16
3rd ID Data
Item
Description
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
1
2
4
8
0
0
1
1
0
1
0
1
Internal Chip Number
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
0
0
1
1
0
1
0
1
1
2
4
8
0
0
1
1
0
1
0
1
Number of
Simultaneously
Programmed Pages
Interleave Program
Between Multiple Chips
Not Support
Support
0
1
Not Support
Support
0
1
Cache Program
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ESMT
(Preliminary)
F59D4G81KA (2R)
4th ID Data
Item
Description
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
2KB
4KB
0
0
1
1
0
1
0
1
Page Size
(w/o redundant area)
8KB
Reserved
128KB
256KB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
512KB
Block Size
(w/o redundant area)
1MB
Reserved
Reserved
Reserved
Reserved
Reserved
128B
224B
400B
436B
512B
640B
1KB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Redundant Area Size
(Byte / Page Size)
5th ID Data
Item
Description
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
1
2
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
Plane Number
4
8
16
1bit
2bit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4bit
8bit
ECC Level
Reserved
12bit
24bit
40bit
60bit
Reserved
0
0
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ESMT
(Preliminary)
F59D4G81KA (2R)
Read Status
The Read Status function (command 70h) retrieves a status value for the last operation issued in the case of one-plane operations.
Both 70h is followed without address setting. Specifically, Read Status return the combined status values of the independent status
register bits according to Table below.
Read Status Definition
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Pass: 0
Fail: 1
Pass: 0
Fail: 1
Busy: 0
Ready: 1
Busy: 0
Ready: 1
Protected: 0
Not Protected: 1
Definition
Reserved Reserved Reserved
Read
NA
NA
NA
NA
NA
NA
NA
NA
NA
Busy/Ready
Write Protect
Cache
Read
Flash array
Busy/Ready
Host
Busy/Ready
NA
NA
Write Protect
Page
Program
Pass/Fail
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Busy/Ready
Write Protect
Write Protect
Write Protect
Cache
Program
Flash array
Busy/Ready
Host
Busy/Ready
Pass/Fail (N-1) Pass/Fail
Pass/Fail NA
Block
Erase
NA
Busy/Ready
Note:
1. During Block Erase, Page Program or Copy-Back operation, I/O0 is only valid when I/O6 shows the Ready state.
2. During Cache Program operation, I/O0 is only valid when I/O5 shows the Ready state, and I/O1 is only valid when I/O6 shows the
Ready state.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
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ESMT
(Preliminary)
F59D4G81KA (2R)
Reset
The device offers a reset function by command FFh. When the device is in ‘Busy’ state during any operation, the Reset operation will
abort these operations except during power-on when Reset shall not be issued until R/B# is set to one (i.e. ready). The contents of
memory cells being programmed are no longer valid, as the data will be partially programmed or erased. Although the device is already
in process of reset operation, a new Reset command will be accepted.
R/B#
I/Ox
tRST
FFh
Reset Timing
When Status Read command (70h) is input after Reset Operation
70
FF
Status ：Pass/Fail -> Pass
：Ready/Busy -> Ready
R/B#
Status Read after Reset operation
When two or more Reset commands are input in succession
(1)
FF
(2)
FF
(3)
FF
10
R/B#
FF
FF
The second
command is invalid, but the third
Successive Reset operation
command is valid.
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ESMT
(Preliminary)
F59D4G81KA (2R)
Read Parameter Page Operation
Read Parameter Page (ECh) command is used to read the ONFI parameter page programmed into the target. This command is
accepted by the target only when the die(s) on the target is idle. Writing ECh to the command register puts the target in read parameter
page mode. The target stays in this mode until another valid command is issued.
When ECh command is followed by one 00h address cycle, the target goes busy for tR. If the Read Status (70h) command is used to
monitor for command completion, the Read mode (00h) command must be used to re-enable data output mode.
A minimum of three copies of the parameter page are stored in the device. Each parameter page is 256 bytes. Random Data Output
(05h-E0h) can be used to change the location of data output. Each copy has the CRC value stored at the last two bytes. The software
can read the first copy of ONFI parameter page, calculate the CRC and compare it with the stored value. If mis-match found then the
2nd copy should be read and so forth.
Command Address
Cycle type
I/O[7:0]
R/B#
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
…
…
ECh
00h
P10
P00
P01
P11
tRR
tR
tWB
Read Parameter Page Operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 40/50
ESMT
(Preliminary)
F59D4G81KA (2R)
Parameter Page Data Structure
Byte
0-3
Description
Value
Parameter page signature ("O", "N", "F", "I")
Revision number
4Fh, 4Eh, 46h, 49h
02h, 00h
4-5
6-7
Features supported
10h, 00h
8-9
Optional commands supported
Reserved
33h, 00h
10-31
All 00h
50h, 4Fh, 57h, 45h, 52h, 43h, 48h, 49h, 50h,
20h, 20h, 20h
32-43
44-63
Device manufacturer
Device model
50h, 53h, 52h, 34h, 47h, 41h, 33h, 30h, 43h,
54h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h
64
Manufacturer ID
C8h
65-66
67-79
80-83
84-85
86-89
90-91
92-95
96-99
100
Date code
00h, 00h
All 00h
Reserved
Number of data bytes per page
Number of spare bytes per page
Number of data bytes per partial page
Number of spare bytes per partial page
Number of pages per block
Number of blocks per unit
Number of logical units
Number of address cycles
Number of bits per cell
00h, 10h, 00h, 00h
00h, 01h
00h, 04h, 00h, 00h
40h, 00h
40h, 00h, 00h, 00h
00h, 08h, 00h, 00h
01h
101
23h
102
01h
103-104 Number of maximum bad blocks per unit
105-106 Block endurance
28h, 00h
06h, 04h
01h
107
Guaranteed valid blocks at beginning of target
108-109 Block endurance of guaranteed valid blocks
00h, 00h
04h
110
111
112
113
114
Number of partial programs per page
Partial programming attributes
Number of bits ECC
00h
08h
Number of Interleaved address bits
Interleaved operation attributes
01h
0Ch
115-127 Reserved
All 00h
128
I/O pin capacitance
0Ah
129-130 Timing mode support (Reserved)
131-132 Program cache timing mode support (Reserved)
133-134 tPROG (max)
1Fh, 00h
1Fh, 00h
BCh, 02h
10h, 27h
19h, 00h
135-136 tBERS (max)
137-138 tR (max)
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Publication Date: Jan. 2020
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ESMT
(Preliminary)
F59D4G81KA (2R)
Parameter Page Data Structure- continued
Byte
Description
Value
139-140 tCCS (min)
141-163 Reserved
46h, 00h
All 00h
164-165 Vendor-specific revision number
Two-Plane Page Read support
00h, 00h
166
167
168
169
Bit[7:1]: Reserved (0)
Bit 0: 0= Doesn’t support Two Plane Page Read
Read cache support
Bit[7:1]: Reserved (0)
Bit 0: 0= Doesn’t support ONFI-specific read cache
Read Unique ID support
Bit[7:1]: Reserved (0)
Bit 0: 0= Doesn’t support ONFI-specific Read Unique ID
Programmable output impedance support
Bit[7:1]: Reserved (0)
00h
01h
01h
00h
Bit 0: 0= Doesn’t support programmable output impedance support
Number of programmable output impedance support
settings
170
00h
Bit[7:3]: Reserved (0)
Bit[2:0]: Number of programmable IO output impedance settings
171
172
173
174
Reserved
00h
00h
00h
00h
Programmable R/B# pull-down strength support
Bit[7:1]: Reserved (0)
Bit 0: 0= Doesn’t support programmable R/B# pull-down strength
Reserved
Number of programmable R/B# pull-down strength support
Bit[7:3]: Reserved (0)
Bit[2:0]: Number of programmable R/B# pull-down strength settings
OTP mode support
Bit[7:2]: Reserved (0)
Bit 1: 0= Doesn’t support Get/Set Feature command set
Bit 0: 1= support OTP mode
175
01h
OTP page start
Bit[7:0] = Page where OTP page space begins
OTP Data Protect address
Bit[7:0] = Page address to use when issuing OTP Data Protect command
Number of OTP pages
176
177
00h
00h
178
179
Bit[15:5]: Reserved (0)
Bit[4:0] = Number of OTP pages
1Eh
OTP Feature Address
90h
180-253 Reserved
All 00h
254-255 Integrity CRC
Set at test
256-511 Values of bytes 0-255
512-767 Values of bytes 0-255
Values of bytes 0-255
Values of bytes 0-255
768+
Additional redundant parameter pages
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 42/50
ESMT
(Preliminary)
F59D4G81KA (2R)
Read Unique ID Operation
Read Unique ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the
target only when the die(s) on the target is idle. Writing EDh to the command register puts the target in read unique ID mode. The target
stays in this mode until another valid command is issued.
When EDh command is followed by one 00h address cycle, the target goes busy for tR. If the Read Status (70h) command is used to
monitor for command completion, the Read mode (00h) command must be used to re-enable data output mode. After tR completes,
the host enables data output mode to read the unique ID.
Sixteen copies of the unique ID data are store in the device. Each copy is 32 bytes. The first 16 bytes of a 32-byte copy are unique ID
data, and the second 16 bytes are the complement of the first 16 bytes of FFh, then that copy of the unique ID data is correct. In the
event that a non-FFh result is returned, the host can repeat the XOR operation on a subsequent copy of the unique ID data. Random
Data Output (05h-E0h) can be used to change the location of data output.
Command
EDh
Address
00h
Cycle type
I/O[7:0]
R/B#
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
…
…
U01
U11
U00
U10
tRR
tR
tWB
Read Unique ID Operation
Elite Semiconductor Memory Technology Inc.
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Revision: 0.1 43/50
ESMT
(Preliminary)
F59D4G81KA (2R)
Page Copy
By using Page Copy, data in a page can be copied to another page after the data has been read out. When the block address changes
(increments) this sequenced has to be started from the beginning.
tR
tDCBSYW2
R/B#
I/Ox
Address
5Cycles
Address
5Cycles
00h
Data Input 15h
Data output 8Ch
30h
Col. Add. 1,2 & Row Add. 1,2,3
Col. Add. 1,2 & Row Add. 1,2,3
Destination Address (Page-B)
1
Source Address (Page-A)
(Data
output)
(Data
input)
Data cache
Page Buffer
Page A
Page A
Page A
Page A
(I)
(II)
(IV)
(III)
I. Data for Page A is transferred to the Data Cache
II. Data for Page A is read out
III. Copy Page address B is input and if the data needs to be changed, changed data is input
IV. Data Cache for Page B is transferred to the Page Buffer
I/Ox
tDCBSYW2
tDCBSYR2
Address
5Cycles
Address
5Cycles
3Ah
Data Input
15h
00h
Data output
8Ch
Col. Add. 1,2 & Row Add. 1,2,3
Col. Add. 1,2 & Row Add. 1,2,3
Destination Address (Page-D)
1
2
Source Address (Page-C)
(Data
input)
(Data
output)
Page B
Page A
Page C
Page B
Page D
Page C
Page D
Page C
Page A
Page C
(VI)
(V)
(VII)
(VIII)
V. Data for Page C is transferred to Data Cache while the data of Page B is being programmed
VI. After the Ready state, Data for Page C is output from the Data Cache
VII. Copy Page address D is input and if the data needs to be changed, changed data is input
VIII. After programming of page B is completed, Data Cache for Page D is transferred to the Page Buffer
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
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ESMT
(Preliminary)
F59D4G81KA (2R)
tDCBSYR2
tDCBSYR2
I/Ox
Address
5Cycles
Address
5Cycles
3Ah
00h
00h
3Ah
Data output
Col. Add. 1,2 & Row Add. 1,2,3
Col. Add. 1,2 & Row Add. 1,2,3
2
3
Source Address (Page-Y)
Source Address (Page-E)
(Data output)
Page E
Page D
Page E
Page D
Page X
Page X
Page C
Page C
Page Y
Page Y
(X)
(XI)
(XII)
IX. By the 15h command, the data in the Page Buffer is programmed to Page D. Data for Page E is transferred
to the Data cache
X. Data for Page E is read out
XI. Data Cache for Page X is transferred to the Page Buffer
XII.The data in the Page Buffer is programmed to Page X. Data for Page Y is transferred to the Data Cache
R/B#
I/Ox
tLPROG (*1)
Address
5Cycles
70h
I/O0
Data output
8Ch
Data Input
10h
“0”
Pass
“1”
Fail
Col. Add. 1,2 & Row Add. 1,2,3
Destination Address (Page-Z)
3
(Data output)
(Data
input)
Page X
Page X
Page Z
Page X
Page Z
Page Y
Page Y
Page Y
(XIII)
(XIV)
(XV)
XIII. After the Ready state, Data for Page Y is output from the Data Cache
XIV. Copy Page address Z is input and if the data needs to be changed, changed data is input
XV. By issuing the 10h command, the data in the Page Buffer is programmed to Page Z
(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the tLPROG here will be expected as the following,
tLPROG = tPROG of the last page + tPROG of the previous page - ( command input cycle + address input cycle + data output/input cycle time of the last page)
NOTE)
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command,
and change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
Make sure WP is held to High level when Page Copy operation is performed.
Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 45/50
ESMT
(Preliminary)
F59D4G81KA (2R)
PACKING DIMENSION
48-LEAD TSOP(I) ( 12x20 mm )
Dimension in mm
Min Norm Max
------- ------- 1.20 ------- ------- 0.047
0.05 ------- 0.15 0.006 ------- 0.002
Dimension in inch
Min Norm Max
Dimension in mm
Dimension in inch
Min Norm Max
0.787 BSC
Symbol
Symbol
Min Norm Max
20.00 BSC
18.40 BSC
12.00 BSC
0.50 BSC
A
A 1
A 2
b
b1
c
D
D 1
E
e
L
0.724 BSC
0.472 BSC
0.020 BSC
0.95 1.00
0.17 0.22
0.17 0.20
1.05 0.037 0.039 0.041
0.27 0.007 0.009 0.011
0.23 0.007 0.008 0.009
0.50 0.60
0O
-------
0.70 0.020 0.024 0.028
8O 0O 8O
-------
0.10 ------- 0.21 0.004 ------- 0.008
0.10 ------- 0.16 0.004 ------- 0.006
θ
c1
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ESMT
(Preliminary)
F59D4G81KA (2R)
PACKING DIMENSIONS
63-BALL
NAND Flash ( 9x11 mm )
E
Pin #1
D
A2
A
A1
Seating plane
C
ccc C
Detail A
Detail A
e
e
Solder ball
e
e
b
D1
Detail B
Pin #1
Index
E1
Detail B
Dimension in mm
Norm
Dimension in inch
Norm
Symbol
Min
Max
1.00
0.35
Min
Max
0.039
0.014
A
A1
A2
Φb
D
0.25
0.010
0.60 BSC
0.024 BSC
0.40
10.90
8.90
0.50
11.10
9.10
0.016
0.429
0.350
0.020
0.437
0.358
11.00
9.00
0.433
0.354
E
D1
E1
e
8.80 BSC
7.20 BSC
0.8 BSC
0.346 BSC
0.283 BSC
0.031 BSC
ccc
0.10
0.004
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
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ESMT
(Preliminary)
F59D4G81KA (2R)
PACKING DIMENSIONS
67-BALL Flash ( 6.5x8 mm )
D
Pin# 1
index
Seating plane
Detail "A"
"A"
D1
e
Φ
b
Pin# 1
index
Detail "B"
"B"
Symbol
Dimension in mm
Dimension in inch
Min
Norm
Max
1.00
0.32
0.71
0.40
6.60
8.10
Min
Norm
Max
A
A1
A2
Φb
D
0.039
0.013
0.028
0.016
0.260
0.319
0.22
0.61
0.30
6.40
7.90
0.27
0.66
0.35
6.50
8.00
0.009
0.024
0.012
0.252
0.311
0.011
0.026
0.014
0.256
0.315
E
D1
E1
e
5.60 BSC
7.20 BSC
0.80 BSC
0.220 BSC
0.283 BSC
0.031 BSC
Controlling dimension : Millimeter.
(Revision date : Jun 29 2014)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1 48/50
ESMT
(Preliminary)
F59D4G81KA (2R)
Revision History
Revision
Date
Description
0.1
2020.01.07
Original
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2020
Revision: 0.1
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ESMT
(Preliminary)
F59D4G81KA (2R)
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
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Revision: 0.1 50/50
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