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F59L2G81KA-25TG2N [ESMT]

2 Gbit (256M x 8) 3.3V NAND Flash Memory;
F59L2G81KA-25TG2N
型号： F59L2G81KA-25TG2N
厂家： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.    ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
描述：

2 Gbit (256M x 8) 3.3V NAND Flash Memory
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Flash  
2 Gbit (256M x 8)  
3.3V NAND Flash Memory  
FEATURES  
Voltage Supply  
1bit/cell  
­
VCC: 3.3V (2.7 V ~ 3.6V)  
Command/Address/Data Multiplexed DQ Port  
Hardware Data Protection  
Organization  
­
­
­
­
Page Size: (2K + 128) bytes  
Data Register: (2K + 128) bytes  
Block Size: 64Pages = (128K + 8K) bytes  
Number of Block per Die (LUN)= 2048  
­
Program/Erase Lockout During Power Transitions  
Reliable CMOS Floating Gate Technology  
­
­
­
ECC Requirement: 8bit / 512Byte  
Endurance: 50K-P/E Cycle Times  
Data Retention: 10year  
Automatic Program and Erase  
Command Register Operation  
Number of partial program cycles in the same page (NOP) : 4  
Automatic Page 0 Read at Power-Up Option  
­
­
Page Program: (2K + 128) bytes  
Block Erase: (128K + 8K) bytes  
Page Read Operation  
­
­
Write Cycle Time  
­
­
Boot from NAND support  
Random Read: 25us (Max.)  
Read Cycle: 25ns  
­
Automatic Memory Download  
Cache Program Operation for High Performance Program  
Cache Read Operation  
Copy-Back Operation  
Two-Plane Operation  
EDO mode  
Page Program Time: 400us (Typ.)  
700us (Max.)  
Block Erase Time: 3 ms (Typ.)  
10ms (Max.)  
­
Page copy  
ORDERING INFORMATION  
Product ID  
Speed  
25 ns  
25 ns  
Package  
48 pin TSOPI  
63 ball BGA  
67 ball BGA  
Comments  
Pb-free  
F59L2G81KA -25TG2N  
F59L2G81KA -25BG2N  
Pb-free  
F59L2G81KA -25BCG2N 25 ns  
Pb-free  
GENERAL DESCRIPTION  
The device has two 2176-byte static registers which allow program and read data to be transferred between the register  
and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block unit (128Kbytes  
+ 8Kbytes).  
The device is a memory device which utilizes the I/O pins for both address and data input/output as well as command  
inputs. The Erase and Program operations are automatically executed making the device most suitable for applications  
such as solid state file storage, voice recording, image file memory for still cameras and other systems which require high  
density non-volatile memory data storage.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 1/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
PIN CONFIGURATION (TOP VIEW)  
(TSOPI 48L, 12mm X 20mm Body, 0.5mm Pin Pitch)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 2/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
BALL CONFIGURATION (x8) (TOP VIEW)  
(BGA 63 BALL, 9mm X 11mm Body, 0.8 Ball Pitch)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2  
3/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
BALL CONFIGURATION (TOP VIEW)  
(BGA 67 Ball, 6.5mmx8mmx1.0mm Body, 0.8mm Ball Pitch)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 4/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
PIN/ BALL NAMES  
Pin/ Ball Name  
Type  
Function  
VCC  
VSS  
Supply  
Supply  
NAND Power Supply  
Ground  
Data inputs/outputs: The I/O0 to 7 pins are used as a port for transferring address, command  
and input/output data to and from the device.  
I/O0 to I/O7  
ALE  
Input/output  
Input  
Address latch enable: The ALE signal is used to control loading address information into the  
internal address register. Address information is latched into the address register from the I/O  
port on the rising edge of WE# while ALE is High.  
Command latch enable: The CLE input signal is used to control loading of the operation mode  
command into the internal command register. The command is latched into the command  
register from the I/O port on the rising edge of the WE# signal while CLE is High.  
CLE  
CE#  
Input  
Input  
Chip enable: The device goes into a low-power Standby mode when CE# goes High during the  
device is in Ready state. The CE# signal is ignored when device is in Busy state (R/B# = L),  
such as during a Program or Erase or Read operation, and will not enter Standby mode even if  
the CE# input goes High.  
Read enable: The RE# signal controls serial data output. Data is available tREA after the falling  
edge of RE#. The internal column address counter is also incremented (Address = Address +  
l) on this falling edge.  
RE#  
Input  
Input  
WE#  
Write enable: The WE# signal is used to control the acquisition of data from the I/O port.  
Write protect: The WP# signal is used to protect the device from accidental programming or  
erasing. The internal voltage regulator is reset when WP# is Low. This signal is usually used  
for protecting the data during the power-on/off sequence when input signals are invalid.  
WP#  
R/B#  
Input  
Ready/busy: The R/B# output signal is used to indicate the operating condition of the device.  
The R/B# signal is in Busy state ( R/B# = L) during the Program, Erase and Read operations  
and will return to Ready state (R/B# = H) after completion of the operation. The output buffer  
for this signal is an open drain and has to be pulled-up to VCC with an appropriate resister. If  
R/B# signal is not pulled-up to VCC (“Open” state), device operation can not guarantee.  
Output  
-
NC  
No connect: NCs are not internally connected. They can be driven or left unconnected.  
NOTE:  
1. See Device and Array Organization for detailed signal connections.  
2. If See Asynchronous Interface Bus Operation for detailed asynchronous interface signal descriptions.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 5/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Block Diagram  
Vcc Vss  
Status register  
Address register  
Command register  
Column buffer  
Column decoder  
Data register  
Sense amp  
I/O0  
to  
I/O  
Control circuit  
I/O7  
CE#  
CLE  
ALE  
WE#  
RE#  
Memory cell array  
Control circuit  
Logic control  
WP#  
R/B#  
HV generator  
R/B#  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2  
6/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Definitions and Abbreviations  
LSB  
Acronym for the least significant bit.  
Address  
The address is comprised of a column address 2 cycles and a row address with 3 cycles. The row address identifies the  
page, block, and LUN to be accessed. The column address identifies the byte within a page to access.  
Column  
The byte location within the page register.  
Row  
Refer to the block and page to be accessed.  
Page  
The smallest addressable unit for the Read and the Program operations.  
Block  
Consists of multiple pages and is the smallest unit for the Erase operation.  
Page register  
Register used to transfer data to and from the Flash Array.  
Cache register  
Register used to transfer data to and from the Host.  
Defect area  
The defect area is where the factory defects are marked by the manufacturer. It is a reference for initial invalid block(s).  
Device  
The packaged NAND unit. A device may contain more than a target.  
LUN (Logical Unit Number)  
The minimum unit that can independently execute commands and report status. There are one or more LUNs per CE#.  
Target  
An independent NAND Flash component with its own CE# signal.  
SR[x] (Status Read)  
SR refers to the status register contained within a particular LUN. SR[x] refers to bit x in the status register for the  
associated LUN.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 7/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Absolute Maximum Rating  
Parameter  
Symbol  
VCC  
Rating  
Unit  
V
-0.6 to +4.6  
-0.6 to +4.6  
Voltage on any pin relative to VSS  
Short Circuit Current  
VIN  
VI/O  
-0.6 to Vcc+0.3(<4.6V)  
5
IOS  
mA  
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be  
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions  
for extended periods may affect reliability.  
Operating Temperature Condition  
Parameter  
Operating Temperature Range for indurtrial  
Soldering Temperature (10s)  
Storage Temperature  
Symbol  
TOPER  
Rating  
0 to +70  
260  
Unit  
°C  
TSOLDER  
TSTG  
°C  
-55 to +125  
°C  
NOTE:  
1.  
2.  
Operating Temperature TOPER is the case surface temperature on the center/top side of the NAND.  
Operating Temperature Range specifies the temperatures where all NAND specifications will be supported. During operation, the  
NAND case temperature must be maintained between the range specified in the table under all operating conditions.  
Recommended Operating Conditions  
(Voltage reference to GND, TA= 0 to 70°C)  
Parameter  
Supply Voltage  
Symbol  
VCC  
Min  
2.7  
Typ.  
Max  
3.6  
Unit  
3.3  
V
High Level Input Voltage  
Low Level Input Voltage  
Ground Voltage  
VIH  
0.8 VCC  
-0.3  
-
-
VCC + 0.3  
0.2 VCC  
0
VIL  
VSS  
0
0
V
Valid Blocks  
Parameter  
Symbol  
Min  
Typ.  
Max  
Unit  
F59L2G81KA (2N)  
NVB  
2,008  
-
2,048  
Block  
NOTE:  
1.  
The device may include initial invalid blocks when first shipped. The number of valid blocks is presented as first shipped. Invalid  
blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation.  
Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial  
invalid blocks.  
2.  
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 8/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
DC Operation Characteristics  
(Recommended operating conditions otherwise noted)  
Parameter  
Symbol  
Test Conditions  
Min  
Typ.  
Max  
Unit  
Page Read  
ICC1  
CE#= VIL, Iout= 0, tRC= tRC(min)  
-
15  
with Serial Access  
Operating  
Current  
30  
Program  
Erase  
ICC2  
ICC3  
-
-
-
15  
15  
-
mA  
-
-
Stand-by Current (TTL)  
Stand-by Current (CMOS)  
Input Leakage Current  
Output Leakage Current  
Output High Voltage Level  
Output Low Voltage Level  
Output Low Current (R/B#)  
NOTE :  
ISB1  
CE#= VIH, WP#= 0V/VCC  
CE#= VCC-0.2, WP#= 0V/VCC  
VIN= 0 to VCC (max)  
VOUT= 0 to VCC (max)  
IOH= -400uA  
1
50  
ISB2  
-
10  
-
ILI  
-
+/-10  
+/-10  
-
ILO  
-
-
uA  
VOH  
2.4  
-
-
VOL  
IOL= 2.1mA  
-
0.4  
-
IOL (R/B#)  
mA  
VOL= 0.4V  
8
10  
1.  
2.  
3.  
Typical value are measured at VCC= 3.3V, TA= 25°C. Not 100% tested.  
ICC1 and ICC2 are without data cache.  
ICC1, ICC2, ICC3, and ISB2 are the values of one chip.  
Capacitance  
(TA= 25°C, VCC= 3.3V, f= 1.0MHz)  
Symbol  
CDQ  
Test Condition  
VOUT=0V  
Min  
Max  
Unit  
pF  
Item  
Input/Output Capacitance  
Input Capacitance  
-
-
8
8
CIN  
VIN=0V  
pF  
NOTE: Capacitance is periodically sampled and not 100% tested.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 9/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Ready/Busy  
R/B# represents the status of the selected target. R/B# goes busy when only a single LUN is busy while rest of LUNs on the same  
target are idle.  
Rp  
ibusy  
VccQ  
Ready VccQ  
R/B#  
Open drain output  
VOH  
C
L
VOL  
Busy  
tf  
tf  
VssQ  
Device  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2  
10/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Write Protect  
When WP# is enabled, Flash array is blocked from any program and erase operations. This signal shall only transitioned when a target  
is idle. The host shall be allowed to issue a new command after tWW once WP# is enabled. Figures below describes the tWW timing  
requirement, shown with the start of a Program command and the start of a Erase command.  
1. Enable Mode  
WE#  
DQ[7:0]  
WP#  
80h  
10h  
min.100ns  
tWW  
2. Disable Mode  
WE#  
DQ[7:0]  
WP#  
80h  
10h  
min.100ns  
tWW  
Write Protect timing requirements of the Program operation  
1. Enable Mode  
WE#  
60h  
D0h  
DQ[7:0]  
WP#  
min.100ns  
tWW  
2. Disable Mode  
WE#  
DQ[7:0]  
WP#  
60h  
D0h  
tWW  
min.100ns  
Write Protect timing requirements of the Erase operation  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 11/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Memory Organization  
Addressing  
There are two address types used: the column address and the row address. The column address is used to access bytes within a  
page, i.e. the column address is the byte offset into the page. The row address is used to address pages, blocks, and LUNs (in x8  
device, there is only one LUN).  
When both the column and row addresses are required to be issued, the column address is always issued first in one or more 8-bit  
address cycles. The row addresses follow in one or more 8-bit address cycles. There are some functions that may require only row  
addresses, such as Block Erase. In this case the column addresses shall not be issued.  
For both column and row addresses, the first address cycle always contains the least significant bits and the last cycle always contains  
the most significant bits. If there are bits in the most significant cycles of the column and row addresses that are not used, then they are  
required to be cleared to zero.  
1 Block = 64 Pages  
2048 Blocks  
8 bits  
128 Byte  
2048 Byte  
2176 Byte  
I/O0 ~ I/O7  
Page Register  
Array Address  
I/O0  
A0  
I/O1  
A1  
I/O2  
A2  
I/O3  
A3  
I/O4  
I/O5  
A5  
I/O6  
A5  
I/O7  
A7  
Address  
1st cycle  
2nd cycle  
3rd cycle  
4th cycle  
5th cycle  
NOTE:  
A4  
*L  
Column Address  
Column Address  
Row Address  
Row Address  
Row Address  
A8  
A9  
A10  
A14  
A22  
*L  
A11  
A15  
A23  
*L  
*L  
*L  
*L  
A12  
A20  
A28  
A13  
A21  
*L  
A16  
A24  
*L  
A17  
A25  
*L  
A18  
A26  
*L  
A19  
A27  
*L  
1. Column address: Starting Address of the Register.  
2. *L must be set to ‘Low’  
3. The device ignores any additional input of address cycles than required.  
4. A18 is for Plane Address setting, A12~A17 are for Page Address, A19~A28 are for Block Address.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 12/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Addressing for Program Operation  
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most  
significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB  
among the pages to be programmed. Therefore, LSB page doesn’t need to be page 0.  
Page 63  
Page 31  
Page 63  
Page 31  
(64)  
(32)  
(64)  
(1)  
Page 2  
Page 1  
Page 0  
Page 2  
Page 1  
Page 0  
(3)  
(2)  
(1)  
(3)  
(32)  
(2)  
Data register  
Data register  
From the LSB page to MSB page  
Ex.) Random page program (Prohibition)  
DATA IN: Data (1) → Data (64)  
DATA IN: Data (1) → Data (64)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 13/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Factory Defect Mapping and Error Management  
Mask Out Initial Invalid Block(s)  
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed. The information  
regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same  
quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the  
performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system  
design must be able to mask out the initial invalid block(s) via address mapping.  
Identifying Initial Invalid Block(s) and Block Replacement Management  
If a block is defective, the manufacturer shall mark as defective by setting the Defective Block Marking, as shown in figure, of the first or  
second page of the defective block to a value of non-FFh. The Defective Block Marking is located on the first byte of spare data area in  
the pages within a block.  
The host shall not erase or program blocks marked as defective by the manufacturer, and any attempt to do so yields indeterminate  
results. Figure below outlines the flow chart how to create an initial invalid block table. It should be performed by the host to create the  
initial invalid block table prior to performing any erase or programming operations on the target. All pages in non-defective blocks are  
read FFh with ECC enabled on the controller. A defective block is indicated by the majority of bits being read non-FFh in the Defective  
Block Marking location of either the first page or second page of the block. The host shall check the Defective Block Marking location of  
both the first and second page of each block to verify the block is valid prior to any erase or program operations on that block.  
Over the lifetime use of a NAND device, the Defective Block Marking of defective blocks may encounter read disturbs that cause bit  
changes. The initial defect marks by the manufacturer may change value over the lifetime of the device, and are expected to be read  
by the host and used to create a bad block table during initial use of the part.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 14/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Start  
Set Block Address=0  
Increase  
Block  
Address  
Create Initial  
Invalid Block  
Table  
n
Check “FFh” at the 1st Byte column address in  
the spare area of the 1st and 2nd page in the  
block.  
Check  
”FFh”?  
yes  
n
Last Block?  
yes  
End  
Algorithm for Bad Block Scanning  
For (i=0; i<Num_of_LUs; i++)  
For (j=0; j<Blocks_Per_LU; j++)  
{
{
Defect_Block_Found=False;  
Read_Page(lu=i, block=j, page=0);  
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;  
Read_Page(lu=i, block=j, page=1);  
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;  
If (Defect_Block_Found) Mark_Block_as_Defective(lu=i, block=j);  
}
}
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 15/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Errors in Write or Read Operation  
Within its lifetime, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.  
The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after  
erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of  
the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and  
reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve  
the efficiency of memory space, it is recommended that the read or verification failure due to bits error (less than 8 bits / 512 byte) be  
reclaimed by ECC without any block replacement. The additional block failure rate does not include those reclaimed blocks.  
Failure Mode  
Erase failure  
Detection and Countermeasure Sequence  
Read Status after Erase Block Replacement  
Write  
Read  
Program failure  
Up to 8 bits failure  
Read Status after Program Block Replacement  
Verify ECC ECC Correction  
NOTE: Error Correcting Code RS Code or BCH Code etc.  
Example: 8bit correction / 512Byte  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 16/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Start  
Write  
80h  
No  
I/O6=1? or  
R/B#=1?  
Write  
Address  
Yes  
Write  
Data  
No  
I/O0=0?  
Program Error  
Yes  
Write  
10h  
Mark Bad Block  
& Replace Block  
Program  
Completed  
Read Status  
Register  
Program Flow Chart  
Start  
No  
I/O6=1?  
or  
Write  
60h  
R/B#=1?  
Yes  
Write Block  
Address  
No  
I/O0=0?  
Erase Error  
Write  
D0h  
Yes  
Read  
Status  
Register  
Erase  
Completed  
Mark Bad Block  
Erase Flow Chart  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2  
17/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Start  
Write  
00h  
ECC Generation  
Yes  
Yes  
Write  
Address  
No  
Verify  
ECC  
Reclaim the Error  
Write  
30h  
Read  
Data  
Page Read  
Completed  
Read Flow Chart  
Block A  
1st  
~
(n-1)th  
n th  
An error occurs.  
page  
1
Block B  
Buffer memory of the  
controller  
2
* Step 1  
1st  
~
(n-1)th  
When an error happens in the nth page of the Block 'A' during erase or program  
operation.  
* Step 2  
Copy the data in the 1st ~ (n-1)th page to the same location of another free  
block. (Block 'B')  
An error occurs.  
n th  
* Step 3  
Then, copy the nth page data of the Block 'A' in the buffer memory to the nth  
page of the Block 'B'  
page  
* Step 4  
Do not erase or program to Block 'A' by creating an 'invalid block' table or other  
appropriate scheme.  
Block Replacement  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2  
18/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Function Description  
Discovery and Initialization  
The device is designed to offer protection from any involuntary program/erase during power transitions. An internal voltage detector  
disables all functions whenever VCC is below about 2.3V. Max busy time is 5ms after Power-On Reset. During busy time of resetting,  
the acceptable command is the Read Status (70h).  
WP# provides hardware protection and is recommended to be kept at VIL during power up and power down. The two step command  
sequence for program/erase provides additional protection. Figure below defines the Initialization behavior and timings.  
Data Protection and Power On Sequence  
The timing sequence shown in the figure below is necessary for the power-on/off sequence.  
The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the  
initialization the device R/B# signal indicates the Busy state as shown in the figure below. In this time period, the acceptable commands  
are 70h.  
The WP# signal is useful for protecting against data corruption at power on/off.  
AC Waveforms for Power Transition  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Mode Selection  
SDR  
CLE  
ALE  
CE#  
WE#  
RE#  
WP#  
Mode  
H
L
H
L
L
H
X
Command Input  
Read Mode  
Write Mode  
L
H
L
L
L
L
L
L
L
L
H
H
H
H
X
H
H
H
X
Address Input (5 clock)  
Command Input  
H
L
Address Input (5 clock)  
Data Input  
L
H
Data Output  
X
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X
X
X
X
During Read (Busy)  
During Program (Busy)  
During Erase (Busy)  
Write Protect  
X
H
H
X
X
X
X
X(1)  
L
(2)  
X
0V/VCC  
Stand-by  
NOTE :  
1. X can be VIL or VIH.  
2. WP# should be biased to CMOS high or CMOS low for standby.  
AC Test Condition  
(TA= 0 to 70°C, VCC= 2.7V ~ 3.6V)  
Parameter  
Single-ended signaling  
Input Pulse  
0 to VCC  
5ns  
Input Rise and Fall Times  
Input and Output Timing Levels  
Output Load*  
VCC/2  
CL(50pF) and 1TTL  
NOTE: Refer to Ready/Busy, R/B# output’s Busy to Ready time is decided by the pull-up resistor (Rp) tied to the R/B# pin.  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Read / Program / Erase Characteristics  
(TA= 0 to 70°C, VCC= 2.7V ~ 3.6V)  
Parameter  
Symbol  
tR  
Min  
Typ  
Max  
25  
Unit  
us  
Data Transfer from Cell to Register  
Program Time  
-
-
-
400  
800  
3
tPROG  
700  
1400  
750  
4
us  
Last Page Program Time  
tLPROG  
tCBSY  
us  
Dummy Busy Time for Cache Operation  
Number of Partial Program Cycles in the Same Page  
Block Erase Time  
-
-
-
-
-
-
us  
NOP  
-
cycle  
ms  
us  
tBERS  
3
10  
Dummy Busy Time for Two-Plane Page Program (following 11h)  
tDBSY  
0.5  
-
1
tDCBSYW1  
tDCBSYW2  
10  
us  
Data Cache Busy Time in Write Cache (following11h )  
Data Cache Busy Time in Write Cache (following 15h)  
NOTE :  
-
700  
us  
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and  
25°C temperature.  
2. tCBSY max. time depends on timing between internal program completion and data-in.  
3. tDCBSYW2 depends on the timing between internal programming time and data in time.  
4. tLPROG=tPROG(last page) + tPROG(last-1 page) – Command load time(last page) – Address load time(last page)-Data load time(last  
page)  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
AC Timing Characteristics  
SDR (VCC = 2.7~3.6V)  
Parameter  
Symbol  
Min  
12  
5
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
ns  
ns  
ns  
ns  
ns  
ns  
(1)  
CLE Setup Time  
tCLS  
-
-
CLE Hold Time  
tCLH  
(1)  
CE# Setup Time  
tCS  
20  
5
-
CE# Hold Time  
tCH  
tWP  
-
WE# Pulse Width  
12  
12  
5
-
(1)  
ALE Setup Time  
tALS  
-
ALE Hold Time  
tALH  
-
(1)  
Data Setup Time  
tDS  
12  
5
-
Data Hold Time  
tDH  
tWC  
tWH  
-
Write Cycle Time  
25  
10  
70  
-
-
WE# High Hold Time  
Address to Data Loading Time  
Data Transfer from Cell to Register  
ALE to RE# Delay  
-
(2)  
tADL  
-
tR  
25  
-
tAR  
tCLR  
tRR  
tRW  
tRP  
tWB  
10  
10  
20  
20  
12  
-
CLE to RE# Delay  
-
Ready to RE# Low  
-
Ready to WE# Falling Edge  
RE# Pulse Width  
-
WE# High to Busy  
100  
WP# Low to WE# Low (disable mode)  
WP# High to WE# Low (enable mode)  
Read Cycle Time  
tWW  
100  
-
ns  
tRC  
tCR  
25  
9
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE# Low to RE# Low  
RE# Access Time  
tREA  
tCEA  
tRHZ  
tCHZ  
tCLHZ  
tRHOH  
tRLOH  
tCOH  
tREH  
tIR  
-
20  
25  
100  
30  
30  
-
CE# Access Time  
-
RE# High to Output Hi-Z  
CE# High to Output Hi-Z  
CLE High to Output Hi-Z  
RE# High to Output Hold  
RE# Low to Output Hold  
CE# High to Output Hold  
RE# High Hold Time  
Output Hi-Z to RE# Low  
RE# High to WE# Low  
WE# High to RE# Low (Read Status)  
-
-
-
15  
5
15  
10  
0
-
-
-
-
tRHW  
tWHR1  
100  
60  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
tWHR2  
WE# High to RE# Low (Column Address Change in Read)  
60  
-
-
5
ns  
us  
us  
us  
us  
us  
us  
Ready  
Read  
-
5
Device Resetting  
Time during…  
tRST  
Program  
-
10  
500  
30  
30  
Erase  
-
Data Cache Busy in Read Cache (following 31h and 3Fh)  
Data Cache Busy in Page Copy (following 3Ah)  
NOTE :  
tDCBSYR1  
tDCBSYR2  
1. The transition of the corresponding control pins must occur only once while WE# is held low.  
2. tADL is the time from the WE rising edge of final address cycle to the WE# rising edge of first data cycle.  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
General Timing  
CE bar = CE#  
WE bar = WE#  
RE bar = RE#  
R/ B bar = R/B#  
Command/Address/Data Latch Timing  
CLE  
ALE  
CE#  
RE#  
Setup Time  
Hold Time  
WE#  
tDH  
tDS  
I/O  
: VIH or VIL  
Command/Address/Data Latch Timing  
Command Input Cycle  
tCLS  
tCS  
tCLH  
tCH  
CLE  
CE#  
WE#  
tWP  
tALS  
tALH  
ALE  
I/O  
tDS  
tDH  
: VIH or VIL  
Command Input Cycle Timing  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Address Input Cycle  
tCLH  
tCLS  
CLE  
CE#  
WE#  
ALE  
I/Ox  
tCS  
tCH  
tWC  
tWC  
tWC  
tWC  
tWP  
tWP  
tWP  
tWP  
tWP  
tWH  
tWH  
tALH  
tWH  
tALH  
tWH  
tALH  
tALH  
tALH  
tALS  
tALS  
tALS  
tALS  
tALS  
t
tDS  
tDH  
DS tDH  
tDH  
tDS  
tDS t  
DH  
tDS  
tDH  
Col.Ad  
Row.A  
Col.Ad  
Row.A  
Row.A  
Address Input Cycle Timing  
Data Input Cycle  
tCLS  
tCLH  
CLE  
CE#  
tCH  
tCS  
tCS  
tCH  
tALS  
tALH  
tWC  
ALE  
tWP  
tWH  
tWP  
tWP  
WE#  
tDH  
tDH  
tDS  
tDS  
tDS tDH  
I/O  
DIN1  
DINF  
DIN0  
NOTE: DINF means the Final Data Input.  
Data Input Cycle Timing  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Data Output Cycle  
tRC  
tCR  
CE#  
RE#  
tCHZ  
tRHZ  
tRP  
tREH  
tRHZ  
tRHOH  
tRP  
tRP  
tRHZ  
tREA  
tCEA  
tREA  
tRHOH  
tREA  
tRHOH  
tCEA  
I/O  
tRR  
R/B#  
: VIH or VIL  
Data Output Cycle Timing  
Basic Data Output  
CLE  
tCLH  
tCH  
tCLS2  
tCS2  
tCR  
CE#  
WE#  
ALE  
tCHZ  
tCLHZ  
tALH  
tREA  
tRC  
tRHZ  
tRHOH  
tRP  
tREH  
tRP  
tRP  
RE#  
I/O  
tDH  
tDS  
tRLOH  
tREA  
tREA  
tRLOH  
Command  
Dout  
tRHOH  
Dout  
Comma  
tRP  
R/B#  
Basic Data Output Timing  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Read ID  
tCLS  
tCLS  
tCS  
CLE  
CE#  
tCR  
tCH  
tCS  
tWHR1  
tCH  
WE#  
tALH  
tALS  
tALH  
tAR  
ALE  
RE#  
tDH  
tREA  
tREA  
tREA  
tREA  
tREA  
tDS  
90h  
I/O  
00h  
Address  
Device code  
Maker code  
Read ID Operation Timing  
Status Read Cycle  
tCLR  
tCLS  
CLE  
tCLH  
tCS  
tCR  
CE#  
tCHZ  
tWP  
tCH  
tCEA  
WE#  
tWHC  
tRHZ  
tWHR1  
RE#  
tIR  
tDS tDH  
tRHOH  
tREA  
Status  
output  
I/O  
70h  
R/B#  
: VIH or VIL  
Status Read Cycle Timing  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Page Read Operation  
tCLR  
CLE  
CE#  
tCLS  
tCLS  
tCLH  
tCH  
tCLH  
tCH  
tCS  
tCS  
tWC  
WE#  
tALH  
tALS  
tALH  
tALS  
ALE  
RE#  
tR  
tRC  
tWB  
tCEA  
tDS tDH  
00h  
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH  
CA  
RA  
Column Address  
tDS tDH  
30h  
tRR  
tREA  
Dout  
N+1  
Dout  
N
I/O  
CA  
RA  
RA  
Data out from  
Col. Add. N  
R/B#  
Page Read Operation Timing  
Page Program Operation  
CLE  
CE#  
tWC  
tWC  
tWC  
WE#  
tADL  
tPROG  
tWB  
tWHR  
ALE  
RE#  
Row  
Add3  
Row  
Add2  
Col  
Add2  
Row  
Add1  
Col  
Add1  
Din  
N
Din  
M
80h  
70h  
IO0  
10h  
I/O
X  
Program  
Command  
1 up to m Byte  
Serial input  
Read Status  
Command  
Serial data  
Input Command  
Column  
Address  
Row Address  
R/B#  
I/O0=0 Successful Program  
I/O0=1 Error in Program  
Page Program Operation  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Command Description and Device Operation  
Command Sets  
Function  
1st Cycle  
2nd Cycle  
Acceptable Command during Busy  
Read  
00h  
00h  
30h  
35h  
-
Read for Copy-Back  
Read ID  
90h  
Reset  
FFh  
-
O
Page Program  
Copy-Back Program  
Block Erase  
80h  
10h  
10h  
D0h  
-
85h  
60h  
Random Data Input (1)  
85h  
Random Data Output (1)  
05h  
E0h  
-
Read Status  
70h  
O
O
Read Status2  
F1h  
-
Cache Program  
80h  
15h  
-
Cache Read  
31h  
Read Start for Last Page Cache Read  
Two-Plane Page Read  
3Fh  
-
60h-60h  
60h-60h  
60h-60h  
00h-05h  
80h-11h  
85h-11h  
60h-60h  
80h-11h  
00h  
30h  
33h  
35h  
E0h  
81h-10h  
81h-10h  
D0h  
81h-15h  
3Ah  
15h  
10h  
Two-Plane Cache Read  
Two-Plane Read for Copy-Back  
Two-Plane Random Data Output(1)  
Two-Plane Page Program(2)  
Two-Plane Copy-Back Program(2)  
Two-Plane Block Erase  
Two-Plane Cache Program(2)  
Read for Page Copy with Data Out  
Auto Program with Data Cache during Page Copy  
Auto Program for last page during Page Copy  
8Ch  
8Ch  
NOTE:  
1. Random Data Input/Output can be executed in a page.  
2. The page address and block address shall be the same in Two-Plane operation.  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Operations  
Page Read Operation  
The Page Read function reads a page of data identified by row address for the selected LUN. The page of data is made available to be  
read from the page register starting at the specified column address. Figure below defines the Page Read behavior and timings.  
Reading beyond the end of a page results in indeterminate values being returned to the host.  
CE#  
CLE  
ALE  
WE#  
RE#  
．
．
．  
tR  
R/B#  
I/Ox  
Data Output( Serial Access)  
00h Address(5cycles) 30h  
Col.Add.1,2 & Row Add.1,2,3  
(00h Command)  
Data Field  
Spare Field  
Page Read Operation Timing  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
The Random Data Output function changes the column address from which data is being read in the page register for the selected LUN.  
The Random Data Output command shall only be issued when LUN is in a read idle condition. Figure below defines the Random Data  
Output behavior and timings. The host shall not read data from the LUN until tWHR(ns) after the second command (i.e. E0h) is written to  
the LUN.  
RE#  
．．．  
tR  
R/B#  
I/Ox  
Data Output( Serial Access)  
30h  
Address 5 cycles  
00h  
Col.Add.1,2 & Row Add.1,2,3  
1
Data Field  
Spare Field  
RE#  
．．．  
R/B#  
I/Ox  
Data Output( Serial Access)  
Col.2  
Col.1  
E0h  
05h  
Col.Add.1,2  
1
Data Field  
Spare Field  
Random Data Output in a Page Timing  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Cache Read Operation  
Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read command (00h-30h) is always  
issued before invoking Cache Read. After issuing the Cache Read command (31h), read data of the designated page (page N) are  
transferred from data registers to cache registers in a short time period of tDCBSYR1, and then data of the next page (page N+1) is  
transferred to data registers while the data in the cache registers are being read out. Host controller can retrieve continuous data and  
achieve fast read performance by iterating Cache Read operation. The Read Start for Last Page Cache Read command (3Fh) is used  
to complete data transfer from memory cells to data registers.  
CLE  
CE#  
WE#  
ALE  
RE#  
tR  
1
tDCBSYR1  
2
tDCBSYR1  
tDCBSYR1  
R/B#  
I/O  
7
5
3
4
6
00h  
31h  
31h  
3Fh  
2
30h  
0
3
1
Col.M  
Page N  
Column 0  
the Final Col.Dout  
Page  
Page Address  
Page Address N  
Page Address N  
Page N + 2  
Page N + 1  
Page N + 2  
Data Cache  
Page Buffer  
2
1
Page  
Page N + 1  
7
3
5
4
6
Cell  
Array  
Page  
Page N  
1
Page N + 2  
3
5
3Fh & #RE clock  
30h  
31h & #RE clock  
31h & #RE clock  
Cache Read Operation Timing  
If the 31th command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out  
from the Data Cache, and therefore the tR (Data transfer from memory cell to data register) will be reduced.  
1.  
2.  
3.  
4.  
Normal read. Data is transferred from Page N to Data cache through Page Buffer. During this time period, the device outputs  
Busy state for tR max.  
After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again.  
This data transfer takes tDCBSYR1 max and the completion of this time period can be deleted by Ready/Busy signal.  
Data of Page N + 1 is transferred to Page Buffer from cell while the data of Page N in Data Cache can be read out by RE# clock  
simultaneously.  
The 31h command makes data of Page N + 1 transfer to Data Cache from Page Buffer after the completion of the transfer from  
cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max.. This Busy period depends on the combination of the internal  
data transfer time from cell to Page Buffer and the serial data out time.  
5.  
6.  
Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data Cache can be read out by RE#  
clock simultaneously.  
The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the  
transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max.. This Busy period depends on the combination  
of the internal data transfer time from cell to Page Buffer and the serial data out time.  
7.  
Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command dose not transfer the data from the memory cell  
to Page Buffer, the device can accept new command input immediately after the completion of serial data out.  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Page Program Operation  
The device is programmed basically on a page basis, and each page shall be programmed only one before being erased. The  
addressing order shall be sequential within a block. The contents of the page register are programmed into the Flash array specified by  
row address. After tPROG program time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after  
10h.Figure below defines the Page Program behavior and timings. Writing beyond the end of the page register is undefined.  
R/B#  
tPROG  
“0”  
80h  
Address & Data Input  
10h  
70h  
I/O0  
Fail  
I/Ox  
Pass  
Col. Add. 1,2 & Row Add.1,2,3  
Data  
“1”  
Program & Read Status Operation Timing  
The device supports random data input in a page. The column address for the next data, which will be written, may be changed to the  
address using Random Data Input command (i.e. 85h). Random data input may be operated multiple times without limitation.  
R/B#  
tPROG  
“0”  
Address &  
Data Input  
Address &  
Data Input  
85h  
10h  
I/Ox  
70h  
I/O0  
“1”  
Fail  
80h  
Pass  
Col. Add. 1,2 & Row Add.1,2,3  
Data  
Col. Add. 1,2  
Data  
Random Data Input in a Page Timing  
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ESMT  
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F59L2G81KA (2N)  
Cache Program Operation  
The Cache Program function allows the host to write the next data for another page to the page register while a page of data to be  
programmed to the Flash array for the selected LUN. When command 15h is issued, R/B# returns high (i.e. ready) when a cache  
register is ready to be written after data in the cache register is transferred to a page register. However, when command 10h is issued  
for the final page, R/B# turns to high after outstanding program operation performed by previous Cache Program command and the  
program operation for the final page is completed. SR[0] is valid for this command after SR[5] transitions from zero to one until the next  
transition. SR[1] is valid for this command after SR[6] transitions from zero to one, and it is invalid after the first Cache Program  
command completion since there is no previous Cache Program operation. Cache Program operation shall work only within a block.  
Figure below defines the Cache Program behavior and timings. Note that tLPROG at the end of the caching operation may be longer than  
typical as this time also includes completing the programming operation for the previous page. Writing beyond the end of the page  
register is undefined.  
tCBSY  
tCBSY  
R/B#  
I/Ox  
Address & Data Input  
80h  
15h  
Address & Data Input  
80h  
15h  
Col. Add. 1,2 & Row Add.1,2,3  
Data  
Col. Add. 1,2 & Row Add.1,2,3  
Data  
1
Max.63 times repeatable  
R/B#  
I/Ox  
tLPROG  
80h  
10h  
70h  
Address & Data Input  
I/O0  
“0”  
Pass  
Col. Add. 1,2 & Row Add.1,2,3  
Data  
“1”  
Fail  
1
Last Page Input and Program  
Cache Program Operation Timing  
Block Erase Operation  
The Block Erase operation is done on a block basis. Only three cycles of row addresses are required for Block Erase operation and a  
page address within the cycles is ignored while plane and block address are valid. After Block Erase operation passes, all bits in the  
block shall be set to one. SR[0] is valid for this command after SR[6] transitions from zero to one (i.e. the selected LUN is ready) until  
the LUN goes in busy state by a next command. Figure below defines the Block Erase behavior and timings.  
R/B#  
I/Ox  
tBERS  
60h  
D0h  
70h  
Address Input  
Row Add.1,2,3  
I/O0  
“0”  
“1”  
Pass  
Fail  
Block Erase Operation Timing  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 34/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Copy-Back Program Operation  
The Copy-Back Program with Read for Copy-Back is configured to efficiently rewrite data stored in a page without data re-loading  
when no error within the page is found. Since the time consuming re-loading cycles are removed, copy-back operation helps the  
system performance improve. The benefit is especially obvious when a part of a block is updated and the rest of the block also needs  
to be copied to the newly assigned free block. The Copy-Back operation consists of Read for Copy-Back and Copy-Back Program. A  
host reads a page of data from a source page using Read for Copy-Back and copies read data back to a destination page on the same  
LUN by Copy-Back Program command. Copy-Back Program operation shall work only within the same plane. Figure below defines the  
Copy-Back Program behavior and timings.  
tPROG  
tR  
R/B#  
I/Ox  
Address  
5Cycles  
Address  
5Cycles  
00h  
10h  
70h  
35h  
Data output  
85h  
I/O0  
“0”  
Col. Add. 1,2 & Row Add. 1,2,3  
Source Address  
Col. Add. 1,2 & Row Add. 1,2,3  
Destination Address  
Pass  
“1”  
Fail  
NOTE: The LSB of page address shall be the same between source and destination pages. In other words, the page of even page  
address can’t be copied to the page of odd page address, and the page of odd page address can’t be copied to the page of even page  
address as well.  
Page Copy-Back Program Operation Timing  
After a host completes to read data from a page register, the host may modify data using Random Data Input command if required.  
Figure below defines Copy-Back Program with Random Data Input behavior and timings.  
tR  
R/B#  
I/Ox  
Address  
5Cycles  
Address  
5Cycles  
00h  
Data output  
35h  
85h  
Data Input  
Col. Add. 1,2 & Row Add. 1,2,3  
Source Address  
Col. Add. 1,2 & Row Add. 1,2,3  
Destination Address  
1
R/B#  
I/Ox  
tPROG  
Address  
Data Input  
I/O0  
70h  
10h  
85h  
5Cycles  
“0”  
Pass  
Col. Add.1,2  
“1”  
Fail  
1
There is no limitation for the  
Number of repetition  
Page Copy-Back Program Operation with Random Data Input  
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Publication Date: Dec. 2019  
Revision: 0.2  
35/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Read ID  
CE#  
CLE  
tAR  
ALE  
WE#  
tREA  
tRC  
RE#  
I/Ox  
3rd cyc.  
4th cyc.  
5th cyc.  
2nd cyc.  
90h  
00h  
1st cyc.  
Read ID Command  
Maker Code.  
Device Code.  
Address 1cycle  
Read ID Timing  
00h Address ID Cycle  
Users can read five bytes of ID containing manufacturer code, device code and architecture information of the target by command  
90h followed by 00h address. The command register remains in Read ID mode until another command is issued.  
Description  
x8 device  
1st Byte  
2nd Byte  
3rd Byte  
4th Byte  
5th Byte  
Maker Code  
C8h  
6Ah  
90h  
04h  
34h  
Device Code  
Internal Chip Number, Cell Type, etc  
Page Size, Block Size, etc  
Plane Number, ECC Level  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 36/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
2nd ID Data  
Item  
Description  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
DQ2  
DQ1  
DQ0  
1Gb  
2Gb  
4Gb  
8Gb  
16Gb  
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
Density  
1.8V  
3.3V  
0
1
1
0
Voltage  
SPI  
X8  
0
0
1
0
1
0
Interface  
X16  
3rd ID Data  
Item  
Description  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
DQ2  
DQ1  
DQ0  
1
2
4
8
0
0
1
1
0
1
0
1
Internal Chip Number  
Cell Type  
2 Level Cell  
4 Level Cell  
8 Level Cell  
16 Level Cell  
0
0
1
1
0
1
0
1
1
2
4
8
0
0
1
1
0
1
0
1
Number of  
Simultaneously  
Programmed Pages  
Interleave Program  
Between Multiple Chips  
Not Support  
Support  
0
1
Not Support  
Support  
0
1
Cache Program  
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Publication Date: Dec. 2019  
Revision: 0.2 37/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
4th ID Data  
Item  
Description  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
DQ2  
DQ1  
DQ0  
2KB  
4KB  
0
0
1
1
0
1
0
1
Page Size  
(w/o redundant area)  
8KB  
Reserved  
128KB  
256KB  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
512KB  
Block Size  
(w/o redundant area)  
1MB  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
128B  
224B  
400B  
436B  
512B  
640B  
1KB  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Redundant Area Size  
(Byte / Page Size)  
5th ID Data  
Item  
Description  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
DQ2  
DQ1  
DQ0  
1
2
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
Plane Number  
4
8
16  
1bit  
2bit  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4bit  
8bit  
ECC Level  
Reserved  
12bit  
24bit  
40bit  
60bit  
Reserved  
0
0
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 38/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Read Status and Read Status2  
The Read Status function (command 70h) retrieves a status value for the last operation issued in the case of one-plane operations.  
While the Read Status2 function (command F1h) retrieves plane0 and plane1 status. Both 70h and F1h are followed without address  
setting. Specifically, Read Status and Read Status 2 return the combined status values of the independent status register bits according  
to Table below.  
Read Status Definition  
I/O0  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
Pass: 0  
Fail: 1  
Pass: 0  
Fail: 1  
Busy: 0  
Ready: 1  
Busy: 0  
Ready: 1  
Protected: 0  
Not Protected: 1  
Definition  
Reserved Reserved Reserved  
Read  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
Busy/Ready  
Write Protect  
Cache  
Read  
Flash array  
Busy/Ready  
Host  
Busy/Ready  
NA  
NA  
Write Protect  
Page  
Program  
Pass/Fail  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
NA  
Busy/Ready  
Write Protect  
Write Protect  
Write Protect  
Cache  
Program  
Flash array  
Busy/Ready  
Host  
Busy/Ready  
Pass/Fail (N-1) Pass/Fail  
Pass/Fail NA  
Block  
Erase  
NA  
Busy/Ready  
NOTE:  
1. During Block Erase, Page Program or Copy-Back operation, I/O0 is only valid when I/O6 shows the Ready state.  
2. During Cache Program operation, I/O0 is only valid when I/O5 shows the Ready state, and I/O1 is only valid when I/O6 shows the  
Ready state.  
Read Status2 Definition  
I/O0  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
Pass: 0  
Fail: 1  
Pass: 0  
Fail: 1  
Pass: 0  
Fail: 1  
Pass: 0  
Fail: 1  
Pass: 0  
Fail: 1  
Busy: 0  
Ready: 1  
Busy: 0  
Ready: 1  
Protected: 0  
Not Protected: 1  
Definition  
Read  
NA  
NA  
NA  
NA  
NA  
NA  
Busy/Ready  
Write Protect  
Cache  
Read  
Flash array  
Busy/Ready  
Host  
Busy/Ready  
NA  
NA  
NA  
NA  
NA  
Write Protect  
Plane#0  
Pass/Fail  
Plane#1  
Pass/Fail  
Page  
Program  
Pass/Fail  
Pass/Fail  
Pass/Fail  
NA  
NA  
NA  
Busy/Ready  
Write Protect  
Write Protect  
Write Protect  
Plane#0  
(N-1)  
Pass/Fail Pass/Fail  
Plane#1  
(N-1)  
Plane#0 (N)  
Pass/Fail  
Plane#1 (N)  
Pass/Fail  
Cache  
Program  
Flash array  
Busy/Ready  
Host  
Busy/Ready  
Plane#0  
Pass/Fail  
Plane#1  
Pass/Fail  
Block  
Erase  
NA NA  
NA  
Busy/Ready  
NOTE:  
1. (N) means current page, and (N-1) means previous page.  
2. During Block Erase, Page Program or Copy-Back operation, I/O0, I/O1, and I/O2 are only valid when I/O6 shows the Ready state.  
3. During Cache Program operation, I/O0, I/O1, and I/O2 are only valid when I/O5 shows the Ready state, and I/O3 and I/O4 is only  
valid when I/O6 shows the Ready state.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 39/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Reset  
The device offers a reset function by command FFh. When the device is in ‘Busy’ state during any operation, the Reset operation will  
abort these operations except during power-on when Reset shall not be issued until R/B# is set to one (i.e. ready). The contents of  
memory cells being programmed are no longer valid, as the data will be partially programmed or erased. Although the device is already  
in process of reset operation, a new Reset command will be accepted.  
R/B#  
I/Ox  
tRST  
FFh  
Reset Timing  
When Status Read command (70h) is input after Reset Operation  
70  
FF  
Status ：Pass/Fail -> Pass  
：Ready/Busy -> Ready  
R/B#  
Status Read after Reset operation  
When two or more Reset commands are input in succession  
(1)  
FF  
(2)  
FF  
(3)  
FF  
10  
R/B#  
FF  
The second  
command is invalid, but the third  
Successive Reset operation  
command is valid.  
FF  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2  
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ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Two-Plane Operation  
Two page address may be set over two planes. The page addresses and block address shall be identical when setting each plane. The  
same plane address shall not be set twice or more within a set of address setting sequence. The number of planes which are set for  
this operation shall be even. Multi page operation in this mode is also regarded as multi-plane operation.  
Two-Plane Page Read  
The Two-Plane Page Read operation is and extension of the Page Read operation. The device supporting Two-Plane Page Read  
operation also allows multiple Random data-output from each page (i.e. Two-Plane Page Random Data Output) once two- plane pages  
are loaded to page registers.  
Once the data are loaded into the cache registers, the data on the first page can be read out by issuing the Two-Plane Random Data  
Output command. The data on other pages can be also read out using the identical command sequences. Figures below define  
Two-Plane Page Read and Two-Plane Random Data Output behavior and timings.  
R/B#  
I/Ox  
tR  
Address  
(3 Cycle)  
Address  
(3 Cycle)  
60h  
60h  
30h  
Row Add. 1,2,3  
Row Add. 1,2,3  
Page address: Page M  
Plane address: Fixed ‘Low’  
Block address: Block N  
Page address: Page M  
Plane address: Fixed ‘High’  
Block address: Block N  
1
R/B#  
I/Ox  
Address  
(5 Cycle)  
Address  
(2 Cycle)  
00h  
E0h  
05h  
Data Output  
Col. Add. 1,2 & Row Add. 1,2,3  
Col. Add. 1,2  
1
2
Column address: Fixed ’Low’  
Page address: Page M  
Column address: Valid  
Plane address: Fixed ‘Low’  
Block address: Block N  
R/B#  
I/Ox  
Address  
(5 Cycle)  
Address  
(2 Cycle)  
05h  
00h  
E0h  
Data Output  
Col. Add. 1,2  
Col. Add. 1,2 & Row Add. 1,2,3  
2
Column address: Valid  
Column address: Fixed ’Low’  
Page address: Page M  
Plane address: Fixed ‘High’  
Block address: Block N  
Two-Plan Page Read Operation  
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Publication Date: Dec. 2019  
Revision: 0.2 41/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Two-Plane Cache Read  
Two-Plane Sequential Cache Read operation provides fast sequential read function after the initial Two-Plane Page Read operation is  
set. With the primary command, once Two-Plane Page Read operation performs, next page data can be loaded to page register by  
command 31h without additional address setting while a host reads data, which is loaded by Two-Plane Page Read operation, from  
cache registers. Since the next page data are loaded to page registers during host read-out period, R/B# turns to high (i.e. ready) in a  
short time after command 31h although data loading by command 31h is being performed internally. If the previous data is still being  
loaded after command 31h, R/B# busy state may takes as long as tR, hence the maximum time of tDCBSYR1 is identical to tR. At the last  
page, command 3Fh shall be issued to transfer data from page registers to cache registers. Two-Plane Sequential Cache Read  
operation shall work only within a block of each plane and shall not be continued over the boundary of plane. Figure below define  
Two-Plane Sequential Cache Read behavior and timings.  
tR  
R/B#  
I/Ox  
Address (3 Cycle)  
Row Add. 1,2,3  
Address (3 Cycle)  
Row Add. 1,2,3  
60h  
60h  
33h  
1
Page address: Page M  
Plane address: Fixed ‘Low’  
Block address: Block N  
Page address: Page M  
Plane address: Fixed ‘High’  
Block address: Block N  
tDCBSYR1  
R/B#  
I/Ox  
Address (2 Cycle)  
Col. Add. 1,2  
Data Output  
Address (5 Cycle)  
00h  
E0h  
31h  
05h  
Col. Add. 1,2 & Row Add. 1,2,3  
2
Column address: Valid  
1
Column address: Fixed ’Low’  
Page address: Page M  
Plane address: Fixed ‘Low’  
Block address: Block N  
R/B#  
I/Ox  
Data Output  
E0h  
Address (2 Cycle)  
Col. Add. 1,2  
Address (5 Cycle)  
00h  
05h  
Col. Add. 1,2 & Row Add. 1,2,3  
2
3
Column address: Valid  
Column address: Fixed ’Low’  
Page address: Page M  
Plane address: Fixed ‘High’  
Block address: Block N  
tDCBSYR1  
R/B#  
I/Ox  
Address (5 Cycle)  
00h  
Col. Add. 1,2 & Row Add. 1,2,3  
Address (2 Cycle)  
Col. Add. 1,2  
Data Output  
E0h  
3Fh  
05h  
3
4
Column address: Valid  
Column address: Fixed ’Low’  
Page address: Page M+n  
Plane address: Fixed ‘Low’  
Block address: Block N  
R/B#  
I/Ox  
Data Output  
Address (5 Cycle)  
05h  
Col. Add. 1,2 & Row Add. 1,2,3  
Address (2 Cycle)  
Col. Add. 1,2  
E0h  
00h  
4
Column address: Fixed ’Low’  
Page address: Page M+n  
Plane address: Fixed ‘High’  
Block address: Block N  
Column address: Valid  
Two-Plane Cache Read Operation with Two-Plane Random Data Out  
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Publication Date: Dec. 2019  
Revision: 0.2 42/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Two-Plane Page Program  
Two-Plane Program function extends and effective programmable page size using multiple pages. When a host moves to load data for  
another page, command 11h for the second command is used. After 11h command, R/B3 returns high (i.e. ready) in a short period of  
time since it is not actual programming operation. At the last page loading, command 81h is issued before loading data and command  
10h after data loading is issued for the second command. After command 10h, all loaded data in each page stars to be programmed to  
Flash array simultaneously. Figure below defines Two-Plane Page Program behavior and timings.  
tDBSY  
Note  
80h  
tPROG  
R/B#  
I/Ox  
“0”  
Pass  
Address &  
Data Input  
Address &  
Data Input  
70h/  
F1h  
80h  
81h  
10h  
11h  
I/O0  
“1”  
Fail  
Column address: Valid  
Page address: Page M  
Plane address: Fixed ‘Low’  
Column address: Valid  
Page address: Page M  
Plane address: Fixed ‘High’  
Block address: Block N  
Block address: Block N  
Data  
Input  
11h  
80h  
11h  
Block0  
Block2  
Block1  
Block3  
Plane 0  
Plane 1  
NOTE: The page address and block address shall be the same in Two-Plane Page Program operation.  
Two-Plane Page Program  
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Publication Date: Dec. 2019  
Revision: 0.2 43/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Two-Plane Cache Program  
The Two-Plane Cache Program is an extension of the Cache Program. After loading pages for Two-Plane Cache Program, command  
15h is issued. After command 15h, R/B# returns high once transferring data from cache register to page register is completed. Internal  
program operation is in progress after R/B# returns while other pages are loaded by a host. At the last page loading for the entire  
Two-Plane Cache Program, command 10h is required to finalize the operation and R/B# stays busy as long as tLPROG. Two-Plane  
Cache Program operation shall work only within a block of each plane and shall not be continued over the boundary of plane. The  
activated planes for the first Two-Plane Cache Program shall be kept using in the next address sequence until Two-Plane Cache  
Program operation is completed by command 10h. Figure below defines Two-Plane Cache Program behavior and timings.  
tCBSY  
tDBSY  
R/B#  
I/Ox  
11h  
81h  
15h  
Address & Data Input  
80h Address & Data Input  
Column address: Valid  
Page address: Page M  
Plane address: Fixed ‘Low’  
Block address: Block N  
Column address: Valid  
Page address: Page M  
Plane address: Fixed ‘Low’  
Block address: Block N  
1
tLPROG  
tDBSY  
R/B#  
I/Ox  
81h Address & Data Input  
80h Address & Data Input  
11h  
10h  
Column address: Valid  
Page address: Page M+n  
Plane address: Fixed ‘High’  
Block address: Block N  
Column address: Valid  
Page address: Page M+n  
Plane address: Fixed ‘Low’  
Block address: Block N  
Note  
1
1
2
3
80h  
11h  
81h  
15h  
2
Cache register  
Data register  
1
3
3
Plane 1  
Block 1  
Plane 0  
Block 0  
Block 2  
•
•
Block 3  
•
•
NOTE: The page address and block address shall be the same in Two-Plane Page Program operation.  
Two-Plane Cache Program  
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Publication Date: Dec. 2019  
Revision: 0.2 44/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Two-Plane Block Erase  
Two-Plane Block Erase allows users to erase multiple blocks comprising a block of each plane simultaneously. The same plane  
address shall not be set twice within a set of address setting sequence for the Two-Plane Block Erase operation. Figure below defines  
Two-Plane Block Erase behavior and timings.  
tBERS  
R/B#  
“0”  
70h/  
F1h  
D0h  
60h  
Address (3 Cycle)  
60h Address (3 Cycle)  
I/O0  
“1”  
Fail  
I/Ox  
Pass  
Row Add. 1,2,3  
Row Add. 1,2,3  
Page address: Fix Low  
Plane address: Fix Low  
Block address: Block N  
Page address: Fix Low  
Plane address: Fix High  
Block address:Block N  
Two-Plane Block Erase Operation  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 45/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Two-Plane Copy-Back Program  
The Two-Plane Copy-Back Program is an extension of the Copy-Back Program. Two-Plane Copy-Back Program operation is executed  
two sets of commands. Two-Plane Read for Copy-Back and Two-Plane Copy-Back Program. The read data shall be copied back to a  
page in the same plane. Figures below define Two-Plane Copy-Back Program behavior and timings.  
tR  
R/B#  
35h  
60h  
60h  
I/Ox  
Address (3 Cycle)  
Address (3 Cycle)  
Row Add. 1,2,3  
Row Add. 1,2,3  
1
Page address: Page M  
Plane address: Fixed ‘Low’  
Block address: Block N  
Page address: Page M  
Plane address: Fixed ‘High’  
Block address: Block N  
R/B#  
I/Ox  
Address (2 Cycle)  
E0h  
E0h  
Address (5 Cycle)  
Col. Add. 1,2 & Row Add. 1,2,3  
00h  
05h  
Data Output  
Data Output  
Col. Add. 1,2  
2
Column address: Fixed ’Low’  
Page address: Page M  
Plane address: Fixed ‘Low’  
Block address: Block N  
Column address: Valid  
1
R/B#  
I/Ox  
00h  
Address (5 Cycle)  
Address (2 Cycle)  
05h  
Col. Add. 1,2 & Row Add. 1,2,3  
Col. Add. 1,2  
2
3
Column address: Fixed ’Low’  
Page address: Page M  
Column address: Valid  
Plane address: Fixed ‘High’  
Block address: Block N  
tPROG  
tDBSY  
R/B#  
I/Ox  
70h/  
F1h  
“0”  
Address  
(5 Cycle)  
Destination Address  
Address  
11h  
85h  
81h  
10h  
I/O0  
(5 Cycle)  
Pass  
3
Destination Address  
“1”  
Fail  
Note  
Col. Add. 1,2 & Row Add. 1,2,3  
Col. Add. 1,2 & Row Add. 1,2,3  
Column address: Fixed ’Low’  
Page address: Page M  
Column address: Fixed ’Low’  
Page address: Page M  
Plane address: Fixed ‘High’  
Block address: Block N  
Plane address: Fixed ‘Low’  
Block address: Block N  
Plane0  
Plane1  
Data Field  
Target page  
Data Field  
Target page  
(1):Two-Plane Read for Copy Back  
(2):Two-Plane Random Date Out  
(3):Two-Plane Copy Back Program  
Source page  
Source page  
3
3
1
1
Spare Field  
Spare Field  
2
2
NOTE: The LSB of page address shall be the same between source and destination pages. In other words, the page of even page  
address can’t be copied to the page of odd page address, and the page of odd page address can’t be copied to the page of even page  
address as well.  
Two-Plane Copy-Back Program Operation  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 46/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
tR  
R/B#  
I/Ox  
35h  
60h  
00h  
60h  
Address (3 Cycle)  
Row Add. 1,2,3  
Address (3 Cycle)  
Row Add. 1,2,3  
1
Page address: Page M  
Page address: Page M  
Plane address: Fixed ‘Low’  
Plane address: Fixed ‘High’  
Block address: Block N  
Block address: Block N  
R/B#  
I/Ox  
Address (2 Cycle)  
Col. Add. 1,2  
E0h  
Data Output  
Address (5 Cycle)  
05h  
Col. Add. 1,2 & Row Add. 1,2,3  
2
Column address: Valid  
1
Column address: Fixed ’Low’  
Page address: Page M  
Plane address: Fixed ‘Low’  
Block address: Block N  
R/B#  
I/Ox  
E0h  
Data Output  
00h  
05h  
Address (2 Cycle)  
Col. Add. 1,2  
Address (5 Cycle)  
Col. Add. 1,2 & Row Add. 1,2,3  
2
3
Column address: Valid  
Column address: Fixed ’Low’  
Page address: Page M  
Plane address: Fixed ‘High’  
Block address: Block N  
R/B#  
tDBSY  
Data  
Input  
Address  
(2 Cycle)  
Data  
Input  
Address  
(5 Cycle)  
85h  
11h  
I/Ox  
85h  
3
Destination Address  
Col. Add. 1,2  
Destination Address  
Note  
4
Col. Add. 1,2 & Row Add. 1,2,3  
Column address: Valid  
Column address: Valid  
Page address: Page M  
Plane address: Fixed ‘Low’  
Block address: Block N  
tPROG  
R/B#  
I/Ox  
4
Address  
Data  
Input  
Data  
Input  
Address  
(5 Cycle)  
Destination Address  
85h  
10h  
85h  
(2 Cycle)  
Destination Address  
Col. Add. 1,2  
Col. Add. 1,2 & Row Add. 1,2,3  
Column address: Valid  
Column address: Fixed ’Valid’  
Page address: Page M  
Plane address: Fixed ‘High’  
Block address: Block N  
NOTE: The page address and block address shall be the same in Two-Plane Page Program operation.  
Two-Plane Copy-Back Program with Random Data Input Operation  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 47/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Read Parameter Page Operation  
Read Parameter Page (ECh) command is used to read the ONFI parameter page programmed into the target. This command is  
accepted by the target only when the die(s) on the target is idle. Writing ECh to the command register puts the target in read parameter  
page mode. The target stays in this mode until another valid command is issued.  
When ECh command is followed by one 00h address cycle, the target goes busy for tR. If the Read Status (70h) command is used to  
monitor for command completion, the Read mode (00h) command must be used to re-enable data output mode.  
A minimum of three copies of the parameter page are stored in the device. Each parameter page is 256 bytes. Random Data Output  
(05h-E0h) can be used to change the location of data output. Each copy has the CRC value stored at the last two bytes. The software  
can read the first copy of ONFI parameter page, calculate the CRC and compare it with the stored value. If mis-match found then the  
2nd copy should be read and so forth.  
Command Address  
Cycle type  
I/O[7:0]  
R/B#  
DOUT  
DOUT  
DOUT  
DOUT  
DOUT  
DOUT  
…
…
ECh  
00h  
P10  
P01  
P00  
P11  
tR  
tRR  
tWB  
Read Parameter Page Operation  
Parameter Page Data Structure  
Byte  
0-3  
Description  
Value  
Parameter page signature ("O", "N", "F", "I")  
Revision number  
4Fh, 4Eh, 46h, 49h  
02h, 00h  
4-5  
6-7  
Features supported  
10h, 00h  
8-9  
Optional commands supported  
Reserved  
31h, 00h  
10-31  
All 00h  
50h, 4Fh, 57h, 45h, 52h, 43h, 48h, 49h, 50h,  
20h, 20h, 20h  
32-43  
44-63  
Device manufacturer  
Device model  
50h, 53h, 55h, 32h, 47h, 41h, 33h, 30h, 43h,  
54h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h,  
20h, 20h  
64  
Manufacturer ID  
C8h  
65-66  
67-79  
80-83  
84-85  
86-89  
90-91  
92-95  
96-99  
100  
Date code  
00h, 00h  
Reserved  
All 00h  
Number of data bytes per page  
Number of spare bytes per page  
Number of data bytes per partial page  
Number of spare bytes per partial page  
Number of pages per block  
Number of blocks per unit  
Number of logical units  
00h, 08h, 00h, 00h  
80h, 00h  
00h, 02h, 00h, 00h  
20h, 00h  
40h, 00h, 00h, 00h  
00h, 08h, 00h, 00h  
01h  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2  
48/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
101  
Number of address cycles  
23h  
01h  
102  
Number of bits per cell  
103-104 Number of maximum bad blocks per unit  
105-106 Block endurance  
28h, 00h  
05h, 04h  
01h  
107  
Guaranteed valid blocks at beginning of target  
108-109 Block endurance of guaranteed valid blocks  
00h, 00h  
04h  
110  
111  
112  
113  
114  
Number of partial programs per page  
Partial programming attributes  
Number of bits ECC  
00h  
08h  
Number of Interleaved address bits  
Interleaved operation attributes  
01h  
0Ch  
115-127 Reserved  
All 00h  
08h  
128  
I/O pin capacitance  
129-130 Timing mode support (Reserved)  
131-132 Program cache timing mode support (Reserved)  
133-134 tPROG (max)  
1Fh, 00h  
1Fh, 00h  
BCh, 02h  
10h, 27h  
19h, 00h  
46h, 00h  
All 00h  
00h, 00h  
135-136 tBERS (max)  
137-138 tR (max)  
139-140 tCCS (min)  
141-163 Reserved  
164-165 Vendor-specific revision number  
Two-Plane Page Read support  
166  
167  
168  
169  
Bit[7:1]: Reserved (0)  
Bit 0: 0= Doesn’t support Two Plane Page Read  
Read cache support  
Bit[7:1]: Reserved (0)  
Bit 0: 0= Doesn’t support ONFI-specific read cache  
Read Unique ID support  
Bit[7:1]: Reserved (0)  
Bit 0: 0= Doesn’t support ONFI-specific Read Unique ID  
Programmable output impedance support  
Bit[7:1]: Reserved (0)  
01h  
01h  
01h  
00h  
Bit 0: 0= Doesn’t support programmable output impedance support  
Number of programmable output impedance support  
settings  
170  
00h  
Bit[7:3]: Reserved (0)  
Bit[2:0]: Number of programmable IO output impedance settings  
171  
172  
173  
174  
Reserved  
00h  
00h  
00h  
00h  
Programmable R/B# pull-down strength support  
Bit[7:1]: Reserved (0)  
Bit 0: 0= Doesn’t support programmable R/B# pull-down strength  
Reserved  
Number of programmable R/B# pull-down strength support  
Bit[7:3]: Reserved (0)  
Bit[2:0]: Number of programmable R/B# pull-down strength settings  
OTP mode support  
Bit[7:2]: Reserved (0)  
Bit 1: 0= Doesn’t support Get/Set Feature command set  
Bit 0: 1= support OTP mode  
175  
01h  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 49/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
OTP page start  
Bit[7:0] = Page where OTP page space begins  
176  
00h  
00h  
OTP Data Protect address  
Bit[7:0] = Page address to use when issuing OTP Data Protect command  
177  
Number of OTP pages  
178  
179  
Bit[15:5]: Reserved (0)  
Bit[4:0] = Number of OTP pages  
1Eh  
OTP Feature Address  
90h  
180-253 Reserved  
All 00h  
254-255 Integrity CRC  
01h, E6h  
256-511 Values of bytes 0-255  
512-767 Values of bytes 0-255  
Values of bytes 0-255  
Values of bytes 0-255  
768+  
Additional redundant parameter pages  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 50/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Read Unique ID Operation  
Read Unique ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the  
target only when the die(s) on the target is idle. Writing EDh to the command register puts the target in read unique ID mode. The target  
stays in this mode until another valid command is issued.  
When EDh command is followed by one 00h address cycle, the target goes busy for tR. If the Read Status (70h) command is used to  
monitor for command completion, the Read mode (00h) command must be used to re-enable data output mode. After tR completes, the  
host enables data output mode to read the unique ID.  
Sixteen copies of the unique ID data are store in the device. Each copy is 32 bytes. The first 16 bytes of a 32-byte copy are unique ID  
data, and the second 16 bytes are the complement of the first 16 bytes of FFh, then that copy of the unique ID data is correct. In the  
event that a non-FFh result is returned, the host can repeat the XOR operation on a subsequent copy of the unique ID data. Random  
Data Output (05h-E0h) can be used to change the location of data output.  
Command  
EDh  
Address  
00h  
Cycle type  
I/O[7:0]  
R/B#  
DOUT  
DOUT  
DOUT  
DOUT  
DOUT  
DOUT  
…
…
U10  
U01  
U00  
U11  
tRR  
tR  
tWB  
Read Unique ID Operation  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 51/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Page Copy  
By using Page Copy, data in a page can be copied to another page after the data has been read out. When the block address changes  
(increments) this sequenced has to be started from the beginning.  
tR  
tDCBSYW2  
R/B#  
I/Ox  
Address  
5Cycles  
Address  
5Cycles  
15h  
00h  
Data Input  
Data output  
30h  
8Ch  
Col. Add. 1,2 & Row Add. 1,2,3  
Col. Add. 1,2 & Row Add. 1,2,3  
Destination Address (Page-B)  
1
Source Address (Page-A)  
(Data  
output)  
(Data  
input)  
Data cache  
Page Buffer  
Page A  
Page A  
Page A  
Page A  
(I)  
(II)  
(IV)  
(III)  
I. Data for Page A is transferred to the Data Cache  
II. Data for Page A is read out  
III. Copy Page address B is input and if the data needs to be changed, changed data is input  
IV. Data Cache for Page B is transferred to the Page Buffer  
R/B#  
I/Ox  
tDCBSYW2  
tDCBSYR2  
Address  
5Cycles  
Address  
5Cycles  
3Ah  
Data Input 15h  
00h  
Data output  
8Ch  
Col. Add. 1,2 & Row Add. 1,2,3  
Col. Add. 1,2 & Row Add. 1,2,3  
Destination Address (Page-D)  
1
2
Source Address (Page-C)  
(Data  
input)  
(Data  
output)  
Page B  
Page A  
Page C  
Page B  
Page D  
Page C  
Page D  
Page C  
Page A  
Page C  
(VI)  
(V)  
(VII)  
(VIII)  
V. Data for Page C is transferred to Data Cache while the data of Page B is being programmed  
VI. After the Ready state, Data for Page C is output from the Data Cache  
VII. Copy Page address D is input and if the data needs to be changed, changed data is input  
VIII. After programming of page B is completed, Data Cache for Page D is transferred to the Page Buffer  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 52/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
tDCBSYR2  
Address  
tDCBSYR2  
R/B#  
Address  
5Cycles  
3Ah  
Data output  
I/Ox  
00h  
00h  
3Ah  
5Cycles  
Col. Add. 1,2 & Row Add. 1,2,3  
Col. Add. 1,2 & Row Add. 1,2,3  
2
3
Source Address (Page-Y)  
Source Address (Page-E)  
(Data output)  
Page E  
Page D  
Page E  
Page D  
Page X  
Page X  
Page C  
Page C  
Page Y  
Page Y  
(IX)  
(X)  
(XI)  
(XII)  
IX. By the 15h command, the data in the Page Buffer is programmed to Page D. Data for Page E is transferred  
to the Data cache  
X. Data for Page E is read out  
XI. Data Cache for Page X is transferred to the Page Buffer  
XII.The data in the Page Buffer is programmed to Page X. Data for Page Y is transferred to the Data Cache  
R/B#  
I/Ox  
tPROG (*1)  
Address  
5Cycles  
70h  
I/O0  
Data output  
8Ch  
Data Input  
10h  
“0”  
Pass  
“1”  
Fail  
Col. Add. 1,2 & Row Add. 1,2,3  
Destination Address (Page-Z)  
3
(Data output)  
(Data  
input)  
Page X  
Page X  
Page Z  
Page X  
Page Z  
Page Y  
Page Y  
Page Y  
(XIII)  
(XIV)  
(XV)  
XIII. After the Ready state, Data for Page Y is output from the Data Cache  
XIV. Copy Page address Z is input and if the data needs to be changed, changed data is input  
XV. By issuing the 10h command, the data in the Page Buffer is programmed to Page Z  
(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG here will be expected as the following,  
tPROG = tPROG of the last page + tPROG of the previous page - ( command input cycle + address input cycle + data output/input cycle time of the last page)  
NOTE) This operation needs to be executed within Plane-0 or Plane-1.  
Data input is required only if previous data output needs to be altered.  
If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command,  
and change only the data that needs be changed.  
If the data does not have to be changed, data input cycles are not required.  
Make sure WP is held to High level when Page Copy operation is performed.  
Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 53/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Two-Plane Page Copy  
By using Two-Plane Page Copy, data in two pages on different plane can be copied to other pages after the data has been read out.  
When each block address changes (increments) this sequence has to be started from the beginning. Same page address (A13 to A18)  
and same block address (A20~A29) within two plane has to be selected.  
tR  
R/B#  
I/Ox  
Address  
3Cycles  
Address  
Address  
5Cycles  
Col. Add.1,2 & Row add. 1,2,3 Col. Add.1,2  
Address  
60h  
Row address 1,2,3 Row address 1,2,3  
Data output  
60h  
30h  
00h  
05h  
E0h  
3Cycles  
2Cycles  
Column address: Valid  
Column address: Fixed Low  
Page address: Page M0  
Plane address: Fixed Low  
Block address: Block N0  
1
Page address: Page M0  
Plane address: Fixed High  
Block address: Block N0  
Page address: Page M0  
Plane address: Fixed Low  
Block address: Block N0  
tDCBSYW1  
R/B#  
Address  
5Cycles  
Address  
Address  
00h  
05h  
E0h  
Data output  
Data input  
11h  
8Ch  
I/Ox  
2Cycles  
5Cycles  
Col. Add.1,2 & Row add. 1,2,3 Col. Add.1,2  
Col. Add.1,2 & Row add. 1,2,3  
Column address: Valid  
Column address: Fixed Low  
Page address: Page M0  
Plane address: Fixed High  
Block address: Block N0  
Column address: Valid  
Page address: Page T0  
Plane address: Fixed Low  
Block address: Block U0  
2
1
tDCBSYW2  
Data input  
tDCBSYR2  
Address  
R/B#  
I/Ox  
Address  
3Cycles  
Address  
8Ch  
60h  
60h  
3Ah  
15h  
3Cycles  
5Cycles  
Row address 1,2,3 Row address 1,2,3  
Col. Add.1,2 & Row add. 1,2,3  
Page address: Page M1  
Plane address: Fixed High  
Block address: Block N1  
Page address: Page M1  
Plane address: Fixed Low  
Block address: Block N1  
Column address: Valid  
Page address: Page T0  
Plane address: Fixed High  
Block address: Block U0  
3
2
R/B#  
I/Ox  
Address  
5Cycles  
Address  
Address  
Address  
00h  
00h  
05h  
Data output  
Data output  
05h  
E0h  
E0h  
2Cycles  
5Cycles  
2Cycles  
Col. Add.1,2 & Row add. 1,2,3 Col. Add.1,2  
Col. Add.1,2 & Row add. 1,2,3 Col. Add.1,2  
Column address: Valid  
Column address: Valid  
Column address: Fixed Low  
Page address: Page M1  
Plane address: Fixed Low  
Block address: Block N1  
Column address: Fixed Low  
Page address: Page M1  
Plane address: Fixed High  
Block address: Block N1  
4
3
R/B#  
I/Ox  
tDCBSYW1  
Data input  
tDCBSYW2  
Address  
Address  
8Ch  
Data input  
8Ch  
15h  
11h  
5Cycles  
5Cycles  
Col. Add.1,2 & Row add. 1,2,3  
Col. Add.1,2 & Row add. 1,2,3  
Column address: Valid  
Page address: Page T1  
Plane address: Fixed Low  
Block address: Block U1  
Column address: Valid  
Page address: Page T1  
Plane address: Fixed High  
Block address: Block U1  
5
4
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 54/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
tDCBSYR2  
R/B#  
Address  
3Cycles  
Address  
Address  
5Cycles  
Address  
60h  
Data output  
60h  
3Ah  
00h  
05h  
E0h  
I/Ox  
3Cycles  
2Cycles  
Row address 1,2,3 Row address 1,2,3  
Col. Add.1,2 & Row add. 1,2,3 Col. Add.1,2  
Column address: Valid  
Page address: Page M63 Column address: Fixed Low  
Plane address: Fixed High Page address: Page M63  
6
Page address: Page M63  
Plane address: Fixed Low  
Block address: Block N63  
5
Plane address: Fixed Low  
Block address: Block N63  
Block address: Block N63  
tDCBSYW1  
Data input  
R/B#  
I/Ox  
Address  
Address  
Address  
8Ch  
00h  
05h  
E0h  
Data output  
11h  
5Cycles  
2Cycles  
5Cycles  
Col. Add.1,2 & Row add. 1,2,3 Col. Add.1,2  
Col. Add.1,2 & Row add. 1,2,3  
Column address: Valid  
Column address: Fixed Low  
Page address: Page M63  
Plane address: Fixed High  
Block address: Block N63  
Column address: Valid  
Page address: Page T63  
Plane address: Fixed Low  
Block address: Block U63  
7
6
R/B#  
I/Ox  
tPROG (*1)  
Address  
8Ch  
Data input  
10h  
5Cycles  
Col. Add.1,2 & Row add. 1,2,3  
Column address: Valid  
7
Page address: Page T63  
Plane address: Fixed High  
Block address: Block U63  
(*1) tPROG: Since the last page programming by 10h command is initiated after the previous cache program,  
the tPROG* during cache programming is given by the following equation.  
tPROG = tPROG of the last page + tPROG of the previous page-A  
A = (command input cycle + address input cycle + data output/input cycle time of the last page)  
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.  
Note)  
This operation needs to be executed within each Plane.  
Data input is required only if previous data output needs to be altered.  
If the data has to be changed, locate the desired address with the column and page address input after  
the 8Ch command, and change only the data that needs be changed.  
If the data does not have to be changed, data input cycles are not required.  
Make sure WP is held to High level when Two-Plane Page Copy operation is performed.  
Also make sure the Multi Page Copy operation is terminated with 8Ch-10h command sequence  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 55/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
PACKING DIMENSION  
48-LEAD TSOP(I) ( 12x20 mm )  
Dimension in mm  
Min Norm Max  
------- ------- 1.20 ------- ------- 0.047  
0.05 ------- 0.15 0.006 ------- 0.002  
Dimension in inch  
Min Norm Max  
Dimension in mm  
Dimension in inch  
Min Norm Max  
0.787 BSC  
Symbol  
Symbol  
Min Norm Max  
20.00 BSC  
18.40 BSC  
12.00 BSC  
0.50 BSC  
A
A 1  
A 2  
b
b1  
c
D
D 1  
E
e
L
0.724 BSC  
0.472 BSC  
0.020 BSC  
0.95 1.00  
0.17 0.22  
0.17 0.20  
1.05 0.037 0.039 0.041  
0.27 0.007 0.009 0.011  
0.23 0.007 0.008 0.009  
0.50 0.60  
0O  
-------  
0.70 0.020 0.024 0.028  
8O 0O 8O  
-------  
0.10 ------- 0.21 0.004 ------- 0.008  
0.10 ------- 0.16 0.004 ------- 0.006  
θ
c1  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 56/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
PACKING DIMENSIONS  
63-BALL  
NAND Flash ( 9x11 mm )  
E
Pin #1  
D
A2  
A
A1  
Seating plane  
C
ccc C  
Detail A  
Detail A  
e
e
Solder ball  
e
e
b
D1  
Detail B  
Pin #1  
Index  
E1  
Detail B  
Dimension in mm  
Norm  
Dimension in inch  
Norm  
Symbol  
Min  
0.25  
0.40  
Max  
1.00  
0.35  
Min  
Max  
0.039  
0.014  
A
A1  
A2  
Φb  
D
0.010  
0.60 BSC  
0.024 BSC  
0.50  
11.10  
9.10  
0.016  
0.429  
0.350  
0.020  
0.437  
0.358  
10.90  
8.90  
11.00  
9.00  
0.433  
0.354  
E
D1  
E1  
e
8.80 BSC  
7.20 BSC  
0.8 BSC  
0.346 BSC  
0.283 BSC  
0.031 BSC  
ccc  
0.10  
0.004  
Controlling dimension : Millimeter.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 57/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
PACKING DIMENSIONS  
67-BALL Flash ( 6.5x8 mm )  
D
Pin# 1  
index  
Seating plane  
Detail "A"  
"A"  
D1  
e
Φ
b
Pin# 1  
index  
Detail "B"  
"B"  
Symbol  
Dimension in mm  
Dimension in inch  
Min  
Norm  
Max  
Min  
Norm  
Max  
A
A1  
A2  
Φb  
D
1.00  
0.32  
0.71  
0.40  
6.60  
8.10  
0.039  
0.013  
0.028  
0.016  
0.260  
0.319  
0.22  
0.61  
0.30  
6.40  
7.90  
0.27  
0.66  
0.35  
6.50  
8.00  
0.009  
0.024  
0.012  
0.252  
0.311  
0.011  
0.026  
0.014  
0.256  
0.315  
E
D1  
E1  
e
5.60 BSC  
7.20 BSC  
0.80 BSC  
0.220 BSC  
0.283 BSC  
0.031 BSC  
Controlling dimension : Millimeter.  
(Revision date : Jun 29 2014)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 58/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Revision History  
Revision  
Date  
Description  
0.1  
2019.07.29  
2019.12.12  
Original  
1. Add 67 ball BGA packing  
2. Correct typo  
0.2  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2  
59/60  
ESMT  
(Preliminary)  
F59L2G81KA (2N)  
Important Notice  
All rights reserved.  
No part of this document may be reproduced or duplicated in any form or  
by any means without the prior permission of ESMT.  
The contents contained in this document are believed to be accurate at  
the time of publication. ESMT assumes no responsibility for any error in  
this document, and reserves the right to change the products or  
specification in this document without notice.  
The information contained herein is presented only as a guide or  
examples for the application of our products. No responsibility is  
assumed by ESMT for any infringement of patents, copyrights, or other  
intellectual property rights of third parties which may result from its use.  
No license, either express , implied or otherwise, is granted under any  
patents, copyrights or other intellectual property rights of ESMT or  
others.  
Any semiconductor devices may have inherently a certain rate of failure.  
To minimize risks associated with customer's application, adequate  
design and operating safeguards against injury, damage, or loss from  
such failure, should be provided by the customer when making  
application designs.  
ESMT's products are not authorized for use in critical applications such  
as, but not limited to, life support devices or system, where failure or  
abnormal operation may directly affect human lives or cause physical  
injury or property damage. If products described here are to be used for  
such kinds of application, purchaser must do its own quality assurance  
testing appropriate to such applications.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Dec. 2019  
Revision: 0.2 60/60  

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