M16U4G16256A [ESMT]
32M x 16 Bit x 8 Banks DDR4 SDRAM;
| 型号： | M16U4G16256A |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | 32M x 16 Bit x 8 Banks DDR4 SDRAM 动态存储器 双倍数据速率 |
| 文件： | 总53页 (文件大小：1901K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
M16U4G16256A
DDR4 SDRAM
32M x 16 Bit x 8 Banks
DDR4 SDRAM
Feature
Power supply (JEDEC standard 1.2V)
- VDD = 1.2V ± 5%
- VPP = 2.375V to 2.75V
16 internal banks
Differential clock inputs (CK_t and CK_c)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
Data Mask (DM) for write data
Write Cyclic Redundancy Code (CRC) for DQ error detect
and inform it to controller during high-speed operation
Data Bus Inversion (DBI)
- Improve the power consumption and signal integrity of
the memory interface (x16 product only)
Programmable preamble is supported both of 1tCK and
2tCK mode
Command Address (CA) Parity for command/address
signal error detect and inform it to controller
VREFDQ training
- 8 banks (4 banks x 2 bank groups) for x 16 product
Interface: Pseudo Open Drain (POD)
Burst Length (BL): 8 and 4 with Burst Chop (BC)
CAS Latency (CL): 9, 11, 12, 13, 14, 15, 16, 18
CAS Write Latency (CWL): 9, 10, 11, 12, 14, 16
On-Die Termination (ODT): nom. values of RZQ/7,
RZQ/5 (RZQ = 240Ω)
Precharge: auto precharge option for each burst access
Refresh: auto-refresh, self-refresh
Refresh cycles
Average refresh period
- 7.8μs at 0°C ≤ TC ≤ +85°C
- 3.9μs at +85°C < TC ≤ +95°C
- VREFDQ generate inside DRAM and further train per
DRAM
Double-data-rate architecture: two data transfers per
clock cycle
Per DRAM Addressability (PDA)
- Each DRAM can be set a different mode register value
individually and has individual adjustment.
Fine granularity refresh
- 2x, 4x mode for smaller tRFC
Programmable Partial Array Self-Refresh (PASR)
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS_t and DQS_c)
is transmitted/received with data for capturing data at the
receiver
RESET_n pin for power-up sequence and reset function
Operating case temperature range: TC = 0°C to +95°C
DQS is edge-aligned with data for READs; center aligned
with data for WRITEs
Ordering Information
Data Rate
(CL-tRCD-tRP)
Product ID
Max Freq.
VDD
Package
Comments
M16U4G16256A-QLBG
M16U4G16256A-KJBG
M16U4G16256A-HHBG
1600MHz
1333MHz
1200MHz
1.2V
1.2V
1.2V
DDR4- 3200 (24-24-24)
96 ball BGA
96 ball BGA
96 ball BGA
Pb-free
Pb-free
Pb-free
DDR4- 2666 (19-19-19)
DDR4- 2400 (17-17-17)
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
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ESMT
M16U4G16256A
DDR4 SDRAM Addressing
Parameter
256 Mb x16
# of Bank
2
BG0
Bank group address
Bank count per group
Bank address in bank group
Row addressing
4
BA0 – BA1
A0 – A14
A0 – A9
2KB
Column addressing
Page size1
Note:
1.
Page size is per bank, calculated as follows:
Page size = 2COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits.
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ESMT
M16U4G16256A
Ball Configuration – 96 balls BGA Package
< TOP View>
See the balls through the package
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
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ESMT
M16U4G16256A
Input / Output Functional Description
Symbol
Type
Function
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.
CK_t, CK_c
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any
bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have
become stable during the power on and initialization sequence, they must be maintained
during all operations (including Self-Refresh). CKE must be maintained high throughout
read and write accesses. Input buffers, excluding CK_t ꢀꢁꢂꢃꢅꢆꢇꢈꢉꢊꢋꢈꢀꢁꢌꢈꢉꢍꢎꢈꢋꢏꢐꢉꢑꢒꢎꢋ
during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.
CKE
Input
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for
external Rank selection on systems with multiple Ranks. CS_n is considered part of the
command code.
CS_n
ODT
Input
Input
On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance
internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t,
DQS_c and DM_n/DBI_n/ TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode
Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT is applied
to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT
pin will be ignored if MR1 is programmed to disable RTT_NOM.
Activation Command Input : ACT_n defines the Activation command being entered along
with CS_n. The input into RAS_n, CAS_n/A15 and WE_n/A14 will be considered as Row
Address A15 and A14
ACT_n
Input
Input
Command Inputs: RAS_n, CAS_n/A15 and WE_n/A14 (along with CS_n) define the
command being entered. Those pins have multi function. For example, for activation with
ACT_n Low, those are Addressing like A15, A14 but for non-activation command with
ACT_n High, those are Command pins for Read, Write and other command defined in
command truth table
RAS_n, CAS_n/A15,
WE_n/A14
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.
Input data is masked when DM_n is sampled LOW coincident with that input data during a
Write access. DM_nis sampled on both edges of DQS. DM is muxed with DBI function by
DM_n/DBI_n
(DMU_n/DBIU_n),
(DML_n/DBIL_n)
Input/Output Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of DM or TDQS is
enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifying
whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/
output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH.
Bank Group Inputs : BG0 - BG1 define to which bank group an Active, Read, Write or
BG0 - BG1
BA0 - BA1
Input
Input
Precharge command is being applied. BG0 also determines which mode register is to be
accessed during a MRS cycle. x4/8 have BG0 and BG1 but x16 has only BG0
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
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ESMT
M16U4G16256A
Symbol
Type
Function
Address Inputs: Provide the row address for ACTIVATE Commands and the column
address for Read/ Write commands to select one location out of the memory array in the
respective bank. (A10/AP,A12/ BC_n, RAS_n, CAS_n/A15 and WE_n/A14 have additional
functions, see other rows.The address inputs also provide the op-code during Mode
Register Setcommands.
A0 - A15
A10 / AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge
command to determine whether thePrecharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.
Input
Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst
chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See
command truth table for details.
A12 / BC_n
RESET_n
Input
Input
Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive
when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC
code is added at the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal
Vref level during test via Mode Register Setting MR4 A4=High. During this mode, RTT
value should be set to Hi-Z. Refer to vendor specific datasheets to determine which DQ is
used.
DQ
Input / Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU
corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t and DQSU_t
are paired with differential signals DQS_c, DQSL_c and DQSU_c, respectively, to provide
differential pair signaling to the system during reads and writes. DDR4 SDRAM supports
differential data strobe only and does not support single-ended.
DQS_t, DQS_c,
DQSU_t, DQSU_c, Input / Output
DQSL_t, DQSL_c
Command and Address Parity Input : DDR4 Supports Even Parity check in DRAMs with
MRꢈ ꢐꢎttꢏꢊg.ꢈ ꢅꢊꢃꢎꢈ ꢏt’ꢐꢈ ꢎꢊꢉꢑꢒꢎꢋꢈ vꢏꢉꢈ Rꢎgꢏꢐtꢎꢍꢈ ꢏꢊꢈ MR5 ꢈ thꢎꢊꢈ ꢆRAM calculates Parity
withACT_n,RAS_n,CAS_n/A15,WE_n/ A14,BG0-BG1,BA0-BA1,A15-A0. Input parity
should maintain at the rising edge of the clock and at the same time with command &
address with CS_n LOW
PAR
ALERT_n
TEN
Input
Input/Output
Input
Alert : It has multi functions such as CRC error flag , Command and Address Parity error
flag as Output signal. If there is error in CRC, then Alert_n goes LOW for the period time
interval and goes back HIGH. If there is error in Command Address Parity Check, then
Alert_n goes LOW for relatively long period until on going DRAM internal recovery
transaction to complete. During Connectivity Test mode, this pin works as input.
Using this signal or not is dependent on system. In case of not connected as Signal,
ALERT_n Pin must be bounded to VDD on board.
Connectivity Test Mode Enable : Required on x16 devices and optional input on x4/x8 with
densities equal to or greater than 8Gb. HIGH in this pin will enable Connectivity Test Mode
operation along with other pins. It is a CMOS rail to rail signal with AC high and low at 80%
and 20% of VDD. Using this signal or not is dependent on System. This pin may be DRAM
internally pulled low through a weak pull-down resistor to VSS
.
NC
No Connect: No internal electrical connection is present.
DQ Power Supply: 1.2 V +/- 0.06 V
VDDQ
VSSQ
Supply
Supply
DQ Ground
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ESMT
M16U4G16256A
Power Supply: 1.2 V +/- 0.06 V
VDD
VSS
Supply
Supply
Supply
Supply
Supply
Ground
DRAM Activating Power Supply: 2.5V ( 2.375V min , 2.75V max)
Reference voltage for CA
VPP
VREFCA
ZQ
Reference Pin for ZQ calibration
Note: Input only pins (BG0-BG1, BA0-BA1, A0-A15, ACT_n, RAS_n, CAS_n/A15, W E_n/A14, CS_n, CKE, ODT, and
RESET_n) do not supplytermination.
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M16U4G16256A
Electrical Conditions
All voltages are referenced to VSS (GND)
Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Note
Power supply voltage
Power supply voltage for output
DRAM activation power supply
Input voltage
VDD
VDDQ
VPP
-0.3 to +1.5
-0.3 to +1.5
V
V
1, 3
1, 3
4
-0.3 to +3.0
V
VIN
-0.3 to +1.5
V
1
Output voltage
VOUT
VREFCA
Tstg
-0.3 to +1.5
V
1
Reference voltage
Storage temperature
Notes:
-0.3 to 0.6 x VDD
-55 to +100
V
3
1, 2
C
1.
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2.
3.
Storage temperature is the case surface temperature on the center/top side of the DRAM.
VDD and VDDQ must be within 300mV of each other at all times; and VREFCA must be no greater than 0.6 x VDDQ,
When VDD and VDDQ are less than 500mV; VREFCA may be equal to or less than 300mV.
VPP must be equal or greater than VDD/VDDQ at all times.
4.
Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Temperature Range
Symbol
Parameter
Value
0 to 85
85 to 95
Units
C
Notes
1
Normal Operating Temperature Range
Extended Temperature Range
TC
1,2
C
Note:
1. The normal temperature range specifies the temperatures at which all DRAM specifications will be supported. During
operation, the DRAM case temperature must be maintained between 0°C to 85°C under all operating conditions for the
commercial offering.
2. Some applications require operation of the commercial and industrial temperature DRAMs in the extended temperature
range (between 85°C and 95°C case temperature). Full specifications are supported in this range, but the following
additional conditions apply:
a) REFRESH commands must be doubled in frequency, reducing the refresh interval tREFI to 3.9us. It is also possible to
specify a component with 1X refresh (tREFI to 7.8us) in the extended temperature range.
b) If SELF REFRESH operation is required in the extended temperature range, it is mandatory to use either the manual
self refresh mode with extended temperature range capability (MR2[6] = 0 and MR2 [7] = 1) or enable the optional auto
self refresh mode (MR2 [6] = 1 and MR2 [7] = 1).
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M16U4G16256A
Operating Temperature Condition
Recommended DC Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Note
Supply voltage
Supply voltage for DQ
DRAM activating power
Ground
VDD
VDDQ
VPP
1.14
1.14
2.375
0
1.2
1.2
2.5
0
1.26
1.26
2.75
0
V
V
V
V
V
1, 2, 3
1, 2, 3
3
VSS
Ground for DQ
VSSQ
0
0
0
Notes:
1.
2.
3.
Under all conditions VDDQ must be less than or equal to VDD.
VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
DC bandwidth is limited to 20MHz.
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M16U4G16256A
IDD and IDDQ Specification Parameters and Test conditions
IDD, IPP and IDDQ Measurement Conditions
In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined.
The figure Measurement Setup and Test Load for IDD and IDDQ Measurements shows the setup and test load for IDD, IPP and
IDDQ measurements.
IDD currents (such as IDD0, IDD0A, IDD1, IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B,
IDD6N, IDD6E, IDD6A and IDD7) are measured as time-averaged currents with all VDD balls of the DDR4 SDRAM under
test tied together. Any IPP or IDDQ current is not included in IDD currents.
IPP currents have the same definition as IDD except that the current on the VPP supply is measured.
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the
DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Note: IDDQ values cannot be directly used to calculate I/O power of the DDR4 SDRAM. They can be used to support
correlation of simulated I/O power to actual I/O power as outlined in correlation from simulated channel I/O power to
actual channel I/O power supported by IDDQ measurement.
For IDD, IPP and IDDQ measurements, the following definitions apply:
L and 0: VIN VIL(AC) max
H and 1: VIN VIH(AC) min
MID-LEVEL: defined as inputs are VREFCA = VDD / 2
Timings used for IDD, IPP and IDDQ measurement-loop patterns are provided in Timings Used for IDD and IDDQ
Measurement-Loop Patterns table.
Basic IDD, IPP and IDDQ measurement conditions are described in Basic IDD, IPP and IDDQ Measurement Conditions
table.
Note:The IDD, IPP and IDDQ measurement-loop patterns need to be executed at least one time before actual IDD or
IDDQ measurement is started.
Detailed IDD, IPP and IDDQ measurement-loop patterns are described in IDD0 Measurement-Loop Pattern table through
IDD7 Measurement-Loop Pattern table.
IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not limited to setting.
RON = RZQ/7 (34Ω in MR1);
Qoff = 0B (Output buffer enabled in MR1);
RTT_Nom = RZQ/6 (40Ω in MR1);
RTT_WR = RZQ/2 (120Ω in MR2);
RTT_PARK = Disable;
TDQS_t feature disabled in MR1;
CRC disabled in MR2;
CA parity feature disabled in MR5;
Gear-down mode disabled in MR3;
Read/Write DBI disabled in MR5;
DM_n disabled in MR5
Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n} : = {H, L, L, L, L} ; apply BG/BA changes when directed.
Define /D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n} : = {H, H, H, H, H}; apply BG/BA changes when directed.
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M16U4G16256A
Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements
Correlation from Simulated Channel I/O Power to Actual Channel I/O Power Supported by IDDQ Measurement
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M16U4G16256A
Timings Used for IDD and IDDQ Measurement-Loop Patterns
Symbol
DDR4-2400 (17-17-17) DDR4-2666 (19-19-19) DDR4-3200 (24-24-24) Unit
tCK
CL
0.833
17
16
17
56
39
17
36
7
0.750
19
18
19
62
43
19
40
7
0.625
24
20
24
76
52
24
48
9
ns
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
CWL
nRCD
nRC
nRAS
nRP
nFAW
nRRDS
nRRDL
tCCD_S
tCCD_L
tWTR_S
tWTR_L
nRFC 4Gb
8
9
11
4
4
4
6
7
8
3
4
4
9
10
347
12
416
313
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M16U4G16256A
Basic IDD and IDDQ Measurement Conditions
Basic IDD, IPP and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current (AL=0)
CKE: H; External clock: on; tCK, nRC, nRAS, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: H
between ACT and PRE; Command, address, bank group address, bank address inputs: partially toggling
according to Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Measurement-Loop Pattern table); Output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0; Pattern details: see Measurement-Loop Pattern table
IDD0
Operating One Bank Active-Precharge Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD0
IDD0A
IPP0
Operating One Bank Active-Precharge IPP Current
Same condition with IDD0
Operating One Bank Active-Read-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0;
CS_n: H between ACT, RD and PRE; Command, address, bank group address, bank address inputs, data I/O:
partially toggling according to Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: cycling with one
bank active at a time: 0,0,1,1,2,2,... (see Measurement-Loop Pattern table); Output buffer and RTT: enabled in
MR*2; ODT Signal: stable at 0; Pattern details: see Measurement-Loop Pattern table
IDD1
Operating One Bank Active-Read-Precharge Current (AL=CL-1)
AL=CL-1, Other conditions : see IDD1
IDD1A
IPP1
Operating One Bank Active-Read-Precharge IPPCurrent
Same condition with IDD1
Precharge Standby Current (AL=0)
CKE: H; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address Inputs: partially toggling according to Measurement-Loop
Pattern table; data I/O: VDDQ; DM_n: stable at 1; bank activity: all banks closed; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0; pattern details: see Measurement-Loop Pattern table
IDD2N
Precharge Standby Current (AL=CL-1)
Same condition with IDD2N
IDD2NA
IPP2N
Precharge Standby IPP Current
AL = CL-1, Other conditions: see IDD2N
Precharge Standby ODT Current
CKE: H; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address Inputs: partially toggling according to Measurement-Loop
Pattern table; data I/O: VSSQ; DM_n: stable at 1; bank activity: all banks closed; output buffer and RTT: enabled in
MR*2; ODT signal: toggling according to Measurement-Loop Pattern table
IDD2NT
IDDQ2NT
(Optional)
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Standby Current with CAL enabled
Same definition like for IDD2N, CAL enabled*3
IDD2NL
IDD2NG
Precharge Standby Current with Gear Down mode enabled
Same definition like for IDD2N, Gear Down mode enabled*3,*5
Precharge Standby Current with DLL disabled
Same definition like for IDD2N, DLL disabled*3
IDD2ND
Precharge Standby Current with CA parity enabled
Same definition like for IDD2N, CA parity enabled*3
IDD2N_par
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Precharge Power-Down Current
CKE: Low; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address inputs: stable at 0; data I/O: VDDQ; DM_n: stable at 1;
bank activity: all banks closed; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0
IDD2P
IPP2P
IDD2Q
Precharge Power-Down IPP Current
Same condition with IDD2P
Precharge Quiet Standby Current
CKE: H; External clock: On; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address Inputs: stable at 0; data I/O: VDDQ; DM_n: stable at
1;bank activity: all banks closed; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0
Active Standby Current
CKE: H; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address Inputs: partially toggling according to Measurement-Loop
Pattern table; data I/O: VDDQ; DM_n: stable at 1; bank activity: all banks open; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0; pattern details: see Measurement-Loop Pattern table
IDD3N
Active Standby Current (AL=CL-1)
Same condition with IDD3N
IDD3NA
IPP3N
Active Standby IPP Current
AL = CL-1, Other conditions: see IDD3N
Active Power-Down Current
CKE: L; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: stable at 1;
Command, address, bank group address, bank address inputs: stable at 0; data I/O: VDDQ; DM_n:stable at 1;
bank activity: all banks open; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0
IDD3P
IPP3P
Active Power-Down IPP Current
Same condition with IDD3P
Operating Burst Read Current
CKE: H; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: H between RD;
Command, address, Bank group address, Bank address Inputs: partially toggling according to Measurement-Loop
Pattern table; data I/O: seamless read data burst with different data between one burst and the next one according
to Measurement-Loop Pattern table; DM_n: stable at 1;Bank activity: all Banks open, RD commands cycling
through banks: 0,0,1,1,2,2,... (see Measurement-Loop Pattern table); output buffer and RTT: enabled in MR*2;
ODT signal: stable at 0; pattern details: see Measurement-Loop Pattern table
IDD4R
Operating Burst Read Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4R
IDD4RA
IDD4RB
IPP4R
Operating Burst Read Current with Read DBI
Read DBI enabled*3, Other conditions: see IDD4R
Operating Burst Read IPP Current
Same condition with IDD4R
IDDQ4R Operating Burst Read IDDQ Current
(Optional) Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDDQ4RB Operating Burst Read IDDQ Current with Read DBI
(Optional) Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
CKE: H; External clock: on; tCK, CL: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: H between WR;
command, address, bank group address, bank address inputs: partially toggling according to Measurement-Loop
IDD4W
Pattern table; data I/O: seamless write data burst with different data between one burst and the next one according
to Measurement-Loop Pattern table;DM_n: stable at 1; bank activity: all banks open, WR commands cycling
through banks: 0,0,1,1,2,2,.. (see Measurement-Loop Pattern table); output buffer and RTT: enabled in MR*2;
ODT signal: stable at H; pattern details: see Measurement-Loop Pattern table
Operating Burst Write Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4W
IDD4WA
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ESMT
M16U4G16256A
Operating Burst Write Current with Write DBI
IDD4WB
IDD4WC
IDD4W_par
IPP4W
Write DBI enabled*3, Other conditions: see IDD4W
Operating Burst Write Current with Write CRC
Write CRC enabled*3, Other conditions: see IDD4W
Operating Burst Write Current with CA Parity
CA Parity enabled*3, Other conditions: see IDD4W
Operating Burst Write IPP Current
Same condition with IDD4W
Burst Refresh Current (1X REF)
CKE: H; External clock: on; tCK, CL, nRFC: see Measurement-Loop Pattern table; BL: 8*1; AL: 0; CS_n: H
between REF; Command, address, bank group address, bank address Inputs: partially toggling according to
Measurement-Loop Pattern table; data I/O: VDDQ; DM_n: stable at 1; bank activity: REF command every nRFC
(Measurement-Loop Pattern table); output buffer and RTT: enabled in MR*2; ODT signal: stable at 0; pattern
details: see Measurement-Loop Pattern table
IDD5B
Burst Refresh IPP Current (1X REF)
Same condition with IDD5B
IPP5B
IDD5F2
IPP5F2
IDD5F4
IPP5F4
Burst Refresh Current (2X REF)
tRFC=tRFC_x2, Other conditions: see IDD5B
Burst Refresh Write IPP Current (2X REF)
Same condition with IDD5F2
Burst Refresh Current (4X REF)
tRFC=tRFC_x4, Other conditions: see IDD5B
Burst Refresh Write IPP Current (4X REF)
Same condition with IDD5F4
Self Refresh Current: Normal Temperature Range
TC: 0 to 85°C; LP ASR: Normal*4; CKE: L; External clock: off; CK_t and CK_c: L; CL: see Measurement-Loop
Pattern table; BL: 8*1; AL: 0; CS_n, command, address, bank group address, bank address, data I/O: H; DM_n:
stable at 1; bank activity: self-refresh operation; Output buffer and RTT: enabled in MR*2; ODT signal: MID-LEVEL
IDD6N
IPP6N
Self Refresh IPP Current: Normal Temperature Range
Same condition with IDD6N
Self-Refresh Current: Extended Temperature Range
TC: 0 to 95°C; LP ASR: Extended*4; CKE: L; External clock: off; CK_t and CK_c: L; CL: see Measurement-Loop
Pattern table; BL: 8*1; AL: 0; CS_n, command, address, bank group address, bank address, data I/O: H; DM_n:
stable at 1; bank activity: Extended temperature self-refresh operation; Output buffer and RTT: enabled in MR*2;
ODT signal: MID-LEVEL
IDD6E
IPP6E
IDD6R
Self Refresh IPP Current: Extended Temperature Range
Same condition with IDD6E
Self-Refresh Current: Reduced Temperature Range
TC: 0 to 45°C; LP ASR: Reduced*4; CKE: L; External clock: off; CK_t and CK_c: L; CL: see Measurement-Loop
Pattern table; BL: 8*1; AL: 0; CS_n, command, address, bank group address, bank address, data I/O: H; DM_n:
stable at 1; bank activity: Reduced temperature self-refresh operation; Output buffer and RTT: enabled in MR*2;
ODT signal: MID-LEVEL
Self Refresh IPP Current: Reduced Temperature Range
Same condition with IDD6R
IPP6R
IDD6A
IPP6A
Auto Self Refresh Current
TC: 0 to 95°C; LP ASR: Auto*4; CKE: L; External clock: off; CK_t and CK_c: L; CL: see Measurement-Loop Pattern
table; BL: 8*1; AL: 0; CS_n, command, address, bank group address, bank address, data I/O: H; DM_n: stable at
1; bank activity: auto self-refresh operation; Output buffer and RTT: enabled in MR*2; ODT signal: MID-LEVEL
Auto Self Refresh IPP Current
Same condition with IDD6A
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ESMT
M16U4G16256A
Operating Bank Interleave Read Current
CKE: H; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Measurement-Loop Pattern table; BL:
8*1 ; AL: CL-1; CS_n: H between ACT and RDA; Command, address, bank group address, bank address Inputs:
partially toggling according to Measurement-Loop Pattern table; data I/O: read data bursts with different data
between one burst and the next one according to Measurement-Loop Pattern table; DM_n: stable at 1; bank
ꢉꢃtꢏvꢏty:ꢈtwoꢈtꢏmꢎꢐꢈꢏꢊtꢎꢍꢒꢎꢉvꢎꢋꢈꢃyꢃꢒꢏꢊgꢈthꢍoughꢈꢑꢉꢊkꢐꢈ(0 ꢈ1 ꢈ…7)ꢈwꢏthꢈꢋꢏffꢎꢍꢎꢊtꢈꢉꢋꢋꢍꢎꢐꢐꢏꢊg ꢈꢐꢎꢎ Measurement-Loop
Pattern table; output buffer and RTT: enabled in MR*2; ODT signal: stable at 0; pattern details: see
Measurement-Loop Pattern table
IDD7
Operating Bank Interleave Read IPP Current
Same condition with IDD7
IPP7
IDD8
IPP8
Maximum Power Down Current
TBD
Maximum Power Down IPP Current
Same condition with IDD8
Note:
1.
2.
Burst Length: BL8 fixed by MRS: MR0 bits A[1,0] = [0,0].
MR: Mode Register
Output buffer enable:
set MR1 bit A12 = 0: Qoff = output buffer enabled
and MR1 bits A[2, 1] = [0,0]: output driver impedance control = RZQ/7
RTT_Nom enable:
set MR1 bits A[10:8] = [0,1,1]: RTT_Nom = RZQ/6
RTT_WR enable:
set MR2 bits A[11:9] = [0,0,1]: RTT_WR = RZQ/2
RTT_PARK disable:
set MR5 bits A[8:6] = [0,0,0]
CAL enabled:
3.
set MR4 bits A[8:6] = [0,0,1]: 1600MT/s;
[0,1,0]: 1866MT/s, 2133MT/s;
[0,1,1]: 2400MT/s
[0,1,1]: 2666MT/s
[1,0,0]: 3200MT/s
Gear down mode enabled :
set MR3 bit A3 = 1: 1/4 Rate
DLL disabled:
set MR1 bit A0 = 0
CA parity enabled:
set MR5 bits A[2:0] = [0,0,1]: 1600MT/s,1866MT/s, 2133MT/s
[0,1,0]: 2400MT/s, 2666MT/s
[0,1,1]: 3200MT/s
Read DBI enabled:
set MR5 bit A12 = 1
Write DBI enabled:
set :MR5 bit A11 = 1
4.
Low Power Array Self-Refresh (LP ASR)
set MR2 bits A[7:6] = [0,0]: Normal
[0,1]: Reduced temperature range
[1,0]: Extended temperature range
[1,1]: Auto self-refresh
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ESMT
IDD0, IDD0A and IPP0 Measurement-Loop Pattern1
M16U4G16256A
Data4
0
ACT
D, D
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
-
-
-
1, 2
3, 4
…
D#, D#
32
0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
repeat pattern 1...4 until nRC - 1, truncate if necessary
nRAS
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
-
…
1
2
3
4
5
6
7
8
9
1*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
2*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
5*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead
6*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
7*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead
8*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
9*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead
10 10*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
11 11*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead
12 12*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
13 13*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead
14 14*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
15 15*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead
Note :
1.
2.
3.
4.
DQS_t, DQS_c are VDDQ.
BG1ꢈꢏꢐꢈꢋoꢊ’tꢈꢃꢉꢍꢎꢈfoꢍꢈx16ꢈꢋꢎvꢏꢃꢎ
C[2:0] are used only for 3DS device
DQ signals are VDDQ.
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ESMT
IDD1, IDD1A and IPP1 Measurement-Loop Pattern1
M16U4G16256A
Data4
0
ACT
D, D
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
F
0
0
0
-
-
-
1, 2
3, 4
…
D#, D#
32
repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary
D0=00
D1=FF
D2=FF
D3=00
D4=FF
D5=00
0
nRCD
-AL
RD
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
…
nRAS
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
repeat pattern 1...4 until nRC - 1, truncate if necessary
0
1
0
1
0
0
0
0
0
-
1*nRC
+ 0
-
-
-
ACT
D, D
0
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
1
0
1
0
3
0
0
0
0
0
0
0
0
0
0
0
7
0
0
0
0
1*nRC
+ 1, 2
1*nRC
+ 3, 4
0
F
D#, D#
32
...
repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if necessary
D0=FF
D1=00
D2=00
D3=FF
D4=00
1
1*nRC
+nRCD
- AL
RD
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary
1*nRC
+ nRAS
0
1
0
1
0
0
0
0
0
-
...
2
3
4
5
6
8
9
2*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
3*nRC repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
4*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1instead
5*nRC repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2instead
6*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
7*nRC repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
9*nRC repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 0instead
10 10*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1instead
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ESMT
M16U4G16256A
11 11*nRC repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 2 instead
12 12*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3instead
13 13*nRC repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 1instead
14 14*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead
15 15*nRC repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 3 instead
16 16*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0instead
Note :
1.
2.
3.
4.
DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ
BG1ꢈꢏꢐꢈꢋoꢊ’tꢈꢃꢉꢍe for x16 device
C[2:0] are used only for 3DS device
Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.
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ESMT
M16U4G16256A
IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2N_par, IPP2, IDD3N, IDD3NA, and IDD3P Measurement-Loop
Pattern1
Data4
0
D, D
D, D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
0
0
F
F
0
0
0
0
0
0
0
0
1
0
2
D#, D#
32
32
3
D#, D#
1
2
4-7
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead
8-11
12-15
16-19
20-23
24-27
28-31
32-35
36-39
40-43
44-47
48-51
52-55
56-59
60-63
3
4
5
6
7
8
9
10
11
12
13
14
15
Note :
1.
2.
3.
4.
DQS_t, DQS_c are VDDQ
BG1ꢈꢏꢐꢈꢋoꢊ’tꢈꢃꢉꢍꢎꢈfoꢍꢈx16ꢈꢋꢎvꢏꢃꢎ
C[2:0] are used only for 3DS device
DQ signals are VDDQ
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ESMT
IDD2NT and IDDQ2NT Measurement-Loop Pattern1
M16U4G16256A
Data4
0
D, D
D, D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
0
0
F
F
0
0
0
0
-
-
-
-
1
0
2
D#, D#
32
32
3
D#, D#
1
2
4-7
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 1 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 0 instead
8-11
12-15
16-19
20-23
24-27
28-31
32-35
36-39
40-43
44-47
48-51
52-55
56-59
60-63
3
4
5
6
7
8
9
10
11
12
13
14
15
Note :
1.
2.
3.
4.
DQS_t, DQS_c are VDDQ.
BG1ꢈꢏꢐꢈꢋoꢊ’tꢈꢃꢉꢍꢎꢈfoꢍꢈx16ꢈꢋꢎvꢏꢃꢎ
C[2:0] are used only for 3DS device
DQ signals are VDDQ
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ESMT
M16U4G16256A
IDD4R, IDD4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern1
Data4
D0=00
D1=FF
D2=FF
D3=00
D4=FF
D5=00
D6=00
D7=FF
0
RD
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
D
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
2,3
D#, D#
32
D0=FF
D1=00
D2=00
D3=FF
D4=00
D5=FF
D6=FF
D7=00
4
RD
0
1
1
0
1
0
0
1
1
0
0
0
7
F
0
1
5
D
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
6,7
D#, D#
32
2
3
8-11
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
12-15
16-19
20-23
24-27
28-31
32-35
36-39
40-43
44-47
48-51
52-55
56-59
60-63
4
5
6
7
8
9
10
11
12
13
14
15
Note :
1.
2.
3.
4.
QS_t, DQS_c are used according to RD Commands, otherwise VDDQ
BG1ꢈꢏꢐꢈꢋoꢊ’tꢈꢃꢉꢍꢎꢈfoꢍꢈx16ꢈꢋꢎvꢏꢃꢎ
C[2:0] are used only for 3DS device
Burst Sequence driven on each DQ signal by Read Command
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 21/53
ESMT
M16U4G16256A
IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern1
Data4
D0=00
D1=FF
D2=FF
D3=00
D4=FF
D5=00
D6=00
D7=FF
0
WR
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
D
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
2,3
D#, D#
32
D0=FF
D1=00
D2=00
D3=FF
D4=00
D5=FF
D6=FF
D7=00
4
WR
0
1
1
0
0
1
0
1
1
0
0
0
7
F
0
1
5
D
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
6,7
D#, D#
32
2
3
8-11
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
12-15
16-19
20-23
24-27
28-31
32-35
36-39
40-43
44-47
48-51
52-55
56-59
60-63
4
5
6
7
8
9
10
11
12
13
14
15
Note :
1.
2.
3.
4.
DQS_t, DQS_c are used according to W R Commands, otherwise VDDQ
BG1ꢈꢏꢐꢈꢋoꢊ’tꢈꢃꢉꢍꢎꢈfoꢍꢈx16ꢈꢋꢎvꢏꢃꢎ
C[2:0] are used only for 3DS device
Burst Sequence driven on each DQ signal by Write Command
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 22/53
ESMT
M16U4G16256A
IDD4WC Measurement-Loop Pattern1
Data4
D0=00
D1=FF
D2=FF
D3=00
0
WR
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
D4=FF
D5=00
0
D6=00
D7=FF
D8=CRC
1,2
3,4
D, D
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
D#, D#
32
D0=FF
D1=00
D2=00
D3=FF
D4=00
D5=FF
D6=FF
D7=00
D8=CRC
5
WR
0
1
1
0
0
1
0
1
1
0
0
0
7
F
0
1
6,7
D, D
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
8,9
D#, D#
32
2
3
10-14
15-19
20-24
25-29
30-34
35-39
40-44
45-49
50-54
55-59
60-64
65-69
70-74
75-79
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
4
5
6
7
8
9
10
11
12
13
14
15
Note :
1.
2.
3.
4.
DQS_t, DQS_c are used according to W R Commands, otherwise VDDQ
BG1ꢈꢏꢐꢈꢋoꢊ’tꢈꢃꢉꢍꢎꢈfoꢍꢈx16ꢈꢋꢎvꢏꢃꢎ
C[2:0] are used only for 3DS device
Burst Sequence driven on each DQ signal by Write Command
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 23/53
ESMT
IDD5B Measurement-Loop Pattern1
M16U4G16256A
Data4
0
0
REF
D
0
1
1
1
1
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
7
0
0
0
F
F
0
0
0
0
0
-
-
-
-
-
1
2
D
0
3
D#, D#
D#, D#
32
32
4
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 1 instead
repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 3 instead
repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 2 instead
repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 0 instead
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 2 instead
repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 0 instead
5-8
9-12
13-16
17-20
21-24
25-28
29-32
33-36
37-40
41-44
45-48
49-52
53-56
57-60
61-64
1
65...
nRFC - 1
2
repeat Sub-Loop 1, Truncate, if necessary
Note :
1.
2.
3.
4.
DQS_t, DQS_c are VDDQ
BG1ꢈꢏꢐꢈꢋoꢊ’tꢈꢃꢉꢍꢎꢈfor x16 device
C[2:0] are used only for 3DS device
DQ signals are VDDQ
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 24/53
ESMT
IDD7 Measurement-Loop Pattern1
M16U4G16256A
Data4
0
1
ACT
RDA
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
-
D0=00
D1=FF
D2=FF
D3=00
D4=FF
D5=00
D6=00
D7=FF
0
2
3
D
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
3
0
0
0
0
0
0
0
7
0
F
0
0
-
-
D#
32
...
repeat pattern 2...3 until nRRD - 1, if nRCD > 4. Truncate if necessary
nRRD
ACT
RDA
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
-
D0=FF
D1=00
D2=00
D3=FF
D4=00
D5=FF
D6=FF
D7=00
1
0
1
1
0
1
0
0
1
0
0
1
nRRD +1
...
repeat pattern 2 ... 3 until 2*nRRD - 1, if nRCD > 4. Truncate if necessary
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead
2
3
4
2*nRRD
3*nRRD
4*nRRD
repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRCD. Truncate if necessary
5
6
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead
nFAW
nFAW +
nRRD
nFAW +
2*nRRD
nFAW +
3*nRRD
nFAW +
4*nRRD
7
8
9
repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead
repeat Sub-Loop 4
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 25/53
ESMT
IDD7 Measurement-Loop Pattern1- continued
M16U4G16256A
Data4
10
11
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead
2*nFAW
2*nFAW +
nRRD
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead
repeat Sub-Loop 4
2*nFAW +
2*nRRD
2*nFAW +
3*nRRD
2*nFAW +
4*nRRD
12
13
14
15
16
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead
3*nFAW
3*nFAW
nRRD
+
+
+
+
3*nFAW
2*nRRD
3*nFAW
3*nRRD
3*nFAW
4*nRRD
17
18
19
repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead
repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead
repeat Sub-Loop 4
20 4*nFAW
repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary
Note :
1.
2.
3.
4.
DQS_t, DQS_c are VDDQ
BG1ꢈꢏꢐꢈꢋoꢊ’tꢈꢃꢉꢍꢎꢈfoꢍꢈx16ꢈꢋꢎvꢏꢃꢎ
C[2:0] are used only for 3DS device
Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 26/53
ESMT
M16U4G16256A
Electrical Specifications
IDD Specifications
IDD and IPP values are for full operating range of voltage and temperature unless otherwise noted.
IDD and IDDQ Specification
Symbol
IDD0
DDR4-2400
86
DDR4-2666
92
DDR4-3200
104
105
170
174
88
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD0A
87
93
IDD1
128
122
67
142
146
74
IDD1A
IDD2N
IDD2NA
IDD2NT
IDD2NL
IDD2NG
IDD2ND
IDD2N_par
IDD2P
68
75
89
86
97
104
71
59
63
65
71
83
49
52
58
82
94
98
40
44
52
IDD2Q
67
75
91
IDD3N
78
86
102
97
IDD3NA
IDD3P
79
85
64
67
73
IDD4R
188
197
190
211
227
199
194
215
170
179
147
234
30
205
227
206
230
266
215
210
204
180
189
160
235
30
254
254
231
283
282
284
307
332
209
220
185
302
30
IDD4RA
IDD4RB
IDD4W
IDD4WA
IDD4WB
IDD4WC
IDD4W _par
IDD5B
IDD5F2
IDD5F4
IDD7
IDD8
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1
27/53
ESMT
M16U4G16256A
IPP Specification
Symbol
IPP0
DDR4-2400
DDR4-2666
DDR4-3200
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
8
8
9
9
11
11
9
IPP1
IPP2N
6
7
IPP2P
6
7
9
IPP3N
6
7
9
IPP3P
6
7
9
IPP4R
6
7
9
IPP4W
IPP5B
6
7
9
24
25
18
33
2
27
29
20
40
3
33
37
24
54
5
IPP5F2
IPP5F4
IPP7
IPP8
IDD6 Specification
Symbol
Value
DDR4-2400/ 2666/ 3200
Unit
Notes
IDD (max)
IPP (Max)
IDD6N
IDD6E
0 - 85°C
0 - 95°C
0 - 45°C
0 - 85°C
30
36
25
30
6
8
4
6
mA
mA
mA
mA
1
2
3
4
IDD6R
IDD6A
Note :
1.
2.
Applicable for MR2 settings A6 = 0 and A7 = 0
Applicable for MR2 settings A6 = 0 and A7 = 1. IDD6E is only specified for devices which support the extended
temperature range feature
3.
4.
Applicable for MR2 settings A6 = 1 and A7 = 0. IDD6R is only specified for devices which support the reduced temperature
range feature
Applicable for MR2 settings A6 = 1 and A7 = 1. IDD6A is only specified for devices which support the auto self-refresh
feature
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
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ESMT
M16U4G16256A
Input/Output Capacitance
Silicon pad I/O Capacitance
DDR4- 2400/ 2666
DDR4- 3200
Symbol
Parameter
Units
Note
Min.
0.55
-0.1
Min.
1.15
0.1
Min.
0.55
-0.1
Max.
1.00
0.1
CIO
Input/output capacitance
pF
pF
1,2,3
CDIO
Input/output capacitance delta
1,2,3,11
Input/output capacitance delta DQS_t
and DQS_c
CDDQS
-
0.05
-
0.05
pF
1,2,3,5
CCK
Input capacitance, CK_t and CK_c
0.2
-
0.7
0.2
-
0.7
pF
pF
1,3
CDCK
Input capacitance delta CK_t and CK_c
0.05
0.05
1,3,4
Input capacitance
CI
0.2
-0.1
-0.1
0.7
0.1
0.1
0.2
-0.1
-0.1
0.55
0.1
pF
pF
pF
1,3,6
1,3,7,8
1,2,9,10
(CTRL, ADD, CMD pins only)
Input capacitance delta
(All CTRL pins only)
CDI_ CTRL
CDI_ ADD_CMD
Input capacitance delta
(All ADD/CMD pins only)
0.1
CALERT
CZQ
Input/output capacitance of ALERT
Input/output capacitance of ZQ
Input capacitance of TEN
0.5
-
1.5
2.3
2.3
0.5
-
1.5
2.3
2.3
pF
pF
pF
1,3
1,3,12
1,3,13
CTEN
0.2
0.2
Note:
1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is
validated by de-embedding the package L & C parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ
applied with all other signal pins floating. Measurement procedure TBD.
2. DQ, DM_n, DQS_T, DQS_C, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions,
the loading matches DQ and DQS
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value CK_T-CK_C
5. Absolute value of CIO(DQS_T)-CIO(DQS_C)
6. CI applies to ODT, CS_n, CKE, A0-A15, BA0-BA1, BG0-BG1, RAS_n, CAS_n/A15, W E_n/A14, ACT_n and PAR.
7. CDI CTRL applies to ODT, CS_n and CKE
8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C))
9. CDI_ADD_ CMD applies to, A0-A15, BA0-BA1, BG0-BG1,RAS_n, CAS_n/A15, W E_n/A14, ACT_n and PAR.
10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C))
11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_C))
12. Maximum external load capacitance on ZQ pin: TBD pF.
13. TEN pin is DRAM internally pulled low through a weak pull-down resistor to VSS.
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 29/53
ESMT
M16U4G16256A
DRAM package electrical specifications
DDR4- 2400/ 2666/ 3200
Symbol
Parameter
Units
Note
Min.
45
14
-
Max.
85
ZIO
TdIO
Lio
Input/output Zpkg
Ω
ps
nH
pF
Ω
1
1
Input/output Pkg Delay
Input/Output Lpkg
45
3.4
0.82
85
1,2
1,3
1
Cio
Input/Output Cpkg
-
ZIO DQS
TdIO DQS
Lio DQS
DQS_t, DQS_c Zpkg
DQS_t, DQS_c Pkg Delay
DQS Lpkg
45
14
-
45
ps
nH
pF
Ω
1
3.4
0.82
10
1,2
1,3
-
Cio DQS
DQS Cpkg
-
Delta Zpkg DQSU_t, DQSU_c
Delta Zpkg DQSL_t, DQSL_c
Delta Delay DQSU_t, DQSU_c
Delta Delay DQSL_t, DQSL_c
Input- CTRL pins Zpkg
Input- CTRL pins Pkg Delay
Input CTRL Lpkg
-
DZDIO DQS
-
10
Ω
-
-
5
ps
ps
Ω
-
DTdDIO DQS
-
5
-
ZI CTRL
TdI_ CTRL
Li CTRL
50
14
-
90
1
42
ps
nH
pF
Ω
1
3.4
0.7
90
1,2
1,3
1
Ci CTRL
ZIADD CMD
TdIADD_ CMD
Li ADD CMD
Ci ADD CMD
ZCK
Input CTRL Cpkg
-
Input- CMD ADD pins Zpkg
Input- CMD ADD pins Pkg Delay
Input CMD ADD Lpkg
Input CMD ADD Cpkg
CLK_t & CLK_c Zpkg
CLK_t & CLK_c Pkg Delay
Input CLK Lpkg
50
14
-
52
ps
nH
pF
Ω
1
3.9
0.86
90
1,2
1,3
1
-
50
14
-
TdCK
42
ps
nH
pF
Ω
1
Li CLK
3.4
0.7
10
1,2
1,3
-
Ci CLK
Input CLK Cpkg
-
DZDCK
DTdCK
Delta Zpkg CLK_t & CLK_c
Delta Delay CLK_t & CLK_c
ZQ Zpkg
-
-
5
ps
Ω
-
ZOZQ
-
100
90
-
TdO ZQ
ZO ALERT
TdO ALERT
ZQ Delay
20
40
20
ps
Ω
-
ALERT Zpkg
100
55
-
ALERT Delay
ps
-
Note:
1.
Package implementations shall meet spec if the Zpkg and Pkg Delay fall within the ranges shown, and the maximum Lpkg
and Cpkg do not exceed the maximum value shown
2.
3.
It is assumed that Lpkg can be approximated as Lpkg = Zo*Td
It is assumed that Cpkg can be approximated as Cpkg = Td/Zo
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ESMT
M16U4G16256A
Standard Speed Bins
DDR4-2400 Speed Bins
Speed Bins
DDR4-2400 (17-17-17)
Unit
Note
Parameter
Symbol
Min
Max
14.1614
Internal read command to first data
tAA
18.00
ns
ns
ns
10
10
10
(13.75)5,12
Internal read command to first data with
read DBI enabled
tAA_DBI
tRCD
tAA(min) + 3nCK
tAA(max) +3nCK
-
14.16
(13.75)5,12
14.16
ACT to internal read or write delay time
PRE command period
tRP
tRAS
tRC
-
ns
ns
ns
10
10
10
(13.75)5,12
ACT to PRE command period
ACT to ACT or REF command period
32
9 x tREFI
-
46.16
(45.75)5,12
Normal
Read DBI
CL = 11
CL = 9
tCK(AVG)
Reserved
ns
1,2,3,4,9
(Optional)5
CWL =9
CL = 10
CL = 10
CL = 12
CL = 12
tCK(AVG)
tCK(AVG)
1.5
1.6
ns
ns
1,2,3,4,9
4
Reserved
1.25
1.25
<1.5
CWL = 9,11
CL = 11
CL = 13
tCK(AVG)
ns
1,2,3,4,6
(Optional)5,12
Reserved
CL = 12
CL = 12
CL = 14
CL = 14
tCK(AVG)
tCK(AVG)
<1.5
ns
ns
1,2,3,6
4
1.071
1.071
0.938
0.938
<1.25
<1.25
<1.071
<1.071
CWL = 10,12
CWL = 11,14
CWL = 12,16
CL = 13
CL = 15
tCK(AVG)
ns
1,2,3,4,6
(Optional)5,12
Reserved
CL = 14
CL = 14
CL = 16
CL = 17
tCK(AVG)
tCK(AVG)
ns
ns
1,2,3,6
4
CL = 15
CL = 18
tCK(AVG)
ns
1,2,3,4,6
(Optional)5,12
CL = 16
CL = 15
CL = 16
CL = 17
CL = 18
CL = 19
CL = 18
CL = 19
CL = 20
CL = 21
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
ns
ns
1,2,3,6
1,2,3,4
1,2,3,4
Reserved
Reserved
ns
0.833
0.833
<0.938
<0.938
ns
ns
1,2,3
11
Supported CL Settings
10,11,12,13,14,15,16,17,18
12,13,14,15,16,18,19,20,21
9,10,11,12,14,16
nCK
nCK
nCK
Supported CL Settings with read DBI
Supported CWL Settings
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M16U4G16256A
DDR4-2666 Speed Bins
Speed Bins
DDR4-2666 (19-19-19)
Unit
Note
Parameter
Symbol
Min
Max
14.2514
Internal read command to first data
tAA
18.00
ns
ns
ns
10
10
10
(13.75)5,12
Internal read command to first data with
read DBI enabled
tAA_DBI
tRCD
tAA(min) + 3nCK
tAA(max) +3nCK
-
14.25
(13.75)5,12
14.25
ACT to internal read or write delay time
PRE command period
tRP
tRAS
tRC
-
ns
ns
ns
10
10
10
(13.75)5,12
ACT to PRE command period
ACT to ACT or REF command period
32
9 x tREFI
-
46.25
(45.75)5,12
Normal
CL = 9
Read DBI
CL = 11
CL = 12
CL = 12
tCK(AVG)
tCK(AVG)
tCK(AVG)
Reserved
ns
ns
ns
1,2,3,4,9
1,2,3,4,9
4
CWL =9
CL = 10
CL = 10
1.5
1.6
<1.5
Reserved
1.25
1.25
CWL = 9,11
CL = 11
CL = 13
tCK(AVG)
ns
1,2,3,4,7
(Optional)5,12
Reserved
CL = 12
CL = 12
CL = 14
CL = 14
tCK(AVG)
tCK(AVG)
<1.5
ns
ns
1,2,3,7
4
1.071
1.071
0.937
0.937
<1.25
<1.25
<1.071
<1.071
CWL = 10,12
CWL = 11,14
CL = 13
CL = 15
tCK(AVG)
ns
1,2,3,4,7
(Optional)5,12
Reserved
CL = 14
CL = 14
CL = 16
CL = 17
tCK(AVG)
tCK(AVG)
ns
ns
1,2,3,7
4
CL = 15
CL = 18
tCK(AVG)
ns
1,2,3,4,7
(Optional)5,12
CL = 16
CL = 15
CL = 16
CL = 19
CL = 18
CL = 19
tCK(AVG)
tCK(AVG)
tCK(AVG)
ns
ns
ns
1,2,3,7
4
Reserved
Reserved
1,2,3,4,7
CWL = 12,16
CWL = 14,18
0.833
0.833
<0.937
<0.937
CL = 17
CL = 20
tCK(AVG)
ns
1,2,3,4,7
(Optional)5,12
CL = 18
CL = 17
CL = 18
CL = 19
CL = 20
CL = 21
CL = 20
CL = 21
CL = 22
CL = 23
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
ns
ns
1,2,3
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3
Reserved
Reserved
ns
0.75
0.75
<0.833
<0.833
ns
ns
Supported CL Settings
10,11,12,13,14,15,16,17,18,19,20
12,13,14,15,16,18,19,20,21,22,23
9,10,11,12,14,16,18
nCK
nCK
nCK
11
Supported CL Settings with read DBI
Supported CWL Settings
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M16U4G16256A
DDR4-3200 Speed Bins
Speed Bins
DDR4-3200 (24-24-24)
Unit
Note
Parameter
Symbol
Min
Max
Internal read command to first data
tAA
15.00
19.00
ns
ns
10
10
Internal read command to first data with
read DBI enabled
tAA_DBI
tAA(min) + 4nCK
tAA(min) + 4nCK
ACT to internal read or write delay time
PRE command period
tRCD
tRP
15.00
15.00
-
ns
ns
ns
ns
10
10
10
10
-
ACT to PRE command period
ACT to ACT or REF command period
tRAS
tRC
32
9 x tREFI
-
tRAS + tRP
Normal
CL = 9
Read DBI
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL = 17
CL = 18
CL = 19
CL = 18
CL = 19
CL = 20
CL = 21
CL = 20
CL = 21
CL = 22
CL = 23
CL = 24
CL = 26
CL = 28
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Reserved
ns
ns
1,2,3,4,9
1,2,3,4,9
1,2,3,4
1,2,3,4,8
1,2,3,8
1,2,3,4
1,2,3,4,8
1,2,3,8
1,2,3,4
1,2,3,4,8
1,2,3,8
1,2,3,4
1,2,3,4,8
1,2,3,4,8
1,2,3,8
1,2,3,4
1,2,3,4,8
1,2,3,4,8
1,2,3,8
1,2,3,4
1,2,3,4
1,2,3
CWL =9
CL = 10
CL = 10
CL = 11
CL = 12
CL = 12
CL = 13
CL = 14
CL = 14
CL = 15
CL = 16
CL = 15
CL = 16
CL = 17
CL = 18
CL = 17
CL = 18
CL = 19
CL = 20
CL = 20
CL = 22
CL = 24
1.5
1.9
<1.5
Reserved
ns
CWL = 9,11
Reserved
ns
1.25
1.071
0.937
ns
Reserved
Reserved
ns
CWL = 10,12
CWL = 11,14
ns
<1.25
<1.071
ns
Reserved
Reserved
ns
ns
ns
Reserved
Reserved
Reserved
ns
ns
CWL = 12,16
ns
0.833
<0.937
ns
Reserved
Reserved
Reserved
ns
ns
CWL = 14,18
CWL = 16,20
ns
0.75
<0.833
<0.682
ns
Reserved
Reserved
ns
ns
0.625
ns
Supported CL Settings
10,12,14,16,18,20,22,24
12,14,16,19,21,23,28
9,10,11,12,14,16,18,20
nCK
nCK
nCK
11
Supported CL Settings with read DBI
Supported CWL Settings
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M16U4G16256A
Speed Bin Table Notes
Absolute Specification
VDDQ = VDD = 1.20V +/- 0.06 V
VPP = 2.5V +0.25/-0.125 V
The values defined with above-mentioned table are DLL ON case.
DDR4-2400, 2666 and 3200 Speed Bin Tables are valid only when Geardown Mode is disabled.
1.
2.
The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of
tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all
possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard
tCK(avg) value (1.5, 1.25, 1.071, 0.938 or 0.833 ns) when calculating CL [nCK] = tAA [ns] / tCK(avg) [ns], rounding up to
thꢎꢈꢊꢎxtꢈ‘SuppoꢍtꢎꢋꢈꢀL’ ꢈwhꢎꢍꢎꢈtAAꢈ=ꢈ12.5ꢊꢐꢈꢉꢊꢋꢈtꢀꢁ(ꢉvg)ꢈ=ꢈ1.3ꢈꢊꢐꢈꢐhouꢒꢋꢈoꢊꢒyꢈꢑꢎꢈuꢐꢎꢋꢈfoꢍꢈꢀLꢈ=ꢈ10ꢈꢃꢉꢒꢃuꢒꢉtꢏoꢊ.
tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next
valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.938 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to
CL SELECTED.
3.
4.
5.
‘Rꢎꢐꢎꢍvꢎꢋ’ꢈꢐꢎttꢏꢊgꢐꢈꢉꢍꢎꢈꢊotꢈꢉꢒꢒowꢎꢋ.ꢈUꢐꢎꢍꢈmuꢐtꢈpꢍogꢍꢉmꢈꢉꢈꢋꢏffꢎꢍꢎꢊt value.
'Optional' settings allow certain devices in the industry to support this setting, however, it is not
a mandatory feature.
Refer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported.
6.
7.
8.
9.
Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not
subject to Production Tests but verified by Design/Characterization.
Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are not
subject to Production Tests but verified by Design/Characterization.
Any DDR4-3200 speed bin also supports functional operation at lower frequencies as shown in the table which are not
subject to Production Tests but verified by Design/Characterization.
DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.
10. Parameter apply from tCK(avg)min to tCH(avg)max at all standard JEDEC clock period values as stated in the Speed Bin
Tables.
11. CL number in parentheses, it means that these numbers are optional.
12. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).
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M16U4G16256A
Electrical Characteristics & AC Timing
Reference Load for AC Timing and Output Slew Rate
Figure represents the effective reference load of 50 ohms used in defining the relevant AC timing parameters of the device as
well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by
a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a
system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission
lines terminated at the tester electronics.
Reference Load for AC Timing and Output SlewRate
tREFI
Average periodic Refresh interval (tREFI) of DDR4 SDRAM is defined as shown in the table.
tREFI by device density
Parameter
Symbol
0°C≦TC≦85°C
85°C< TC≦95°C
4Gb
7.8
Units
us
tREFI
Average periodic refresh interval
3.9
us
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M16U4G16256A
Timing Parameters by Speed Grade
Timing Parameters by Speed Bin for DDR4-2400
DDR4-2400
Parameter
Symbol
Units
Max.
Note
Min.
Clock Timing
Minimum Clock Cycle Time (DLL
off mode)
tCK
8
20
ns
(DLL_OFF)
tCK(avg)
tCH(avg)
tCL(avg)
Average Clock Period
Average high pulse width
Average low pulse width
Absolute Clock Period
0.833
0.48
< 0.938
ns
35,36
0.52
tCK(avg)
tCK(avg)
0.48
0.52
tCK(avg)min
+
tCK(avg)max
+
tCK(abs)
tCK(avg)
tJIT(per)min
_ tot
tJIT(per)max
_ tot
-
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
Clock Period Jitter- total
tCH(abs)
tCL(abs)
0.45
tCK(avg)
tCK(avg)
ps
23
24
25
26
0.45
-
JIT(per)_tot
JIT(per)_dj
-42
42
21
Clock Period Jitter- deterministic
Clock Period Jitter during DLL
locking period
-21
ps
tJIT(per, lck)
tJIT(cc)_total
tJIT(cc)_dj
-33
33
ps
ps
ps
Cycle to Cycle Period Jitter
Cycle to Cycle Period
83
42
25
26
Jitterdeterministic
Cycle to Cycle Period Jitter
during DLL locking period
tJIT(cc, lck)
67
ps
Duty Cycle Jitter
tJIT(duty)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
tERR(13per)
tERR(14per)
tERR(15per)
tERR(16per)
tERR(17per)
tERR(18per)
TBD
-61
TBD
61
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across 13 cycles
Cumulative error across 14 cycles
Cumulative error across 15 cycles
Cumulative error across 16 cycles
Cumulative error across 17 cycles
Cumulative error across 18 cycles
Cumulative error across
-73
73
-81
81
-87
87
-92
92
-97
97
-101
-104
-107
-110
-112
-114
-116
-118
-120
-122
-124
101
104
107
110
112
114
116
118
120
122
124
tERR(nper)min = ((1 + 0.68ln(n)) * tJIT(per)_total min)
tERR(nper)max = ((1 + 0.68ln(n)) * tJIT(per)_total max)
tERR(nper)
ps
n = 13, 14 ... 49, 50 cycles
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M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2400- continued
DDR4-2400
Parameter
Symbol
Units
Max.
Note
Min.
Command and Address setup time
to CK_t, CK_c referenced to
Vih(ac) /Vil(ac) levels
tIS(base)
62
-
-
-
ps
ps
ps
Command and Address setup time
to CK_t, CK_c referenced to Vref
levels
tIS(Vref)
162
87
Command and Address hold time
to CK_t, CK_c referenced to
Vih(dc) / Vil(dc) levels
tIH(base)
Command and Address hold time
to CK_t, CK_c referenced to Vref
levels
tIH(Vref)
tIPW
162
410
-
-
ps
ps
Control and Address Input pulse
width for each input
Command and AddressTiming
CAS_n to CAS_n command delay
for same bank group
tCCD_L
tCCD_S
Max(5nCK, 5.000ns)
4
-
-
nCK
nCK
34
34
CAS_n to CAS_n command delay
for different bank group
ACTIVATE to ACTIVATE
Command delay to different bank
group for 2KB page size
ACTIVATE to ACTIVATE
Command delay to different bank
group for 2KB page size
ACTIVATE to ACTIVATE
Command delay to different bank
group for 1/ 2KB page size
ACTIVATE to ACTIVATE
Command delay to same bank
group for 2KB page size
ACTIVATE to ACTIVATE
Command delay to same bank
group for 1KB page size
ACTIVATE to ACTIVATE
Command delay to same bank
group for 1/2KB page size
Four activate window for 2KB page
size
tRRD_S(2K)
Max(4nCK, 5.3ns)
Max(4nCK, 3.3ns)
Max(4nCK, 3.3ns)
Max(4nCK, 6.4ns)
Max(4nCK, 4.9ns)
Max(4nCK, 4.9ns)
-
-
-
-
-
-
nCK
nCK
nCK
nCK
nCK
nCK
34
34
34
34
34
34
tRRD_S
(1K)
tRRD_S
(1/ 2K)
tRRD_L(2K)
tRRD_L(1K)
tRRD_L
(1/ 2K)
tFAW_2K
tFAW_1K
Max(28nCK, 30ns)
Max(20nCK, 21ns)
Max(16nCK, 13ns)
-
-
-
ns
ns
ns
34
34
34
Four activate window for 1KB page
size
Four activate window for 1/2KB
page size
tFAW_1/2K
Delay from start of internal write
transaction to internal read
command for different bank group
Delay from start of internal write
transaction to internal read
command for same bank group
Internal READ Command to
PRECHARGE Command delay
1,2,
34
tWTR_S
max (2nCK, 2.5ns)
-
tWTR_L
tRTP
max(4nCK, 7.5ns)
Max(4nCK, 7.5ns)
-
-
1,34
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Timing Parameters by Speed Bin for DDR4-2400- continued
DDR4-2400
Parameter
Symbol
Units
Max.
Note
Min.
WRITE recovery time
tWR
tWR_CRC
_DM
15
-
-
ns
ns
1
Write recovery time when CRC
and DM are enabled
tW R+max (5nCK,3.75ns)
1, 28
delay from start of internal write
transaction to internal read
command for different bank group
with both CRC and DM enabled
delay from start of internal write
transaction to internal read
command for same bank group
with both CRC and DM enabled
DLL locking time
tWTR_S_CRC
_DM
2, 29,
34
tW TR_S+max (5nCK,3.75ns)
-
-
ns
ns
tWTR_L_CRC
_DM
3,30,
34
tW TR_L+max (5nCK,3.75ns)
tDLLK
tMRD
768
8
-
-
nCK
nCK
Mode Register Set command cycle
time
Mode Register Set command
update delay
Max
tMOD
tMPRR
-
-
-
(24nCK, 15ns)
Multi-Purpose Register Recovery
Time
1
nCK
-
33
Multi Purpose Register W rite
Recovery Time
tMOD (min)
+ AL + PL
tWR_MPR
tDAL(min)
Auto precharge write recovery +
precharge time
Programmed WR + roundup ( tRP / tCK(avg))
nCK
CS_n to Command Address Latency
CS_n to Command Address
Latency
tCAL
5
-
nCK
DRAM Data Timing
DQS_t,DQS_c to DQ skew,per
group, per access
tCK(avg)
/2
tDQSQ
tQH
-
TBD
-
13,18
DQ output hold time from
DQS_t,DQS_c
tCK(avg)
/2
13,17,
18
TBD
0.9
DQS_t, DQS_c differential READ
Preamble(1 clock preamble)
DQS_t, DQS_c differential READ
Preamble(2 clock preamble)
DQS_t, DQS_c differential READ
Postamble
tRPRE
tRPRE
tRPST
tQSH
TBD
TBD
TBD
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
1.8
0.33
0.4
DQS_t, DQS_c differential output
high time
21
20
DQS_t, DQS_c differential
outputlow time
tQSL
0.4
-
DQS_t, DQS_c differential WRITE
Preamble
tWPRE
tWPST
tLZ(DQS)
0.9
-
DQS_t, DQS_c differential WRITE
Postamble
0.33
-300
TBD
150
DQS_t and DQS_c low-impedance
time (Referenced from RL-1)
DQS_t and DQS_c
high-impedance time (Referenced
from RL+BL/2)
tHZ(DQS)
tDQSL
-
150
ps
DQS_t, DQS_c differential input
low pulse width
0.46
0.54
tCK
Elite Semiconductor Memory Technology Inc
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ESMT
M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2400- continued
DDR4-2400
Parameter
Symbol
Units
Note
Min.
Max.
DQS_t, DQS_c differential input
high pulse width
tDQSH
0.46
0.54
0.27
tCK
tCK
DQS_t, DQS_c rising edge to
CK_t, CK_c rising edge (1 clock
preamble)
tDQSS
-0.27
DQS_t, DQS_c falling edge
setup time to CK_t, CK_c rising
edge
tDSS
tDSH
0.18
0.18
-
-
tCK
tCK
DQS_t, DQS_c falling edge hold
time from CK_t, CK_c rising edge
DQS_t, DQS_c rising edge
output timing locatino from
rising CK_t, CK_c with DLL On
mode
tDQSCK
-175
175
ps
MPSM Timing
Command path disable delay upon
MPSM entry
tMPED
tCKMPE
tCKMPX
tXMP
tMOD(min) + tCPDED(min)
tMOD(min) + tCPDED(min)
tCKSRX(min)
-
-
-
-
-
Valid clock requirement after
MPSM entry
Valid clock requirement before
MPSM exit
Exit MPSM to commands not
requiring a locked DLL
Exit MPSM to commands requiring
a locked DLL
TBD
tXMPDLL
tXMP(min) + tXSDLL(min)
CS setup time to CKE
CS hold time to CKE
tMPX_S
tMPX_H
TBD
TBD
-
-
Calibration Timing
Power-up and RESET calibration
time
tZQinit
tZQoper
tZQCS
1024
512
-
-
-
nCK
nCK
nCK
Normal operation Full calibration
time
Normal operation Short calibration
time
128
Reset/Self Refresh Timing
Exit Reset from CKE HIGH to a
valid command
max (5nCK,tRFC
(min) + 10ns)
tXPR
tXS
-
-
-
Exit Self Refresh to commands not
requiring a locked DLL
SRX to commands not requiring a
locked DLL in Self RefreshABORT
Exit Self Refresh to ZQCL,ZQCS
and MRS (CL,CWL,WR,RTP and
Gear Down)
tRFC(min)+ 10ns
tXS_ABORT
(min)
tRFC4(min) + 10ns
tXS_FAST
(min)
tRFC4(min) + 10ns
tDLLK(min)
-
Exit Self Refresh to commands
requiring a locked DLL
Minimum CKE low width for Self
refresh entry to exit timing
tXSDLL
tCKESR
-
-
tCKE(min) +
1 nCK
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 39/53
ESMT
M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2400- continued
DDR4-2400
Parameter
Symbol
Units
Max.
Note
Min.
Minimum CKE low width for Self
re- fresh entry to exit timing with
CA Parity enabled
tCKESR_ PAR
tCKE(min) + 1nCK + PL
-
-
Valid Clock Requirement after Self
Refresh Entry (SRE) or
tCKSRE
max (5nCK,10ns)
Power-Down Entry (PDE)
Valid Clock Requirement after Self
Refresh Entry (SRE) or
max (5nCK,10ns)
+ PL
tCKSRE_PAR
-
-
Power-Down when CA Parity is
enabled
Valid Clock Requirement before
Self Refresh Exit (SRX) or
Power-Down Exit (PDX) or
Reset Exit
tCKSRX
max (5nCK,10ns)
Power Down Timing
Exit Power Down with DLL on to
any valid command;Exit Precharge
Power Down with DLL frozen to
commands not requiring a locked
DLL
tXP
max (4nCK,6ns)
-
-
Max
(3nCK, 5ns)
4
CKE minimum pulse width
tCKE
31,32
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power
Down entry
tCPDED
tPD
-
nCK
tCKE(min)
9*tREFI
6
7
tACTPDEN
tPRPDEN
tRDPDEN
2
2
-
-
-
nCK
nCK
nCK
Timing of PRE or PREA command
to Power Down entry
7
Timing of RD/RDA command to
Power Down entry
RL+4+1
Timing of WR command to Power
Down entry
WL+4+(tW R/
tCK(avg))
tWRPDEN
-
-
nCK
nCK
4
5
(BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power
Down entry
tWRAPDEN
WL+4+WR+1
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power
Down entry (BC4MRS)
tWRP
WL+2+(tW R/
tCK(avg))
-
-
-
-
nCK
nCK
nCK
4
5
7
- BC4DEN
tWRAP
Timing of WRA command to Power
Down entry (BC4MRS)
WL+2+WR+1
2
- BC4DEN
Timing of REF command to Power
Down entry
tREFPDEN
tMRSPDEN
Timing of MRS command to Power
Down entry
tMOD(min)
PDA Timing
Mode Register Set command
cycle time in PDA mode
Mode Register Set command
update delay in PDA mode
tMRD_PDA
tMOD_PDA
Max
(16nCK, 10ns)
tMOD
Elite Semiconductor Memory Technology Inc
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ESMT
M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2400- continued
DDR4-2400
Parameter
Symbol
Units
Max.
Note
Min.
ODT Timing
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
RTT dynamic change skew
Write Leveling Timing
tAONAS
1.0
9.0
ns
tAOFAS
tADC
1.0
0.3
9.0
0.7
ns
tCK(avg)
First DQS_t/DQS_n rising edge
after write leveling mode is
programmed
tWLMRD
tWLDQSEN
tWLS
40
25
-
-
-
nCK
nCK
12
12
DQS_t/DQS_n delay after write
level- ing mode is programmed
Write leveling setup time from
rising CK_t, CK_c crossing to
rising DQS_t/ DQS_n crossing
Write leveling hold time from rising
DQS_t/DQS_n crossing to rising
CK_t, CK_ crossing
0.13
tCK(avg)
tWLH
0.13
0
-
tCK(avg)
Write leveling output delay
Write leveling output error
CA Parity Timing
tWLO
9.5
ns
ns
tWLOE
Commands not guaranteed to be
ex- ecuted during this time
Delay from errant command to
ALERT_n assertion
tPAR_UN-
KNOWN
tPAR_ALER
T_ON
-
-
PL
PL+6ns
144
Pulse width of ALERT_n signal
when asserted
tPAR_ALER
T_PW
72
nCK
Time from when Alert is asserted
till controller must start providing
DES commands in Persistent CA
parity mode
tPAR_ALERT_
RSP
-
64
nCK
nCK
Parity Latency
PL
5
CRC Error Reporting
CRC error to ALERT_nlatency
tCRC_ALERT
CRC_ALERT_
PW
3
6
13
10
ns
CRC ALERT_n pulsewidth
nCK
tREFI
tRFC1 (min)
tRFC2 (min)
tRFC4 (min)
4Gb
4Gb
4Gb
260
160
110
-
-
-
ns
ns
ns
34
34
34
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ESMT
M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2666/3200
DDR4-2666
DDR4-3200
Units
Parameter
Symbol
Note
Min.
Max.
Min.
Max.
Clock Timing
Minimum Clock Cycle Time (DLL
off mode)
tCK
8
20
8
20
ns
ns
(DLL_OFF)
<0.833
Average Clock Period
tCK(avg)
0.750
0.625
<0.682
35,36
Average high pulse width
Average low pulse width
Absolute Clock Period
tCH(avg)
tCL(avg)
0.48
0.48
0.52
0.48
0.48
0.52
tCK(avg)
tCK(avg)
0.52
0.52
tCK(avg)min
+
tCK(avg)max
tCK(avg)min
+
tCK(avg)max
+
+
tCK(abs)
tCK(avg)
tJIT(per)min
_ tot
tJIT(per)max
tJIT(per)min
_ tot
tJIT(per)max
_ tot
-
_ tot
-
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
Clock Period Jitter- total
tCH(abs)
tCL(abs)
0.45
0.45
tCK(avg)
tCK(avg)
ps
23
24
25
26
0.45
-
0.45
-
JIT(per)_tot
JIT(per)_dj
-38
38
19
-32
32
16
Clock Period Jitter- deterministic
Clock Period Jitter during DLL
locking period
-19
-16
ps
tJIT(per, lck)
tJIT(cc)_total
tJIT(cc)_dj
-30
30
-25
-
25
62
ps
ps
ps
Cycle to Cycle Period Jitter
Cycle to Cycle Period
75
38
32
26
Jitterdeterministic
Cycle to Cycle Period Jitter
during DLL locking period
tJIT(cc, lck)
60
-
62
ps
Duty Cycle Jitter
tJIT(duty)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
tERR(13per)
tERR(14per)
tERR(15per)
tERR(16per)
tERR(17per)
tERR(18per)
TBD
-55
TBD
55
TBD
-46
-55
-61
-65
-69
-73
-76
-78
-80
-83
-84
-86
-87
-89
-90
-92
-93
TBD
46
55
61
65
69
73
76
78
80
83
84
86
87
89
90
92
93
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across 13 cycles
Cumulative error across 14 cycles
Cumulative error across 15 cycles
Cumulative error across 16 cycles
Cumulative error across 17 cycles
Cumulative error across 18 cycles
Cumulative error across
-66
66
-73
73
-78
78
-83
83
-87
87
-91
91
-94
94
-96
96
-99
99
-101
-103
-104
-106
-108
-110
-112
101
103
104
106
108
110
112
tERR(nper)min = ((1 + 0.68ln(n)) * tJIT(per)_total min)
tERR(nper)max = ((1 + 0.68ln(n)) * tJIT(per)_total max)
tERR(nper)
ps
n = 13, 14 ... 49, 50 cycles
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 42/53
ESMT
M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2666/3200- continued
DDR4-2666
DDR4-3200
Units
Parameter
Symbol
Note
Min.
Max.
Min.
Max.
Command and Address setup
time to CK_t, CK_c referenced to
Vih(ac) /Vil(ac) levels
tIS(base)
55
-
40
-
-
-
ps
ps
ps
Command and Address setup
time to CK_t, CK_c referenced to
Vref levels
tIS(Vref)
145
80
-
-
130
65
Command and Address hold time
to CK_t, CK_c referenced to
Vih(dc) / Vil(dc) levels
tIH(base)
Command and Address hold time
to CK_t, CK_c referenced to Vref
levels
tIH(Vref)
tIPW
145
385
-
-
130
340
-
-
ps
ps
Control and Address Input pulse
width for each input
Command and AddressTiming
CAS_n to CAS_n command delay
for same bank group
tCCD_L
tCCD_S
Max(5nCK, 5ns)
4
-
-
Max(4nCK, 5ns)
4
-
-
nCK
nCK
34
34
CAS_n to CAS_n command delay
for different bank group
ACTIVATE to ACTIVATE
Command delay to different bank
group for 2KB page size
ACTIVATE to ACTIVATE
Command delay to different bank
group for 2KB page size
ACTIVATE to ACTIVATE
Command delay to different bank
group for 1/ 2KB page size
ACTIVATE to ACTIVATE
Command delay to same bank
group for 2KB page size
ACTIVATE to ACTIVATE
Command delay to same bank
group for 1KB page size
ACTIVATE to ACTIVATE
Command delay to same bank
group for 1/2KB page size
Four activate window for 2KB
page size
Max(4nCK,
5.3ns)
Max(4nCK,
5.3ns)
tRRD_S(2K)
-
-
-
-
-
-
-
-
-
-
-
-
nCK
nCK
nCK
nCK
nCK
nCK
34
34
34
34
34
34
tRRD_S
(1K)
Max(4nCK,
2.5ns)
Max(4nCK, 3ns)
Max(4nCK, 3ns)
tRRD_S
(1/ 2K)
Max(4nCK,
2.5ns)
Max(4nCK,
6.4ns)
Max(4nCK,
6.4ns)
tRRD_L(2K)
tRRD_L(1K)
Max(4nCK,
4.9ns)
Max(4nCK,
4.9ns)
tRRD_L
(1/ 2K)
Max(4nCK,
4.9ns)
Max(4nCK,
4.9ns)
Max(28nCK,
30ns)
Max(28nCK,
30ns)
tFAW_2K
tFAW_1K
-
-
-
-
-
-
ns
ns
ns
34
34
34
Four activate window for 1KB
page size
Max(20nCK,
21ns)
Max(20nCK,
21ns)
Four activate window for 1/2KB
page size
Max(16nCK,
12ns)
Max(16nCK,
10ns)
tFAW_1/2K
Delay from start of internal write
transaction to internal read
command for different bank group
Delay from start of internal write
transaction to internal read
command for same bank group
Internal READ Command to
PRECHARGE Command delay
Max(2nCK,
2.5ns)
Max(2nCK,
2.5ns)
tWTR_S
-
-
nCK
1,2,34
Max(4nCK,
7.5ns)
Max(4nCK,
7.5ns)
tWTR_L
tRTP
-
-
-
-
nCK
nCK
1,34
34
Max(4nCK,
7.5ns)
Max(4nCK,
7.5ns)
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 43/53
ESMT
M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2666/3200- continued
DDR4-2666
DDR4-3200
Units
Parameter
Symbol
Note
Min.
Max.
Min.
Max.
WRITE recovery time
tWR
tWR_CRC
_DM
15
-
15
-
-
ns
ns
1
Write recovery time when CRC
and DM are enabled
tWR+max
(5nCK, 3.75ns
tWR+max
(5nCK, 3.75ns
-
-
1, 28
delay from start of internal write
transaction to internal read
command for different bank group
with both CRC and DM enabled
delay from start of internal write
transaction to internal read
command for same bank group
with both CRC and DM enabled
DLL locking time
tWTR_S+max
(5nCK,
tWTR_S+max
(5nCK,
tWTR_S_C
RC_DM
2, 29,
34
-
-
ns
ns
3.75ns)
3.75ns)
tWTR_L+max
(5nCK,
tWTR_L+max
(5nCK,
tWTR_L_C
RC_DM
3,30,
34
-
3.75ns)
3.75ns)
tDLLK
tMRD
854
8
-
-
1024
8
-
-
nCK
nCK
Mode Register Set command cycle
time
Mode Register Set command
update delay
max(24nCK,
15ns)
max(24nCK,
15ns)
tMOD
tMPRR
nCK
nCK
-
Multi-Purpose Register Recovery
Time
1
-
1
-
33
Multi Purpose Register W rite
Recovery Time
tWR_MPR
tDAL(min)
MIN = tMOD + AL + PL; MAX = N/A
Auto precharge write recovery +
precharge time
Programmed WR +
roundup ( tRP / tCK(avg))
MIN = WR + ROUNDtRP/tCK
(AVG); MAX = N/A
nCK
CS_n to Command Address Latency
CS_n to Command Address
Latency
tCAL
5
-
6
-
nCK
DRAM Data Timing
DQS_t,DQS_c to DQ skew,per
group, per access
tCK(avg)
/2
tDQSQ
tQH
-
0.18
-
0.20
13,18
DQ output hold time from
DQS_t,DQS_c
tCK(avg)
/2
13,17,
18
0.74
0.9
-
0.70
0.9
-
DQS_t, DQS_c differential READ
Preamble(1 clock preamble)
DQS_t, DQS_c differential READ
Preamble(2 clock preamble)
DQS_t, DQS_c differential READ
Postamble
tRPRE
tRPRE
tRPST
tQSH
-
-
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
1.8
-
1.8
-
0.33
0.4
-
0.33
0.4
-
DQS_t, DQS_c differential output
high time
-
-
21
20
DQS_t, DQS_c differential
outputlow time
tQSL
0.4
-
0.4
-
DQS_t, DQS_c differential WRITE
Preamble
tWPRE
tWPST
tLZ(DQS)
0.9
-
-
0.9
-
-
DQS_t, DQS_c differential WRITE
Postamble
0.33
-310
0.33
-250
DQS_t and DQS_c low-impedance
time (Referenced from RL-1)
DQS_t and DQS_c
170
160
high-impedance time (Referenced
from RL+BL/2)
tHZ(DQS)
tDQSL
-
170
-
160
ps
DQS_t, DQS_c differential input
low pulse width
0.46
0.54
0.46
0.54
tCK
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 44/53
ESMT
M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2666/3200- continued
DDR4-2666
DDR4-3200
Units
Parameter
Symbol
Note
Min.
Max.
Min.
Max.
DQS_t, DQS_c differential input
high pulse width
tDQSH
0.46
0.54
0.46
0.54
0.27
tCK
tCK
DQS_t, DQS_c rising edge to
CK_t, CK_c rising edge (1 clock
preamble)
tDQSS
-0.27
0.27
-0.27
DQS_t, DQS_c falling edge
setup time to CK_t, CK_c rising
edge
tDSS
tDSH
0.18
0.18
-
-
0.18
0.18
-
-
tCK
tCK
DQS_t, DQS_c falling edge hold
time from CK_t, CK_c rising edge
DQS_t, DQS_c rising edge
output timing locatino from
rising CK_t, CK_c with DLL On
mode
tDQSCK
-170
170
-160
160
ps
MPSM Timing
Command path disable delay upon
MPSM entry
tMPED
tCKMPE
tCKMPX
tXMP
MIN = tMOD (MIN) + tCPDED (MIN) ; MAX = N/A
MIN = tMOD (MIN) + tCPDED (MIN) ; MAX = N/A
MIN = tCKSRX (MIN) ; MAX = N/A
nCK
nCK
nCK
nCK
nCK
Valid clock requirement after
MPSM entry
Valid clock requirement before
MPSM exit
Exit MPSM to commands not
requiring a locked DLL
Exit MPSM to commands requiring
a locked DLL
MIN = tXS (MIN) ; MAX = N/A
MIN = tXMP (MIN) + tXSDLL (MIN) ; MAX = N/A
MIN = tIS (MIN) + tIH (MIN) ; MAX = N/A
tXMPDLL
CS setup time to CKE
CS_n High hold time to CKE
CS_n Low hold time to CKE
Calibration Timing
tMPX_S
tMPX_HH
tMPX_LH
ns
ns
ns
tXP
12
-
tXP
12
-
tXMP-10ns
tXMP-10ns
Power-up and RESET calibration
time
tZQinit
tZQoper
tZQCS
1024
512
-
-
-
1024
512
-
-
-
nCK
nCK
nCK
Normal operation Full calibration
time
Normal operation Short calibration
time
128
128
Reset/Self Refresh Timing
max (5nCK,
tRFC(min)+
10ns)
max (5nCK,
tRFC(min)+
10ns)
Exit Reset from CKE HIGH to a
valid command
-
-
tXPR
tXS
nCK
Exit Self Refresh to commands not
requiring a locked DLL
tRFC(min)+
10ns
tRFC(min)+
10ns
-
-
-
-
nCK
nCK
SRX to commands not requiring a
locked DLL in Self RefreshABORT
Exit Self Refresh to ZQCL,ZQCS
and MRS (CL,CWL,WR,RTP and
Gear Down)
tXS_ABORT
(min)
tRFC4(min)+
10ns
tRFC4(min)+
10ns
tXS_FAST
(min)
tRFC4(min)+
10ns
tRFC4(min)+
10ns
-
-
nCK
Exit Self Refresh to commands re-
quiring a locked DLL
tXSDLL
tCKESR
tDLLK(min)
-
-
tDLLK(min)
-
-
nCK
nCK
Minimum CKE low width for Self
refresh entry to exit timing
tCKE(min)+
1 nCK
tCKE(min)+
1 nCK
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 45/53
ESMT
M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2666/3200- continued
DDR4-2666
DDR4-3200
Units
Parameter
Symbol
Note
Min.
Max.
Min.
Max.
Minimum CKE low width for Self
tCKE(min)+
1nCK+PL
tCKE(min)+
1nCK+PL
refresh entry to exit timing with CA tCKESR_ PAR
Parity enabled
-
-
-
nCK
nCK
Valid Clock Requirement after Self
max
max
Refresh Entry (SRE) or
Power-Down Entry (PDE)
Valid Clock Requirement after Self
Refresh Entry (SRE) or
Power-Down when CA Parity is
enabled
tCKSRE
-
-
(5nCK,10ns)
(5nCK,10ns)
max
(5nCK,10ns)
+PL
max
(5nCK,10ns)
+PL
tCKSRE_PAR
-
-
nCK
nCK
Valid Clock Requirement before
Self Refresh Exit (SRX) or
Power-Down Exit (PDX) or
Reset Exit
max
max
tCKSRX
-
(5nCK,10ns)
(5nCK,10ns)
Power Down Timing
Exit Power Down with DLL on to
any valid command;Exit Precharge
Power Down with DLL frozen to
commands not requiring a locked
DLL
max
max
tXP
-
-
-
-
nCK
nCK
(4nCK,6ns)
(4nCK,6ns)
max
(3nCK,5ns)
4
max
(3nCK,5ns)
4
CKE minimum pulse width
tCKE
31,32
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power
Down entry
tCPDED
tPD
-
-
nCK
nCK
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
6
7
tACTPDEN
tPRPDEN
tRDPDEN
2
2
-
-
-
2
2
-
-
-
nCK
nCK
nCK
Timing of PRE or PREA command
to Power Down entry
7
Timing of RD/RDA command to
Power Down entry
RL + 4 + 1
RL + 4 + 1
Timing of WR command to Power
Down entry
tWRPDEN
MIN = WL + 4 + tWR/tCK (AVG) ; MAX = N/A
MIN = WL + 4 + WR + 1 ; MAX = N/A
nCK
nCK
4
5
(BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power
Down entry
tWRAPDEN
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power
Down entry (BC4MRS)
tWRP
MIN = WL + 2 + tWR/tCK (AVG) ; MAX = N/A
MIN = WL + 2 + WR + 1 ; MAX = N/A
nCK
nCK
nCK
nCK
4
5
7
- BC4DEN
tWRAP
Timing of WRA command to Power
Down entry (BC4MRS)
- BC4DEN
Timing of REF command to Power
Down entry
tREFPDEN
tMRSPDEN
2
-
-
2
-
-
Timing of MRS command to Power
Down entry
tMOD (MIN)
tMOD (MIN)
PDA Timing
Mode Register Set command
cycle time in PDA mode
Mode Register Set command
update delay in PDA mode
max
max
tMRD_PDA
tMOD_PDA
-
-
-
-
nCK
nCK
(16nCK,10ns)
(16nCK,10ns)
tMOD
tMOD
Elite Semiconductor Memory Technology Inc
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ESMT
M16U4G16256A
Timing Parameters by Speed Bin for DDR4-2666/3200- continued
DDR4-2666
DDR4-3200
Units
Parameter
Symbol
Note
Min.
Max.
Min.
Max.
ODT Timing
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
RTT dynamic change skew
Write Leveling Timing
tAONAS
1.0
9.0
1.0
9.0
ns
tAOFAS
tADC
1.0
0.3
9.0
0.7
1.0
9.0
ns
0.26
0.74
tCK(avg)
First DQS_t/DQS_n rising edge
after write leveling mode is
programmed
tWLMRD
tWLDQSEN
tWLS
40
25
-
-
-
40
25
-
-
-
nCK
nCK
12
12
DQS_t/DQS_n delay after write
level- ing mode is programmed
Write leveling setup time from
rising CK_t, CK_c crossing to
rising DQS_t/ DQS_n crossing
Write leveling hold time from rising
DQS_t/DQS_n crossing to rising
CK_t, CK_ crossing
0.13
0.13
tCK(avg)
tWLH
0.13
-
0.13
-
tCK(avg)
Write leveling output delay
Write leveling output error
CA Parity Timing
tWLO
0
0
9.5
2
0
0
9.5
2
ns
ns
tWLOE
Commands not guaranteed to be
executed during this time
Delay from errant command to
ALERT_n assertion
tPAR_UN-
KNOWN
tPAR_
-
-
PL
PL+6ns
160
-
-
PL
PL+6ns
192
nCK
nCK
nCK
ALERT_ON
tPAR_
Pulse width of ALERT_n signal
when asserted
80
96
ALERT_PW
Time from when Alert is asserted
till controller must start providing
DES commands in Persistent CA
parity mode
tPAR_
-
71
-
85
-
nCK
nCK
ALERT_RSP
Parity Latency
PL
5
6
CRC Error Reporting
CRC error to ALERT_nlatency
tCRC_ALERT
CRC_
3
6
13
10
3
6
13
10
ns
CRC ALERT_n pulsewidth
nCK
ALERT_PW
tGEAR_setup
tGEAR_hold
Geardown setup time
Geardown hold time
tREFI
2
2
-
-
2
2
-
-
nCK
nCK
tRFC1 (min)
4Gb
4Gb
4Gb
260
160
110
-
-
-
260
160
110
-
-
-
ns
ns
ns
34
34
34
tRFC2 (min)
tRFC4 (min)
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 47/53
ESMT
M16U4G16256A
Note:
1.
Start of internal write transaction is defined as follows :
For BL8 (Fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after W L.
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after W L.
2.
3.
4.
5.
6.
7.
A separate timing parameter will cover the delay from write to read when CRC and DM are simultaneously enabled.
Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
tWR is defined in ns, for calculation of tW RPDEN it is necessary to round up tWR/tCK to the next integer.
WR in clock cycles as programmed in MR0.
tREFI depends on TC.
CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in
progress, but power-down IDD spec will not be applied until finishing those operations.
For these parameters, the DDR4 SDRAM device supports tnPARAM[nCK]=RU{tPARAM[ns]/tCK(avg)[ns]}, which is in
clock cycles assuming all input clock jitter specifications are satisfied.
8.
9.
When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.
10. When CRC and DM are both enabled, tWTR_S_CRC_DM is used in place of tWTR_S.
11. When CRC and DM are both enabled, tWTR_L_CRC_DM is used in place of tWTR_L.
12. The max values are system dependent.
13. DQ to DQS total timing per group where the total includes the sum of deterministic and random timing terms for a
specified BER. BER spec and measurement method are TBD.
14. The deterministic component of the total timing. Measurement method TBD.
15. DQ to DQ static offset relative to strobe per group. Measurement method TBD.
16. This parameter will be characterized and guaranteed by design.
17. When the device is operated with the input clock jitter, this parameter needs to be derated by the actual tjit(per)_total of
the input clock. (output deratings are relative to the SDRAM input clock). Example TBD.
18. DRAM DBI mode is off.
19. DRAM DBI mode is enabled. Applicable to x8 and x16 DRAM only.
20. tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as measured from on falling
edge to the next consecutive rising edge.
21. tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as measured from on falling
edge to the next consecutive rising edge.
22. There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI.
23. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling
edge.
24. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising
edge.
25. Total jitter includes the sum of deterministic and random jitter terms for a specified BER. BER target and measurement
method are TBD.
26. The deterministic jitter component out of the total jitter. This parameter is characterized and guaranteed by design.
27. This parameter has to be even number of clocks.
28. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.
29. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.
30. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.
31. After CKE is registered LOW, CKE signal level shall be maintained below VILDC for tCKE specification (Low pulse width).
32. After CKE is registered HIGH, CKE signal level shall be maintained above VIHDC for tCKE specification (HIGH pulse
width).
33. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
34. Parameters apply from tCK(avg) min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed
Bin Tables.
35. This parameter must keep consistency with Speed-Bin Tables.
36. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate. UI=tCK(avg) min/2.
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
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ESMT
M16U4G16256A
Function Matrix
DDR4 SDRAM has several features supported by ORG and also by Speed. The following Table is the summary of the features.
Function Matrix (By ORG. V:Supported, Blank:Not supported)
Functions
x4
V
x8
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
x16
V
Note
Write Leveling
Temperature controlled Refresh
Low Power Auto Self Refresh
Fine Granularity Refresh
Multi Purpose Register
Data Mask
V
V
V
V
V
V
V
V
V
Data Bus Inversion
TDQS
V
ZQ calibration
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQ Vref Training
Per DRAM Addressability
Mode Register Readout
CAL
WRITE CRC
CA Parity
Control Gear Down Mode
Programmable Preamble
Maximum Power Down Mode
Boundary Scan Mode
Additive Latency
V
V
V
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ESMT
M16U4G16256A
Function Matrix (By Speed. V:Supported, Blank:Not supported)
DLL Off mode
Functions
DLL On mode
Note
equal or slower
2133 Mbps
2400 Mbps
2666/3200 Mbps
Write Leveling
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Temperature controlled Refresh
Low Power Auto Self Refresh
Fine Granularity Refresh
Multi Purpose Register
Data Mask
Data Bus Inversion
TDQS
ZQ calibration
V
V
DQ Vref Training
Per DRAM Addressability
Mode Register Readout
CAL
V
WRITE CRC
CA Parity
Control Gear Down Mode
Programmable Preamble ( = 2tCK)
Maximum Power Down Mode
Boundary Scan Mode
V
V
V
V
V
V
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ESMT
M16U4G16256A
PACKING DIMENSIONS
96-BALL
DDR SDRAM ( 7.5x13 mm )
D
Pin# A1
Index
Side
SEATING PLANE
SOLDER BALL
DETAIL : "A"
D1
"A"
e
o
b
Pin# A1
Index
Pin# A1
Index
DETAIL : "B"
"B"
Dimension in mm
Symbol
Dimension in inch
Min
—
Norm
—
Max
1.00
0.40
0.50
7.60
13.10
Min
Norm
—
Max
A
A1
Φb
D
—
0.039
0.016
0.020
0.299
0.516
0.30
0.40
7.40
12.90
0.35
0.012
0.016
0.291
0.508
0.014
0.45
0.018
7.50
0.295
E
13.00
0.512
D1
E1
e
6.40 BSC
12.00 BSC
0.80 BSC
0.252 BSC
0.472 BSC
0.031 BSC
Controlling dimension : Millimeter.
(Revision date : Nov172 2017)
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 51/53
ESMT
M16U4G16256A
Revision History
Revision
Date
Description
0.1
2019.08.21
2019.11.19
Original
1.0
Delete Preliminary
1. Add speed grade 2600Mbps and 3200Mbps
2. Correct typo
1.1
2020.01.03
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 52/53
ESMT
M16U4G16256A
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express, implied
or otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc
Publication Date : Jan. 2020
Revision : 1.1 53/53
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