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M32L1632512A-8SQ [ESMT]

Synchronous DRAM, 512KX32, 6.5ns, CMOS, PQFP100,;
M32L1632512A-8SQ
型号： M32L1632512A-8SQ
厂家： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.    ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
描述：

Synchronous DRAM, 512KX32, 6.5ns, CMOS, PQFP100,

时钟 动态存储器 内存集成电路
文件： 总54页 (文件大小：877K)
中文：  中文翻译
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M32L1632512A  
SGRAM  
256K x 32 Bit x 2 Banks  
Synchronous Graphic RAM  
FEATURES  
GENERAL DESCRIPTION  
The M32L1632512A is 16, 777, 216 bits synchro-  
nous high data rate Dynamic RAM organized as 2 x  
JEDEC standard 3.3V power supply  
LVTTL compatible with multiplexed address  
Dual bank / Pulse RAS  
262, 144 words by 32 bits, fabricated with ESMT’s  
high performance CMOS technology. Synchronous  
design allows precise cycle control with the use of  
system clock. I/O transactions are possible on every  
clock cycle. Range of operating frequencies , progra-  
mmable burst length, and programmable latencies  
allows the same device to be useful for a variety of  
high bandwidth, high performance memory system  
applications.  
MRS cycle with address key programs  
- CAS Latency ( 2, 3 )  
- Burst Length ( 1, 2, 4, 8 & full page )  
- Burst Type ( Sequential & Interleave )  
All inputs are sampled at the positive going  
edge of the system clock  
Burst Read Single-bit Write operation  
DQM 0-3 for byte masking  
Auto & self refresh  
Write per bit and 8 columns block write improves  
performance in graphic systems.  
32ms refresh period (2K cycle)  
100 pin QFP  
ORDERING INFORMATION  
Graphic Features  
SMRS cycle  
- Load mask register  
- Load color register  
Write Per Bit  
Block Write (8 Columns)  
Part NO.  
Cycle  
Clock  
Access  
tRDL  
(clk)  
time Frequency time@CL=3  
M32L1632512A-5Q  
5ns  
200MHz  
200MHz  
166MHz  
166MHz  
143MHz  
143MHz  
125MHz  
125MHz  
4.5ns  
4.5ns  
5.5ns  
5.5ns  
6.0ns  
6.0ns  
6.5ns  
6.5ns  
1
2
1
2
1
2
1
2
M32L1632512A-5SQ 5ns  
M32L1632512A-6Q 6ns  
M32L1632512A-6SQ 6ns  
M32L1632512A-7Q 7ns  
M32L1632512A-7SQ 7ns  
M32L1632512A-8Q 8ns  
M32L1632512A-8SQ 8ns  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 1/54  
M32L1632512A  
FUNCTIONAL BLOCK DIAGRAM  
MASK  
REGISTER  
DQMi  
BLOCK  
WRITE  
CONTROL  
LOGIC  
COLOR  
REGISTER  
WRITE  
CONTROL  
LOGIC  
MUX  
CLK  
CKE  
DQi  
(i=0~31)  
COLUMN  
MASK  
DQMi  
CS  
RAS  
256Kx32  
CELL  
ARRAY  
256Kx32  
CELL  
ARRAY  
CAS  
WE  
DSF  
ROW DECORDER  
BANK SELECTION  
DQMi  
ROW ADDRESS  
BUFFER  
SERIAL  
COUNTER  
REFRESH  
COUNTER  
COLUMN ADDRESS  
BUFFER  
ADDRESS REGISTER  
ADDRESS(A0~A10)  
CLOCK  
PIN CONFIGURATION (TOP VIEW)  
81  
A7  
50  
DQ29  
VSSQ  
A6  
82  
83  
84  
85  
86  
87  
88  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
A5  
DQ30  
DQ31  
VSS  
A4  
VSS  
N.C  
N.C  
N.C  
N.C  
N.C  
N.C  
N.C  
N. C  
N. C  
N. C  
N.C  
N. C  
N. C  
N. C  
N.C  
N.C  
1
F
0
o
0
P
in  
r d  
Q
F
P
e
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
r w  
a
T
y p  
2
0
x
1
4
m m  
39  
38  
37  
36  
35  
34  
33  
32  
31  
0
. 6  
5
m
m
p
i n  
P i t c h  
N.C  
N.C  
N.C  
VDD  
A3  
N.C  
VDD  
DQ0  
A2  
A1  
A0  
DQ1  
VSSQ  
DQ2  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 2/54  
M32L1632512A  
PIN DESCRIPTION  
PIN  
NAME  
System Clock  
INPUT FUNCTION  
CLK  
CS  
Active on the positive going edge to sample all inputs  
Disables or enable device operation by masking or enabling all  
inputs except CLK, CKE and DQMi  
Chip Select  
Masks system clock to freeze operation from the next clock cycle.  
CKE  
Clock Enable  
Address  
CKE should be enabled at least one clock+ ss prior to new  
command.  
Disable input buffers for power down in standby.  
t
Row / column addresses are multiplexed on the same pins.  
Row address : RA0~RA9, column address : CA0~CA7  
A0 ~ A9  
A10(BA)  
RAS  
Selects bank to be activated during row address latch time.  
Selects bank for read / write during column address latch time.  
Bank Select Address  
Row Address Strobe  
Latches row addresses on the positive going edge of the CLK with  
RAS low.  
Enables row access & precharge.  
Latches column address on the positive going edge of the CLK  
With  
Column Address Strobe  
CAS  
CAS low.  
Enables column access.  
Write Enable  
Enables write operation and Row precharge.  
WE  
Makes data output Hi-Z, SHZ after the clock and masks the output.  
t
DQMi  
Data Input/Output Mask  
Blocks data input when DQM active. (Byte Masking)  
Data inputs/outputs are multiplexed on the same pins.  
Enables write per bit, block write and special mode register set.  
DQi  
Data Input/Output  
DSF  
Define Special/ Function  
Power Supply/ Ground  
Data Output Power/Ground  
VDD/VSS  
VDDQ/VSSQ  
ABSOLUTE MAXIMUM RATINGS (Voltage referenced to VSS)  
Parameter  
Voltage on any pin relative to VSS  
Voltage on VDD supply relative to VSS  
Storage temperature  
Symbol  
VIN, VOUT  
VDD, VDDQ  
TSTG  
Value  
-1.0 ~ 4.6  
-1.0 ~ 4.6  
-55 ~ +150  
1
Unit  
V
V
i
Power dissipation  
PD  
W
mA  
Short circuit current  
IOS  
50  
Note : Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device  
reliability.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 3/54  
M32L1632512A  
DC OPERATING CONDITIONS  
Recommended operating conditions (Voltage referenced to VSS = 0V)  
Parameter  
Supply voltage  
Symbol  
VDD, VDDQ  
VIH  
Min  
3.0  
2.0  
-0.3  
2.4  
-
Typ  
3.3  
3.0  
0
Max  
Unit  
V
Note  
3.6  
Input high voltage  
Input low voltage  
Output high voltage  
Output low voltage  
Input leakage current  
VDD+0.3  
V
VIL  
0.8  
-
V
Note 1  
IOH = -2mA  
IOL = 2mA  
Note 2  
VOH  
-
V
VOL  
-
0.4  
5
V
IIL  
-5  
-
µ
Output leakage current  
IOL  
-5  
-
5
Note 3  
µ
Output Loading Condition  
See Fig 1  
Note: 1. VIL(min) = -1.5V AC (pulse width ≤ 5ns)  
2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.  
4. Dout is disabled, 0V ≤ VOUT ≤ VDD.  
CAPACITANCE  
(VDD/VDDQ = 3.3V, TA = 25 , f = 1MHZ)  
°C  
Parameter  
Symbol  
Min  
Max  
Unit  
Input capacitance (A0 ~ A10)  
CIN1  
-
4
pF  
Input capacitance  
CIN2  
-
-
4
5
pF  
pF  
(CLK, CKE, CS , RAS , CAS , WE , DSF& DQM0-3)  
Data input/output capacitance (DQ0 ~ DQ31)  
COUT  
DECOUPLING CAPACITANCE GUIDE LINE  
Recommended decoupling capacitance added to power line at board.  
Parameter  
Symbol  
CDC1  
Value  
Unit  
uF  
Decoupling Capacitance between VDD & VSS  
Decoupling Capacitance between VDDQ & VSSQ  
0.1+0.01  
0.1+0.01  
CDC2  
uF  
*Note: 1. VDD and VDDQ pins are separated each other.  
All VDD pins are connected in chip. All VDDQ pins are connected in chip.  
2. VSS and VSSQ pins are separated each other.  
All VSS pins are connected in chip. All VSSQ pins are connected in chip.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 4/54  
M32L1632512A  
DC CHARACTERISTICS  
Recommended operating condition unless otherwise noted, TA = 0 to 70  
VIH(min) /VIL(max) =2.0V/0.8V  
°C  
Version  
CAS  
Parameter  
Symbol  
Test Condition  
Unit Note  
Latency  
-5/5S -6/6S -7/7S -8/8S  
Burst Length = 1  
3
230 210 195 170  
Operating Current  
(One Bank Active)  
mA  
mA  
mA  
1
ICC1  
,
≥
tRC ≥ tRC(min) tCC tCC(min)  
2
230 210 195 170  
IOL = 0 mA  
ICC2P  
2
2
2
2
2
2
2
2
CKE ≤ VIL(max), tCC = 15ns  
Precharge Standby Current  
in power-down mode  
ICC2PS  
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), = 15ns  
Input signals are changed one time during  
30ns  
tCC  
ICC2N  
35  
35  
35  
35  
Precharge Standby Current  
in non power-down mode  
∞
CKE ≥ VIH(min), CLK ≤ VIL(max),  
input signals are stable  
=
tCC  
ICC2NS  
15  
15  
15  
15  
ICC3P  
3
3
3
3
3
3
3
3
CKE ≤ VIL(max),  
= 15ns  
tCC  
Active Standby Current  
in power-down mode  
mA  
mA  
ICC3PS  
∞
CKE ≤ VIL(min), CLK ≤ VIL(max),  
=
tCC  
ICC3N CKE ≥ VIH(min), CS ≥ VIH(min),  
= 15ns  
tCC  
Active Standby Current  
in non power-down mode  
(One Bank Active)  
60  
60  
60  
60  
Input signals are changed one time during  
30ns  
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞  
ICC3NS  
20  
20  
20  
20  
input signals are stable  
IOL = 0 mA, Page Burst  
3
230 210 195 170  
Operating Current  
(Burst Mode)  
All Banks Activated,  
(min)  
=
ICC4  
tCCD tCCD  
mA 1, 2  
2
3
230 210 195 170  
190 170 160 150  
Refresh Current  
ICC5  
mA  
mA  
3
4
tRC ≥ tRC(min)  
2
190 170 160 150  
Self Refresh Current  
ICC6  
ICC7  
CKE ≤ 0.2V  
tCC ≥ tCC(min), IOL = 0 mA,  
2
2
2
2
Operating Current  
(One Bank Block Write)  
220 200 190 180 mA  
tBWC(min)  
*Note : 1. Measured with outputs open.  
2. Assumes minimum column address update cycle tCCD(min).  
3. Refresh period is 32ms.  
4. Assumes minimum column address update cycle tBWC(min).  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 5/54  
M32L1632512A  
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70  
)
°C  
Parameter  
Value  
VIH/VIL = 2.4V/0.4V  
1.4V  
AC Input levels  
Input timing measurement reference level  
Input rise and fall-time (See note3)  
tR/tF = 1ns/1ns  
Output timing measurement reference level  
Output load condition  
1.4V  
See Fig. 2  
VREF = 1.4V  
50  
3 .3 V  
1200  
VOH (DC) =2.4V , IOH = -2 m A  
VOL (DC) =0.4V , IOL = 2 m A  
Ou tput  
Ou tput  
Z0 =50  
30pF  
30pF  
870  
(Fig. 1) DC Output Load Circuit  
(Fig. 2) AC Output Load Circuit  
AC CHARACTERISTICS  
(AC operating conditions unless otherwise noted)  
-5/5S  
-6/6S  
-7/7S  
-8/8S  
Parameter  
Symbol  
Unit  
Note  
Min Max Min Max Min Max Min Max  
CAS latency =3  
5
7.5  
-
6
8
-
7
10  
-
8
12  
-
CLK cycle time  
1000  
1000  
1000  
1000  
ns  
ns  
1
1, 2  
2
tCC  
tSAC  
tOH  
CAS latency =2  
CAS latency =3  
CAS latency =2  
CAS latency =3  
CAS latency =2  
CLK to valid  
output delay  
4.5  
5
5.5  
6
6
7
6.5  
8
-
-
-
-
Output data  
hold time  
2
2
2
2
2
2
ns  
ns  
ns  
2
2
2
CLK high pulse width  
CLK low pulse width  
Input setup time  
2
2.5  
3
3
3
3
3
2
tCH  
tCL  
tSS  
tSH  
tSLZ  
2
2
1
1
2
2
1
1
2.5  
2
3
2.5  
1
ns  
ns  
ns  
ns  
Input hold time  
1
CLK to output in Low-Z  
CLK to output CAS latency =3  
1
1
-
-
5
5
-
-
5.5  
6
-
-
6
7
-
-
6.5  
8
ns  
tSHZ  
In Hi-Z  
CAS latency =2  
* All AC parameters are measured from half to half.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6  
6/54  
M32L1632512A  
*Note : 1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2 - 0.5) ns should be added to the parameter.  
3. Assumed input rising and falling time (tr & tf) = 1ns.  
If tr & tf is longer 1ns, transient time compensation should be considered.  
i.e., [(tr + tf)/2 - 1] ns should be added to the parameter.  
OPERATING AC PARAMETER  
(AC operating conditions unless otherwise noted)  
Version  
Parameter  
Symbol  
Unit  
Note  
-5  
-5S  
-6  
-6S -7 -7S -8 -8S  
Row active to row active delay  
1
1
1
1
10  
15  
15  
40  
12  
18  
18  
40  
14  
20  
21  
42  
16  
20  
24  
48  
tRRD(min)  
tRCD(min)  
tRP(min)  
ns  
ns  
RAS to CAS delay  
Row precharge time  
ns  
tRAS(min)  
tRAS(max)  
tRC(min)  
tCDL(min)  
tRDL(min)  
tBPL(min)  
Row active time  
us  
100  
Row cycle time  
ns  
1
2
2
55  
60  
63  
72  
Last data in to new col. address delay  
Last data in to row precharge  
Block write data-in to PRE command delay  
CLK  
CLK  
ns  
1
2
1
2
1
1
2
1
2
10  
25  
12  
30  
14  
35  
16  
40  
Block write data-in to Active (REF)  
command period (Auto precharge)  
Last data to burst stop  
ns  
tBAL(min)  
CLK  
CLK  
CLK  
2
3
4
1
1
tBDL(min)  
tCCD(min)  
tBWC(min)  
Col. Address to col. Address delay  
Block write cycle time  
2
2
2
2
2
1
CAS latency = 3  
CLK  
5
Number of valid Output data  
CAS latency = 2  
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with  
clock cycle time and then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
3. All parts allow every cycle column address change except block write cycle.  
4. This parameter means minimum CAS to CAS delay at block write cycle only.  
5. In case of row precharge interrupt, auto precharge and read burst stop.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 7/54  
M32L1632512A  
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE  
M32L1632512A-5Q ( * : -5SQ )  
(Unit : number of clock)  
tRC  
tRAS  
tRP  
tRRD  
tRCD  
tCCD  
5ns  
1
tCDL  
5ns  
1
tRDL * tRDL  
CAS  
Frequency  
55ns  
11  
10  
8
40ns  
15ns  
10ns  
15ns  
5ns  
1
10ns  
Latency  
200 MHz(5.0ns)  
166 MHz(6.0ns)  
143 MHZ(7.0ns )  
125 MHZ(8.0ns )  
3
3
3
2
8
7
6
5
3
3
3
2
2
2
2
2
3
3
3
2
2
2
2
2
1
1
1
1
1
1
7
1
1
1
M32L1632512A-6Q ( * : -6SQ )  
(Unit : number of clock)  
tRC  
tRAS  
tRP  
tRRD  
tRCD  
tCCD  
tCDL  
6ns  
1
tRDL * tRDL  
CAS  
Frequency  
Latency  
60ns  
10  
9
40ns  
18ns  
12ns  
18ns  
6ns  
1
6ns  
1
12ns  
166 MHz(6.0ns)  
143 MHZ(7.0ns )  
125 MHZ(8.0ns )  
100 MHZ(10.0ns )  
3
3
2
2
7
6
5
4
3
3
3
2
2
2
2
2
3
3
3
2
2
2
2
2
1
1
1
8
1
1
1
6
1
1
1
M32L1632512A-7Q ( * : -7SQ )  
(Unit : number of clock)  
tRC  
tRAS  
tRP  
tRRD TRCD tCCD  
tCDL  
7ns  
1
tRDL * tRDL  
CAS  
Frequency  
Latency  
63ns  
42ns  
21ns  
14ns  
20ns  
7ns  
1
7ns  
1
14ns  
143 MHZ(7.0ns )  
125 MHZ(8.0ns )  
100 MHZ(10.0ns )  
83 MHZ(12.0ns )  
3
3
2
2
9
8
7
6
6
6
5
4
3
3
3
2
2
2
2
2
3
3
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
M32L1632512A-8Q ( * : -8SQ )  
(Unit : number of clock)  
tRC  
tRAS  
tRP  
tRRD  
tRCD  
tCCD  
8ns  
1
tCDL  
8ns  
1
tRDL * tRDL  
CAS  
Frequency  
72ns  
48ns  
24ns  
16ns  
20ns  
8ns  
1
16ns  
Latency  
125 MHZ(8.0ns )  
100 MHZ(10.0ns )  
83 MHZ(12.0ns )  
75 MHZ(13.4ns )  
3
3
2
2
9
8
6
6
6
5
4
4
3
3
2
2
2
2
2
2
3
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 8/54  
M32L1632512A  
SIMPLIFIED TRUTH TABLE  
COMMAND  
Mode Register set  
CKEn-1 CKEn  
DSF DQM A10 A9 A8~A0  
Note  
CS  
WE  
RAS CAS  
L
1, 2  
Register  
Refresh  
H
H
L
X
L
L
L
L
L
L
X
X
X
X
OP CODE  
1, 2, 7  
Special Mode Register Set  
Auto Refresh  
H
H
L
3
3
L
H
L
X
Entry  
Self  
L
H
X
H
X
H
X
3
Refresh  
Exit  
H
X
X
X
H
3
L
Write Per Bit Disable  
Write Per Bit Enable  
4, 5  
Bank Active  
& Row Addr.  
H
L
L
H
H
V
Row Address  
H
4,5,9  
4
Auto Precharge Disable  
Auto Precharge Enable  
Auto Precharge Disable  
Auto Precharge Enable  
Auto Precharge Disable  
Auto Precharge Enable  
L
H
L
Column  
Address  
Read & Column  
Address  
H
H
X
X
L
L
H
H
L
L
H
L
L
L
X
X
V
V
V
4, 6  
4, 5  
4,5,6,9  
4, 5  
4,5,6,9  
7
Write & Column  
Address  
Column  
Address  
H
L
Block Write &  
Column  
Address  
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
H
L
L
X
X
X
Column Address  
H
Burst Stop  
Precharge  
X
Bank Selection  
Both Banks  
V
X
L
X
H
L
H
X
L
H
X
X
H
X
H
X
X
H
X
H
X
X
H
X
H
L
L
H
L
Clock Suspend or  
Active Power Down  
Entry  
Exit  
X
X
X
X
X
X
X
X
Entry  
H
H
Precharge Power Down Mode  
L
V
X
V
X
V
X
V
X
X
V
X
Exit  
L
H
X
H
DQM  
H
X
H
X
X
8
L
H
X
H
X
H
X
No Operation Command  
H
X
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low )  
Note : 1.OP Code : Operand Code  
A0~A10 : Program keys. (@ MRS)  
A5, A6 : LMR & LCR select. (@ SMRS)  
Color register exists only one per DQi which both banks share.  
So does Mask Register.  
Color or mask is loaded into chip through DQ pin.  
2.MRS can be issued only at both banks precharge state.  
SMRS can be issued only if DQ’s are idle.  
A new command can be issued at the next clock of MRS/SMRS.  
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Revision : 1.6 9/54  
M32L1632512A  
3.Auto refresh functions as same as CBR refresh of DRAM.  
The automatical precharge without Row precharge of command is meant by “Auto”.  
Auto/self refresh can be issued only at both banks precharge state.  
4.A10 : Bank select address.  
If “Low” at read, (block) write, Row active and precharge, bank A is selected.  
If “High” at read, (block) write, Row active and precharge, bank B is selected.  
If A9 is “High” at Row precharge, A10 is ignored and both banks are selected.  
5.It is determined at Row active cycle.  
whether Normal/Block write operates in write per bit mode or not.  
For A bank write, at A bank Row active, for B bank write, at B bank Row active.  
Terminology : Write per bit = I/O mask  
(Block) Write with write per bit mode = Masked (Block) Write  
6.During burst read or write with auto precharge, new read/(block) write command cannot be issued.  
Another bank read/(block) write command can be issued at tRP after the end of burst.  
7.Burst stop command is valid for all burst length.  
8.DQM sampled at positive going edge of a CLK.  
masks the data-in at the very CLK (Write DQM latency is 0)  
but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)  
9.Graphic features added to SDRAM’s original features.  
If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32  
DQ’s.  
SGRAM vs SDRAM  
SDRAM Function  
MRS  
Bank Active  
Write  
DSF  
L
H
L
H
L
H
Bank Active  
With  
Write per bit Write per bit  
Disable Enable  
Bank Active  
With  
SGRAM  
Function  
Normal  
Write  
Block  
Write  
MRS  
SMRS  
If DSF is low. SGRAM functionality is identical to SDRAM functionality.  
SGRAM can be uesed as an unified memory by the appropriate DSF control  
SGRAM = Graphic Memory + Main Memory.  
MODE REGISTER FIELD TABLE TO PROGRAM MODES  
Register Programmed with MRS  
Address  
Function  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
BT  
A2  
A1  
A0  
RFU  
W.B.L  
TM  
CAS Latency  
Burst Length  
(Note1)  
(Note2)  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 10/54  
M32L1632512A  
Test Mode  
Type  
CAS Latency  
Burst Type  
Type  
Burst Length  
A8  
0
A7  
0
A6  
0
A5  
0
A4 Latency A3  
A2  
0
A1  
0
A0  
0
BT = 0  
BT = 1  
Reserved  
Reserved  
4
Mode Register Set  
0
1
0
1
0
1
0
1
Reserved  
-
0
Sequential  
1
2
4
8
0
1
Vendor  
Use  
0
0
1
Interleave  
0
0
1
1
0
0
1
2
0
1
0
1
1
Only  
0
1
3
0
1
1
8
Write Burst Length  
Length  
1
0
Reserved  
Reserved  
Reserved  
Reserved  
1
0
0
Reserved Reserved  
Reserved Reserved  
Reserved Reserved  
256(Full) Reserved  
(Note 3)  
A9  
0
1
0
1
0
1
Burst  
1
1
1
1
0
1
Single Bit  
1
1
1
1
1
Special Mode Register Programmed with SMRS  
Address  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A
Function  
X
LC  
LM  
X
Load Color  
Load Mask  
A6  
0
Function  
A5  
Function  
Disable  
Enable  
Disable  
Enable  
0
1
1
(Note 4)  
POWER UP SEQUENCE  
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP  
condition at the inputs.  
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µ s.  
3. Issue precharge commands for all banks of the devices.  
4. Issue 2 or more auto-refresh commands.  
5. Issue a mode register set command to initialize the mode register.  
cf.) Sequence of 4 & 5 may be changed.  
The device is now ready for normal operation.  
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.  
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.  
3. The full column burst (256bit) is available only at Sequential mode of burst type.  
4. If LC and LM both high (1), data of mask and color register will be unknown.  
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Revision : 1.6 11/54  
M32L1632512A  
BURST SEQUENCE (BURST LENGTH = 4)  
Initial Address  
Sequential  
Interleave  
A1  
A0  
0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
BURST SEQUENCE (BURST LENGTH = 8)  
Initial address  
Sequential  
Interleave  
A2  
0
A1  
A0  
0
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
0
1
0
3
2
5
4
7
6
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
6
5
4
3
2
1
0
0
0
1
7
0
1
2
3
4
5
1
2
3
4
5
6
7
3
0
1
6
7
4
5
7
4
5
2
3
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PIXEL to DQ MAPPING (at BLOCK WRITE)  
Column address  
3 Byte  
I/O31~ I/O24  
DQ24  
2 Byte  
I/O23~ I/O16  
DQ16  
1 Byte  
0 Byte  
A2  
A1  
0
A0  
I/O15~ I/O8  
DQ8  
I/O7~ I/O0  
DQ0  
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
DQ25  
DQ17  
DQ9  
DQ1  
1
DQ26  
DQ18  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ2  
1
DQ27  
DQ19  
DQ3  
0
DQ28  
DQ20  
DQ4  
0
DQ29  
DQ21  
DQ5  
1
DQ30  
DQ22  
DQ6  
1
DQ31  
DQ23  
DQ7  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 12/54  
M32L1632512A  
DEVICE OPERATIONS  
CLOCK (CLK)  
ADDRESS INPUTS (A0~A9)  
The clock input is used as the reference for all  
The 18 address bits are required to decode the  
262,144 word locations are multiplexed into 10  
address input pins (A0~A9). The 10 bit row  
SGRAM  
operations.  
All  
operations  
are  
synchronized to the positive going edge of the  
clock. The clock transitions must be monotonic  
between VIL and VIH. During operation with CKE  
high all inputs are assumed to be in valid state (low  
or high) for the duration of setup and hold time  
around positive edge of the clock for proper  
functionality and Icc specifications.  
address is latched along with RAS and A10  
during bank activate command. The 8 bit  
column address is latched along with  
,
CAS  
and A10 during read or write command.  
WE  
NOP and DEVICE DESELECT  
CLOCK ENABLE(CKE)  
When RAS , CAS and WE are high, The  
SGRAM performs no operation (NOP). NOP  
does not initiate any new operation, but is  
needed to complete operations which require  
more than single clock cycle like bank activate,  
burst read, auto refresh, etc. The device deselect  
The clock enable (CKE) gates the clock onto  
SGRAM. If CKE goes low synchronously with  
clock (set-up and hold time same as other inputs),  
the internal clock suspended from the next clock  
cycle and the state of output and burst address is  
frozen as long as the CKE remains low. All other  
inputs are ignored from the next clock cycle after  
CKE goes low. When both banks are in the idle  
state and CKE goes low synchronously with clock,  
the SGRAM enters the power down mode from the  
next clock cycle. The SGRAM remains in the  
power down mode ignoring the other inputs as long  
as CKE remains low. The power down exit is  
synchronous as the internal clock is suspended.  
When CKE goes high at least “tSS+1CLOCK”  
before the high going edge of the clock, then the  
SGRAM becomes active from the same clock edge  
accepting all the input commands.  
is also a NOP and is entered by asserting  
CS  
high. CS high disables the command decoder  
so that RAS , CAS, WE , DSF and all the  
address inputs are ignored.  
POWER-UP  
The following sequence is recommended for  
POWER UP  
1.Power must be applied to either CKE and  
DQM inputs to pull them high and other pins  
are NOP condition at the inputs before or  
along with VDD (and VDDQ) supply.  
The clock signal must also be asserted at the  
same time.  
BANK SELECT (A10)  
2.After VDD reaches the desired voltage, a  
minimum pause of 200 microseconds is  
required with inputs in NOP condition.  
3.Both banks must be precharged now.  
4.Perform a minimum of 2 Auto refresh cycles  
to stabilize the internal circuitry.  
This SGRAM is organized as two independent  
banks of 262, 144 words x 32 bits memory arrays.  
The A10 inputs are latched at the time of assertion  
of RAS and CAS to select the bank to be used  
for the operation. When A10 is asserted low, bank  
A is selected. When A10 is latched high, bank B is  
selected. The banks select A10 is latched at bank  
activate, read, write, mode register set and  
precharge operations.  
5.Perform a MODE REGISTER SET cycle to  
program the CAS latency, burst length and  
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M32L1632512A  
DEVICE OPERATIONS (Continued)  
burst type as the default value of mode register is  
undefined.  
BANK ACTIVATE  
The bank activate command is used to select a  
random row in an idle bank. By asserting low  
At the end of one clock cycle from the mode  
register set cycle, the device is ready for operation.  
When the above sequence is used for Power-up, all  
the outputs will be in high impedance state. The  
high impedance of outputs is not guaranteed in any  
other power-up sequence.  
on RAS and CS with desired row and bank  
addresses, a row access is initiated. The read or  
write operation can occur after a time delay of  
tRCD (min) from the time of bank activation. tRCD  
(min) is the internal timing parameter of SGRAM,  
therefore it is dependent on operating clock  
frequency. The minimum number of clock  
cycles required between bank activate and read  
or write command should be calculated by  
dividing tRCD (min) with cycle time of the clock  
and then rounding of the result to the next  
higher integer. The SGRAM has two internal  
banks in the same chip and shares part of the  
internal circuitry to reduce chip area, therefore  
it restricts the activation of both banks  
immediately. Also the noise generated during  
sensing of each bank of SGRAM is high  
requiring some time for power supplies to  
recover before another bank can be sensed  
reliably. tRRD (min) specifies the minimum time  
required between activating different bank. The  
number of clock cycles required between  
different bank activation must be calculated  
similar to tRCD specification. The minimum time  
required for the bank to be active to initiate  
sensing and restoring the complete row of  
dynamic cells is determined by tRAS (min). Every  
SGRAM bank activate command must satisfy  
tRAS (min) specification before a precharge  
command to that active bank can be asserted.  
The maximum time any bank can be in the  
active state is determined by tRAS (max). The  
number of cycles for both tRAS(min) and tRAS  
(max) can be calculated similar to tRCD  
specification.  
cf.) Sequence of 4 & 5 may be changed.  
MODE REGISTER SET (MRS)  
The mode register stores the data for controlling the  
various operating modes of SGRAM. It programs  
the CAS latency, burst type, addressing, burst  
length, test mode and various vendor specific  
options to make SGRAM useful for variety of  
different applications. The default value of the  
mode register is not defined, therefore the mode  
register must be written after power up to operate  
the SGRAM. The mode register is written by  
asserting low on CS, RAS , CAS, WE and  
DSF (The SGRAM should be in active mode with  
CKE already high prior to writing the mode  
register). The state of address pins A0~A9 and A10  
in the same cycle as CS, RAS , CAS, WE and  
DSF going low is the data written in the mode  
register. One clock cycles is required to complete  
the write in the mode register. The mode register  
contents can be changed using the same command  
and clock cycle requirements during operation as  
long as both banks are in the idle state. The mode  
register is divided into various fields depending  
on functionality. The burst length field uses  
A0~A2, burst type uses A3, CAS latency (read  
latency from column address) A4~A6, A7~A8 and  
A10 are uses for vendor specific options or test  
mode use. And the write burst length is  
programmed using A9. A7~A8 and A10 must be  
set to low for normal SGRAM operation. Refer to  
the table for specific codes for various burst length,  
BURST READ  
addressing modes and CAS latencies.  
The burst read command is used to access burst  
of data on consecutive clock cycles from an  
Elite Semiconductor Memory Technology Inc.  
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M32L1632512A  
DEVICE OPERATIONS (Continued)  
active row in an active bank. The burst read  
command is issued by asserting low on CS and  
The write burst can also be terminated by using  
DQM for blocking data and precharging the  
bank “tRDL” after the last data input to be written  
into the active row. See DQM OPERATION  
also.  
CAS with WE being high on the positive edge of  
the clock. The bank must be active for at least tRCD  
before the burst read command is issued. The  
(min)  
first output appears in CAS latency number of  
clock cycles after the issue of burst read command.  
The burst length, burst sequence and latency from  
the burst read command is determined by the mode  
register which is already programmed. The burst  
read can be initiated on any column address of the  
active row. The address wraps around if the initial  
address does not start from a boundary such that  
number of outputs from each I/O are equal to the  
burst length programmed in the mode register. The  
output goes into high-impedance at the end of burst,  
unless a new burst read was initiated to keep the  
data output gapless. The burst read can be  
terminated by issuing another burst read or burst  
write in the same bank or the other active bank or a  
precharge command to the same bank. The burst  
stop command is valid for all burst length.  
DQM OPERATION  
The DQM is used mask input and output  
operations. It works similar to OE during  
operation and inhibits writing during write  
operation. The read latency is two cycles from  
DQM and zero cycle for write, which means  
DQM masking occurs two cycles later in read  
cycle and occurs in the same cycle during write  
cycle. DQM operation is synchronous with the  
clock. The DQM signal is important during  
burst interrupts of write with read or precharge  
in the SGRAM. Due to asynchronous nature of  
the internal write, the DQM operation is critical  
to avoid unwanted or incomplete writes when  
the complete burst write is required. DQM is  
also used for device selection and bus control in  
a memory system. DQM0 controls DQ0 to  
DQ7, DQM1 controls DQ8 to DQ15, DQM2  
controls DQ16 to DQ23, DQM3 controls DQ24  
to DQ31. DQM masks the DQ’s by a byte  
regardless that the corresponding DQ’s are in a  
state of WPB masking or Pixel masking. Please  
refer to DQM timing diagram also.  
BURST WRITE  
The burst write command is similar to burst read  
command, and is used to write data into the  
SGRAM on consecutive clock cycles in adjacent  
addresses depending on burst length and burst  
sequence. By asserting low on CS, CAS and  
WE with valid column address, a write burst is  
initiated. The data inputs are provided for the initial  
address in the same clock cycle as the burst write  
command. The input buffer is deselected at the end  
of the burst length, even though the internal writing  
may not have been completed yet. The writing can  
not complete to burst length. The burst write can be  
terminated by issuing a burst read and DQM for  
blocking data inputs or burst write in the same or  
the other active bank.  
PRECHARGE  
The precharge is performed on an active bank  
by asserting low on  
,
,
and A9  
CS RAS WE  
with valid A10 of the bank to be precharged.  
The precharge command can be asserted  
anytime after tRAS (min) is satisfy from the bank  
activate command in the desired bank. “tRP” is  
defined as the minimum time required to  
precharge a bank.  
Elite Semiconductor Memory Technology Inc.  
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Revision : 1.6  
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M32L1632512A  
DEVICE OPERATIONS (Continued)  
The minimum number of clock cycles required to  
complete row precharge is calculated by dividing  
“tRP” with clock cycle time and rounding up to the  
next higher integer. Care should be taken to make  
sure that burst write is completed or DQM is used  
to inhibit writing before precharge command is  
asserted. The maximum time any bank can be  
active is specified by tRAS (max). Therefore, each  
bank has to be precharged within tRAS (max) from  
the bank activate command. At the end of  
precharge, the bank enters the idle state and is ready  
to be activated again.  
AUTO REFRESH  
The storage cells of SGRAM need to be  
refreshed every 32ms to maintain data. An auto  
refresh cycle accomplishes refresh of a single  
row of storage cells. The internal counter  
increments automatically on every auto refresh  
cycle to refresh all the rows. An auto refresh  
command is issued by asserting low on  
,
CS  
and  
with high on CKE and  
WE  
.
RAS  
CAS  
The auto refresh command can only be asserted  
with both banks being in idle state and the  
device is not in power down mode (CKE is high  
in the previous cycle). The time required to  
complete the auto refresh operation is specified  
by tRC (min). The minimum number of clock  
cycles required can be calculated by driving tRC  
with clock cycle time and them rounding up to  
the next higher integer. The auto refresh  
command must be followed by NOP’s until the  
auto refresh operation is completed. Both banks  
will be in the idle state at the end of auto refresh  
operation. The auto refresh is the preferred  
refresh mode when the SGRAM is being used  
for normal data transactions. The auto refresh  
cycle can be performed once in 15.6us or the  
burst of 2048 auto refresh cycles in 32ms.  
Entry to Power Down, Auto refresh, Self refresh  
and Mode register Set etc. is possible only when  
both banks are in idle state.  
AUTO PRECHARGE  
The precharge operation can also be performed by  
using auto precharge. The SGRAM internally  
generates the timing to satisfy tRAS (min) and “tRP” for  
the programmed burst length and CAS latency.  
The auto precharge command is issued at the same  
time as burst read or burst write by asserting high  
on A9. If burst read or burst write command is  
issued with low on A9, the bank is left active until a  
new command is asserted. Once auto precharge  
command is given, no new command are possible  
to that particular bank until the bank achieves idle  
state.  
SELF REFRESH  
The self refresh is another refresh mode  
available in the SGRAM. The self refresh is the  
preferred refresh mode for data retention and  
low power operation of SGRAM. In self refresh  
mode, the SGRAM disables the internal clock  
and all the input buffers except CKE. The  
refresh addressing and timing is internally  
generated to reduce power consumption.  
BOTH BANKS PRECHARGE  
Both banks can be precharged at the same time by  
using Precharge all command. Asserting low on  
CS, RAS and WE with high on A9 after all  
banks have satisfied tRAS (min) requirement, performs  
precharge on both banks. At the end of tRP after  
performing precharge all, all banks are in idle state.  
The self refresh mode is entered from all banks  
idle state by asserting low on CS, RAS ,  
CAS and CKE with high on WE . Once the  
self refresh mode is entered, only CKE state  
Elite Semiconductor Memory Technology Inc.  
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M32L1632512A  
DEVICE OPERATIONS (Continued)  
being low matters, all the other inputs including  
clock are ignored to remain in the refresh.  
the condition that DQ’s are idle. As in write  
operation, SMRS accepts the data needed  
through DQ pins. Therefore it should be  
attended not to induce bus contention. The more  
detailed materials can be obtained by referring  
corresponding timing diagram.  
The self refresh is exited by restarting the external  
clock and then asserting high on CKE. This must be  
followed by NOP’s for a minimum time of tRC  
before the SGRAM reaches idle state to begin  
normal operation. If the system uses burst auto  
refresh during normal operation, it is recommended  
to use burst 2048 auto refresh cycles immediately  
after exiting self refresh.  
WRITE PER BIT  
Write per bit(i.e. I/O mask mode) for SGRAM  
is a function that selectively masks bits of data  
being written to the devices. The mask is stored  
in an internal register and applied to each bit of  
data written when enable. Bank active command  
with DSF=High enable write per bit for the  
associated bank. The mask used for write per bit  
operations is stored in the mask register  
accessed by SWCBR (Special Mode Register  
Set Command). When a mask bit=0, the  
associated data bit is unaltered when a write  
command is executed and the write per bit has  
been enable for the bank being written. No  
additional timing conditions. Write per bit  
writes can be either masking is the same for  
write per bit and non-WPB write.  
DEFINE SPECIAL FUNCTION(DSF)  
The DSF controls the graphic applications of  
SGRAM. If DSF is tied to low, SGRAM functions  
as 256K x 32 x 2 Bank SDRAM. SGRAM can be  
used as an unified memory by the appropriate DSF  
command. All the graphic function mode can be  
entered only by setting DSF high when issuing  
commands which otherwise would be normal  
SDRAM commands.  
SDRAM functions such as RAS Active, Write and  
WCBR change to SGRAM functions such as RAS  
Active with WPB, Block Write and SWCBR  
respectively, see the sessions below for the graphic  
functions that DSF controls.  
BLOCK WRITE  
Block write is  
a
feature allowing the  
SPECIAL MODE REGISTER SET(SMRS)  
simultaneous writing of consecutive 8 columns  
of data within a RAM device during a single  
access cycle. During block write the data to be  
written comes from the internal “color” register  
and DQ I/O pins are used for independent  
column selection. The block of column to be  
written is aligned on 8 column boundaries and is  
defined by the column address with the 3 LSB’s  
ignored. Write command with DSF=1 enable  
block write for the associated bank. The block  
width is 8 column where column =”n” bits for  
by “n” part. The color register is the same width  
as the data port of the chip. It is width via a  
SWCBR where data present on the DQ pins is  
There are two kinds of special mode registers in  
SGRAM. One is color register and the other is  
mask register. Those usage will be explained at  
“WRITE PER BIT” and “BLOCK WRITE”  
session. When A5 and DSF goes high in the same  
cycle as CS, RAS , CAS and WE going low,  
load color register is filled with color data for  
associated DQ’s through the DQ pins. If both A5  
and A6 are high at SMRS, data of mask and color  
cycle is required to complete the write in the mask  
register and the color register at LMR and LCR  
respectively. The next color of LMR and LCR, a  
new commands can be issued. SMRS, compared  
with MRS, can be issued at the active state under  
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M32L1632512A  
DEVICE OPERATIONS (Continued)  
Timing Diagram to Illustrate tBWC  
to be coupled into the internal color register. The  
color register provides the data masked by the DQ  
column select, WPB mask (if enable), and DQM  
byte mask. Column data masking (Pixel masking) is  
provided on an individual column basis for each  
byte of data. The column mask is driven on the DQ  
pins during a block write command. The DQ  
column mask function is segmented on a per bit  
basis (i.e. DQ [0:7] provided the column mask for  
data bits [0:7], DQ [8:15] provided the column mask  
for data bits [8:15], DQ0 masks column [0] for data  
bits[0:7], DQ9 masks column [1] for data bits[8:15],  
etc). Block writes are always non-burst independent  
of the burst length that has been programmed into to  
the mode register. If write per bit was enabled by the  
bank active command with DSF=1, then write per  
bit masking of the color register data is enabled.  
If write per bit was disabled by a bank active  
command with DSF=0, the write per bit masking of  
the color register data is disabled. DQM masking  
provides independent data byte masking during  
normal write operations, except that the control is  
extended to the consecutive 8 columns of the block  
write.  
1. 2CLK Cycle Block Write  
C L O C K  
H IG H  
C K E  
C S  
R A S  
C A S  
W E  
D S F  
2
C L K B W  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 18/54  
M32L1632512A  
SUMMARY OF 2M Byte SGRAM BASIC FEATURES AND BENEFITS  
Features  
256K x 32 x 2 SGRAM  
Benefits  
Better interaction between memory and system without wait-state  
of asynchronous DRAM.  
Interface  
Bank  
Synchronous  
High speed vertical and horizontal drawing.  
High operation frequency allows performance gain for SCROLL,  
FILL, and BitBLT.  
Pseudo-infinite row length by on-chip interleaving operation.  
Hidden row activation precharge.  
2ea  
Page Depth /1 Row  
Total Page Depth  
256 bit  
High speed vertical and horizontal drawing.  
High speed vertical and horizontal drawing.  
2048 bytes  
Programmable burst of 1, 2, 4, 8 and full page transfer per column  
address.  
Burst length (Read)  
1, 2, 4, 8 Full Page  
1, 2, 4, 8 Full Page  
Programmable burst of 1, 2, 4, 8 and full page transfer per column  
address.  
Burst length (Write)  
BRSW  
Sequential & Interleave  
2, 3  
Switch to burst length of 1 at write without MRS.  
Compatible with Intel and Motorola CPU based system.  
Programmable CAS latency.  
Burst Type  
CAS Latency  
High speed FILL, CLEAR, Text with color registers.  
Maximum 32 byte data transfer (e.g. for 8bpp : 32 pixels) with  
plane and byte masking functions.  
Block Write  
8 Column  
Color Register  
Mask Register  
1ea.  
1 ea.  
A and B bank share.  
Write-per-bit capability (bit plane masking). A and B bank share.  
Byte masking (pixel masking for 8bpp system) for data-out/in  
DQM0~3  
Each bit of the mask register directly controls a corresponding bit  
plane.  
Mask function  
Write per bit  
Pixel Mask at Block Write Byte masking (pixel masking for 8bpp system) for color DQi.  
BASIC FEATURE AND FUNCTION DESCRIPTION  
1.CLOCK Suspend  
1 ) C l o c k S u s p e n d e d D u r i n g W r i t e ( B L = 4 )  
2 ) C l o c k S u s p e n d e d D u r i n g R e a d ( B L = 4 )  
C L K  
C MD  
W R  
R D  
C K E  
M a s k e d b y C K E  
M a s k e d b y C K E  
I n t e r n a l  
C L K  
D 3  
D 3  
D Q ( C L2 )  
D Q ( C L 3 )  
D 2  
Q 2  
Q 1  
Q 3  
Q 2  
D 0  
D 0  
Q 0  
Q 1  
Q 0  
D 1  
D 1  
D 2  
Q 3  
S u s p e n d e d D o u t  
N o t W r i t t e n  
*Note : CKE to CLK disable/enable=1 clock  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 19/54  
M32L1632512A  
2. DQM Operation  
2 ) R e a d M a s k ( B L = 4 )  
1 ) W r i t e M a s k ( B L = 4 )  
C L K  
C M D  
W R  
R D  
D Q M  
D Q ( C L 2 )  
D Q ( C L3 )  
M a s k e d b y D Q M  
M a s k e d b y D Q M  
D 3  
H i - Z  
Q 2  
Q 1  
Q 3  
Q 2  
D 0  
D 0  
D 1  
D 1  
Q 0  
H i - Z  
D 3  
Q 3  
D Q M t o D a t a - o u t M a s k = 2  
D Q M t o D a t a - i n M a s k = 0 C L K  
3 ) D Q M w i t h c l c o k s u s p e n d e d ( F u l l P a g e R e a d )  
N o t e 2  
C L K  
R D  
C M D  
C K E  
D Q M  
H i - Z  
H i - Z  
H i - Z  
H i - Z  
H i - Z  
Q 6  
Q 5  
Q 8  
Q 7  
Q 2  
Q 1  
Q 7  
Q 6  
Q 4  
Q 3  
Q 0  
D Q ( C L2 )  
D Q ( C L 3 )  
H i - Z  
*Note : 1. There are 4 DQMi (i = 0~3).  
Each DQMi masks 8 DQ’s. (1 Byte, 1 Pixel for 8bpp).  
2. DQM masks data out Hi-Z after 2 clocks which should masked by CKE “L”.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 20/54  
M32L1632512A  
3.  
Interrupt (I)  
CAS  
* N o t e 1  
1 ) R e a d i n t e r r u p t e d b y R e a d ( B L = 4 )  
C L K  
C M D  
AD D  
R D  
A
R D  
B
Q A0  
D Q ( C L2 )  
D Q ( C L 3 )  
Q B 1 Q B 2 Q B 3  
Q B 0  
Q A0  
Q B 0 Q B 1  
Q B 3  
Q B 2  
t C C D  
* N o t e  
2
2 ) W r i t e i n t e r r u p t e d b y ( B l o c k ) W r i t e ( B L = 2 )  
3 ) W r i t e i n t e r r u p t e d b y R e a d ( B L = 2 )  
C L K  
B W  
W R  
R D  
C M D  
W R  
W R  
W R  
t C C D  
t C C D  
* N o t e  
2
* N o t e 2  
t C C D  
* N o t e  
2
A
B
A
A
AD D  
D Q  
B
B
* N o t e  
4
D A0  
D A0  
D B 1  
P i x e l  
D B 0  
D A0 D B 0  
D C 0  
D B 1  
D Q ( C L 2 )  
D Q ( C L 3 )  
t C D L  
t C D L  
D B 0 D B 1  
* N o t e  
3
* N o t e  
3
t C D L  
* N o t e  
3
4 ) B l o c k W r i t e t o B l o c k W r i t e  
C L K  
N O P  
B W  
B
B W  
C M D  
AD D  
N o t e  
7
A
X
N o t e  
4
P i x e l  
P i x e l  
D Q  
t B W C  
* N o t e  
6
*Note : 1. By “Interrupt”, It is possible to stop burst read/write by external before the end of burst.  
By “ CAS Interrupt”, to stop burst read/write by CAS access ; read, write and block write.  
2.tCCD : CAS to CAS delay.(=1CLK)  
3.tCDL : Last Data in to new column address delay.(=1CLK)  
4.Pixel : Pixel mask.  
5.tCC : Clock cycle time.  
6.tBWC : Block write minimum cycle time.  
7.Other Bank can be active or precharge.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 21/54  
M32L1632512A  
4. CAS Interrupt ( ) : Read Interrupted by Write & DQM  
(1) CL=2, BL=4  
C L K  
i )C M D  
R D  
R D  
R D  
W R  
D 0  
DQ M  
D 1  
DQ  
D 2  
D 3  
i i )C M D  
W R  
DQ M  
DQ  
H i - Z  
D 0  
D 1  
D 2  
D 3  
i i i )C M D  
W R  
D Q M  
D Q  
H i - Z  
D 2  
D 0  
D 3  
D 1  
W R  
i v )C M D  
R D  
D Q M  
DQ  
H i - Z  
Q 0  
D 2  
D 0  
D 1  
D 3  
*N o t e 1  
(2) CL=3 , BL=4  
C L K  
i )C M D  
R D  
W R  
D 0  
D Q M  
D Q  
D 3  
D 2  
D 1  
W R  
i i )C M D  
D Q M  
R D  
R D  
R D  
R D  
D 0  
D 1  
D 2  
D 3  
D Q  
i i i )C M D  
D Q M  
W R  
D 0  
D 1  
D 2  
D 3  
D 2  
D 1  
DQ  
i v)C M D  
D Q M  
W R  
H i - Z  
D 0  
D 3  
D Q  
D 1  
W R  
v) C M D  
D Q M  
H i - Z  
D 0  
D Q  
Q 0  
D 2  
D 3  
* N o t e 2  
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.  
2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 22/54  
M32L1632512A  
5. Write Interrupted by Precharge & DQM  
C L K  
* N o t e 2  
C MD  
P R E  
W R  
D 0  
* N o t e 1  
D Q M  
D Q  
D 2  
D 3  
D 1  
M a s k e d b y D Q M  
*Note : 1. To inhibit invalid write, DQM should be issued.  
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt  
but only another bank precharge of dual banks operation.  
6. Precharge  
1) Normal Write (BL = 4)  
2) Block Write  
C L K  
C MD  
C L K  
C MD  
P R E  
P R E  
W R  
D 0  
B W  
DQ  
P i x e l  
D 2  
D 3  
D Q  
D 1  
t B P L  
* N o t e 1  
t R D L  
* N o t e 1  
3) Read (BL=4)  
C L K  
C M D  
P R E  
R D  
1* N o t e 2  
Q 3  
Q 2  
D Q ( C L 2 )  
D Q ( C L 3 )  
Q 0  
Q 1  
Q 2  
Q 1  
2
Q 0  
Q 3  
7. Auto Precharge  
1) Normal Write (BL = 4)  
2) Block Write  
C L K  
C MD  
D Q  
C L K  
C M D  
DQ  
B W  
W R  
D 0  
D 2  
D 3  
D 1  
P i x e l  
t B P L  
t R P  
t B A L  
* N o t e 3  
A u t o P r e c h a r g e s t a r t s  
* N o t e 3  
Au t o P r e c h a r g e s t a r t s  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 23/54  
M32L1632512A  
3) Read (BL=4)  
C L K  
C M D  
R D  
D Q ( C L 2 )  
D Q ( C L 3 )  
Q 0  
Q 2  
Q 1  
Q 3  
Q 1  
Q 0  
Q 2  
Q 3  
* N o t e 3  
A u t o P r e c h a r g e s t a r t s  
*Note : 1. tRDL : Write data-in to PRE command delay, tBPL : Block Write data-in to PRE command delay.  
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.  
3. The row active command of the precharge bank can be issued after tRP from this point.  
The new read/write command of other activated bank can be issued from this point.  
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.  
4. For -5S/-6S/-7S/-8S, auto precharge after a normal write starts at clock(n+BL+1).  
8. Burst Stop & Precharge Interrupted  
1) Write interrupted by Precharge (BL=4)  
2) Write Burst Stop (Full Page Only)  
C L K  
C M D  
C L K  
C M D  
S T O P  
P R E  
W R  
W R  
D Q M  
D Q  
D Q  
D 3  
D 0  
D 2  
D 0  
D 1  
D 1  
D 2  
* N o t e 1  
t B D L  
t R D L  
3) Read interrupted by Precharge (BL=4)  
4) Read Burst Stop (Full Page Only)  
C L K  
C M D  
C L K  
C MD  
D Q (C L2 )  
D Q (C L3 )  
S TO P  
Q 0  
R D  
R D  
P R E  
Q 0  
* N o t e 3  
1
* N o t e 3  
1
Q 1  
Q 0  
Q 1  
Q 0  
D Q (C L2 )  
D Q (C L3 )  
2
2
Q 1  
Q 1  
9. MRS & SMRS  
1) Mode Register Set  
2) Special Mode Register Set  
C L K  
C M D  
C L K  
* N o t e 4  
C M D  
P R E  
S M R S AC T  
S M R S  
AC T  
S M R S AC T  
M R S  
1 C L K  
1 C L K  
1 C L K  
1 C L K  
1 C L K  
t R P  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 24/54  
M32L1632512A  
*Note: 1. tRDL : 1 CLK ; Last data in to Row Precharge.  
2. tBDL : 1 CLK ; Last data in to Burst Stop Delay.  
3. Number of valid output data after Row Precharge or burst stop : 1, 2 for CAS latency = 2, 3 respectively.  
4. PRE : Both banks precharge, if necessary.  
MRS can be issued only at all banks precharge state.  
10. Clock Suspend Exit & Power Down Exit  
1) Clock Supend (=Active Power Down) Exit  
2) Power Down (=Precharge Power Down) Exit  
C L K  
C L K  
C K E  
C K E  
t S S  
t S S  
I n t e r n a l  
C L K  
I n t e r n a l  
* N o t e 1  
* N o t e 2  
C LK  
R D  
C M D  
AC T  
C MD  
N O P  
11. Auto Refresh & Self Refresh  
*Note3  
1) Auto Refresh  
C L K  
* N o t e 4  
* N o t e 5  
C MD  
C K E  
AR  
P R E  
C M D  
t R P  
t R C  
*Note6  
1) Self Refresh  
C L K  
C M D  
* N o t e 4  
P R E  
C M D  
S R  
C K E  
t R P  
t R C  
*Note 1. Active power down : one or more banks active state.  
:
2. Precharge power down : both banks precharge state.  
3. The auto refresh is the same as CBR refresh of conventional DRAM.  
No precharge commands are required after Auto Refresh command.  
During tRC from auto refresh command, any other command can not be accepted.  
4. Before executing auto/self refresh command, both banks must be idle state.  
5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.  
6. During self refresh mode, refresh interval and refresh operation are performed internally.  
After self refresh entry, self refresh mode is kept while CKE is low.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 25/54  
M32L1632512A  
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.  
During tRC from self refresh exit command, any other command can not be accepted.  
Before/After self refresh mode, burst auto refresh (2K cycles) is recommended.  
12. About Burst Type Control  
At MRS A3=”0”. See the BURST SEQUENCE TABLE. (BL=4, 8)  
BL=1, 2, 4, 8 and full page wrap around.  
Sequential Counting  
Interleave Counting  
Basic  
Mode  
At MRS A3=”1”. See the BURST SEQUENCE TABLE. (BL=4, 8)  
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting  
At MRS A3=”1”. (See to interleave Counting Mode)  
Staring Address LSB 3 bits A 0-2 should be “000” or “111”. @BL=8  
- if LSB =”000” : Increment Counting.  
- if LSB =”111” : Decrement Counting.  
Pseudo-  
Document Sequential  
Counting  
For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8)  
-- @ write, LSB =”000”, Accessed Column in order 0-1-2-3-4-5-6-7  
-- @ read, LSB =”111”, Accessed Column in order 7-6-5-4-3-2-1-0  
At BL=4, same applications are possible. As above example, at interleave Counting  
mode, by confining starting address to some value, Pseudo-Decrement Counting  
Mode can be realize. See the BURST SEQUENCE TABLE carefully.  
Pseudo-  
MODE  
At MRS A3=”0”. (See to Sequential Counting Mode)  
A0-2 =”111”. (See to Full Page Mode)  
Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be  
realize.  
-- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8)  
-- @ Pseudo-Binary Counting  
Pseudo-  
Binary Counting  
Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command)  
Note. The next column address of 256 is 0.  
Random column  
Access  
Every cycle Read/Write Command with random column address can realize  
Random Column Access  
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.  
Random  
MODE  
tCCD = 1 CLK  
13. About Burst Length Control  
At MRS A2, 1, 0 =”000”.  
1
At auto precharge, tRAS should not be violated.  
Basic  
MODE  
At MRS A2, 1, 0 =”001”.  
2
At auto precharge, tRAS should not be violated.  
4
8
At MRS A2, 1, 0 =”010”.  
At MRS A2, 1, 0 =”011”.  
At MRS A2, 1, 0 =”111”.  
Full Page  
Wrap around mode (Infinite burst length) should be stopped by burst stop.  
RAS interrupt or CAS interrupt.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6  
26/54  
M32L1632512A  
At MRS A9 =”1”  
Read Burst =1, 2, 4, 8, full page/write Burst =1  
BRSW  
Special  
MODE  
At auto precharge of write, tRAS should not be violated.  
8 Column Block Write. LSB A0-2 are ignored. Burst length =1  
tRAS should not be violated.  
Block Write  
At auto precharge, tRAS should not be violated.  
Random  
MODE  
tBDL =1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively.  
Using burst stop command, random mode it is possible only at full page burst  
length.  
Burst Stop  
Before the end of burst, Row precharge command of the same bank stops read/write  
burst with Row precharge.  
RAS interrupt  
(Interrupted by  
Precharge)  
tRDL =1 with DQM, valid DQ after burst stop is 1, 2 for CL = 2, 3 respectively  
During read/write burst with auto precharge, RAS interrupt can not be issued.  
Interrupt  
MODE  
Before the end of burst, new read/write stops read/write burst and starts new  
read/write burst or block write.  
CAS Interrupt  
During read/write burst with auto precharge, CAS interrupt can not be issued.  
14. Mask Function  
1) Normal Write  
I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.  
If bit plane 0, 3, 7, 9, 19, 22, 24 and 31 keep the original value.  
i) STEP  
I SMRS(LMR) : Load mask [31-0]=”0111, 1110, 1011, 0111, 1111, 1101, 0111, 0110”  
II Row Active with DSF “H” : Write Per Bit Mode Enable  
III Perform Normal Write  
i) ILLUSTRATION  
I/O (=DQ)  
External Data-in  
DQMi  
31  
24  
23  
16  
15  
8
7
0
1 1 1 1 1 1 1 1  
DQM3=0  
1 1 1 1 1 1 1 1  
DQM2=0  
0 0 0 0 0 0 0 0  
DQM1=0  
0 0 0 0 0 0 0 0  
DQM0=1  
Mask Register  
Before Write  
After Write  
0 1 1 1 1 1 1 0  
0 0 0 0 0 0 0 0  
0 1 1 1 1 1 1 0  
1 0 1 1 0 1 1 1  
0 0 0 0 0 0 0 0  
1 0 1 1 0 1 1 1  
1 1 1 1 1 1 0 1  
1 1 1 1 1 1 1 1  
0 0 0 0 0 0 1 0  
0 1 1 1 0 1 1 0  
1 1 1 1 1 1 1 1  
1 1 1 1 1 1 1 1  
Note 1  
2) Block Write  
Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data.  
See PIXEL TO DQ MAPPING TABLE.  
If Pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color.  
Assume 8bpp  
White = “0000, 0000”, Red = “1010, 0011”, Green = “1110, 0001”, Yellow = “0000, 1111”, Blue = “1100, 0011”  
i) STEP  
I SMRS(LCR) : Load color (for 8bpp, through x32 DQ color0-3 are loaded into color registers)  
Load (color3, color2, color1, color0) = (Blue, Green, Yellow, Red)  
= ”1100, 0011, 1110, 0001, 0000, 1111, 1010, 0011 ”  
II Row Active with DSF “L” : I/O Mask by Write Per Bit Mode Disable  
III Block write with DQ[31-0] = “0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110”  
* Note : 1. DQM byte masking.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 27/54  
M32L1632512A  
(Continued)  
i) ILLUSTRATION  
I/O (=DQ)  
DQMi  
31  
24  
23  
16  
15  
DQM1=0  
8
7
0
DQM3=0  
DQM2=0  
DQM0=1  
Color Register  
000  
Color3=Blue  
White DQ24=H  
White DQ25=H  
White DQ26=H  
White DQ27=L  
White DQ28=H  
White DQ29=H  
White DQ30=H  
White DQ31=L  
Color2=Green  
White DQ16=H  
White DQ17=H  
White DQ18=L  
White DQ19=H  
White DQ20=H  
White DQ21=H  
White DQ22=L  
White DQ23=H  
Color1=Yellow  
White DQ8=H  
White DQ9=L  
White DQ10=H  
White DQ11=H  
White DQ12=H  
White DQ13=L  
White DQ14=H  
White DQ15=H  
Color0=Red  
White DQ0=L  
White DQ1=H  
White DQ2=H  
White DQ3=H  
White DQ4=L  
White DQ5=H  
White DQ6=H  
White DQ7=H  
Before  
Block  
Write  
&
001  
010  
011  
100  
101  
110  
111  
DQ  
(Pixel  
data)  
000  
001  
Blue  
Blue  
Blue  
White  
Blue  
Blue  
Blue  
White  
Green  
Green  
White  
Green  
Green  
Green  
White  
Green  
Yellow  
White  
White  
White  
White  
White  
White  
White  
White  
White  
010  
Yellow  
Yellow  
Yellow  
White  
After  
Block  
Write  
011  
100  
101  
110  
Yellow  
Yellow  
111  
Note 1  
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.  
By Pixel Data issued through DQ pin, the selected pixels keep the original data.  
See PIXEL TO DQ MAPPING TABLE.  
Assume 8bpp,  
White = “0000, 0000”, Red = “1010, 0011”, Green = “1110, 0001”, Yellow = “0000, 1111”, Blue = “1100, 0011”  
i) STEP  
I SMRS(LCR) : Load color (for 8bpp, through x 32 DQ color0-3 are loaded into color registers)  
Load (color3, color2, color1, color0, ) = (Blue, Green, Yellow, Red)  
=”1100, 0011, 1110, 0001, 0000, 1111, 1010, 0011”  
II SMRS(LMR) Load mask. Mask[31-0] = ”1111.1111. 1101, 1101, 0100, 0010, 0111, 0110”  
Byte 3 : No I/O Masking ; Byte 2 : I/O Masking ; Byte 1 : I/O and Pixel Masking ; Byte 0 : DQM Byte Masking  
III Row Active with DSF “H” : I/O mask by Write Per Bit Mode Enable  
IV Block Write with DQ [31-0] = ”0111, 0111 .1111, 1111, 0101, 0101, 1110, 1110 ”(Pixel Mask)  
*Note : 1. At normal write, ONE column is selected among columns decorded by A2-0 (000-111).  
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 28/54  
M32L1632512A  
i) ILLUSTRATION  
I/O (=DQ)  
31  
24  
23  
16  
15  
6
7
0
Blue  
1 1 0 0 0 0 1 1  
Green  
1 1 1 0 0 0 0 1  
Yellow  
0 0 0 0 1 1 1 1  
Red  
1 0 1 0 0 0 1 1  
Color Register  
DQMi  
DQM3=0  
DQM2=0  
DQM1=0  
DQM0=1  
Mask Register  
1 1 1 1 1 1 1 1  
1 1 0 1 1 1 0 1  
0 1 0 0 0 0 1 0  
0 1 1 1 0 1 1 0  
Yellow  
0 0 0 0 1 1 1 1  
Yellow  
0 0 0 0 1 1 1 1  
Green  
1 1 1 0 0 0 0 1  
White  
0 0 0 0 0 0 0 0  
Before Write  
After Write  
Blue  
1 1 0 0 0 0 1 1  
Blue  
1 1 0 0 0 0 1 1  
Red  
1 0 1 0 0 0 1 1  
White  
0 0 0 0 0 0 0 0  
I/O (=DQ)  
DQMi  
31  
24  
23  
16  
15  
DQM1=0  
6
7
0
DQM3=0  
DQM2=0  
DQM0=1  
Color Register  
000  
Color3=Blue  
Color2=Green  
Yellow DQ16=H  
Yellow DQ17=H  
Yellow DQ18=H  
Yellow DQ19=H  
Yellow DQ20=H  
Yellow DQ21=H  
Yellow DQ22=H  
Yellow DQ23=H  
Color1=Yellow  
Green DQ8=H  
Green DQ9=L  
Green DQ10=H  
Green DQ11=L  
Green DQ12=H  
Green DQ13=L  
Green DQ14=H  
Green DQ15=L  
Color0=Red  
White DQ0=L  
White DQ1=H  
White DQ2=H  
White DQ3=H  
White DQ4=L  
White DQ5=H  
White DQ6=H  
White DQ7=H  
Yellow DQ24=H  
Yellow DQ25=H  
Yellow DQ26=H  
Yellow DQ27=L  
Yellow DQ28=H  
Yellow DQ29=H  
Yellow DQ30=H  
Yellow DQ31=L  
Before  
Block  
Write  
&
001  
010  
011  
100  
101  
110  
111  
DQ  
(Pixel  
data)  
000  
001  
Blue  
Blue  
Blue  
Blue  
Blue  
Blue  
Blue  
Blue  
Blue  
Blue  
Red  
Green  
Red  
White  
White  
White  
White  
White  
White  
White  
White  
Note 1  
010  
Blue  
After  
Block  
Write  
011  
Yellow  
Blue  
Green  
Red  
100  
101  
Blue  
Green  
Red  
110  
Blue  
Yellow  
111  
Green  
Note 2  
PIXEL MASK  
I/O MASK  
PIXEL & I/O MASK  
BYTE MASK  
*Note : 1. DQM byte masking.  
2. At normal write, ONE column is selected among columns decorded by A2-0(000-111)  
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 29/54  
M32L1632512A  
FUNCTION TRUTH TABLE (TABLE 1)  
Current  
State  
BA  
(A10)  
X
X
X
BA  
BA  
BA  
X
BA  
X
DSF  
ADDR  
ACTION  
Note  
CS RAS CAS WE  
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
H
L
L
L
L
L
X
H
H
L
H
H
H
H
L
L
L
L
X
H
H
L
L
L
L
H
H
H
L
L
L
X
H
H
H
L
L
L
L
H
H
H
L
X
H
H
H
L
L
L
L
X
H
L
X
H
H
L
L
H
H
L
L
X
H
L
H
H
L
L
H
L
L
H
L
L
X
H
L
L
H
H
L
L
H
L
L
X
X
H
L
L
H
H
L
L
X
X
X
X
L
H
L
H
L
X
X
X
CA  
RA  
RA  
PA  
X
NOP  
NOP  
ILLEGAL  
ILLEGAL  
2
2
Row Active ; Latch Row Address ; Non-IO Mask  
Row Active ; Latch Row Address ; IO Mask  
Auto Refresh or Self Refresh  
NOP  
Auto Refresh or Self Refresh  
ILLEGAL  
Mode Register Access  
Special Mode Register Access  
NOP  
IDLE  
4
5
X
X
L
L
L
H
L
BA  
OP Code  
OP Code  
X
X
X
BA  
X
BA  
BA  
BA  
BA  
X
5
6
H
X
X
X
L
H
L
H
X
L
H
X
L
H
X
X
L
H
L
H
L
H
X
L
H
X
X
X
L
H
L
H
L
X
H
H
H
H
H
H
L
L
L
L
L
X
X
X
NOP  
ILLEGAL  
2
2
6
3
CA, AP Begin Read ; Latch CA ; Determine AP  
ILLEGAL  
X
Row  
Active  
CA, AP Begin Write ; Latch CA ; Determine AP  
CA, AP Begin Write ; Latch CA ; Determine AP  
RA  
RA  
X
ILLEGAL  
Precharge  
ILLEGAL  
ILLEGAL  
X
X
X
X
ILLEGAL  
L
OP Code  
X
X
X
X
Special Mode Register Access  
NOP (Continue Burst to End  
NOP (Continue Burst to End  
Term burst Row active  
ILLEGAL  
X
H
H
H
H
H
H
H
L
X
X
X
X
Row Active)  
Row Active)  
BA  
X
CA, AP Term burst, Begin Read ; Latch CA ; Determine AP  
Read  
X
ILLEGAL  
Term burst, Begin Write ; Latch CA ; Determine AP  
Term burst, Begin Write ; Latch CA ; Determine AP  
BA  
BA  
BA  
BA  
X
X
X
X
X
X
BA  
X
BA  
BA  
CA, AP  
CA, AP  
RA  
PA  
X
3
3
2
3
ILLEGAL  
L
L
L
Term Burst, Precharge timing for Reads  
ILLEGAL  
ILLEGAL  
X
X
X
X
X
H
H
H
H
H
H
H
NOP (Continue Burst to End  
NOP (Continue Burst to End  
Row Active)  
Row Active)  
Term burst  
ILLEGAL  
Row Active  
Write  
X
CA, AP Term burst, Begin Read ; Latch CA ; Determine AP  
3
X
ILLEGAL  
Term burst, Begin Write ; Latch CA ; Determine AP  
Term burst, Begin Write ; Latch CA ; Determine AP  
CA, AP  
CA, AP  
3
3
H
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 30/54  
M32L1632512A  
FUNCTION TRUTH TABLE (TABLE 1, Continued)  
Current  
State  
BA  
(A10)  
BA  
BA  
X
X
X
X
X
BA  
BA  
BA  
X
X
X
DSF  
ADDR  
ACTION  
Note  
CS RAS CAS WE  
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
H
H
H
L
X
H
H
L
L
H
L
X
H
H
L
H
L
X
L
RA  
RA  
X
X
X
ILLEGAL  
2
3
Write  
Term Burst : Precharge timing for Writes  
ILLEGAL  
H
X
X
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
ILLEGAL  
X
H
H
H
H
L
NOP(Continue Burst to End Precharge)  
NOP(Continue Burst to End Precharge)  
ILLEGAL  
X
X
Read with  
Auto  
Precharge  
H
L
CA, AP ILLEGAL  
CA, AP ILLEGAL  
RA, PA ILLEGAL  
2
2
X
X
X
H
L
H
L
X
X
X
L
X
X
X
X
ILLEGAL  
2
X
H
H
H
H
L
NOP(Continue Burst to End Precharge)  
NOP(Continue Burst to End Precharge)  
ILLEGAL  
Write with  
Auto  
Precharge  
X
BA  
BA  
BA  
X
CA, AP ILLEGAL  
CA, AP ILLEGAL  
RA, PA ILLEGAL  
2
2
L
H
L
L
X
X
X
ILLEGAL  
2
X
X
NOP Idle after tRP  
NOP Idle after tRP  
ILLEGAL  
L
H
H
H
X
X
X
L
L
L
L
H
H
L
L
H
L
H
H
L
X
H
L
X
X
X
X
X
X
Precharging  
BA  
BA  
BA  
CA, AP ILLEGAL  
RA  
PA  
2
2
2
ILLEGAL  
NOP Idle after tRP  
ILLEGAL  
L
H
L
X
L
X
X
X
X
X
X
X
X
X
4
NOP Row Active after tBWC  
NOP Row Active after tBWC  
ILLEGAL  
L
H
H
H
X
X
X
X
Block  
Write  
Recovering  
L
L
L
L
L
H
H
H
L
L
L
X
H
L
H
H
L
L
X
H
L
X
X
X
X
X
X
X
X
X
BA  
BA  
BA  
X
CA, AP ILLEGAL  
2
2
2
2
RA  
PA  
X
ILLEGAL  
Term Block Write : Precharge timing for Block Write  
ILLEGAL  
X
X
X
NOP Row Active after tRCD  
NOP Row Active after tRCD  
ILLEGAL  
L
H
H
H
X
X
X
X
Row  
Activating  
L
L
L
L
L
H
H
H
L
L
L
X
H
L
H
H
L
L
X
H
L
X
X
X
X
X
X
X
X
X
BA  
BA  
BA  
X
CA, AP ILLEGAL  
2
2
2
2
RA  
PA  
X
ILLEGAL  
ILLEGAL  
ILLEGAL  
X
X
X
NOP Idle after tRC  
NOP Idle after tRC  
ILLEGAL  
L
H
H
X
X
X
X
Refreshing  
L
L
L
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL  
ILLEGAL  
ABBREVIATIONS :  
RA = Row Address (A0~A9)  
NOP = No Operation Command  
BA = Bank Address (A10)  
CA = Column Address (A0~A7)  
PA = Precharge All (A9)  
AP = Auto Precharge (A9)  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 31/54  
M32L1632512A  
FUNCTION TRUTH TABLE (TABLE 1, Continued)  
*Note : 1. All entries assume the CKE was active (High) during the preceding clock cycle and the current clock cycle.  
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that  
bank.  
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.  
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).  
5. Illegal if any bank is not idle.  
6. Legal only if all banks are in idle or row active state.  
FUNCTION TRUTH TABLE for CKE (TABLE2)  
Current  
State  
CKE CKE  
DSF ADDR  
ACTION  
Note  
CS RAS CAS WE  
( n-1 )  
n
H
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
INVALID  
7
7
Exit Self Refresh  
after tRC  
after tRC  
Self  
L
H
L
H
H
H
X
X
Exit Self Refresh  
ILLEGAL  
ILLEGAL  
ILLEGAL  
NOP (Maintain Self Refresh)  
INVALID  
Exit Power Down ABI  
Exit Power Down ABI  
ILLEGAL  
ILLEGAL  
ILLEGAL  
NOP (Maintain Low Power Mode)  
Refer to Table 1  
Enter Power Down  
Enter Power Down  
ILLEGAL  
ILLEGAL  
ILLEGAL  
Enter Self Refresh  
ILLEGAL  
NOP  
Refresh  
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
H
L
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
Both  
Bank  
Precharge  
Power  
8
8
Down  
9
9
All  
Banks  
Idle  
L
L
9
X
X
X
X
X
Any State  
other than  
Listed  
Refer to Operations in Table 1  
Begin Clock Suspend next cycle  
Exit Clock Suspend next cycle  
Maintain Clock Suspend  
10  
10  
Above  
ABBREVIATIONS : ABI = All Banks Idle  
*Note : 7.After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low to  
high transition to issue a new command.  
8.CKE low to high transition is asynchronous as if restart internal clock.  
A minimum setup time “ tSS + one clock “ must be satisfy before any command other than exit.  
9.Power down and self refresh can be entered only from the all banks idle state.  
10.Must be a legal command.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 32/54  
M32L1632512A  
Power On Sequence & Auto Refresh  
11  
12  
13  
15  
17  
19  
0
1
2
3
6
8
9
10  
14  
16  
18  
4
5
7
C L O C K  
C K E  
H i gh l e v el i s n ec es s ar y  
C S  
tR C  
tR P  
R A S  
C A S  
KEY  
KEY  
KEY  
R a  
A D D R  
A10 /BA  
A9 /AP  
BS  
R a  
W E  
D S F  
D Q M  
D Q  
H i gh l ev el i s n ec es s ar y  
H i g h - z  
Au to Refr es h  
M o de R eg is t e r Set  
R ow A c t i v e  
Au to R ef res h  
Pr ec h arg e  
( A l l Ba n k s )  
(W r i te P er Bi t  
E na ble o r D is a bl e)  
:D on ' t C ar e  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 33/54  
M32L1632512A  
Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency = 3, Burst Length = 1  
tC H  
4
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
5
7
C L O C K  
C K E  
tC L  
tC C  
H I G H  
tR A S  
tR C  
* N ot e 1  
tS H  
tS S  
C S  
tR P  
tR C D  
tS H  
tS S  
R A S  
tC C D  
tS H  
tS S  
C A S  
tS S  
tS H  
C c  
R a  
C a  
C b  
R b  
A D D R  
tS H  
tS S  
* N o t e 2, 3  
BS  
* N ot e 2  
* N o t e 2 , 3  
BS  
* N o t e 2, 3 * N ot e 4  
* N ot e 2  
BS  
BS  
BS  
BS  
A10  
A9  
* N ot e 3  
* N ot e 3  
* N ot e 3 * N ot e 4  
R a  
R b  
tS H  
W E  
D S F  
tS S  
* N o t e 6  
* N ot e 5  
* No t e 5  
tS S  
tS H  
tS H  
tS S  
D Q M  
tR A C  
tS H  
tS A C  
tS L Z  
Qa  
D b  
Qc  
D Q  
tS S  
tO H  
tS H Z  
R o w A c t i v e  
( W r i te per B i t  
E n a bl e o r D i s abl e )  
R ead  
W r i t e  
o r  
Bl o c k W r i t e  
R ead  
R ow A c t i v e  
(W r i te P er B i t  
E na b le or D is a bl e)  
Pr ec h a rg e  
:D on ' t C a r e  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 34/54  
M32L1632512A  
* Note : 1. All input can be don’t care when  
is high at the CLK high going edge.  
CS  
2. Bank active & read/write are controlled by A10.  
A10  
0
Active & Read/Write  
Bank A  
1
Bank B  
3. Enable and disable auto precharge function are controlled by A9 in read/write command.  
A9  
0
A10  
0
Operation  
Disable auto precharge, leave bank A active at end of burst.  
1
0
1
Disable auto precharge, leave bank B active at end of burst.  
Enable auto precharge, precharge bank A at end of burst.  
Enable auto precharge, precharge bank B at end of burst.  
1
4. A9 and A10 control bank precharge when precharge command is asserted.  
A9  
0
A10  
0
Precharge  
Bank A  
0
1
Bank B  
1
X
Both Bank  
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.  
A10  
0
DSF  
L
Operation  
Bank A row active, disable write per bit function for bank A.  
H
L
Bank A row active, enable write per bit function for bank A.  
Bank B row active, disable write per bit function for bank B.  
Bank B row active, enable write per bit function for bank B.  
1
H
6. Block write/normal write is controlled by DSF.  
DSF  
L
Operation  
Minimum cycle time  
Normal write  
t
CCD  
H
Block write  
t
BWC  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 35/54  
M32L1632512A  
Read & Write Cycle at Same Bank @ Burst Length = 4  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
4
5
7
C L O C K  
H I G H  
C K E  
* N o t e 1  
tR C  
C S  
R C D  
t
R A S  
* N o t e 2  
C A S  
R a  
R b  
C b0  
C a0  
A D D R  
A10  
A9  
R a  
R b  
W E  
D S F  
D Q M  
tO H  
Qa3  
DQ C L = 2  
D b0 D b1  
Qa0 Qa1  
D b2 Db3  
Qa2  
tR A C  
R D L  
t
* N o t e 3  
* N o t e 4  
S A C  
t
S H Z  
t
tO H  
C L = 3  
Qa3  
Qa0  
Qa1 Qa2  
Db0  
Db1 Db2 Db3  
R A C  
* N o t e 3  
t
tR D L  
*N o t e 4  
tS A C  
tS H Z  
R ea d  
(A - Ban k )  
R ow A c t i v e  
( A- B an k )  
Prec ha rg e  
( A- B an k )  
W r i te  
(A - Ba n k )  
R ow A c t i v e  
( A- Ban k )  
Pre ch arg e  
( A- B an k )  
: D on ' t C ar e  
*Note :  
1. Minimum row cycle time is required to complete internal DRAM operation.  
2. Row precharge can interrupt burst on any cycle.[CAS Length - 1] valid output data available after Row. enters precharge. Last valid output will be  
Hi-Z after tSHZ  
from the clock.  
3. Access time from Row address. tCC *( tRCD +CAS latency - 1) + tSAC  
4. Output will be Hi-Z after the end of burst. (1, 2, 4 & 8)  
At Full page bit burst, burst is wrap-around.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 36/54  
M32L1632512A  
Page Read & Write Cycle Same Bank @ Burst Length = 4  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
4
5
7
C L O C K  
H I G H  
C K E  
C S  
tR C D  
R A S  
* N o t e 2  
C A S  
R a  
Cb0  
Cc 0  
C d0  
Ca0  
A D D R  
A10  
A9  
R a  
tR D L  
tC D L  
W E  
D S F  
* N o t e 2  
* N o t e 3  
* N o t e 1  
D Q M  
DQ C L= 2  
Qa0 Qa1 Qb0  
Qb1  
Qb0  
Dc 0 Dc 1 Dd0 Dd1  
CL = 3  
D c 0  
Dc 1 D d0  
Dd1  
Qa0  
Qa1  
Rea d  
( A- Ban k )  
Rea d  
( A- Ban k )  
Row Ac t i v e  
( A- B an k )  
W ri t e  
(A - Ban k )  
W r i te  
(A- Ba n k )  
Pre char ge  
( A- B an k )  
:D on' t C ar e  
* Note : 1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus  
contention.  
2. Row precharge will interrupt writing. Last data input, RDL before Row precharge, will be written.  
t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.  
Input data after Row precharge cycle will be masked internally.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 37/54  
M32L1632512A  
Block Write cycle (with Auto Precharge)  
12  
9
11  
13  
14  
15  
16  
17  
18  
19  
1
2
3
4
7
8
10  
5
6
0
C L O C K  
H I G H  
C K E  
C S  
R A S  
C A S  
* N ot e 4  
R Aa  
CB b  
CA b  
C Ba  
CAa  
RBa  
A D D R  
A10  
A9  
RAa  
RBa  
W E  
D SF  
* N o t e 2  
tB W C  
D Q M  
* N ot e 3  
* N o t e 1  
P ix e l  
M a s k  
P i x e l  
M a s k  
P ix e l  
M a s k  
P i xe l  
M a s k  
D Q  
Mas ked  
Bl oc k W r i t e  
(A -B an k )  
R ow Ac t i ve  
( B- Ban k )  
Row Ac t i ve w i t h  
W r i te- per - Bi t  
Enabl e  
Bl ock W r i t e w i t h  
Auto P rechar ge  
( B- Bank )  
Bl oc k W r i t e  
( B- Ban k )  
M asked  
( A- Bank )  
Bl ock W r i t e w i th  
Auto Pr echar ge  
( A- Bank)  
:D on't C ar e  
*Note : 1. Column Mask (DQi = L : Mask, DQi = H : Non Mask)  
2. BWC : Block Write Cycle time  
t
3. At Block Write, second cycle should be in NOP.  
Other Bank can be active or precharge.  
4. At Block Write. CA0-2 are ignored.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 38/54  
M32L1632512A  
SMRS and Block/Normal Write @ Burst Length = 4  
12  
11  
13  
14  
15  
9
16  
17  
18  
19  
1
2
3
4
5
6
7
8
10  
0
C L O C K  
H I G H  
C K E  
C S  
R A S  
C A S  
*N o t e 1  
R Ba  
RB a  
RB a  
RB a  
R Ba  
R Aa  
RAa  
RA a  
RA a  
R Aa  
CBa  
A 0 - 2  
CB a  
C Ba  
C Ba  
A3,4,7, 8  
C Aa  
CA a  
C Aa  
A5  
A6  
A9  
A9  
W E  
D S F  
D Q M  
I / O  
M a s k  
I / O  
M a s k  
P i xe l  
M a s k  
C o l o r  
C o l o r  
D Ba0  
DBa3  
DBa1 D Ba2  
D Q  
L oad M as k  
R e gis t er  
Load C olor  
R e gis t er  
Load Color  
R egis ter  
Row Ac t i v e  
with W PB *  
Enable  
Mas k ed  
Bl oc k W r i te  
(A -B an k )  
Ro w A c t i ve  
wi th W PB*  
Enable  
Ma s ke d W r i t e  
with Au to  
(B -B an k )  
Pr ec h arg e  
( B- Ban k )  
Load M as k Regi st er  
( A-B an k )  
W PB * : W r i t e- P er- B i t  
:D on' t C ar e  
*Note : 1. At the next clock of special mode register set command, new command is possible.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 39/54  
M32L1632512A  
Page Read Cycle at Different Bank @ Burst Length = 4  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
4
5
6
7
8
C L O C K  
H I G H  
C K E  
* N o t e1 `  
C S  
R A S  
*N o t e 2 `  
C A S  
R Aa  
CAa R Bb  
C Ac  
CB d  
A D D R  
CBb  
CA e  
A10  
A9  
R Aa  
R Bb  
W E  
D SF  
LOW  
D Q M  
DQ C L= 2  
QAa2 QAa3 QBb0  
QAc 0 QAc 1 QBd0 QBd1 QAe0 QAe1  
QBb1 QBb2 QBb3  
QAa0  
QAa1  
QBb2  
QBb3 QAc0  
QAc 1 QBd0 QBd1 QAe0 QAe1  
C L =  
3
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1  
Read  
Read  
Read  
(B - Ban k )  
Read  
(A- Ban k )  
Pr echar ge  
( A- B an k )  
Row Ac t i ve  
( A- B an k )  
Ro w A c ti ve  
( B- Ban k )  
(A- Ban k )  
(B- Ban k )  
Read  
(A- Ban k )  
:D on' t C ar e  
*Note : 1. CS can be don’t care when RAS , CAS and WE are high at the clock high going edge.  
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 40/54  
M32L1632512A  
Page Write Cycle at Different Bank @ Burst Length =4  
1
2
3
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
0
6
8
4
5
7
C L O C K  
H I GH  
C K E  
C S  
R A S  
C A S  
RAa Key  
CA a RB b  
C Ac  
CBb  
CBd  
A D D R  
A10  
A9  
RAa  
RB b  
tC D L  
W E  
D SF  
DQ M  
DAa2 DAa3 DBb0  
DAc 0 D Ac 1  
DAc 3  
DBd0 DBd1 DBd2 D Bd3  
M as k  
DAa0  
DBb1 DBb2 D Bb3  
DAc 2  
DAa1  
D Q  
W ri t e  
( B- Bank )  
M as ked W r i t e  
wi th aut o  
W ri te w i th aut o  
Pr ech arge  
Row Ac t i v e  
( B- Ban k )  
Load M as k  
R egis t er  
pr echar ge  
( A- Ban k )  
( B- Bank )  
Mas ked W r i t e  
( A- Bank)  
Row Ac t i ve w i t h  
W r i t e- Per - Bi t  
enable  
: Don't C ar e  
(A- Bank)  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 41/54  
M32L1632512A  
Read & Write Cycle at Different Bank @ Burst Length =4  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
4
5
7
C L O C K  
C K E  
H IG H  
C S  
R A S  
C A S  
R A a  
C A a  
C B b R A c  
R B b  
C A c  
A D D R  
A10  
A9  
R A a  
R B b  
R A c  
tCD L  
* N ot e 1  
W E  
D S F  
D Q M  
D Q C L = 2  
QAc 1 QAc 2  
QAc 0 QAc 1  
D Bb0 D Bb1  
D Bb0 D Bb1  
D Bb3  
D Bb3  
QAa0 QAa1 QAa2 QAa3  
D Bb2  
D Bb2  
QA c 0  
QAa0 QAa1 QAa2 QAa3  
C L = 3  
P re c ha r ge  
( A- B an k )  
R ow A c t i v e  
(A - B an k )  
Rea d  
(A - Ba n k )  
R ea d  
( A - Ba n k )  
W r i t e  
( B - B an k )  
R o w A c t i v e  
( B- B an k )  
R o w A c t i v e  
( A - B an k )  
:D o n ' t C a r e  
*Note : 1. CDL should be met to complete write.  
t
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 42/54  
M32L1632512A  
Read & Write Cycle with Auto Precharge @ Burst Length =4  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
4
5
7
C L O C K  
C K E  
H IG H  
C S  
R A S  
C A S  
C a  
C b  
R a  
R b  
A D D R  
A10  
A9  
R a  
R b  
W E  
D S F  
D Q M  
D Q C L= 2  
Qa3  
Qa2  
Qa0  
Qa2  
Qa1  
Db3  
Db3  
Qa1  
Qa0  
Db0  
Db0  
Db2  
Db1  
Qa3  
CL = 3  
Db1 D b2  
Ro w A c t i v e  
( A -B an k )  
R ea d w it h  
Auto Pr ec h ar ge  
( A- Ban k )  
W r i te wi t h  
Auto Pr ec h ar ge  
( B- Bank )  
Auot Pr ec h ar ge  
Star t Poin t  
( A- Ban k )  
Au ot Pr ec harg e  
Star t Poin t  
( B- Ba nk )  
R o w A c t i v e  
(B - B an k )  
:D on ' t C ar e  
*Note : 1. RDL should be controlled to meet minimum RAS before internal precharge start.  
t
t
(In the case of Burst Length = 1 & 2, BRSW mode and Block write)  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 43/54  
M32L1632512A  
Read & Write Cycle with Auto Precharge II @ Burst Length =4  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
4
5
6
7
8
C L O C K  
C K E  
H I G H  
C S  
R A S  
C A S  
R a  
R b  
C a  
R a  
C a  
A D D R  
C b  
A10  
A9  
R a  
R b  
R a  
W E  
D SF  
D Q M  
DQ C L =2  
Da1  
Da1  
Qa0  
Qa1 Qb0 Qb1  
D b3  
Db2  
Db2  
Da0  
Da0  
Qa0  
Qa1 Qb0 Qb1  
D b3  
W r ite wi th  
Auot Pr echarge  
( A- Bank )  
Row Ac t i ve  
(A -Ban k )  
Rea d wit h  
Auto Pr ec harg e  
( A- Bank )  
Prec harge  
( B- Ban k )  
Row A c t i v e  
(A- Ban k )  
Row A c t i v e  
(B- Ban k )  
Read without Auto  
Pr ec har ge(B -Ban k )  
Au toPreaharge  
Star t Poin t  
( A- Bank )  
:D on' t C ar e  
*Note : 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.  
- If Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank  
auto precharge will start at the next cycle of B Bank read command input point.  
- any command can not be issued at A Bank during RP after A Bank auto precharge starts.  
t
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 44/54  
M32L1632512A  
Read & Write Cycle with Auto Precharge @ Burst Length =4  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
4
5
7
C L O C K  
C K E  
H IG H  
C S  
R A S  
C A S  
R a  
C a  
R b  
C b  
A D D R  
A10  
A9  
R a  
R b  
W E  
D S F  
tR C D  
D Q M  
D Q C L = 2  
Qa3  
Qa2  
Qa0  
Qa2  
Qa1  
D b3  
D b2  
Qa1  
Qa0  
D b0  
D b2  
Db1  
D b1  
D b0  
Qa3  
Db3  
C L = 3  
* N ot e  
1
Rea d w it h  
Au to Pr ec h ar g e  
( B- Ba nk )  
Au ot P r ec h ar g e  
Star t Poin t  
( B- Ba nk )  
R ow A c t i v e  
(A - B an k )  
R ead w it h  
Au to Pr ec h arg e  
( A - Ba nk )  
Au ot Pr ec h ar g e  
Star t Poin t  
( A- Ba nk )  
Ro w A c ti ve  
( B- Ba nk )  
:D o n ' t C a r e  
*Note : 1. Any command to A Bank is not allowed in this period.  
RP is determined from at auto precharge start point.  
t
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 45/54  
M32L1632512A  
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@ Full Page Only)  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
4
5
6
7
8
C L O C K  
C K E  
H I GH  
C S  
R A S  
C A S  
RAa  
CA a  
CAb  
A D D R  
A10  
A9  
*N o t e  
1
* N o t e 1  
RAa  
W E  
D SF  
D Q M  
*N o t e  
2
1
1
DQ C L=2  
QAa3  
QAa4  
QAa2  
QAa1  
DAb4 DAb5  
D Ab0 DAb1 DAb2 D Ab3  
QAa0  
2
2
QAa3 QAa4  
DAb2 DAb3  
DAb4 D Ab5  
C L= 3  
QAa0 QAa1 QAa2  
D Ab0 DAb1  
R ow A c t i v e  
( A-B an k )  
Read  
(A- Ban k )  
Read  
(A- Ban k )  
Prec harg e  
( A- Ban k )  
Burst Stop  
: D on' t C ar e  
*Note : 1. At full page mode, burst is warp-around at the end of burst. So auto precharge is impossible.  
2. About the valid DQ’s after burst stop, it is same as the case of RAS interrupt.  
Both cases are illustrated above timing diagram. See the label 1, 2 on them.  
But at burst write, Burst stop and RAS interrupt should be compared carefully.  
Refer the timing diagram of “Full page write burst stop cycle”.  
3. Burst stop is valid at full page mode.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 46/54  
M32L1632512A  
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full Page Only)  
12  
11  
13  
14  
15  
1
2
3
4
7
8
9
10  
16  
17  
18  
19  
5
6
0
C L O C K  
H I G H  
C K E  
C S  
R A S  
C A S  
RA a  
C A b  
A D D R  
C A a  
A10  
A9  
*N o t e 1  
*N o t e 1  
RA a  
tR D L  
tB D L  
W E  
D SF  
D Q M  
* N o t e 3  
* N o t e 2  
D Aa2 D Aa3 DAa4  
D Ab0 DAb1 D Ab2  
D Aa0 D Aa1  
DAb3 DAb4 D Ab5  
D Q  
W r i te  
(A - Ba n k )  
W r i t e  
(A - Ba n k )  
Bu rs t Sto p  
Pr ec ha rg e  
( A- B an k )  
R ow Ac t i ve  
( A- B an k )  
: D o n' t C a r e  
*Note : 1. At full page mode, burst is warp-around at the end of burst. So auto precharge is impossible.  
2. Data-in at the cycle of burst stop command cannot be written into the corresponding memory cell.  
It is defined by AC parameter of BDL (=1CLK).  
t
3. Data-in at the cycle interrupted by precharge cannot be written into the corresponding memory cell.  
It is defined by AC parameter of RDL (=1CLK).  
t
DQM at write interrupted by precharge command is needed to ensure RDL of 1CLK.  
t
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.  
Input data after Row precharge cycle will be masked internally.  
4. Burst stop is valid only at full page burst length.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 47/54  
M32L1632512A  
Burst Read Single bit Write Cycle @ Burst Length = 2, BRSW  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
4
5
7
C L O C K  
C K E  
* N o t e  
1
H I G H  
C S  
R A S  
* N o t e  
2
C A S  
C Bc  
RA a  
C Aa R Bb CA b  
RA b  
C A d  
A D D R  
A10  
A9  
R A c  
RA a  
R Bb  
W E  
D SF  
D Q M  
D Ad1  
DAd0  
QAa0  
QAa0  
DAb0 D Ab1  
D Bc 0  
D Bc 0  
D Ad0  
DAd1  
CL = 3  
D Ab0 DAb1  
Row A c t i ve  
(A -B an k )  
R ead  
(A - Ban k )  
Ro w Ac t i v e  
( B- B an k )  
Ro w Ac t i v e  
( A- B an k )  
Pre ch arg e  
( A- B an k )  
W ri t e  
(A - Ban k )  
W ri t e wi t h  
Read w ith  
Auto Pr ec harge  
( B- Bank )  
Auto Pr ec harge  
( A- Bank )  
: D on' t C ar e  
*Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).  
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.  
2. When BRSW write command with auto precharge is executed, keep it in mind that RAS should not be violated.  
t
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command.  
The next cycle is also starts the precharge.  
3. WPB function is also possible at BRSW mode.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 48/54  
M32L1632512A  
Clock suspension & DQM operation cycle @ CAS Latency = 2, Burst Length = 4  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
4
5
7
C L O C K  
C K E  
C S  
R A S  
C A S  
R a  
C a  
C b  
C c  
A D D R  
A10  
A9  
R A  
W E  
D S F  
D Q M  
D Q  
* N o t e 1  
Qb0  
Qb1  
Dc 0  
Qa0  
Qa1  
Qa2  
Qa3  
D c 2  
tS H Z  
tS H Z  
R ow Ac t i v e  
C l oc k  
Sus pen s ion  
W r i te  
D Q M  
R ea d  
R ead  
R ea d D Q M  
C l oc k  
W r i te  
Sus pens ion  
:Do n' t C ar e  
*Note : 1. DQM needed to prevent bus contention.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 49/54  
M32L1632512A  
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length =4  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
4
5
7
C L O C K  
C K E  
* N o t e  
2
S S  
1
t
S S  
t
tS S  
tS S  
* N o t e  
* N o t e  
3
C S  
R A S  
C A S  
C a  
R a  
A D D R  
A10  
A9  
R a  
W E  
D S F  
D Q M  
D Q  
Qa0  
Qa1 Qa2  
Pr ec h ar ge  
Pr ech ar ge  
Pr e ch ar ge  
R ead  
Pow er - dow n  
E xi t  
Po w er - dow n  
Entr y  
R o w A c t i v e  
A c ti ve  
A c tive  
P ow er - dow n  
Entr y  
Pow er - do w n  
E xi t  
:Do n' t C ar e  
*Note : 1. All banks should be in idle state prior to entering precharge power down mode.  
2. CKE should be set high at lease “1CLK + SS” prior to Row active command.  
t
3. Cannot violate minimum refresh specification. (32ms)  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 50/54  
M32L1632512A  
Self Refresh Entry & Exit Cycle  
11  
12  
13  
15  
17  
19  
1
2
3
9
10  
14  
16  
18  
0
6
8
4
5
7
C L O C K  
C K E  
* N o t e  
2
* N o t e  
4
tR C m i n  
* N o t e  
6
S S  
t
*N o t e  
3
* N o t e  
1
tS S  
* N o t e  
5
C S  
R A S  
* N o t e  
7
* N o t e  
7
C A S  
A D D R  
A10  
A9  
W E  
D S F  
D Q M  
D Q  
H i - Z  
H i - Z  
Auto R ef res h  
Sel f Refr es h En tr y  
Se lf R ef res h E xi t  
: D o n' t C ar e  
*Note : TO ENTER SELF REFRESH MODE  
1. CS , RAS & CAS with CKE should be low at the same clock cycle.  
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.  
3.The device remains in self refresh mode as long as CKE stays “Low”.  
cf.) Once the device enters self refresh mode minimum RAS is required before exit from self refresh.  
t
TO EXIT SELF REFRESH MODE  
4.System clock restart and be stable before returning CKE high.  
5. CS starts from high.  
6.Minimum RC is required after CKE going high to complete self refresh exit.  
t
7.2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit  
if the system uses burst refresh.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 51/54  
M32L1632512A  
Mode Register Set Cycle  
Auto Refresh Cycle  
1
2
3
8
9
10  
6
1
2
3
0
4
5
7
0
6
4
5
C L O C K  
C K E  
H I G H  
H I G H  
C S  
* N o t e  
2
tR C  
R A S  
* N o t e  
1
C A S  
* N o t e  
3
Key  
A D D R  
R a  
W E  
D SF  
D Q M  
H i - Z  
H i - Z  
D Q  
N ew  
C om m an d  
M R S  
Ne w C om m an d  
Auto R ef res h  
: D o n' t C ar e  
*Both bank precharge should be completed Mode Register Set cycle and auto refresh cycle.  
MODE REGISTER SET CYCLE  
*Note : 1. CS , RAS , CAS & WE activation and DSF of low at the same clock cycle with address key will set internal mode  
register.  
2. Minimum 1 clock cycles should be met before new RAS activation.  
3. Please refer to Mode Register Set table.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 52/54  
M32L1632512A  
PACKING DIMENSIONS  
100-LEAD QFP(14 x 20 mm)  
SEE DETAIL "A"  
D
D1  
80  
51  
50  
81  
E
E1  
θ
L
PIN 1  
L1  
DETAIL "A"  
100  
31  
1
30  
A1  
A2  
A
c
SEATING PLANE  
e
b
Symbol  
Dimension in mm  
Min Norm Max  
Dimension in inch  
Min Norm Max  
0.134  
A
A1  
A2  
b
3.400  
0.250  
2.650  
0.220  
0.110  
0.010  
2.970 0.104  
0.380 0.0087  
0.230 0.0043  
0.117  
0.015  
0.009  
c
D
D1  
E
E1  
L
23.000 23.200 23.400 0.906 0.913 0.921  
19.900 20.000 20.100 0.783 0.787 0.791  
17.000 17.200 17.400 0.669 0.677 0.685  
13.900 14.000 14.100 0.547 0.551 0.555  
0.650 0.800 0.950 0.026 0.031 0.037  
L1  
e
1.600 REF  
0.650 REF  
0.063 REF  
0.026 REF  
θ
0°  
0°  
7°  
7°  
y
0.080  
0.003  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 53/54  
M32L1632512A  
Important Notice  
All rights reserved.  
No part of this document may be reproduced or duplicated in any form or by any  
means without the prior permission of ESMT.  
The contents contained in this document are believed to be accurate at the time of  
publication. ESMT assumes no responsibility for any error in this document, and  
reserves the right to change the products or specification in this document without  
notice.  
The information contained herein is presented only as a guide or examples for the  
application of our products. No responsibility is assumed by ESMT for any  
infringement of patents, copyrights, or other intellectual property rights of third  
parties which may result from its use. No license, either express , implied or  
otherwise, is granted under any patents, copyrights or other intellectual property  
rights of ESMT or others.  
Any semiconductor devices may have inherently a certain rate of failure. To  
minimize risks associated with customer's application, adequate design and  
operating safeguards against injury, damage, or loss from such failure, should be  
provided by the customer when making application designs.  
ESMT's products are not authorized for use in critical applications such as, but not  
limited to, life support devices or system, where failure or abnormal operation may  
directly affect human lives or cause physical injury or property damage. If products  
described here are to be used for such kinds of application, purchaser must do its  
own quality assurance testing appropriate to such applications.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 54/54  

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