M52D5121632A-7BG [ESMT]
8M x 16 Bit x 4 Banks Mobile Synchronous DRAM;
| 型号： | M52D5121632A-7BG |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | 8M x 16 Bit x 4 Banks Mobile Synchronous DRAM 动态存储器 |
| 文件： | 总46页 (文件大小：1185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
M52D5121632A
8M x 16 Bit x 4 Banks
Mobile Synchronous DRAM
Mobile SDRAM
ORDERING INFORMATION
FEATURES
ó
ó
ó
ó
1.8V power supply
LVCMOS compatible with multiplexed address
Four banks operation
Product ID
Max Freq.
Package
Comments
Pb-free
M52D5121632A-5BG
M52D5121632A-6BG
M52D5121632A-7BG
200MHz 54 Ball FBGA
166MHz 54 Ball FBGA
143MHz 54 Ball FBGA
MRS cycle with address key programs
Pb-free
-
CAS Latency (2, 3)
Pb-free
-
-
Burst Length (1, 2, 4, 8 & full page)
Burst Type (Sequential & Interleave)
ó
ó
EMRS cycle with address
All inputs are sampled at the positive going edge of the
system clock
ó
Special function support
-
PASR (Partial Array Self Refresh)
TCSR (Temperature Compensated Self Refresh)
DS (Driver Strength)
-
-
-
Deep Power Down (DPD) Mode
ó
ó
ó
DQM for masking
Auto & self refresh
64ms refresh period (8K cycle)
GENERAL DESCRIPTION
The M52D5121632A is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
BALL CONFIGURATION (TOP VIEW)
(BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)
1
2
3
4
5
6
7
8
9
VDDQ
DQ15
VSSQ
DQ0
VDD
A
B
C
D
E
F
VSS
VSSQ
VDDQ
DQ2
DQ4
DQ1
DQ3
DQ14
DQ12
DQ13
DQ11
VDDQ
VSSQ
VSSQ
VDD
VDDQ
VSS
DQ6
DQ10
DQ8
DQ9
NC
DQ5
DQ7
LDQM
UDQM
A12
CLK
A11
CKE
A9
CAS
BA0
RAS
BA1
WE
CS
G
H
J
A10
A8
A7
A5
A6
A4
A0
A3
A1
A2
VSS
VDD
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 1/46
ESMT
M52D5121632A
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Clock
Generator
Bank D
Bank C
Bank B
Row
Address
Address
Buffer
&
Mode
Bank A
Register
Refresh
Counter
Sense Amplifier
Column Decoder
L(U)DQM
Column
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
DQ
Data Control Circuit
BALL FUNCTION DESCRIPTION
PIN
NAME
System Clock
INPUT FUNCTION
CLK
CS
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~ RA12, column address : CA0~CA9
A0 ~ A12
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
BA0 , BA1
Bank Select Address
Latches row addresses on the positive going edge of the CLK with
RAS low.
Row Address Strobe
RAS
CAS
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
Column Address Strobe
CAS low.
Enables column access.
Enables write operation and row precharge.
Write Enable
WE
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
L(U)DQM
Data Input / Output Mask
DQ0 ~ DQ15
VDD / VSS
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power Supply / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ / VSSQ
NC
Data Output Power / Ground
No Connection
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1
2/46
ESMT
M52D5121632A
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
-1.0 ~ 2.6
-1.0 ~ 2.6
0 ~ +70
UNIT
V
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Operation ambient temperature
Storage temperature
V
IN, VOUT
V
DD, VDDQ
V
°C
TA
°C
W
TSTG
-55 ~ +150
Power dissipation
P
D
1
Short circuit current
I
OS
50
mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V)
PARAMETER
Supply voltage
SYMBOL
MIN
1.7
TYP
1.8
1.8
0
MAX
1.95
VDDQ+0.3
0.3
UNIT
NOTE
V
DD, VDDQ
IH
V
V
V
V
V
1
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
V
0.8 x VDDQ
-0.3
2
V
IL
3
V
OH
V
DDQ-0.2
-
-
-
I
OH = -0.1mA
V
OL
IL
-
0.2
I
OL = 0.1mA
4
I
µ
A
-2
-
2
Note: 1. under all conditions, VDDQ must be less than or equal to VDD
.
2. VIH (max) = 2.2V. The overshoot voltage duration is
3. VIL (min) = -1.0V. The undershoot voltage duration is
≤
≤
3ns.
3ns.
4. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
CAPACITANCE (VDD = 1.8V, TA = 25 °C , f = 1MHz)
PARAMETER
Input capacitance (A0 ~ A12, BA0 ~ BA1)
Input capacitance
SYMBOL
MIN
MAX
UNIT
C
IN1
2
5
pF
C
IN2
pF
pF
2
2
7
7
(CLK, CKE, CS , RAS , CAS , WE &
L(U)DQM)
Data input/output capacitance (DQ0 ~ DQ15)
C
OUT
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 3/46
ESMT
M52D5121632A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted
Version
Parameter
Symbol
Test Condition
Unit Note
-5
-6
-7
Burst Length = 1
Operating Current
(One Bank Active)
I
CC1
65
60
55
mA
1
t
RC
≥
t
RC (min), tCC
≥
t
CC (min), IOL= 0mA
Precharge Standby
Current in power-down
mode
I
I
CC2P
CKE
CKE
≤
V
V
IL(max), tCC =15ns
1.2
1.2
mA
mA
CC2PS
≤
IL(max), CLK
≤
V
IL(max), tCC
= ∞
CKE
≥
V
IH(min), CS
≥
V
IH(min), tCC =10ns
5
3
mA
mA
mA
I
CC2N
Precharge Standby
Current in non
power-down mode
Input signals are changed one time during 20ns
CKE IH(min), CLK
Input signals are stable
≥
V
≤ VIL(max), tCC = ∞
I
I
I
CC2NS
CC3P
CKE
CKE
CKE
≤
V
IL(max), tCC =15ns
IL(max), CLK
IH(min), CS
5
5
Active Standby Current
in power-down mode
CC3PS
≤
V
≤
V
IL(max), tCC
= ∞
≥
V
≥ VIH(min), tCC=15ns
Active Standby Current
in non power-down
mode
Input signals are changed one time during 2clks
All other pins VDD-0.2V or 0.2V
CKE IH (min), CLK
Input signals are stable
OL= 0mA, Page Burst
All Bank Activated, tCCD = tCCD (min)
I
I
CC3N
10
7
mA
≥
≤
(One Bank Active)
≥
V
≤ VIL(max), tCC= ∞
mA
mA
CC3NS
I
Operating Current
(Burst Mode)
65
85
55
75
50
70
1
2
I
I
CC4
CC5
Refresh Current
tRFC
≥
tRFC(min)
mA
°C
45
85
TCSR range
Full array
1/2 array
1.4
1.3
1.2
1.1
1
1.5
1.4
1.3
1.2
1.1
Self Refresh Current
I
CC6
CKE
≤
0.2V
mA
uA
1/4 array
1/8 array
1/16 array
Deep Power Down
Current
10
I
CC7
CKE
≤
0.2V
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 64ms. Addresses are changed only one time during tCC(min).
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 4/46
ESMT
M52D5121632A
AC OPERATING TEST CONDITIONS (VDD= 1.7V~1.95V)
Parameter
Input levels (Vih/Vil)
Value
0.9 x VDDQ / 0.2
0.5 x VDDQ
tr / tf = 1 / 1
0.5 x VDDQ
See Fig.2
Unit
V
Input timing measurement reference level
Input rise and fall time
V
ns
V
Output timing measurement reference level
Output load condition
1.8V
Vtt =0.5x VDDQ
13.9K
50
Output
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
Output
Z0=50
10.6K
20 pF
20 pF
(Fig.2) AC Output Load Circuit
(Fig.1) DC Output Load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-5
10
15
-6
12
18
-7
14
21
Row active to row active delay
t
RRD(min)
RCD(min)
ns
ns
1
1
t
RAS to CAS delay
Row precharge time
t
RP(min)
15
40
18
42
100
60
96
1
21
42
ns
ns
1
1
t
RAS(min)
Row active time
t
RAS(max)
RC(min)
us
-
@ Operating
@ Auto refresh
t
55
96
63
96
ns
1
Row cycle time
t
RFC(min)
CDL(min)
RDL(min)
ns
1 , 5
2
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
t
t
CLK
CLK
CLK
CLK
3
2
t
BDL(min)
1
2
Col. Address to col. Address delay
t
CCD(min)
1
3
Mode Register command to Active or Refresh
Command
t
MRD(min)
2
CLK
ms
-
Refresh period(8,192 rows)
t
REF(max)
64
2
6
CAS Latency = 3
CAS Latency = 2
Number of valid output data
ea
4
1
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
5. A new command may be given tRFC after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8x7.8μs.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 5/46
ESMT
M52D5121632A
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-5
-6
-7
Parameter
Symbol
Unit Note
Min
5
Max
Min
6
Max
Min
7
Max
CAS Latency = 3
CAS Latency = 2
CAS Latency = 3
CLK cycle time
t
CC
1000
1000
1000
ns
ns
1
1
9
9
9
4.5
8
5
8
6
8
CLK to valid output delay
t
SAC
CAS Latency = 2
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
t
OH
CH
2
2
2.6
2.5
2.5
1.5
1
2.6
2.5
2.5
1.5
1
ns
ns
ns
ns
ns
ns
2
3
3
3
3
2
t
t
CL
SS
2
t
1.5
1
Input hold time
t
SH
CLK to output in Low-Z
t
SLZ
1
1
1
CAS Latency = 3
CAS Latency = 2
4.5
8
5
8
6
8
CLK to output in Hi-Z
t
SHZ
ns
*All AC parameters are measured from half to half.
Note: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to
the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 6/46
ESMT
M52D5121632A
SIMPLIFIED TRUTH TABLE
A12~A11,
A9~A0
BA0
BA1
COMMAND
CKEn-1 CKEn
DQM
X
Note
CS RAS CAS WE
A10/AP
Mode Register set
Register
H
H
X
L
L
L
L
L
L
L
OP CODE
X
1,2
Extended Mode Register
set
Auto Refresh
H
L
3
3
3
3
H
X
Entry
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
X
X
X
Refresh
Exit
L
H
X
X
Bank Active & Row Addr.
H
V
V
Row Address
Column
Address
(A0~A9)
Column
Address
(A0~A9)
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4,5
4
Read &
H
H
X
X
L
L
H
H
L
L
H
L
X
X
Column Address
Write &
V
Column Address
H
4,5
6
Burst Stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank Selection
All Banks
V
X
L
X
H
H
L
X
H
X
X
H
X
X
H
X
Entry
H
L
X
Clock Suspend or
X
X
Active Power Down Mode
Exit
L
H
L
X
X
X
H
L
X
H
X
H
X
X
H
X
H
X
H
X
H
X
H
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
H
L
L
X
H
H
X
H
L
No Operating Command
Entry
Exit
H
L
L
H
X
X
X
Deep Power Down Mode
X
H
X
X
X
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)
Note:
1.OP Code: Operating Code
A0~A12 & BA0~BA1: Program keys. (@ MRS). BA1=0 for MRS and BA1=1 for EMRS
2.MRS/EMRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS/EMRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 7/46
ESMT
M52D5121632A
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address BA0 BA1
Function
A12~A10/AP
RFU
A9
A8~A7
TM
A6
A5
A4
A3
BT
A2
A1
A0
0
0
W.B.L
CAS Latency
Burst Length
Test Mode
Type
CAS Latency
Burst Type
Burst Length
A8
0
A7
A6
A5
0
A4
0
Latency
Reserved
Reserved
2
A3
Type
A2
0
A1
0
A0
0
BT = 0
BT = 1
0
1
0
1
Mode Register Set
Reserved
0
0
0
0
1
1
1
1
0
1
Sequential
Interleave
1
2
4
8
1
2
4
8
0
0
1
0
0
1
1
Reserved
1
0
0
1
0
1
Reserved
1
1
3
0
1
1
Write Burst Length
Length
0
0
Reserved
Reserved
Reserved
Reserved
1
0
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
A9
0
0
1
1
0
1
Burst
1
0
1
1
0
1
Single Bit
1
1
1
1
1
Full Page Length: 1024
Note:
1. RFU (Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (1024 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 8/46
ESMT
M52D5121632A
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register stores for selecting PASR; DS. The extended mode register set must be done before any active
command after the power up sequence. The extended mode register is written by asserting low on CS ,RAS , CAS , WE and
high on BA1,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended
more register). The state of address pins
A0~An in the same cycle as CS ,RAS , CAS , WE going low is written in the extended mode register. Refer to the table for
specific codes.
The extended mode register can be changed by using the same command and clock cycle requirements during operations as
long as all banks are in the idle state.
Internal Temperature Compensated Self Refresh (TCSR)
Note:
1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the device temperature.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
BA1 BA0
0*
A12 ~ A8
0*
A7 A6 A5 A4 A3
DS TCSR
A2
A1
PASR
A0 Address bus
Extended Mode Register Set
1
A2-A0
000
Self Refresh Coverage
Full array
001
1/2 array (BA1=0)
1/4 array
010
(BA0=BA1=0)
011
100
Reserved
PASR
Reserved
1/8 array
101
(BA1=BA0= Row Addr MSB** = 0)
1/16 array
110
111
(BA1=BA0= Row Addr 2 MSB = 0)
Reserved
Internal TCSR
A7-A5
Driver Strength
Full Strength
1/2 Strength
1/4 Strength
1/8 Strength
3/4 Strength
000
001
010
011
100
DS
Note: * BA0 and A12~ A8 should stay “0” during EMRS cycle
** MSB: most significant bit
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1
9/46
ESMT
M52D5121632A
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
0
1
0
3
2
5
4
7
6
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
6
5
4
3
2
1
0
7
0
1
2
3
4
5
1
2
3
4
5
6
7
3
0
1
6
7
4
5
7
4
5
2
3
0
1
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 10/46
ESMT
M52D5121632A
DEVICE OPERATIONS
CLOCK (CLK)
MODE REGISTER SET (MRS)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of setup and hold time around positive edge
of the clock for proper functionality and ICC specifications.
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and
various vendor specific options to make SDRAM useful
for variety of different applications. The default value of
the mode register is not defined, therefore the mode
register must be written after power up to operate the
SDRAM. The mode register is written by asserting low
on CS , RAS , CAS and WE (The SDRAM should
be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0~A12
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down mode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at
least “1CLK + tSS” before the high going edge of the clock,
then the SDRAM becomes active from the same clock edge
accepting all the input commands.
and BA0~BA1 in the same cycle as CS , RAS , CAS
and WE going low is the data written in the mode
register. Two clock cycles is required to complete the
write in the mode register. The mode register contents
can be changed using the same command and clock
cycle requirements during operation as long as all banks
are in the idle state. The mode register is divided into
various fields into depending on functionality. The burst
length field uses A0~A2, burst type uses A3, CAS
latency (read latency from column address) use A4~A6,
vendor specific options or test mode use A7~A8,
A10~A12 and BA1~BA0. The write burst length is
programmed using A9. A7~A8, A10/AP~A12 and
BA0~BA1 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for
various burst length, burst type and CAS latencies.
BANK ADDRESSES (BA0~BA1)
This SDRAM is organized as four independent banks of
8,388,608 words x 16 bits memory arrays. The BA0~BA1
inputs are latched at the time of assertion of RAS and
CAS to select the bank to be used for the operation. The
banks addressed BA0~BA1 are latched at bank active, read,
write, mode register set and precharge operations.
ADDRESS INPUTS (A0~A12)
The 23 address bits are required to decode the 8,388,608
word locations are multiplexed into 13 address input pins
(A0~A12). The 13 row addresses are latched along with
RAS and BA0~BA1 during bank active command. The 10
bit column addresses are latched along with CAS , WE
and BA0~BA1 during read or with command.
NOP and DEVICE DESELECT
When RAS , CAS and WE are high, The SDRAM
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock cycle like bank activate, burst
read, auto refresh, etc. The device deselect is also a NOP
and is entered by asserting CS high. CS high disables
the command decoder so that RAS , CAS , WE and all
the address inputs are ignored.
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DEVICE OPERATIONS (Continued)
BANK ACTIVATE
and WE with valid column address, a write burst is
initiated. The data inputs are provided for the initial
address in the same clock cycle as the burst write
command. The input buffer is deselected at the end of
the burst length, even though the internal writing can be
completed yet. The writing can be complete by issuing a
burst read and DQM for blocking data inputs or burst
write in the same or another active bank. The burst stop
command is valid at every burst length. The write burst
can also be terminated by using DQM for blocking data
and procreating the bank tRDL after the last data input to
be written into the active row. See DQM OPERATION
also.
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and CS with
desired row and bank address, a row access is initiated. The
read or write operation can occur after a time delay of tRCD
(min) from the time of bank activation. tRCD is the internal
timing parameter of SDRAM, therefore it is dependent on
operating clock frequency. The minimum number of clock
cycles required between bank activate and read or write
command should be calculated by dividing tRCD (min) with
cycle time of the clock and then rounding of the result to the
next higher integer. The SDRAM has four internal banks in
the same chip and shares part of the internal circuitry to
reduce chip area, therefore it restricts the activation of four
banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high requiring some time
for power supplies to recover before another bank can be
sensed reliably. tRRD (min) specifies the minimum time
required between activating different bank. The number of
clock cycles required between different bank activation must
be calculated similar to tRCD specification. The minimum time
required for the bank to be active to initiate sensing and
restoring the complete row of dynamic cells is determined by
DQM OPERATION
The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits
writing during write operation. The read latency is two
cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in read cycle and
occurs in the same cycle during write cycle. DQM
operation is synchronous with the clock. The DQM
signal is important during burst interrupts of write with
read or precharge in the SDRAM. Due to asynchronous
nature of the internal write, the DQM operation is critical
to avoid unwanted or incomplete writes when the
complete burst write is required. Please refer to DQM
timing diagram also.
t
RAS (min). Every SDRAM bank activate command must
satisfy tRAS (min) specification before a precharge command
to that active bank can be asserted. The maximum time any
bank can be in the active state is determined by tRAS (max)
and tRAS (max) can be calculated similar to tRCD specification.
BURST READ
PRECHARGE
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank
CS and RAS with WE being high on the positive edge
of the clock. The bank must be active for at least tRCD (min)
before the burst read command is issued. The first output
appears in CAS latency number of clock cycles after the
issue of burst read command. The burst length, burst
sequence and latency from the burst read command is
determined by the mode register which is already
programmed. The burst read can be initiated on any column
address of the active row. The address wraps around if the
initial address does not start from a boundary such that
number of outputs from each I/O are equal to the burst
length programmed in the mode register. The output goes
into high-impedance at the end of burst, unless a new burst
read was initiated to keep the data output gapless. The burst
read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
activate and CS , RAS , WE and A10/AP with valid
BA0~BA1 of the bank to be precharged. The precharge
command can be asserted anytime after tRAS (min) is
satisfied from the bank active command in the desired
bank. tRP is defined as the minimum number of clock
cycles required to complete row precharge is calculated
by dividing tRP with clock cycle time and rounding up to
the next higher integer. Care should be taken to make
sure that burst write is completed or DQM is used to
inhibit writing before precharge command is asserted.
The maximum time any bank can be active is specified
by tRAS (max). Therefore, each bank activates command.
At the end of precharge, the bank enters the idle state
and is ready to be activated again. Entry to power-down,
Auto refresh, Self refresh and Mode register set etc. is
possible only when all banks are in idle state.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive
clock cycles in adjacent addresses depending on burst
length and burst sequence. By asserting low on CS , CAS
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DEVICE OPERATIONS (Continued)
AUTO PRECHARGE
SELF REFRESH
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy tRAS (min) and “tRP” for the programmed burst length
and CAS latency. The auto precharge command is issued at
the same time as burst write by asserting high on A10/AP,
the bank is precharge command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode
for data retention and low power operation of SDRAM.
In self refresh mode, the SDRAM disables the internal
clock and all the input buffers except CKE. The refresh
addressing and timing is internally generated to reduce
power consumption. The self refresh mode is entered
from all banks idle state by asserting low on CS ,
RAS , CAS and CKE with high on WE . Once the self
refresh mode is entered, only CKE state being low
matters, all the other inputs including clock are ignored
to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed
by NOP’s for a minimum time of tRFC before the SDRAM
reaches idle state to begin normal operation. 8K cycles
of burst auto refresh is required immediately before self
refresh entry and immediately after self refresh exit.
ALL BANKS PRECHARGE
All banks can be precharged at the same time by using
Precharge all command. Asserting low on CS ,RAS , and
WE with high on A10/AP after all banks have satisfied tRAS
(min) requirement, performs precharge on all banks. At the
end of tRP after performing precharge all, all banks are in idle
state.
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on CS , RAS and CAS with high on CKE
and WE . The auto refresh command can only be asserted
with all banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by tRFC (min). The minimum number of clock cycles
required can be calculated by driving tRFC with clock cycle
time and them rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 7.8us.
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COMMANDS
Mode register set command
(
CS
,
RAS
,
CAS
,
WE BA1, BA0 = Low)
,
The DRAM has a mode register that defines how the device operates. In this
command, A0 through BA0 are the data input pins. After power on, the mode register
set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state. During 2CLK (tMRD
)
following this command, the DRAM cannot accept any other commands.
Extended Mode register set command
( CS ,RAS , CAS , WE , BA0 = Low ; BA1= High)
The DRAM has an extended mode register that defines how to set PASR, DS.
Activate command
( CS ,RAS = Low, CAS , WE = High)
The DRAM has four banks, each with 8,192 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row address
selected by A0 through A12.
This command corresponds to a conventional DRAM’s RAS falling.
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Precharge command
( CS ,RAS , WE = Low, CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0 (BS).
When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10
is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the DRAM can’t accept the activate command to the precharging
bank during tRP (precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
Write command
( CS , CAS , WE = Low, RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first write
data in burst can be input with this command with subsequent data on following
clocks.
Read command
( CS , CAS = Low, RAS , WE = High)
Read data is available after CAS latency requirements have been met.
This command sets the burst start address given by the column address.
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CBR (auto) refresh command
( CS ,RAS , CAS = Low, WE , CKE = High)
This command is a request to begin the CBR refresh operation. The refresh address is
generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a row activate
command.
During tRFC period (from refresh command to refresh or activate command), the DRAM
cannot accept any other command.
Self refresh entry command
( CS ,RAS , CAS , CKE = Low , WE = High)
After the command execution, self refresh operation continues while CKE remains low.
When CKE goes to high, the DRAM exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed internally,
so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
( CS , WE = Low, RAS , CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
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No operation
( CS = Low,RAS , CAS , WE = High)
This command is not an execution command. No operations begin or terminate by this
command.
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BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1 ) C l o c k S u s p e n d e d D u r i n g W r i t e ( B L = 4 )
2 ) C l o c k S u s p e n d e d D u r i n g R e a d ( B L = 4 )
C L K
C M D
C K E
W R
R D
M a s ke d b y C K E
I n t e rn a l
C L K
D Q ( C L 3 )
D 2
D 3
D 0
D 1
Q3
Q0
Q1
Q2
N o t W r i t t e n
Suspe nd ed D ou t
2. DQM Operation
2 ) R e a d M a s k ( B L = 4 )
1 ) W r i t e M a s k ( B L = 4 )
C L K
C M D
W R
R D
D Q M
M a s k e d b y D Q M
M a s k e d b y D Q M
H i - Z
D Q ( C L 3 )
D 3
D 1
Q1
D 0
Q2
Q3
D Q M t o D a t a - i n Ma s k= 0
D Q M t o D a ta -o u t M a sk = 2
* N o t e 2
3 ) D Q M w i t h c l c o k s u s p e n d e d ( F u l l P a g e R e a d )
C L K
C M D
C K E
R D
I n te rn a l
C L K
D Q M
H i - Z
H i - Z
H i - Z
Q3
Q7
Q1
Q5
Q 8
Q 6
D Q ( C L 3 )
*Note: 1. CKE to CLK disable/enable = 1CLK.
2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.
3. DQM masks both data-in and data-out.
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3. CAS Interrupt (I)
* N o t e 1
1 ) R e a d i n t e r r u p t e d b y R e a d ( B L = 4 )
C L K
C M D
R D
A
R D
B
A D D
D Q ( C L 3 )
Q B 1
Q A 0 Q B 0
Q B 2 Q B 3
t
C C D
* N o t e
2
2 ) W r i t e i n t e r r u p t e d b y W r i t e ( B L = 2 )
3 ) W r i t e i n t e r r u p t e d b y R e a d ( B L = 2 )
C L K
C M D
W R
W R
R D
W R
t
C C D * N o t e 2
t
C C D * N o t e
2
A
A D D
D Q
B
A
B
D Q ( C L 3 )
D A 0 D B 0
D B 1
D A 0
D B 1
D B 0
t
C D L
t
C D L
* N o t e
3
* N o t e
3
*Note: 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access; read and write.
2. tCCD:CAS to CAS delay. (=1CLK)
3. tCDL: Last data in to new column address delay. (=1CLK)
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4. CAS Interrupt (II): Read Interrupted by Write & DQM
CL =3 , BL =4
C L K
i) CM D
RD
W R
D 0
D QM
D Q
D2
D 3
D 1
W R
i i) CM D
R D
D QM
D Q
D0
D3
D1
D 2
i ii) C MD
WR
R D
RD
RD
D QM
DQ
D0
D3
D 2
D 1
i v) CM D
W R
DQ M
D Q
H i- Z
D2
D 3
D 0
D 1
v) C M D
W R
D QM
D Q
Hi- Z
Q0
D 0
D 1
D2
D 3
* N o t e 1
*Note: 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
C L K
* N o t e 3
C M D
D Q M
W R
D 0
P R E
* N o t e 2
D Q
D 3
D 1
t
R D L ( m i n )
M a s k e d b y D Q M
*Note: 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of four banks operation.
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6. Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
C L K
C M D
D Q
C L K
C M D
P R E
P R E C L= 3
W R
D 0
R D
* N o t e 2
Q3
Q1
D 1
D 2
D 3
D Q ( C L 3 )
Q0
Q 2
t
R D L
* N o t e 1
.
7. Auto Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
C L K
C L K
C MD
C M D
D Q
W R
R D
D 0
D 2
D 1
D 3
D Q ( C L 3 )
D 3
D 0
D 2
D 1
t
R D L ( m i n )
* N o t e 3
* N o t e 3
A u to P r e ch a r ge s ta r ts
A u t o P re ch a rg e st a rt s
*Note: 1. tRDL: Last data in to row precharge delay.
2. Number of valid output data after row precharge: 2 for CAS Latency = 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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8. Burst Stop & Interrupted by Precharge
1 ) W r i t e B u r s t S t o p ( B L = 8 )
1 ) W r i t e i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C L K
* N o t e 3
* N o t e 4
C M D
W R
C M D
W R
D 0
P R E
S T O P
t
R D L
D Q M
D Q
D Q M
D Q
M a s k
M a s k
D 0
D 1
D 3
D 1
D 2
D 4
D 5
* N o t e 1
t
B D L
2 ) R e a d B u r s t S t o p ( B L = 4 )
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C L K
* N o t e 5
C M D
C M D
R D
P R E
Q1
R D
S TO P
* N o t e 2
D Q ( C L 3 )
Q 0
Q 1
D Q ( C L 3 )
Q3
Q 0
Q 2
9. MRS
1 )M o d e R e g is t e r S e t
C L K
*N o t e 6
C MD
AC T
PR E
M RS
t
RP
2 C L K
*Note: 1. tBDL: 1 CLK; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop: 2 for CAS latency = 3 respectiviely.
3. Write burst is terminated. tRDL determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM.
6. PRE: All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
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10. Clock Suspend Exit & Power Down Exit
1 ) C l o c k S u s p e n d ( = Ac t i v e P o w e r D o w n ) E x i t
2 ) P o w e r D o w n ( = P r e c h a r g e P o w e r D o w n )
CLK
CK E
CLK
CK E
t
S S
t
S S
Int ernal
CLK
Int ernal
C LK
* N o t e 1
* N o t e 2
C M D
R D
C M D
NO P
A C T
11. Auto Refresh & Self Refresh
* N o t e 3
1 ) A u t o Re f r e s h
&
S e lf R e f r e s h
C L K
* N o t e 4
* N o t e 5
CM D
PR E
CM D
AR
C KE
t
RP
t
R F C
* N o t e 6
2 ) S e l f Re f r e s h
C LK
CMD
* N o t e 4
SR
PR E
C M D
C KE
t
R P
t
R F C
*Note: 1. Active power down: one or more banks active state.
2. Precharge power down: all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refresh exit command, any other command can not be accepted.
8K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
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12. About Burst Type Control
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
Sequential Counting
Basic
MODE
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Interleave Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
Random
MODE
Random Column Access
t
CCD = 1 CLK
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
At MRS A210 = “000”
At auto precharge. tRAS should not be violated.
1
At MRS A210 = “001”
At auto precharge. tRAS should not be violated.
2
Basic
MODE
4
At MRS A210 = “010”
At MRS A210 = “011”
8
At MRS A210 = “111”
At the end of the burst length, burst is warp-around.
Full Page
t
BDL = 1, Valid DQ after burst stop is 2 for CAS latency 3 respectively.
Random
MODE
Burst Stop
Using burst stop command, any burst length control is possible.
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
RAS Interrupt
(Interrupted by
Precharge)
t
RDL = 3clk with DQM , Valid DQ after burst stop is 2 for CAS latency 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Interrupt
MODE
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
CAS Interrupt
During read/write burst with auto precharge, CAS interrupt can not be issued.
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FUNCTION TRUTH TABLE (TABLE 1)
Current
State
BA
ADDR
ACTION
Note
CS RAS CAS
WE
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
X
X
H
L
X
X
X
BA
BA
BA
X
X
X
X
NOP
NOP
ILLEGAL
2
2
IDLE
CA, A10/AP ILLEGAL
RA
A10/AP
Row (&Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
4
5
5
X
L
OP code
X
OP code
X
H
H
L
X
X
X
X
X
2
2
Row
Active
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
X
X
X
CA, A10/AP Begin Read ; latch CA ; determine AP
CA, A10/AP Begin Write ; latch CA ; determine AP
RA
A10/AP
L
H
H
L
X
H
H
L
ILLEGAL
Precharge
ILLEGAL
L
L
X
X
X
X
X
H
H
H
H
L
NOP (Continue Burst to End ‰ Row Active)
NOP (Continue Burst to End ‰ Row Active)
Term burst ‰ Row active
Read
Write
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
A10/AP
L
3
2
H
H
L
X
H
H
L
ILLEGAL
L
L
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End ‰ Row Active)
NOP (Continue Burst to End ‰ Row Active)
Term burst ‰ Row active
X
X
X
X
X
H
H
H
H
L
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
A10/AP
3
3
2
3
L
H
H
L
X
H
H
L
H
L
X
H
H
L
ILLEGAL
L
L
Term burst, Precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End ‰ Row Active)
NOP (Continue Burst to End ‰ Row Active)
ILLEGAL
X
X
X
X
X
H
H
H
L
Read with
Auto
Precharge
CA, A10/AP ILLEGAL
RA, RA10
ILLEGAL
ILLEGAL
2
2
L
X
X
X
X
X
H
H
H
L
NOP (Continue Burst to End ‰ Row Active)
NOP (Continue Burst to End ‰ Row Active)
ILLEGAL
Write with
Auto
Precharge
X
X
X
X
BA
BA
X
CA, A10/AP ILLEGAL
RA, RA10
X
H
L
ILLEGAL
ILLEGAL
L
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1
25/46
ESMT
M52D5121632A
Current
State
BA
ADDR
ACTION
Note
CS RAS CAS
WE
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
CA
RA
A10/AP
NOP ‰ Idle after tRP
NOP ‰ Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP ‰ Idle after tRP
ILLEGAL
NOP ‰ Row Active after tRCD
NOP ‰ Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP ‰ Idle after tRFC
NOP ‰ Idle after tRFC
ILLEGAL
ILLEGAL
ILLEGAL
Precharging
2
2
2
4
L
L
X
X
X
X
X
H
H
H
L
L
L
X
H
H
L
Row
Activating
2
2
2
2
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
Refreshing
L
X
H
H
H
L
NOP ‰ Idle after 2clocks
NOP ‰ Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
Mode
Register
Accessing
X
X
X
X
X
X
X
Abbreviations:
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note: 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 26/46
ESMT
M52D5121632A
FUNCTION TRUTH TABLE (TABLE2)
Current
State
CKE
( n-1 )
CKE
n
ADDR
ACTION
Note
CS RAS CAS WE
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh ‰ Idle after tRFC (ABI)
Exit Self Refresh ‰ Idle after tRFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh ‰ ABI
Exit Self Refresh ‰ ABI
ILLEGAL
6
6
Self
Refresh
L
X
X
H
L
L
L
All
Banks
Precharge
Power
7
7
ILLEGAL
ILLEGAL
Down
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
NOP (Maintain Low Power Mode)
Refer to Table1
Enter Power Down
Enter Power Down
ILLEGAL
8
8
X
X
X
RA
All
Banks
Idle
ILLEGAL
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
L
L
X
8
OP Code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any State
other than
Listed
H
H
L
H
L
H
L
9
9
above
L
Abbreviations: ABI = All Banks Idle, RA = Row Address
*Note: 6.CKE low to high transition is asynchronous.
7.CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + tSS must be satisfy before any command other than exit.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1
27/46
ESMT
M52D5121632A
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3, Burst Length = 1
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 28/46
ESMT
M52D5121632A
Note:
1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
BA1
BA0
Active & Read/Write
Bank A
0
0
1
1
0
1
0
1
Bank B
Bank C
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP
BA1
0
BA0
0
Operating
Disable auto precharge, leave A bank active at end of burst.
Disable auto precharge, leave B bank active at end of burst.
Disable auto precharge, leave C bank active at end of burst.
Disable auto precharge, leave D bank active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
Enable auto precharge, precharge bank C at end of burst.
Enable auto precharge, precharge bank D at end of burst.
0
1
0
1
0
1
1
0
0
0
1
1
1
0
1
1
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP
BA1
0
BA0
0
Precharge
Bank A
0
0
0
0
1
0
1
Bank B
1
0
Bank C
1
1
Bank D
X
X
All Banks
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 29/46
ESMT
M52D5121632A
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
10
11
12
C L O C K
C K E
H i g h l e v e l i s n e c e s s a r y
C S
t
R F C
t
R F C
t
R P
t
M R D
t
M R D
R A S
C A S
A D D R
K e y
K e y
R A
B A 1
B A 0
B S
B S
R A
A10/AP
H i g h - Z
D Q
W E
D Q M
H i g h l e v e l i s n e c e s s a r y
M o d e R e g i s t e r S e t
A u t o R e f r e s h
A u t o R e f r e s h
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
E x t e n d e d M o d e
R e g i s t e r S e t
:
D o n ' t c a r e
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
-
-
Apply VDD before or at the same time as VDDQ
Apply VDDQ
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1
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ESMT
M52D5121632A
Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
10
11
12
C L O C K
H I G H
C K E
* N o t e 1
t
R C
C S
t
R C D
R A S
C A S
* N o t e 2
C b
Ca
R b
R a
A D D R
B A 0
B A1
A10/AP
R a
R b
D Q
C L = 3
Q a 0 Qa 1 Q a 2 Q a 3
D b0 D b 1 D b 2 D b 3
* N o t e 3
t
R D L
W E
D Q M
Precharge
( A - Bank )
Read
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Row Active
A - Bank )
P r e ch a r g e
( A B a n k )
(
-
: D o n ' t C a r e
*Note:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 31/46
ESMT
M52D5121632A
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
H I G H
C K E
C S
tR C D
R A S
* N o t e 2
C A S
A D D R
C b
R a
C a
C c
C d
B A 0
B A1
A1 0/AP
R a
D Q
C L = 3
Qa 1
D c 1
Q a 0
Q b 0 Q b 1
D c 0
D d 0
D d 1
tC D L
W E
* N o t e 1
* N o t e 3
D Q M
Read
( A - Bank )
Read
( A - Bank )
Write
( A - Bank )
Write
( A - Bank )
Row Active
( A - Bank )
P r e c h a r g e
( A B a n k )
-
: D o n ' t C a r e
Note: 1. To Write data before burst read ends. DQM should be asserted three cycles prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input, tRDL before row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
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ESMT
M52D5121632A
Page Read Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
10
11
12
C L O C K
C K E
H I G H
* N o t e 1
C S
R A S
* N o t e 2
C A S
A D D R
B A 1
R A a
C A a
R C c
C C c
R D d
C D d
R B b
C B b
B A 0
A1 0/AP
RCc
RAa
RBb
RDd
D Q
C L = 3
QCc2
QCc1
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0
QDd0 QDd1 QDd2
W E
D Q M
P r e c h a r g e
( D - B a n k )
R e a d
( B - B a n k )
R e a d
( A - B a n k )
R e a d
( C - B a n k )
R e a d
( D - B a n k )
R o w A c t i v e
( A - B a n k )
R o w A c t i v e
( D - B a n k )
P r e c h a r g e
( C - B a n k )
R o w A c t i v e
( B - B a n k )
R o w A c t i v e
( C - B a n k )
P r e c h a r g e
( A - B a n k )
P r e c h a r g e
( B - B a n k )
: D o n ' t C a r e
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 33/46
ESMT
M52D5121632A
Page Write Cycle at Different Bank @ Burst Length = 4
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
11
12
10
C L O C K
C K E
H I G H
C S
R A S
* N o t e 2
C A S
A D D R
R A a
R B b C A a
R C c
C C c
C D d
C B b
R D d
B A 0
B A 1
R A a
R B b
R C c
R D d
A1 0/AP
D Q
DA a 0
D C c 1
D D d 1
DA a 1 D A a 2 D Aa 3 DB b 0 DB b 1
tC D L
D Bb 3 D C c 0
D D d 0
C D d 2
D Bb 2
tR D L
W E
* N o t e 1
D Q M
W r i t e
( D - B a n k )
R o w A c t i v e
( D - B a n k )
W r i t e
( A - B a n k )
W r i t e
( B - B a n k )
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
A - Bank )
(
R o w A c t i v e
( B - B a n k )
W r i t e
( C - B a n k )
R o w A c t i v e
( C - B a n k )
:
D o n ' t c a r e
*Note: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 34/46
ESMT
M52D5121632A
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
11
12
10
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
C B c
R A a
R D b
C D b R B c
C A a
B A 1
B A 0
A10/AP
R A a
R B b
R A c
* N o t e 1
t
C D L
D Q
C L = 3
Q Aa 3
Dd b 1
D D b 0
QAa0
Q Aa2
D D b 2 D D d 3
Q B c 0
QAa 1
Q Bc1
W E
D Q M
R e a d
( B - B a n k )
W r i t e
( D - B a n k )
Read
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note: 1. tCDL should be met to complete write.
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ESMT
M52D5121632A
Read & Write cycle with Auto Precharge @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
C S
H IG H
R A S
C A S
A D D R
R a
C a
R b
C b
B A 0
BA 1
A1 0/AP
R a
R b
D Q
C L = 3
Q Aa1 QAa2 QAa 3
QAa 0
D D b 0 Dd b 1 D D b 2 D D d 3
W E
D Q M
Read with
Auto Precharge
( A - Bank )
Write with
Auto Precharge
(D-Bank)
Row Active
A - Bank )
Auto Precharge
Start Point
(D-Bank)
(
Row Active
( D - Bank )
Auto Precharge
Start Point
: D o n ' t C a r e
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Publication Date: Jan. 2016
Revision: 1.1
36/46
ESMT
M52D5121632A
Clock Suspension & DQM Operation Cycle @ CAS Latency = 3, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
10
11
12
C L O C K
C K E
C S
R A S
C A S
A D D R
C a
R a
C c
C b
B A 1
BA 0
A 10/AP
D Q
R a
Q a 0
Q a 1
Q a 2 Q a3
Q b0
D c 0
D c 2
t
S H Z
t
S H Z
W E
* N o t e 1
D Q M
Cl ock
S upe nsi on
W r i t e
D Q M
Ro w A c t i ve
Read
R ead
W r i t e
D Q M
R ea d D QM
W r i t e
Cl ock
Susp en sion
: D o n ' t C a r e
*Note: 1. DQM is needed to prevent bus contention
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ESMT
M52D5121632A
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
10
11
12
C L O C K
H I G H
C K E
C S
R A S
C A S
A D D R
C A b
R A a
C A a
B A 1
B A 0
A10/AP
D Q
R A a
1
1
QAb4 QAb5
C L= 3
QAa1 QAa 2 QAa 3 QAa4
QAb0 QAb1
QAb2 QAb3
QAa0
W E
D Q M
R ea d
( A - B a n k )
B u rst S to p
R e a d
( A - B a n k )
P r ec h ar g e
( A - B an k )
R o w A c t i ve
( A - B a n k)
: D o n 't C a r e
*Note: 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
This case is illustrated above timing diagram. See the label 1
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
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ESMT
M52D5121632A
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
16
17
18
11
12
13
14
15
19
0
1
2
5
9
1 0
3
4
6
7
8
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
C A b
R A a
C A a
B A 0
BA 1
A 10/AP
D Q
R A a
t
R D L
t
B D L
* N o t e 1
D Ab0
D Aa0 DA a 1 DA a 2
DA b 2
D Ab 3 D Ab 4 DA b5
D A a 3 D Aa 4
D Ab 1
W E
D Q M
W r i t e
( A - B a n k )
B u rs t S t o p
R o w A c ti v e
( A - B a n k)
P r e c h a r ge
( A -B an k )
W r i t e
( A - B a n k )
: D o n ' t C a re
*Note: 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined
by AC parameter of tRDL
.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 39/46
ESMT
M52D5121632A
Active/Precharge Power Down Mode @ CAS Latency = 3, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
10
11
12
C L O C K
C K E
* N o t e 2
t
S S
t
S S
* N o t e 1
C S
R A S
C A S
A D D R
C a
R a
B A 1
B A 0
A 1 0 / A P
R a
t
S H Z
Q a 0 Q a 1 Q a 2
DQ
W E
D Q M
R e a d
P r e c h a r g e
P r e c h ar g e
Po we r- Do w n
E n t ry
R o w A c t i v e
P r e ch a r ge
Po w e r- Down
E xi t
A c t i v e
P o w e r - d o w n
E x i t
A c t i ve
P o we r - d o wn
E n t r y
:
D o n ' t c a r e
*Note: 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 40/46
ESMT
M52D5121632A
Deep Power Down Mode Entry & Exit Cycle
Note:
DEFINITION OF DEEP POWER MODE FOR Mobile SDRAM:
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory
of the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when
the device exits from Deep Power Down Mode.
TO ENTER DEEP POWER DOWN MODE
1) The deep power down mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of
the clock. While CKE is low.
2) Clock must be stable before exited deep power down mode.
3) Device must be in the all banks idle state prior to entering Deep Power Down mode.
TO EXIT DEEP POWER DOWN MODE
4) The deep power down mode is exited by asserting CKE high.
5) 200
μs wait time is required to exit from Deep Power Down.
6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands
and a load mode register sequence.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 41/46
ESMT
M52D5121632A
Self Refresh Entry & Exit Cycle
*Note: TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 8K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh
exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 42/46
ESMT
M52D5121632A
Mode Register Set Cycle
Extended Mode Register Set Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
C L O C K
C K E
C S
C L O C K
C K E
C S
H I G H
H I G H
* N o t e 2
* N o t e 2
R A S
R A S
* N o t e 1
* N o t e 3
* N o t e 1
* No t e 3
C A S
C A S
A D D R
A D D R
Ke y
Ra
K e y
Ra
B A 1
B A 0
B A 1
B A 0
BS
B S
B S
BS
A 1 0
A 1 0
DQ
H I - Z
H I -Z
D Q
W E
W E
DQ M
D Q M
N e w
C o mm a n d
N e w
Co m ma n d
M R S
E M RS
: Do n 't Ca r e
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal
mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 43/46
ESMT
M52D5121632A
PACKING
DIMENSIONS
54-BALL
SDRAM ( 8x8 mm )
Symbol
Dimension in mm
Dimension in inch
Min
Norm
Max
1.00
0.30
0.71
0.40
8.10
8.10
Min
Norm
Max
A
A1
A2
Φb
D
0.039
0.012
0.028
0.016
0.319
0.319
0.20
0.61
0.30
7.90
7.90
0.25
0.66
0.35
8.00
8.00
6.40
6.40
0.80
0.008
0.024
0.012
0.311
0.311
0.010
0.026
0.014
0.315
0.315
0.252
0.252
0.031
E
D1
E1
e
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1
44/46
ESMT
M52D5121632A
Revision History
Revision
Date
Description
0.1
0.2
2013.07.17
2014.11.14
Original
Modify the specification of tRDL
1. Modify the specification of Icc2p/Icc2ps, Icc2ns,
Icc3p/Icc3ps, Icc5, Icc6 and Icc7.
0.3
2015.03.10
2. Modify the specification of tRFC
1. Add –5 speed specification
2. Modify CAPACITANCE specification
Modify the specification of IDD2P, IDD2PS and IDD6
1.0
1.1
2015.07.06
2016.01.15
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 45/46
ESMT
M52D5121632A
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express ,
implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2016
Revision: 1.1 46/46
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