M54D1G1664A_技术文档

ESMT

M54D1G1664A

LPDDR2 SDRAM

8M x 16 Bit x 8 Banks

LPDDR2 SDRAM

Feature



JEDEC LPDDR2‐S4B compliance

HSUL_12 interface (High Speed Unterminated Logic 1.2V)

Power supply:

-

V_DD1= 1.7 to 1.95V

V_DD2, V_DDCA, V_DDQ= 1.14 to 1.3V



4n prefetch architecture

Multiplexed, double data rate, command/address inputs; commands entered on every CK edge

Bidirectional/differential data strobe per byte of data (DQS_t/DQS_c)

Programmable read latency (RL) and write latency (WL)

Programmable burst lengths (BL): 4, 8, 16

Pre-bank refresh for concurrent operation

Partial Array Self Refresh (PASR)

Temperature Compensated Self Refresh (TCSR) by built‐in temperature sensor

Deep Power Down mode (DPD)

Programmable Driver Strength (DS)

Clock stop capability

Ordering Information

Max Freq.

(MHz)

Data Rate

(Mb/s/pin)

VDD1 / VDD2,

VDDCA, VDDQ

RL

WL

Package

Comments

Product ID

M54D1G1664A-1.8BKG

M54D1G1664A-2.5BKG

M54D1G1664A-3BKG

533

400

333

1066

800

8

6

5

4

3

2

1.8V / 1.2V 134 ball BGA

Pb-free

667

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LPDDR2 SDRAM Addressing

Items

1Gb (64Mb x16)

Device Type

S4

8

Number of Banks

Bank Addresses

t_REFI(us) ^*2

BA0-BA2

7.8

Row Addresses

Column Addresses^*1

R0-R12

C0-C9

Notes:

1. The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.

2. t_REFIvalues for all bank refresh is within temperature specification (T_CASE<= 85℃).

3. Row and Column Address values on the CA bus that are not used are “don’t care”.

Block Diagram

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M54D1G1664A

BALL CONFIGURATION (TOP VIEW)

(BGA 134 Ball, 10mmx11.5mmx1.0mm Body, 0.65mm Ball Pitch)

1

2

3

4

5

6

7

8

9

10

DNU

NC

DNU

NC

DNU

A

B

C

D

E

F

NC

VDD2

VSS

VDD1

VSSQ

NC

VDDQ

NC

VDD1

VSS

VDD2

CA9

CA6

VSSQ

NC

VDDQ

VSSQ

VDDQ

VSSQ

ZQ

VDDQ

NC

VSSCA

VDDCA

VDD2

VDDCA

VSSCA

CKE

CA8

CA7

NC

DQ15

DQ14

DQ9

VDDQ

DQ12

DQ8

VSSQ

DQ11

DQ13

DQ10

= NC / DNU

= Ground

= DRAM

DQS1_c DQS1_t

CA5 VREF(CA)

G

H

J

VSS

NC

CK_c

CK_t

NC

DM1

VSSQ

DM0

VDDQ

VDD2

VSS VREF(DQ)

= Power

NC

K

L

DQS0_c DQS0_t

CS_n

CA4

NC

DQ5

DQ2

NC

DQ6

DQ1

DQ0

NC

DQ7

DQ3

VDDQ

NC

VSSQ

VDDQ

VSSQ

VDDQ

DNU

CA3

VDDCA

VDD2

VSS

NC

CA2

CA1

CA0

NC

VSSQ

NC

DQ4

NC

M

N

P

R

T

VSSCA

VSS

VDDQ

VSS

NC

VDD1

DNU

VSSQ

VDD1

VDDQ

NC

VSSQ

NC

VDD2

NC

DNU

U

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Ball Descriptions

Ball Name

Type

Function

Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are

sampled on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n

and CKE, are sampled at the positive Clock edge.

CK_t, CK_c

Input

Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by

the crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is defined by the

crosspoint of a falling CK_t and a rising CK_c.

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and

therefore device input buffers and output drivers. Power savings modes are entered and exited

through CKE transitions. CKE is considered part of the command code. CKE is sampled at the

positive Clock edge.

CKE

Input

Chip Select: CS_n is considered part of the command code and CS_n is sampled at the

positive Clock edge.

CS_n

CA[n:0]

DQ[n:0]

Input

I/O

DDR Command/Address Inputs: Uni-directional command/address bus inputs.

CA is considered part of the command code.

Data Inputs/Output: Bi-directional data bus. n=15 for 16 bits DQ.

Data Strobe (Bi-directional, Differential):

The data strobe is bi-directional (used for read and write data) and differential (DQS_t and

DQS_c). It is output with read data and input with write data. DQS_t is edge-aligned to read

data and centered with write data.

DQS[n:0]_t,

DQS[n:0]_c

I/O

DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7; DQS1_t and DQS1_c to the data

on DQ8 - DQ15.

Input Data Mask:

DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH

coincident with that input data during a Write access. DM is sampled on both edges of DQS_t.

Although DM is for input only, the DM loading shall match the DQ and DQS_t (or DQS_c).

DM0 is the input data mask signal for the data on DQ0-7, DM1 is the input data mask signal

for the data on DQ8-15.

DM[n:0]

Input

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M54D1G1664A

Ball Name

Type

Function

VDD1

VDD2

Supply

Core power supply 1: Core power supply.

Core power supply 2: Core power supply

Input Receiver Power Supply: Power supply for CA[n:0], CKE, CS_n, CK_t, and CK_c input

buffers.

VDDCA

VDDQ

Supply

I/O Power Supply: Power supply for Data input/output buffers.

Reference Voltage for CA Command and Control Input Receiver: Reference voltage for

all CA[n:0], CKE, CS_n, CK_t, and CK_c input buffers.

VREF(CA)

VREF(DQ)

VSS

Supply

Reference Voltage for DQ Input Receiver: Reference voltage for all Data input buffers.

Ground.

VSSCA

VSSQ

Ground for Input Receivers.

I/O Ground.

ZQ

I/O

-

Reference Pin for Output Drive Strength Calibration.

NC / DNU

No Connection / Do Not Use

Notes: Data includes DQ and DM.

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M54D1G1664A

Electrical Specifications

Absolute Maximum DC Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Parameter

V_DD1supply voltage relative to V_SS

V _DD2supply voltage relative to V_SS

V_DDCAsupply voltage relative to V_SSCA

V_DDQsupply voltage relative to V_SSQ

Voltage on any ball relative to V_SS

Storage Temperature

Symbol

V_DD1

Min

-0.4

-55

Max

+2.3

+1.6

+125

Unit

V

Notes

1

V_DD2

V

1

V_DDCA

V_DDQ

V

1, 2

1, 3

V

V_IN, V_OUT

T_STG

V

℃

4

Notes:

1. See “Power Ramp” section.

2. V_REFCA≦ 0.6 x V_DDCA; however, V_REFCAmay be ≧ V_DDCAprovided that V_REFCA≦ 300mV.

3. V_REFDQ≦ 0.6 x V_DDQ; however, V_REFDQmay be ≧ V_DDQprovided that V_REFDQ≦ 300mV.

4. Storage Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement

conditions, please refer to JESD51-2 standard.

AC & DC Operating Conditions

Recommended DC Operating Conditions

Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the LPDDR2

Device must be powered down and then restarted through the specialized initialization sequence before normal operation can

continue.

Symbol

V_DD1

Min

1.7

Typ

1.8

1.2

Max

1.95

1.3

Power Supply

Core power 1

Unit

V

V_DD2

1.14

Core power 2

V

V_DDCA

V_DDQ

1.3

Input buffer power

I/O buffer power

V

1.3

V

Notes: V_DD1uses significantly less power than V_DD2

.

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Input Leakage Current

Parameter / Condition

Symbol

Min

Max

Unit

Note

Input Leakage current

For CA, CKE, CS_n, CK_t, CK_c

Any input 0V ≦ V_IN≦ V_DDCA

(All other pins not under test = 0V)

I_L

-2

2

uA

1

V_REFsupply leakage current

V_REFDQ= V_DDQ/2 or V_REFCA= V_DDCA/2

(All other pins not under test = 0V)

I_VREF

-1

1

uA

2

Notes:

1. Although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specification.

2. The minimum limit requirement is for testing purposes. The leakage current on V_REFCAand V_REFDQpins should be minimal.

Operating Temperature Range

Parameter / Condition

Standard

Extended

Symbol

Rating

Unit

℃

-25 to +85

+85 to +105

T_CASE

℃

Notes:

1. Operating temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement

conditions, please refer to JESD51-2 standard.

2. Some applications require operation in the maximum case temperature conditons in the Extended Temperature Range

between 85 ℃ and 105 ℃ case temperature. For LPDDR2 devices, some derating is necessary to operate in this range.

See MR4.

3. Either the device case temperature rating or the temperature sensor may be used to set an appropriate refresh rate,

determine the need for AC timing derating and/or monitor the operating temperature. When using the temperature sensor,

the actual device case temperature may be higher than the T_CASErating that applies for the Operating Temperature Range.

For example, T_CASEmay be above 85 ℃ when the temperature sensor indicates a temperature of less than 85 ℃.

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M54D1G1664A

AC and DC Input Measurement Levels

AC and DC Logic Input Levels for Single-Ended Signals

Single-Ended AC and DC Input Levels for CA and CS_n Inputs

Value

Symbol

Parameter

AC input logic high

Unit

Note

Min

Max

Note 2

V_IHCA(AC)

V_ILCA(AC)

V_IHCA(DC)

V_ILCA(DC)

V_REF+ 0.220

Note 2

V

1,2

1

AC input logic low

DC input logic high

DC input logic low

V_REF- 0.220

V_DDCA

V_REF+ 0.130

V_SSCA

V_REF- 0.130

1

Reference Voltage for CA and CS_n

inputs

V_REFCA(DC)

0.49 * V_DDCA

0.51 * V_DDCA

V

3,4

Notes:

1. For CA and CS_n input only pins. V_REF= V_REFCA(DC)

2. See “Overshoot and Undershoot Specifications” section.

.

3. The ac peak noise on V_REFCAmay not allow V_REFCAto deviate from V_REFCA(DC)by more than +/-1% V_DDCA(for reference:

approx. +/- 12 mV).

4. For reference: approx. V_DDCA/2 +/- 12 mV.

Single-Ended AC and DC Input Levels for CKE

Symbol

V_IHCKE

V_ILCKE

Parameter

Min

Max

Note 1

Unit

V

Note

CKE Input High Level

CKE Input Low Level

0.8 * V_DDCA

Note 1

1

0.2 * V_DDCA

V

Note: See “Overshoot and Undershoot Specifications” section.

Single-Ended AC and DC Input Levels for DQ and DM

Value

Symbol

Parameter

AC input logic high

Unit

Note

Min

Max

V_IHDQ(AC)

V_ILDQ(AC)

V_IHDQ(DC)

V_ILDQ(DC)

V_REFDQ(DC)

V_REF+ 0.220

Note 2

V

1,2

1

AC input logic low

Note 2

V_REF+ 0.130

V_SSQ

V_REF- 0.220

V_DDQ

DC input logic high

DC input logic low

V_REF- 0.130

0.51 * V_DDQ

1

Reference Voltage for DQ, DM inputs

0.49 * V_DDQ

3,4

Notes:

1. For DQ input only pins. V_REF= V_REFDQ(DC)

2. See “Overshoot and Undershoot Specifications” section.

.

3. The ac peak noise on V_REFDQmay not allow V_REFDQto deviate from V_REFDQ(DC)by more than +/-1% V_DDQ(for reference:

approx. +/- 12 mV).

4. For reference: approx. V_DDQ/2 +/- 12 mV.

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M54D1G1664A

V_REFTolerances

The DC tolerance limits and AC noise limits for the reference voltages V_REFCAand V_REFDQare illustrated in the Figure below. It

shows a valid reference voltage V_REF(t) as a function of time. (V_REFstands for V_REFCAand V_REFDQlikewise). V_DDstands for V_DDCA

for V_REFCAand V_DDQfor V_REFDQ. V_REF(DC)is the linear average of V_REF(t) over a very long period of time (e.g. 1 sec) and is specified

as a fraction of the linear average of V_DDQor V_DDCAalso over a very long period of time (e.g. 1 sec). This average has to meet the

min/max requirements in Table of “Single-Ended AC and DC Input Levels for CA and CS_n Inputs”. Furthermore V_REF(t) may

temporarily deviate from V_REF(DC)by no more than +/- 1% V_DD. V_REF(t) cannot track noise on V_DDQor V_DDCAif this would send V_REF

outside these specifications.

Figure of Illustration of V_REFDC tolerance and V_REFAC noise limits

The voltage levels for setup and hold time measurements V_IH(AC), V_IH(DC), V_IL(AC)and V_IL(DC)are dependent on V_REF

.

V_REFDC variations affect the absolute voltage a signal must reach to achieve a valid high or low level, as well as the time from

which setup and hold times are measured. When V_REFis outside these specified levels, devices will function correctly with

appropriate timing deratings as long as:

V_REFis maintained between 0.44 x V_DDQ(or V_DDCA) and 0.56 x V_DDQ(or V_DDCA) and so long as the controller achieves the required

single-ended AC and DC input levels from instantaneous V_REF(see the Tables of “Single-Ended AC and DC Input Levels for CA

and CS_n Inputs” and “Single-Ended AC and DC Input Levels for DQ and DM”) Therefore, system timing and voltage budgets

need to account for V_REFdeviations outside of this range.

This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage associated with

V_REFAC noise. Timing and voltage effects due to AC noise on V_REFup to the specified limit (+/-1% of V_DD) are included in

LPDDR2 timings and their associated deratings.

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Input Signal

LPDDR2-466 to LPDDR2-1066 Input Signal

Notes:

1. Numbers reflect nominal values.

2. For CA0-9, CK_t, CK_c, and CS_n, V_DDstands for V_DDCA. For DQ, DM, DQS_t, and DQS_c, V_DDstands for V_DDQ

3. For CA0-9, CK_t, CK_c, and CS_n, V_SSstands for V_SSCA. For DQ, DM, DQS_t, and DQS_c, V_SSstands for V_SSQ

.

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AC and DC Logic Input Levels for Differential Signals

Differential signal definition

Figure of Differential AC swing time and t_DVAC

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Differential swing requirements for clock and strobe

Table of Differential AC and DC Input Levels

For CK_t and CK_c, V_REF= V_REFCA(DC); For DQS_t and DQS_c, V_REF= V_REFDQ(DC)

Value

Symbol

Parameter

Differential input high

Unit

Note

Min

2x (V_IH(DC)- V_REF

Note 1

Max

Note 1

V_IHDIFF(DC)

V_ILDIFF(DC)

V_IHDIFF(AC)

V_ILDIFF(AC)

)

V

3

2

Differential input low

2x (V_REF- V_IL(DC)

)

Differential input high AC

Differential input low AC

2x (V_IH(AC)- V_REF

Note 1

)

Note 1

2x (V_REF- V_IL(AC)

Notes:

1. These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t and DQS_c need to be within the

respective limits (V_IH(DC)max, V_IL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.

Refer to “Overshoot and Undershoot Specifications” section.

2. For CK_t - CK_c use V_IH/V_IL(AC)of CA and V_REFCA; for DQS_t and DQS_c, use V_IH/V_IL(AC)of DQs and V_REFDQ. If a reduced AC

high or AC low level is used for a signal group, the reduced level also applies.

3. Used to define a differential signal slew rate.

Table of Allowed time before ringback (t_DVAC) for CK_t - CK_c and DQS_t - DQS_c

t_DVAC(ps)

@ |V_IH/V_ILDIFF(AC)| = 440mV

@ |V_IH/V_ILDIFF(AC)| = 600mV

Slew Rate [V/ns]

Min

175

170

167

163

162

161

159

155

150

Min

75

57

50

38

34

29

22

13

0

> 4.0

4.0

3.0

2.0

1.8

1.6

1.4

1.2

1.0

< 1.0

0

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Single-ended requirements for differential signals

Each individual component of a differential signal (CK_t, DQS_t, CK_c, or DQS_c) has also to comply with certain requirements

for single-ended signals.

CK_t and CK_c shall meet V_SEH(AC)min / V_SEL(AC)max in every half-cycle.

DQS_t, DQS_c shall meet V_SEH(AC)min / V_SEL(AC)max in every half-cycle preceeding and following a valid transition.

Note that the applicable AC levels for CA and DQ‘s are different per speed-bin.

Figure of Single-ended requirement for differential signals

Note that while CA and DQ signal requirements are with respect to V_REF, the single-ended components of differential signals

have a requirement with respect to V_DDQ/2 for DQS_t, DQS_c and V_DDCA/2 for CK_t, CK_c; this is nominally the same.

The transition of single-ended signals through the AC levels is used to measure setup time. For single-ended components of

differential signals the requirement to reach V_SEL(AC)max, V_SEH(AC)min has no bearing on timing, but adds a restriction on the

common mode characteristics of these signals.

The signal ended requirements for CK_t, CK_c, DQS_t and DQS_c are found in Tables of “Single-Ended AC and DC Input

Levels for CA and CS_n Inputs” and “Single-Ended AC and DC Input Levels for DQ and DM” respectively.

Table of Single-ended levels for CK_t, DQS_t, CK_c, DQS_c

Value

Symbol

V_{SEH (AC)}

V_{SEL (AC)}

Parameter

Unit

Note

Min

Max

Single-ended high-level for strobes

(V_DDQ/2) + 0.220

(V_DDCA/2) + 0.220

Note 3

V

1,2

Single-ended high-level for CK_t, CK_c

Single-ended low-level for strobes

Single-ended low-level for CK_t, CK_c

(V_DDQ/2) - 0.220

(V_DDCA/2) - 0.220

Note 3

Notes:

1. For CK_t, CK_c use V_SEH/V_SEL(AC)of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t,

DQS3_c) use V_IH/V_IL(AC)of DQs.

2. V_IH(AC)/V_IL(AC)for DQs is based on V_REFDQ; V_SEH(AC)/V_SEL(AC)for CA is based on V_REFCA; if a reduced AC high or AC low level is

used for a signal group, then the reduced level applies also here.

3. These values are not defined, however the single-ended signals CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t,

DQS2_c, DQS3_t, DQS3_c need to be within the respective limits (V_IH(DC)max, V_IL(DC)min) for single-ended signals as well

as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” section.

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Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point

voltage of differential input signals (CK_t, CK_c and DQS_t, DQS_c) must meet the requirements in Table of “Single-ended

levels for CK_t, DQS_t, CK_c, DQS_c”. The differential input cross point voltage V_IXis measured from the actual cross point of

true and complement signals to the midlevel between of V_DDand V_SS

.

Figure of V_IXDefinition

Table of Cross point voltage for differential input signals (CK, DQS)

Value

Symbol

Parameter

Unit

Note

Min

Max

Differential Input Cross Point Voltage relative to

V_DDCA/2 for CK_t, CK_c

V_IXCA

V_IXDQ

-120

120

mV

1,2

Differential Input Cross Point Voltage relative to

V_DDQ/2 for DQS_t, DQS_c

-120

120

Notes:

1. The typical value of V_IX(AC)is expected to be about 0.5 × V_DDof the transmitting device, and V_IX(AC)is expected to track

variations in V_DD. V_IX(AC)indicates the voltage at which differential input signals must cross.

2. For CK_t and CK_c, V_REF= V_REFCA(DC). For DQS_t and DQS_c, V_REF= V_REFDQ(DC)

.

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Slew Rate Definitions for Single-Ended Input Signals

See “CA and CS_n Setup, Hold and Derating” section for single-ended slew rate definitions for address and command signals.

See “Data Setup, Hold and Slew Rate Derating” section for single-ended slew rate definitions for data signals.

Slew Rate Definitions for Differential Input Signals

Input slew rate for differential signals (CK_t, CK_c and DQS_t, DQS_c) are defined and measured as shown in Table and Figure

below.

Table of Differential Input Slew Rate Definition

Measured

Description

Defined by

from

to

Differential input slew rate for rising edge

(CK_t - CK_c and DQS_t - DQS_c).

[V_IHDIFFmin - V_ILDIFFmax] / △TR_DIFF

[V_IHDIFFmin – V_IHDIFFmax] / △TF_DIFF

V_ILDIFFmax

V_IHDIFFmin

Differential input slew rate for falling edge

(CK_t - CK_c and DQS_t - DQS_c).

V_IHDIFFmin

V_ILDIFFmax

Note: The differential signal (i.e. CK_t - CK_c and DQS_t - DQS_c) must be linear between these thresholds

Figure of Differential Input Slew Rate Definition for DQS_t, DQS_c and CK_t, CK_c

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AC and DC Output Measurement Levels

Table of Single-Ended AC and DC Output Levels

Symbol

V_OH(DC)

V_OL(DC)

V_OH(AC)

V_OL(AC)

Parameter

Value

Unit

V

Notes

0.9 x V_DDQ

0.1 x V_DDQ

DC output high measurement level (for IV curve linearity)

DC output low measurement level (for IV curve linearity)

AC output high measurement level (for output slew rate )

AC output low measurement level (for output slew rate )

Output Leakage current (DQ, DM, DQS_t, DQS_c)

(DQ, DQS_t, DQS_c are disabled; 0V ≦ V_OUT≦ V_DDQ

1

2

V

V_REFDQ+ 0.12

V

V_REFDQ- 0.12

V

Min

Max

Min

-5

5

uA

%

I_OZ

-15

15

MM_PUPD

Delta R_ONbetween pull-up and pull-down for DQ/DM

Max

%

Notes:

1. I_OH= -0.1 mA.

2. I_OL= 0.1 mA.

Table of Differential AC and DC Output Levels

Symbol

V_OHDIFF(AC)

V_OLDIFF(AC)

Parameter

Value

Unit

V

0.2 x V_DDQ

-0.2 x V_DDQ

AC differential output high measurement level (for output SR)

AC differential output low measurement level (for output SR)

V

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Single-Ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between

V_OL(AC)and V_OH(AC)for single-ended signals as shown in Table and Figure below.

Table of Single-Ended Output Slew Rate Definition

Measured

Description

Defined by

from

V_OL(AC)

V_OH(AC)

to

[V_OH(AC)- V_OL(AC)] / △TR_SE

[V_OH(AC)- V_OL(AC)] / △TF_SE

Single-ended output slew rate for rising edge

Single-ended output slew rate for falling edge

V_OH(AC)

V_OL(AC)

Note: Output slew rate is verified by design and characterization, and may not be subject to production test.

Figure of Single-Ended Output Slew Rate Definition

Table of Single-Ended Output Slew Rate *^1~5

Value

Parameter

Symbol

Unit

Min

1.5

1.0

0.7

Max

3.5

Single-Ended Output Slew Rate (R_ON= 40 +/- 30%)

Single-Ended Output Slew Rate (R_ON= 60 +/- 30%)

Output Slew Rate Matching Ratio (pull-up to pull-down)

SRQ_SE

V/ns

-

2.5

1.4

Notes:

1. Description: SR = Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, Query-Output); SE: Single-Ended

Signals

2. Measured with output reference load.

3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and

voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to

process variation.

4. The output slew rate for falling and rising edges is defined and measured between V_OL(AC)and V_OH(AC)

.

5. Slew rates are measured under normal simultaneous switching output (SSO) conditions, with 1/2 of DQ signals per data byte

driving logic-high and 1/2 of DQ signals per data byte driving logic-low.

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Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between

V_OLDIFF(AC)and V_OHDIFF(AC)for differential signals as shown in Table and Figure below.

Table of Differential Output Slew Rate Definition

Measured

Description

Defined by

From

to

[V_OHDIFF(AC)- V_OLDIFF(AC)] / △TR_DIFF

[V_OHDIFF(AC)- V_OLDIFF(AC)] / △TF_DIFF

Differential output slew rate for rising edge

Differential output slew rate for falling edge

V_OLDIFF(AC)

V_OHDIFF(AC)

V_OLDIFF(AC)

Note: Output slew rate is verified by design and characterization, and may not be subject to production test.

Figure of Differential Output Slew Rate Definition

Table of Differential Output Slew Rate *^1~4

Value

Parameter

Symbol

Unit

Min

3.0

2.0

Max

7.0

Differential Output Slew Rate (R_ON= 40 +/- 30%)

Differential Output Slew Rate (R_ON= 60 +/- 30%)

SRQ_DIFF

V/ns

5.0

Notes:

1. Description: SR = Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, Query-Output); DIFF: Differentia Signals

2. Measured with output reference load.

3. The output slew rate for falling and rising edges is defined and measured between V_OLDIFF(AC)and V_OHDIFF(AC)

.

4. Slew rates are measured under normal simultaneous switching output (SSO) conditions, with 1/2 of DQ signals per data byte

driving logic-high and 1/2 of DQ signals per data byte driving logic-low.

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AC Overshoot/Undershoot Specification

Parameter

1066

933

800

667

533

466

Unit

Maximum peak amplitude

allowed for overshoot area.

Max

0.35

V

Maximum peak amplitude

allowed for undershoot area.

1

Maximum area above V_DD

.

Max

0.15

0.17

0.20

0.24

0.30

0.35 V-ns

2

Maximum area below V_SS

.

(CA0-9, CS_n, CKE, CK_t, CK_c, DQ, DQS_t, DQS_c, DM)

Notes:

1. For CA0-9, CK_t, CK_c, CS_n, and CKE, V_DDstands for V_DDCA. For DQ, DM, DQS_t, and DQS_c, V_DDstands for V_DDQ

.

2. For CA0-9, CK_t, CK_c, CS_n, and CKE, V_SSstands for V_SSCA. For DQ, DM, DQS_t, and DQS_c, V_SSstands for V_SSQ

.

Figure of Overshoot/Undershoot Definition

Notes:

1. For CA0-9, CK_t, CK_c, CS_n, and CKE, V_DDstands for V_DDCA. For DQ, DM, DQS_t, and DQS_c, V_DDstands for V_DDQ

2. For CA0-9, CK_t, CK_c, CS_n, and CKE, V_SSstands for V_SSCA. For DQ, DM, DQS_t, and DQS_c, V_SSstands for V_SSQ

.

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Output buffer characteristics

HSUL_12 Driver Output Timing Reference Load

These “Timing Reference Loads” are not intended as a precise representation of any particular system environment or a

depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to

correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally

one or more coaxial transmission lines terminated at the tester electronics.

Figure of HSUL_12 Driver Output Reference Load for Timing and Slew Rate

Note: All output timing parameter values (like t_DQSCK, t_DQSQ, t_QHS, t_HZ, t_RPREetc.) are reported with respect to this reference load.

This reference load is also used to report slew rate.

R_ONPUand R_ONPDResistor Definition

V_DDQ- V_OUT

R_ONPU

=

ABS (I_OUT

)

When R_ONPUis turned off.

V_OUT

R_ONPD

=

ABS (I_OUT

)

When R_ONPDis turned off.

Figure of Output Driver: Definition of Voltages and Currents

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R_ONPUand R_ONPDCharacteristics with ZQ Calibration

Output driver impedance R_ONis defined by the value of the external reference resistor R_ZQ. Nominal R_ZQis 240 ohm.

Table of Output Driver DC Electrical Characteristics with ZQ Calibration

R_{ON, nom}

Resistor

R_ON34PD

R_ON34PU

R_ON40PD

R_ON40PU

R_ON48PD

R_ON48PU

R_ON60PD

R_ON60PU

R_ON80PD

R_ON80PU

R_ON120PD

R_ON120PU

MM_PUPD

V_OUT

Min

0.85

-15.00

Nom

1.00

Max

1.15

+15.00

Unit

R_ZQ/7

R_ZQ/6

R_ZQ/5

R_ZQ/4

R_ZQ/3

R_ZQ/2

%

Notes

1,2,3,4

1,2,3,4,5

0.5 x V_DDQ

34.3 Ω

40.0 Ω

48.0 Ω

60.0 Ω

80.0 Ω

120.0 Ω

Mismatch between

pull-up and pull-down

Notes:

1. Applies across entire operating temperature range, after calibration.

2. R_ZQ= 240 ohm.

3. The tolerance limits are specified after calibration with fixed voltage and temperature. For behavior of the tolerance limits if

temperature or voltage changes after calibration.

4. Pull-down and pull-up output driver impedances should be calibrated at 0.5 x V_DDQ

5. Measurement definition for mismatch between pull-up and pull-down, MM_PUPD: Measure R_ONPUand R_ONPD, both at 0.5 x

V_DDQ

.

:

R_ONPU- R_ONPD

R_{ON, nom}

MM_PUPD

=

x 100

For example, with MM_PUPD(max) = 15% and R_ONPD= 0.85, R_ONPUmust be less than 1.0.

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Output Driver Temperature and Voltage Sensitivity

If temperature and/or voltage change after calibration, the tolerance limits widen according to the Tables shown below.

Table of Output Driver Sensitivity Definition

Resistor

R_ONPD

V_OUT

Min

Max

Unit

85 – ( dR_ONdT x |Δ T| ) – ( dR_ONdV x |Δ V| )

115 + ( dR_ONdT x |Δ T| ) + ( dR_ONdV x |Δ V| )

0.5 x V_DDQ

%

R_ONPU

Notes:

1. Δ T = T-T (@ calibration), Δ V =V-V (@ calibration)

2. dR_ONdT and dR_ONdV are not subject to production test but are verified by design and characterization.

Table of Output Driver Temperature and Voltage Sensitivity

Symbol

dR_ONdT

dR_ONdV

Parameter

Min

0.00

Max

0.75

0.20

Unit

% / C

R_ONTemperature Sensitivity

R_ONVoltage Sensitivity

% / mV

R_ONPUand R_ONPDCharacteristics without ZQ Calibration

Output driver impedance R_ONis defined by design and characterization as default setting.

Table of Output Driver DC Electrical Characteristics without ZQ Calibration

R_{ON, nom}

Resistor

R_ON34PD

R_ON34PU

R_ON40PD

R_ON40PU

R_ON48PD

R_ON48PU

R_ON60PD

R_ON60PU

R_ON80PD

R_ON80PU

R_ON120PD

R_ON120PU

V_OUT

Min

24

Nom

34.3

40

Max

44.6

52

Unit

Ω

Notes

0.5 x V_DDQ

1

34.3 Ω

Ω

24

Ω

28

40.0 Ω

48.0 Ω

60.0 Ω

80.0 Ω

120.0 Ω

Ω

28

40

52

Ω

33.6

42

48

62.4

78

Ω

48

Ω

60

Ω

42

60

78

Ω

56

80

104

156

Ω

56

80

Ω

84

120

Ω

84

Note: 1. Applies across entire operating temperature range, without calibration.

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R_ZQI-V Curve

R_ON= 240 (R_ZQ

)

Pull-Down

Pull-Up

Current [mA] / R_ON[Ohms]

default value with

Current [mA] / R_ON[Ohms]

Voltage [V]

default value

after ZQReset

with

Calibration

after ZQReset Calibration

Min

[mA]

0.00

0.19

0.38

0.56

0.74

0.92

1.08

1.25

1.40

1.54

1.68

1.81

1.92

2.02

2.11

2.19

2.25

2.30

2.34

2.37

2.41

2.43

2.46

2.48

2.50

Max

[mA]

0.00

0.32

0.64

0.94

1.26

1.57

1.86

2.17

2.46

2.74

3.02

3.30

3.57

3.83

4.08

4.31

4.54

4.74

4.92

5.08

5.20

5.31

5.41

5.48

5.55

Min

Max

[mA]

0.00

0.26

0.53

0.78

1.04

1.29

1.53

1.79

2.03

2.26

2.49

2.72

2.94

3.15

3.36

3.55

3.74

3.91

4.05

4.23

4.33

4.44

4.52

4.59

4.65

Min

Max

[mA]

0.00

Min

Max

[mA]

0.00

[mA]

0.00

0.21

0.40

0.60

0.79

0.98

1.17

1.35

1.52

1.69

1.86

2.02

2.17

2.32

2.46

2.58

2.70

2.81

2.89

2.97

3.04

3.09

3.14

3.19

3.23

[mA]

0.00

[mA]

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

-0.19

-0.38

-0.56

-0.74

-0.92

-1.08

-1.25

-1.40

-1.54

-1.68

-1.81

-1.92

-2.02

-2.11

-2.19

-2.25

-2.30

-2.34

-2.37

-2.41

-2.43

-2.46

-2.48

-2.50

-0.32

-0.64

-0.94

-1.26

-1.57

-1.86

-2.17

-2.46

-2.74

-3.02

-3.30

-3.57

-3.83

-4.08

-4.31

-4.54

-4.74

-4.92

-5.08

-5.20

-5.31

-5.41

-5.48

-5.55

-0.21

-0.40

-0.60

-0.79

-0.98

-1.17

-1.35

-1.52

-1.69

-1.86

-2.02

-2.17

-2.32

-2.46

-2.58

-2.70

-2.81

-2.89

-2.97

-3.04

-3.09

-3.14

-3.19

-3.23

-0.26

-0.53

-0.78

-1.04

-1.29

-1.53

-1.79

-2.03

-2.26

-2.49

-2.72

-2.94

-3.15

-3.36

-3.55

-3.74

-3.91

-4.05

-4.23

-4.33

-4.44

-4.52

-4.59

-4.65

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Figure of R_ON= 240 Ohms IV Curve after ZQReset

Figure of R_ON= 240 Ohms IV Curve after calibration

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Input/Output Capacitance

(T_CASE, V_DD1= 1.7V to 1.95V, V_DD2/V_DDCA/V_DDQ= 1.14V to 1.3V, V_SS/V_SSCA/V_SSQ= 0V)

Parameter

Symbol

CCK

Value

1.0

2.0

0

Unit

pF

Note

1,2

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Input capacitance, CK_t and CK_c

1,2

1,2,3

1,2,4

1,2,5

1,2,6,7

1,2,7,8

1,2,7,9

1,2

Input capacitance delta, CK_t and CK_c

Input capacitance, all other input-only pins

Input capacitance delta, all other input-only pins

Input/output capacitance, DQ, DM, DQS_t, DQS_c

Input/output capacitance delta, DQS_t, DQS_c

Input/output capacitance delta, DQ, DM

Input/output capacitance ZQ Pin

CDCK

CI

0.20

1.0

2.0

-0.40

0.40

1.25

2.5

0

CDI

CIO

CDDQS

CDIO

CZQ

0.25

-0.5

0.5

0

2.5

1,2

Notes:

1. This parameter applies to die device only (does not include package capacitance).

2. This parameter is not subject to production test. It is verified by design and characterization.

The capacitance is measured according to JEP147 (Procedure for measuring input capacitance using a vector network

analyzer (VNA) with V_DD1, V_DD2, V_DDQ, V_SS, V_SSCA, V_SSQapplied and all other pins floating.

3. Absolute value of CCK_t - CCK_c.

4. CI applies to CS_n, CKE, CA0-CA9.

5. CDI = CI - 0.5 * (CCK_t + CCK_c)

6. DM loading matches DQ and DQS.

7. MR3 I/O configuration DS OP3-OP0 = 0001B (34.3 Ohm typical)

8. Absolute value of CDQS_t and CDQS_c.

9. CDIO = CIO - 0.5 * (CDQS_t + CDQS_c) in byte-lane.

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IDD Specification Parameters and Test Conditions

IDD Measurement Conditions

The following definitions are used within the IDD measurement tables:



LOW: V_IN≦ V_IL(DC)MAX



HIGH: V_IN≧ V_IH(DC)MIN

STABLE: Inputs are stable at a HIGH or LOW level

SWITCHING: See the following three tables

Table of Definition of Switching for CA Input Signals

Switching for CA

CK_t

(RISING) /

CK_c

(FALLING) / (RISING) / (FALLING) / (RISING) / (FALLING) / (RISING) / (FALLING) /

CK_c

(FALLING)

(RISING)

(FALLING)

(RISING)

(FALLING)

(RISING)

(FALLING)

(RISING)

Cycle

CS_n

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CA9

N

N+1

HIGH

N+2

HIGH

N+3

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

Notes:

1. CS_n must always be driven HIGH.

2. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus.

3. The above pattern (N, N+1, N+2, N+3...) is used continuously during IDD measurement for IDD values that require

SWITCHING on the CA bus.

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Table of Definition of Switching for IDD4R

Clock

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

CKE

HIGH

CS_n

LOW

HIGH

LOW

HIGH

Clock Cycle Number

Command

Read_Rising

Read_Falling

NOP

CA0-CA2

HLH

LLL

CA3-CA9

All DQ

N

LHLHLHL

LLLLLLL

L

N

N + 1

N + 2

N + 3

LLL

LLLLLLL

H

L

NOP

HLH

LLL

HLHLLHL

HHHHHHH

LHLHLHL

Read_Rising

Read_Falling

NOP

H

L

LLL

NOP

HLH

Notes:

1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle.

2. The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4R.

Table of Definition of Switching for IDD4W

Clock

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Falling

CKE

HIGH

CS_n

LOW

HIGH

LOW

HIGH

Clock Cycle Number

Command

Write_Rising

Write_Falling

NOP

CA0-CA2

HLL

CA3-CA9

LHLHLHL

LLLLLLL

All DQ

N

L

N

LLL

N + 1

N + 2

N + 3

LLL

LLLLLLL

H

L

NOP

HLH

HLL

HLHLLHL

HHHHHHH

LHLHLHL

Write_Rising

Write_Falling

NOP

H

L

LLL

NOP

HLH

Notes:

1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle.

2. Data masking (DM) must always be driven LOW.

3. The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4W.

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IDD Specifications

IDD values are for the entire operating voltage range, and all of them are for the entire standard range.

Table of IDD Specification Parameters and Operating Conditions

Max

Power

Parameter / Test Condition

Symbol

Unit Note

Supply

1066

10

800

10

667

10

Operating one bank active-precharge current:

t_CK= t_CK(avg)min; t_RC= t_RCmin;

CKE is HIGH;

CS_n is HIGH between valid commands;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD0₁

IDD0₂

V_DD1

V_DD2

mA

3

30

V_DDCA

,

IDD0_IN

IDD2P₁

5

1

5

1

5

1

3,4

V_DDQ

Idle power down standby current:

t_CK= t_CK(avg)min;

CKE is LOW; CS_n is HIGH;

All banks idle;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

V_DD1

V_DD2

uA

mA

uA

3

IDD2P₂

2

V_DDCA

V_DDQ

IDD2P_IN

IDD2PS₁

IDD2PS₂

IDD2PS_IN

IDD2N₁

50

1

50

1

50

1

3,4

3

Idle power down standby current with clock stop:

V_DD1

V_DD2

uA

CK_t = LOW, CK_c = HIGH;

CKE is LOW; CS_n is HIGH;

All banks idle;

CA bus inputs are STABLE;

Data bus inputs are STABLE

2

mA

uA

3

V_DDCA

V_DDQ

50

1.5

15

1

50

1.5

15

1

50

1.5

15

1

3,4

3

Idle non power down standby current:

V_DD1

V_DD2

mA

uA

t_CK= t_{CK (avg)}min;

CKE is HIGH; CS_n is HIGH;

All banks idle;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD2N₂

3

V_DDCA

V_DDQ

IDD2N_IN

IDD2NS₁

IDD2NS₂

IDD2NS_IN

IDD3P₁

3,4

3

Idle non power down standby current with clock stop:

V_DD1

V_DD2

1.5

10

1

1.5

10

1

1.5

10

1

CK_t = LOW, CK_c = HIGH;

CKE is HIGH; CS_n is HIGH;

All banks idle;

CA bus inputs are STABLE;

Data bus inputs are STABLE

3

V_DDCA

V_DDQ

3,4

3

Active power down standby current:

V_DD1

V_DD2

2

t_CK= t_CK(avg)min;

CKE is LOW; CS_n is HIGH;

One bank active;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD3P₂

6

3

V_DDCA

V_DDQ

IDD3P_IN

IDD3PS₁

IDD3PS₂

IDD3PS_IN

50

2

50

2

50

2

3,4

3

V_DD1

V_DD2

mA

uA

Active power down standby current with clock stop:

CK_t = LOW, CK_c = HIGH;

CKE is LOW; CS_n is HIGH;

One bank active;

CA bus inputs are STABLE; Data bus inputs are STABLE

6

3

V_DDCA

V_DDQ

50

3,4

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Max

Power

Parameter / Test Condition

Symbol

Unit Note

Supply

1066

3

800

3

667

3

Active non power down standby current:

IDD3N₁

IDD3N₂

V_DD1

V_DD2

mA

3

t_CK= t_CK(avg)min;

CKE is HIGH; CS_n is HIGH;

One bank active;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

15

V_DDCA

,

IDD3N_IN

6

mA

3,4

V_DDQ

Active non power down standby current with clock

IDD3NS₁

IDD3NS₂

V_DD1

V_DD2

3

mA

3

stop:

10

CK_t = LOW, CK_c = HIGH;

CKE is HIGH; CS_n is HIGH;

One bank active;

CA bus inputs are STABLE;

Data bus inputs are STABLE

V_DDCA

V_DDQ

,

IDD3NS_IN

5

mA

3,4

IDD4R₁

IDD4R₂

IDD4R_IN

V_DD1

V_DD2

V_DDCA

V_DDQ

V_DD1

V_DD2

10

150

7

10

140

7

10

130

7

mA

3

Operating burst READ current:

t_CK= t_CK(avg)min;

CS_n is HIGH between valid commands;

One bank active;

BL = 4; RL = RL(min);

CA bus inputs are SWITCHING;

50% data change each burst transfer

IDD4R_Q

-

mA

3,5

Operating burst WRITE current:

IDD4W₁

IDD4W₂

5

mA

3

t_CK= t_CK(avg)min;

CS_n is HIGH between valid commands;

One bank active;

140

130

120

BL = 4; WL = WL(min);

CA bus inputs are SWITCHING;

50% data change each burst transfer

V_DDCA

V_DDQ

,

IDD4W_IN

15

mA

3,4

All Bank REFRESH Burst current:

IDD5₁

IDD5₂

V_DD1

V_DD2

25

80

25

80

25

80

mA

3

t_CK= t_CK(avg)min;

CKE is HIGH between valid commands;

t_RC= t_RFCabmin;

Burst refresh;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

V_DDCA

V_DDQ

,

IDD5_IN

5

mA

3,4

All Bank REFRESH Average current:

IDD5AB₁

IDD5AB₂

IDD5AB_IN

IDD5PB₁

IDD5PB₂

IDD5PB_IN

V_DD1

V_DD2

2

11

5

2

11

5

2

11

5

mA

3

t_CK= t_CK(avg)min;

CKE is HIGH between valid commands;

t_RC= t_REFI

;

V_DDCA

V_DDQ

,

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

3,4

1,3

1,3,4

Pre Bank REFRESH Average current:

V_DD1

V_DD2

2

1

t_CK= t_CK(avg)min;

CKE is HIGH between valid commands;

t_RC= t_REFI/ 8;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

16

5

16

5

16

5

V_DDCA

V_DDQ

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Max

Power

Parameter / Test Condition

Symbol

Unit Note

Supply

1066

1

800

1

667

1

2,3,7,

8

Self refresh current (Standard Temperature Range):

IDD6₁

IDD6₂

V_DD1

V_DD2

mA

CK_t = LOW, CK_c = HIGH;

CKE is LOW;

CA bus inputs are STABLE;

2,3,7,

8

2.5

Data bus inputs are STABLE;

2,3,4

7,8

V_DDCA

V_DDQ

,

IDD6_IN

50

uA

Maximum 1x Self Refresh Rate

IDD8₁

IDD8₂

IDD8_IN

V_DD1

V_DD2

30

150

50

30

150

50

30

150

50

uA

mA

uA

3

Deep power down current:

CK_t = LOW, CK_c = HIGH;

CKE is LOW;

CA bus inputs are STABLE;

Data bus inputs are STABLE

V_DDCA

V_DDQ

3,4

Notes:

1. Per Bank Refresh only applicable for LPDDR2-S4 devices of 1Gb or higher densities.

2. This is the general definition that applies to full array Self Refresh. Refer to Table of “IDD6 Partial Array Self Refresh

Current”.

3. IDD values published are the maximum of the distribution of the arithmetic mean.

4. Measured currents are the summation of V_DDQand V_DDCA

.

5. Guaranteed by design with output load of 5pF and R_ON= 40Ohm.

6. IDD current specifications are tested after the device is properly initialized.

7. In addition, supplier data sheets may include additional Self Refresh IDD values for temperature subranges within the

Standard or Extended Temperature Ranges.

8. 1x Self Refresh Rate is the rate at which the LPDDR2-SX device is refreshed internally during Self Refresh before going into

the Extended Temperature range.

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Table of IDD6 Partial Array Self Refresh Current

Parameter

Supply

Value

1

Unit

mA

uA

V_DD1

V_DD2

Full Array

1/2 Array

2.5

50

V_DDCA, V_DDQ

V_DD1

0.9

2.4

50

mA

uA

V_DD2

V_DDCA, V_DDQ

V_DD1

IDD6 Partial Array Self

Refresh Current

0.8

2.3

50

mA

uA

1/4 Array

1/8 Array

V_DD2

V_DDCA, V_DDQ

V_DD1

0.7

2.2

50

mA

uA

V_DD2

V_DDCA, V_DDQ

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Electrical Characteristics and AC Timing

Clock Specification

The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in

malfunction of the LPDDR2 device.

Definition for t_CK(avg)and nCK

t_CK(avg)is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated

from rising edge to rising edge.

N

t _{CK (avg)}

=

/ N

S t _CKj

j =1

where

N = 200

Unit ‘t_CK(avg)’ represents the actual clock average t_CK(avg)of the input clock under operation. Unit ‘nCK’ represents one clock cycle

of the input clock, counting the actual clock edges.

t_CK(avg)may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and timing specs are met.

Definition for t_CK(abs)

t_CK(abs)is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge.

t_CK(abs)is not subject to production test.

Definition for t_CH(avg)and t_CL(avg)

t_CH(avg)is defined as the average high pulse width, as calculated across any consecutive 200 high pulses.

N

t _{CH (avg)}

=

/ (N x t _{CK (avg)})

S t _CHj

j =1

where

N = 200

t_CL(avg)is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.

N

t _{CL (avg)}

=

/ (N x t _{CK (avg)})

S t _CLj

j =1

where

N = 200

Definition for t_JIT(per)

t_JIT(per)is the single period jitter defined as the largest deviation of any signal t_CKfrom t_CK(avg)

t_JIT(per)= Min/max of {t_CKi- t_CK(avg)where i = 1 to 200}.

t_JIT(per),actis the actual clock jitter for a given system.

.

t_{JIT(per),allowed}is the specified allowed clock period jitter.

t_JIT(per)is not subject to production test.

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Definition for t_JIT(cc)

t_JIT(cc)is defined as the absolute difference in clock period between two consecutive clock cycles.

t_JIT(cc)= Max of |{t_{CKi +1}- t_CKi}|.

t_JIT(cc)defines the cycle to cycle jitter.

t_JIT(cc)is not subject to production test.

Definition for t_ERR(nper)

t_ERR(nper)is defined as the cumulative error across n multiple consecutive cycles from t_CK(avg)

t_{ERR(nper),act}is the actual clock jitter over n cycles for a given system.

t_{ERR(nper),allowed}is the specified allowed clock period jitter over n cycles.

t_ERR(nper)is not subject to production test.

.

i+n-1

t _{ERR (nper)}

=

- n x t _{CK (avg)}

S t _CKj

j = i

t_{ERR(nper),min}can be calculated by the formula shown below:

t _{ERR (nper), min}= (1 + 0.68 LN (n )) x t _{JIT(per), min}

t_{ERR(nper),max}can be calculated by the formula shown below:

t _{ERR (nper), max}= (1 + 0.68 LN (n )) x t _{JIT(per), max}

Using these equations, t_ERR(nper)tables can be generated for each t_JIT(per),actvalue.

Definition for duty cycle jitter t_JIT(duty)

t_JIT(duty)is defined with absolute and average specification of t_CH/ t_CL.

t _{JIT (duty), min}= MIN ((t _{CH(abs), min}- t _{CH(avg), min}), (t _{CL(abs), min}- t _{CL(avg), min}) ) x t _CK(avg)

t _{JIT (duty), max}= MAX ((t _{CH(abs), max}- t _{CH(avg), max}), (t _{CL(abs), max}- t _{CL(avg), max}) ) x t _CK(avg)

Definition for t_CK(abs), t_CH(abs)and t_CL(abs)

These parameters are specified per their average values, however it is understood that the following relationship between the

average timing and the absolute instantaneous timing holds at all times.

Parameter

Symbol

Min

Unit

ps

Absolute Clock Period

t_CK(abs)

t_CH(abs)

t_CL(abs)

t_CK(avg),min+ t_JIT(per),min

t_CH(avg),min+ t_{JIT(duty),min}/ t_CK(avg),min

t_CL(avg),min+ t_{JIT(duty),min}/ t_CK(avg),min

Absolute Clock HIGH Pulse Width

Absolute Clock LOW Pulse Width

t_CK(avg)

Notes:

1. t_CK(avg),minis expressed is ps for this table.

2. t_{JIT(duty),min}is a negative value.

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Period Clock Jitter

LPDDR2 devices can tolerate some clock period jitter without core timing parameter derating. This section describes device

timing requirements in the presence of clock period jitter (t_JIT(per)) in excess of the values found in Table of “AC Timing” and how to

determine cycle time derating and clock cycle derating.

Clock period jitter effects on core timing parameters (t_RCD, t_RP, t_RTP, t_WR, t_WRA, t_WTR, t_RC, t_RAS, t_RRD, t_FAW

)

Core timing parameters extend across multiple clock cycles. Period clock jitter will impact these parameters when measured in

numbers of clock cycles. When the device is operated with clock jitter within the specification limits, the LPDDR2 device is

characterized and verified to support tn_PARAM= RU{ t_PARAM/ t_CK(avg)}.

When the device is operated with clock jitter outside specification limits, the number of clocks or t_CK(avg)may need to be increased

based on the values for each core timing parameter.

Cycle time derating for core timing parameters

For a given number of clocks (tn_PARAM), for each core timing parameter, average clock period (t_CK(avg)) and actual cumulative

period error (t_ERR(tn_PARAM),act) in excess of the allowed cumulative period error (t_ERR(tn_PARAM),allowed), the equation below

calculates the amount of cycle time derating (in ns) required if the equation results in a positive value for a core timing parameter.

t _PARAM+ t _ERR(tn _PARAM),act - t _ERR(tn _PARAM),allowed

- t _CK(avg), 0

CycleTimeDerating = Max

tn _PARAM

A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating required is

the maximum of the cycle time deratings determined for each individual core timing parameter.

Clock Cycle derating for core timing parameters

For a given number of clocks (tn_PARAM) for each core timing parameter, clock cycle derating should be specified with amount of

period jitter (t_JIT(per)).

For a given number of clocks (tn_PARAM), for each core timing parameter, average clock period (t_CK(avg)) and actual cumulative

period error (t_ERR(tn_PARAM),act) in excess of the allowed cumulative period error (t_ERR(tn_PARAM),allowed), the equation below

calculates the clock cycle derating (in clocks) required if the equation results in a positive value for a core timing parameter.

t _PARAM+ t _ERR(tn _PARAM),act - t _ERR(tn _PARAM),allowed

- tn _PARAM

ClockCycleDerating = RU

t _CK(avg)

A clock cycle derating analysis should be conducted for each core timing parameter.

Clock jitter effects on Command/Address timing parameters (t_IS, t_IH, t_ISCKE, t_IHCKE, t_ISb, t_IHb, t_ISCKEb, t_IHCKEb

)

These parameters are measured from a command/address signal (CKE, CS_n, CA0 - CA9) transition edge to its respective clock

signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT(per), as the setup and

hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values

shall be met.

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Clock jitter effects on Read timing parameters

t_RPRE

When the device is operated with input clock jitter, t_RPREneeds to be derated by the actual period jitter (t_JIT(per),act,max) of the

input clock in excess of the allowed period jitter (t_JIT(per),allowed,max). Output deratings are relative to the input clock.

t _JIT(per),act,max - t _JIT(per),allowed,max

t _{RPRE (min, derated)}= 0.9 -

t _CK(avg)

For example,

if the measured jitter into a LPDDR2-800 device has t_CK(avg)= 2500 ps, t_JIT(per),act,min = -172 ps and t_JIT(per),act,max = + 193 ps,

then

t_{RPRE (min,derated)}= 0.9 - (t_JIT(per),act,max - t_JIT(per),allowed,max)/t_CK(avg)= 0.9 - (193 - 100)/2500= 0.8628 t_CK(avg)

t_LZ(DQ), t_HZ(DQ), t_DQSCK, t_LZ(DQS), t_HZ(DQS)

These parameters are measured from a specific clock edge to a data signal (DMn, DQm: n=0, 1, 2, 3. m=0-31) transition and will

be met with respect to that clock edge. Therefore, they are not affected by the amount of clock jitter applied (i.e. t_JIT(per)).

t_QSH, t_QSL

These parameters are affected by duty cycle jitter which is represented by t_{CH(abs), min}and t_{CL(abs), min}

t_{QSH(abs), min}= t_{CH(abs), min}- 0.05

.

t_{QSL(abs), min}= t_{CL(abs), min}- 0.05

These parameters determine absolute Data-Valid window at the LPDDR2 device pin.

Absolute min data-valid window @ LPDDR2 device pin =

min { ( t_{QSH(abs), min}* t_{CK(avg), min}- t_{DQSQ, max}- t_{QHS, max}), ( t_{QSL(abs), min}* t_{CK(avg), min}- t_{DQSQ, max}- t_{QHS, max}) }

This minimum data-valid window shall be met at the target frequency regardless of clock jitter.

t_RPST

t_RPSTis affected by duty cycle jitter which is represented by t_CL(abs). Therefore t_{RPST(abs),min}can be specified by t_{CL(abs), min}

t_{RPST(abs), min}= t_{CL(abs), min}- 0.05 = t_{QSL(abs), min}

.

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Clock jitter effects on Write timing parameters

t_DS, t_DH

These parameters are measured from a data signal (DMn, DQm: n=0, 1, 2, 3. m=0-31) transition edge to its respective data

strobe signal (DQSn_t, DQSn_c: n=0, 1, 2, 3) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.

t_JIT(per)), as the setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock

jitter values, these values shall be met.

t_DSS, t_DSH

These parameters are measured from a data strobe signal (DQSx_t, DQSx_c) crossing to its respective clock signal (CK_t/CK_c)

crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT(per)), as the setup and hold are relative to

the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values shall be met.

t_DQSS

This parameter is measured from a data strobe signal (DQSx_t, DQSx_c) crossing to the subsequent clock signal (CK_t/CK_c)

crossing. When the device is operated with input clock jitter, this parameter needs to be derated by the actual period jitter

t_JIT(per),act of the input clock in excess of the allowed period jitter t_JIT(per),allowed.

t _JIT(per),act,min - t _JIT(per),allowed,min

t _{DQSS (min, derated)}= 0.75 -

t _CK(avg)

t _JIT(per),act,max - t _JIT(per),allowed,max

t _{DQSS (max, derated)}= 1.25 -

t _CK(avg)

For example,

if the measured jitter into a LPDDR2-800 device has t_CK(avg)= 2500 ps, t_JIT(per),act,min = -172 ps and t_JIT(per),act,max = + 193 ps,

then

t_{DQSS,(min,derated)}= 0.75 - (t_JIT(per),act,min - t_JIT(per),allowed,min)/t_CK(avg)= 0.75 - (-172 + 100)/2500 = 0.7788 t_CK(avg)

and

t_{DQSS,(max,derated)}= 1.25 - (t_JIT(per),act,max - t_JIT(per),allowed,max)/t_CK(avg)= 1.25 - (193 - 100)/2500 = 1.2128 t_CK(avg)

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Refresh Requirements

Table of Refresh Requirement Parameters

Parameter

Number of Banks

Symbol

Value

Unit

8

Refresh Window

t_REFW

32

8

ms

T_CASE≦ 85 ℃

Refresh Window

t_REFW

85℃＜T_CASE≦ 105 ℃

4,096

7.8

Required number of REFRESH commands (min)

R

Average time between REFRESH commands

(for reference only)

REFab

REFpb

t_REFI

us

t_REFIpb

0.975

130

60

T_CASE≦ 85 ℃

Refresh Cycle time

t_RFCab

t_RFCpb

t_REFBW

ns

us

Pre Bank Refresh Cycle time

Burst Refresh Window = 4 x 8 x t_RFCab

4.16

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AC Timing

Table of AC Timing^*1~2

AC timing parameters must satisfy the t_CKminimum conditions (in multiples of t_CK) as well as the timing specifications when

values for both are indicated.

LPDDR2

800

Min / Min

Parameter

Max. Frequency^*4

Symbol

Unit

Max

t_CK

1066

667

~

533

400

333

MHz

Clock Timing

min

max

min

max

min

max

min

max

min

max

min

max

1.875

2.5

3

ns

Average Clock Period

t_CK(avg)

100

ns

0.45

t_CK(avg)

ps

Average HIGH Pulse Width

t_CH(avg)

0.55

0.45

Average LOW Pulse Width

Absolute Clock Period

t_CL(avg)

0.55

t_CK(abs)

t_{CK(avg), min}+ t_JIT(per),

min

0.43

0.57

0.43

0.57

-100

100

t_CK(avg)

ps

Absolute Clock HIGH Pulse Width (with

allowed jitter)

t_CH(abs),

allowed

Absolute Clock LOW Pulse Width (with

allowed jitter)

t_CL(abs),

allowed

-90

90

-110

110

t_JIT(per)

,

Clock Period Jitter (with allowed jitter)

allowed

ps

Maximum Clock Jitter between Two

Consecutive Clock Cycles (with allowed

jitter)

t_JIT(cc)

,

max

180

200

220

ps

allowed

min((t_{CH(abs) min}

(t_{CL(abs) min}‐ t_{CL(avg) min}

max((t_{CH(abs) max}‐ t_{CH(avg) max}

(t_{CL(abs) max}‐ t_{CL(avg) max})) x t_CK(avg)

,

‐ t_{CH(avg) min}

)) x t_CK(avg)

),

,

),

min

ps

,

t_JIT(duty)

allowed

,

Duty Clock Jitter (with allowed jitter)

,

max

,

min

max

min

max

min

max

min

max

-132 -162

-147

147

-175

175

-194

194

-209

209

ps

t_ERR(2per)

,

Cumulative Error Across 2 Cycles

Cumulative Error Across 3 Cycles

Cumulative Error Across 4 Cycles

Cumulative Error Across 5 Cycles

allowed

132

-157

157

162

-192

192

-214

214

-230

230

t_ERR(3per)

allowed

-175

175

t_ERR(4per)

allowed

-188

188

t_ERR(5per)

allowed

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LPDDR2

Min / Min

Parameter

Symbol

Unit

Max

min

max

min

max

min

max

min

max

min

max

min

max

min

max

t_CK

1066

800

667

-200

-222

-244

ps

t_ERR(6per)

,

Cumulative Error Across 6 Cycles

Cumulative Error Across 7 Cycles

Cumulative Error Across 8 Cycles

Cumulative Error Across 9 Cycles

Cumulative Error Across 10 Cycles

Cumulative Error Across 11 Cycles

Cumulative Error Across 12 Cycles

allowed

200

-209

209

-217

217

-224

224

-231

231

-237

237

-242

242

222

-232

232

-241

241

-249

249

-257

257

-263

263

-269

269

244

-256

256

t_ERR(7per)

allowed

,

-266

266

t_ERR(8per)

allowed

-274

274

t_ERR(9per)

allowed

-282

282

t_ERR(10per)

,

allowed

-289

289

t_ERR(11per)

allowed

-296

t_ERR(12per)

allowed

296

t_{ERR(nper) allowed, min}

,

= (1 + 0.68ln(n)) ×

min

ps

t_{JIT(per),allowed, min}

Cumulative Error Across n = 13, 14,…, 49,

t_ERR(nper),

50 Cycles

allowed

t_{ERR(nper),allowed, max}=(1 +0.68ln(n)) ×

t_{JIT(per),allowed , max}

max

ZQ Calibration Parameters

Initialization Caibration Time

Long Calibration Time

Short Calibration Time

Calibration Reset Time

Read Parameters^*14

t_ZQINIT

t_ZQCL

min

1

us

ns

6

3

360

90

t_ZQCS

t_ZQRESET

50

min

max

2500

5500

ps

DQS Output Access Time from CK_t, CK_c

t_DQSCK

DQSCK Delta Short^*18

DQSCK Delta Medium^*19

DQSCK Delta Long^*20

DQS-DQ Skew

t_DQSCKDS

330

680

920

200

230

450

900

540

1050

1400

280

t_DQSCKDM

t_DQSCKDL

t_DQSQ

1200

240

Data Hold Skew Factor

t_QHS

280

340

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LPDDR2

Min / Min

Parameter

Symbol

Unit

Max

min

max

t_CK

1066

800

667

DQS Output HIGH Pulse Width

DQS Output LOW Pulse Width

Data Half Period

t_QSH

t_QSL

t_CH(abs)- 0.05

t_CK(avg)

ps

t_CL(abs)- 0.05

t_QHP

min(t_QSH, t_QSL

t_QHP- t_QHS

)

DQ / DQS Output Hold Time from DQS

READ Preamble^*15~16

t_QH

t_CK(avg)

t_RPRE

t_RPST

t_LZ(DQS)

t_LZ(DQ)

t_HZ(DQS)

t_HZ(DQ)

0.9

READ Postamble^*15,17

t_CL(abs)- 0.05

DQS Low-Z from Clock^*15

t_{DQSCK, min}- 300

t_{DQSCK, min}- (1.4 x t_{QHS, max}

t_{DQSCK, max}- 100

ps

DQ Low-Z from Clock^*15

)

DQS High-Z from Clock^*15

DQ High-Z from Clock^*15

t_{DQSCK, max}+ (1.4 x t_{DQSQ, max}

)

Write Parameters^*14

DQ and DM Input Hold Time (V_REFbased)

DQ and DM Input Setup Time (V_REFbased)

DQ and DM Input Pulse Width

t_DH

t_DS

min

max

min

210

270

0.35

0.75

1.25

0.4

350

ps

210

ps

t_DIPW

t_CK(avg)

Write Command to 1st DQS Latching

Transition

t_DQSS

DQS Input High-Level Width

DQS Input Low-Level Width

DQS Falling Edge to CK Setup Time

DQS Falling Edge Hold Time from CK

Write Postamble

t_DQSH

t_DQSL

t_DSS

0.4

0.2

t_DSH

0.2

t_WPST

t_WPRE

0.4

Write Preamble

0.35

CKE Input Parameters

CKE Min. Pulse Width (high and low pulse

width)

t_CKE

min

3

t_CK(avg)

*2

CKE Input Setup Time

t_ISCKE

0.25

*3

CKE Input Hold Time

t_IHCKE

Command / Address Input Parameters^*14

Address and Control Input Hold Time (V_REF

based)

*1

t_IH

min

220

290

0.4

370

ps

Address and Control Input Setup Time (V_REF

based)

*1

t_IS

ps

Address and Control Input Pulse Width

t_IPW

t_CK(avg)

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LPDDR2

Min / Min

Parameter

Symbol

Unit

Max

t_CK

1066

800

667

Boot Parameters (10 MHz ‐ 55 MHz) ^*8,10,11

max

min

max

100

18

ns

ps

ns

Clock Cycle Time

t_CKb

CKE Input Setup Time

t_ISCKEb

t_IHCKEb

t_ISb

2.5

CKE Input Hold Time

2.5

Address & Control Input Setup Time

Address & Control Input Hold Time

1150

2.0

t_IHb

DQS Output Data Access Time from CK_t/

CK_c

t_DQSCKb

10.0

Data Strobe Edge to Output Data Edge

t_DQSQb-1.2

t_DQSQb

t_QHSb

max

1.2

ns

Data Hold Skew Factor

Mode Register Parameters

Mode Register Read Command Period

Mode Register Write Command Period

SDRAM Core Parameters^*12

Read Latency

t_MRR

t_MRW

min

2

5

2

5

t_CK(avg)

RL

min

8

4

6

3

5

2

t_CK(avg)

Write Latency

WL

t_RAS+ t_RPab(with all‐bank Precharge)

t_RAS+ t_RPpb(with per‐bank Precharge)

Active to Active Command Period

t_RC

min

ns

CKE Minimum Pulse Width during Self

Refresh (Low Pulse Width during Self

Refresh)

t_CKESR

min

3

2

15

ns

Self Refresh Exit to Next Valid Command

Delay

t_XSR

t_RFCab+10

Exit Power Down to Next Valid Command

Delay

t_XP

min

2

7.5

2

ns

t_CK(avg)

ns

CAS to CAS Delay

t_CCD

t_RTP

Internal Read to Precharge Command

Delay

7.5

Fast

Typ

3

15

18

24

ns

RAS to CAS Delay

t_RCD

Slow

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LPDDR2

Min / Min

Parameter

Symbol

Unit

Max

Fast

Typ

t_CK

1066

800

667

3

15

ns

us

ns

us

Row Precharge Time (single bank)

t_RPpb

3

18

24

18

21

27

42

70

15

7.5

10

50

500

Slow

Fast

Typ

3

Row Precharge Time (all bank)

Row Active Time

t_RPab

3

Slow

min

3

t_RAS

max

min

Write Recovery Time

t_WR

t_WTR

t_RRD

t_FAW

t_DPD

3

2

8

Internal Write to Read Command Delay

Active Bank A to Active Bank B Command

Four Bank Activate Window

min

Minimum Deep Power Down Time

Temperature Derating

min

t_DQSCK

t_DQSCKDerating

max

min

5620

6000

ps

ns

(Derated)

t_RCD

(Derated)

t_RCD+ 1.875

t_RC+ 1.875

t_RAS+ 1.875

t_RP+ 1.875

t_RRD+ 1.875

t_RC

(Derated)

t_RAS

Core Timings Temperature Derating

(Derated)

t_RP

(Derated)

t_RRD

(Derated)

Notes:

1. Frequency values are for reference only. Clock cycle time (t_CK) shall be used to determine device capabilities.

2. All AC timings assume an input slew rate of 1V/ns.

3. Read, Write, and input setup and hold values are referenced to V_REF

.

4. t_DQSCKDSis the absolute value of the difference between any two t_DQSCKmeasurements (in a byte lane) within a contiguous

sequence of bursts in a 160ns rolling window. t_DQSCKDSis not tested and is guaranteed by design. Temperature drift in the

system is < 10℃/s. Values do not include clock jitter.

5. t_DQSCKDMis the absolute value of the difference between any two t_DQSCKmeasurements (in a byte lane) within a 1.6us rolling

window. t_DQSCKDMis not tested and is guaranteed by design. Temperature drift in the system is < 10℃/s. Values do not

include clock jitter.

6. t_DQSCKDLis the absolute value of the difference between any two t_DQSCKmeasurements (in a byte lane) within a 32ms rolling

window. t_DQSCKDLis not tested and is guaranteed by design. Temperature drift in the system is < 10℃/s. Values do not

include clock jitter.

For Low-to-High and High-to-Low transitions, the timing reference is at the point when the signal crosses V_TT. t_HZand t_LZ

transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not

referenced to a specific voltage level but to the time when the device output is no longer driving (for t_RPST, t_HZ(DQS)and t_HZ(DQ)),

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or begins driving (for t_RPRE, t_LZ(DQS), t_LZ(DQ)). The figure below shows a method to calculate the point when device is no longer

driving t_HZ(DQS)and t_HZ(DQ), or begins driving t_LZ(DQS)and t_LZ(DQ)by measuring the signal at two different voltages. The actual

voltage measurement points are not critical as long as the calculation is consistent. The parameters t_LZ(DQS), t_LZ(DQ), t_HZ(DQS)

and t_HZ(DQ)are defined as single-ended. The timing parameters t_RPREand t_RPSTare determined from the differential signal

DQS_t / DQS_c.

,

Output Transition Timing

7. Measured from the start driving of DQS_t / DQS_c to the start driving the first rising strobe edge.

8. Measured from the start driving the last falling strobe edge to the stop driving DQS_t / DQS_c.

9. CKE input setup time is measured from CKE reaching High/Low voltage level to CK_t / CK_c crossing.

10. CKE input hold time is measured from CK_t/CK_c crossing to CKE reaching High/Low voltage level.

11. Input setup/hold time for signal (CA0 ~ 9, CS_n).

12. To ensure device operation before the device is configured a number of AC boot timing parameters are defined in this table.

Boot parameter symbols have the letter b appended, e.g., t_CKduring boot is t_CKb

.

13. The LPDDR2 devices set some mode register default values upon receiving a RESET (MRW) command as specified in

“Mode Register Definition” section.

14. The output skew parameters are measured with R_ONdefault settings into the reference load.

15. The min t_CKcolumn applies only when t_CKis greater than 6ns.

16. Timing derating applies for operation at 85˚C to 105˚C when the requirement to derate is indicated by mode register 4

op-code (see the Table of “MR4_Device Temperature (MA[7:0] = 04h)”).

17. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address

may result in reduction of the product lifetime.

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CA and CS_n Setup, Hold and Derating

For all input signals (CA and CS_n) the total t_IS(setup time) and t_IH(hold time) is calculated by adding the data sheet t_IS(base)and

t_IH(base)value to the △t_ISand △t_IHderating value respectively (see the series of tables following this section). Example: t_IS(total

setup time) = t_IS(base)+ △t_IS.

Setup (t_IS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_REF(DC)and the first

crossing of V_{IH(AC), min}. Setup (t_IS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of

V_REF(DC)and the first crossing of V_{IL(AC), max}. If the actual signal is always earlier than the nominal slew rate line between shaded

‘V_REF(DC)to AC region’, use nominal slew rate for derating value (see the Figure of “Illustration of nominal slew rate and t_VACfor

setup time t_ISfor CA and CS_n with respect to clock”). If the actual signal is later than the nominal slew rate line anywhere

between shaded ‘V_REF(DC)to AC region’, the slew rate of a tangent line to the actual signal from the AC level to DC level is used

for derating value (see the Figure of “Illustration of tangent line for setup time t_ISfor CA and CS_n with respect to clock”).

Hold (t_IH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_{IL(DC), max}and the first

crossing of V_REF(DC). Hold (t_IH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of

V_IH(DC),minand the first crossing of V_REF(DC). If the actual signal is always later than the nominal slew rate line between shaded ‘DC

to V_REF(DC)region’, use nominal slew rate for derating value (see the Figure of “Illustration of nominal slew rate for hold time t_IHfor

CA and CS_n with respect to clock”). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC

to V_REF(DC)region’, the slew rate of a tangent line to the actual signal from the DC level to V_REF(DC)level is used for derating value

(see the Figure of “Illustration of tangent line for hold time t_IHfor CA and CS_n with respect to clock”).

For a valid transition, the input signal has to remain above/below V_IH/V_IL(AC)for some time t_VAC(see the Table of “Required time

t_VACabove V_IH(AC){below V_IL(AC)} for valid transition”). Although for slow slew rates the total setup time might be negative (i.e. a

valid input signal will not have reached V_IH/V_IL(AC)at the time of the rising clock transition). A valid input signal is still required to

complete the transition and reach V_IH/V_IL(AC)

.

For slew rates between the values listed in the tables, the derating values are obtained by linear interpolation. These values are

typically not subject to production test. They are verified by design and characterization.

Table of CA and CS_n Setup and Hold Base-Values for 1V/ns

LPDDR2

Unit [ps]

Reference

1066

0

933

30

800

70

667

150

240

533

240

330

466

300

390

t_IS(base)

t_IH(base)

V_IH/V_IL(AC)= V_REF(DC)± 220mV

V_IH/V_IL(DC)= V_REF(DC)± 130mV

90

120

160

LPDDR2

Unit [ps]

Reference

400

300

400

333

440

540

266

600

700

200

850

950

t_IS(base)

t_IH(base)

V_IH/V_IL(AC)= V_REF(DC)± 300mV

V_IH/V_IL(DC)= V_REF(DC)± 200mV

Note: AC/DC referenced for 1V/ns CA and CS_n slew rate and 2V/ns differential CK_t / CK_c slew rate.

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Table of Derating values LPDDR2 t_IS/t_IH- AC/DC based AC220

△t_IS, △t_IHderating in [ps] AC/DC based

AC220 Threshold -> V_IH(AC)= V_REF(DC)+220mV, V_IL(AC)= V_REF(DC)-220mV

DC130 Threshold -> V_IH(DC)= V_REF(DC)+130mV, V_IL(DC)= V_REF(DC)-130mV

CK_t, CK_c Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH

2.0

1.5

110

74

65

43

110

73

65

43

110

73

65

43

89

16

59

16

1.0

0

32

0.9

0.8

0.7

0.6

0.5

0.4

-3

-5

-3

-8

-5

13

8

11

3

29

24

18

10

27

19

10

-3

45

40

34

26

4

43

35

26

13

-4

-13

56

50

42

20

-7

55

46

33

16

2

-6

66

58

36

17

78

65

48

34

Note: Cell contents shaded in blue are defined as ‘not supported’.

Table of Derating values LPDDR2 t_IS/t_IH- AC/DC based - AC300

△t_IS, △t_IHderating in [ps] AC/DC based

AC300 Threshold -> V_IH(AC)= V_REF(DC)+300mV, V_IL(AC)= V_REF(DC)-300mV

DC200 Threshold -> V_IH(DC)= V_REF(DC)+200mV, V_IL(DC)= V_REF(DC)-200mV

CK_t, CK_c Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH

2.0

1.5

150 100 150 100 150 100

100

0

67

0

100

0

67

0

100

67

116

16

83

16

1.0

0

32

0.9

0.8

0.7

0.6

-4

-8

-4

-8

12

4

8

28

20

13

2

24

12

-2

44

36

29

18

-12

40

28

14

-5

-12

-20

-4

52

45

34

4

48

34

-3

-18

61

50

66

47

20

-8

-21

15

0.5

0.4

-32

-12

-40

20

-35

-11

Note: Cell contents shaded in blue are defined as ‘not supported’.

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Table of Required time t_VACabove V_IH(AC){below V_IL(AC)} for valid transition

t_VAC@ 300mV [ps]

t_VAC@ 220mV [ps]

Slew Rate [V/ns]

min

75

57

50

38

34

29

22

13

0

max

min

175

170

167

163

162

161

159

155

150

max

> 2.0

2.0

-

1.5

1.0

0.9

0.8

0.7

0.6

0.5

< 0.5

0

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Figure of Illustration of nominal slew rate and t_VACfor setup time t_ISfor CA and CS_n with respect to clock

V_REF(DC)- V_{IL(AC) max}

V_{IH(AC) min}- V_REF(DC)

Setup Slew Rate

Falling Signal

Setup Slew Rate

Rising Signal

=

△TF

△TR

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Figure of Illustration of nominal slew rate for hold time t_IHfor CA and CS_n with respect to clock

V_REF(DC)- V_{IL(DC) max}

V_{IH(DC) min}- V_REF(DC)

Hold Slew Rate

Rising Signal

Hold Slew Rate

Fallng Signal

=

△TR

△TF

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Figure of Illustration of tangent line for setup time t_ISfor CA and CS_n with respect to clock

tangent line [ V_{IH(AC) min}- V_REF(DC)

]

Setup Slew Rate

Rising Signal

=

△TR

tangent line [ V_REF(DC)- V_{IL(AC) max}

Setup Slew Rate

Fallng Signal

△TF

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Figure of Illustration of tangent line for for hold time t_IHfor CA and CS_n with respect to clock

tangent line [ V_REF(DC)- V_{IL(DC) max}

]

Hold Slew Rate

Rising Signal

=

△TR

tangent line [ V_{IH(DC) min}- V_REF(DC)

Hold Slew Rate

Fallng Signal

△TF

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Data Setup, Hold and Slew Rate Derating

For all input signals (DQ, DM), the total t_DS(setup time) and t_DH(hold time) required is calculated by adding the data sheet t_DS(base)

and t_DH(base)value to the △t_DSand △t_DHderating value respectively(see the series of tables following this section). Example: t_DS

(total setup time) = t_DS(base)+ △t_DS

.

Setup (t_DS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_REF(DC)and the first

crossing of V_{IH(AC), min}. Setup (t_DS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of

V_REF(DC)and the first crossing of V_{IL(AC), max}(see the Figure of “Illustration of nominal slew rate and t_VACfor setup time t_DSfor DQ

with respect to strobe”).

If the actual signal is always earlier than the nominal slew rate line between shaded ‘V_REF(DC)to AC region’, use nominal slew rate

for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded ‘V_REF(DC)to AC region’,

the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value (see the Figure of

“Illustration of tangent line for setup time t_DSfor DQ with respect to strobe”).

Hold (t_DH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V_{IL(DC), max}and the first

crossing of V_REF(DC). Hold (t_DH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of

V_IH(DC),minand the first crossing of V_REF(DC)(see the Figure of “Illustration of nominal slew rate for hold time t_DHfor DQ with respect

to strobe”).

If the actual signal is always later than the nominal slew rate line between shaded ‘DC level to V_REF(DC)region’, use nominal slew

rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to V_REF(DC)

region’, the slew rate of a tangent line to the actual signal from the DC level to V_REF(DC)level is used for derating value (see the

Figure of “Illustration of tangent line for hold time t_DHfor DQ with respect to strobe”).

For a valid transition the input signal has to remain above/below V_IH/V_IL(AC)for some time t_VAC(see the Table of “Required time

t_VACabove V_IH(AC){below V_IL(AC)} for valid transition”).

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V_IH/V_IL(AC)at the

time of the rising clock transition), a valid input signal is still required to complete the transition and reach V_IH/V_IL(AC)

.

For slew rates between the values listed in the tables, the derating values can be obtained by linear interpolation. These values

are typically not subject to production test. They are verified by design and characterization.

Table of Data Setup and Hold Base-Values for 1V/ns

LPDDR2

Unit [ps]

Reference

1066

-10

933

15

800

50

667

130

220

533

210

300

466

230

320

t_DS(base)

t_DH(base)

V_IH/V_IL(AC)= V_REF(DC)± 220mV

V_IH/V_IL(DC)= V_REF(DC)± 130mV

80

105

140

LPDDR2

Unit [ps]

Reference

400

180

280

333

300

400

266

450

550

200

700

800

t_DS(base)

t_DH(base)

V_IH/V_IL(AC)= V_REF(DC)± 300mV

V_IH/V_IL(DC)= V_REF(DC)± 200mV

Note: AC/DC referenced for 1V/ns DQ, DM slew rate and 2V/ns differential DQS_t / DQS_c slew rate.

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Table of Derating values LPDDR2 t_DS/t_DH- AC/DC based AC220

△t_DS, △t_DHderating in [ps] AC/DC based

AC220 Threshold -> V_IH(AC)= V_REF(DC)+220mV, V_IL(AC)= V_REF(DC)-220mV

DC130 Threshold -> V_IH(DC)= V_REF(DC)+130mV, V_IL(DC)= V_REF(DC)-130mV

DQS_t, DQS_c Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△t_DS△t_DH△t_DS△t_DH△t_DS△t_DH△t_DS△t_DH△t_DS△t_DH△t_DS△t_DH△t_DS△t_DH△t_DS△t_DH

2.0

1.5

110

74

65

43

110

73

65

43

110

73

65

43

89

16

59

16

1.0

0

32

0.9

0.8

0.7

0.6

0.5

0.4

-3

-5

-3

-8

-5

13

8

11

3

29

24

18

10

27

19

10

-3

45

40

34

26

4

43

35

26

13

-4

-13

56

50

42

20

-7

55

46

33

16

2

-6

66

58

36

17

78

65

48

34

Note: Cell contents shaded in blue are defined as ‘not supported’.

Table of Derating values LPDDR2 t_DS/t_DH- AC/DC based - AC300

△t_DS, △t_DHderating in [ps] AC/DC based

AC300 Threshold -> V_IH(AC)= V_REF(DC)+300mV, V_IL(AC)= V_REF(DC)-300mV

DC200 Threshold -> V_IH(DC)= V_REF(DC)+200mV, V_IL(DC)= V_REF(DC)-200mV

DQS_t, DQS_c Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH△t_IS△t_IH

2.0

1.5

150 100 150 100 150 100

100

0

67

0

100

0

67

0

100

67

116

16

83

16

1.0

0

32

0.9

0.8

0.7

0.6

-4

-8

-4

-8

12

4

8

28

20

13

2

24

12

-2

44

36

29

18

-12

40

28

14

-5

-12

-20

-4

52

45

34

4

48

34

-3

-18

61

50

66

47

20

-8

-21

15

0.5

0.4

-32

-12

-40

20

-35

-11

Note: Cell contents shaded in blue are defined as ‘not supported’.

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Table of Required time t_VACabove V_IH(AC){below V_IL(AC)} for valid transition

t_VAC@ 300mV [ps]

t_VAC@ 220mV [ps]

Slew Rate [V/ns]

min

75

57

50

38

34

29

22

13

0

max

min

175

170

167

163

162

161

159

155

150

max

> 2.0

2.0

-

1.5

1.0

0.9

0.8

0.7

0.6

0.5

< 0.5

0

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Figure of Illustration of nominal slew rate and t_VACfor setup time t_DSfor DQ with respect to strobe

V_REF(DC)- V_{IL(AC) max}

V_{IH(AC) min}- V_REF(DC)

Setup Slew Rate

Falling Signal

Setup Slew Rate

Rising Signal

=

△TF

△TR

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Figure of Illustration of nominal slew rate for hold time t_DHfor DQ with respect to strobe

V_REF(DC)- V_{IL(DC) max}

V_{IH(DC) min}- V_REF(DC)

Hold Slew Rate

Rising Signal

Hold Slew Rate

Fallng Signal

=

△TR

△TF

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Figure of Illustration of tangent line for setup time t_DSfor DQ with respect to strobe

tangent line [ V_{IH(AC) min}- V_REF(DC)

]

Setup Slew Rate

Rising Signal

=

△TR

tangent line [ V_REF(DC)- V_{IL(AC) max}

Setup Slew Rate

Fallng Signal

△TF

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Figure of Illustration of tangent line for for hold time t_DHfor DQ with respect to strobe

tangent line [ V_REF(DC)- V_{IL(DC) max}

Hold Slew Rate

]

=

Rising Signal

△TR

tangent line [ V_{IH(DC) min}- V_REF(DC)

Hold Slew Rate

=

Fallng Signal

△TF

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Functional Description

LPDDR2 devices use double data rate archiecture on the Command/Address (CA) bus to reduce the number of input pins in the

system. The 10-bit CA bus contains command, address, and bank information. Each command uses one clock cycle, during

which command information is transferred on both the positive and negative edge of the clock.

LPDDR2-S4 devices use double data rate architecture on the DQ pins to achieve high speed operation. The double data rate

architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle

at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a single 4n-bit-wide, one-clock-cycle data

transfer at the internal SDRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses are burst oriented; accesses start at a selected location and continue for a programmed number of

locations in a programmed sequence.

For LPDDR2-S4 devices, accesses begin with the registration of an Activate command, which is then followed by a Read or

Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the

Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and

the starting column location for the burst access.

Prior to normal operation, the LPDDR2 device must be initialized. The following section provides detailed information covering

device initialization, register definition, command description and device operation.

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Power Up, Initialization, and Power Off

The LPDDR2 Devices must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation.

Power Ramp and Device Initialization

The following sequence shall be used to power up an LPDDR2 device. Unless specified otherwise, these steps are mandatory.

1. Power Ramp

While applying power (after Ta), CKE shall be held at a logic low level (=<0.2 x V_DDCA), all other inputs shall be between V_{IL min}

and V_IHmax. The device will only guarantee that outputs are in a high impedance state while CKE is held low.

On or before the completion of the power ramp (Tb), CKE must be held low. DQ, DM, DQS_t and DQS_c voltage levels must be

between V_SSQand V_DDQduring voltage ramp to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be between V_SSCA

and V_DDCAduring voltage ramp to avoid latchup.

The following conditions apply:



Ta is the point when any power supply first reaches 300mV.

Noted conditions apply between Ta and power down (controlled or uncontrolled).

Tb is the point at which all supply and reference voltages are within their defined operating ranges.

Power ramp duration t_INIT0(Tb - Ta) must not exceed 20ms.

For supply and reference voltage operating conditions, see the Table of “Recommended DC Operating Conditions”.

The voltage difference between any of V_SS, V_SSQ, and V_SSCApins must not exceed 100mV.

Power Ramp Completion

After Ta is reached:



V_DD1must be greater than V_DD2- 200mV.

V_DD1and V_DD2must be greater than V_DDCA- 200mV.

V_DD1and V_DD2must be greater than V_DDQ- 200mV.

V_REFmust always be less than all other supply voltages.

2. CKE and Clock

Beginning at Tb, CKE must remain low for at least t_INIT1= 100 ns, after which it may be asserted high. Clock must be stable at

least t_INIT2= 5 x t_CKprior to the first low to high transition of CKE (Tc). CKE, CS_n and CA inputs must observe setup and hold

time (t_IS, t_IH) requirements with respect to the first rising clock edge (as well as to the subsequent falling and rising edges).

The clock period shall be within the range defined for t_CKb(18ns to 100ns), if any Mode Register Reads are performed. Mode

Register Writes can be sent at normal clock operating frequencies so long as all AC Timings are met. Furthermore, some AC

parameters (e.g. t_DQSCK) may have relaxed timings (e.g. t_DQSCKb) before the system is appropriately configured.

While keeping CKE high, issue NOP commands for at least t_INIT3= 200us. (Td).

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3. Reset command

After t_INIT3is satisfied, a MRW (Reset) command shall be issued (Td). The memory controller may optionally issue a

Precharge-All command prior to the MRW Reset command. Wait for at least t_INIT4= 1us while keeping CKE asserted and issuing

NOP commands.

4. Mode Registers Reads and Device Auto-Initialization (DAI) polling

After t_INIT4is satisfied (Te), only MRR commands and power down entry/exit commands are allowed. Therefore, after Te, CKE

may go low in accordance to power down entry and exit specification. (See “Power Down” section)

The MRR command may be used to poll the DAI bit to acknowledge when device auto-Initialization is complete or the memory

controller shall wait a minimum of t_INIT5before proceeding.

As the memory output buffers are not properly configured yet, some AC parameters may have relaxed timings before the system

is appropriately configured.

After the DAI bit (MR0, “DAI”) is set to zero ”DAI complete” by the memory device, the device is in idle state (Tf). The state of the

DAI status bit can be determined by an MRR command to MR0.

The device will set the DAI bit no later than t_INIT5after the RESET command. The memory controller shall wait a minimum of t_INIT5

or until the DAI bit is set before proceeding.

After the DAI bit is set, it is recommended to determine the device type and other device characteristics by issuing MRR

commands (MR0 “Device Information” etc.).

5. ZQ Calibration

After t_INIT5(Tf), an MRW ZQ Initialization Calibration command may be issued to the memory (MR10).

This command is used to calibrate the LPDDR2 output drivers (R_ON) over process, voltage, and temperature variations.

Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate R_ZQpin connection. In systems in which

more than one LPDDR2 device exists on the same bus, the controller must not overlap ZQ Calibration commands. The device is

ready for normal operation after t_ZQINIT

.

6. Normal Operation

After t_ZQINIT(Tg), MRW commands may be used to properly configure the memory (for example the output buffer driver strength,

latencies, etc). Specifically, MR1, MR2, and MR3 shall be set to configure the memory for the target frequency and memory

configuration.

The LPDDR2 device will now be in IDLE state and ready for any valid command.

After Tg, the clock frequency may be changed according to the clock frequency change procedure described in “Input clock stop

and frequency change” section.

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Table of Timing Parameters for initialization

Value

Symbol

Unit

Comment

Maximum Power Ramp Time

min

max

t_INIT0

t_INIT1

t_INIT2

t_INIT3

t_INIT4

t_INIT5

t_ZQINIT

t_CKb

20

ms

ns

t_CK

us

ns

100

5

Minimum CKE low time after completion of power ramp

Minimum stable clock before first CKE high

Minimum Idle time after first CKE assertion

Minimum Idle time after Reset command

Maximum duration of Device Auto-Initialization

ZQ Initial Calibration for LPDDR2-S4

200

1

10

1

18

100

Clock cycle time during boot

Figure of Power Ramp and Initialization Sequence

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Initialization after Reset (without Power ramp)

If the RESET command is issued outside the power up initialization sequence, the reinitialization procedure shall begin with step

3 (Td).

Power Off Sequence

While removing power, CKE shall be held at a logic low level (=< 0.2 x V_DDCA), all other inputs shall be between V_{IL min}and V_{IH max}

.

The device will only guarantee that outputs are in a high impedance state while CKE is held low.

DQ, DM, DQS_t and DQS_c voltage levels must be between V_SSQand V_DDQduring power off sequence to avoid latchup. CK_t,

CK_c, CS_n and CA input levels must be between V_SSCAand V_DDCAduring power off sequence to avoid latchup.

Tx is the point where any power supply decreases under its minimum value specified in the Table of “Recommended DC

Operating Conditions”.

Tz is the point where all power supplies are below 300 mV. After Tz, the device is powered off.

The time between Tx and Tz (t_POFF) shall be less than 2s.

The following conditions apply between Tx and Tz:



V_DD1must be greater than V_DD2- 200 mV.

V_DD1and V_DD2must be greater than V_DDCA- 200 mV.

V_DD1and V_DD2must be greater than V_DDQ- 200 mV.

V_REFmust always be less than all other supply voltages.

The voltage difference between any of V_SS, V_SSQ, and V_SSCApins may not exceed 100 mV.

For supply and reference voltage operating conditions, see the Table of “Recommended DC Operating Conditions”.

Table of Timing Parameters Power Off

Value

Symbol

Unit

Comment

Maximum power off ramp time

min

max

t_POFF

2

s

Uncontrolled Power Off Sequence

The following sequence shall be used to power off the LPDDR2 device under uncontrolled condition.



Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition table.

After turning off all power supplies, any power supply current capacity must be zero, except for any static charge remaining

in the system.



Tz is the point where all power supply first reaches 300 mV. After Tz, the device is powered off. The time between Tx and

Tz shall be less than t_POFF. The relative voltage between supply voltages is uncontrolled during this period. V_DD1and V_DD2

shall decrease with a slope lower than 0.5 V/us between Tx and Tz.

Uncontrolled power off sequence can be applied only up to 400 times in the life of the device.

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Mode Register Definition

Mode Register Assignment and Definition

Each register is denoted as “R” if it can be read but not written, “W” if it can be written but not read, and “R/W” if it can be read and

written.

Mode Register Read command is used to read a register. Mode Register Write command is used to write a register.

Table of Mode Register Assignment ^*1~5

MR#

MA [7:0]

00h

Function

Device Info.

Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0

Link

0

1

2

3

R

(RFU)

nWR (for AP)

(RFU)

RZQI

WC BT

DNVI

DI

DAI

go to MR0

go to MR1

go to MR2

go to MR3

01h

Device Feature 1

Device Feature 2

I/O Config-1

W

BL

02h

RL & WL

DS

03h

(RFU)

SDRAM Refresh

Rate

4

04h

R

TUF

(RFU)

Refresh Rate

go to MR4

5

05h

06h

Basic Config-1

Basic Config-2

Basic Config-3

Basic Config-4

Test Mode

R

LPDDR2 Manufacturer ID

Revision ID1

go to MR5

go to MR6

go to MR7

go to MR8

go to MR9

go to MR10

go to MR11

6

7

8

07h

R

Revision ID2

08h

R

I/O width

Density

Type

9

09h

W

Vendor-Specific Test Mode

Calibration Code

(RFU)

10

0Ah

I/O Calibration

(Reserved)

11~15

0Bh~0Fh

16

10h

11h

PASR_Bank

PASR_Seg

(Reserved)

W

Bank Mask

Segment Mask

(RFU)

go to MR16

go to MR17

go to MR18

MR20~MR30

17

18~19

20~31

12h~13h

14h~1Fh

Reserved for NVM

DQ Calibration

Pattern A

32

33:39

40

20h

21h~27h

28h

R

See “DQ Calibration” section

go to MR32

go to MR33

go to MR40

(Do Not Use)

DQ Calibration

Pattern B

See “DQ Calibration” section

41:47

48:62

63

29h~2Fh

30h~3Eh

3Fh

(Do Not Use)

(Reserved)

Reset

go to MR41

go to MR48

go to MR63

go to MR64

go to MR127

go to MR128

go to MR191

go to MR192

go to MR255

(RFU)

X

W

64:126 40h~7Eh

127 7Fh

128:190 80h~BEh

191 BFh

(Reserved)

(Do Not Use)

(RFU)

(Reserved for vendor use)

(Do Not Use)

(RFU)

192:254 C0h~FEh (Reserved for vendor use)

255

FFh

(Do Not Use)

Notes:

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1. RFU bits must be set to ‘0‘ during Mode Register Write.

2. RFU bits must be read as ‘0‘ during Mode Register Read.

3. All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS_t, DQS_c shall

be toggled.

4. All Mode Registers that are specified as RFU shall not be written.

5. Writes to read-only registers shall have no impact on the functionality of the device.

MR0_Device Information (MA[7:0] = 00h) ^*1~4

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

(RFU)

RZQI

DNVI

DI

DAI

0b: DAI complete

1b: DAI still in progress

DAI (Device

Auto-Initialization Status)

Read-only

OP0

OP1

OP2

0b: S2 or S4 SDRAM

1b: NVM

DI (Device Information)

DNVI (Data Not Valid

Information)

0b: DNVI not supported

00b: R_ZQself test not supported

01b: ZQ pin may connect to V_DDCAor float

10b: ZQ pin may short to GND

RZQI (Built in Self Test for

R_ZQInformation)

Read-only

OP[4:3]

11b: ZQ pin self test completed, no error condition detected

(ZQ pin may not connect to V_DDCAor float nor short to

GND)

Notes:

1. If RZQI is supported, it will be set upon completion of the MRW ZQ Initialization Calibration command.

2. If ZQ is connected to V_DDCAto set default calibration, OP[4:3] must be set to 01. If ZQ is not connected to V_DDCA, either

OP[4:3]=01 or OP[4:3]=10 might indicate a ZQ pin assembly error. It is recommended that the assembly error is corrected.

3. In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 as defined above), the device will default to factory

trim settings for R_ONand will ignore ZQ calibration commands. In either case, the system may not function as intended.

4. In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a resistor connection

to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor tolerance meets

the specified limits (i.e. 240ohm +/-1%).

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MR1_Device Feature 1 (MA[7:0] = 01h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

nWR (for AP)

WC

BT

BL

010b: BL4 (default)

011b: BL8

BL (Burst Length)

Write-only

OP[2:0]

100b: BL16

All others: reserved

0b: Sequential (default)

1b: Interleaved

BT (Burst Type)

Write-only

OP3

OP4

0b: Wrap (default)

1b: No wrap

WC (Wrap Control)

001b: nWR=3 (default)

010b: nWR=4

011b: nWR=5

nWR (Number of t_WRClock

Cycles) ^*1

100b: nWR=6

Write-only

OP[7:5]

101b: nWR=7

110b: nWR=8

All others: reserved

Notes:

1. Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge

operation for a write burst with AP enabled. It is determined by RU(t_WR/t_CK).

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Table of Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC)^*1~5

Burst Cycle Number and Burst Address Sequence

BL BT C3 C2 C1 C0 WC

1

0

2

y

2

1

3

2

0

4

3

1

5

6

7

8

9

10 11 12 13 14 15 16

X

0b 0b

1b 0b

wrap

nw

4

any

seq

X

0b

y+1 y+2 y+3

0b 0b 0b

0b 1b 0b

1b 0b 0b

1b 1b 0b

0b 0b 0b

0b 1b 0b

1b 0b 0b

1b 1b 0b

0

2

4

6

0

2

4

6

1

3

5

7

1

3

5

7

2

4

6

0

2

0

6

4

3

5

7

1

3

1

7

5

4

6

0

2

4

6

0

2

5

7

1

3

5

7

1

3

6

0

2

4

6

4

2

0

7

1

3

5

7

5

3

1

wrap

nw

8

int

illegal (not allowed)

any

X

0b

0b 0b 0b 0b

0b 0b 1b 0b

0b 1b 0b 0b

0b 1b 1b 0b

0

2

1

3

5

7

9

B

D

F

2

4

3

5

7

9

B

D

F

1

4

6

5

7

9

B

D

F

1

3

6

8

7

9

B

D

F

1

3

5

8

A

C

E

0

9

B

D

F

1

3

5

7

A

C

E

0

2

4

6

8

B

D

F

1

3

5

7

9

C

E

0

2

4

6

8

A

D

F

1

3

5

7

9

B

E

0

2

4

6

8

A

C

F

1

3

5

7

9

B

D

4

6

8

A

C

E

0

6

8

A

C

E

0

seq

1b 0b 0b 0b wrap

1b 0b 1b 0b

8

A

C

E

0

16

A

C

E

2

1b 1b 0b 0b

2

4

1b 1b 1b 0b

2

4

6

illegal (not allowed)

int

X

0b

any

nw

Notes:

1. C0 input is not present on CA bus. It is implied zero.

2. For BL=4, the burst address represents C[1: 0].

3. For BL=8, the burst address represents C[2:0].

4. For BL=16, the burst address represents C[3:0].

5. For no-wrap (nw), BL4, the burst must not cross the page boundary or sub-page boundary. The variable y may start at any

address with C0 equal to 0 and must not start at any address in table below for the respective density and bus width

combinations.

Table of Non Wrap Restrictions

1Gb

Not across full page boundary

x16

3FE, 3FF, 000, 001

Not across sub-page boundary

1FE, 1FF, 200, 201

Note: Non-wrap BL=4 data orders shown above are prohibited.

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MR2_Device Feature 2 (MA[7:0] = 02h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

(RFU)

RL & WL

0001b: RL = 3 / WL = 1 (default)

0010b: RL = 4 / WL = 2

0011b: RL = 5 / WL = 2

0100b: RL = 6 / WL = 3

0101b: RL = 7 / WL = 4

0110b: RL = 8 / WL = 4

All others: reserved

RL & WL

Write-only

OP[3:0]

MR3_I/O Configuration 1 (MA[7:0] = 03h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

(RFU)

DS

0000b: reserved

0001b: 34.3 ohm typical

0010b: 40 ohm typical (default)

0011b: 48 ohm typical

0100b: 60 ohm typical

0101b: reserved

DS

Write-only

OP[3:0]

0110b: 80-ohm typical

0111b: 120-ohm typical (optional)

All others: reserved

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MR4_Device Temperature (MA[7:0] = 04h) ^*1~8

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

TUF

(RFU)

SDRAM Refresh Rate

000b: SDRAM Low temperature operating limit exceeded

001b: 4x t_REFI, 4x t_REFIpb, 4x t_REFW

010b: 2x t_REFI, 2x t_REFIpb, 2x t_REFW

011b: 1x t_REFI, 1x t_REFIpb, 1x t_REFW(<=85 ℃)

100b: Reserved

SDRAM Refresh Rate

Read-only

OP[2:0]

OP[7]

101b: 0.25x t_REFI, 0.25x t_REFIpb, 0.25x t_REFW, do not derate

SDRAM AC timing

110b: 0.25x t_REFI, 0.25x t_REFIpb, 0.25x t_REFW, derate SDRAM

AC timing

111b: SDRAM High temperature operating limit exceeded

0b: OP[2:0] value has not changed since last read of MR4.

1b: OP[2:0] value has changed since last read of MR4.

Temperature Update Flag

(TUF)

Notes:

1. A Mode Register Read from MR4 will reset OP7 to ‘0’.

2. OP7 is reset to ‘0’ at power up. OP[2:0] bits are undefined after power up.

3. If OP2 equals ‘1’, the device temperature is greater than 85 ℃.

4. OP7 is set to ‘1’ if OP[2:0] has changed at any time since the last read of MR4.

5. The device might not operate properly when OP[2:0] = 000b or 111b.

6. For specified operating temperature range and maximum operating temperature refer to the Table of “Operating

Temperature Range”.

7. The devices shall be derated by adding 1.875 ns to the following core timing parameters: t_RCD, t_RC, t_RAS, t_RP, and t_RRD. t_DQSCK

must be derated according to the t_DQSCKderating in the Table of “AC timing”. Prevailing clock frequency specifications and

related setup and hold timings shall remain unchanged.

8. The recommended frequency for reading MR4 is provided in “Temperature Sensor” section.

MR5_Basic Configuration 1 (MA[7:0] = 05h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

LPDDR2 Manufacturer ID

0000 1001b

LPDDR2 Manufacturer ID

Read-only

OP[7:0]

MR6_Basic Configuration 2 (MA[7:0] = 06h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Revision ID1

0000 0000b: A-version

Revision ID1

Read-only

OP[7:0]

Note: MR6 is vendor-specific.

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MR7_Basic Configuration 3 (MA[7:0] = 07h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Revision ID2

0000 0000b: A-version

Revision ID2

Read-only

OP[7:0]

Note: MR7 is vendor-specific.

MR8_Basic Configuration 4 (MA[7:0] = 08h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

I/O width

Density

Type

00b: S4 SDRAM

0100b: 1Gb

Type

Read-only

OP[1:0]

OP[5:2]

Density

00b: x32

01b: x16

I/O width

Read-only

OP[7:6]

MR9_Test Mode (MA[7:0] = 09h)

OP7 OP6

OP5

OP4

OP3

OP2

OP1

OP0

Vendor-specific Test Mode

MR10_Calibration (MA[7:0] = 0Ah) ^*1~4

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Calibration Code

0xFF: Calibration command after initialization

0xAB: Long calibration

0x56: Short calibration

Calibration Code

Notes:

Write-only

OP[7:0]

0xC3: ZQ Reset

others: Reserved

1. Host processor must not write MR10 with “Reserved” values.

2. The device ignores calibration commands when a “Reserved” value is written into MR10.

3. See the Table of “AC timing” for the calibration latency.

4. If ZQ is connected to V_SSCAthrough R_ZQ, either the ZQ calibration function (see “Mode Register Write ZQ Calibration

Command” section) or default calibration (through the ZQreset command) is supported. If ZQ is connected to V_DDCA, the

device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection must

not change after power is applied to the device.

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MR16_PASR_Bank Mask (MA[7:0] = 10h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Bank Mask (8-bank)

0b: refresh enable to the bank (=unmasked, default)

1b: refresh blocked (=masked)

Bank [7:0] Mask

Write-only

OP[7:0]

OP

0

Bank Mask

XXXXXXX1

XXXXXX1X

XXXXX1XX

XXXX1XXX

XXX1XXXX

XX1XXXXX

X1XXXXXX

1XXXXXXX

8-Bank SDRAM

Bank 0

Bank 1

1

Bank 2

2

Bank 3

3

Bank 4

4

Bank 5

5

Bank 6

6

Bank 7

7

MR17_PASR_Segment Mask (MA[7:0] = 11h)

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

Segment mask

0b: refresh enable to the segment (=unmasked, default)

1b: refresh blocked (=masked)

Segment [7:0] Mask

Write-only

OP[7:0]

Segment

OP

0

Segment Mask

XXXXXXX1

R12:10

000b

001b

010b

011b

100b

101b

110b

111b

0

1

2

3

4

5

6

7

1

XXXXXX1X

XXXXX1XX

XXXX1XXX

XXX1XXXX

XX1XXXXX

X1XXXXXX

1XXXXXXX

2

3

4

5

6

7

Note: X is “Don’t Care” for the designated segment.

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MR32_DQ Calibration Pattern A (MA[7:0] = 20h)

Reads to MR32 return DQ Calibration Pattern “A”. See “DQ Calibration” section.

MR40_DQ Calibration Pattern B (MA[7:0] = 28h)

Reads to MR40 return DQ Calibration Pattern “B”. See “DQ Calibration” section.

MR63_Reset (MA[7:0] = 3Fh): MRW only

OP7

OP6

OP5

OP4

OP3

OP2

OP1

OP0

X

Note: For additional information on MRW RESET, see “Mode Register Write Command” section.

Table of Reserved Mode Registers

Mode Register

MR[11:15]

MR[18:19]

MR[20:31]

MR[33:39]

MR[41:47]

MR[48:62]

MR[64:126]

MR127

MA

Address

0Bh-0Fh

12h–13h

14h–1Fh

21h–27h

29h–2Fh

30h–3Eh

40h–7Eh

7Fh

Restriction

RFU

OP[7:0]

RFU

NVM (DNU)

DNU

RFU

MA[7:0]

Reserved

RFU

DNU

MR[128:190]

MR191

80h–BEh

BFh

RVU

DNU

MR[192:254]

MR255

C0h–FEh

FFh

RVU

DNU

Note: NVM = nonvolatile memory use only; DNU = Do not use; RVU = Reserved for vendor use.

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Command Definitions and Timing Diagram

Activate Command

The Activate command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at the rising edge of the clock. The bank

addresses are used to select the desired bank. The row addresses are used to determine which row to activate in the selected

bank. The Activate command must be applied before any Read or Write operation can be executed. The device can accept a

read or write command at time t_RCDafter the activate command is sent. Once a bank has been activated it must be precharged

before another Activate command can be applied to the same bank. The bank active and precharge times are defined as t_RASand

t_RP, respectively. The minimum time interval between successive Activate commands to the same bank is determined by the RAS

cycle time of the device (t_RC). The minimum time interval between Activate commands to different banks is t_RRD

.

Certain restrictions on operation of the 8-bank devices must be observed. There are two rules. One for restricting the number of

sequential Activate commands that can be issued and another for allowing more time for RAS precharge for a Precharge All

command. The rules are as follows:



8-bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated (or refreshed, in the case of

REFpb) in a rolling t_FAWwindow. Converting to clocks is done by dividing t_FAW[ns] by t_CK[ns], and rounding up to next

integer value. As an example of the rolling window, if RU{ (t_FAW/ t_CK) } is 10 clocks, and an activate command is issued in

clock N, no more than three further activate commands may be issued at or between clock N+1 and N+9. REFpb also

counts as bank-activation for the purposes of t_FAW

.

8-bank device Precharge All Allowance: t_RPfor a Precharge All command for an 8-bank device shall equal t_RPab, which is

greater than t_RPpb

.

Figure of Activate command cycle: t_RCD=3, t_RP=3, t_RRD=2

Note: A Precharge-All command uses t_RPabtiming, while a Single Bank Precharge command uses t_RPpbtiming. In this figure, t_RPis

used to denote either an All-bank Precharge or a Single Bank Precharge

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Figure of t_FAWtiming

Note: For 8-bank devices only.

Command Input Signal Timing Definition

Figure of Command Input Setup and Hold Timing

Note: Setup and hold conditions also apply to the CKE pin. See section related to power down for timing diagrams related to the

CKE pin.

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Figure of CKE Input Setup and Hold Timing

Notes:

1. After CKE is registered LOW, CKE signal level must be maintained below V_ILCKEfor t_CKEspecification (LOW pulse width).

2. After CKE is registered HIGH, CKE signal level must be maintained above V_IHCKEfor t_CKEspecification (HIGH pulse width)

Read and Write access modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting CS_n LOW, CA0 HIGH,

and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine whether the access cycle is a

READ operation (CA2 HIGH) or a WRITE operation (CA2 LOW).

The device provides a fast column access operation. A single Read or Write Command initiates a burst read or write operation on

successive clock cycles.

A new burst access must not interrupt the previous 4-bit burst operation in case of BL = 4 setting. In case of BL = 8 and BL = 16

settings, Reads may be interrupted by Reads and Writes may be interrupted by Writes, provided that this occurs on even clock

cycles after the Read or Write command and t_CCDis met.

Burst Read command

The Burst Read command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising edge of the clock.

The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst. The Read

Latency (RL) is defined from the rising edge of the clock on which the Read Command is issued to the rising edge of the clock

from which the t_DQSCKdelay is measured. The first valid datum is available RL * t_CK+ t_DQSCK+ t_DQSQafter the rising edge of the

clock where the Read Command is issued. The data strobe output is driven LOW t_RPREbefore the first rising valid strobe edge.

The first bit of the burst is synchronized with the first rising edge of the data strobe. Each subsequent data-out appears on each

DQ pin edge aligned with the data strobe. The RL is programmed in the mode registers.

Timings for the data strobe are measured relative to the crosspoint of DQS_t and its complement, DQS_c.

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Figure of Data output (read) timing (t_{DQSCK max}

)

Notes:

1. t_DQSCKmay span multiple clock periods.

2. An effective Burst Length of 4 is shown

Figure of Data output (read) timing (t_{DQSCK min}

)

Note: An effective Burst Length of 4 is shown

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Figure of Burst read: RL = 5, BL = 4, t_DQSCK> t_CK

Figure of Burst read: RL = 3, BL = 8, t_DQSCK< t_CK

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Figure of t_DQSCKDLtiming

Note: t_{DQSCKDL, max}is defined as the maximum of ABS (t_DQSCKn- t_DQSCKm) for any {t_DQSCKn, t_DQSCKm} pair within any 32ms rolling

window.

Figure of t_DQSCKDMtiming

Note: t_{DQSCKDM, max}is defined as the maximum of ABS (t_DQSCKn- t_DQSCKm) for any {t_DQSCKn, t_DQSCKm} pair within any 1.6us rolling

window.

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Figure of t_DQSCKDStiming

Note: t_{DQSCKDS, max}is defined as the maximum of ABS (t_DQSCKn- t_DQSCKm) for any {t_DQSCKn, t_DQSCKm} pair for reads within a

consecutive burst within any 160ns rolling window.

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Figure of Burst read followed by burst write: RL = 3, WL = 1, BL = 4

The minimum time from the burst read command to the burst write command is defined by the Read Latency (RL) and the Burst

Length (BL). Minimum read to write latency is RL + RU (t_{DQSCK, max}/ t_CK) + BL/2 + 1 - WL clock cycles. Note that if a read burst is

truncated with a Burst Terminate (BST) command, the effective burst length of the truncated read burst should be used as “BL” to

calculate the minimum read to write delay.

Figure of Seamless burst read: RL = 3, BL= 4, t_CCD= 2

The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, every 4th

clocks for BL = 8 operation, and every 8th clocks for BL=16 operation. This operation is allowed regardless of whether the

accesses read the same or different banks as long as the banks are activated.

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Reads interrupted by a read

A burst read can be interrupted by another read on even clock cycles after the Read command, provided that t_CCDis met.

Figure of Read burst interrupt example: RL = 3, BL= 8, t_CCD= 2

Notes:

1. Read burst interrupt function is only allowed on burst of 8 and burst of 16.

2. Read burst interrupt may only occur on even clock cycles after the previous commands, provided that t_CCDis met.

3. Reads can only be interrupted by other reads or the BST command.

4. Read burst interruption is allowed to any bank inside DRAM.

5. Read burst with Auto-Precharge is not allowed to be interrupted.

6. The effective burst length of the first read equals two times the number of clock cycles between the first read and the

interrupting read.

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Burst Write operation

The Burst Write command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 LOW at the rising edge of the clock.

The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst. The Write

Latency (WL) is defined from the rising edge of the clock on which the Write Command is issued to the rising edge of the clock

from which the t_DQSSdelay is measured. The first valid data must be driven WL * t_CK+ t_DQSSfrom the rising edge of the clock from

which the Write command is issued. The data strobe signal (DQS) must be driven LOW t_WPREprior to the data input. The data bits

of the burst cycle must be applied to the DQ pins t_DSprior to the respective edge of the DQS and held valid until t_DHafter that

edge. The burst data is sampled on successive edges of the DQS until the burst length is completed, which is 4, 8, or 16 bit burst.

t_WRmust be satisfied before a precharge command to the same bank may be issued after a burst write operation.

Input timings are measured relative to the crosspoint of DQS_t and its complement, DQS_c.

Figure of Data input (write) timing

Figure of Burst write: WL = 1, BL= 4

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Figure of Burst write followed by burst read: RL = 3, WL= 1, BL=4

Notes:

1. The minimum number of clock cycles from the burst write command to the burst read command for any bank is [WL + 1 +

BL/2 + RU( t_WTR/ t_CK)].

2. t_WTRstarts at the rising edge of the clock after the last valid input datum.

3. If a write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated write burst

should be used as “BL” to calculate the minimum write to read delay.

Figure of Seamless burst write: WL= 1, BL=4, t_CCD=2

Note: The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every

four clocks for BL = 8 operation, or every eight clocks for BL=16 operation. This operation is allowed regardless of same or

different banks as long as the banks are activated.

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Writes interrupted by a write

A burst writes can only be interrupted by another write on even clock cycles after the write command, provided that t_CCD(min)is

met.

Figure of Write burst interrupt timing: WL= 1, BL= 8, t_CCD= 2

Notes:

1. Write burst interrupt function is only allowed on burst of 8 and burst of 16.

2. Write burst interrupt may only occur on even clock cycles after the previous write commands, provided that t_CCD(min)is met.

3. Writes can only be interrupted by other writes or the BST command.

4. Write burst interruption is allowed to any bank inside DRAM.

5. Write burst with Auto-Precharge is not allowed to be interrupted.

6. The effective burst length of the first write equals two times the number of clock cycles between the first write and the

interrupting write.

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Burst Terminate

The Burst Terminate (BST) command is initiated by having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 LOW at the

rising edge of clock. A Burst Teminate command can only be issued to terminate an active Read or Write burst. Therefore, a

Burst Terminate command can only be issued up to and including BL/2 - 1 clock cycles after a Read or Write command. The

effective burst length of a Read or Write command truncated by a BST command is as follows:



Effective burst length = 2 x {Number of clock cycles from the Read or Write Command to the BST command}

If a read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated burst

should be used as “BL” to calculate the minimum read to write or write to read delay.



The BST command only affects the most recent read or write command. The BST command truncates an ongoing read

burst RL * t_CK+ t_DQSCK+ t_DQSQafter the rising edge of the clock where the Burst Terminate command is issued. The BST

command truncates an on going write burst WL * t_CK+ t_DQSSafter the rising edge of the clock where the Burst Terminate

command is issued.



The 4-bit prefetch architecture allows the BST command to be issued on an even number of clock cycles after a Write or

Read command. Therefore, the effective burst length of a Read or Write command truncated by a BST command is an

integer multiple of 4.

Figure of Write burst truncated by BST: WL= 1, BL = 16

Notes:

1. The BST command truncates an ongoing write burst WL * t_CK+ t_DQSSafter the rising edge of the clock where the Burst

Terminate command is issued.

2. Additional BST commands are not allowed after T4 and must not be issued until after the next Read or Write command.

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Figure of Burst Read truncated by BST: RL= 3, BL=16

Notes:

1. The BST command truncates an ongoing read burst RL * t_CK+ t_DQSCK+ t_DQSQafter the rising edge of the clock where the

Burst Terminate command is issued.

2. BST can only be issued at even number of clock cycles after the Read command.

3. Additional BST commands are not allowed after T4 and may not be issued until after the next Read or Write command.

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Write data mask

One write data mask (DM) pin for each data byte (DQ) is supported on LPDDR2 devices, consistent with the implementation on

LPDDR SDRAMs. Each data mask (DM) can mask its respective data byte (DQ) for any given cycle of the burst. Data mask has

identical timings on write operations as the data bits, though used as input only, is internally loaded identically to data bits to

ensure matched system timing.

Figure of Write data mask

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Precharge operation

The Precharge command is used to precharge or close a bank that has been activated. The Precharge command is initiated by

having CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The Precharge Command

can be used to precharge each bank independently or all banks simultaneously. For 8-bank devices, the AB flag and the bank

address bits, BA0, BA1, and BA2, are used to determine which bank(s) to precharge. The bank(s) will be available for a

subsequent row access t_RPabafter an All-Bank Precharge command is issued and t_RPpbafter a Single-Bank Precharge command

is issued.

In order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank devices, the Row

Precharge time (t_RP) for an All-Bank Precharge for 8-bank devices (t_RPab) will be longer than the Row Precharge time for a

Single-Bank Precharge (t_RPpb).

Figure of “Activate command cycle: t_RCD=3, t_RP=3, t_RRD=2” shows Activate to Precharge timing.

Table of Bank selection for Precharge by address bits

Precharged Bank(s)

AB (CA4r)

BA2 (CA9r)

BA1 (CA8r)

BA0 (CA7r)

8-bank device

Bank 0 only

Bank 1 only

Bank 2 only

Bank 3 only

Bank 4 only

Bank 5 only

Bank 6 only

Bank 7 only

All Banks

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DON’T CARE

Burst Read operation followed by Precharge

For the earliest possible precharge, the precharge command may be issued BL/2 clock cycles after a Read command. For an

untruncated burst, BL is the value from the Mode Register. For a truncated burst, BL is the effective burst length. A new bank

active command can be issued to the same bank after the Row Precharge time (t_RP). A precharge command cannot be issued

until after t_RASis satisfied.

The minimum Read to Precharge timing (t_RTP) must also satisfy a minimum analog time from the rising clock edge that initiates

the last 4-bit prefetch of a Read command.

t_RTPbegins BL/2 - 2 clock cycles after the Read command. If the burst is truncated by a BST command or a Read command to a

different bank, the effective BL is used to calculate when t_RTPbegins.

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Figure of Burst read followed by Precharge: RL= 3, BL=8, RU( t_RTP(min)/ t_CK) = 2

Figure of Burst read followed by Precharge: RL= 3, BL=4, RU( t_RTP(min)/ t_CK)=3

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Burst Write followed by Precharge

For write cycles, a delay must be satisfied from the time of the last valid burst input data until the Precharge command may be

issued. This delay is known as the write recovery time (t_WR) referenced from the completion of the burst write to the precharge

command. No Precharge command can be issued prior to the t_WRdelay.

These devices write data to the array in prefetch quadruples (prefetch = 4). The beginning of an internal write operation may only

begin after a prefetch group has been latched completely.

The minimum Write to Precharge time for command to the same bank is WL + BL/2 + 1 + RU( t_WR/ t_CK) clock cycles. For an

untruncated burst, BL is the value from the Mode Register. For a truncated burst, BL is the effective burst length.

Figure of Burst write followed by precharge: WL = 1, BL= 4

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Auto Precharge operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or

the auto-precharge function. When a Read or a Write command is given to the device, the AP bit (CA0f) may be set to allow the

active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle.

If AP is LOW when the Read or Write command is issued, then normal Read or Write burst operation is executed and the bank

remains active at the completion of the burst.

If AP is HIGH when the Read or Write command is issued, then the auto-precharge function is engaged. This feature allows the

precharge operation to be partially or completely hidden during burst read cycles (dependent upon Read or Write latency), thus

improving system performance for random data access.

Burst Read with Auto-Precharge

If AP (CA0f) is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. The devices start an

Auto-Precharge operation on the rising edge of the clock BL/2 or BL/2 - 2 + RU(t_RTP/ t_CK) clock cycles later than the Read with AP

command.

A new bank Activate command can be issued to the same bank if both of the following two conditions are satisfied

simultaneously.



The RAS precharge time (t_RP) has been satisfied from the clock at which the auto precharge begins.

The RAS cycle time (t_RC) from the previous bank activation has been satisfied.



Figure of Burst read with Auto-Precharge: RL= 3, BL=4, RU(t_RTP(min)/t_CK)=2

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Burst write with Auto-Precharge

If AP (CA0f) is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The device starts an

Auto Precharge operation on the rising edge which is t_WRcycles after the completion of the burst write.

A new bank activate command can be issued to the same bank if both of the following two conditions are satisfied.



The RAS precharge time (t_RP) has been satisfied from the clock at which the auto precharge begins.

RAS cycle time (t_RC) from the previous bank activation has been satisfied.



Figure of Burst write with Auto precharge: WL = 1, BL= 4

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Table of Precharge & Auto Precharge Clarification

From Command

To Command

Precharge (to same Bank as Read)

Precharge All

Minimum Delay Between Commands

Unit

CLK

Notes

BL/2 + max(2, RU(t_RTP/ t_CK)) - 2

1

Read

BL/2 + max(2, RU(t_RTP/ t_CK)) - 2

Precharge (to same Bank as Read)

Precharge All

1

BST (for Reads)

Precharge (to same Bank as Read

w/AP)

BL/2 + max(2, RU(t_RTP/ t_CK)) - 2

CLK

1,2

1

Precharge All

BL/2 + max(2, RU(t_RTP/ t_CK)) - 2

BL/2 + max(2, RU(t_RTP/ t_CK)) - 2 +

Activate (to same Bank as Read

w/AP)

1

RU(t_RPpb/ t_CK

)

Read w/AP

Write or Write w/AP (same bank)

Write or Write w/AP (different bank)

Read or Read w/AP (same bank)

Read or Read w/AP (different bank)

Precharge (to same Bank as Write)

Precharge All

Illegal

CLK

3

1

RL + BL/2 + RU(t_DQSCKmax/ t_CK) - WL + 1

Illegal

BL/2

WL + BL/2 + RU(t_WR/ t_CK) + 1

WL + RU(t_WR/ t_CK) + 1

Write

Precharge (to same Bank as Write)

Precharge All

BST (for Writes)

Precharge (to same Bank as Write

w/AP)

WL + BL/2 + RU(t_WR/ t_CK) + 1

CLK

1,2

1

Precharge All

Activate (to same Bank as Write

w/AP)

WL + BL/2 + RU(t_WR/ t_CK) + 1 + RU(t_RPpb/ t_CK

)

1

Writes w/AP

Write or Write w/AP (same bank)

Write or Write w/AP (different bank)

Read or Read w/AP (same bank)

Read or Read w/AP (different bank)

Illegal

CLK

3

BL/2

Illegal

WL + BL/2 + RU(t_WTR/ t_CK) + 1

Precharge (to same Bank as

Precharge)

1

CLK

1

Precharge

Precharge All

Precharge

1

CLK

1

Precharge All

Notes:

1. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or

precharge all, issued to that bank. The precharge period is satisfied after t_RPdepending on the latest precharge command

issued to that bank.

2. Any command issued during the minimum delay time is illegal.

3. After Read with AP, seamless read operations to different banks are supported. After Write with AP, seamless write

operations to different banks are supported. Read w/AP and Write w/AP must not be interrupted or truncated.

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Refresh command

The Refresh command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of clock. Per

Bank Refresh is initiated by having CA3 LOW at the rising edge of clock and All Bank Refresh is initiated by having CA3 HIGH at

the rising edge of clock. Per Bank Refresh is only allowed in devices with 8 banks.

A Per Bank Refresh command, REFpb performs a refresh operation to the bank which is scheduled by the bank counter in the

memory device. The bank sequence of Per Bank Refresh is fixed to be a sequential round-robin: “0-1-2-3-4-5-6-7-0-1-...”. The

bank count is synchronized between the controller and the SDRAM upon issuing a RESET command or at every exit from self

refresh, by resetting bank count to zero. The bank addressing for the Per Bank Refresh count is the same as established in the

single-bank Precharge command. A bank must be idle before it can be refreshed. It is the responsibility of the controller to track

the bank being refreshed by the Per Bank Refresh command.

The REFpb command may not be issued to the memory until the following conditions are met:

a) t_RFCabhas been satisfied after the prior REFab command

b) t_RFCpbhas been satisfied after the prior REFpb command

c) t_RPhas been satisfied after the prior Precharge command to that given bank

t_RRDhas been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a different bank

than affected by the REFpb command).

The target bank is inaccessable during the Per Bank Refresh cycle time (t_RFCpb), however other banks within the device are

accessable and can be addressed during the Per Bank Refresh cycle. During the REFpb operation, any of the banks other than

the one being refreshed can be maintained in active state or accessed by a read or a write command.

When the Per Bank refresh cycle has completed, the affected bank will be in the Idle state after issuing REFpb:

a) t_RFCpbmust be satisfied before issuing a REFab command

b) t_RFCpbmust be satisfied before issuing an ACTIVATE command to the same bank

c) t_RRDmust be satisfied before issuing an ACTIVATE command to a different bank

d) t_RFCpbmust be satisfied before issuing another REFpb command

An All Bank Refresh command, REFab performs a refresh operation to all banks. All banks have to be in Idle state when REFab

is issued (for instance, by Precharge all-bank command). REFab also synchronizes the bank count between the controller and

the SDRAM to zero. The REFab command may not be issued to the memory until the following conditions have been met:

a) t_RFCabhas been satisfied after the prior REFab command

b) t_RFCpbhas been satisfied after the prior REFpb command

c) t_RPhas been satisfied after prior PRECHARGE commands

When the All Bank refresh cycle has completed, all banks will be in the Idle state after issuing REFab:

a) the t_RFCablatency must be satisfied before issuing an ACTIVATE command

b) the t_RFCablatency must be satisfied before issuing a REFab or REFpb command

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Table of Command Scheduling Separations related to Refresh

Minimum delay

Symbol

from

To

Note

REFab

t_RFCab

t_RFCpb

t_RRD

REFab

REFpb

Activate command to any bank

REFpb

REFab

Activate command to same bank as REFpb

REFpb

Activate command to different bank than REFpb

REFpb affecting an idle bank (different bank than Activate)

1

Activate

Activate command to different bank than the prior Activate

command

Note:

1. A bank must be in the Idle state before it is refreshed. Therefore, after Activate, REFab is not allowed and REFpb is

allowed only if it affects a bank which is in the Idle state.

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Refresh Requirements

1. Minimum number of Refresh commands:

The device requires a minimum number, R, of Refresh (REFab) commands within any rolling Refresh Window (t_REFW= 32 ms @

MR4[2:0] = “011” or T_CASE≤ 85 °C). See the Table of “Refresh Requirement Parameters” for actual numbers per density. The

resulting average refresh interval (t_REFI) is given in the Table of “Refresh Requirement Parameters”.

See MR4 for t_REFWand t_REFIrefresh multipliers at different MR4 settings.

For devices supporting Per-Bank-Refresh, a REFab command can be replaced by a full cycle of eight REFpb commands.

2. Burst Refresh limitation:

To limit maximum current consumption, a maximum of eight REFab commands can be issued in any rolling t_REFBW(t_REFBW= 4 x 8

x t_RFCab). This condition does not apply if REFpb commands are used.

3. Refresh Requirements and Self Refresh:

If any time within a refresh window is spent in Self Refresh Mode, the number of required Refresh commands in this particular

window is reduced to:

R* = R - RU{t_SRF/ t_REFI} = R - RU{R * t_SRF/ t_REFW}; where RU stands for the round-up function

Figure of Definition of t_SRF

Several examples on how t_SRFis calculated:

A: with the time spent in Self Refresh Mode fully enclosed in the Refresh Window (t_REFW).

B: at Self Refresh entry

C: at Self Refresh exit

D: with several different invervals spent in Self Refresh during one t_REFWinterval

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The devices provide significant flexibility in scheduling REFRESH commands, as long as the boundary conditions are met.

In the most straight forward case, a REFRESH command should be scheduled every t_REFI. In this case, Self Refresh can be

entered at any time.

The users may choose to deviate from this regular refresh pattern e.g., to enable a period where no refreshes are required. As an

example, using a 1Gb LPDDR2 device, the user can choose to issue a refresh burst of 4096 REFRESH commands with the

maximum allowable rate (limited by t_REFBW), followed by a long time without any REFRESH commands, until the refresh window

is complete, then repeating this sequence. The achieveable time without REFRESH commands is given by t_REFW- (R / 8) * t_REFBW

= t_REFW- R * 4 * t_RFCab. For example, a 1Gb device at T_CASE≦ 85℃can be operation without a refresh for up to 32 ms - 4096 * 4

* 130 ns ~ 30 ms.

While both - the regular and the burst/pause - patterns can satisfy the refresh requirements per rolling refresh interval, if they are

repeated in every subsequent 32 ms window, extreme care must be taken when transitioning from one pattern to another to

satisfy the refresh requirement in every rolling refresh window during the transition. If this transition happens directly after the

burst refresh phase, all rolling t_REFWintervals will meet the minimum required number of REFRESH commands.

As an example of a non-allowable transition, the regular refresh pattern starts after the completion of the pause-phase of the

burst/pause refresh pattern. For several rolling t_REFWintervals the minimum number of REFRESH commands is not satisfied.

The understanding of the pattern transition is extremely relevant (even if in normal operation only one pattern is employed), as in

Self Refresh Mode, a regular distributed refresh pattern must be assumed, which is reflected in the equation for R* above.

Therefore it is recommended to enter Self Refresh Mode ONLY directly after the burst-phase of a burst/pause refresh pattern and

begin with the burst phase upon exit from Self Refresh.

Figure of Regular, Distributed Refresh Pattern vs. Repetitive Burst Refresh with Subsequent Refresh Pause

Note: As an example, in a 1Gb device at T_CASE≦ 85 ℃, the distributed refresh pattern has one REFRESH command per 7.8

us; the burst refresh pattern has one REFRESH command per 0.52 us, followed by ~30ms without any REFRESH command.

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Figure of Allowable Transition from Repetitive Burst Refresh with Subsequent Refresh Pause to Regular, Distributed

Refresh Pattern

Note: As an example, in a 1Gb device at T_CASE≦ 85 ℃, the distributed refresh pattern has one REFRESH command per 7.8 us;

the burst refresh pattern has one REFRESH command per 0.52us, followed by ~30ms without any REFRESH command.

Figure of NOT-Allowable Transition from Repetitive Burst Refresh with Subsequent Refresh Pause to Regular,

Distributed Refresh Pattern

Note: Only ~2048 REFRESH commands (<R which is 4096) in the indicated t_REFWwindow.

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Figure of Recommended Self Refresh entry and exit in conjunction with a Burst/Pause Refresh patterns

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Figure of All Bank Refresh Operation

Figure of Per Bank Refresh Operation

Notes:

1. In the beginning of this example, the REFpb bank is pointing to Bank 0.

2. Operations to other banks than the bank being refreshed are allowed during the t_RFCpbperiod.

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Self Refresh operation

The Self Refresh command can be used to retain data in the array, even if the rest of the system is powered down. When in the

Self Refresh mode, the device retains data without external clocking. The device has a built-in timer to accommodate Self

Refresh operation. The Self Refresh command is defined by having CKE LOW, CS_n LOW, CA0 LOW, CA1 LOW, and CA2

HIGH at the rising edge of the clock. CKE must be HIGH during the previous clock cycle. A NOP command must be driven in the

clock cycle following the Self Refresh command. Once the command is registered, CKE must be held LOW to keep the device in

Self Refresh mode.

LPDDR2 devices can operate in Self Refresh in both the Standard or Extended Temperature Ranges. The devices will also

manage Self Refresh power consumption when the operating temperature changes, lower at low temperatures and higher

temperatures. See the Table of “IDD Specification Parameters and Operating Conditions” for details.

Once the device has entered Self Refresh mode, all of the external signals except CKE, are “don‘t care”. For proper self refresh

operation, power supply pins (V_DD1, V_DD2, V_DDQand V_DDCA) must be at valid levels. V_DDQcan be turned off during Self Refresh. If

V_DDQis turned off, V_REFDQmust also be turned off. Prior to exiting Self Refresh, both V_DDQand V_REFDQmust be within specified

limits (see the Table of “Single-Ended AC and DC Input Levels for DQ and DM”).

V_REFDQand V_REFCAcan be at any level within minimum and maximum levels (see “AC and DC Logic Input Levels for

Single-Ended Signals” section). However, prior to exit Self Refresh, V_REFDQand V_REFCAmust be within specified limits (See 7.1).

The device initiates a minimum of one all-bank REFRESH command internally within t_CKESRperiod once it enters Self Refresh

mode. The clock is internally disabled during Self Refresh Operation to save power. The minimum time that the device must

remain in Self Refresh mode is t_CKESR. The user can change the external clock frequency or halt the external clock one clock after

Self Refresh entry is registered; however, the clock must be restarted and stable before the device can exit Self Refresh

operation.

The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable and within specified

limits for a minimum of 2 clock cycles prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least t_XSR

must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must

remain HIGH for the entire Self Refresh exit period t_XSRfor proper operation except for self refresh re-entry. NOP commands

must be registered on each rising clock edge during t_XSR

.

The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is driven

HIGH for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one REFRESH command (8

per-bank or 1 all-bank) must be issued before entry into a subsequent Self Refresh command.

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Figure of Self Refresh Operation

Notes:

1. Input clock frequency can be changed or stopped during self refresh, provided that upon exiting self refresh, a minimum of

two cycles of stable clock are provided, and the clock frequency is between the minimum and maximum frequency for the

particular speed grade.

2. The device must be in the “All banks idle” state prior to entering Self Refresh mode.

3. t_XSRbegins at the rising edge of the clock after CKE is driven HIGH.

4. A valid command can be issued only after t_XSRis satisfied. NOPs must be issued during t_XSR

.

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Partial Array Self Refresh: Bank Masking

Each bank can be independently configured whether a self refresh operation is taking place. One mode register unit of 8 bits

accessible via MRW command is assigned to program the bank masking status of each bank up to 8 banks. For bank masking bit

assignments, see Mode Register 16 (MR16).

The mask bit to the bank controls a refresh operation of entire memory within the bank. If a bank is masked via MRW, a

REFRESH operation to the entire bank is blocked and data retention by a bank is not guaranteed in self refresh mode. To enable

a REFRESH operation to a bank, a corresponding bank mask bit must be programmed, “unmasked”. When a bank mask bit is

unmasked, a refresh to a bank is determined by the programmed status of segment mask bits, which is described in the following

chapter.

Partial Array Self Refresh: Segment Masking

Segment masking scheme can be used in place of or in combination with bank masking scheme in the device. The numbers of

segment differ from the density and the setting of each segment mask bit is applied across all the banks. For segment masking

bit assignments, see Mode Register 17 (MR17).

For those refresh-enabled banks, a refresh operation to the address range which is represented by a segment is blocked when

the mask bit to this segment is programmed, “masked”. Programming of segment mask bits is similar to the one of bank mask

bits. For 1Gb and larger densities, 8 segments are used as listed in Mode Register 17 (MR17). One mode register unit is used for

the programming of segment mask bits up to 8 bits. For densities less than 1Gb, segment masking is not supported.

Table of Bank and Segment Masking Example

Segment Mask

Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7

(MR17)

Bank Mask

(MR16)

0

1

0

1

Segment 0

0

1

0

1

-

M

-

M

Segment 1

Segment 2

Segment 3

Segment 4

Segment 5

Segment 6

Segment 7

M

-

M

-

M

-

M

-

M

-

M

-

M

Note: This table illustrates an example of an 8-bank device, when a refresh operation to bank 1 and bank 7, as well as segment 2

and segment 7 are masked.

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Mode Register Read Command

The Mode Register Read (MRR) command is used to read configuration and status data from mode registers. The Mode

Register Read (MRR) command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising

edge of the clock. The mode register is selected by {CA1f-CA0f, CA9r- CA4r}. The mode register contents are available on the

first data beat of DQ[7:0] after RL * t_CK+ t_DQSCK+ t_DQSQand following the rising edge of the clock where the Mode Register Read

command is issued. Subsequent data beats contain valid, but undefined content, except in the case of the DQ Calibration

function, where subsequent data beats contain valid content as described in “DQ Calibration” section. All DQS_t, DQS_c are

toggled for the duration of the Mode Register Read burst.

The MRR command has a burst length of four. The Mode Register Read operation (consisting of the MRR command and the

corresponding data traffic) must not be interrupted. The MRR command period (t_MRR) is 2 clock cycles. Mode Register Reads to

reserved and write-only registers shall return valid, but undefined content on all data beats and DQS_t, DQS_c shall be toggled.

Figure of Mode Register Read timing example: RL = 3, t_MRR= 2

Notes:

1. Mode Register Read has a burst length of four.

2. Mode Register Read operation must not be interrupted.

3. Mode Register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain valid, but undefined data. DQ[Max:8]

contain valid, but undefined data for the duration of the MRR burst.

4. The Mode Register Command period is t_MRR. No command (other than Nop) is allowed during this period.

5. Mode Register Reads to DQ Calibration registers MR32 and MR40 are described in the section on DQ Calibration.

6. Minimum Mode Register Read to write latency is RL + RU(t_{DQSCK, max}/ t_CK) + 4/2 + 1 - WL clock cycles.

7. Minimum Mode Register Read to Mode Register Write (MRW) latency is RL + RU(t_{DQSCK, max}/ t_CK) + 4/2 + 1 clock cycles.

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The MRR command must not be issued earlier than BL/2 clock cycles after a prior Read command and WL + 1 + BL/2 + RU( t_WTR

/t_CK) clock cycles after a prior Write command, because read bursts and write bursts can not be truncated by MRR. Note that if a

read or write burst is truncated with a Burst Terminate (BST) command, the effective burst length of the truncated burst should be

used as “BL”.

Figure of Read to MRR timing example: RL = 3, t_MRR= 2

Notes:

1. The minimum number of clock cycles from the burst read command to the Mode Register Read command is BL/2.

2. The Mode Register Read Command period is t_MRR. No command (other than Nop) is allowed during this period

Figure of Burst Write Followed by MRR: RL = 3, WL = 1, BL = 4

Notes:

1. The minimum number of clock cycles from the burst write command to the Mode Register Read command is [WL + 1 + BL/2

+ RU( t_WTR/ t_CK)].

2. The Mode Register Read command period is t_MRR. No command (other than No) is allowed during this period.

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Temperature Sensor

LPDDR2 device features a temperature sensor whose status can be read from MR4. This sensor can be used to determine an

appropriate refresh rate, determine whether AC timing derating is required in the Extended Temperature Range and/or monitor

the operating temperature. Either the temperature sensor or the device T_CASE(See the Table of “Operating Temperature Range”)

can be used to determine whether operating temperature requirements are being met.

LPDDR2 devices can monitor device temperature and update MR4 according to t_TSI. Upon exiting self refresh or power down, the

device temperature status bits will be no older than t_TSI

.

When using the temperature sensor, the actual device temperature may be higher than the T_CASEspecification (See the Table of

“Operating Temperature Range”) that applies for the Standard or Extended Temperature Ranges. For example, T_CASEmay be

above 85℃ when MR4[2:0] equals 011b.

To assure proper operation using the temperature sensor, applications must accommodate the parameters in the temperature

sensor definitions table.

Table of Temperature Sensor Definitions

Symbol

Parameter

Description

Max/Min

Value

Unit

Maximum temperature gradient

experienced by the memory device

at the temperature of interest over a

range of 2℃

System

Temperature

Gradient

℃/s

TempGradient

Max

System Dependent

MR4 Read

Interval

Time period between MR4 reads

from the system

System Dependent

32

ReadInterval

t_TSI

Max

ms

Temperature

Sensor Interval

Maximum delay between internal

updates of MR4

System

Maximum time between a read of

System Dependent

SysRespDelay

Response Delay MR4 and the response by the system

Margin between the point at which

Device

Temperature

Margin

the device temperature enters the

Extended Temperature Range and

point at which the controller

℃

TempMargin

Max

2

re-configures the system accordingly

To determine the required frequency of polling MR4, the system must use the maximum TempGradient and the maximum

response time of the system using the following equation:

TempGradient x (ReadInterval + t_TSI+ SysRespDelay) ≤ 2℃

For example, if TempGradient is 10℃/s and the SysRespDelay is 1 ms:

10℃/s * (ReadInterval + 32ms + 1ms) ≤ 2℃

In this case, ReadInterval must be no greater than 167ms.

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Figure of Temperature Sensor Timing

DQ Calibration

LPDDR2-S4 device features a DQ Calibration function that outputs one of two predefined system timing calibration patterns. A

Mode Register Read to MR32 (Pattern “A”) or MR40 (Pattern “B”) will return the specified pattern on DQ0 and DQ8.

DQ[7:1] and DQ[15:9] drive the same information as DQ0 during the MRR burst.

MRR DQ Calibration commands can only occur in the Idle state.

Table of Data Calibration Pattern Description

Pattern

Pattern A

Pattern B

MR#

MR32

MR40

Bit Time 0

Bit Time 1

Bit Time 2

Bit Time 3

Description

Read to MR32 return DQ calibration

pattern A

1

0

1

0

1

Read to MR40 return DQ calibration

pattern B

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Figure of MR32 and MR40 DQ Calibration timing example: RL = 3, t_MRR= 2

Note:

1. Mode Register Read has a burst length of four.

2. Mode Register Read operation must not be interrupted.

3. The Mode Register Command period is t_MRR. No command (other than Nop) is allowed during this period.

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Mode Register Write Command

The Mode Register Write command is used to write configuration data to mode registers. The Mode Register Write (MRW)

command is initiated by having CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising edge of the clock. The

mode register is selected by {CA1f-CA0f, CA9r-CA4r}. The data to be written to the mode register is contained in CA9f-CA2f. The

MRW command period is defined by t_MRW. Mode Register Writes to read-only registers have no impact on the functionality of the

device.

The MRW can only be issued when all banks are in the idle precharge state. One method of ensuring that the banks are in the

idle precharge state is to issue a Precharge-All command.

Figure of Mode Register Write timing example: RL = 3, t_MRW= 5

Notes:

1. The Mode Register Write Command period is t_MRW. No command (other than Nop) is allowed during this period.

2. At time Ty, the device is in the idle state.

Table of Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW)

Current State

Command

MRR

Intermediate State

Mode Register Reading (All Banks Idle)

Mode Register Writing (All Banks Idle)

Resetting (Device Auto Initialization)

Mode Register Reading (Bank(s) Active)

Not Allowed

Next State

All Banks Idle

Bank(s) Active

Not Allowed

All Banks Idle

MRW

MRW (RESET)

MRR

Bank(s) Active

MRW

MRW (RESET)

Not Allowed

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Mode Register Write Reset (MRW RESET)

The MRW RESET command brings the device to the Device Auto Initialization (Resetting) state in the power on Initialization

sequence (See “Reset command” of Power Ramp and Device Initialization). The MRW RESET command can be issued from the

idle state. This command resets all Mode Registers to their default values. No commands other than NOP can be issued to the

device during the MRW RESET period (t_INIT4). After MRW Reset, boot timings must be observed until the device initialization

sequence is complete and the device is in the idle state. Array data is undefined after the MRW RESET command. For the timing

diagram related to MRW Reset, refer to the Figure of “Power Ramp and Initialization Sequence”.

Mode Register Write ZQ Calibration Command

The MRW command is also used to initiate the ZQ Calibration command. The ZQ Calibration command is used to calibrate the

output drivers (R_ON) over process, temperature, and voltage. LPDDR2-S4 devices support ZQ Calibration.

There are four ZQ Calibration commands and related timings times: t_ZQINIT, t_ZQRESET, t_ZQCL, and t_ZQCS. t_ZQINITcorresponds to the

initialization calibration; t_ZQRESETis for resetting ZQ setting to default impedance; t_ZQCLis for long calibration; and t_ZQCSis for short

calibration.

The Initialization ZQ Calibration (ZQINIT) must be performed for LPDDR2 devices. This Initialization Calibration achieves a R_ON

accuracy of +/-15%. After initialization, the ZQ Long Calibration can be used to re-calibrate the system to a R_ONaccuracy of

+/-15%. A ZQ Short Calibration can be used periodically to compensate for temperature and voltage drift in the system.

The ZQRESET Command resets the R_ONcalibration to a default accuracy of +/-30% across process, voltage, and temperature.

This command is used to ensure R_ONaccuracy to +/-30% when ZQCS and ZQCL are not used.

One ZQCS command can effectively correct a minimum of 1.5% (ZQ correction) of R_ONimpedance error within t_ZQCSfor all speed

bins, assuming the maximum sensitivities specified in “Output Driver Temperature and Voltage Sensitivity” section. The

appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (T_driftrate) and voltage (V_driftrate) drift

rates that the LPDDR2 is subject to in the application, is illustrated. The interval could be defined by the following formula:

ZQ correction

(T _sensx T _driftrate) + (V _sensx V _driftrate

)

Where T_sens= max (dR_ONdT) and V_sens= max (dR_ONdV) define the temperature and voltage sensitivities.

For example, if T_sens= 0.75% / ℃, V_sens= 0.20% / mV, T_driftrate= 1 ℃ / sec and V_driftrate= 15 mV / sec, then the interval between

ZQCS commands is calculated as:

1.5

= 0.4 s

(0.75 x 1) + (0.20 x 15)

A ZQ Calibration command can only be issued when the device is in Idle state with all banks precharged.

No other activities can be performed on the data bus during the calibration period (t_ZQINIT, t_ZQCL, t_ZQCS). The quiet time on the data

bus helps to accurately calibrate R_ON. There is no required quiet time after the ZQ RESET command. If multiple devices share a

single ZQ resistor, only one device can be calibrating at any given time. After calibration is achieved, the device shall disable the

ZQ ball’s current consumption path to reduce power.

In systems that share the ZQ resistor between devices, the controller must not allow overlap of t_ZQINIT, t_ZQCS, or t_ZQCLbetween the

devices. ZQ RESET overlap is allowed. If the ZQ resistor is absent from the system, ZQ must be connected to V_DDCA. In this case,

the device must ignore ZQ calibration commands and the device will use the default calibration settings.

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Figure of ZQ Calibration Initialization timing example

Notes:

1. The ZQ Calibration Initialization period is t_ZQINIT. No command (other than Nop) is allowed during this period.

2. CKE must be continuously registered HIGH during the calibration period.

3. All devices connected to the DQ bus should be high impedance during the calibration process.

Figure of ZQ Calibration Short timing example

Notes:

1. The ZQ Calibration Short period is t_ZQCS. No command (other than Nop) is allowed during this period.

2. CKE must be continuously registered HIGH during the calibration period.

3. All devices connected to the DQ bus should be high impedance during the calibration process.

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Figure of ZQ Calibration Long timing example

Notes:

1. The ZQ Calibration Long period is t_ZQCL. No command (other than Nop) is allowed during this period.

2. CKE must be continuously registered HIGH during the calibration period.

3. All devices connected to the DQ bus should be high impedance during the calibration process.

Figure of ZQ Calibration Reset timing example

Notes:

1. The ZQ Calibration Reset period is t_ZQRESET. No command (other than Nop) is allowed during this period.

2. CKE must be continuously registered HIGH during the calibration period.

3. All devices connected to the DQ bus should be high impedance during the calibration process.

ZQ External Resistor Value, Tolerance, and Capacitive Loading

To use the ZQ Calibration function, a 240 Ohm +/- 1% tolerance external resistor must be connected between the ZQ pin and

ground. A single resistor can be used for each device or one resistor can be shared between multiple devices if the ZQ calibration

timings for each device do not overlap. The total capacitive loading on the ZQ pin must be limited.

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Power Down

Power down is synchronously entered when CKE is registered LOW and CS_n HIGH at the rising edge of clock. CKE must be

registered HIGH in the previous clock cycle. A NOP command must be driven in the clock cycle following the power down

command. CKE is not allowed to go LOW while mode register, read, or write operations are in progress. CKE is allowed to go

LOW while any of other operations such as row activation, precharge, autoprecharge, or refresh is in progress, but power down

I_DDspec will not be applied until finishing those operations.

If power down occurs when all banks are idle, this mode is referred to as idle power down; if power down occurs when there is a

row active in any bank, this mode is referred to as active power down.

Entering power down deactivates the input and output buffers, excluding CK_t, CK_c, and CKE. In power down mode, CKE must

be maintained LOW while all other input signals are “Don‘t Care”. CKE LOW must be maintained until t_CKEhas been satisfied.

V_REFCAmust be maintained at a valid level during power down.

V_DDQmay be turned off during power down. If V_DDQis turned off, then V_REFDQmust also be turned off. Prior to exiting power down,

both V_DDQand V_REFDQmust be within their respective minimum/maximum operating ranges (see “AC and DC Operating

Conditions” section).

The maximum duration in power down mode is only limited by the refresh requirements, as no refresh operations are performed

in power down mode.

The power down state is exited when CKE is registered HIGH. The controller must drive CS_n HIGH in conjunction with CKE

HIGH when exiting the power down state. CKE HIGH must be maintained until t_CKEhas been satisfied. A valid, executable

command can be applied with power down exit latency, t_XPafter CKE goes HIGH. Power down exit latency is defined in the “AC

Timing” section.

Figure of Basic Power Down Entry and Exit timing

Note: Input clock frequency can be changed or the input clock stopped during power down, provided that upon exiting power

down, the clock is stable and within specified limits for a minimum of 2 clock cycles prior to power down exit and the clock

frequency is between the minimum and maximum frequency for the particular speed grade.

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Figure of CKE Intensive Environment

Figure of Refresh to Refresh timing with CKE Intensive Environment

Note: The pattern shown above can repeat over a long period of time. With this pattern, all AC and DC timing & voltage

specifications with temperature and voltage drift are ensured.

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Figure of Read to Power Down Entry

Note: CKE can be registered LOW at (RL + RU( t_{DQSCK (MAX)}/ t_CK) + BL/2 + 1) clock cycles after the clock on which the Read

command is registered.

Figure of Read with Auto Precharge to Power Down Entry

Note: CKE can be registered LOW at (RL + RU( t_{DQSCK (MAX)}/ t_CK) + BL/2 + 1) clock cycles after the clock on which the Read

command is registered.

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Figure of Write to Power Down Entry

Note: CKE can be registered LOW at (WL + 1 + BL/2 + RU( t_WR/ t_CK)) clock cycles after the clock on which the Write command is

registered.

Figure of Write with Auto Precharge to Power Down Entry

Note: CKE can be registered LOW at (WL + 1 + BL/2 + RU( t_WR/ t_CK) + 1) clock cycles after the Write command is registered.

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Figure of Refresh command to Power Down Entry

Note: CKE can go LOW at t_IHCKEafter the clock on which the Refresh command is registered.

Figure of Activate command to Power Down Entry

Note: CKE can go LOW at t_IHCKEafter the clock on which the Activate command is registered.

Figure of Precharge/Precharge All command to Power Down Entry

Note: CKE may go LOW at t_IHCKEafter the clock on which the Precharge/Precharge All command is registered.

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Figure of Mode Register Read to Power Down Entry

Note: CKE can be registered LOW at (RL + RU( t_{DQSCK (MAX)}/ t_CK)+ BL/2 + 1) clock cycles after the clock on which the Mode

Register Read command is registered.

Figure of Mode Register Write to Power Down Entry

Note: CKE can be registered LOW at t_MRWafter the clock on which the Mode Register Write command is registered

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Deep Power Down

Deep Power Down (DPD) is entered when CKE is registered LOW with CS_n LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW at the

rising edge of clock. A NOP command must be driven in the clock cycle following the power down command. CKE is not allowed

to go LOW while MRR or MRW operations are in progress. All banks must be in idle state with no activity on the data bus prior to

entering the Deep Power Down mode. During Deep Power Down, CKE must be held LOW.

In Deep Power Down mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry are disabled

within the device. All power supplies must be within specified limits prior to exiting Deep Power Down. V_REFDQand V_REFCAcan be

at any level within minimum and maximum levels. However prior to exiting Deep Power Down, V_REFmust be within specified

limits (See "AC & DC Operating Conditions" section).

The contents of the device may be lost upon entry into Deep Power Down mode.

The Deep Power Down state is exited when CKE is registered HIGH, while meeting t_ISCKEwith a stable clock input. The device

must be fully re-initialized by controller as described in the Power Up and Initialization sequence. The device is ready for normal

operation after the initialization sequence.

Figure of Deep Power Down Entry and Exit timing

Notes:

1. Initialization sequence can start at any time after T_C.

2. t_INIT3and T_Crefer to timings in the initialization sequence. For more detail, see “Power Up, Initialization, and Power Down”.

3. Input clock frequency can be changed or the input clock stopped during deep power down, provided that upon exiting deep

power down, the clock is stable and within specified limits for a minimum of 2 clock cycles prior to deep power down exit and

the clock frequency is between the minimum and maximum frequency for the particular speed grade.

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Input clock stop and frequency change

LPDDR2 devices support input clock frequency change during CKE LOW under the following conditions:



t_{CK(abs), min}is met for each clock cycle;

Refresh Requirements apply during clock frequency change;

During clock frequency change, only REFab or REFpb commands may be executing;

Any Activate, Preactive or Precharge commands have executed to completion prior to changing the frequency;

The related timing conditions (t_RCD, t_RP) have been met prior to changing the frequency;

The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;

The clock satisfies t_CH(abs)and t_CL(abs)for a minimum of 2 clock cycles prior to CKE going HIGH.

After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set the WR, RL

etc. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency.

LPDDR2 devices support clock stop during CKE LOW under the following conditions:



CK_t is held LOW and CK_c is held HIGH during clock stop;

Refresh Requirements apply during clock stop;

During clock stop, only REFab or REFpb commands may be executing;

Any Activate, Preactive or Precharge commands have executed to completion prior to stopping the clock;

The related timing conditions (t_RCD, t_RP) have been met prior to stopping the clock;

The initial clock frequency shall be maintained for a minimum of 2 clock cycles after CKE goes LOW;

The clock satisfies t_CH(abs)and t_CL(abs)for a minimum of 2 clock cycles prior to CKE going HIGH.

LPDDR2 devices support input clock frequency change during CKE HIGH under the following conditions:



t_{CK (abs), min}is met for each clock cycle;

Refresh Requirements apply during clock frequency change;

Any Activate, Read, Write, Preactive, Precharge, Mode Register Write, or Mode Register Read commands must have

executed to completion, including any associated data bursts prior to changing the frequency;

The related timing conditions (t_RCD, t_WR, t_WRA, t_RP, t_MRW, t_MRR, etc.) have been met prior to changing the frequency;

CS_n shall be held HIGH during clock frequency change;



During clock frequency change, only REFab or REFpb commands may be executing;

The LPDDR2 device is ready for normal operation after the clock satisfies t_CH(abs)and t_CL(abs)for a minimum of 2t_CK+ t_XP

.

After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL etc. These settings

may need to be adjusted to meet minimum timing requirements at the target clock frequency.

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LPDDR2 devices support clock stop during CKE HIGH under the following conditions:



CK_t is held LOW and CK_c is held HIGH during clock stop;

CS_n shall be held HIGH during clock clock stop;

Refresh Requirements apply during clock stop;

During clock stop, only REFab or REFpb commands may be executing;

Any Activate, Read, Write, Preactive, Precharge, Mode Register Write, or Mode Register Read commands must have

executed to completion, including any associated data bursts prior to stopping the clock;



The related timing conditions (t_RCD, t_WR, t_WRA, t_RP, t_MRW, t_MRR, etc.) have been met prior to stopping the clock;

The LPDDR2 device is ready for normal operation after the clock is restarted and satisfies t_CH(abs)and t_CL(abs)for a minimum

of 2t_CK+ t_XP

.

No Operation command

The purpose of the No Operation command (NOP) is to prevent the device from registering any unwanted command between

operations. Only when the CKE level is constant for clock cycle N-1 and clock cycle N, a NOP command can be issued at clock

cycle N. A NOP command has two possible encodings:

1. CS_n HIGH at the clock rising edge N.

2. CS_n LOW and CA0, CA1, CA2 HIGH at the clock rising edge N.

The No Operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle.

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Truth tables

Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the device

must be powered down and then restarted through the specified initialization sequence before normal operation can continue.

Table of Command Truth Table ^1~12

Command Pins

CKE

CA Pins

CK_t

Edge

Command

CS_n

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CA9

CK_t (n-1) CK_t (n)

H

X

H

X

H

L

H

L

X

L

MA6

L

MA7

L

OP0

L

OP1

H

MA0

OP2

MA0

MA1

OP3

MA1

MA2

OP4

MA2

MA3

OP5

MA3

MA4

OP6

MA4

MA5

OP7

MA5

MRW

MRR

X

L

MA6

L

MA7

L

X

H

L

X

Refresh

(pre bank)¹¹

X

L

X

L

H

Refresh

(all bank)

X

L

X

Enter Self

Refresh

L

X

L

H

L

R0

H

R1

L

R8

R2

L

R9

R3

R10

R4

R11

R5

C1

C7

C1

C7

X

R12

R6

C2

C8

C2

C8

X

BA0

R7

BA1

R13

BA1

C10

BA1

C10

BA1

BA2

R14

BA2

C11

BA2

C11

BA2

Activate

(bank)

X

L

RFU

C5

RFU

C6

BA0

C9

Write (bank)

Read (bank)

X

L

AP^3,4

C3

L

C4

H

RFU

C5

RFU

C6

BA0

C9

X

L

AP^3,4

H

C3

H

C4

L

Precharge

(pre bank,

all bank)

H

AB

BA0

X

L

X

H

L

X

BST

X

L

X

Enter Deep

Power Down

L

X

L

H

L

H

NOP

X

L

Maintain PD,

SREF, DPD

(NOP)

L

X

H

X

H

X

H

X

H

X

H

L

H

L

NOP

Maintain PD,

SREF, DPD

(NOP)

L

H

X

L

Enter Power

Down

L

H

Exit PD,

SREF, DPD

X

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Notes:

1. All commands are defined by the current states of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock.

2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon.

3. AP “HIGH” during a READ or WRITE command indicates that an auto precharge will occur to the bank associated with the

READ or WRITE command.

4. “X” means “H or L (but a defined logic level)”.

5. Self refresh exit and Deep Power Down exit are asynchronous.

6. V_REFmust be between 0 and V_DDQduring Self Refresh and Deep Power Down operation.

7. CAxr refers to command/address bit “x” on the rising edge of clock.

8. CAxf refers to command/address bit “x” on the falling edge of clock.

9. CS_n and CKE are sampled at the rising edge of clock.

10. Per Bank Refresh is only allowed in devices with 8 banks.

11. The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero.

12. AB “HIGH” during Precharge command indicates that all bank Precharge will occur. In this case, Bank Address is

do-not-care.

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Table of CKE Truth Table ^1~5,11

Current State

CKE n-1

CKE n

CS_n

Command n

Operation n

Next State

Notes

6,9

Maintain Active Power

Down

L

X

Active Power Down

Exit Active Power

Down

L

H

NOP

Active

Maintain Idle Power

Down

L

H

L

X

H

X

NOP

X

Idle Power Down

Idle

Idle Power Down

Exit Idle Power Down

6,9

Maintain Resetting

Power Down

Resetting Power Down

Resetting Idle Power

Down

Exit Resetting Power

Down

L

H

L

H

X

NOP

X

Idle or Resetting

6,9,12

Maintain Deep Power

Down

Deep Power Down

L

H

L

H

X

H

NOP

X

Exit Deep Power Down

Maintain Self Refresh

Exit Self Refresh

Power On

Self Refresh

Idle

8

Self Refresh

H

NOP

7,10

Enter Active Power

Down

Bank(s) Active

H

L

H

L

NOP

Active Power Down

Idle Power Down

Self Refresh

Enter Idle Power Down

Enter Self Refresh

Enter Self

Refresh

All Banks Idle

Deep Power

Down

Enter Deep Power

Down

H

L

Deep Power Down

Enter Resetting Power

Down

Resetting

H

L

H

NOP

Resetting Power Down

Other states

H

Refer to the Command Truth Table

Notes:

1. “CKE n” is the logic state of CKE at clock rising edge n; “CKE n-1” was the state of CKE at the previous clock edge.

2. “CS_n” is the logic state of CS_n at the clock rising edge n;

3. “Current state” is the state of the device immediately prior to clock rising edge n.

4. “Command n” is the command registered at clock edge N, and “Operation n” is a result of “Command n”.

5. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

6. Power Down exit time (t_XP) should elapse before a command other than NOP is issued.

7. Self Refresh exit time (t_XSR) should elapse before a command other than NOP is issued.

8. The Deep Power Down exit procedure must be followed as discussed in the Deep Power Down section.

9. The clock must toggle at least twice during the t_XPperiod.

10. The clock must toggle at least twice during the t_XSRtime.

11. ‘X‘ means “Don‘t care”.

12. Upon exiting Resetting Power Down, the device will return to the idle state if t_INIT5has expired.

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Table of Current State Bank n - Command to Bank n ^1~5

Current State

Command

NOP

Operation

Continue previous operation

Select and activate row

Next State

Current State

Active

Notes

Any

ACTIVATE

Refresh (Per Bank)

Refresh (All Bank)

MRW

Begin to refresh

Refreshing (Per Bank)

Refreshing (All Bank)

MR Writing

Idle, MR Reading

Resetting

6

7

Begin to refresh

Idle

Load value to Mode Register

Read value from Mode Register

Begin Device Auto-Initialization

Deactivate row in bank or banks

Select column, and start read burst

Select column, and start write burst

Read value from Mode Register

Deactivate row in bank or banks

Select column, and start new read burst

Select column, and start write burst

Read burst terminate

MRR

Reset

7,8

Precharge

Read

Precharging

Reading

9,15

Write

Writing

Row Active

MRR

Active MR Reading

Precharging

Reading

Precharge

Read

9

10,11

10,11,12

13

Reading

Writing

Write

Writing

BST

Active

Write

Select column, and start new write burst

Select column, and start read burst

Write burst terminate

Writing

10,11

10,11,14

13

Read

Reading

BST

Active

Power On

Resetting

Reset

Begin Device Auto-Initialization

Read value from Mode Register

Resetting

7,9

MRR

Resetting MR Reading

Notes:

1. The table applies when both CKEn-1 and CKEn are HIGH, and after t_XSRor t_XPhas been met if the previous state was Power

Down.

2. All states and sequences not shown are illegal or reserved.

3. Current State Definitions:

Idle: The bank or banks have been precharged, and t_RPhas been met.

Active: A row in the bank has been activated, and t_RCDhas been met. No data bursts / accesses and no register accesses

are in progress.

Reading: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Writing: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. NOP commands or allowable

commands to the other bank must be issued on any clock edge occurring during these states. Allowable commands to the

other banks are determined by its current state, and according to Table of Current State Bank n - Command to Bank m.

Precharging: starts with the registration of a Precharge command and ends when t_RPis met. Once t_RPis met, the bank will be

in the idle state.

Row Activating: starts with registration of an Activate command and ends when t_RCDis met. Once t_RCDis met, the bank will be

in the ‘Active‘ state.

Read with AP Enabled: starts with the registration of the Read command with Auto Precharge enabled and ends when t_RP

has been met. Once t_RPhas been met, the bank will be in the idle state.

Write with AP Enabled: starts with registration of a Write command with Auto Precharge enabled and ends when t_RPhas

been met. Once t_RPis met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; NOP commands must be applied to each positive

clock edge during these states.

Refreshing (Per Bank): starts with registration of a Refresh (Per Bank) command and ends when t_RFCpbis met. Once t_RFCpbis

met, the bank will be in the idle state.

Refreshing (All Bank): starts with registration of a Refresh (All Bank) command and ends when t_RFCabis met. Once t_RFCabis

met, the device will be in the all banks idle state.

Idle MR Reading: starts with the registration of a MRR command and ends when t_MRRhas been met. Once t_MRRhas been

met, the bank will be in the idle state.

Resetting MR Reading: starts with the registration of a MRR command and ends when t_MRRhas been met. Once t_MRRhas

been met, the bank will be in the resetting state.

Active MR Reading: starts with the registration of a MRR command and ends when t_MRRhas been met. Once t_MRRhas been

met, the bank will be in the active state.

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MR Writing: starts with the registration of a MRW command and ends when t_MRWhas been met. Once t_MRWhas been met,

the bank will be in the idle state.

Precharging All: starts with the registration of a Precharge All command and ends when t_RPis met. Once t_RPis met, the bank

will be in the idle state.

6. Bank-specific; requires that the bank is idle and no bursts are in progress.

7. Not bank-specific; requires that all banks are idle and no bursts are in progress.

8. Not bank-specific; reset command is achieved through Mode Register Write command.

9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for

precharging.

10. A command other than NOP should not be issued to the same bank while a Read or Write burst with Auto Precharge is

enabled.

11. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled.

12. A Write command can be applied after the completion of the Read burst; otherwise, a BST must be used to end the Read

prior to asserting a Write command.

13. Not bank-specific. Burst Terminate (BST) command affects the most recent read/write burst started by the most recent

Read/Write command, regardless of bank.

14. A Read command may be applied after the completion of the Write burst; otherwise, a BST must be used to end the Write

prior to asserting a Read command.

15. If a Precharge command is issued to a bank in the idle state, t_RPshall still apply.

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Table of Current State Bank n - Command to Bank m ^1~6

Current State of

Bank n

Command for

Bank m

Operation

Next State for Bank m

Notes

Any

Idle

NOP

Any

Continue previous operation

Current State of Bank m

Any command allowed to Bank m

Select and activate row in Bank m

-

18

7

Activate

Active

Select column, and start read burst from Bank

m

Read

Reading

8

Write

Select column, and start write burst to Bank m

Deactivate row in bank or banks

Writing

8

9

Row Activating,

Active, or

Precharge

Precharging

Idle MR Reading or Active

MR Reading

MRR

BST

Read value from Mode Register

10,11,13

18

Read or Write burst terminate an ongoing

Read/Write from/to Bank m

Active

Select column, and start read burst from Bank

m

Read

Reading

8

Reading (Auto

precharge disabled)

Write

Select column, and start write burst to Bank m

Select and activate row in Bank m

Deactivate row in bank or banks

Writing

Active

8,14

Activate

Precharge

Precharging

9

8,16

8

Select column, and start read burst from Bank

m

Read

Reading

Writing (Auto

precharge disabled)

Write

Select column, and start write burst to Bank m

Select and activate row in Bank m

Deactivate row in bank or banks

Writing

Active

Activate

Precharge

Precharging

9

Select column, and start read burst from Bank

m

Read

Reading

8,15

Reading with Auto

precharge

Write

Select column, and start write burst to Bank m

Select and activate row in Bank m

Deactivate row in bank or banks

Writing

Active

8,14,15

Activate

Precharge

Precharging

9

Select column, and start read burst from Bank

m

Read

Reading

8,15,16

8,15

Writing with

Autoprecharge

Write

Activate

Precharge

Reset

Select column, and start write burst to Bank m

Select and activate row in Bank m

Deactivate row in bank or banks

Begin Device Auto-Initialization

Writing

Active

Precharging

Resetting

9

Power On

Resetting

12,17

MRR

Read value from Mode Register

Resetting MR Reading

Notes:

1. The table applies when both CKEn-1 and CKEn are HIGH, and after t_XSRor t_XPhas been met if the previous state was Self

Refresh or Power Down.

2. All states and sequences not shown are illegal or reserved.

3. Current State Definitions:

Idle: the bank has been precharged, and t_RPhas been met.

Active: a row in the bank has been activated, and t_RCDhas been met. No data bursts/accesses and no register accesses are

in progress.

Reading: a Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Writing: a Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. Refresh, Self Refresh, and Mode Register Write commands can only be issued when all bank are idle.

5. A Burst Terminate (BST) command cannot be issued to another bank; it applies to the bank represented by the current state

only.

6. The following states must not be interrupted by any executable command; NOP commands must be applied during each

clock cycle while in these states:

Idle MR Reading: starts with the registration of a MRR command and ends when t_MRRhas been met. Once t_MRRhas been

met, the bank will be in the idle state.

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Resetting MR Reading: starts with the registration of a MRR command and ends when t_MRRhas been met. Once t_MRRhas

been met, the bank will be in the resetting state.

Active MR Reading: starts with the registration of a MRR command and ends when t_MRRhas been met. Once t_MRRhas been

met, the bank will be in the active state.

MR Writing: starts with the registration of a MRW command and ends when t_MRWhas been met. Once t_MRWhas been met,

the bank will be in the idle state.

7. t_RRDmust be met between Activate command to Bank n and a subsequent Activate command to Bank m.

8. Reads or Writes listed in the Command column include Reads and Writes with Auto Precharge enabled and Reads and

Writes with Auto Precharge disabled.

9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for

precharging.

10. MRR is allowed during the Row Activating state (Row Activating starts with registration of an Activate command and ends

when t_RCDis met.)

11. MRR is allowed during the Precharging state. (Precharging starts with registration of a Precharge command and ends when

t_RPis met.

12. Not bank-specific; requires that all banks are idle and no bursts are in progress.

13. The next state for Bank m depends on the current state of Bank m (Idle, Row Activating, Precharging, or Active). The reader

shall note that the state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating state and

Precharging, the next state may be Active and Precharge dependent upon t_RCDand t_RPrespectively.

14. A Write command may be applied after the completion of the Read burst; otherwise a BST must be issued to end the Read

prior to asserting a Write command.

15. Read with auto precharge enabled or a Write with auto precharge enabled may be followed by any valid command to other

banks provided that the timing restrictions of auto precharge are followed.

16. A Read command may be applied after the completion of the Write burst; otherwise, a BST must be issued to end the Write

prior to asserting a Read command.

17. Reset command is achieved through Mode Register Write command.

18. BST is allowed only if a Read or Write burst is ongoing.

Table of Data Mask Truth Table

Name (Functional)

Write enable

DM

L

DQs

Valid

X

Note

1

Write inhibit

H

Note: Used to mask write data, provided coincident with the corresponding data.

Elite Semiconductor Memory Technology Inc

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M54D1G1664A

Simplified Bus Interface State Diagram

Note: All banks are precharged in the idle state.

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Publication Date : Apr. 2019

Revision : 1.0

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M54D1G1664A

PACKING DIMENSIONS

134-BALL

( 10x11.5 mm )

Pin #1

Index side

D

Seating plane

Detail "A"

"A"

D1

Solder ball

Detail "B"

Pin #1

Index

e

"B"

Symbol

Dimension in mm

Norm

Dimension in inch

Norm

Min

-

0.27

0.35

9.90

11.40

Max

1.00

0.37

0.45

10.10

11.60

Min

-

0.011

0.014

0.390

0.449

Max

0.039

0.015

0.018

0.398

0.457

A

A₁

Φ_b

D

-

0.32

0.40

10.00

11.50

0.013

0.016

0.394

0.453

E

D₁

E₁

e

5.85 BSC

10.40 BSC

0.65 BSC

0.230 BSC

0.409 BSC

0.026 BSC

Controlling dimension : Millimeter.

(Revision date : May 23 2018)

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Revision : 1.0 129/131

ESMT

M54D1G1664A

Revision History

Revision

Date

Description

0.1

2015.08.27

Original

1. Delete Preliminary

2. Add 134 ball BGA package

3. Add the specification of IDD

4. Correct typo

1.0

2019.04.29

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ESMT

M54D1G1664A

Important Notice

No part of this document may be reproduced or duplicated in any form or by

any means without the prior permission of ESMT.

The contents contained in this document are believed to be accurate at the

time of publication. ESMT assumes no responsibility for any error in this

document, and reserves the right to change the products or specification in

this document without notice.

The information contained herein is presented only as a guide or examples

for the application of our products. No responsibility is assumed by ESMT for

any infringement of patents, copyrights, or other intellectual property rights of

third parties which may result from its use. No license, either express, implied

or otherwise, is granted under any patents, copyrights or other intellectual

property rights of ESMT or others.

Any semiconductor devices may have inherently a certain rate of failure. To

minimize risks associated with customer's application, adequate design and

operating safeguards against injury, damage, or loss from such failure,

should be provided by the customer when making application designs.

ESMT's products are not authorized for use in critical applications such as,

but not limited to, life support devices or system, where failure or abnormal

operation may directly affect human lives or cause physical injury or property

damage. If products described here are to be used for such kinds of

application, purchaser must do its own quality assurance testing appropriate

to such applications.

Elite Semiconductor Memory Technology Inc

Publication Date : Apr. 2019

Revision : 1.0 131/131


型号：	M54D1G1664A
厂家：	ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
描述：	8M x 16 Bit x 8 Banks LPDDR2 SDRAM 动态存储器双倍数据速率光电二极管
文件：	总131页 (文件大小：5061K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M54D1G1664A [ESMT]

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