W78E054DDG [ETC]
8-bit microcontroller;
| 型号： | W78E054DDG |
| 厂家： | 
ETC |
| 描述： | 8-bit microcontroller 时钟 光电二极管 外围集成电路 装置 |
| 文件： | 总89页 (文件大小：1719K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78E054D/W78E052D Data Sheet
Table of Contents-
1
2
3
4
5
6
7
GENERAL DESCRIPTION ......................................................................................................... 4
FEATURES ................................................................................................................................. 5
PARTS INFORMATION LIST ..................................................................................................... 6
PIN CONFIGURATIONS............................................................................................................. 7
PIN DESCRIPTIONS .................................................................................................................. 9
BLOCK DIAGRAM .................................................................................................................... 11
FUNCTIONAL DESCRIPTION.................................................................................................. 12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
On-Chip Flash EPROM ................................................................................................ 12
I/O Ports........................................................................................................................ 12
Serial I/O....................................................................................................................... 12
Timers........................................................................................................................... 12
Interrupts....................................................................................................................... 12
Data Pointers ................................................................................................................ 12
Architecture................................................................................................................... 13
7.7.1 ALU ................................................................................................................................13
7.7.2 Accumulator ...................................................................................................................13
7.7.3 B Register.......................................................................................................................13
7.7.4 Program Status Word.....................................................................................................13
7.7.5 Scratch-pad RAM ...........................................................................................................13
7.7.6 Stack Pointer..................................................................................................................13
8
9
MEMORY ORGANIZATION...................................................................................................... 14
8.1
8.2
Program Memory (on-chip Flash)................................................................................. 14
Scratch-pad RAM and Register Map............................................................................ 14
8.2.1 Working Registers ..........................................................................................................16
8.2.2 Bit addressable Locations ..............................................................................................17
8.2.3 Stack ..............................................................................................................................17
SPECIAL FUNCTION REGISTERS.......................................................................................... 18
9.1 SFR Detail Bit Descriptions .......................................................................................... 20
10 INSTRUCTION.......................................................................................................................... 34
10.1 Instruction Timing.......................................................................................................... 42
11 POWER MANAGEMENT.......................................................................................................... 43
11.1 Idle Mode ...................................................................................................................... 43
11.2 Power Down Mode........................................................................................................ 43
12 RESET CONDITIONS............................................................................................................... 44
12.1 Sources of reset............................................................................................................ 44
12.1.1 External Reset..............................................................................................................44
12.1.2 Software Reset.............................................................................................................44
12.1.3 Watchdog Timer Reset.................................................................................................44
12.2 Reset State ................................................................................................................... 44
13 INTERRUPTS ........................................................................................................................... 45
13.1 Interrupt Sources .......................................................................................................... 45
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13.2 Priority Level Structure ................................................................................................. 45
13.3 Interrupt Response Time .............................................................................................. 47
13.4 Interrupt Inputs.............................................................................................................. 48
14 PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 49
14.1 Timer/Counters 0 & 1.................................................................................................... 49
14.2 Time-Base Selection..................................................................................................... 49
14.2.1 Mode 0 .........................................................................................................................49
14.2.2 Mode 1 .........................................................................................................................49
14.2.3 Mode 2 .........................................................................................................................50
14.2.4 Mode 3 .........................................................................................................................50
14.3 Timer/Counter 2............................................................................................................ 51
14.3.1 Capture Mode...............................................................................................................51
14.3.2 Auto-Reload Mode, Counting up ..................................................................................52
14.3.3 Auto-reload Mode, Counting Up/Down.........................................................................52
14.3.4 Baud Rate Generator Mode..........................................................................................53
15 WATCHDOG TIMER................................................................................................................. 54
16 SERIAL PORT........................................................................................................................... 55
16.1 MODE 0 ........................................................................................................................ 56
16.2 MODE 1 ........................................................................................................................ 57
16.3 MODE 2 ........................................................................................................................ 58
17 FLASH ROM CODE BOOT MODE SLECTION........................................................................ 61
18 ISP (IN-SYSTEM PROGRAMMING) ........................................................................................ 62
19 CONFIG BITS ........................................................................................................................... 66
20 ELECTRICAL CHARACTERISTICS......................................................................................... 68
20.1 Absolute Maximum Ratings.......................................................................................... 68
20.2 DC ELECTRICAL CHARACTERISTICS ...................................................................... 69
20.3 AC ELECTRICAL CHARACTERISTICS....................................................................... 70
20.3.1 Clock Input Waveform ..................................................................................................70
20.3.2 Program Fetch Cycle....................................................................................................71
20.3.3 Data Read Cycle ..........................................................................................................71
20.3.4 Data Write Cycle...........................................................................................................71
20.3.5 Port Access Cycle ........................................................................................................72
20.4 TIMING waveforms....................................................................................................... 73
20.4.1 Program Fetch Cycle....................................................................................................73
20.4.2 Data Read Cycle ..........................................................................................................73
20.4.3 Data Write Cycle...........................................................................................................74
20.4.4 Port Access Cycle ........................................................................................................74
20.4.5 Reset Pin Access Cycle ...............................................................................................75
21 APPLICATION CIRCUITS ........................................................................................................ 76
21.1 External Program Memory and Crystal ........................................................................ 76
21.2 Expanded External Data Memory and Oscillator.......................................................... 76
21.3 Internal Program Memory and Oscillator for EFT application ...................................... 77
21.4 Reference Value of XTAL............................................................................................. 77
22 APPLICATION NOTE ............................................................................................................... 78
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23 PACKAGE DIMENSIONS......................................................................................................... 83
23.1 40-pin DIP..................................................................................................................... 83
23.2 44-pin PLCC ................................................................................................................. 84
23.3 44-pin PQFP ................................................................................................................. 84
23.4 48-pin LQFP.................................................................................................................. 86
23.5 44-pin TQFP ................................................................................................................. 87
24 REVISION HISTORY................................................................................................................ 88
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1
GENERAL DESCRIPTION
The W78E054D/W78E052D series is an 8-bit microcontroller which can accommodate a wider fre-
quency range with low power consumption. The instruction set for the W78E054D/W78E052D series
is fully compatible with the standard 8052.
The W78E054D/W78E052D series contains 16K/8K bytes Flash EPROM programmable by hardware
writer; a 256 bytes RAM; four 8-bit bi-directional (P0, P1, P2, P3) and bit-addressable I/O ports; an
additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port.
These peripherals are supported by 8 sources 4-level interrupt capability. To facilitate programming
and verification, the Flash EPROM inside the W78E054D/W78E052D series allows the program
memory to be programmed and read electronically. Once the code is confirmed, the user can protect
the code for security.
The W78E054D/W78E052D series microcontroller has two power reduction modes, idle mode and
power-down mode, both of which are software selectable. The idle mode turns off the processor clock
but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for
minimum power consumption. The external clock can be stopped at any time and in any state without
affecting the processor. The W78E054D/W78E052D series contains In-System Programmable (ISP)
2KB LDROM for loader program, operating voltage from 3.3V to 5.5V.
Note: If the applied VDD is not stable, especially with long transition time of power on/off, it’s
recommended to apply an external RESET IC to the RST pin for improving the stability of sys-
tem.
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2
FEATURES
Fully static design 8-bit CMOS microcontroller
Optional 12T or 6T mode
12T Mode, 12 clocks per machine cycle operation (default), Speed up to 40 MHz/5V
6T Mode, 6 clocks per machine cycle operation set by the writer, Speed up to 20 MHz/5V
Wide supply voltage of 2.4V to 5.5V
Temperature grade is (-40oC~85oC)
Pin and Instruction-sets compatible with MCS-51
256 bytes of on-chip scratchpad RAM
16K/8K bytes electrically erasable/programmable Flash EPROM
2K bytes LDROM support ISP function (Reference Application Note)
64KB program memory address space
64KB data memory address space
Four 8-bit bi-directional ports
8-sources, 4-level interrupt capability
One extra 4-bit bit-addressable I/O port, additional INT2/
INT3 (available on PQFP, PLCC and
LQFP package)
Three 16-bit timer/counters
One full duplex serial port
Watchdog Timer
EMI reduction mode
Software Reset
Built-in power management with idle mode and power down mode
Code protection
Packages: DIP40, PLCC44, PQFP44, LQFP48, TQFP44
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3
PARTS INFORMATION LIST
LDROM
SIZE
APROM
SIZE
Temperature
PART NO.
W78E054DDG
W78E054DPG
RAM
PACKAGE
grade
2K Bytes
14K Bytes
16K Bytes
14K Bytes
16K Bytes
14K Bytes
16K Bytes
14K Bytes
16K Bytes
14K Bytes
16K Bytes
DIP-40 Pin
PLCC-44 Pin
PQFP-44 Pin
TQFP-44 Pin
LQFP-48 Pin
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
0
2K Bytes
0
2K Bytes
W78E054DFG
W78E054DTG
W78E054DLG
0
2K Bytes
256
Bytes
0
2K Bytes
0
W78E052DDG
W78E052DPG
W78E052DFG
W78E052DTG
W78E052DLG
DIP-40 Pin
PLCC-44 Pin
PQFP-44 Pin
TQFP-44 Pin
LQFP-48 Pin
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
2K Bytes
8K Bytes
Table 3–1: Lad Free (RoHS) Parts information list
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4
PIN CONFIGURATIONS
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, P1.0
VDD
2
T2EX, P1.1
P1.2
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
3
4
P1.3
5
P1.4
6
P1.5
7
P1.6
8
P1.7
9
RST
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
XTAL1
VSS
7
39
P1.5
P1.6
P0.4, AD4
8
38
P0.5, AD5
9
37
P1.7
P0.6, AD6
10
11
12
13
14
15
16
17
36
RST
P0.7, AD7
35
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
EA
PLCC 44-pin
34
P4.1
33
ALE
32
PSEN
31
P2.7, A15
30
P2.6, A14
29
P2.5, A13
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W78E054D/W78E052D Data Sheet
1
33
P1.5
P1.6
P0.4, AD4
2
32
P0.5, AD5
3
31
P1.7
P0.6, AD6
4
30
RST
P0.7, AD7
5
29
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
EA
PQFP 44-pin
TQFP 44-pin
6
28
P4.1
7
27
ALE
8
26
PSEN
9
25
P2.7, A15
10
11
24
P2.6, A14
23
P2.5, A13
1
36
P1.5
P1.6
P1.7
RST
P3.0
NC
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
2
35
3
34
4
33
5
32
6
31
INT2, P4.3
LQFP 48-pin
7
30
P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
NC
8
29
9
28
10
11
12
27
26
25
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5
PIN DESCRIPTIONS
SYMBOL
TYPE DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address
I
EA
EA
and data will not be present on the bus if
pin is high and the program coun-
ter is within internal ROM area. Otherwise they will be present on the bus.
PSEN
PROGRAM STORE ENABLE:
enables the external ROM data onto the
O H Port 0 address/data bus during fetch and MOVC operations. When internal ROM
PSEN
PSEN
access is performed, no
strobe signal outputs from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that sepa-
rates the address from the data on Port 0.
ALE
O H
I L
I
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
RST
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an ex-
ternal clock.
XTAL1
XTAL2
VSS
O
I
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential
VDD
I
POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a
multiplexed low order address/data bus during accesses to external memory.
I/O D
I/O H
I/O H
P0.0P0.7
P1.0P1.7
P2.0P2.7
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2 (P1.0): Timer/Counter 2 external count input
T2EX (P1.1): Timer/Counter 2 Reload/Capture control
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
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Pin Description, continued
SYMBOL
TYPE DESCRIPTIONS
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have al-
ternate functions, which are described below:
RXD (P3.0): Serial Port 0 input
TXD (P3.1): Serial Port 0 output
INT0 (P3.2) : External Interrupt 0
I/O H
P3.0P3.7
INT1 (P3.3) : External Interrupt 1
T0 (P3.4) : Timer 0 External Input
T1 (P3.5) : Timer 1 External Input
WR
RD
(P3.6) : External Data Memory Write Strobe
(P3.7) : External Data Memory Read Strobe
PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are
alternative function pins. It can be used as general I/O port or external interrupt
I/O H
P4.0P4.3
input sources (INT2/
INT3).
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain.
In application if MCU pins need external pull-up, it is recommended to add a pull-up resistor
(10K) between pin and power (VDD) instead of directly wiring pin to VDD for enhancing EMC.
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W78E054D/W78E052D Data Sheet
6
BLOCK DIAGRAM
P1.0
|
P1.7
Port 1
Port 1
Latch
P0.0
|
P0.7
Port 0
Latch
ACC
B
Port 0
T1 Register
T2 Register
Interrupt
DPTR
Stack
Pointer
PSW
ALU
Timer
1
Timer Reg.
PC
Timer
0
SFR & RAM
Address
Incrementor
Addr. Reg.
Timer
2
Instruction
Decoder
&
256 bytes
RAM & SFR
UART
Flash EPROM
Sequencer
P3.0
|
P3.7
Port 3
Port 3
Latch
P2.0
|
P2.7
Port 2
Latch
Port 2
Bus & Lock
Controller
Port 4
Latch
P4.0
|
Port 4
P4.3
Oscillator
Selecter
Power Control
Watchdog
Timer
Reset Block
Oscillator
VCC GND
XTAL1
XTAL2
ALE /PSEN
RST
Figure 6–1 W78E054D/W78E052D Block Diagram
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7
FUNCTIONAL DESCRIPTION
The W78E054D/W78E052D series architecture consists of a core controller surrounded by various
registers, five general purpose I/O ports, 16K/8K flash EPROM, 2K FLASH EPROM for ISP function,
256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different op-
codes and references both a 64K program address space and a 64K data storage space.
7.1 On-Chip Flash EPROM
The W78E054D/W78E052D series include one 16K/8K bytes of main Flash EPROM for application
program.
7.2 I/O Ports
The W78E054D/W78E052D series has four 8-bit ports and one extra 4-bit port. Port 0 can be used as
an Address/Data bus when external program is running or external memory/device is accessed by
MOVC or MOVX instruction. In these cases, it has strong pull-ups and pull-downs, and does not need
any external pull-ups. Otherwise it can be used as a general I/O port with open-drain circuit. Port 2 is
used chiefly as the upper 8-bits of the Address bus when port 0 is used as an address/data bus. It also
has strong pull-ups and pull-downs when it serves as an address bus. Port1 and 3 act as I/O ports
with alternate functions. Port 4 is only available on PLCC/PQFP/LQFP package type. It serves as a
general purpose I/O port as Port 1 and Port 3. Another bit-addressable bidirectional I/O port P4. P4.3
and P4.2 are alternative function pins. It can be used as general I/O port or external interrupt input
sources (INT2/INT3).
7.3 Serial I/O
The W78E054D/W78E052D series have one serial port that is functionally similar to the serial port of
the original 8032 family. However the serial port on the W78E054D/W78E052D series can operate in
different modes in order to obtain timing similarity as well.
7.4 Timers
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide con-
trol functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the 8051 CPU. Timer 2 is a special feature
of the W78E054D/W78E052D: it is a 16-bit timer/counter that is configured and controlled by the
T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as
an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes:
capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the
same as that of Timers 0 and 1.
7.5 Interrupts
The Interrupt structure in the W78E054D/W78E052D is slightly different from that of the standard
8052. Due to the presence of additional features and peripherals, the number of interrupt sources and
vectors has been increased. The W78E054D/W78E052D provides 8 interrupt resources with four pri-
ority level, including four external interrupt sources, three timer interrupts, serial I/O interrupts.
7.6 Data Pointers
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W78E054D/W78E052D Data Sheet
The data pointer of W78E054D/W78E052D series is same as standard 8052 that have one 16-bit Da-
ta Pointer (DPTR).
7.7 Architecture
The W78E054D/W78E052D series are based on the standard 8052 device. It is built around an 8-bit
ALU that uses internal registers for temporary storage and control of the peripheral devices. It can ex-
ecute the standard 8052 instruction set.
7.7.1 ALU
The ALU is the heart of the W78E054D/W78E052D series. It is responsible for the arithmetic and logi-
cal functions. It is also used in decision making, in case of jump instructions, and is also used in calcu-
lating jump addresses. The user cannot directly use the ALU, but the Instruction Decoder reads the
op-code, decodes it, and sequences the data through the ALU and its associated registers to generate
the required result. The ALU mainly uses the ACC which is a special function register (SFR) on the
chip. Another SFR, namely B register is also used Multiply and Divide instructions. The ALU generates
several status signals which are stored in the Program Status Word register (PSW).
7.7.2 Accumulator
The Accumulator (ACC) is the primary register used in arithmetic, logical and data transfer operations
in the W78E054D/W78E052D series. Since the Accumulator is directly accessible by the CPU, most
of the high speed instructions make use of the ACC as one argument.
7.7.3 B Register
This is an 8-bit register that is used as the second argument in the MUL and DIV instructions. For all
other instructions it can be used simply as a general purpose register.
7.7.4 Program Status Word
This is an 8-bit SFR that is used to store the status bits of the ALU. It holds the Carry flag, the Auxiliary
Carry flag, General purpose flags, the Register Bank Select, the Overflow flag, and the Parity flag.
7.7.5 Scratch-pad RAM
The W78E054D/W78E052D series has a 256 byte on-chip scratch-pad RAM. This can be used by the
user for temporary storage during program execution. A certain section of this RAM is bit addressable,
and can be directly addressed for this purpose.
7.7.6 Stack Pointer
The W78E054D/W78E052D series has an 8-bit Stack Pointer which points to the top of the Stack.
This stack resides in the Scratch Pad RAM in the W78E054D/W78E052D. Hence the size of the stack
is limited by the size of this RAM.
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W78E054D/W78E052D Data Sheet
8
MEMORY ORGANIZATION
The W78E054D/W78E052D series separate the memory into two separate sections, the Program
Memory and the Data Memory. The Program Memory is used to store the instruction op-codes, while
the Data Memory is used to store data or for memory mapped devices.
FFH
FFFFH
3FFFH
3FFFH
Indirect
Addressing
RAM
SFRs Direct
Addressing
Only
2KB
LDROM
3800H
80H
7FH
Direct &
Indirect
Addressing
RAM
64K Bytes
External
Data
00H
16KB
APROM
14K/8KB
APROM
or
memory
0000H
0000H
0000H
Figure 8–1 Memory Map
8.1 Program Memory (on-chip Flash)
The Program Memory on the W78E054D/W78E052D series can be up to 16K/8K bytes (2K bytes for
ISP F/W, share with the W78E054D) long. All instructions are fetched for execution from this memory
area. The MOVC instruction can also access this memory region.
8.2 Scratch-pad RAM and Register Map
As mentioned before the W78E054D/W78E052D series have separate Program and Data Memory
areas. There are also several Special Function Registers (SFRs) which can be accessed by software.
The SFRs can be accessed only by direct addressing, while the on-chip RAM can be accessed by
either direct or indirect addressing.
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W78E054D/W78E052D Data Sheet
FFH
SFR
Indirect
RAM
Direct
Addressing
Only
Addressing
80H
7FH
Direct
&
Indirect
RAM
Addressing
00H
256 bytes RAM and SFR Data Memory Space
Figure 8–2 W78E054D/W78E052D RAM and SFR Memory Map
Since the scratch-pad RAM is only 256bytes it can be used only when data contents are small. There
are several other special purpose areas within the scratch-pad RAM. These are illustrated in next fig-
ure.
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W78E054D/W78E052D Data Sheet
FFH
Indirect RAM
Direct RAM
80H
7FH
30H
2FH 7F 7E 7D 7C 7B 7A 79
2EH 77 76 75 74 73 72 71
2DH 6F 6E 6D 6C 6B 6A 69
2CH 67 66 65 64 63 62 61
2BH 5F 5E 5D 5C 5B 5A 59
2AH 57 56 55 54 53 52 51
29H 4F 4E 4D 4C 4B 4A 49
28H 47
46 45
41
27H 3F 3E 3D 3C 3B 3A 39
26H 34 33
25H 2F 2E 2D 2C 2B 2A 29
24H 27 26 25 24 23 22 21
23H 1F 1E 1D 1C 1B 1A 19
22H 17 16 15 14 13 12 11
21H 0F 0E 0D 0C 0B 0A 09
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
44
43
42
37
36
35
32
31
20H 07
1FH
06
05
04
03
02
01
Bank 3
18H
17H
Bank 2
Bank 1
Bank 0
10H
0FH
08H
07H
00H
Figure 8–3 Scratch-pad RAM
8.2.1 Working Registers
There are four sets of working registers, each consisting of eight 8-bit registers. These are termed as
Banks 0, 1, 2, and 3. Individual registers within these banks can be directly accessed by separate in-
structions. These individual registers are named as R0, R1, R2, R3, R4, R5, R6 and R7. However, at
one time the W78E054D/W78E052D series can work with only one particular bank. The bank selec-
tion is done by setting RS1-RS0 bits in the PSW. The R0 and R1 registers are used to store the ad-
dress for indirect accessing.
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W78E054D/W78E052D Data Sheet
8.2.2 Bit addressable Locations
The Scratch-pad RAM area from location 20h to 2Fh is byte as well as bit addressable. This means
that a bit in this area can be individually addressed. In addition some of the SFRs are also bit ad-
dressable. The instruction decoder is able to distinguish a bit access from a byte access by the type of
the instruction itself. In the SFR area, any existing SFR whose address ends in a 0 or 8 is bit address-
able.
8.2.3 Stack
The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP),
which stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the re-
turn address is placed on the stack. There is no restriction as to where the stack can begin in the
RAM. By default however, the Stack Pointer contains 07h at reset. The user can then change this to
any value desired. The SP will point to the last used value. Therefore, the SP will be incremented and
then address saved onto the stack. Conversely, while popping from the stack the contents will be read
first, and then the SP is decreased.
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W78E054D/W78E052D Data Sheet
9
SPECIAL FUNCTION REGISTERS
The W78E054D/W78E052D series uses Special Function Registers (SFRs) to control and monitor
peripherals and their Modes. The SFRs reside in the register locations 80-FFh and are accessed by
direct addressing only. Some of the SFRs are bit addressable. This is very useful in cases where us-
ers wish to modify a particular bit without changing the others. The SFRs that are bit addressable are
those whose addresses end in 0 or 8. The W78E054D/W78E052D series contain all the SFRs present
in the standard 8052. However some additional SFRs are added. In some cases the unused bits in the
original 8052, have been given new functions. The list of the SFRs is as follows.
F8
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
F0 B
E8
E0 ACC
D8 P4
D0 PSW
C8 T2CON
C0 XICON
B8 IP
T2MOD
RCAP2L RCAP2H TL2
SFRAL
TH2
SFRAH
SFRRD
SFRCN
EAPAGE CHPCON
IPH
B0 P3
A8 IE
A0 P2
98 SCON
90 P1
SBUF
88 TCON
80 P0
TMOD
SP
TL0
TL1
TH0
TH1
AUXR
WDTC
PCON
8F
87
DPL
DPH
P0UPR
Table 9–1: Special Function Register Location Table
Note:
1. The SFRs in the column with dark borders are bit-addressable
2. The table is condensed with eight locations per row. Empty locations indicate that these are no reg-
isters at these addresses. When a bit or register is not implemented, it will read high.
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W78E054D/W78E052D Data Sheet
Special Function Registers:
SYMBOL
DEFINITION
ADDRESS MSB
BIT ADDRESS, SYMBOL
LSB
(F0)
RESET
B
B register
F0H
E0H
D8H
D0H
(F7)
(E7)
(F6)
(E6)
(F5)
(E5)
(F4)
(E4)
(F3)
(E3)
INT2
(F2)
(E2)
INT3
(F1)
(E1)
0000 0000B
0000 0000B
0000 1111B
0000 0000B
ACC
P4
Accumulator
Port 4
(E0)
PSW
Program status word
(D7)
CY
(D6)
AC
(D5)
F0
(D4)
RS1
(D3)
RS0
(D2)
OV
(D1)
F1
(D0)
P
TH2
T2 reg. high
CDH
CCH
CBH
CAH
C9
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
TL2
T2 reg. low
RCAP2H
RCAP2L
T2MOD
T2CON
T2 capture low
T2 capture high
Timer 2 Mode
Timer 2 control
DCEN
C8H
(CF)
TF2
(CE)
(CD)
(CC)
(CB)
(CA)
TR2
(C9)
(C8)
EXF2
RCLK
TCLK
EXEN2
C/T2
CP/RL2
SFRCN
SFRRD
SFRAH
SFRAL
XICON
CHPCON
EAPAGE
IP
SFR program of control
C7H
C6H
NOE
NCE
CTRL3
CTRL2
CTRL1
CTRL0
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
1100 0000B
SFR program of data register
SFR program of address high byte C5H
SFR program of address low byte
External interrupt control
Chip control
C4H
C0H
BFH
BEH
B8H
PX3
EX3
-
IE3
IT3
-
PX2
-
EX2
-
IE2
IT2
SWRST
ISP
ENP
Erase page operation modes
Interrupt priority
EAPG1
EAPG0
(BF)
-
(BE)
-
(BD)
PT2
(BC)
PS
(BB)
PT1
(BA)
PX1
(B9)
PT0
(B8)
PX0
IPH
P3
Interrupt priority High
Port 3
B7H
B0H
0000 0000B
1111 1111B
(B7)
RD
(B6)
WR
(B5)
T1
(B4)
T0
(B3)
(B2)
(B1)
TXD
(B0)
INT1
INT0
RXD
IE
Interrupt enable
Port 2
A8H
A0H
(AF)
EA
(AE)
-
(AD)
ET2
(AC)
ES
(AB)
ET1
(AA)
EX1
(A9)
ET0
(A8)
EX0
0100 0000B
1111 1111B
P2
(A7)
A15
(A6)
A14
(A5)
A13
(A4)
A12
(A3)
A11
(A2)
A10
(A1)
A9
(A0)
A8
SBUF
SCON
Serial buffer
Serial control
99H
98H
0000 0000B
0000 0000B
(9F)
(9E)
(9D)
SM2
(9C)
REN
(9B)
TB8
(9A)
RB8
(99)
TI
(98)
RI
SM0/FE SM1
P1
Port 1
90H
(97)
(96)
(95)
(94)
(93)
(92)
(91)
(90)
T2
1111 1111B
T2EX
WDTC
AUXR
TH1
Watchdog control
Auxiliary
8FH
8EH
8DH
8CH
8BH
8AH
89H
88H
ENW
-
CLRW
-
WIDL
-
-
-
-
PS2
PS1
PS0
0000 0000B
ALEOFF 0000 0110B
0000 0000B
Timer high 1
Timer high 0
Timer low 1
Timer low 0
Timer mode
Timer control
TH0
0000 0000B
TL1
0000 0000B
TL0
0000 0000B
TMOD
TCON
GATE
C/T
M1
M0
GATE
C/T
M1
M0
0000 0000B
0000 0000B
(8F)
TF1
(8E)
TR1
(8D)
TF0
(8C)
TR0
(8B)
IE1
(8A)
IT1
(89)
IE0
(88)
IT0
PCON
P0UPR
DPH
DPL
Power control
87H
86H
83H
82H
81H
80H
SMOD
-
SMOD0
-
-
-
POR
-
GF1
-
GF0
-
PD
-
IDL
0011 0000B
0000 0001B
0000 0000B
0000 0000B
0000 0111B
1111 1111B
Port 0 pull up option Register
Data pointer high
Data pointer low
Stack pointer
P0UP
SP
P0
Port 0
(87)
(86)
(85)
(84)
(83)
(82)
(81)
(80)
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W78E054D/W78E052D Data Sheet
9.1 SFR Detail Bit Descriptions
Port 0
Bit:
7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Mnemonic: P0
BIT NAME
Address: 80h
FUNCTION
7-0 P0.[7:0]
Port 0 is an open-drain bi-directional I/O port if SFR P0UPR.0 (bit P0UP) clear to “0”, and
when SFR P0UPR.0 (bit P0UP) set to “1”, Port 0 pins are internally pulled-up.
This port also provides a multiplexed low order address/data bus during accesses to external
memory.
STACK POINTER
Bit:
7
6
5
4
3
2
1
0
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
Mnemonic: SP
BIT NAME
Address: 81h
FUNCTION
7-0 SP.[7:0]
The Stack Pointer stores the Scratch-pad RAM address where the stack begins. In other
words it always points to the top of the stack.
DATA POINTER LOW
Bit:
7
6
5
4
3
2
1
0
DPL.7
DPL.6
DPL.5
DPL.4
DPL.3
DPL.2
DPL.1
DPL.0
Mnemonic: DPL
Address: 82h
BIT
NAME
FUNCTION
This is the low byte of the standard 8052 16-bit data pointer.
7-0
DPL.[7:0]
DATA POINTER HIGH
Bit:
7
6
5
4
3
2
1
0
DPH.7
DPH.6
DPH.5
DPH.4
DPH.3
DPH.2
DPH.1
DPH.0
Mnemonic: DPH
Address: 83h
BIT
NAME
FUNCTION
This is the high byte of the standard 8052 16-bit data pointer.
7-0
DPH.[7:0]
Port 0 Pull Up Option Register
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
P0UP
Mnemonic: P0UPR
Address: 86h
BIT NAME
FUNCTION
0
P0UP
0: Port 0 pins are open-drain.
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W78E054D/W78E052D Data Sheet
1: Port 0 pins are internally pulled-up. Port 0 is structurally the same as Port 2.
Power Control
Bit:
7
6
5
-
4
3
2
1
0
SMOD
SMOD0
POR
GF1
GF0
PD
IDL
Mnemonic: PCON
Address: 87h
BIT NAME
FUNCTION
7
6
SMOD
1: This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1.
SMOD
0
0: Framing Error Detection Disable. SCON.7 (SM0/FE) bit is used as SM0 (stand-
ard 8052 function).
1: Framing Error Detection Enable. SCON.7 (SM0/FE) bit is used to reflect as
Frame Error (FE) status flag.
5
4
-
Reserved
POR
0: Cleared by software.
1: Set automatically when a power-on reset has occurred.
General purpose user flags.
General purpose user flags.
3
2
1
GF1
GF0
PD
1: The CPU goes into the POWER DOWN mode. In this mode, all the clocks are
stopped and program execution is frozen.
0
IDL
1: The CPU goes into the IDLE mode. In this mode, the clocks CPU clock stopped,
so program execution is frozen. But the clock to the serial, timer and interrupt
blocks is not stopped, and these blocks continue operating.
Timer Control
Bit:
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic: TCON
Address: 88h
BIT NAME
FUNCTION
7
TF1
Timer 1 Overflow Flag. This bit is set when Timer 1 overflows. It is cleared auto-
matically when the program does a timer 1 interrupt service routine. Software can
also set or clear this bit.
6
5
TR1
TF0
Timer 1 Run Control. This bit is set or cleared by software to turn timer/counter on
or off.
Timer 0 Overflow Flag. This bit is set when Timer 0 overflows. It is cleared auto-
matically when the program does a timer 0 interrupt service routine. Software can
also set or clear this bit.
4
3
TR0
IE1
Timer 0 Run Control. This bit is set or cleared by software to turn timer/counter on
or off.
Interrupt 1 Edge Detect Flag: Set by hardware when an edge/level is detected on
INT1. This bit is cleared by hardware when the service routine is vectored to only if
the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
2
IT1
Interrupt 1 Type Control. Set/cleared by software to specify falling edge/ low level
triggered external inputs.
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W78E054D/W78E052D Data Sheet
1
0
IE0
IT0
Interrupt 0 Edge Detect Flag. Set by hardware when an edge/level is detected
onINT0 . This bit is cleared by hardware when the service routine is vectored to
only if the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
Interrupt 0 Type Control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
Timer Mode Control
Bit:
7
6
5
4
3
2
1
0
GATE
M1
M0
GATE
M1
M0
C/T
C/T
TIMER1
TIMER0
Mnemonic: TMOD
Address: 89h
BIT NAME
FUNCTION
7
GATE
Gating control: When this bit is set, Timer/counter 1 is enabled only while the INT1
pin is high and the TR1 control bit is set. When cleared, the INT1 pin has no effect,
and Timer 1 is enabled whenever TR1 control bit is set.
6
Timer or Counter Select: When clear, Timer 1 is incremented by the internal clock.
When set, the timer counts falling edges on the T1 pin.
C/T
5
4
3
M1
Timer 1 mode select bit 1. See table below.
Timer 1 mode select bit 0. See table below.
M0
GATE
Gating control: When this bit is set, Timer/counter 0 is enabled only while the INT0
pin is high and the TR0 control bit is set. When cleared, the INT0 pin has no ef-
fect, and Timer 0 is enabled whenever TR0 control bit is set.
2
Timer or Counter Select: When clear, Timer 0 is incremented by the internal clock.
When set, the timer counts falling edges on the T0 pin.
C/T
1
0
M1
M0
Timer 0 mode select bit 1. See table below.
Timer 0 mode select bit 0. See table below.
M1, M0: Mode Select bits:
MODE
M1
0
M0
0
Mode 0: 13-bit timer/counter TLx serves as 5-bit pre-scale.
Mode 1: 16-bit timer/counter, no pre-scale.
0
1
Mode 2: 8-bit timer/counter with auto-reload from THx.
1
0
Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer0
control bits. TH0 is an 8-bit timer only controlled by Timer1 control bits. (Timer 1)
Timer/Counter 1 is stopped.
1
1
Timer 0 LSB
Bit:
7
6
5
4
3
2
1
0
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
Mnemonic: TL0
Address: 8Ah
BIT NAME
FUNCTION
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W78E054D/W78E052D Data Sheet
7-0 TL0.[7:0] Timer 0 LSB.
Timer 1 LSB
Bit:
7
6
5
4
3
2
1
0
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
Mnemonic: TL1
Address: 8Bh
BIT NAME
FUNCTION
7-0 TL1.[7:0] Timer 1 LSB.
Timer 0 MSB
Bit:
7
6
5
4
3
2
1
0
TH0.7
TH0.6
TH0.5
TH0.4
TH0.3
TH0.2
TH0.1
TH0.0
Mnemonic: TH0
Address: 8Ch
BIT NAME
FUNCTION
7-0 TH0.[7:0] Timer 0 MSB.
Timer 1 MSB
Bit:
7
6
5
4
3
2
1
0
TH1.7
TH1.6
TH1.5
TH1.4
TH1.3
TH1.2
TH1.1
TH1.0
Mnemonic: TH1
Address: 8Dh
BIT NAME
FUNCTION
7-0 TH1.[7:0] Timer 1 MSB.
AUXR
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
ALE_OFF
Mnemonic: AUXR
BIT NAME
Address: 8Eh
FUNCTION
ALE_OFF
0
1: Disenable ALE output
0: Enable ALE output
Watchdog Timer Control Register
Bit:
7
6
5
4
3
2
1
0
ENW
CLRW
WIDL
-
-
PS2
PS1
PS0
Mnemonic: WDTC
Address: 8FH
BIT NAME
FUNCTION
Enable watch-dog if set.
7
ENW
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W78E054D/W78E052D Data Sheet
6
5
CLRW
WIDL
Clear watch-dog timer and Pre-scalar if set. This flag will be cleared automatical-
ly.
If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is
disabled under IDLE mode. Default is cleared.
2-0 PS2-0
Watch-dog Pre-scalar timer select. Pre-scalar is selected when set PS20 as fol-
lows:
PS2 PS1 PS0
PRE-SCALAR SELECT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
8
4
16
32
64
128
256
Port 1
Bit:
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Mnemonic: P1
BIT NAME
Address: 90h
FUNCTION
7-0 P1.[7:0]
General purpose I/O port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is
read.
Serial Port Control
Bit:
7
6
5
4
3
2
1
0
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
Mnemonic: SCON
Address: 98h
BIT NAME
FUNCTION
7
SM0/FE
Serial port mode select bit 0 or Framing Error Flag: The SMOD0 bit in PCON
SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is
described below. When used as FE, this bit will be set to indicate an invalid stop
bit. This bit must be manually cleared in software to clear the FE condition.
6
5
SM1
SM2
Serial Port mode select bit 1. See table below.
Multiple processors communication. Setting this bit to 1 enables the multiproces-
sor communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1,
then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if
SM2 = 1, then RI will not be activated if a valid stop bit was not received. In
mode 0, the SM2 bit controls the serial port clock. If set to 0, then the serial port
runs at a divide by 12 clock of the oscillator. This gives compatibility with the
standard 8052. When set to 1, the serial clock become divide by 4 of the oscilla-
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W78E054D/W78E052D Data Sheet
tor clock. This results in faster synchronous serial communication.
4
REN
Receive enable:
0: Disable serial reception.
1: Enable serial reception.
3
2
1
TB8
RB8
TI
This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared
by software as desired.
In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is
the stop bit that was received. In mode 0 it has no function.
Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time
in mode 0, or at the beginning of the stop bit in all other modes during serial
transmission. This bit must be cleared by software.
Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time
in mode 0, or halfway through the stop bits time in the other modes during serial
reception. However the restrictions of SM2 apply to this bit. This bit can be
cleared only by software.
0
RI
SM1, SM0: Mode Select bits:
Mode
SM0
SM1
Description
Length
Baud Rate
0
1
2
3
0
0
1
1
0
1
0
1
Synchronous
Asynchronous
Asynchronous
Asynchronous
8
Tclk divided by 4 or 12
Variable
10
11
11
Tclk divided by 32 or 64
Variable
Serial Data Buffer
Bit:
7
6
5
4
3
2
1
0
SBUF.7
SBUF.6
SBUF.5
SBUF.4
SBUF.3
SBUF.2
SBUF.1
SBUF.0
Mnemonic: SBUF
BIT NAME
7~0 SBUF
Address: 99h
FUNCTION
Serial data on the serial port is read from or written to this location. It actually
consists of two separate internal 8-bit registers. One is the receive resister, and
the other is the transmit buffer. Any read access gets data from the receive data
buffer, while write access is to the transmit data buffer.
Port 2
Bit:
7
6
5
4
3
2
1
0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
Mnemonic: P2
BIT NAME
Address: A0h
FUNCTION
7-0 P2.[7:0]
Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the
upper address bits for accesses to external memory.
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W78E054D/W78E052D Data Sheet
Interrupt Enable
Bit:
7
6
-
5
4
3
2
1
0
EA
ET2
ES
ET1
EX1
ET0
EX0
Mnemonic: IE
Address: A8h
BIT NAME
FUNCTION
7
6
5
4
3
2
1
0
EA
Global enable. Enable/Disable all interrupts.
Reserved
-
ET2
ES
Enable Timer 2 interrupt.
Enable Serial Port 0 interrupt.
Enable Timer 1 interrupt.
Enable external interrupt 1.
Enable Timer 0 interrupt.
Enable external interrupt 0.
ET1
EX1
ET0
EX0
Port 3
Bit:
7
6
5
4
3
2
1
0
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
Mnemonic: P3
Address: B0h
P3.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alter-
nate functions are described below:
BIT NAME
FUNCTION
RD
7
P3.7
6
5
4
3
P3.6
P3.5
P3.4
P3.3
WR
T1
T0
INT1
2
P3.2
INT0
TX
1
0
P3.1
P3.0
RX
Interrupt High Priority
Bit:
7
6
5
4
3
2
1
0
IPH.7
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
Mnemonic: IPH
Address: B7h
BIT NAME
FUNCTION
1: Interrupt high priority of INT3 is highest priority level.
7
IPH.7
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W78E054D/W78E052D Data Sheet
6
5
4
3
2
1
0
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
1: Interrupt high priority of INT2 is highest priority level.
1: Interrupt high priority of Timer 2 is highest priority level.
1: Interrupt high priority of Serial Port 0 is highest priority level.
1: Interrupt high priority of Timer 1 is highest priority level.
1: Interrupt high priority of External interrupt 1 is highest priority level.
1: Interrupt high priority of Timer 0 is highest priority level.
1: Interrupt high priority of External interrupt 0 is highest priority level.
Interrupt Priority
Bit:
7
6
5
4
3
2
1
0
-
-
PT2
PS
PT1
PX1
PT0
PX0
Mnemonic: IP
Address: B8h
BIT NAME
FUNCTION
5
4
3
2
1
0
PT2
PS
1: Interrupt priority of Timer 2 is higher priority level.
1: Interrupt priority of Serial port 0 is higher priority level.
1: Interrupt priority of Timer 1 is higher priority level.
PT1
PX1
PT0
PX0
1: Interrupt priority of External interrupt 1 is higher priority level.
1: Interrupt priority of Timer 0 is higher priority level.
1: Interrupt priority of External interrupt 0 is higher priority level.
EAPAGE ERASE PAGE Operation Modes
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EAPG1
EAPG0
Mnemonic: EAPAGE
Address: BD
BIT NAME
FUNCTION
1
0
EAPG1
EAPG0
1: To ease PAGE1 when ease command is set. (LDROM)
1: To ease PAGE0 when ease command is set. (APROM)
;CPU Clock = 12MHz/12T mode
READ_TIME
PROGRAM_TIME
ERASE_TIME
Erase_APROM:
mov
EQU
EQU
EQU
1
50
5000
EAPAGE,#01h
;set EAPAGE is APROM
mov
SFRCN,#ERASE_ROM
mov
mov
TL0,#LOW (65536-ERASE_TIME)
TH0,#HIGH(65536-ERASE_TIME)
TR0
setb
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W78E054D/W78E052D Data Sheet
mov
mov
CHPCON,#00000011b
EAPAGE,#00h
;clear EAPAGE
clr
clr
TF0
TR0
ret
Erase_LDROM:
mov
EAPAGE,#02h
;set EAPAGE is LDROM
mov
SFRCN,#ERASE_ROM
mov
mov
TL0,#LOW (65536-ERASE_TIME)
TH0,#HIGH(65536-ERASE_TIME)
TR0
setb
mov
CHPCON,#00000011b
mov
EAPAGE,#00h
;clear EAPAGE
clr
clr
TF0
TR0
ret
Chip Control
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
ISP
ENP
SWRST
Mnemonic: CHPCON
Address: BFh
Bit
Name
Function
7
SWRST
When this bit is set to 1 and ENP is set to 1. It will enforce microcontroller
reset to initial condition just like power on reset. This action will re-boot the
microcontroller and start to normal operation.
The ISP function Select. When this bit is set to 1 and ENP is set to 1. It will run ISP
function.
1
0
ISP
ENP
When this bit is set to 1 and SWRST is set to 1. It will enforce microcontrol-
ler reset to initial condition just like power on reset.
When this bit is set to 1 and ISP is set to 1. It will run ISP function
Note1: CHPCON = 0x81, it is Software reset
Note2: CHPCON = 0x03, ISP function is enabled.
External Interrupt Control
Bit:
7
6
5
4
3
2
1
0
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
Mnemonic: XICON
Address: C0h
BIT NAME
FUNCTION
7
6
PX3
EX3
External interrupt 3 priority is higher if set this bit to 1
Enable External interrupt 3 if set this bit to 1
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W78E054D/W78E052D Data Sheet
5
4
IE3
IT3
If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detect-
ed/serviced
External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared
by software
3
2
1
PX2
EX2
IE2
External interrupt 2 priority is higher if set this to 1
Enable External interrupt 2 if set this bit to 1
If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detect-
ed/serviced
0
IT2
External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared
by software
SFR program of address low
Bit:
7
6
5
4
3
2
1
0
SFRAL.7
SFRAL.6
SFRAL.5
SFRAL.4
SFRAL.3
SFRAL.2
SFRAL.1
SFRAL.0
Mnemonic: SFRAL
Address: C4h
BIT NAME
FUNCTION
7-0 SFRAL.[7:0] The programming address of on-chip flash memory in programming mode.
SFRFAL contains the low-order byte of address.
SFR program of address high
Bit:
7
6
5
4
3
2
1
0
SFRAH.7
SFRAH.6
SFRAH.5
SFRAH.4
SFRAH.3
SFRAH.2
SFRAH.1
SFRAH.0
Mnemonic: SFRAH
Address: C5h
BIT NAME
FUNCTION
7-0 SFRAH.[7:0] The programming address of on-chip flash memory in programming mode.
SFRFAH contains the high-order byte of address.
SFR program For Data
Bit:
7
6
5
4
3
2
1
0
SFRFD.7
SFRFD.6
SFRFD.5
SFRFD.4
SFRFD.3
SFRFD.2
SFRFD.1
SFRFD.0
Mnemonic: SFRFD
Address: C6h
BIT NAME
FUNCTION
7-0 SFRFD.[7:0] The programming data for on-chip flash memory in programming mode.
SFR for Program Control
Bit:
7
-
6
5
4
3
2
1
0
OEN
CEN
CTRL3
CTRL2
CTRL1
CTRL0
Mnemonic: SFRCN
Address: C7h
BIT NAME
FUNCTION
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W78E054D/W78E052D Data Sheet
5
4
OEN
CEN
FLASH EPROM output enable.
FLASH EPROM chip enable.
3-0 CTRL[3:0] CTRL[3:0]: The flash control signals
Mode
OEN
1
CEN
1
CTRL<3:0>
X
SFRAH, SFRAL
X
SFRFD
X
Flash Standby
Read Company ID
Read Device ID High
Read Device ID Low
Erase APROM
0
0
1011
1100
1100
0010
1001
0001
1010
0000
0FFh, 0FFh
0FFh, 0FFh
0FFh, 0FEh
X
Data out
Data out
Data out
X
0
0
1
0
1
0
Erase Verify APROM
Program APROM
Program Verify APROM
Read APROM
0
0
Address in
Address in
Address in
Address in
Data out
Data in
Data out
Data out
1
0
0
0
0
0
Timer 2 Control
Bit:
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C / T2
CP / RL2
Address: C8h
Mnemonic: T2CON
BIT NAME
FUNCTION
7
TF2
Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set
when the count is equal to the capture register in down count mode. It can be
set only if RCLK and TCLK are both 0. It is cleared only by software. Software
can also set or clear this bit.
6
EXF2
Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2
CP / RL2
overflow will cause this flag to set based on the
, EXEN2 and DCEN
bits. If set by a negative transition, this flag must be cleared by software. Set-
ting this bit in software or detection of a negative transition on T2EX pin will
force a timer interrupt if enabled.
5
4
3
RCLK
TCLK
Receive Clock Flag: This bit determines the serial port 0 time-base when re-
ceiving data in serial modes 1 or 3. If it is 0, then timer 1 overflow is used for
baud rate generation, otherwise timer 2 overflow is used. Setting this bit forces
timer 2 in baud rate generator mode.
Transmit Clock Flag: This bit determines the serial port 0 time-base when
transmitting data in modes 1 and 3. If it is set to 0, the timer 1 overflow is used
to generate the baud rate clock otherwise timer 2 overflow is used. Setting this
bit forces timer 2 in baud rate generator mode.
EXEN2
Timer 2 External Enable. This bit enables the capture/reload function on the
T2EX pin if Timer 2 is not generating baud clocks for the serial port. If this bit
is 0, then the T2EX pin will be ignored, otherwise a negative transition detect-
ed on the T2EX pin will result in capture or reload.
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Revision A13
W78E054D/W78E052D Data Sheet
2
1
TR2
Timer 2 Run Control. This bit enables/disables the operation of timer 2. Clear-
ing this bit will halt the timer 2 and preserve the current count in TH2, TL2.
Counter/Timer Select. This bit determines whether timer 2 will function as a
timer or a counter. Independent of this bit, the timer will run at 2 clocks per tick
when used in baud rate generator mode.
C / T2
0
Capture/Reload Select. This bit determines whether the capture or reload
function will be used for timer 2. If either RCLK or TCLK is set, this bit will be
ignored and the timer will function in an auto-reload mode following each over-
flow. If the bit is 0 then auto-reload will occur when timer 2 overflows or a fall-
ing edge is detected on T2EX pin if EXEN2 = 1. If this bit is 1, then timer 2
captures will occur when a falling edge is detected on T2EX pin if EXEN2 =
1.
CP / RL2
Timer 2 Mode Control
Bit:
7
6
-
5
-
4
-
3
-
2
-
1
-
0
DCEN
Mnemonic: T2MOD
Address: C9h
BIT NAME
FUNCTION
0
DCEN
Down Count Enable: This bit, in conjunction with the T2EX pin, controls the
direction that timer 2 counts in 16-bit auto-reload mode.
Timer 2 Capture LSB
Bit:
7
6
5
4
3
2
1
0
RCAP2L.7
RCAP2L.6
RCAP2L.5
RCAP2L.4
RCAP2L.3
RCAP2L.2
RCAP2L.1
RCAP2L.0
Mnemonic: RCAP2L
Address: CAh
BIT NAME
FUNCTION
7-0 RCAP2L.[7:0] This register is used to capture the TL2 value when a timer 2 is configured in
capture mode. RCAP2L is also used as the LSB of a 16-bit reload value
when timer 2 is configured in auto-reload mode.
Timer 2 Capture MSB
Bit:
7
6
5
4
3
2
1
0
RCAP2h.7
RCAP2h.6
RCAP2h.5
RCAP2h.4
RCAP2h.3
RCAP2h.2
RCAP2h.1
RCAP2h.0
Mnemonic: RCAP2H
Address: CBh
BIT NAME
FUNCTION
7-0 RCAP2H.[7:0] This register is used to capture the TH2 value when a timer 2 is configured in
capture mode. RCAP2H is also used as the MSB of a 16-bit reload value
when timer 2 is configured in auto-reload mode.
Timer 2 LSB
Bit:
7
6
5
4
3
2
1
0
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W78E054D/W78E052D Data Sheet
TL2.7
Mnemonic: TL2
BIT NAME
TL2.6
TL2.5
TL2.4
TL2.3
TL2.2
TL2.1
TL2.0
Address: CCh
FUNCTION
Timer 2 LSB
7-0 TL2.[7:0]
Timer 2 MSB
Bit:
7
6
5
TH2.5
4
3
2
1
0
TH2.7
TH2.6
TH2.4
TH2.3
TH2.2
TH2.1
TH2.0
Mnemonic: TH2
BIT NAME
Address: CDh
FUNCTION
7-0 TH2.[7:0]
Timer 2 MSB
Program Status Word
Bit:
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Mnemonic: PSW
BIT NAME FUNCTION
Address: D0h
7
CY
Carry flag:
Set for an arithmetic operation which results in a carry being generated from the
ALU. It is also used as the accumulator for the bit operations.
6
5
AC
F0
Auxiliary carry:
Set when the previous operation resulted in a carry from the high order nibble.
User flag 0:
The General purpose flag that can be set or cleared by the user.
Register bank select bits:
4
3
2
RS1
RS0
OV
Register bank select bits:
Overflow flag:
Set when a carry was generated from the seventh bit but not from the 8th bit as a
result of the previous operation, or vice-versa.
1
0
F1
P
User Flag 1:
The General purpose flag that can be set or cleared by the user by software.
Parity flag:
Set/cleared by hardware to indicate odd/even number of 1’s in the accumulator.
Port 4
Bit:
7
-
6
-
5
-
4
-
3
2
1
0
P4.3
P4.2
P4.1
P4.0
Mnemonic: P4
Address: D8h
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port ad-
dress is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are alter-
INT2
native function pins. It can be used as general I/O pins or external interrupt input sources (
,
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W78E054D/W78E052D Data Sheet
INT3
).
ACCUMULATOR
Bit:
7
6
5
4
3
2
1
0
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
Mnemonic: ACC
Bit Name
Address: E0h
Function
7-0 ACC
The A or ACC register is the standard 8052 accumulator.
B Register
Bit:
7
6
5
4
3
2
1
0
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
Mnemonic: B
Address: F0h
Bit
Name
Function
7-0
B
The B register is the standard 8052 register that serves as a second accumulator.
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Revision A13
W78E054D/W78E052D Data Sheet
10 INSTRUCTION
The W78E054D/W78E052D series execute all the instructions of the standard 8052 family. The opera-
tions of these instructions, as well as their effects on flag and status bits, are exactly the same.
W78E054D/W78E052D series Clock
Op-code
HEX Code Bytes
cycles
NOP
00
28
29
2A
2B
2C
2D
2E
2F
26
27
25
24
38
39
3A
3B
3C
3D
3E
3F
36
37
35
34
98
99
9A
9B
9C
9D
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
ADD A, R0
ADD A, R1
ADD A, R2
ADD A, R3
ADD A, R4
ADD A, R5
ADD A, R6
ADD A, R7
ADD A, @R0
ADD A, @R1
ADD A, direct
ADD A, #data
ADDC A, R0
ADDC A, R1
ADDC A, R2
ADDC A, R3
ADDC A, R4
ADDC A, R5
ADDC A, R6
ADDC A, R7
ADDC A, @R0
ADDC A, @R1
ADDC A, direct
ADDC A, #data
SUBB A, R0
SUBB A, R1
SUBB A, R2
SUBB A, R3
SUBB A, R4
SUBB A, R5
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Revision A13
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W78E054D/W78E052D Data Sheet
W78E054D/W78E052D series Clock
cycles
Op-code
HEX Code Bytes
SUBB A, R6
SUBB A, R7
SUBB A, @R0
SUBB A, @R1
SUBB A, direct
SUBB A, #data
INC A
9E
9F
96
97
95
94
04
08
09
0A
0B
0C
0D
0E
0F
06
07
05
A3
14
18
19
1A
1B
1C
1D
1E
1F
16
17
15
A4
84
D4
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
12
12
12
12
12
12
48
48
12
INC R0
INC R1
INC R2
INC R3
INC R4
INC R5
INC R6
INC R7
INC @R0
INC @R1
INC direct
INC DPTR
DEC A
DEC R0
DEC R1
DEC R2
DEC R3
DEC R4
DEC R5
DEC R6
DEC R7
DEC @R0
DEC @R1
DEC direct
MUL AB
DIV AB
DA A
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Revision A13
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W78E054D/W78E052D Data Sheet
W78E054D/W78E052D series Clock
cycles
Op-code
HEX Code Bytes
ANL A, R0
ANL A, R1
58
59
5A
5B
5C
5D
5E
5F
56
57
55
54
52
53
48
49
4A
4B
4C
4D
4E
4F
46
47
45
44
42
43
68
69
6A
6B
6C
6D
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
12
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
ANL A, R2
ANL A, R3
ANL A, R4
ANL A, R5
ANL A, R6
ANL A, R7
ANL A, @R0
ANL A, @R1
ANL A, direct
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, R0
ORL A, R1
ORL A, R2
ORL A, R3
ORL A, R4
ORL A, R5
ORL A, R6
ORL A, R7
ORL A, @R0
ORL A, @R1
ORL A, direct
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, R0
XRL A, R1
XRL A, R2
XRL A, R3
XRL A, R4
XRL A, R5
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Revision A13
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W78E054D/W78E052D Data Sheet
W78E054D/W78E052D series Clock
cycles
Op-code
HEX Code Bytes
XRL A, R6
XRL A, R7
XRL A, @R0
XRL A, @R1
XRL A, direct
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
6E
6F
66
67
65
64
62
63
E4
F4
23
33
03
13
C4
E8
E9
EA
EB
EC
ED
EE
EF
E6
E7
E5
74
F8
F9
FA
FB
FC
FD
FE
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
12
12
12
12
12
12
12
24
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
MOV A, R0
MOV A, R1
MOV A, R2
MOV A, R3
MOV A, R4
MOV A, R5
MOV A, R6
MOV A, R7
MOV A, @R0
MOV A, @R1
MOV A, direct
MOV A, #data
MOV R0, A
MOV R1, A
MOV R2, A
MOV R3, A
MOV R4, A
MOV R5, A
MOV R6, A
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Revision A13
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W78E054D/W78E052D Data Sheet
W78E054D/W78E052D series Clock
cycles
Op-code
HEX Code Bytes
MOV R7, A
MOV R0, direct
MOV R1, direct
MOV R2, direct
MOV R3, direct
MOV R4, direct
MOV R5, direct
MOV R6, direct
MOV R7, direct
MOV R0, #data
MOV R1, #data
MOV R2, #data
MOV R3, #data
MOV R4, #data
MOV R5, #data
MOV R6, #data
MOV R7, #data
MOV @R0, A
FF
A8
A9
AA
AB
AC
AD
AE
AF
78
79
7A
7B
7C
7D
7E
7F
F6
F7
A6
A7
76
77
F5
88
89
8A
8B
8C
8D
8E
8F
86
87
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
12
24
24
24
24
24
24
24
24
12
12
12
12
12
12
12
12
12
12
24
24
12
12
12
24
24
24
24
24
24
24
24
24
24
MOV @R1, A
MOV @R0, direct
MOV @R1, direct
MOV @R0, #data
MOV @R1, #data
MOV direct, A
MOV direct, R0
MOV direct, R1
MOV direct, R2
MOV direct, R3
MOV direct, R4
MOV direct, R5
MOV direct, R6
MOV direct, R7
MOV direct, @R0
MOV direct, @R1
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Revision A13
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W78E054D/W78E052D Data Sheet
W78E054D/W78E052D series Clock
cycles
Op-code
HEX Code Bytes
MOV direct, direct
MOV direct, #data
MOV DPTR, #data 16
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @R0
MOVX A, @R1
MOVX A, @DPTR
MOVX @R0, A
MOVX @R1, A
MOVX @DPTR, A
PUSH direct
POP direct
85
75
3
3
3
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
2
1
2
2
2
24
24
24
24
24
24
24
24
24
24
24
24
24
12
12
12
12
12
12
12
12
12
12
12
12
24
12
12
12
12
12
12
24
24
90
93
83
E2
E3
E0
F2
F3
F0
C0
D0
C8
C9
CA
CB
CC
CD
CE
CF
C6
C7
D6
D7
C5
C3
C2
D3
D2
B3
B2
82
XCH A, R0
XCH A, R1
XCH A, R2
XCH A, R3
XCH A, R4
XCH A, R5
XCH A, R6
XCH A, R7
XCH A, @R0
XCH A, @R1
XCHD A, @R0
XCHD A, @R1
XCH A, direct
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
ANL C, /bit
B0
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W78E054D/W78E052D Data Sheet
W78E054D/W78E052D series Clock
cycles
Op-code
HEX Code Bytes
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
72
A0
A2
92
2
2
2
2
24
24
12
24
71, 91, B1,
11, 31, 51,
D1, F1
ACALL addr11
2
24
LCALL addr16
RET
12
22
32
3
1
1
24
24
24
RETI
01, 21, 41,
61, 81, A1,
C1, E1
AJMP ADDR11
2
24
LJMP addr16
JMP @A+DPTR
SJMP rel
02
73
80
60
70
40
50
20
30
10
B5
B4
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
3
1
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
JZ rel
JNZ rel
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE @R0, #data, rel
CJNE @R1, #data, rel
CJNE R0, #data, rel
CJNE R1, #data, rel
CJNE R2, #data, rel
CJNE R3, #data, rel
CJNE R4, #data, rel
CJNE R5, #data, rel
CJNE R6, #data, rel
CJNE R7, #data, rel
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W78E054D/W78E052D Data Sheet
W78E054D/W78E052D series Clock
cycles
Op-code
HEX Code Bytes
DJNZ R0, rel
DJNZ R1, rel
DJNZ R5, rel
DJNZ R2, rel
DJNZ R3, rel
DJNZ R4, rel
DJNZ R6, rel
DJNZ R7, rel
DJNZ direct, rel
D8
D9
DD
DA
DB
DC
DE
DF
D5
2
2
2
2
2
2
2
2
3
24
24
24
24
24
24
24
24
24
Table 10-1: Instruction Set for W78E054D/W78E052D
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W78E054D/W78E052D Data Sheet
10.1 Instruction Timing
A machine cycle consists of a sequence of 6 states, numbered S1 through S6. Each state time lasts
for two oscillator periods. Thus a machine cycle takes 12 oscillator periods or 1us if the oscillator fre-
quency is 12MHz.
Each state is divided into a Phase 1 half and a Phase 2 half. The fetch/execute sequences in states
and phases for various kinds of instructions. Normally two program fetches are generated during each
machine cycle, even if the instruction being executed doesn’t require it. If the instruction being execut-
ed doesn’t need more code bytes, the CPU simply ignores the extra fetch, and the Program Counter is
not incremented. Execution of a one-cycle instruction begins during State 1 of the machine cycle,
when the OPCODE is latched into the Instruction Register. A second fetch occurs during S4 of the
same machine cycle. Execution is complete at the end of State 6 of this machine cycle.
The MOVX instructions take two machine cycles to execute. No program fetch is generated during the
second cycle of a MOVX instruction. This is the only time program fetches are skipped. The
fetch/execute sequence for MOVX instructions.
The fetch/execute sequences are the same whether the Program Memory is internal or external to the
chip. Execution times do not depend on whether the Program Memory is internal or external.
The signals and timing involved in program fetches when the Program Memory is external. If Program
Memory is external, then the Program Memory read strobe PSEN is normally activated twice per ma-
chine cycle. If an access to external Data Memory occurs, two PSEN pulse are skipped, because the
address and data bus are being used for the Data Memory access. Note that a Data Memory bus cy-
cle takes twice as much time as a Program Memory bus cycle.
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W78E054D/W78E052D Data Sheet
11 POWER MANAGEMENT
The W78E054D/W78E052D has several features that help the user to control the power consumption
of the device. The power saved features have basically the POWER DOWN mode and the IDLE mode
of operation.
11.1 Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the
idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle
mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer and Serial port
blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program
Status Word, the Accumulator and the other registers hold their contents. The port pins hold the logi-
cal states they had at the time Idle was activated. The Idle mode can be terminated in two ways. Since
the interrupt controller is still active, the activation of any enabled interrupt can wake up the processor.
This will automatically clear the Idle bit, terminate the Idle mode, and the Interrupt Service Routine
(ISR) will be executed. After the ISR, execution of the program will continue from the instruction which
put the device into Idle mode.
The Idle mode can also be exited by activating the reset. The device can put into reset either by apply-
ing a high on the external RST pin, a Power on reset condition or a Watchdog timer reset. The exter-
nal reset pin has to be held high for at least two machine cycles i.e. 24 clock periods to be recognized
as a valid reset. In the reset condition the program counter is reset to 0000h and all the SFRs are set
to the reset condition. Since the clock is already running there is no delay and execution starts imme-
diately.
11.2 Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does
this will be the last instruction to be executed before the device goes into Power Down mode. In the
Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. The port pins output the
values held by their respective SFRs.
The W78E054D/W78E052D will exit the Power Down mode with a reset or by an external interrupt pin
enabled as level detects. An external reset can be used to exit the Power down state. The high on
RST pin terminates the Power Down mode, and restarts the clock. The program execution will restart
from 0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power down mode.
The W78E054D/W78E052D can be woken from the Power Down mode by forcing an external inter-
rupt pin activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is
set and the external input has been set to a level detect mode. If these conditions are met, then the
high level on the external pin re-starts the oscillator. Then device executes the interrupt service routine
for the corresponding external interrupt. After the interrupt service routine is completed, the program
execution returns to the instruction after one which put the device into Power Down mode and contin-
ues from there.
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W78E054D/W78E052D Data Sheet
12 RESET CONDITIONS
The user has several hardware related options for placing the W78E054D/W78E052D into reset con-
dition. In general, most register bits go to their reset value irrespective of the reset condition, but there
are a few flags whose state depends on the source of reset. The user can use these flags to deter-
mine the cause of reset using software.
12.1 Sources of reset
12.1.1 External Reset
The device continuously samples the RST pin at state S5P2 of every machine cycle. Therefore the
RST pin must be held for at least 2 machine cycles (24 clock cycles) to ensure detection of a valid
RST high. The reset circuitry then synchronously applies the internal reset signal. Thus the reset is a
synchronous operation and requires the clock to be running to cause an external reset. For more tim-
ing information, please reference the character 21.4.5 (Page 77).
Once the device is in reset condition, it will remain so as long as RST is 1. Even after RST is deac-
tivated, the device will continue to be in reset state for up to two machine cycles, and then begin pro-
gram execution from 0000h. There is no flag associated with the external reset condition.
12.1.2 Software Reset
The W78E054D/W78E052D offers a software reset to switch back to the APROM. Setting CHPCON
bits 0, 1 and 7 to logic-1 creates software reset to reset the CPU to start APROM code. Note: Software
Reset only LDROM jump to APROM, APROM can’t software reset to LDROM.
12.1.3 Watchdog Timer Reset
The Watchdog timer is a free running timer with programmable time-out intervals. The user can clear
the watchdog timer at any time, causing it to restart the count. When the time-out interval is reached
an interrupt flag is set. If the Watchdog reset is enabled and the watchdog timer is not cleared, the
watchdog timer will generate a reset. This places the device into the reset condition. The reset condi-
tion is maintained by hardware for two machine cycles. Once the reset is removed the device will
begin execution from 0000h.
12.2 Reset State
Most of the SFRs and registers on the device will go to the same condition in the reset state. The Pro-
gram Counter is forced to 0000h and is held there as long as the reset condition is applied. However,
the reset state does not affect the on-chip RAM. The data in the RAM will be preserved during the re-
set. However, the stack pointer is reset to 07h, and therefore the stack contents will be lost. The RAM
contents will be lost if the VDD falls below approximately 2V, as this is the minimum voltage level re-
quired for the RAM to operate normally. Therefore after a first time power on reset the RAM contents
will be indeterminate. During a power fail condition, if the power falls below 2V, the RAM contents are
lost.
After a reset most SFRs are cleared. Interrupts and Timers are disabled. The Watchdog timer is disa-
bled if the reset source was a POR. The port SFRs has 0FFh written into them which puts the port
pins in a high state.
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W78E054D/W78E052D Data Sheet
13 INTERRUPTS
The W78E054D/W78E052D has a 4 priority level interrupt structure with 8 interrupt sources. Each of
the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
13.1 Interrupt Sources
INT0
INT1
can be either edge triggered or level triggered, depending on
The External Interrupts
and
bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to gener-
ate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine cycle. If
the sample is high in one cycle and low in the next, then a high to low transition is detected and the
interrupts request flag IEx in TCON o is set. The flag bit requests the interrupt. Since the external in-
terrupts are sampled every machine cycle, they have to be held high or low for at least one complete
machine cycle. The IEx flag is automatically cleared when the service routine is called. If the level trig-
gered mode is selected, then the requesting source has to hold the pin low till the interrupt is serviced.
The IEx flag will not be cleared by the hardware on entering the service routine. If the interrupt contin-
ues to be held low even after the service routine is completed, then the processor may acknowledge
INT3
. By
INT2
another interrupt request from the same source. Note that the external interrupts
and
default, the individual interrupt flag corresponding to external interrupt 2 to 3 must be cleared manually
by software.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the over-
flow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware
when the timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of the TF2 and
the EXF2 flags. These flags are set by overflow or capture/reload events in the timer 2 operation. The
hardware does not clear these flags when a timer 2 interrupt is executed. Software has to resolve the
cause of the interrupt between TF2 and EXF2 and clear the appropriate flag.
The Serial block can generate interrupts on reception or transmission. There are two interrupt sources
from the Serial block, which are obtained by the RI and TI bits in the SCON SFR, These bits are not
automatically cleared by the hardware, and the user will have to clear these bits using software.
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated in-
terrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to disa-
ble all the interrupts, at once.
Source
Vector Address
0003h
Source
Vector Address
000Bh
External Interrupt 0
External Interrupt 1
Serial Port
Timer 0 Overflow
Timer 1 Overflow
Timer 2 Overflow
External Interrupt 3
0013h
001Bh
0023h
002Bh
External Interrupt 2
0033h
003Bh
Table 13–1 W78E054D/W78E052D interrupt vector table
13.2 Priority Level Structure
There are 4 priority levels for the interrupts high, low. Naturally, a higher priority interrupt cannot be
interrupted by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the in-
terrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve simul-
taneous requests having the same priority level. This hierarchy is defined as shown on Table.
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W78E054D/W78E052D Data Sheet
PRIORITY BITS
IPH
IP/
XICON.7/
XICON.3
INTERRUPT PRIORITY LEVEL
0
0
1
1
0
1
0
1
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled inter-
rupts are polled and their priority is resolved. If certain conditions are met then the hardware will exe-
cute an internally generated LCALL instruction which will vector the process to the appropriate inter-
rupt vector address. The conditions for generating the LCALL are;
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being executed.
3. The current instruction does not involve a write to IE, IP, IPH, XICON registers and is not a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is re-
peated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt flag
is active in one cycle but not responded to, and is not active when the above conditions are met, the
denied interrupt will not be serviced. This means that active interrupts are not remembered; every poll-
ing cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate ser-
vice routine. This may or may not clear the flag which caused the interrupt. In case of Timer interrupts,
the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the appropriate timer
service routine. In case of external interrupt, /INT0 and /INT1, the flags are cleared only if they are
edge triggered. In case of Serial interrupts, the flags are not cleared by hardware. In the case of Timer
2 interrupt, the flags are not cleared by hardware. The hardware LCALL behaves exactly like the soft-
ware LCALL instruction. This instruction saves the Program Counter contents onto the Stack, but does
not save the Program Status Word PSW. The PC is reloaded with the vector address of that interrupt
which caused the LCALL. These address of vector for the different sources are as shown on the below
table. The vector table is not evenly spaced; this is to accommodate future expansions to the device
family.
Execution continues from the vectored address till an RETI instruction is executed. On execution of
the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the
stack. The user must take care that the status of the stack is restored to what is after the hardware
LCALL, if the execution is to return to the interrupted program. The processor does not notice anything
if the stack contents are modified and will proceed with execution from the address put back into PC.
Note that a RET instruction would perform exactly the same process as a RETI instruction, but it
would not inform the Interrupt Controller that the interrupt service routine is completed, and would
leave the controller still thinking that the service routine is underway.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IE.
The IE register also contains a global disable bit, EA, which disables all interrupts at once.
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W78E054D/W78E052D Data Sheet
Each interrupt source can be individually programmed to one of 2 priority levels by setting or clearing
bits in the IP registers. An interrupt service routine in progress can be interrupted by a higher priority
interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. So, if two requests of different priority levels are
received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence deter-
mines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking
is only used to resolve simultaneous requests of the same priority level.
Table below summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,
arbitration ranking, and External interrupt may wake up the CPU from Power Down mode.
Source
Flag Vector
address
Enable bit Interrupt
Priority
Flag cleared Arbitration
Power-
down
wakeup
by
ranking
External Interrupt 0 IE0
Timer 0 Overflow TF0
External Interrupt 1 IE1
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES (IE.4)
ET2 (IE.5)
EX2
IPH.0, IP.0 Hardware,
software
1(highest)
Yes
IPH.1, IP.1 Hardware,
software
2
No
IPH.2, IP.2 Hardware,
software
3
Yes
No
Timer 1 Overflow
Serial Port
TF1
IPH.3, IP.3 Hardware,
software
4
RI +
TI
IPH.4, IP.4 Software
5
No
Timer 2 Over-
flow/Match
TF2
IPH.5, IP.5 Software
6
No
External Interrupt 2 IE2
IPH.6,
Hardware,
software
7
Yes
Yes
(XICON.2) PX2
External Interrupt 3 IE3
EX3
IPH.7,
Hardware,
software
8(lowest)
(XICON.6) PX3
Table 13–2 Summary of interrupt sources
13.3 Interrupt Response Time
The response time for each interrupt source depends on several factors, such as the nature of the in-
terrupt and the instruction underway. In the case of external interrupts INT0 and INT1, they are sam-
pled at S5P2 of every machine cycle and then their corresponding interrupt flags IEx will be set or re-
set. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has oc-
curred. These flag values are polled only in the next machine cycle. If a request is active and all three
conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes four ma-
chine cycles to be completed. Thus there is a minimum time of five machine cycles between the inter-
rupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the instruc-
tion being executed, then an additional delay is introduced. The maximum response time (if no other
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W78E054D/W78E052D Data Sheet
interrupt is in service) occurs if the device is performing a write to IE, IP, IPH and then executes a
MUL or DIV instruction.
13.4 Interrupt Inputs
Since the external interrupt pins are sampled once each machine cycle, an input high or low should
hold for at least one machine cycle to ensure proper sampling. If the external interrupt is high for at
least one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the
transition is seen and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU
when the service routine is called.
If the external interrupt is level-activated, the external source must hold the request active until the
requested interrupt is actually generated. If the external interrupt is still asserted when the interrupt
service routine is completed another interrupt will be generated. It is not necessary to clear the inter-
rupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the W78E054D/W78E052D is put into Power Down or Idle
mode, the interrupt will cause the processor to wake up and resume operation. Refer to the section on
Power Reduction Modes for details.
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W78E054D/W78E052D Data Sheet
14 PROGRAMMABLE TIMERS/COUNTERS
The W78E054D/W78E052D series have Three 16-bit programmable timer/counters. A machine cycle
equals 12 or 6 oscillator periods, and it depends on 12T mode or 6T mode that the user configured
this device.
14.1 Timer/Counters 0 & 1
W78E054D/W78E052D has two 16-bit Timer/Counters. Each of these Timer/Counters has two 8 bit
registers which form the 16 bit counting register. For Timer/Counter 0 they are TH0, the upper 8 bits
register, and TL0, the lower 8 bit register. Similarly Timer/Counter 1 has two 8 bit registers, TH1 and
TL1. The two can be configured to operate either as timers, counting machine cycles or as counters
counting external inputs.
When configured as a "Timer", the timer counts clock cycles. The timer clock can be programmed to
be thought of as 1/12 of the system clock. In the "Counter" mode, the register is incremented on the
falling edge of the external input pin, T0 in case of Timer 0, and T1 for Timer 1. The T0 and T1 inputs
are sampled in every machine cycle at C4. If the sampled value is high in one machine cycle and low
in the next, then a valid high to low transition on the pin is recognized and the count register is incre-
mented. Since it takes two machine cycles to recognize a negative transition on the pin, the maximum
rate at which counting will take place is 1/24 of the master clock frequency. In either the "Timer" or
"Counter" mode, the count register will be updated at C3. Therefore, in the "Timer" mode, the recog-
nized negative transition on pin T0 and T1 can cause the count register value to be updated only in
the machine cycle following the one in which the negative edge was detected.
C/T
The "Timer" or "Counter" function is selected by the "
" bit in the TMOD Special Function Register.
Each Timer/Counter has one selection bit for its own; bit 2 of TMOD selects the function for Tim-
er/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each Tim-
er/Counter can be set to operate in any one of four possible modes. The mode selection is done by
bits M0 and M1 in the TMOD SFR.
14.2 Time-Base Selection
W78E054D/W78E052D provides users with two modes of operation for the timer. The timers can be
programmed to operate like the standard 8051 family, counting at the rate of 1/12 of the clock speed.
This will ensure that timing loops on W78E054D/W78E052D and the standard 8051 can be matched.
This is the default mode of operation of the W78E054D/W78E052D timers.
14.2.1 Mode 0
In Mode 0, the timer/counter is a 13-bit counter. The 13-bit counter consists of THx (8 MSB) and the
five lower bits of TLx (5 LSB). The upper three bits of TLx are ignored. The timer/counter is enabled
C/T
INTx
when TRx is set and either GATE is 0 or
is 1. When
is 0, the timer/counter counts clock
C/T
cycles; when
is 1, it counts falling edges on T0 (Timer 0) or T1 (Timer 1). For clock cycles, the
time base be 1/12 speed, and the falling edge of the clock increments the counter. When the 13-bit
value moves from 1FFFh to 0000h, the timer overflow flag TFx is set, and an interrupt occurs if ena-
bled.
14.2.2 Mode 1
Mode 1 is similar to Mode 0 except that the counting register forms a 16-bit counter, rather than a 13-
bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer
moves from a count of 0FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if
enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in
Mode 0. The gate function operates similarly to that in Mode 0.
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W78E054D/W78E052D Data Sheet
C/T=TMOD.2
(C/T=TMOD.6)
M1, M0=TMOD.1, TMOD.0
(M1, M0=TMOD.5, TMOD.4)
Fosc
1/12
0
1
00
0
4
7
0
7
01
T0=P3.4
(T1=P3.5)
TL0
(TL1)
TH0
(TH1)
TR0=TCON.4
(TR1=TCON.6)
Interrupt
TFx
TF0
(TF1)
GATE=TMOD.3
(GATE=TMOD.7)
INT0=P3.2
(INT1=P3.3)
Timer/Counter Mode0,1
Figure 14–1 Timer/Counters 0 & 1 in Mode 0, 1
14.2.3 Mode 2
In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as an 8-bit count reg-
ister, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx bit
in TCON is set and TLx is reloaded with the contents of THx, and the counting process continues from
here. The reload operation leaves the contents of the THx register unchanged. Counting is enabled by
INTx
the TRx bit and proper setting of GATE and
lows counting of clock/12 or pulses on pin Tn.
pins. As in the other two modes 0 and 1 mode 2 al-
C/T=TMOD.2
(C/T=TMOD.6)
Fosc
1/12
TL0
(TL1)
0
1
0
0
7
7
Interrupt
TFx
T0=P3.4
(T1=P3.5)
TF0
(TF1)
TR0=TCON.4
(TR1=TCON.6)
TH0
(TH1)
GATE=TMOD.3
(GATE=TMOD.7)
INT0=P3.2
(INT1=P3.3)
Timer/Counter Mode2
Figure 14–2 Timer/Counter 0 & 1 in Mode 2
14.2.4 Mode 3
Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3 simply
freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count
registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer/Counter 0
C/T
INT0
and TF0. The TL0 can be used to count clock cycles (clock/12) or
control bits
, GATE, TR0,
1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle counter
(clock/12) and takes over the use of TR1 and TF1 from Timer/Counter 1. Mode 3 is used in cases
where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still be used in Modes 0, 1
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and 2, but its flexibility is somewhat limited. While its basic functionality is maintained, it no longer has
control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a timer/counter
and retains the use of GATE and INT1 pin. In this condition it can be turned on and off by switching it
out of and into its own Mode 3. It can also be used as a baud rate generator for the serial port.
C/T=TMOD.2
Fosc
1/12
0
TL0
0
7
Interrupt
TF0
1
T0=P3.4
TR0=TCON.4
GATE=TMOD.3
INT0=P3.2
TH0
0
7
Interrupt
TF1
TR1=TCON.6
Figure 14–3 Timer/Counter Mode 3
14.3 Timer/Counter 2
Timer/Counter 2 is a 16 bit up/down counter which is configured by the T2MOD(bit 0) register and
controlled by the T2CON register. Timer/Counter 2 is equipped with a capture/reload capability. As
with the Timer 0 and Timer 1 counters, there exists considerable flexibility in selecting and controlling
the clock, and in defining the operating mode. The clock source for Timer/Counter 2 may be selected
for either the external T2 pin (C/T2 = 1) or the crystal oscillator, which is divided by 12 (C/T2 = 0). The
clock is then enabled when TR2 is a 1, and disabled when TR2 is a 0.
14.3.1 Capture Mode
CP / RL2
The capture mode is enabled by setting the
bit in the T2CON register to a 1. In the capture
mode, Timer/Counter 2 serves as a 16 bit up counter. When the counter rolls over from 0FFFFh to
0000h, the TF2 bit is set, which will generate an interrupt request. If the EXEN2 bit is set, then a nega-
tive transition of T2EX pin will cause the value in the TL2 and TH2 register to be captured by the
RCAP2L and RCAP2H registers. This action also causes the EXF2 bit in T2CON to be set, which will
also generate an interrupt.
(RCLK,TCLK, CP/RL2 )= (0,0,1)
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C/T2=T2CON.1
Fosc
1/12
0
1
T2CON.7
TL2 TH2
TF2
T2=P1.0
Timer2
Interrupt
TR2=T2CON.2
RCAP2L
RCAP2H
T2EX=P1.1
EXF2
T2CON.6
EXEN2=T2CON.3
Figure 14–4 16-Bit Capture Mode
14.3.2 Auto-Reload Mode, Counting up
CP / RL2
The auto-reload mode as an up counter is enabled by clearing the
bit in the T2CON register
and clearing the DCEN bit in T2MOD(bit0) register. In this mode, Timer/Counter 2 is a 16 bit up coun-
ter. When the counter rolls over from 0FFFFh, a reload is generated that causes the contents of the
RCAP2L and RCAP2H registers to be reloaded into the TL2 and TH2 registers. The reload action also
sets the TF2 bit. If the EXEN2 bit is set, then a negative transition of T2EX pin will also cause a reload.
This action also sets the EXF2 bit in T2CON.
(RCLK,TCLK, CP/RL2 )= (0,0,0) & DCEN= 0
C/T2=T2CON.1
Fosc
1/12
0
T2CON.7
TL2 TH2
TF2
1
T2=P1.0
TR2=T2CON.2
Timer2
Interrupt
RCAP2L
RCAP2H
EXF2
T2CON.6
Figure 14–5 16-Bit Auto-reload Mode, Counting Up
14.3.3 Auto-reload Mode, Counting Up/Down
Timer/Counter 2 will be in auto-reload mode as an up/down counter if CP / RL2 bit in T2CON is
cleared and the DCEN bit in T2MOD is set. In this mode, Timer/Counter 2 is an up/down counter
whose direction is controlled by the T2EX pin. A 1 on this pin cause the counter to count up. An over-
flow while counting up will cause the counter to be reloaded with the contents of the capture registers.
The next down count following the case where the contents of Timer/Counter equal the capture regis-
ters will load a 0FFFFh into Timer/Counter 2. In either event a reload will set the TF2 bit. A reload will
also toggle the EXF2 bit. However, the EXF2 bit cannot generate an interrupt while in this mode.
(RCLK,TCLK, CP/RL2 )= (0,0,0) & DCEN= 1
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Down Counting Reload Value
0FFh 0FFh
C/T2=T2CON.1
Fosc
1/12
0
1
T2CON.7
Timer2
Interrupt
TF2
TL2 TH2
T2=P1.0
TR2=T2CON.2
RCAP2L
RCAP2H
Up Counting Reload Value
EXF2
T2EX=P1.1
T2CON.6
Figure 14–6 16-Bit Auto-reload Mode, Counting Up
14.3.4 Baud Rate Generator Mode
The baud rate generator mode is enabled by setting either the RCLK or TCLK bits in T2CON register.
While in the baud rate generator mode, Timer/Counter 2 is a 16 bit counter with auto reload when the
count rolls over from 0FFFFh. However, rolling over does not set the TF2 bit. If EXEN2 bit is set, then
a negative transition of the T2EX pin will set EXF2 bit in the T2CON register and cause an interrupt
request.
RCLK+TCLK=1, CP/RL2=0
Timer1
Overflow
1/2
0
1
1/2
C/T2=T2CON.1
SMOD=
PCON.7
Fosc
0
1
Timer2
Overflow
RCLK=
T2CON.5
TL2 TH2
1
0
0
T2=P1.0
Rx Clock
Tx Clock
1/16
1/16
TCLK=
T2CON.4
TR2=T2CON.2
1
RCAP2L
RCAP2H
T2EX=P1.1
Timer2
Interrupt
EXF2
T2CON.6
EXEN2=T2CON.3
Figure 14–7 Baud Rate Generator Mode
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15 WATCHDOG TIMER
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a sys-
tem monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro-
magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values de-
pending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should
restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog tim-
er are discussed below.
ENW : Enable watchdog if set.
CLRW : Clear watchdog timer and Pre-scalar if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watchdog is disabled un-
der IDLE mode. Default is cleared.
PS2, PS1, PS0: Watchdog Pre-scalar timer select. Pre-scalar is selected when set PS20 as follows:
PS2 PS1 PS0
Pre-scalar select
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
8
4
16
32
64
128
256
The time-out period is obtained using the following equation for 12T per machine cycle:
1
214 Pre scalar 100012ms
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, Pre-scalar and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
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ENW
WIDL
IDLE
EXTERNAL
RESET
INTERNAL
RESET
14- BIT TIMER
CLEAR
1/12
1/6
Pre-Scalar
CLRW
OSC
Figure 15–1 Watchdog Timer Block Diagram
Typical Watch-Dog time-out period when OSC = 20 MHz
Watchdog time-out period
PS2 PS1 PS0
(for 12T per machine cycle)
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
19.66 mS
78.64 mS
39.32 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
Table 15–2 Watch-Dog time-out period for 12T per machine cycle, 20MHz
Watchdog time-out period
PS2 PS1 PS0
(for 6T per machine cycle)
0
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
9.83 mS
0
0
0
1
1
1
1
39.32 mS
19.66 mS
78.64 mS
157.28 mS
314.57mS
629.14 mS
1.250 S
Table 15–3 Watch-Dog time-out period for 6T per machine cycle, 20MHz
16 SERIAL PORT
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Serial port in this device is a full duplex port. The serial port is capable of synchronous as well as
asynchronous communication. In Synchronous mode the device generates the clock and operates in a
half-duplex mode. In the asynchronous mode, full duplex operation is available. This means that it can
simultaneously transmit and receive data. The transmit register and the receive buffer are both ad-
dressed as SBUF Special Function Register. However any write to SBUF will be to the transmit regis-
ter, while a read from SBUF will be from the receiver buffer register. The serial port can operate in four
different modes as described below.
16.1 MODE 0
This mode provides synchronous communication with external devices. In this mode serial data is
transmitted and received on the RXD line. TXD is used to transmit the shift clock. The TxD clock is
provided by the device whether it is transmitting or receiving. This mode is therefore a half-duplex
mode of serial communication. In this mode, 8 bits are transmitted or received per frame. The LSB is
transmitted/received first. The baud rate is fixed at 1/12 of the oscillator frequency. This Baud Rate is
determined by the SM2 bit (SCON.5). When this bit is set to 0, then the serial port runs at 1/12 of the
clock. This additional facility of programmable baud rate in mode 0 is the only difference between the
standard 8051 and W78E054D/W78E052D.
The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line.
The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of this
device and the device at the other end of the line. Any instruction that causes a write to SBUF will start
the transmission. The shift clock will be activated and data will be shifted out on the RxD pin till all 8
bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the falling edge
of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then goes high
again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of shift clock on
TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This ensures
that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift
clock on TxD or latched when the TxD clock is low.
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Transmit Shift Register
Write to
SBUF
Internal
Data Bus
PARIN
LOAD SOUT
Fosc
1/12
RXD
P3.0 Alternate
Output Function
CLOCK
1/4
TX START
TX CLOCK
TX SHIFT
TI
SM2
0
1
Serial Interrupt
RI
RX CLOCK
TXD
SHIFT CLOCK
P3.1 Alternate
Output Function
RI
REN
LOAD SBUF
RX SHIFT
TX START
Read SBUF
Serial Controllor
CLOCK
Internal
SBUF
PAROUT
Data Bus
RXD
SIN
P3.0 Alternate
Input Function
Receive Shift Register
Figure 16–1 Serial port mode 0
The TI flag is set high in S6P2 following the end of transmission of the last bit. The serial port will re-
ceive data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the serial port will
latch data on the rising edge of shift clock. The external device should therefore present data on the
falling edge on the shift clock. This process continues till all the 8 bits have been received. The RI flag
is set in S6P2 following the last rising edge of the shift clock on TxD. This will stop reception, till the RI
is cleared by software.
16.2 MODE 1
In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of
10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit goes into RB8 in the SFR SCON. The baud rate in this
mode is variable. The serial baud can be programmed to be 1/16 or 1/32 of the Timer 1 overflow.
Since the Timer 1 can be set to different reload values, a wide variation in baud rates is possible.
Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at S6P2 follow-
ing the first roll-over of divide by 16 counter. The next bit is placed on TxD pin at S6P2 following the
next rollover of the divide by 16 counter. Thus the transmission is synchronized to the divide by 16
counter and not directly to the write to SBUF signal. After all 8 bits of data are transmitted, the stop bit
is transmitted. The TI flag is set in the S6P2 state after the stop bit has been put out on TxD pin. This
will be at the 10th rollover of the divide by 16 counters after a write to SBUF.
Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,
with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD
line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the
divide by 16 counters is immediately reset. This helps to align the bit boundaries with the rollovers of
the divide by 16 counters.
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a
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best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise rejec-
tion feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then this
indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks for a
falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also detected
and shifted into the SBUF.
After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded
and RI is set. However certain conditions must be met before the loading and setting of RI can be
done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.
Transmit Shift Register
Timer 1
Timer 2
Overflow
Overflow
1
0
STOP
Internal
Data Bus
PARIN
Write to
SBUF
SOUT
TXD
START
LOAD
1/2
CLOCK
SMOD
0
1
TX START
TX CLOCK
0
1
1
TX SHIFT
TCLK
1/16
1/16
0
RCLK
Serial
Controllor
TI
Serial Interrupt
RX CLOCK
RI
LOAD SBUF
RX SHIFT
SAMPLE
1-To-0
DETECTOR
TX START
Read SBUF
Internal
Data Bus
SBUF
RB8
CLOCK PAROUT
BIT
DETECTOR
RXD
SIN
D8
Receive Shift Register
Figure 16–2 Serial port mode 1
16.3 MODE 2
This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional descrip-
tion is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first), a pro-
grammable 9th bit (TB8) and a stop bit (1). The 9th bit received is put into RB8. The baud rate is pro-
grammable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in PCON
SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at S6P2
following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at S6P2 fol-
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lowing the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the di-
vide by 16 counters, and not directly to the write to SBUF signal. After all 9 bits of data are transmitted,
the stop bit is transmitted. The TI flag is set in the S6P2 state after the stop bit has been put out on
TxD pin. This will be at the 11th rollover of the divide by 16 counters after a write to SBUF. Reception
is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the de-
tection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line, sam-
pling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16
counters is immediately reset. This helps to align the bit boundaries with the rollovers of the divide by
16 counters. The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection
is done on a best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th coun-
ter states. By using a majority 2 of 3 voting system, the bit value is selected. This is done to improve
the noise rejection feature of the serial port.
Transmit Shift Register
1
TB8
STOP
D8
Fosc/2
Internal
PARIN
Write to
SBUF
Data Bus
TXD
SOUT
0
START
LOAD
CLOCK
1/2
TX START
TX CLOCK
TX SHIFT
SMOD 0
1
1/16
1/16
Serial
Controllor
TI
Serial Interrupt
RX CLOCK
RI
LOAD SBUF
RX SHIFT
SAMPLE
1-To-0
DETECTOR
TX START
Read SBUF
Internal
Data Bus
SBUF
RB8
CLOCK PAROUT
BIT
DETECTOR
RXD
SIN
D8
Receive Shift Register
Figure 16–3 Serial port mode 2
If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit,
and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line.
If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF. Af-
ter shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and
RI is set. However certain conditions must be met before the loading and setting of RI can be done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.
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MODE 3
This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user
must first initialize the Serial related SFR SCON before any communication can take place. This in-
volves selection of the Mode and baud rate. The Timer 1 should also be initialized if modes 1 and 3
are used. In all four modes, transmission is started by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a
clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the
incoming start bit if REN = 1. The external device will start the communication by transmitting the start
bit.
Transmit Shift Register
Timer 1
Timer 2
Overflow
1
TB8
STOP
D8
Overflow
Internal
PARIN
Write to
SBUF
Data Bus
TXD
SOUT
0
START
LOAD
1/2
SMOD
0
1
CLOCK
0
1
1
TX START
TX CLOCK
TX SHIFT
TCLK
1/16
1/16
0
RCLK
Serial
Controllor
TI
Serial Interrupt
RX CLOCK
RI
LOAD SBUF
RX SHIFT
SAMPLE
1-To-0
DETECTOR
TX START
Read SBUF
Internal
Data Bus
SBUF
RB8
CLOCK PAROUT
BIT
DETECTOR
RXD
SIN
D8
Receive Shift Register
Figure 16–4 Serial port mode 3
SM0
SM1
Mode
Type
Baud Clock
Frame
Size
Start
Bit
Stop
Bit
9th bit
Function
0
0
1
0
1
0
0
1
2
Synch.
4 or 12 TCLKS 8 bits
No
1
No
1
None
None
0, 1
Asynch.
Asynch.
Timer 1 or 2
10 bits
11 bits
32 or 64
TCLKS
1
1
1
1
3
Asynch.
Timer 1 or 2
11 bits
1
1
0, 1
Table 16–5 Serial Ports Modes
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17 FLASH ROM CODE BOOT MODE SLECTION
The W78E054D/W78E052D boots from APROM program (16K/8K bytes) or LDROM program (2K
bytes) at power on reset or external reset.
BOOT MODE Select by CONFIG bits
Config boot select at Power-on reset and external reset.
CBS (CONFIG.2)
1: Boot from APROM (0x0000).
0: Boot from LDROM (0x3800).
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18 ISP (IN-SYSTEM PROGRAMMING)
ISP is the ability of program MCU to be programmed while F/W code in AP-ROM or LD-ROM. (Note:
Timer 0 for program, erase, read on ISP mode. ISP operation voltage 3.3- 5.5V)
Part 1:2KB APROM
procedure of entering
START
In-System Programming Mode
Enter In-System
NO
Programming Mode ?
(conditions depend on
Execute the normal
Application program
user's application)
YES
Setting control registers
MOV SFRCN,#3Fh
MOV SFRFD,#ABh
MOV SFRAL,#FFh
MOV SFRAH,#FFh
MOV CHPCON,#03h
END
Setting Timer (about 450 us)
and enable timer interrupt
Start Timer and enter idle Mode.
(CPU will be wakened from idle mode
by timer interrupt, then enter In-System
Programming mode)
GO
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Part 2:
Procedure of Updating
the 2KB APROM
GO
Timer Interrupt Service Routine:
Stop Timer & disable interrupt
NO
End of Programming
Is F02K BOOT Mode?
PGM
YES
Setting Timer and enable Timer
interrupt for wake-up .
(15 ms for erasing operation)
End of erase
operation. CPU will
be wakened by Timer
interrupt.
Start Timer and enter IDLE
Mode.
Setting erase operation mode:
MOV ERPAGE,#02H
(Erasing...)
MOV SFRCN,#22H
(Erase 2KB APROM ISP )
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PGM
Part 2:
Procedure of Updating
the 2KB APROM
Read_Compay_ID
OV SFRCN,#0Bh
MOV CHPCON,#03h
YES
End of Programming ?
NO
Setting Timer and enable Timer
interrupt for wake-up .
(50us for program operation)
Read_Device_ID
MOV SFRCN,#0Ch
MOV CHPCON,#03h
Get the parameters of new code
(Address and data bytes)
through I/O ports, UART or
Read_VT
other interfaces.
MOV SFRCN,#0Dh
MOV SFRAL,#01h
MOV SFRAH,#00h
MOV CHPCON,#03h
Setting control registers for
programming:
MOV SFRAH,#ADDRESS_H
MOV SFRAL,#ADDRESS_L
MOV SFRFD,#DATA
MOV SFRCN,#21H
Read_Dist
.
Is currently in the
F02K BOOT Mode ?
MOV SFRCN,#0Eh
MOV SFRAL,#02h
MOV SFRAH,#00h
MOV CHPCON,#03h
Ease 14K AP programming:
MOV ERPAGE,#01
MOV SFRCN,#22H
.
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PGM
Part 2:
Procedure of Updating
the 2KB APROM
Read_Compay_ID
Read_Device_ID
Read_VT
YES
End of Programming ?
Read_Dist
NO
Setting Timer and enable Timer
interrupt for wake-up .
Is currently in the
F02K BOOT Mode ?
(50us for program operation)
NO
Get the parameters of new code
(Address and data bytes)
through I/O ports, UART or
YES
Software reset CPU and
re-boot from the 2KB
other interfaces.
APROM.
MOV CHPCON,#81h
Setting control registers for
programming:
MOV SFRAH,#ADDRESS_H
MOV SFRAL,#ADDRESS_L
MOV SFRFD,#DATA
MOV SFRCN,#21H
Hardware Reset
to re-boot from
new 2 KB APROM.
(S/W reset is
invalid in F02K BOOT
Mode)
END
Executing new code
from address
00H in the 2KB APROM.
Ease 14K AP programming:
MOV ERPAGE,#01
MOV SFRCN,#22H
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W78E054D/W78E052D Data Sheet
19 CONFIG BITS
During the on-chip Flash EPROM operation mode, the Flash EPROM can be programmed and veri-
fied repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected.
The protection of Flash EPROM and those operations on it are described below.
The W78E054D/W78E052D has a Special Setting Register, the config Bits, which cannot be accessed
in normal mode. The Security register can only be accessed from the Flash EPROM operation mode.
Those bits of the Security Registers cannot be changed once they have been programmed from high
to low. They can only be reset through erase-all operation. The Security Register is addressed in the
Flash EPROM operation mode by address #0FFFFh.
0000h
3FFFh
B6
B7
B5
B4
Config Bits
B3 B2 B1 B0
16/8/4KB
Flash EPROM
B0: Lock bit,
logic 0 : active Lock Flash
logic 1 : no Lock Flash.
B1: MOVC inhibit,
Program Memory
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory
logic 1 : no restriction.
B2: CBS
logic 0: Boot from LD block (0x3800).
logic 1: Boot from AP block (default).
B3: NSR ( Noise Sensitivity Reduction)
logic 0: Noise Sensitivity Reduction is enabled.
logic 1: Noise Sensitivity Reduction is disabled.
B5: Machine Cycle Select
Reserved
logic 0 : 6T
logic 1 : 12T
Security Register
FFFFh
B7: Crystal Select
logic 0 : 1/2 gain, 24MHz
logic 1 : Full gain, 40MHz
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
Special Setting Register
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W78E054D/W78E052D Data Sheet
Bit 0: Lock bits
0: Lock enable
1: Lock disable
This bit is used to protect the customer's program code in the W78E054D/W78E052D. It may be set
after the programmer finishes the programming and verifies sequence. Once these bits are set to logic
0, both the FLASH data and Special Setting Registers cannot be accessed again.
Bit 1: MOVC inhibit
0: MOVC inhibit enable
1: MOVC inhibit disable
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC in-
struction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
Bit 2: CBS
Config boot select at Power-on reset and external reset.
CBS=1: Boot from APROM block (default).
CBS=0: Boot from LDROM block (0x3800).
Bit 3: NSR (Noise Sensitivity Reduction)
NSR=1: Noise Sensitivity Reduction is disabled.
NSR=0: Noise Sensitivity Reduction is enabled.
Bit 4: Must be “1”
Bit 5: Machine Cycle Select
This bit is select MCU core, default value is logic 1, and the MCU core is 12T per instruction. Once this
bit is set to logic 0, the MCU core is 6T per instruction.
Bit 6: Must be “1”
Bit 7: Crystal Select
0 (24MHz): If system clock is slower than 24MHz, programming “0”. It can reduce EMI effect and save
the power consumption.
1 (40MHz): If system clock is faster than 24MHz, programming “1”.
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W78E054D/W78E052D Data Sheet
20 ELECTRICAL CHARACTERISTICS
20.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
Min
MAX
5.5
UNIT
V
DC Power Supply
Input Voltage
2.4
VDDVSS
VIN
VSS-0.3
-40
VDD+0.3
+85
V
Operating Temperature
(W78E054D/W78E052D)
TA
C
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely af-
fects the lift and reliability of the device.
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W78E054D/W78E052D Data Sheet
20.2 DC ELECTRICAL CHARACTERISTICS
TA =-40℃~+85℃, VDD=2.4V~5.5V, VSS=0V
*1
Sym
VIL
Parameter
Test Condition
Min
Max
Unit
Typ
Input Low Voltage
0.2VDD
-0.1
2.4 < VDD < 5.5V
-0.5
V
(Ports 0~4, /EA, XTAL1,
RST)
Input High Voltage
(Ports 0~4, /EA)
VDD+
0.5
0.2VDD
+0.9
2.4 < VDD < 5.5V
V
V
VIH
Input High Voltage
(XTAL1, RST)
VDD+
0.5
2.4 < VDD < 5.5V
0.7VDD
VIH1
*3,*4
*4
Output Low Voltage
VDD=4.5V, IOL= 12.0mA
0.4
V
V
V
VOL
VOH1
VOH2
(Ports 0~4, ALE,
/PSEN)
*3,*4
VDD=2.4V, IOL= 10mA
VDD=4.5V, IOH= -300A
Output High Voltage
(Ports 1~4)
2.4
2.0
*4
VDD=2.4V, IOH= -35A
*4
*4
Output High Voltage
VDD=4.5V, IOH= -8.0mA
VDD=2.4V, IOH= -2.2mA
2.4
2.0
(Ports 0 & 2 in external
bus mode, ALE, /PSEN)
Logical 0 Input Current
(Ports 1~4)
VDD=5.5V, VIN=0.4V
VDD=5.5V, VIN=2.0V
0 < VIN < VDD+0.5
-45
-510
±0.1
-50
-650
±10
IIL
ITL
ILI
A
A
A
Logical 1-to-0 Transition
*2
Current (Ports 1~4)
Input Leakage Current
(Port 0)
*5
Active mode
9.5
16.0
3.1
@12MHz, VDD=5.0V
@40MHz, VDD=5.0V
@12MHz, VDD=3.3V
@20MHz, VDD=3.3V
mA
mA
3.7
Idle mode
Power Supply Current
IDD
@12MHz, VDD=5.0V
@40MHz, VDD=5.0V
@12MHz, VDD=3.3V
@20MHz, VDD=3.3V
3.5
9.2
1.2
1.7
Power-down mode
2.4 < VDD < 5.5V
<1
50
A
RST-pin Internal Pull-
down Resistor
100
225
KΩ
RRST
Note:
*1: Typical values are not guaranteed. The values listed are tested at room temperature and based on
a limited number of samples.
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W78E054D/W78E052D Data Sheet
*2: Pins of ports 1~4 source a transition current when they are being externally driven from 1 to 0.
The transition current reaches its maximum value when VIN is approximately 2V.
*3: Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 20mA
Maximum IOL per 8-bit port: 40mA
Maximum total IOL for all outputs: 100mA
*4: If IOH exceeds the test condition, VOH will be lower than the listed specification.
If IOL exceeds the test condition, VOL will be higher than the listed specification.
*5: Tested while CPU is kept in reset state and EA=H, Port0=H.
Voltage
4.5-5.5V
4.5-5.5V
2.4V
Max. Frequency
40MHz
6T/12T mode
Note
12T
6T
20MHz
20MHz
12T
6T
2.4V
10MHz
Frequency VS Voltage Table
20.3 AC ELECTRICAL CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experi-
ence less than a 20 nS variation.
20.3.1 Clock Input Waveform
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
Clock Period
Clock High
Fop
TCP
Tch
Tcl
0
-
-
-
-
40
-
-
MHz
nS
nS
1
2
3
3
25
10
10
Clock Low
-
nS
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
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W78E054D/W78E052D Data Sheet
20.3.2 Program Fetch Cycle
PARAMETER
SYMBOL
Taas
MIN.
TYP.
-
MAX.
-
UNIT
nS
NOTES
4
Address Valid to ALE Low
1 TCP -
Address Hold from ALE Low
Taah
Tapl
1 TCP -
-
-
-
-
nS
nS
1, 4
4
1 TCP -
PSEN
ALE Low to
Low
Tpda
Tpdh
Tpdz
Talw
-
-
2 TCP nS
1 TCP nS
1 TCP nS
2
3
PSEN
Low to Data Valid
0
0
-
PSEN
PSEN
Data Hold after
Data Float after
High
High
-
ALE Pulse Width
2 TCP -
2 TCP
-
nS
4
4
Tpsw
3 TCP -
3 TCP
-
nS
PSEN
Notes:
Pulse Width
1. P0.0P0.7, P2.0P2.7 remains stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
PSEN
3. Data have been latched internally prior to
going high.
4. "" (due to buffer driving delay and wire loading) is 20 nS.
20.3.3 Data Read Cycle
PARAMETER
RD
SYMBOL
Tdar
MIN.
TYP.
-
MAX.
UNIT
nS
NOTES
1, 2
3 TCP -
3 TCP +
4 TCP
ALE Low to
Low
Tdda
Tddh
Tddz
Tdrd
-
-
nS
nS
nS
nS
1
RD
Low to Data Valid
0
-
2 TCP
2 TCP
-
RD
RD
Data Hold from
Data Float from
High
High
0
-
6 TCP
2
6 TCP -
RD
Pulse Width
Notes:
1. Data memory access time is 8 TCP.
2. "" (due to buffer driving delay and wire loading) is 20 nS.
20.3.4 Data Write Cycle
PARAMETER
SYMBOL
Tdaw
MIN.
TYP.
-
MAX.
UNIT
nS
nS
3 TCP -
3 TCP +
WR
ALE Low to
Low
Tdad
-
-
1 TCP -
WR
Data Valid to
Low
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W78E054D/W78E052D Data Sheet
Tdwd
Tdwr
-
-
-
nS
nS
1 TCP -
6 TCP -
WR
Data Hold from
WR
High
6 TCP
Pulse Width
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
20.3.5 Port Access Cycle
PARAMETER
SYMBOL
Tpds
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
-
-
-
-
-
-
Tpdh
nS
Tpda
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing
data are referenced to ALE, since it provides a convenient reference.
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W78E054D/W78E052D Data Sheet
20.4 TIMING waveforms
20.4.1 Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
T
ALW
T
APL
PSEN
T
PSW
T
AAS
PORT 2
PORT 0
T
PDA
T
AAH
T T
PDH, PDZ
A0-A7
A0-A7
Code A0-A7
Code
Data
Data
A0-A7
20.4.2 Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
T
T
DDA
DAR
T
T
DDH, DDZ
T
DRD
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W78E054D/W78E052D Data Sheet
20.4.3 Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
DATA OUT
T
DWD
T
DAD
T
T
DWR
DAW
20.4.4 Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDH
TPDA
DATA OUT
PORT
INPUT
SAMPLE
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W78E054D/W78E052D Data Sheet
20.4.5 Reset Pin Access Cycle
65536 crystal clock
12 Crystal Clock = 1 Machine Cycle
Crystal
Clock
ALE
VDD
Power
~0.7V
~2.0V
VSS
POF
Reset
Pin
24 crystal clock
Internal
Reset
1 = reset state
0 = cpu free running
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W78E054D/W78E052D Data Sheet
21 APPLICATION CIRCUITS
21.1 External Program Memory and Crystal
VCC
31
19
39 AD0
38 AD1
37 AD2
36 AD3
35 AD4
34 AD5
33 AD6
32 AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
7
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
11 AD0
12 AD1
13 AD2
15 AD3
16 AD4
17 AD5
18 AD6
19 AD7
EA
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A0
A1
A2
A3
A4
A5
A6
A7
O0
O1
O2
O3
O4
O5
O6
O7
C1
C2
CRYSTAL
XTAL1
8
13
14
17
18
R
18
9
XTAL2
RST
A8
A9
A8
A9
RST
21 A8
22 A9
1
11
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
OC
G
A10
A11
A12
A13
A14
A15
A10
A11
A12
A13
A14
A15
12
13
14
15
23 A10
24 A11
25 A12
26 A13
27 A14
28 A15
P3.2/INT0
P3.3/INT1
P3.4/T0
VCC
74373
P3.5/T1
10uF
8.2K
1
2
3
4
5
6
7
8
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
20
22
CE
OE
16
17
29
30
11
10
WR/P3.6
RD/P3.7
PSEN
ALE
TXD/P3.1
RXD/P3.0
64KB ROM
PSEN
ALE
W78I054DDG-40DIP
W78I052DDG-40DIP
Figure A
21.2 Expanded External Data Memory and Oscillator
VCC
VCC
31
19
39 AD0
38 AD1
37 AD2
36 AD3
35 AD4
34 AD5
33 AD6
32 AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
7
2
5
6
9
12
15
16
19
A0
A0
A1
A2
A3
A4
A5
A6
A7
12
13 AD0
14 AD1
15 AD2
17 AD3
18 AD4
19 AD5
20 AD6
21 AD7
EA
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
A1
A2
A3
A4
A5
A6
A7
11
10
9
8
7
6
5
27
26
23
25
4
28
3
Oscillator
XTAL1
8
13
14
17
18
18
9
XTAL2
RST
A8
A9
A8
A9
RST
21 A8
22 A9
1
11
VCC
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
OC
G
A10
A11
A12
A13
A14
A15
22
30
24
29
A10
A11
A12
A13
A14
A15
CS1
CS2
OE
12
13
14
15
23 A10
24 A11
25 A12
26 A13
27 A14
28 A15
P3.2/INT0
P3.3/INT1
P3.4/T0
VCC
74373
WE
P3.5/T1
10uF
31
1
2
3
4
5
6
7
8
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
64KB RAM
16
17
29
30
11
10
/WR
/RD
WR/P3.6
RD/P3.7
PSEN
ALE
TXD/P3.1
RXD/P3.0
8.2K
ALE
W78I054DDG-40DIP
W78I052DDG-40DIP
Figure B
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Revision A13
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W78E054D/W78E052D Data Sheet
21.3 Internal Program Memory and Oscillator for EFT application
VCC
10K
31
19
39 AD0
38 AD1
37 AD2
36 AD3
35 AD4
34 AD5
33 AD6
32 AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
7
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
12
11
10
9
8
7
13 AD0
14 AD1
15 AD2
17 AD3
18 AD4
19 AD5
20 AD6
21 AD7
EA
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
C19
C18
CRYSTAL
XTAL1
8
13
14
17
18
R
6
5
18
9
XTAL2
RST
A8
A9
27
26
23
25
4
28
3
A8
A9
RST
21 A8
22 A9
1
11
VCC
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
OC
G
A10
A11
A12
A13
A14
A15
22
30
24
29
A10
A11
A12
A13
A14
A15
CS1
CS2
OE
12
13
14
15
23 A10
24 A11
25 A12
26 A13
27 A14
28 A15
P3.2/INT0
P3.3/INT1
P3.4/T0
VCC
74373
WE
P3.5/T1
10uF
8.2K
31
1
2
3
4
5
6
7
8
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
64KB RAM
16
17
29
30
11
10
/WR
/RD
WR/P3.6
RD/P3.7
PSEN
ALE
TXD/P3.1
RXD/P3.0
ALE
W78I054DDG-40DIP
W78I052DDG-40DIP
Figure C
21.4 Reference Value of XTAL
CRYSTAL
6 MHz
C1
C2
R
68P
47P
20P
10P
5P
68P
47P
20P
10P
5P
-
16 MHz
24 MHz
32 MHz
40 MHz
-
-
6.8K
4.7K
Above table shows the reference values for crystal applications.
Notes:
1. C1, C2, R components refer to Figure A,C
2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.
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W78E054D/W78E052D Data Sheet
22 APPLICATION NOTE
In-system Programming Software Examples
This application note illustrates the in-system programmability of the microcontroller. In this example,
microcontroller will boot from 2K LDROM bank enter in-system programming mode for programming
the contents of APROM, this sample to Erase APROM, Erase Verify APROM, Read one byte for
APROM, Write one byte for APROM, Read CID/DID. .
EXAMPLE: Base on Keil C51 Compiler
$nomod51
#include <reg52.h>
EAPAGE
CHPCON
SFRAL
SFRAH
SFRFD
SFRCN
DATA
DATA
DATA
DATA
DATA
DATA
0BEh
0BFh
0C4h
0C5h
0C6h
0C7h
;CPU Clock = 12MHz/12T mode
READ_TIME
EQU
EQU
EQU
1
PROGRAM_TIME
ERASE_TIME
50
5000
;For W78E(I)054D
APROM_END_ADDRESS
;For W78E(I)052D
EQU
03800h
02000h
;APROM_END_ADDRESS EQU
FLASH_STANDBY
READ_CID
EQU
EQU
EQU
EQU
EQU
EQU
00111111B
00001011B
00001100B
00100010B
00001001B
00100001B
00001010B
00000000B
READ_DID
ERASE_ROM
ERASE_VERIFY
PROGRAM_ROM
PROGRAM_VERIFY_ROM EQU
READ_ROM
EQU
ORG
03800h
mov
mov
SP,#060h
TMOD,#01h
;Set Timer0 as mode1
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W78E054D/W78E052D Data Sheet
call
call
call
call
call
call
call
call
sjmp
Read_Company_ID
Read_Device_ID_HIGH
Read_Device_ID_LOW
Erase_APROM
Erase_Verify_ROM
Program_APROM
Program_Verify_APROM
Software_Reset
$
;************************************************************************
; * Read_Company_ID
;************************************************************************
Read_Company_ID:
mov
mov
SFRCN,#READ_CID
TL0,#LOW (65536-READ_TIME)
mov
TH0,#HIGH(65536-READ_TIME)
setb
mov
TR0
CHPCON,#00000011b
clr
clr
TF0
TR0
mov
A,SFRFD
;check Read company ID
cjne
ret
A,#0DAh,CID_Error
CID_Error:
mov
P1,#01h
$
sjmp
;************************************************************************
; * read device ID high
;************************************************************************
Read_Device_ID_HIGH:
mov
mov
mov
mov
mov
setb
mov
clr
clr
mov
ret
SFRAL,#0FFh
SFRAH,#0FFh
SFRCN,#READ_DID
TL0,#LOW (65536-READ_TIME)
TH0,#HIGH(65536-READ_TIME)
TR0
CHPCON,#00000011b
TF0
TR0
A,SFRFD
;read device id high byte
;*************************************************************************
; * read device ID low
;*************************************************************************
Read_Device_ID_LOW:
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W78E054D/W78E052D Data Sheet
mov
mov
mov
mov
mov
setb
mov
clr
clr
mov
ret
SFRAL,#0FEh
SFRAH,#0FFh
SFRCN,#READ_DID
TL0,#LOW (65536-READ_TIME)
TH0,#HIGH(65536-READ_TIME)
TR0
CHPCON,#00000011b
TF0
TR0
A,SFRFD
;read device id low byte
;************************************************************************
;* Flash standby mode
;************************************************************************
Standby:
mov
mov
mov
mov
setb
mov
clr
clr
ret
SFRCN,#FLASH_STANDBY
SFRFD,#0FFh
SFRAL,#0FFh
SFRAH,#0FFh
TR0
CHPCON,#00000011b
TF0
TR0
;************************************************************************
;* Erase APROM
;************************************************************************
Erase_APROM:
mov
mov
mov
mov
setb
mov
mov
clr
clr
ret
EAPAGE,#01h
SFRCN,#ERASE_ROM
;set EAPAGE is APROM
TL0,#LOW (65536-ERASE_TIME)
TH0,#HIGH(65536-ERASE_TIME)
TR0
CHPCON,#00000011b
EAPAGE,#00h
;clear EAPAGE
TF0
TR0
;************************************************************************
; * VERIFY APROM BANK
;************************************************************************
Erase_Verify_ROM:
mov
mov
SFRCN,#ERASE_VERIFY
DPTR,#0000h
er_lp:
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W78E054D/W78E052D Data Sheet
mov
mov
mov
mov
setb
mov
clr
clr
mov
cjne
inc
mov
cjne
mov
cjne
ret
TL0,#LOW (65536-READ_TIME)
TH0,#HIGH(65536-READ_TIME)
SFRAL,DPL
SFRAH,DPH
TR0
CHPCON,#00000011b
TF0
TR0
A,SFRFD
A,#0FFh,Erase_Verify_Error
DPTR
R0,DPL
R0,#LOW (APROM_END_ADDRESS),er_lp
R1,DPH
R1,#HIGH(APROM_END_ADDRESS),er_lp
Erase_Verify_Error:
mov
sjmp
P1,#02h
$
;**************************************************************************
;*PROGRAMMING APROM BANK, APROM write 55h,AAh,55h,AAh........
;**************************************************************************
Program_APROM:
mov
mov
mov
SFRCN,#PROGRAM_ROM
DPTR,#0000h
A,#055h
wr_lp:
mov
mov
mov
mov
mov
setb
mov
clr
clr
cpl
inc
mov
cjne
mov
cjne
ret
TH0,#HIGH(65536-PROGRAM_TIME)
TL0,#LOW (65536-PROGRAM_TIME)
SFRFD,A
SFRAL,DPL
SFRAH,DPH
TR0
CHPCON,#00000011b
TF0
TR0
A
DPTR
R0,DPL
R0,#LOW (APROM_END_ADDRESS),wr_lp
R1,DPH
R1,#HIGH(APROM_END_ADDRESS),wr_lp
;**************************************************************************
;*Program Verify APROM BANK, read APROM 55h,AAh,55h,AAh........
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W78E054D/W78E052D Data Sheet
;**************************************************************************
Program_Verify_APROM:
mov
mov
mov
SFRCN,#PROGRAM_VERIFY_ROM
DPTR,#0000h
B,#055h
rd_lp:
mov
mov
mov
mov
setb
mov
clr
clr
mov
cjne
mov
cpl
mov
inc
mov
cjne
mov
cjne
ret
TH0,#HIGH(65536-READ_TIME)
TL0,#LOW (65536-READ_TIME)
SFRAL,DPL
SFRAH,DPH
TR0
CHPCON,#00000011b
TF0
TR0
A,SFRFD
A,B,Program_Fail
A,B
A
B,A
DPTR
R0,DPL
R0,#LOW (APROM_END_ADDRESS),rd_lp
R1,DPH
R1,#HIGH(APROM_END_ADDRESS),rd_lp
Program_Fail:
mov
P1,#03h
sjmp
$
;**************************************************************************
;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU TO APROM
;**************************************************************************
Software_Reset:
MOV
sjmp
end
CHPCON,#081h
$
;CHPCON=081h, SOFTWARE RESET to APROM.
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W78E054D/W78E052D Data Sheet
23 PACKAGE DIMENSIONS
23.1 40-pin DIP
D
40
21
1
E
20
1
E
S
c
2
1
Base Plane
A
A
L
A
SeatingPlane
B
e1
eA
α
B1
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Min
Max Min
0.210
Max
5.33
A
1
A
2
A
0.010
0.150
0.25
0.155 0.160
3.81
0.41
1.22
0.20
3.94
0.46
4.06
0.56
0.016 0.018
0.022
0.054
B
0.050
1.27
1.37
0.048
0.008
1
B
c
0.36
0.010 0.014
2.055 2.070
0.25
52.58
15.49
13.97
2.79
52.20
15.24
13.84
2.54
D
E
0.610
0.590 0.600
14.99
13.72
0.540
0.545
1
0.550
0.110
E
1
e
0.090 0.100
2.29
3.05
0
0.140
15
3.30
0.120
0
0.130
0.650
3.56
15
L
α
A
e
17.02
0.630
0.670 16.00
0.090
16.51
2.29
S
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W78E054D/W78E052D Data Sheet
23.2 44-pin PLCC
H D
D
6
1
44
40
7
39
E
H
E
G
E
17
29
18
28
c
L
2
A
A
1
A
e
b
b1
y
Seating Plane
GD
Dimension in inch
Dimension in mm
Symbol
Min Nom Max Min Nom Max
0.185
4.70
A
0.020
0.51
3.68
1
A
2
0.145 0.150
0.026 0.028
0.016 0.018
3.81
0.71
0.46
0.25
3.94
0.81
0.56
0.36
A
b
0.155
0.032 0.66
0.022
1
0.41
b
c
0.008 0.010 0.014 0.20
16.46 16.59 16.71
16.46 16.59 16.71
1.27 BSC
0.648 0.653 0.658
D
E
e
0.648 0.653
0.658
0.050 BSC
0.590
0.590
0.680
0.680
14.99 15.49 16.00
14.99 15.49 16.00
17.27 17.53 17.78
17.27 17.53 17.78
G
GE
D
0.610 0.630
0.610 0.630
0.690 0.700
0.690 0.700
H
H
L
y
D
E
0.090 0.100
2.54
2.79
0.10
0.110 2.29
0.004
23.3 44-pin PQFP
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W78E054D/W78E052D Data Sheet
HD
D
34
44
33
1
E
E
H
11
12
22
e
b
c
2
A
A
1
See Detail F
L
A
y
SeatingPlane
L1
Detail F
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Min
Max Min
-
Max
-
A
1
A
2
A
b
c
D
E
e
0.002 0.01
0.02
0.25
2.05
0.35
0.15
10.00
10.00
0.80
0.05
1.90
0.25
0.10
9.9
0.5
0.081 0.087
0.075
0.01
2.20
0.45
0.25
10.1
10.1
0.014
0.006
0.018
0.010
0.004
0.390
0.390
0.394 0.398
0.394 0.398
.0315
9.9
D
H
0.530
0.520
0.510
12.95
13.20 13.45
0.530 12.95 13.20 13.45
0.510 0.520
HE
L
0.65
0.037
0.8
0.025
0.031
0.063
0.95
1.60
1
L
y
0.10
10
0.004
10
0
0
0
Publication Release Date: Jun 9, 2015
Revision A13
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W78E054D/W78E052D Data Sheet
23.4 48-pin LQFP
Publication Release Date: Jun 9, 2015
Revision A13
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W78E054D/W78E052D Data Sheet
23.5 44-pin TQFP
Publication Release Date: Jun 9, 2015
Revision A13
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W78E054D/W78E052D Data Sheet
24 REVISION HISTORY
VERSION
A01
DATE
PAGE
DESCRIPTION
August 14, 2008
November 3, 2008
December 15, 2008
January 7, 2007
-
Initial Issued
A02
-
Update DC table typing error.
Update CONFIG bit table, and ISP BOOT
Update VIL and VIH
A03
-
A04
70
March 9,
2009
A05
A06
A07
43
Update soft reset, only LD jump to AP function.
1. Rename SFR Register POR (0x86H) to P0UPR.
2. Revise some typing errors in data sheet.
18
-
-
March 20,
2009
3. Update DC table
April 22,
2009
68
1. Revise Type Application Circuit in data sheet.
30
1. Add the ISP control table.
June 30,
2009
61
2. Revise content of Char. 17.
A08
81
3. Modify the ISP demo code.
All Pages
4. Remove the “Preliminary” character for each page.
68
1. Revise the “CONFIG BITS” description for Bit4, Bit6 and Bit7.
A09
A10
December 30, 2009
October 20, 2011
2. Add the timing for external reset pin.
77
28
70
1. Revised the CHPCON description
2. Added description for “21.4 Reference Value of XTAL
April 18,
2012
A11
A12
A13
73
73
1. Removed 20.3.6 character.
Aug 31,
2012
1. Removed W78E051D part number.
2. Added TQFP44 package
Jun 9,
2015
1. Revised timing of “Data Read Cycle”
Publication Release Date: Jun 9, 2015
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Revision A13
W78E054D/W78E052D Data Sheet
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of dy-
namic, brake or safety systems designed for vehicular use, traffic signal instruments, all types
of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Publication Release Date: Jun 9, 2015
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Revision A13
相关型号：
W78E054DFG
The W78E054D/W78E052D/W78E051D series is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption. The instruction set for the W78E054D
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