32F8030-CL [ETC]
Programmable Electronic Filter; 可编程电子滤波器
| 型号： | 32F8030-CL |
| 厂家： | 
ETC |
| 描述： | Programmable Electronic Filter |
| 文件： | 总10页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSI 32F8030
Programmable
Electronic Filter
A TDK Group Company
April 1995
DESCRIPTION
FEATURES
The SSI 32F8030 Programmable Electronic Filter pro-
vides an electronically controlled low–pass filter with a
separate differentiated low–pass output. A seven–
pole, 0.05° Equiripple-type linear phase, low–pass
filter is provided along with a single-pole, single-zero
differentiator. Both outputs have matched delays. The
delay matching is unaffected by any amount of pro-
grammed high frequency peaking (boost) or band-
width. This programability, combined with low group
delay variation makes the SSI 32F8030 ideal for use in
many applications. Double differentiation high fre-
quency boost is accomplished by a two–pole, low–
pass with a two–pole, high–pass feed forward section
to provide complementary real axis zeros. A variable
attenuator is used to program the zero locations, which
controls the amount of boost.
•
Ideal for:
- constant density recording applications
- magnetic tape recording
•
•
•
Programmable filter cutoff frequency
(ƒc = 250 kHz to 2.5 MHz)
Programmable high frequency peaking
(0 to 9 dB boost at the filter cutoff frequency)
Matched normal and differentiated low-pass
outputs
•
•
Differential filter input and outputs
±3.0% group delay variation from
0.2 ƒc to 1.75 ƒc, 0.25 MHz ≤ ƒc ≤ 2.5 MHz
•
•
•
•
Total harmonic distortion less than 1%
+5V only operation
The SSI 32F8030 programmable boost and bandwidth
characteristics can be controlled by external DACs or
DACs provided in the SSI 32D4661 Time Base Gen-
erator. Fixed characteristics are easily accomplished
with three external resistors. In addition, boost can be
switched in or out by a logic signal.
16-Lead SON, and SOL packages
5 mW idle mode
The SSI 32F8030 requires only a +5V supply and is
available in 16-Lead SON, and SOL packages.
BLOCK DIAGRAM
PIN DIAGRAM
VO_NORM+
VIN+
VIN-
Low Pass
Filter
Low Pass
Filter
GND1
VO_NORM-
VO_NORM+
VCC1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VO_DIFF+
VO_DIFF-
PWRON
VR
Summer
VO_NORM-
VO_DIFF+
VO_DIFF-
High Pass
Filter
Variable
Atten.
High Pass
Filter
VIN-
VCC2
IFP
VIN+
VBP
VFP
VBP
IFP
FBST
GND2
VREF
BIAS
VR
Filter
Control
VFP
PWRON
FBST
GND1
GND2
VCC1
VCC2
CAUTION: Use handling procedures necessary
for a static sensitive component.
1
04/14/95 - rev.
SSI 32F8030
Programmable
Electronic Filter
FUNCTIONAL DESCRIPTION
SLIMMER HIGH FREQUENCY BOOST
PROGRAMMING
The SSI 32F8030, a high performance programmable
electronic filter, provides a low pass 0.05° Equiripple-
typelinearphasesevenpolefilterwithmatchednormal
and differentiated outputs. The device has been opti-
mized for usage with several Silicon Systems prod-
ucts,includingtheSSI32D4661TimeBaseGenerator,
the SSI 32P54x family of Pulse Detectors, and the SSI
32P4720 Combo device (Data Separator and Pulse
Detector).
The amplitude of the output signal at frequencies near
the cutoff frequency can be increased using this fea-
ture. Applying an external voltage to pin VBP which is
proportional to reference output voltage VR (provided
by the VR pin) will set the amount of boost. A fixed
amount of boost can be set by an external resistor
dividernetworkconnectedfrompinVBPtopinsVRand
GND. No boost is applied if pin FBST, frequency boost
enable, is at a low logic level.
CUTOFF FREQUENCY PROGRAMMING
The amount of boost FB at the cutoff frequency Fc is
related to the voltage VBP by the formula
The SSI 32F8030 programmable electronic filter can
be set to a filter cutoff frequency from 250 kHz to 2.5
MHz (with no boost).
FB (ideal, in dB) = 20 log [1.884(VBP/VR)+1], where
10
0<VBP<VR.
Cutoff frequency programming can be established
usingeitheracurrentsourcefedintotheIFPpin,whose
output current is proportional to the SSI 32F8030
output reference voltage VR, or by means of an exter-
nal resistor tied from the output voltage reference pin
VR to pin VFP. The former method is optimized using
the SSI 32D4661 Time Base Generator, since the
current source into pin IFP is available at the DAC F
output of the 32D4661. Furthermore, the voltage
reference input is supplied to pin VR3 of the 32D4661
by the reference voltage VR from the VR pin of the
32F8030. This reference voltage is an internally gen-
erated bandgap reference, which typically varies less
than 1 % over voltage supply and temperature varia-
tion. (ForthecalculationsbelowIVFP=currentintoIFP
or VFP pins).
The cutoff frequency, determined by the -3dB point
relative to a very low frequency value (< 10kHz), is
related to the current IVFP injected into pin IFP by the
formula
Fc (ideal, in MHz) = 3.125•IFP = 3.125•IVFP•2.2/VR,
where IFP and IVFP are in mA, 0.08<IFP<0.8 mA, and
VR is in volts.
If a current source is used to inject current into pin IFP,
pin VFP should be left open.
If the 32F8030 cutoff frequency is set using voltage VR
tobiasuparesistortiedtopinVFP,thecutofffrequency
is related to the resistor value by the formula
Fc (ideal, in MHz) = 3.125•IFP = 3.125•2.2/(3•Rx)
where Rx is in kΩ, & 0.917 kΩ <Rx<9.17 kΩ.
If pin VFP is used to program cutoff frequency, pin IFP
should be left open.
2
SSI 32F8030
Programmable
Electronic Filter
PIN DESCRIPTION
NAME
TYPE DESCRIPTION
VIN+, VIN-
I
DIFFERENTIAL SIGNAL INPUTS. The input signals must be AC coupled to
these pins.
VO_NORM+,
VO_NORM-
O
DIFFERENTIAL NORMAL OUTPUTS. The output signals must be AC
coupled.
O
O
VO_DIFF+,
VO_DIFF-
DIFFERENTIAL DIFFERENTIATED OUTPUTS. For minimum time skew,
these outputs should be AC coupled to the pulse detector.
IFP
I
FREQUENCY PROGRAM INPUT. The filter cutoff frequency FC, is set by an
external current IFP, injected into this pin. IFP must be proportional to voltage
VR. This current can be set with an external current generator such as a DAC.
VFP should be left open when using this pin.
VFP
VBP
I
I
FREQUENCY PROGRAM INPUT. The filter cutoff frequency can be set by
programming a current through a resistor from VR to this pin. IFP should be
left open when using this pin.
FREQUENCY BOOST PROGRAM INPUT. The high frequency boost is set
by an external voltage applied to this pin. VBP must be proportional to voltage
VR. A fixed amount of boost can be set by an external resistor divider network
connected from VBP to VR and GND. No boost is applied if the FBST pin is
grounded, or at logic low.
FBST
I
I
FREQUENCY BOOST. A high logic level or open input enables the frequency
boost circuitry.
PWRON
POWER ON. A high logic level enables the chip. A low level puts the chip in
a low power state.
VR
–
I
REFERENCE VOLTAGE. Internally generated reference voltage.
VCC1, VCC2
GND1, GND2
+5 VOLT SUPPLY.
GROUND
–
3
SSI 32F8030
Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER
RATING
Storage Temperature
-65 to +150°C
+130°C
Junction Operating Temperature, Tj
Supply Voltage, VCC1, VCC2
Voltage Applied to Inputs
IFP, VFP Inputs Maximum Current
-0.5 to 7V
-0.5 to VCC + 0.5V
≤1.2 mA
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC1, VCC2
4.5 < VCC1,2 < 5.50V
Ambient Temperature
0 < Ta < 70°C
4
SSI 32F8030
Programmable
Electronic Filter
Power Supply Characteristics
Unless otherwise specified, recommended operating conditions apply.
PARAMETER
CONDITIONS
PWRON ≤ 0.8V
PWRON ≥ 2.0V
PWRON ≥ 2.0V
PWRON ≤ 0.8V
MIN
NOM
MAX
0.5
42
UNIT
mA
ICC
ICC
PD
Power Supply Current
Power Supply Current
Power Dissipation
Power Dissipation
28
mA
140
231
3
mW
mW
PD
DC Characteristics
VIH
VIL
IIH
IIL
High Level Input Voltage
TTL input
2.0
VCC+0.3
0.8
V
V
Low Level Input Voltage
High Level Input Current
Low Level Input Current
-0.3
VIH = 2.7V
VIL = 0.4V
20
µA
mA
–1.5
Filter Characteristics
ƒc = 1.25 MHz unless otherwise stated
FCA
Filter ƒc Accuracy
using IFP pin: IFP = 0.4 mA or 1.125
1.375
MHz
using VFP pin: Rx = 1.84 kΩ
AO
AD
VO_NORM Diff Gain
VO_DIFF Diff Gain
F = 0.67 ƒc, FB = 0 dB
F = 0.67 ƒc, FB = 0 dB
VBP = VR
0.8
0.9AO
8.0
1.20
1.1AO
10.4
V/V
V/V
dB
FBA Frequency Boost Accuracy
9.2
TGD0
Group Delay Variation
Without Boost*
0.25 MHz ≤ ƒc ≤ 2.5 MHz
F = 0.2 ƒc to 1.75 ƒc
–3
+3
+3
%
TGDB
Group Delay Variation
With Boost*
0.25 MHz ≤ ƒc ≤ 2.5 MHz
VBP = VR, F = 0.2 ƒc to 1.75 ƒc
–3
%
VIF Filter Input Dynamic Range
THD = 1% max, F = 0.67 ƒc
1.0
Vpp
(no boost, 1000 pF capacitor across Rx)
VOF
VOF
Filter Normal Output
Dynamic Range
THD = 1% max, F = 0.67 ƒc
VBP = 0 (1000 pF capacitor across Rx)
1.0
1.0
1.0
1.0
Vpp
Vpp
Vpp
Vpp
Filter Normal Output
Dynamic Range
THD = 1% max, F = 0.67 ƒc
VBP = VR (1000 pF capacitor across Rx)
VOF Filter Differentiated Output
Dynamic Range
THD = 1% max, F = 0.67 ƒc
VBP = 0 (1000 pF capacitor across Rx)
VOF Filter Differentiated Output
Dynamic Range
THD = 1% max, F = 0.67 ƒc
VBP = VR (1000 pF capacitor across Rx)
5
SSI 32F8030
Programmable
Electronic Filter
Filter Characteristics (continued)
PARAMETER
CONDITIONS
MIN
NOM
4.0
MAX
UNIT
kΩ
RIN Filter Diff Input Resistance
CIN Filter Diff Input Capacitance*
3.0
5.0
3.0
pF
EOUT
EOUT
EOUT
EOUT
EOUT
EOUT
EOUT
EOUT
IO-
Output Noise Voltage*
Differentiated Output
BW = 100 MHz, Rs = 50Ω,
Iƒp = 0.8 mA, VBP = 0.0V
2.7
3.2
2.0
3.8
2.2
2.1
1.2
2.5
1.5
mVRms
Output Noise Voltage*
Normal Output
BW = 100 MHz, Rs = 50Ω
Iƒp = 0.8 mA, VBP = 0.0V
1.6
3.1
1.8
1.8
1.0
2.0
1.1
mVRms
mVRms
mVRms
mVRms
mVRms
mVRms
mVRms
Output Noise Voltage*
Differentiated Output
BW = 100 MHz, Rs = 50Ω
Iƒp = 0.8 mA, VBP = VR
Output Noise Voltage*
Normal Output
BW = 100 MHz, Rs = 50Ω
Iƒp = 0.8 mA, VBP = VR
Output Noise Voltage*
Differentiated Output
BW = 10 MHz, Rs = 50Ω,
Iƒp = 0.08 mA, VBP = 0.0V
Output Noise Voltage*
Normal Output
BW = 10 MHz, Rs = 50Ω
Iƒp = 0.08 mA, VBP = 0.0V
Output Noise Voltage*
Differentiated Output
BW = 10 MHz, Rs = 50Ω
Iƒp = 0.08 mA, VBP = VR
Output Noise Voltage*
Normal Output
BW = 10 MHz, Rs = 50Ω
Iƒp = 0.08 mA, VBP = VR
Filter Output Sink Current
1.0
2.0
mA
mA
Ω
IO+ Filter Output Source Current
RO Filter Output Resistance**
Sinking 1 mA from pin
70
* Not directly testable in production, design characteristic.
** Single ended
Filter Control Characteristics
VR Reference Voltage Output
2.0
2.40
2.0
V
IVR
Reference Output
Source Current
mA
6
SSI 32F8030
Programmable
Electronic Filter
2
1
1.8
1.6
1 ifp = 80 µA
2 ifp = 224 µA
3 ifp = 368 µA
4 ifp = 512 µA
5 ifp = 656 µA
6 ifp = 800 µA
(ƒc = 250 kHz)
(ƒc = 700 kHz)
(ƒc = 1.15 MHz)
(ƒc = 1.6 MHz)
(ƒc = 2.05 MHz)
(ƒc = 2.5 MHz)
1.4
1.2
1.0
0.8
2
0.6
3
0.4
0.2
4
5
6
0.0
300k
400k 500k
100k
200k
700k
1meg
2meg
3meg 4meg 5meg
Frequency (Hz)
FIGURE 1: Typical Normal/Differentiated Output Group Delay Response
32F8030
GND1
VO_NORM-
VO_NORM+
VCC1 (+5V)
VIN-
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VO_DIFF+
VO_DIFF-
PWR_ON
VR
VCC2 (+5V)
R
x
VIN+
IFP
C
x
VBP
VFP
GND2
FBST
R
BP1
R
BP2
FIGURE 1: 32F8030 Applications Setup 16-Pin SO
VR = 2.2V
IVfp = .33VR/Rx
VFP = .667 VR
IVfp range: 0.08 mA to 0.8 mA
(0.25 MHz to 2.5 MHz)
Cx = 1000 pF needed for THD at low ƒc
VFP is used when programming current is set with a resistor from VR.
When VFP is used IFP must be left open.
7
SSI 32F8030
Programmable
Electronic Filter
to µController
Rx
IR
Cx DACF
VR3
Ref
Serial Control
ƒc
Control
IFP
VR
7-bit
DAC
SUM
FOUT
To Data Sync
Phase
Lock
Loop
Ref
DACI
To Data Sync
Boost
Control
7-bit
DAC
LP
HP
LP
HP
VBP
DACS
7-bit
DAC
DACM
To Data Sync
7-bit
DAC
32F8030
32D4661
2k
Active
Differentiator
IN+
IN–
RD
DFF
OS
To Data Sync
Charge
Pump
BYP
FWR
32P54X
AGC
LEVEL
HYS
IOF = DACF output current
IOF = (0.98F•VR)/127Rx
Rx = (0.98F•VR)/127IOF
F = DAC setting: 0-127
Full scale, F = 127
For range of Max ƒc = 2.5 MHz then IFP = 0.8 mA
Rx = current reference setting resistor
VR = Voltage Reference = 2.2V
Therefore, for Max programming current range to 0.8 mA:
Rx = (0.98)(2.2/0.8) = 2.7 kΩ
Please note that in setups such as this where IFP is used for cutoff frequency programming VFP must be left open.
FIGURE 2: Applications Setup, Constant Density Recording
32F8030, 32P54X, 32D4661
NORM
+
2.95139
S + S 1.54203 + 2.95139
5.37034
S 2+ S 1.14558 + 5.37034
0.86133
+1.31703
NORM
DIFF
A
N
D
2
INPUT
∑
S 2+ S 1.68495 + 1.31703
S + 0.86133
+
–KS 2
S
A
S + 0.86133
S 2+ S 1.68495 + 1.31703
Normalized for ωc = (2π) ƒc = 1
AN and AD are adjusted for unity gain (0 dB) at F = 0.67 ƒc
Denormalize the frequency by substituting S → (S/2πƒc)
Eq for ƒc = 2.5 MHz, S = S / [(2π)(2.5•106)] = S / (1.57080 • 107)
FIGURE 3: 32F8030 Normalized Block Diagram
8
SSI 32F8030
Programmable
Electronic Filter
BOOST (dB) / 20
TABLE 1: 32F8030 Frequency Boost Calculations - K = 1.31703 (10
-1)
Assuming 9.2 dB boost for
VBP = VR
Boost
K
VBP/VR
Boost
K
VBP/VR
1 dB
2 dB
3 dB
4 dB
5 dB
0.16
0.34
0.54
0.77
1.03
0.065
0.137
0.219
0.310
0.413
6 dB
7 dB
8 dB
9 dB
1.31
1.63
1.99
2.40
0.528
0.657
0.802
0.965
(
)
FB/20
10
−1
(
)
VBP
VR
1.884
VBP/VR
Boost
VBP/VR
Boost
or,
VBP
VR
0.1
0.2
0.3
0.4
0.5
1.499 dB
2.777 dB
3.891 dB
4.879 dB
5.765 dB
0.6
0.7
0.8
0.9
1.0
6.569 dB
7.305 dB
7.984 dB
8.613 dB
9.200 dB
boost in dB= 20log 1.884
+1
TABLE 2: Calculations
Typical change in
ƒ-3 dB point
with boost
Boost (dB) Gain @ ƒc(dB) Gain @ peak(dB)
ƒpeak/ƒc
f-3 dB/ƒc
0
1
2
3
4
5
6
7
8
9
-3
-2
-1
0
1
2
3
4
5
6
0.00
0.00
0.00
0.15
0.99
2.15
3.41
4.68
5.94
7.18
no peak
no peak
no peak
0.70
1.05
1.23
1.33
1.38
1.43
1.46
1.00
1.21
1.51
1.80
2.04
2.20
2.33
2.43
2.51
2.59
Notes: 1. ƒc is the original programmed cutoff frequency with no boost
2. ƒ-3 dB is the new -3 dB value with boost implemented
3. ƒpeak is the frequency where the magnitude peaks with boost implemented
i.e., ƒc = 2.5 MHz when boost = 0 dB
if boost is programmed to 5 dB then f-3 dB = 5.5 MHz
ƒpeak = 3.075 MHz
9
SSI 32F8030
Programmable
Electronic Filter
PACKAGE PIN DESIGNATIONS
(Top View)
Thermal Characteristics: θjA
GND1
VO_NORM-
VO_NORM+
VCC1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VO_DIFF+
VO_DIFF-
PWRON
VR
16-lead SON (150 mil)
16-lead SOL (300 mil)
105° C/W
100° C/W
VIN-
VCC2
IFP
VIN+
VBP
VFP
FBST
GND2
16-Lead SON, SOL
CAUTION: Use handling procedures necessary
for a static sensitive component.
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGE MARK
16-lead SON (150 mil)
16-lead SOL (300 mil)
32F8030-CN
32F8030-CL
32F8030-CN
32F8030-CN
No responsibility is assumed by Silicon Systems for use of this product nor for any infringements of patents and trademarks or other rights
of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Silicon Systems. Silicon Systems
reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet
is current before placing orders.
Silicon Systems, Inc., 14351 Myford Road, Tustin, CA 92680-7022 (714) 573-6000, FAX (714) 573-6914
©1991 Silicon Systems, Inc.
04/14/95 - rev.
Protection by the following patents: 5182477, 5235540
10
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