48F4270 [ETC]
TRANSISTOR MOSFET TO-220 ; 晶体管MOSFET TO- 220\n型号: | 48F4270 |
厂家: | ETC |
描述: | TRANSISTOR MOSFET TO-220
|
文件: | 总8页 (文件大小:102K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MTP40N10E
Preferred Device
Power MOSFET
40 Amps, 100 Volts
N–Channel TO–220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain–to–source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
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40 AMPERES
100 VOLTS
R
= 40 mΩ
DS(on)
• Avalanche Energy Specified
N–Channel
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
D
• Diode is Characterized for Use in Bridge Circuits
• I
and V Specified at Elevated Temperature
DSS
DS(on)
G
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
S
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (R
Symbol
Value
100
Unit
Vdc
Vdc
V
DSS
MARKING DIAGRAM
& PIN ASSIGNMENT
= 1.0 MΩ)
V
DGR
100
GS
Gate–to–Source Voltage
– Continuous
4
4
V
GS
±ā20
±ā40
Vdc
Vpk
Drain
– Non–Repetitive (t ≤ 10 ms)
V
GSM
p
Drain Current – Continuous
Drain Current – Continuous @ 100°C
Drain Current – Single Pulse (t ≤ 10 µs)
I
I
40
29
140
Adc
Apk
D
D
TO–220AB
CASE 221A
STYLE 5
I
p
DM
MTP40N10E
LLYWW
Total Power Dissipation
Derate above 25°C
P
D
169
1.35
Watts
W/°C
1
Operating and Storage Temperature
Range
T , T
J stg
–55 to
150
°C
2
1
Gate
3
3
Source
Single Pulse Drain–to–Source Avalanche
E
AS
800
mJ
Energy – Starting T = 25°C
2
J
(V
= 75 Vdc, V
= 10 Vdc, Peak
Drain
DD
GS
= 40 Apk, L = 1.0 mH, R = 25 W)
I
L
G
MTP40N10E
LL
Y
WW
= Device Code
= Location Code
= Year
Thermal Resistance
– Junction to Case
– Junction to Ambient
°C/W
°C
R
R
0.74
62.5
θJC
θJA
= Work Week
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10
seconds
T
260
L
ORDERING INFORMATION
Device
MTP40N10E
Package
Shipping
50 Units/Rail
TO–220AB
Preferred devices are recommended choices for future use
and best overall value.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
November, 2000 – Rev. 2
MTP40N10E/D
MTP40N10E
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Drain–to–Source Breakdown Voltage
V
Vdc
(BR)DSS
(V
= 0 Vdc, I = 0.25 mAdc)
100
–
–
112
–
–
GS
D
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 3.)
mV/°C
µAdc
Zero Gate Voltage Drain Current
I
DSS
GSS
(V
DS
(V
DS
= 100 Vdc, V
= 100 Vdc, V
= 0 Vdc)
= 0 Vdc, T =125°C)
–
–
–
–
10
100
GS
GS
J
Gate–Body Leakage Current (V
= ±20 Vdc, V
DS
= 0 Vdc)
I
–
–
100
nAdc
Vdc
GS
ON CHARACTERISTICS (Note 1.)
Gate Threshold Voltage
(Cpk ≥ 2.0) (Note 3.)
(Cpk ≥ 2.0) (Note 3.)
V
GS(th)
(V
= V , I = 250 µAdc)
2.0
–
2.9
6.7
4.0
–
DS
GS
D
Threshold Temperature Coefficient (Negative)
mV/°C
Static Drain–to–Source On–Resistance
R
V
Ohms
DS(on)
(V
GS
= 10 Vdc, I = 20 Adc)
–
0.033
0.04
D
Drain–to–Source On–Voltage
Vdc
DS(on)
(V
GS
(V
GS
= 10 Vdc, I = 40 Adc)
–
–
–
–
1.9
1.7
D
= 10 Vdc, I = 20 Adc, T = 125°C)
D
J
Forward Transconductance (V
DS
= 8.4 Vdc, I = 20 Adc)
g
17
21
–
mhos
pF
D
FS
DYNAMIC CHARACTERISTICS
Input Capacitance
C
–
–
–
2305
620
3230
1240
290
iss
(V
DS
= 25 Vdc, V
GS
f = 1.0 MHz)
= 0 Vdc,
Output Capacitance
C
oss
Transfer Capacitance
C
205
rss
SWITCHING CHARACTERISTICS (Note 2.)
Turn–On Delay Time
t
–
–
–
–
–
–
–
–
19
165
75
97
80
15
40
29
40
330
150
190
110
–
ns
d(on)
(V
= 50 Vdc, I = 40 Adc,
D
Rise Time
DD
DS
t
r
V
= 10 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
d(off)
R
= 9.1 Ω)
t
f
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
nC
(V
= 80 Vdc, I = 40 Adc,
D
V
GS
= 10 Vdc)
–
–
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
V
Vdc
ns
SD
(I = 40 Adc, V
= 0 Vdc)
–
–
0.96
0.88
1.0
–
S
GS
= 0 Vdc, T = 125°C)
(I = 40 Adc, V
S
GS
J
Reverse Recovery Time
(See Figure 14)
t
–
–
–
–
152
117
35
–
–
–
–
rr
t
a
(I = 40 Adc, V
= 0 Vdc,
S
GS
dI /dt = 100 A/µs)
t
b
S
Reverse Recovery Stored
Charge
Q
1.0
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
D
nH
–
–
3.5
4.5
–
–
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
–
7.5
–
1. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
Max limit – Typ
3 sigma
3. Reflects typical values.
Cpk + Ť
Ť
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2
MTP40N10E
TYPICAL ELECTRICAL CHARACTERISTICS
80
70
60
50
40
30
20
80
V
GS
= 10 V
T
= 25°C
J
8 V
9 V
100°C
V
DS
≥ 10 V
70
60
50
40
30
20
25°C
7 V
T
= -55°C
J
6 V
5 V
9
10
0
10
0
0
1
2
3
4
5
6
7
8
10
2
3
4
5
6
7
8
V , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
DS
V , GATE-TO-SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.07
0.06
0.05
0.04
0.03
0.02
0.050
V
GS
= 10 V
T
= 25°C
0.045
0.040
0.035
0.030
J
T
= 100°C
25°C
J
V
GS
= 10 V
15 V
0.025
0.020
-55°C
0.01
0
0.015
0.010
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1000
100
2.0
1.8
1.6
V
GS
= 0 V
T
= 125°C
100°C
V
I
= 10 V
J
GS
= 20 A
D
1.4
1.2
1.0
0.8
0.6
0.4
10
0.2
0
1.0
0
10
20
30
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
DS
40
50
60
70
80
90 100
-50 -25
0
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (°C)
J
V
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
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3
MTP40N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off–state condition when
iss
calculating t
and is read at a voltage corresponding to the
on–state when calculating t
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
GG
= the gate drive resistance
GG
R
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V /(V
In (V /V
iss GG GSP
– V )]
GSP
)
d(on)
d(off)
G
G
iss
GG GG
8000
7000
6000
5000
4000
3000
2000
V
DS
= 0 V
V
GS
= 0 V
T
= 25°C
J
C
iss
C
rss
C
iss
C
oss
1000
0
C
V
rss
-10
-5
0
5
10
15
20
25
V
GS
DS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MTP40N10E
10,000
10
9
80
72
64
56
48
40
32
24
16
V
GS
V
I
= 50 V
DD
QT
Q2
= 40 A
D
8
V
GS
= 10 V
T
= 25°C
J
7
1000
6
Q1
5
t
r
t
f
4
100
10
3
I
= 40 A
D
t
d(off)
T
= 25°C
J
2
V
DS
8
0
1
0
t
Q3
d(on)
1.0
10
R , GATE RESISTANCE (OHMS)
100
0
10
20
30
40
50
60
70
80
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
40
V
= 0 V
GS
= 25°C
35
30
25
20
15
10
T
J
5
0
0.60 0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.0
V , SOURCE-TO-DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance–General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (I
), the energy rating is specified at rated
DM
(I
) nor rated voltage (V
) is exceeded and the
continuous current (I ), in accordance with industry
DM DSS
D
transition time (t ,t ) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
exceed (T
– T )/(R
).
energy at currents below rated continuous I can safely be
assumed to equal the values indicated.
J(MAX)
C
θJC
D
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
MTP40N10E
SAFE OPERATING AREA
800
1000
100
R
LIMIT
V
= 20 V
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
GS
SINGLE PULSE
= 25°C
I
D
= 40 A
700
600
500
400
300
200
T
C
10 ms
100 ms
1.0 ms
10
10 ms
100
0
dc
1.0
100
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.1
1.0
0.1
1.0
10
1000
25
50
75
100
125
150
V
T , STARTING JUNCTION TEMPERATURE (°C)
J
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
D = 0.5
0.2
0.1
P
(pk)
R
(t) = r(t) R
0.05
0.02
θJC
θJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t
READ TIME AT t
1
1
t
T
- T = P
C
R
(t)
2
DUTY CYCLE, D = t /t
J(pk)
(pk) θJC
0.0
1 2
SINGLE PULSE
0.01
1.0E-05
1.0E-04
1.0E-03
1.0E-02
t, TIME (seconds)
1.0E-01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
MTP40N10E
PACKAGE DIMENSIONS
TO–220 THREE–LEAD
TO–220AB
CASE 221A–09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
–T–
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
S
B
F
T
4
1
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
---
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
---
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
---
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
---
2
3
U
H
G
H
J
K
L
L
R
J
N
Q
R
S
T
V
G
D
U
V
Z
N
0.080
2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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MTP40N10E
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MTP40N10E/D
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