48GA002_技术文档

PIC24FJ64GA004 Family

Data Sheet

28/44-Pin General Purpose,

16-Bit Flash Microcontrollers

 2010 Microchip Technology Inc.

DS39881D

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

32

PICtail, PIC logo, REAL ICE, rfLAB, Select Mode, Total

Endurance, TSHARC, UniWinDriver, WiperLock and ZENA

are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-022-5

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS39881D-page 2

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

28/44-Pin General Purpose, 16-Bit Flash Microcontrollers

High-Performance CPU:

• Modified Harvard Architecture

Analog Features:

• 10-Bit, up to 13-Channel Analog-to-Digital Converter:

• Up to 16 MIPS Operation @ 32 MHz

• 8 MHz Internal Oscillator with 4x PLL Option and

Multiple Divide Options

• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier

• 32-Bit by 16-Bit Hardware Divider

• 16-Bit x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set Architecture:

- 76 base instructions

- 500 ksps conversion rate

- Conversion available during Sleep and Idle

• Dual Analog Comparators with Programmable

Input/Output Configuration

Peripheral Features:

• Peripheral Pin Select:

- Allows independent I/O mapping of many peripherals

- Up to 26 available pins (44-pin devices)

- Flexible addressing modes

- Continuous hardware integrity checking and safety

interlocks prevent unintentional configuration changes

• 8-Bit Parallel Master/Slave Port (PMP/PSP):

- Up to 16-bit multiplexed addressing, with up to

11 dedicated address pins on 44-pin devices

- Programmable polarity on control lines

• Two Address Generation Units for Separate Read

and Write Addressing of Data Memory

Special Microcontroller Features:

• Operating Voltage Range of 2.0V to 3.6V

• 5.5V Tolerant Input (digital pins only)

• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins

• Flash Program Memory:

- 10,000 erase/write

- 20-year data retention minimum

• Power Management modes:

- Sleep, Idle, Doze and Alternate Clock modes

- Operating current 650 A/MIPS typical at 2.0V

- Sleep current 150 nA typical at 2.0V

• Fail-Safe Clock Monitor Operation:

- Detects clock failure and switches to on-chip,

low-power RC oscillator

• On-Chip, 2.5V Regulator with Tracking mode

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT) with On-Chip,

Low-Power RC Oscillator for Reliable Operation

• In-Circuit Serial Programming™ (ICSP™) and

In-Circuit Debug (ICD) via 2 Pins

• Hardware Real-Time Clock/Calendar (RTCC):

- Provides clock, calendar and alarm functions

• Programmable Cyclic Redundancy Check (CRC)

• Two 3-Wire/4-Wire SPI modules (support 4 Frame

modes) with 8-Level FIFO Buffer

2

• Two I C™ modules support Multi-Master/Slave

mode and 7-Bit/10-Bit Addressing

• Two UART modules:

- Supports RS-485, RS-232, and LIN 1.2

- On-chip hardware encoder/decoder for IrDA

®

- Auto-wake-up on Start bit

- Auto-Baud Detect

- 4-level deep FIFO buffer

• Five 16-Bit Timers/Counters with Programmable Prescaler

• Five 16-Bit Capture Inputs

• Five 16-Bit Compare/PWM Outputs

• Configurable Open-Drain Outputs on Digital I/O Pins

• Up to 4 External Interrupt Sources

• JTAG Boundary Scan Support

Remappable Peripherals

PIC24FJ

Device

16GA002

32GA002

48GA002

64GA002

16GA004

32GA004

48GA004

64GA004

28

44

16K

32K

48K

64K

16K

32K

48K

64K

4K

8K

4K

8K

16

26

5

2

10

13

2

Y

 2010 Microchip Technology Inc.

DS39881D-page 3

PIC24FJ64GA004 FAMILY

Pin Diagrams

28-Pin SPDIP, SSOP, SOIC

VDD

VSS

1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

MCLR

AN0/VREF+/CN2/RA0

AN1/VREF-/CN3/RA1

AN9/RP15/CN11/PMCS1/RB15

AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14

AN11/RP13/CN13/PMRD/RB13

AN12/RP12/CN14/PMD0/RB12

PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11

PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10

VCAP/VDDCORE

PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0

PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1

AN4/C1IN-/RP2/SDA2/CN6/RB2

AN5/C1IN+/RP3/SCL2/CN7/RB3

VSS

OSCI/CLKI/CN30/RA2

9

DISVREG

10

11

12

13

14

OSCO/CLKO/CN29/PMA0/RA3

SOSCI/RP4/PMBE/CN1/RB4

SOSCO/T1CK/CN0/PMA1/RA4

VDD

TDO/RP9/SDA1/CN21/PMD3/RB9

TCK/RP8/SCL1/CN22/PMD4/RB8

RP7/INT0/CN23/PMD5/RB7

PGC3/EMUC3/RP6/ASCL1/CN24/PMD6/RB6

PGD3/EMUD3/RP5/ASDA1/CN27/PMD7/RB5

(1)

28-Pin QFN

28272625242322

PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0

PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1

AN4/C1IN-/RP2/SDA2/CN6/RB2

AN5/C1IN+/RP3/SCL2/CN7/RB3

VSS

1

2

3

4

5

6

7

AN11/RP13/CN13/PMRD/RB13

AN12/RP12/CN14/PMD0/RB12

PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11

21

20

19

PIC24FJXXGA002

18 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10

VCAP/VDDCORE

16 DISVREG

17

OSCI/CLKI/CN30/RA2

OSCO/CLKO/CN29/PMA0/RA3

15 TDO/RP9/SDA1/CN21/PMD3/RB9

8

9 1011 121314

Legend:

RPn represents remappable peripheral pins.

Note 1: Back pad on QFN devices should be connected to Vss.

DS39881D-page 4

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

Pin Diagrams (Continued)

44-Pin QFN⁽¹⁾

33 SOSCI/RP4/CN1/RB4

RP9/SDA1/CN21/PMD3/RB9

1

2

3

4

5

6

7

8

TDO/PMA8/RA8

32

RP22/CN18/PMA1/RC6

RP23/CN17/PMA0/RC7

RP24/CN20/PMA5/RC8

31 OSCO/CLKO/CN29/RA3

30 OSCI/CLKI/CN30/RA2

VSS

28 VDD

29

RP25/CN19/PMA6/RC9

DISVREG

VCAP/VDDCORE

PGD2/EMUD2/RP10/CN16/PMD2/RB10

PGC2/EMUC2/RP11/CN15/PMD1/RB11

AN12/RP12/CN14/PMD0/RB12

PIC24FJXXGA004

AN8/RP18/CN10/PMA2/RC2

AN7/RP17/CN9/RC1

AN6/RP16/CN8/RC0

AN5/C1IN+/RP3/SCL2/CN7/RB3

27

26

25

24

9

10

23 AN4/C1IN-/RP2/SDA2/CN6/RB2

AN11/RP13/CN13/PMRD/RB13 11

Legend:

RPn represents remappable peripheral pins.

Note 1: Back pad on QFN devices should be connected to Vss.

 2010 Microchip Technology Inc.

DS39881D-page 5

PIC24FJ64GA004 FAMILY

Pin Diagrams (Continued)

44-Pin TQFP

33

32

31

30

29

28

27

26

25

24

23

RP9/SDA1/CN21/PMD3/RB9

SOSCI/RP4/CN1/RB4

TDO/PMA8/RA8

OSCO/CLKO/CN29/RA3

OSCI/CLKI/CN30/RA2

VSS

1

RP22/CN18/PMA1/RC6

RP23/CN17/PMA0/RC7

RP24/CN20/PMA5/RC8

2

3

4

5

6

7

8

9

RP25/CN19/PMA6/RC9

VDD

PIC24FJXXGA004

DISVREG

VCAP/VDDCORE

PGD2/EMUD2/RP10/CN16/PMD2/RB10

PGC2/EMUC2/RP11/CN15/PMD1/RB11

AN12/RP12/CN14/PMD0/RB12

AN11/RP13/CN13/PMRD/RB13

AN8/RP18/CN10/PMA2/RC2

AN7/RP17/CN9/RC1

AN6/RP16/CN8/RC0

AN5/C1IN+/RP3/SCL2/CN7/RB3

AN4/C1IN-/RP2/SDA2/CN6/RB2

10

11

Legend:

RPn represents remappable peripheral pins.

DS39881D-page 6

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19

3.0 CPU ........................................................................................................................................................................................... 25

4.0 Memory Organization................................................................................................................................................................. 31

5.0 Flash Program Memory.............................................................................................................................................................. 49

6.0 Resets ........................................................................................................................................................................................ 55

7.0 Interrupt Controller ..................................................................................................................................................................... 61

8.0 Oscillator Configuration.............................................................................................................................................................. 95

9.0 Power-Saving Features............................................................................................................................................................ 103

10.0 I/O Ports ................................................................................................................................................................................... 105

11.0 Timer1 ..................................................................................................................................................................................... 125

12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 127

13.0 Input Capture............................................................................................................................................................................ 133

14.0 Output Compare....................................................................................................................................................................... 135

15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 141

2

16.0 Inter-Integrated Circuit (I C™) ................................................................................................................................................. 151

17.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 159

18.0 Parallel Master Port (PMP)....................................................................................................................................................... 167

19.0 Real-Time Clock And Calendar (RTCC) ................................................................................................................................. 177

20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 187

21.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 191

22.0 Comparator Module.................................................................................................................................................................. 201

23.0 Comparator Voltage Reference................................................................................................................................................ 205

24.0 Special Features ...................................................................................................................................................................... 207

25.0 Development Support............................................................................................................................................................... 217

26.0 Instruction Set Summary.......................................................................................................................................................... 221

27.0 Electrical Characteristics.......................................................................................................................................................... 229

28.0 Packaging Information.............................................................................................................................................................. 247

Appendix A: Revision History............................................................................................................................................................. 259

Appendix B: Additional Guidance for PIC24FJ64GA004 Family Applications................................................................................... 260

Index ................................................................................................................................................................................................. 261

The Microchip Web Site..................................................................................................................................................................... 265

Customer Change Notification Service .............................................................................................................................................. 265

Customer Support.............................................................................................................................................................................. 265

Reader Response.............................................................................................................................................................................. 266

Product Identification System ............................................................................................................................................................ 267

 2010 Microchip Technology Inc.

DS39881D-page 7

PIC24FJ64GA004 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS39881D-page 8

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

1.1.2

POWER-SAVING TECHNOLOGY

1.0

DEVICE OVERVIEW

All of the devices in the PIC24FJ64GA004 family

incorporate a range of features that can significantly

reduce power consumption during operation. Key

items include:

This document contains device-specific information for

the following devices:

• PIC24FJ16GA002

• PIC24FJ32GA002

• PIC24FJ48GA002

• PIC24FJ64GA002

• PIC24FJ16GA004

• PIC24FJ32GA004

• PIC24FJ48GA004

• PIC24FJ64GA004

• On-the-Fly Clock Switching: The device clock

can be changed under software control to the

Timer1 source or the internal, low-power RC

oscillator during operation, allowing the user to

incorporate power-saving ideas into their software

designs.

• Doze Mode Operation: When timing-sensitive

applications, such as serial communications,

require the uninterrupted operation of peripherals,

the CPU clock speed can be selectively reduced,

allowing incremental power savings without

missing a beat.

This family introduces a new line of Microchip devices:

a 16-bit microcontroller family with a broad peripheral

feature set and enhanced computational performance.

The PIC24FJ64GA004 family offers a new migration

option for those high-performance applications which

may be outgrowing their 8-bit platforms, but don’t

require the numerical processing power of a digital

signal processor.

• Instruction-Based Power-Saving Modes: The

microcontroller can suspend all operations, or

selectively shut down its core while leaving its

peripherals active, with a single instruction in

software.

1.1

Core Features

1.1.3

OSCILLATOR OPTIONS AND

FEATURES

1.1.1

16-BIT ARCHITECTURE

Central to all PIC24F devices is the 16-bit modified

Harvard architecture, first introduced with Microchip’s

dsPIC^®digital signal controllers. The PIC24F CPU core

offers a wide range of enhancements, such as:

All of the devices in the PIC24FJ64GA004 family offer

five different oscillator options, allowing users a range

of choices in developing application hardware. These

include:

• 16-bit data and 24-bit address paths with the

ability to move information between data and

memory spaces

• Two Crystal modes using crystals or ceramic

resonators.

• Two External Clock modes offering the option of a

divide-by-2 clock output.

• Linear addressing of up to 12 Mbytes (program

space) and 64 Kbytes (data)

• A Fast Internal Oscillator (FRC) with a nominal

8 MHz output, which can also be divided under

software control to provide clock speeds as low as

31 kHz.

• A 16-element working register array with built-in

software stack support

• A 17 x 17 hardware multiplier with support for

integer math

• A Phase Lock Loop (PLL) frequency multiplier,

available to the External Oscillator modes and the

FRC oscillator, which allows clock speeds of up to

32 MHz.

• Hardware support for 32 by 16-bit division

• An instruction set that supports multiple

addressing modes and is optimized for high-level

languages such as ‘C’

• A separate internal RC oscillator (LPRC) with a

fixed 31 kHz output, which provides a low-power

option for timing-insensitive applications.

• Operational performance up to 16 MIPS

The internal oscillator block also provides a stable

reference source for the Fail-Safe Clock Monitor. This

option constantly monitors the main clock source

against a reference signal provided by the internal

oscillator and enables the controller to switch to the

internal oscillator, allowing for continued low-speed

operation or a safe application shutdown.

 2010 Microchip Technology Inc.

DS39881D-page 9

PIC24FJ64GA004 FAMILY

1.1.4

EASY MIGRATION

1.3

Details on Individual Family

Members

Regardless of the memory size, all devices share the

same rich set of peripherals, allowing for a smooth

migration path as applications grow and evolve.

Devices in the PIC24FJ64GA004 family are available

in 28-pin and 44-pin packages. The general block

diagram for all devices is shown in Figure 1-1.

The consistent pinout scheme used throughout the

entire family also aids in migrating to the next larger

device. This is true when moving between devices with

the same pin count, or even jumping from 28-pin to

44-pin devices.

The devices are differentiated from each other in two

ways:

1. Flash program memory (64 Kbytes for

PIC24FJ64GA devices, 48 Kbytes for

PIC24FJ48GA devices, 32 Kbytes for

PIC24FJ32GA devices and 16 Kbytes for

PIC24FJ16GA devices).

The PIC24F family is pin-compatible with devices in the

dsPIC33 family, and shares some compatibility with the

pinout schema for PIC18 and dsPIC30. This extends

the ability of applications to grow from the relatively

simple, to the powerful and complex, yet still selecting

a Microchip device.

2. Internal SRAM memory (4k for PIC24FJ16GA

devices, 8k for all other devices in the family).

3. Available I/O pins and ports (21 pins on 2 ports

for 28-pin devices and 35 pins on 3 ports for

44-pin devices).

1.2

Other Special Features

• Communications: The PIC24FJ64GA004 family

incorporates a range of serial communication

peripherals to handle a range of application

requirements. There are two independent I²C

modules that support both Master and Slave

modes of operation. Devices also have, through

the peripheral pin select feature, two independent

UARTs with built-in IrDA encoder/decoders and

two SPI modules.

All other features for devices in this family are identical.

These are summarized in Table 1-1.

A

list of the pin features available on the

PIC24FJ64GA004 family devices, sorted by function, is

shown in Table 1-2. Note that this table shows the pin

location of individual peripheral features and not how

they are multiplexed on the same pin. This information

is provided in the pinout diagrams in the beginning of

the data sheet. Multiplexed features are sorted by the

priority given to a feature, with the highest priority

peripheral being listed first.

• Peripheral Pin Select: The peripheral pin select

feature allows most digital peripherals to be

mapped over a fixed set of digital I/O pins. Users

may independently map the input and/or output of

any one of the many digital peripherals to any one

of the I/O pins.

• Parallel Master/Enhanced Parallel Slave Port:

One of the general purpose I/O ports can be

reconfigured for enhanced parallel data communi-

cations. In this mode, the port can be configured

for both master and slave operations, and

supports 8-bit and 16-bit data transfers with up to

16 external address lines in Master modes.

• Real-Time Clock/Calendar: This module

implements a full-featured clock and calendar with

alarm functions in hardware, freeing up timer

resources and program memory space for use of

the core application.

• 10-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sampling period, as

well as faster sampling speeds.

DS39881D-page 10

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 1-1:

DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY

Features

Operating Frequency

DC – 32 MHz

Program Memory (bytes)

Program Memory (instructions)

Data Memory (bytes)

16K

5,504

4096

32K

48K

64K

16K

5,504

4096

32K

48K

64K

11,008 16,512 22,016

8192

11,008 16,512 22,016

8192

Interrupt Sources

43

(soft vectors/NMI traps)

(39/4)

I/O Ports

Ports A, B

21

Ports A, B, C

35

Total I/O Pins

Timers:

Total Number (16-bit)

32-Bit (from paired 16-bit timers)

Input Capture Channels

Output Compare/PWM Channels

Input Change Notification Interrupt

Serial Communications:

UART

5⁽¹⁾

2

5⁽¹⁾

21

30

2⁽¹⁾

2

SPI (3-wire/4-wire)

I²C™

Parallel Communications (PMP/PSP)

JTAG Boundary Scan

Yes

10-Bit Analog-to-Digital Module

(input channels)

10

16

13

26

Analog Comparators

Remappable Pins

Resets (and delays)

2

POR, BOR, RESETInstruction, MCLR, WDT, Illegal Opcode,

REPEATInstruction, Hardware Traps, Configuration Word Mismatch

(PWRT, OST, PLL Lock)

Instruction Set

Packages

76 Base Instructions, Multiple Addressing Mode Variations

28-Pin SPDIP/SSOP/SOIC/QFN

44-Pin QFN/TQFP

Note 1: Peripherals are accessible through remappable pins.

 2010 Microchip Technology Inc.

DS39881D-page 11

PIC24FJ64GA004 FAMILY

FIGURE 1-1:

PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM

Data Bus

Interrupt

Controller

16

8

Data Latch

Data RAM

PSV & Table

Data Access

Control Block

PCH

PCL

23

Program Counter

Address

Latch

PORTA⁽¹⁾

RA0:RA9

Stack

Control

Logic

Repeat

Control

Logic

16

23

16

Read AGU

Write AGU

Address Latch

Program Memory

Data Latch

PORTB

RB0:RB15

16

EA MUX

Address Bus

24

PORTC⁽¹⁾

RC0:RC9

16

Inst Latch

Inst Register

RP⁽¹⁾

Instruction

Decode &

RP0:RP25

Control

Divide

Support

Control Signals

16 x 16

W Reg Array

17x17

Multiplier

Power-up

Timer

Timing

Generation

OSCO/CLKO

OSCI/CLKI

Oscillator

Start-up Timer

FRC/LPRC

Oscillators

16-Bit ALU

16

Power-on

Reset

Precision

Band Gap

Reference

Watchdog

Timer

DISVREG

BOR and

LVD⁽²⁾

Voltage

Regulator

VDDCORE/VCAP

VDD,VSS

MCLR

10-Bit

ADC

Timer2/3⁽³⁾

Comparators⁽³⁾

Timer4/5⁽³⁾

RTCC

Timer1

PMP/PSP

PWM/

OC1-5⁽³⁾

UART1/2⁽³⁾

IC1-5⁽³⁾

SPI1/2⁽³⁾

I2C1/2

CN1-22⁽¹⁾

Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.

2: BOR and LVD functionality is provided when the on-board voltage regulator is enabled.

3: Peripheral I/Os are accessible through remappable pins.

DS39881D-page 12

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 1-2:

PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS

Pin Number

Input

Buffer

28-Pin

SPDIP/

SSOP/SOIC

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

AN0

2

3

27

28

1

19

20

21

22

23

24

25

26

27

15

14

11

10

42

41

17

16

23

24

21

22

30

31

I

ANA

A/D Analog Inputs.

AN1

I

AN2

4

I

AN3

5

2

I

AN4

6

3

I

AN5

7

4

I

AN6

—

26

25

24

23

15

14

—

6

—

23

22

21

20

12

11

—

3

I

AN7

I

AN8

I

AN9

I

AN10

AN11

AN12

ASCL1

ASDA1

AVDD

AVSS

C1IN-

C1IN+

C2IN-

C2IN+

CLKI

CLKO

Legend:

I

2

(1)

I/O

P

I

I C

Alternate I2C1 Synchronous Serial Clock Input/Output.

Alternate I2C2 Synchronous Serial Clock Input/Output.

Positive Supply for Analog Modules.

Ground Reference for Analog Modules.

Comparator 1 Negative Input.

2

(1)

I C

—

ANA

—

7

4

I

Comparator 1 Positive Input.

4

1

I

Comparator 2 Negative Input.

5

2

I

Comparator 2 Positive Input.

9

6

I

Main Clock Input Connection.

10

7

O

System Clock Output.

TTL = TTL input buffer

ANA = Analog level input/output

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

ST = Schmitt Trigger input buffer

2

I C™ = I C/SMBus input buffer

 2010 Microchip Technology Inc.

DS39881D-page 13

PIC24FJ64GA004 FAMILY

TABLE 1-2:

PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SSOP/SOIC

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

CN0

12

11

2

9

34

33

19

20

21

22

23

24

25

26

27

15

14

11

10

9

I

ST

ANA

ST

Interrupt-on-Change Inputs.

CN1

8

I

CN2

27

28

1

I

CN3

3

I

CN4

4

I

CN5

5

2

I

CN6

6

3

I

CN7

7

4

I

CN8

—

26

25

24

23

22

21

—

18

17

16

15

—

14

—

10

9

—

23

22

21

20

19

18

—

15

14

13

12

—

11

—

7

I

CN9

I

CN10

CN11

CN12

CN13

CN14

CN15

CN16

CN17

CN18

CN19

CN20

CN21

CN22

CN23

CN24

CN25

CN26

CN27

CN28

CN29

CN30

CVREF

DISVREG

EMUC1

EMUD1

EMUC2

EMUD2

EMUC3

EMUD3

INT0

I

8

I

3

I

2

I

5

I

4

I

1

I

44

43

42

37

38

41

36

31

30

14

6

I

6

I

25

19

5

22

16

2

O

I

Comparator Voltage Reference Output.

Voltage Regulator Disable.

21

22

9

I/O

I

In-Circuit Emulator Clock Input/Output.

In-Circuit Emulator Data Input/Output.

In-Circuit Emulator Clock Input/Output.

In-Circuit Emulator Data Input/Output.

In-Circuit Emulator Clock Input/Output.

In-Circuit Emulator Data Input/Output.

External Interrupt Input.

4

1

22

21

15

14

16

1

19

18

12

11

13

26

8

42

41

43

18

MCLR

I

Master Clear (device Reset) Input. This line is brought low

to cause a Reset.

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C™ = I C/SMBus input buffer

2

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

DS39881D-page 14

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 1-2:

PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SSOP/SOIC

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

OSCI

9

6

7

30

31

22

21

9

I

ANA

ST

Main Oscillator Input Connection.

OSCO

PGC1

PGD1

PGC2

PGD2

PGC3

PGD3

PMA0

10

5

O

Main Oscillator Output Connection.

2

I/O

In-Circuit Debugger and ICSP™ Programming Clock

In-Circuit Debugger and ICSP Programming Data.

In-Circuit Debugger and ICSP Programming Clock.

In-Circuit Debugger and ICSP Programming Data.

In-Circuit Debugger and ICSP Programming Clock.

In-Circuit Debugger and ICSP Programming Data.

4

1

ST

22

21

14

15

10

19

18

12

11

7

ST

8

ST

42

41

3

ST

ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slave

modes) and Output (Master modes).

PMA1

12

9

2

I/O

ST/TTL Parallel Master Port Address Bit 1 Input (Buffered Slave

modes) and Output (Master modes).

PMA2

PMA3

PMA4

PMA5

PMA6

PMA7

PMA8

PMA9

PMA10

PMA11

PMA12

PMA13

PMBE

PMCS1

PMD0

PMD1

PMD2

PMD3

PMD4

PMD5

PMD6

PMD7

PMRD

PMWR

Legend:

—

11

26

23

22

21

18

17

16

15

14

24

25

—

8

27

38

37

4

O

—

Parallel Master Port Address (Demultiplexed Master

modes).

O

5

O

13

32

35

12

—

36

15

10

9

O

Parallel Master Port Byte Enable Strobe.

23

20

19

18

15

14

13

12

11

21

22

O

Parallel Master Port Chip Select 1 Strobe/Address Bit 14.

I/O

O

ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or

Address/Data (Multiplexed Master modes).

ST/TTL

8

ST/TTL

1

44

43

42

41

11

14

—

Parallel Master Port Read Strobe.

Parallel Master Port Write Strobe.

O

TTL = TTL input buffer

ANA = Analog level input/output

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

ST = Schmitt Trigger input buffer

2

I C™ = I C/SMBus input buffer

 2010 Microchip Technology Inc.

DS39881D-page 15

PIC24FJ64GA004 FAMILY

TABLE 1-2:

PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SSOP/SOIC

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

RA0

RA1

RA2

RA3

RA4

RA7

RA8

RA9

RA10

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

RB8

RB9

RB10

RB11

RB12

RB13

RB14

RB15

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

RC8

RC9

Legend:

2

27

28

6

19

20

30

31

34

13

32

35

12

21

22

23

24

33

41

42

43

44

1

I/O

ST

PORTA Digital I/O.

3

9

10

12

—

4

7

9

—

1

PORTB Digital I/O.

5

2

6

3

7

4

11

14

15

16

17

18

21

22

23

24

25

26

—

8

11

12

13

14

15

18

19

20

21

22

23

—

8

9

10

11

14

15

25

26

27

36

37

38

2

PORTC Digital I/O.

3

4

5

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

2

I C™ = I C/SMBus input buffer

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

DS39881D-page 16

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 1-2:

PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SSOP/SOIC

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

RP0

4

1

21

22

23

24

33

41

42

43

44

1

I/O

O

ST

—

Remappable Peripheral.

RP1

5

2

RP2

6

3

RP3

7

4

RP4

11

14

15

16

17

18

21

22

23

24

25

26

—

25

17

7

8

RP5

11

12

13

14

15

18

19

20

21

22

23

—

22

14

4

RP6

RP7

RP8

RP9

RP10

RP11

RP12

RP13

RP14

RP15

RP16

RP17

RP18

RP19

RP20

RP21

RP22

RP23

RP24

RP25

RTCC

SCL1

SCL2

SDA1

SDA2

SOSCI

SOSCO

Legend:

8

9

10

11

14

15

25

26

27

36

37

38

2

3

4

5

14

44

24

1

Real-Time Clock Alarm Output.

2

I/O

I

I C

I2C1 Synchronous Serial Clock Input/Output.

I2C2 Synchronous Serial Clock Input/Output.

I2C1 Data Input/Output.

2

I C

2

18

6

15

3

I C

2

23

33

34

I C

I2C2 Data Input/Output.

11

12

8

ANA

Secondary Oscillator/Timer1 Clock Input.

Secondary Oscillator/Timer1 Clock Output.

9

O

TTL = TTL input buffer

ANA = Analog level input/output

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

ST = Schmitt Trigger input buffer

2

I C™ = I C/SMBus input buffer

 2010 Microchip Technology Inc.

DS39881D-page 17

PIC24FJ64GA004 FAMILY

TABLE 1-2:

PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

28-Pin

SPDIP/

SSOP/SOIC

Function

I/O

Description

28-Pin

QFN

44-Pin

QFN/TQFP

T1CK

TCK

12

17

9

14

34

13

I

ST

—

Timer1 Clock.

JTAG Test Clock Input.

JTAG Test Data Input.

TDI

21

18

35

I

TDO

18

15

32

O

I

JTAG Test Data Output.

TMS

22

19

12

ST

—

JTAG Test Mode Select Input.

VDD

13, 28

20

10, 25

17

28, 40

7

P

Positive Supply for Peripheral Digital Logic and I/O Pins.

External Filter Capacitor Connection (regulator enabled).

VDDCAP

VDDCORE

—

20

17

7

—

Positive Supply for Microcontroller Core Logic (regulator

disabled).

VREF-

VREF+

VSS

3

2

28

27

20

19

I

ANA

—

A/D and Comparator Reference Voltage (low) Input.

A/D and Comparator Reference Voltage (high) Input.

Ground Reference for Logic and I/O Pins.

8, 27

5, 24

29, 39

P

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C™ = I C/SMBus input buffer

2

Note 1: Alternative multiplexing when the I2C1SEL Configuration bit is cleared.

DS39881D-page 18

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

FIGURE 2-1:

RECOMMENDED

MINIMUM CONNECTIONS

2.0

2.1

GUIDELINES FOR GETTING

STARTED WITH 16-BIT

MICROCONTROLLERS

(2)

C2

VDD

Basic Connection Requirements

Getting started with the PIC24FJ64GA004 Family of

16-bit microcontrollers requires attention to a minimal

set of device pin connections before proceeding with

development.

(1)

R1

R2

(EN/DIS)VREG

VCAP/VDDCORE

MCLR

C1

The following pins must always be connected:

C7

PIC24FXXXX

• All VDD and VSS pins

(see Section 2.2 “Power Supply Pins”)

VDD

VSS

VDD

(2)

C3

C6

• All AVDD and AVSS pins, regardless of whether or

not the analog device features are used

(see Section 2.2 “Power Supply Pins”)

• MCLR pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

(2)

C4

C5

• ENVREG/DISVREG and VCAP/VDDCORE pins

(PIC24FJ devices only)

(see Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and VCAP/VDDCORE)”)

Key (all values are recommendations):

C1 through C6: 0.1 F, 20V ceramic

These pins must also be connected if they are being

used in the end application:

C7: 10 F, 6.3V or greater, tantalum or ceramic

R1: 10 kΩ

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

R2: 100Ω to 470Ω

Note 1: See Section 2.4 “Voltage Regulator Pins

(ENVREG/DISVREG and VCAP/VDDCORE)”

for explanation of ENVREG/DISVREG pin

connections.

• OSCI and OSCO pins when an external oscillator

source is used

(see Section 2.6 “External Oscillator Pins”)

2: The example shown is for a PIC24F device

with five VDD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;

adjust the number of decoupling capacitors

appropriately.

Additionally, the following pins may be required:

• VREF+/VREF- pins used when external voltage

reference for analog modules is implemented

Note:

The AVDD and AVSS pins must always be

connected, regardless of whether any of

the analog modules are being used.

The minimum mandatory connections are shown in

Figure 2-1.

 2010 Microchip Technology Inc.

DS39881D-page 19

PIC24FJ64GA004 FAMILY

2.2

Power Supply Pins

2.3

Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions: device Reset, and device programming

and debugging. If programming and debugging are

2.2.1

DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS is required.

not required in the end application,

a

direct

connection to VDD may be all that is required. The

addition of other components, to help increase the

application’s resistance to spurious Resets from

Consider the following criteria when using decoupling

capacitors:

voltage sags, may be beneficial.

A

typical

• Value and type of capacitor: A 0.1 F (100 nF),

10-20V capacitor is recommended. The capacitor

should be a low-ESR device with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

configuration is shown in Figure 2-1. Other circuit

designs may be implemented, depending on the

application’s requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the

application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated

from the MCLR pin during programming and

debugging operations by using a jumper (Figure 2-2).

The jumper is replaced for normal run-time

operations.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type capaci-

tor in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 F to 0.001 F. Place this

second capacitor next to each primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible

(e.g., 0.1 F in parallel with 0.001 F).

Any components associated with the MCLR pin

should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2:

EXAMPLE OF MCLR PIN

CONNECTIONS

VDD

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB trace

R1

R2

MCLR

PIC24FXXXX

JP

C1

inductance.

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the

MCLR pin VIH and VIL specifications are met.

2.2.2

TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including microcontrollers to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device, and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 F to 47 F.

2: R2  470 will limit any current flowing into

MCLR from the external capacitor, C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

DS39881D-page 20

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

FIGURE 2-3:

FREQUENCY vs. ESR

PERFORMANCE FOR

SUGGESTED VCAP

2.4

Voltage Regulator Pins

(ENVREG/DISVREG and

VCAP/VDDCORE)

10

1

Note:

This section applies only to PIC24FJ

devices with an on-chip voltage regulator.

The on-chip voltage regulator enable/disable pin

(ENVREG or DISVREG, depending on the device

family) must always be connected directly to either a

supply voltage or to ground. The particular connection

is determined by whether or not the regulator is to be

used:

0.1

0.01

• For ENVREG, tie to VDD to enable the regulator,

or to ground to disable the regulator

0.001

0.01

0.1

1

10

100

1000 10,000

Frequency (MHz)

• For DISVREG, tie to ground to enable the

regulator or to VDD to disable the regulator

Note:

Data for Murata GRM21BF50J106ZE01 shown.

Measurements at 25°C, 0V DC bias.

Refer to Section 24.2 “On-Chip Voltage Regulator”

for details on connecting and using the on-chip

regulator.

2.5

ICSP Pins

When the regulator is enabled, a low-ESR (<5Ω)

capacitor is required on the VCAP/VDDCORE pin to

stabilize the voltage regulator output voltage. The

VCAP/VDDCORE pin must not be connected to VDD, and

must use a capacitor of 10 F connected to ground. The

type can be ceramic or tantalum. A suitable example is

the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or

equivalent. Designers may use Figure 2-3 to evaluate

ESR equivalence of candidate devices.

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming (ICSP) and debugging purposes.

It is recommended to keep the trace length between

the ICSP connector and the ICSP pins on the device as

short as possible. If the ICSP connector is expected to

experience an ESD event, a series resistor is recom-

mended, with the value in the range of a few tens of

ohms, not to exceed 100Ω.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin input voltage high

(VIH) and input low (VIL) requirements.

The placement of this capacitor should be close to

VCAP/VDDCORE. It is recommended that the trace

length not exceed 0.25 inch (6 mm). Refer to

Section 27.0 “Electrical Characteristics” for

additional information.

When the regulator is disabled, the VCAP/VDDCORE pin

must be tied to a voltage supply at the VDDCORE level.

Refer to Section 27.0 “Electrical Characteristics” for

information on VDD and VDDCORE.

For device emulation, ensure that the “Communication

Channel Select” (i.e., PGECx/PGEDx pins) programmed

into the device matches the physical connections for the

ICSP to the Microchip debugger/emulator tool.

For more information on available Microchip

development tools connection requirements, refer to

Section 25.0 “Development Support”.

 2010 Microchip Technology Inc.

DS39881D-page 21

PIC24FJ64GA004 FAMILY

FIGURE 2-4:

SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

2.6

External Oscillator Pins

Many microcontrollers have options for at least two

oscillators: a high-frequency primary oscillator and a

low-frequency

secondary

oscillator

(refer to

Single-Sided and In-line Layouts:

Section 8.0 “Oscillator Configuration” for details).

Copper Pour

(tied to ground)

Primary Oscillator

Crystal

The oscillator circuit should be placed on the same

side of the board as the device. Place the oscillator

circuit close to the respective oscillator pins with no

more than 0.5 inch (12 mm) between the circuit

components and the pins. The load capacitors should

be placed next to the oscillator itself, on the same side

of the board.

DEVICE PINS

Primary

OSCI

OSCO

GND

Oscillator

C1

C2

`

Use a grounded copper pour around the oscillator cir-

cuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a two-sided

board, avoid any traces on the other side of the board

where the crystal is placed.

SOSCO

SOSC I

Secondary

Oscillator

Crystal

`

Layout suggestions are shown in Figure 2-4. In-line

packages may be handled with a single-sided layout

that completely encompasses the oscillator pins. With

fine-pitch packages, it is not always possible to com-

pletely surround the pins and components. A suitable

solution is to tie the broken guard sections to a mirrored

ground layer. In all cases, the guard trace(s) must be

returned to ground.

Sec Oscillator: C2

Sec Oscillator: C1

Fine-Pitch (Dual-Sided) Layouts:

Top Layer Copper Pour

(tied to ground)

In planning the application’s routing and I/O assign-

ments, ensure that adjacent port pins and other signals

in close proximity to the oscillator are benign (i.e., free

of high frequencies, short rise and fall times and other

similar noise).

Bottom Layer

Copper Pour

(tied to ground)

OSCO

For additional information and design guidance on

oscillator circuits, please refer to these Microchip

Application Notes, available at the corporate web site

(www.microchip.com):

C2

Oscillator

Crystal

GND

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro^®Devices”

C1

• AN849, “Basic PICmicro^®Oscillator Design”

OSCI

• AN943, “Practical PICmicro^®Oscillator Analysis

and Design”

• AN949, “Making Your Oscillator Work”

DEVICE PINS

DS39881D-page 22

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

If your application needs to use certain A/D pins as

analog input pins during the debug session, the user

application must modify the appropriate bits during

initialization of the ADC module, as follows:

2.7

Configuration of Analog and

Digital Pins During ICSP

Operations

If an ICSP compliant emulator is selected as a debug-

ger, it automatically initializes all of the A/D input pins

(ANx) as “digital” pins. Depending on the particular

device, this is done by setting all bits in the ADnPCFG

register(s), or clearing all bit in the ANSx registers.

• For devices with an ADnPCFG register, clear the

bits corresponding to the pin(s) to be configured

as analog. Do not change any other bits, particu-

larly those corresponding to the PGECx/PGEDx

pair, at any time.

All PIC24F devices will have either one or more

ADnPCFG registers or several ANSx registers (one for

each port); no device will have both. Refer to

Section 21.0 “10-Bit High-Speed A/D Converter” for

more specific information.

• For devices with ANSx registers, set the bits

corresponding to the pin(s) to be configured as

analog. Do not change any other bits, particularly

those corresponding to the PGECx/PGEDx pair,

at any time.

The bits in these registers that correspond to the A/D

pins that initialized the emulator must not be changed

by the user application firmware; otherwise,

communication errors will result between the debugger

and the device.

When a Microchip debugger/emulator is used as a

programmer, the user application firmware must

correctly configure the ADnPCFG or ANSx registers.

Automatic initialization of this register is only done

during debugger operation. Failure to correctly

configure the register(s) will result in all A/D pins being

recognized as analog input pins, resulting in the port

value being read as a logic '0', which may affect user

application functionality.

2.8

Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ

to 10 kΩ resistor to VSS on unused pins and drive the

output to logic low.

 2010 Microchip Technology Inc.

DS39881D-page 23

PIC24FJ64GA004 FAMILY

NOTES:

DS39881D-page 24

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

For most instructions, the core is capable of executing

a data (or program data) memory read, a working reg-

3.0

CPU

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 2. CPU” (DS39703).

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, three parameter instructions can be supported,

allowing trinary operations (that is, A + B = C) to be

executed in a single cycle.

A high-speed, 17-bit by 17-bit multiplier has been

included to significantly enhance the core arithmetic

capability and throughput. The multiplier supports

Signed, Unsigned and Mixed mode, 16-bit by 16-bit or

8-bit by 8-bit, integer multiplication. All multiply

instructions execute in a single cycle.

The PIC24F CPU has a 16-bit (data) modified Harvard

architecture with an enhanced instruction set and a

24-bit instruction word with a variable length opcode

field. The Program Counter (PC) is 23 bits wide and

addresses up to 4M instructions of user program

memory space. A single-cycle instruction prefetch

mechanism is used to help maintain throughput and pro-

vides predictable execution. All instructions execute in a

single cycle, with the exception of instructions that

change the program flow, the double-word move

(MOV.D) instruction and the table instructions. Over-

head-free program loop constructs are supported using

the REPEAT instructions, which are interruptible at any

point.

The 16-bit ALU has been enhanced with integer divide

assist hardware that supports an iterative non-restoring

divide algorithm. It operates in conjunction with the

REPEATinstruction looping mechanism and a selection

of iterative divide instructions to support 32-bit (or

16-bit), divided by 16-bit, integer signed and unsigned

division. All divide operations require 19 cycles to

complete but are interruptible at any cycle boundary.

The PIC24F has a vectored exception scheme with up

to 8 sources of non-maskable traps and up to 118 inter-

rupt sources. Each interrupt source can be assigned to

one of seven priority levels.

PIC24F devices have sixteen, 16-bit working registers

in the programmer’s model. Each of the working

registers can act as a data, address or address offset

register. The 16th working register (W15) operates as

a Software Stack Pointer for interrupts and calls.

A block diagram of the CPU is shown in Figure 3-1.

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K word boundary defined by the 8-bit Program Space

Visibility Page Address (PSVPAG) register. The program

to data space mapping feature lets any instruction

access program space as if it were data space.

3.1

Programmer’s Model

The programmer’s model for the PIC24F is shown in

Figure 3-2. All registers in the programmer’s model are

memory mapped and can be manipulated directly by

instructions. A description of each register is provided

in Table 3-1. All registers associated with the

programmer’s model are memory mapped.

The Instruction Set Architecture (ISA) has been

significantly enhanced beyond that of the PIC18, but

maintains an acceptable level of backward compatibil-

ity. All PIC18 instructions and addressing modes are

supported, either directly, or through simple macros.

Many of the ISA enhancements have been driven by

compiler efficiency needs.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct and three groups of addressing

modes. All modes support Register Direct and various

Register Indirect modes. Each group offers up to seven

addressing modes. Instructions are associated with

predefined addressing modes depending upon their

functional requirements.

 2010 Microchip Technology Inc.

DS39881D-page 25

PIC24FJ64GA004 FAMILY

FIGURE 3-1:

PIC24F CPU CORE BLOCK DIAGRAM

PSV & Table

Data Access

Control Block

Data Bus

Interrupt

Controller

16

8

Data Latch

Data RAM

23

16

PCH

PCL

23

Program Counter

Address

Latch

Loop

Control

Logic

Stack

Control

Logic

23

16

RAGU

WAGU

Address Latch

Program Memory

Data Latch

EA MUX

16

Address Bus

ROM Latch

24

16

Instruction

Decode &

Control

Instruction Reg

Control Signals

to Various Blocks

Hardware

Multiplier

16 x 16

W Register Array

Divide

16

Support

16-Bit ALU

16

To Peripheral Modules

DS39881D-page 26

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 3-1:

CPU CORE REGISTERS

Register(s) Name

Description

W0 through W15

PC

Working Register Array

23-Bit Program Counter

SR

ALU STATUS Register

SPLIM

Stack Pointer Limit Value Register

Table Memory Page Address Register

Program Space Visibility Page Address Register

Repeat Loop Counter Register

CPU Control Register

TBLPAG

PSVPAG

RCOUNT

CORCON

FIGURE 3-2:

PROGRAMMER’S MODEL

15

0

W0 (WREG)

Divider Working Registers

Multiplier Registers

W1

W2

W3

W4

W5

W6

W7

Working/Address

Registers

W8

W9

W10

W11

W12

W13

W14

W15

Frame Pointer

Stack Pointer

0

Stack Pointer Limit

Value Register

0

SPLIM

22

0

PC

Program Counter

7

0

Table Memory Page

Address Register

TBLPAG

7

Program Space Visibility

Page Address Register

PSVPAG

15

Repeat Loop Counter

Register

RCOUNT

IPL

SRH

SRL

0

— — — — — — —

ALU STATUS Register (SR)

DC

RA N OV Z

C

2 1 0

15

0

— — — — — — — — — — — — IPL3 PSV — —

CPU Control Register (CORCON)

Registers or bits shadowed for PUSH.Sand POP.Sinstructions.

 2010 Microchip Technology Inc.

DS39881D-page 27

PIC24FJ64GA004 FAMILY

3.2

CPU Control Registers

REGISTER 3-1:

SR: ALU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DC

bit 15

bit 8

R/W-0⁽¹⁾

IPL2⁽²⁾

bit 7

R/W-0⁽¹⁾

IPL1⁽²⁾

R/W-0⁽¹⁾

IPL0⁽²⁾

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-9

bit 8

Unimplemented: Read as ‘0’

DC: ALU Half Carry/Borrow bit

1= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0= No carry-out from the 4th or 8th low-order bit of the result has occurred

bit 7-5

IPL2:IPL0: CPU Interrupt Priority Level Status bits^(1,2)

111= CPU interrupt priority level is 7 (15); user interrupts disabled.

110= CPU interrupt priority level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU interrupt priority level is 4 (12)

011= CPU interrupt priority level is 3 (11)

010= CPU interrupt priority level is 2 (10)

001= CPU interrupt priority level is 1 (9)

000= CPU interrupt priority level is 0 (8)

bit 4

bit 3

bit 2

bit 1

bit 0

RA: REPEATLoop Active bit

1= REPEATloop in progress

0= REPEATloop not in progress

N: ALU Negative bit

1= Result was negative

0= Result was non-negative (zero or positive)

OV: ALU Overflow bit

1= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation

0= No overflow has occurred

Z: ALU Zero bit

1= An operation which effects the Z bit has set it at some time in the past

0= The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)

C: ALU Carry/Borrow bit

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.

DS39881D-page 28

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 3-2:

CORCON: CPU CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽¹⁾

R/W-0

PSV

U-0

—

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-4

bit 3

Unimplemented: Read as ‘0’

IPL3: CPU Interrupt Priority Level Status bit⁽¹⁾

1= CPU interrupt priority level is greater than 7

0= CPU interrupt priority level is 7 or less

bit 2

PSV: Program Space Visibility in Data Space Enable bit

1= Program space visible in data space

0= Program space not visible in data space

bit 1-0

Unimplemented: Read as ‘0’

Note 1: User interrupts are disabled when IPL3 = 1.

The PIC24F CPU incorporates hardware support for

both multiplication and division. This includes a

dedicated hardware multiplier and support hardware

for 16-bit divisor division.

3.3

Arithmetic Logic Unit (ALU)

The PIC24F ALU is 16 bits wide and is capable of addi-

tion, subtraction, bit shifts and logic operations. Unless

otherwise mentioned, arithmetic operations are 2’s

complement in nature. Depending on the operation, the

ALU may affect the values of the Carry (C), Zero (Z),

Negative (N), Overflow (OV) and Digit Carry (DC)

Status bits in the SR register. The C and DC Status bits

operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

3.3.1

MULTIPLIER

The ALU contains a high-speed, 17-bit x 17-bit

multiplier. It supports unsigned, signed or mixed sign

operation in several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

register array, or data memory, depending on the

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

 2010 Microchip Technology Inc.

DS39881D-page 29

PIC24FJ64GA004 FAMILY

3.3.2

DIVIDER

3.3.3

MULTI-BIT SHIFT SUPPORT

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

The PIC24F ALU supports both single bit and

single-cycle, multi-bit arithmetic and logic shifts.

Multi-bit shifts are implemented using a shifter block,

capable of performing up to a 15-bit arithmetic right

shift, or up to a 15-bit left shift, in a single cycle. All

multi-bit shift instructions only support Register Direct

Addressing for both the operand source and result

destination.

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. Sixteen-bit signed and

unsigned DIV instructions can specify any W register

for both the 16-bit divisor (Wn), and any W register

(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes one cycle per bit of divisor,

so both 32-bit/16-bit and 16-bit/16-bit instructions take

the same number of cycles to execute.

A full summary of instructions that use the shift

operation is provided below in Table 3-2.

TABLE 3-2:

Instruction

INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION

Description

ASR

SL

Arithmetic shift right source register by one or more bits.

Shift left source register by one or more bits.

LSR

Logical shift right source register by one or more bits.

DS39881D-page 30

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

from either the 23-bit Program Counter (PC) during pro-

gram execution, or from table operation or data space

remapping, as described in Section 4.3 “Interfacing

Program and Data Memory Spaces”.

4.0

MEMORY ORGANIZATION

As Harvard architecture devices, PIC24F micro-

controllers feature separate program and data memory

spaces and busses. This architecture also allows the

direct access of program memory from the data space

during code execution.

User access to the program memory space is restricted

to the lower half of the address range (000000h to

7FFFFFh). The exception is the use of TBLRD/TBLWT

operations which use TBLPAG<7> to permit access to

the Configuration bits and Device ID sections of the

configuration memory space.

4.1

Program Address Space

The program address memory space of the

PIC24FJ64GA004 family devices is 4M instructions.

The space is addressable by a 24-bit value derived

Memory maps for the PIC24FJ64GA004 family of

devices are shown in Figure 4-1.

FIGURE 4-1:

PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES

PIC24FJ16GA

PIC24FJ32GA

PIC24FJ48GA

PIC24FJ64GA

000000h

000002h

000004h

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

0000FEh

000100h

000104h

0001FEh

000200h

Alternate Vector Table

User Flash

Program Memory

(5.5K instructions)

Flash Config Words

002BFEh

002C00h

User Flash

Program Memory

(11K instructions)

User Flash

Program Memory

(16K instructions)

User Flash

Program Memory

(22K instructions)

0057FEh

005800h

Flash Config Words

0083FEh

008400h

Flash Config Words

00ABFEh

00AC00h

Unimplemented

Read ‘0’

Unimplemented

Read ‘0’

7FFFFFh

800000h

Reserved

F7FFFEh

F80000h

Device Config Registers

Reserved

Device Config Registers

Reserved

Device Config Registers

Reserved

Device Config Registers

Reserved

F8000Eh

F80010h

FEFFFEh

FF0000h

DEVID (2)

FFFFFFh

Note:

Memory areas are not shown to scale.

 2010 Microchip Technology Inc.

DS39881D-page 31

PIC24FJ64GA004 FAMILY

4.1.1

PROGRAM MEMORY

ORGANIZATION

4.1.3

FLASH CONFIGURATION WORDS

In PIC24FJ64GA004 family devices, the top two words

of on-chip program memory are reserved for configura-

tion information. On device Reset, the configuration

information is copied into the appropriate Configuration

registers. The addresses of the Flash Configuration

Word for devices in the PIC24FJ64GA004 family are

shown in Table 4-1. Their location in the memory map

is shown with the other memory vectors in Figure 4-1.

The program memory space is organized in

word-addressable blocks. Although it is treated as

24 bits wide, it is more appropriate to think of each

address of the program memory as a lower and upper

word, with the upper byte of the upper word being

unimplemented. The lower word always has an even

address, while the upper word has an odd address

(Figure 4-2).

The Configuration Words in program memory are a

compact format. The actual Configuration bits are

mapped in several different registers in the configuration

memory space. Their order in the Flash Configuration

Words do not reflect a corresponding arrangement in the

configuration space. Additional details on the device

Configuration Words are provided in Section 24.1

“Configuration Bits”.

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the program memory space.

4.1.2

HARD MEMORY VECTORS

TABLE 4-1:

FLASH CONFIGURATION

WORDS FOR PIC24FJ64GA004

FAMILY DEVICES

All PIC24F devices reserve the addresses between

00000h and 000200h for hard coded program execu-

tion vectors. A hardware Reset vector is provided to

redirect code execution from the default value of the

PC on device Reset to the actual start of code. A GOTO

instruction is programmed by the user at 000000h with

the actual address for the start of code at 000002h.

Program

Memory

Configuration

Word

Device

(K words)

Addresses

002BFCh:

002BFEh

PIC24F devices also have two interrupt vector tables,

located from 000004h to 0000FFh and 000100h to

0001FFh. These vector tables allow each of the many

device interrupt sources to be handled by separate

ISRs. A more detailed discussion of the interrupt vector

tables is provided in Section 7.1 “Interrupt Vector

Table”.

PIC24FJ16GA

PIC24FJ32GA

PIC24FJ48GA

PIC24FJ64GA

5.5

11

0057FCh:

0057FEh

0083FCh:

0083FEh

16

22

00ABFCh:

00ABFEh

FIGURE 4-2:

PROGRAM MEMORY ORGANIZATION

least significant word

8

msw

Address

PC Address

(lsw Address)

most significant word

23

16

0

000000h

000002h

000004h

000006h

00000000

000001h

000003h

000005h

000007h

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

Instruction Width

DS39881D-page 32

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

PIC24FJ64GA family devices implement a total of

8 Kbytes of data memory. Should an EA point to a

location outside of this area, an all zero word or byte will

be returned.

4.2

Data Address Space

The PIC24F core has a separate, 16-bit wide data mem-

ory space, addressable as a single linear range. The

data space is accessed using two Address Generation

Units (AGUs), one each for read and write operations.

The data space memory map is shown in Figure 4-3.

4.2.1

DATA SPACE WIDTH

The data memory space is organized in

byte-addressable, 16-bit wide blocks. Data is aligned

in data memory and registers as 16-bit words, but all

data space EAs resolve to bytes. The Least Significant

Bytes of each word have even addresses, while the

Most Significant Bytes have odd addresses.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the data space.

This gives a data space address range of 64 Kbytes or

32K words. The lower half of the data memory space

(that is, when EA<15> = 0) is used for implemented

memory addresses, while the upper half (EA<15> = 1) is

reserved for the program space visibility area (see

Section 4.3.3 “Reading Data From Program Memory

Using Program Space Visibility”).

FIGURE 4-3:

DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES⁽¹⁾

MSB

Address

LSB

Address

MSB

LSB

0000h

0001h

SFR

Space

SFR Space

Data RAM

07FFh

0801h

07FEh

0800h

Near

Data Space

Implemented

Data RAM

1FFFh

2001h

1FFEh

2000h

27FEh⁽²⁾

2800h

27FFh⁽²⁾

2801h

Unimplemented

Read as ‘0’

7FFFh

8001h

7FFFh

8000h

Program Space

Visibility Area

FFFFh

FFFEh

Note 1: Data memory areas are not shown to scale.

2: Upper memory limit for PIC24FJ16GAXXX devices is 17FFh.

 2010 Microchip Technology Inc.

DS39881D-page 33

PIC24FJ64GA004 FAMILY

A sign-extend instruction (SE) is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

zero-extend (ZE) instruction on the appropriate

address.

4.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC^®devices

and improve data space memory usage efficiency, the

PIC24F instruction set supports both word and byte

operations. As a consequence of byte accessibility, all

Effective Address (EA) calculations are internally scaled

to step through word-aligned memory. For example, the

core recognizes that Post-Modified Register Indirect

Addressing mode [Ws++] will result in a value of Ws + 1

for byte operations and Ws + 2 for word operations.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions operate only on words.

4.2.3

NEAR DATA SPACE

The 8-Kbyte area between 0000h and 1FFFh is

referred to as the near data space. Locations in this

space are directly addressable via a 13-bit absolute

address field within all memory direct instructions. The

remainder of the data space is addressable indirectly.

Additionally, the whole data space is addressable using

MOV instructions, which support Memory Direct

Addressing with a 16-bit address field.

Data byte reads will read the complete word which con-

tains the byte, using the LSb of any EA to determine

which byte to select. The selected byte is placed onto

the LSB of the data path. That is, data memory and reg-

isters are organized as two parallel, byte-wide entities

with shared (word) address decode but separate write

lines. Data byte writes only write to the corresponding

side of the array or register which matches the byte

address.

4.2.4

SFR SPACE

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap will be generated. If the error occurred on a read,

the instruction underway is completed; if it occurred on

a write, the instruction will be executed but the write will

not occur. In either case, a trap is then executed, allow-

ing the system and/or user to examine the machine

state prior to execution of the address Fault.

The first 2 Kbytes of the near data space, from 0000h

to 07FFh, are primarily occupied with Special Function

Registers (SFRs). These are used by the PIC24F core

and peripheral modules for controlling the operation of

the device.

SFRs are distributed among the modules that they

control and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’. A diagram of the SFR space,

showing where SFRs are actually implemented, is

shown in Table 4-2. Each implemented area indicates

a 32-byte region where at least one address is imple-

mented as an SFR. A complete listing of implemented

SFRs, including their addresses, is shown in Tables 4-3

through 4-24.

All byte loads into any W register are loaded into the

Least Significant Byte. The Most Significant Byte is not

modified.

TABLE 4-2:

IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00

xx20

xx40

xx60

xx80

xxA0

xxC0

xxE0

000h

100h

200h

300h

400h

500h

600h

700h

Core

ICN

—

Interrupts

—

Timers

A/D

Capture

Compare

—

I²C™

UART

SPI

—

I/O

—

PMP

—

RTC/Comp

—

CRC

System

PPS

NVM/PMD

—

Legend: — = No implemented SFRs in this block

DS39881D-page 34

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

4.2.5

SOFTWARE STACK

4.3

Interfacing Program and Data

Memory Spaces

In addition to its use as a working register, the W15

register in PIC24F devices is also used as a Software

Stack Pointer. The pointer always points to the first

available free word and grows from lower to higher

addresses. It pre-decrements for stack pops and

post-increments for stack pushes, as shown in

Figure 4-4. Note that for a PC push during any CALL

instruction, the MSB of the PC is zero-extended before

the push, ensuring that the MSB is always clear.

The PIC24F architecture uses a 24-bit wide program

space and 16-bit wide data space. The architecture is

also a modified Harvard scheme, meaning that data

can also be present in the program space. To use this

data successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Aside from normal execution, the PIC24F architecture

provides two methods by which program space can be

accessed during operation:

Note:

A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

• Using table instructions to access individual bytes

or words anywhere in the program space

The Stack Pointer Limit Value register (SPLIM), associ-

ated with the Stack Pointer, sets an upper address

boundary for the stack. SPLIM is uninitialized at Reset.

As is the case for the Stack Pointer, SPLIM<0> is

forced to ‘0’ because all stack operations must be

word-aligned. Whenever an EA is generated using

W15 as a source or destination pointer, the resulting

address is compared with the value in SPLIM. If the

contents of the Stack Pointer (W15) and the SPLIM

register are equal, and a push operation is performed,

a stack error trap will not occur. The stack error trap will

occur on a subsequent push operation. Thus, for

example, if it is desirable to cause a stack error trap

when the stack grows beyond address 2000h in RAM,

initialize the SPLIM with the value, 1FFEh.

• Remapping a portion of the program space into

the data space (program space visibility)

Table instructions allow an application to read or write

to small areas of the program memory. This makes the

method ideal for accessing data tables that need to be

updated from time to time. It also allows access to all

bytes of the program word. The remapping method

allows an application to access a large block of data on

a read-only basis, which is ideal for look ups from a

large table of static data. It can only access the least

significant word of the program word.

4.3.1

ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

Similarly, a Stack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0800h. This prevents the stack from

interfering with the Special Function Register (SFR)

space.

For table operations, the 8-bit Table Memory Page

Address register (TBLPAG) is used to define a 32K word

region within the program space. This is concatenated

with a 16-bit EA to arrive at a full 24-bit program space

address. In this format, the Most Significant bit of

TBLPAG is used to determine if the operation occurs in

the user memory (TBLPAG<7> = 0) or the configuration

memory (TBLPAG<7> = 1).

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

FIGURE 4-4:

CALL STACK FRAME

0000h

15

0

For remapping operations, the 8-bit Program Space

Visibility Page Address register (PSVPAG) is used to

define a 16K word page in the program space. When

the Most Significant bit of the EA is ‘1’, PSVPAG is con-

catenated with the lower 15 bits of the EA to form a

23-bit program space address. Unlike table operations,

this limits remapping operations strictly to the user

memory area.

PC<15:0>

000000000

W15 (before CALL)

PC<22:16>

W15 (after CALL)

POP : [--W15]

PUSH: [W15++]

Table 4-25 and Figure 4-5 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> refers to a program

space word, whereas D<15:0> refers to a data space

word.

 2010 Microchip Technology Inc.

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PIC24FJ64GA004 FAMILY

TABLE 4-25: PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

Access

Space

Access Type

<23>

<22:16>

<15>

<14:1>

<0>

Instruction Access

(Code Execution)

User

0

PC<22:1>

0

0xx xxxx xxxx xxxx xxxx xxx0

TBLPAG<7:0> Data EA<15:0>

0xxx xxxx

TBLRD/TBLWT

(Byte/Word Read/Write)

xxxx xxxx xxxx xxxx

Data EA<15:0>

Configuration

TBLPAG<7:0>

1xxx xxxx

xxxx xxxx xxxx xxxx

Data EA<14:0>⁽¹⁾

Program Space Visibility User

(Block Remap/Read)

0

PSVPAG<7:0>

xxxx xxxx

xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

FIGURE 4-5:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Program Counter⁽¹⁾

Program Counter

23 Bits

0

1/0

EA

Table Operations⁽²⁾

1/0

TBLPAG

8 Bits

16 Bits

24 Bits

Select

1

0

EA

Program Space Visibility⁽¹⁾

(Remapping)

0

PSVPAG

8 Bits

15 Bits

23 Bits

Byte Select

User/Configuration

Space Select

Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of

data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted in the

configuration memory space.

DS39881D-page 46

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PIC24FJ64GA004 FAMILY

2. TBLRDH (Table Read High): In Word mode, it

4.3.2

DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

maps the entire upper word of a program address

(P<23:16>) to

a data address. Note that

D<15:8>, the ‘phantom’ byte, will always be ‘0’.

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program space without going through

data space. The TBLRDH and TBLWTH instructions are

the only method to read or write the upper 8 bits of a

program space word as data.

In Byte mode, it maps the upper or lower byte of

the program word to D<7:0> of the data

address, as above. Note that the data will

always be ‘0’ when the upper ‘phantom’ byte is

selected (byte select = 1).

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 5.0 “Flash

Program Memory”.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

word-wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word, and TBLRDHand TBLWTHaccess the space

which contains the upper data byte.

For all table operations, the area of program memory

space to be accessed is determined by the Table

Memory Page Address register (TBLPAG). TBLPAG

covers the entire program memory space of the

device, including user and configuration spaces. When

TBLPAG<7> = 0, the table page is located in the user

memory space. When TBLPAG<7> = 1, the page is

located in configuration space.

Two table instructions are provided to move byte or

word-sized (16-bit) data to and from program space.

Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space

location (P<15:0>) to a data address (D<15:0>).

Note:

Only table read operations will execute in

the configuration memory space, and only

then, in implemented areas such as the

Device ID. Table write operations are not

allowed.

In Byte mode, either the upper or lower byte of

the lower program word is mapped to the lower

byte of a data address. The upper byte is

selected when byte select is ‘1’; the lower byte

is selected when it is ‘0’.

FIGURE 4-6:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space

TBLPAG

02

Data EA<15:0>

23

15

0

000000h

23

16

8

0

00000000

020000h

030000h

‘Phantom’ Byte

TBLRDH.B(Wn<0> = 0)

TBLRDL.B(Wn<0> = 1)

TBLRDL.B(Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.

Only read operations are shown; write operations are also valid in

the user memory area.

800000h

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24-bit program word are used to contain the data. The

upper 8 bits of any program space locations used as

data should be programmed with ‘1111 1111’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

4.3.3

READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word page of the program space.

This provides transparent access of stored constant

data from the data space without the need to use

special instructions (i.e., TBLRDL/H).

Note:

PSV access is temporarily disabled during

table reads/writes.

Program space access through the data space occurs if

the Most Significant bit of the data space EA is ‘1’, and

program space visibility is enabled by setting the PSV bit

in the CPU Control register (CORCON<2>). The loca-

tion of the program memory space to be mapped into the

data space is determined by the Program Space Visibil-

ity Page Address register (PSVPAG). This 8-bit register

defines any one of 256 possible pages of 16K words in

program space. In effect, PSVPAG functions as the

upper 8 bits of the program memory address, with the

15 bits of the EA functioning as the lower bits. Note that

by incrementing the PC by 2 for each program memory

word, the lower 15 bits of data space addresses directly

map to the lower 15 bits in the corresponding program

space addresses.

For operations that use PSV and are executed outside

a REPEATloop, the MOV and MOV.Dinstructions will

require one instruction cycle in addition to the specified

execution time. All other instructions will require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV which are executed inside

a REPEAT loop, there will be some instances that

require two instruction cycles in addition to the

specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

• Execution upon re-entering the loop after an

interrupt is serviced

Data reads to this area add an additional cycle to the

instruction being executed, since two program memory

fetches are required.

Any other iteration of the REPEAT loop will allow the

instruction accessing data, using PSV, to execute in a

single cycle.

Although each data space address, 8000h and higher,

maps directly into a corresponding program memory

address (see Figure 4-7), only the lower 16 bits of the

FIGURE 4-7:

PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1and EA<15> = 1:

Program Space

Data Space

PSVPAG

02

23

15

0

000000h

0000h

Data EA<14:0>

010000h

018000h

The data in the page

designated by PSV-

PAG is mapped into

the upper half of the

data memory

8000h

space....

PSV Area

...while the lower 15

bits of the EA specify

an exact address

within the PSV area.

This corresponds

exactly to the same

lower 15 bits of the

actual program space

address.

FFFFh

800000h

DS39881D-page 48

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user

5.0

FLASH PROGRAM MEMORY

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

may write program memory data in blocks of 64 instruc-

tions (192 bytes) at a time, and erase program memory

in blocks of 512 instructions (1536 bytes) at a time.

5.1

Table Instructions and Flash

Programming

”Section

4.

Program

Memory”

(DS39715).

Regardless of the method used, all programming of

Flash memory is done with the table read and table

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed using the TBLPAG<7:0> bits and the Effective

Address (EA) from a W register specified in the table

instruction, as shown in Figure 5-1.

The PIC24FJ64GA004 family of devices contains inter-

nal Flash program memory for storing and executing

application code. The memory is readable, writable and

erasable when operating with VDD over 2.25V.

Flash memory can be programmed in three ways:

• In-Circuit Serial Programming™ (ICSP™)

• Run-Time Self-Programming (RTSP)

• Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

The TBLRDLand the TBLWTLinstructions are used to

read or write to bits<15:0> of program memory.

TBLRDLand TBLWTLcan access program memory in

both Word and Byte modes.

ICSP allows a PIC24FJ64GA004 family device to be

serially programmed while in the end application circuit.

This is simply done with two lines for the programming

clock and programming data (which are named PGCx

and PGDx, respectively), and three other lines for

power (VDD), ground (VSS) and Master Clear (MCLR).

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

The TBLRDHand TBLWTHinstructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTHcan also access program memory in Word

or Byte mode.

FIGURE 5-1:

ADDRESSING FOR TABLE REGISTERS

24 Bits

Program Counter

Using

Program

Counter

0

Working Reg EA

Using

Table

Instruction

TBLPAG Reg

8 Bits

1/0

16 Bits

User/Configuration

Space Select

Byte

Select

24-Bit EA

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5.2

RTSP Operation

5.3

Enhanced In-Circuit Serial

Programming

The PIC24F Flash program memory array is organized

into rows of 64 instructions or 192 bytes. RTSP allows

the user to erase blocks of eight rows (512 instructions)

at a time and to program one row at a time. It is also

possible to program single words.

Enhanced In-Circuit Serial Programming uses an

on-board bootloader, known as the program executive,

to manage the programming process. Using an SPI

data frame format, the program executive can erase,

program and verify program memory. For more

information on Enhanced ICSP, see the device

programming specification.

The 8-row erase blocks and single row write blocks are

edge-aligned, from the beginning of program memory, on

boundaries of 1536 bytes and 192 bytes, respectively.

When data is written to program memory using TBLWT

instructions, the data is not written directly to memory.

Instead, data written using table writes is stored in

holding latches until the programming sequence is

executed.

5.4

Control Registers

There are two SFRs used to read and write the

program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 5-1) controls which

blocks are to be erased, which memory type is to be

programmed and when the programming cycle starts.

Any number of TBLWT instructions can be executed

and a write will be successfully performed. However,

64 TBLWTinstructions are required to write the full row

of memory.

NVMKEY is a write-only register that is used for write

protection. To start a programming or erase sequence,

the user must consecutively write 55h and AAh to the

NVMKEY register. Refer to Section 5.5 “Programming

Operations” for further details.

To ensure that no data is corrupted during a write, any

unused addresses should be programmed with

FFFFFFh. This is because the holding latches reset to

an unknown state, so if the addresses are left in the

Reset state, they may overwrite the locations on rows

which were not rewritten.

5.5

Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. During a programming or erase operation, the

processor stalls (waits) until the operation is finished.

Setting the WR bit (NVMCON<15>) starts the opera-

tion and the WR bit is automatically cleared when the

operation is finished.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWTinstructions

to load the buffers. Programming is performed by

setting the control bits in the NVMCON register.

Data can be loaded in any order and the holding regis-

ters can be written to multiple times before performing

a write operation. Subsequent writes, however, will

wipe out any previous writes.

Configuration Word values are stored in the last two

locations of program memory. Performing a page erase

operation on the last page of program memory clears

these values and enables code protection. As a result,

avoid performing page erase operations on the last

page of program memory.

Note:

Writing to a location multiple times without

erasing it is not recommended.

All of the table write operations are single-word writes

(2 instruction cycles), because only the buffers are writ-

ten. A programming cycle is required for programming

each row.

DS39881D-page 50

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REGISTER 5-1:

NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0

WR

R/W-0

WREN

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

WRERR

bit 15

bit 8

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

ERASE

NVMOP3⁽¹⁾NVMOP2⁽¹⁾NVMOP1⁽¹⁾NVMOP0⁽¹⁾

bit 7

bit 0

Legend:

SO = Set Only bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

WR: Write Control bit

1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete.

0= Program or erase operation is complete and inactive

bit 14

bit 13

WREN: Write Enable bit

1= Enable Flash program/erase operations

0= Inhibit Flash program/erase operations

WRERR: Write Sequence Error Flag bit

1= An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0= The program or erase operation completed normally

bit 12-7

bit 6

Unimplemented: Read as ‘0’

ERASE: Erase/Program Enable bit

1= Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command

0= Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

NVMOP3:NVMOP0: NVM Operation Select bits⁽¹⁾

1111= Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)⁽²⁾

0011= Memory word program operation (ERASE = 0) or no operation (ERASE = 1)

0010= Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)

0001= Memory row program operation (ERASE = 0) or no operation (ERASE = 1)

Note 1: All other combinations of NVMOP3:NVMOP0 are unimplemented.

2: Available in ICSP™ mode only. Refer to device programming specification.

 2010 Microchip Technology Inc.

DS39881D-page 51

PIC24FJ64GA004 FAMILY

4. Write the first 64 instructions from data RAM into

the program memory buffers (see Example 5-1).

5.5.1

PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

5. Write the program block to Flash memory:

The user can program one row of Flash program memory

at a time. To do this, it is necessary to erase the 8-row

erase block containing the desired row. The general

process is:

a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit.

b) Write 55h to NVMKEY.

c) Write AAh to NVMKEY.

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration

of the write cycle. When the write to Flash

memory is done, the WR bit is cleared

automatically.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 5-1):

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the

ERASE (NVMCON<6>) and WREN

(NVMCON<14>) bits.

6. Repeat steps 4 and 5, using the next available

64 instructions from the block in data RAM by

incrementing the value in TBLPAG, until all

512 instructions are written back to Flash

memory.

b) Write the starting address of the block to be

erased into the TBLPAG and W registers.

c) Write 55h to NVMKEY.

d) Write AAh to NVMKEY.

For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

must wait for the programming time until programming

is complete. The two instructions following the start of

the programming sequence should be NOPs, as shown

in Example 5-3.

e) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

EXAMPLE 5-1:

ERASING A PROGRAM MEMORY BLOCK

; Set up NVMCON for block erase operation

MOV

#0x4042, W0

W0, NVMCON

;

; Initialize NVMCON

; Init pointer to row to be ERASED

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

; Initialize PM Page Boundary SFR

; Initialize in-page EA[15:0] pointer

; Set base address of erase block

; Block all interrupts with priority <7

; for next 5 instructions

TBLWTL W0, [W0]

DISI

#5

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

DS39881D-page 52

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EXAMPLE 5-2:

LOADING THE WRITE BUFFERS

; Set up NVMCON for row programming operations

MOV

#0x4001, W0

W0, NVMCON

;

; Initialize NVMCON

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV

#0x0000, W0

W0, TBLPAG

#0x6000, W0

;

; Initialize PM Page Boundary SFR

; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV

TBLWTL

#LOW_WORD_0, W2

#HIGH_BYTE_0, W3

W2, [W0]

;

; Write PM low word into program latch

; Write PM high byte into program latch

TBLWTH

W3, [W0++]

; 1st_program_word

MOV

#LOW_WORD_1, W2

#HIGH_BYTE_1, W3

W2, [W0]

;

MOV

TBLWTL

; Write PM low word into program latch

; Write PM high byte into program latch

TBLWTH

W3, [W0++]

;

2nd_program_word

MOV

TBLWTL

#LOW_WORD_2, W2

#HIGH_BYTE_2, W3

W2, [W0]

;

; Write PM low word into program latch

; Write PM high byte into program latch

TBLWTH

W3, [W0++]

•

; 63rd_program_word

MOV

#LOW_WORD_31, W2

;

MOV

TBLWTL

TBLWTH

#HIGH_BYTE_31, W3

W2, [W0]

W3, [W0]

;

; Write PM low word into program latch

; Write PM high byte into program latch

EXAMPLE 5-3:

INITIATING A PROGRAMMING SEQUENCE

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

NOP

BTSC

BRA

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; 2 NOPs required after setting WR

;

; Wait for the sequence to be completed

;

NVMCON, #15

$-2

 2010 Microchip Technology Inc.

DS39881D-page 53

PIC24FJ64GA004 FAMILY

instructions write the desired data into the write latches

and specify the lower 16 bits of the program memory

address to write to. To configure the NVMCON register

for a word write, set the NVMOP bits (NVMCON<3:0>)

to ‘0011’. The write is performed by executing the

unlock sequence and setting the WR bit (see

Example 5-4).

5.5.2

PROGRAMMING A SINGLE WORD

OF FLASH PROGRAM MEMORY

If a Flash location has been erased, it can be pro-

grammed using table write instructions to write an

instruction word (24-bit) into the write latch. The

TBLPAG register is loaded with the 8 Most Significant

Bytes of the Flash address. The TBLWTLand TBLWTH

EXAMPLE 5-4:

PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY

; Setup a pointer to data Program Memory

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

;Initialize PM Page Boundary SFR

;Initialize a register with program memory address

MOV

#LOW_WORD_N, W2

#HIGH_BYTE_N, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; Setup NVMCON for programming one word to data Program Memory

MOV

#0x4003, W0

W0, NVMCON

;

; Set NVMOP bits to 0011

DISI

MOV

BSET

NOP

#5

; Disable interrupts while the KEY sequence is written

; Write the key sequence

#0x55, W0

W0, NVMKEY

#0xAA, W0

W0, NVMKEY

NVMCON, #WR

; Start the write cycle

; 2 NOPs required after setting WR

;

DS39881D-page 54

 2010 Microchip Technology Inc.

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Any active source of Reset will make the SYSRST

signal active. Many registers associated with the CPU

6.0

RESETS

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 7. Reset” (DS39712).

and peripherals are forced to a known Reset state.

Most registers are unaffected by a Reset; their status is

unknown on POR and unchanged by all other Resets.

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 6-1). A Power-on Reset will clear all bits

except for the BOR and POR bits (RCON<1:0>) which

are set. The user may set or clear any bit at any time

during code execution. The RCON bits only serve as

status bits. Setting a particular Reset status bit in

software will not cause a device Reset to occur.

• POR: Power-on Reset

• MCLR: Pin Reset

• SWR: RESETInstruction

• WDT: Watchdog Timer Reset

• BOR: Brown-out Reset

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

A simplified block diagram of the Reset module is

shown in Figure 6-1.

FIGURE 6-1:

RESET SYSTEM BLOCK DIAGRAM

RESET

Instruction

Glitch Filter

MCLR

WDT

Module

Sleep or Idle

POR

VDD Rise

Detect

SYSRST

VDD

Brown-out

Reset

BOR

Enable Voltage Regulator

Trap Conflict

Illegal Opcode

Configuration Mismatch

Uninitialized W Register

 2010 Microchip Technology Inc.

DS39881D-page 55

PIC24FJ64GA004 FAMILY

REGISTER 6-1:

RCON: RESET CONTROL REGISTER⁽¹⁾

R/W-0

TRAPR

bit 15

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CM

R/W-0

IOPUWR

VREGS

bit 8

R/W-0

EXTR

R/W-0

SWR

R/W-0

SWDTEN⁽²⁾

R/W-0

WDTO

R/W-0

IDLE

R/W-1

BOR

R/W-1

POR

SLEEP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

TRAPR: Trap Reset Flag bit

1= A Trap Conflict Reset has occurred

0= A Trap Conflict Reset has not occurred

IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0= An illegal opcode or uninitialized W Reset has not occurred

bit 13-10

bit 9

Unimplemented: Read as ‘0’

CM: Configuration Word Mismatch Reset Flag bit

1= A Configuration Word Mismatch Reset has occurred

0= A Configuration Word Mismatch Reset has not occurred

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

VREGS: Voltage Regulator Standby Enable bit

1= Regulator remains active during Sleep

0= Regulator goes to standby during Sleep

EXTR: External Reset (MCLR) Pin bit

1= A Master Clear (pin) Reset has occurred

0= A Master Clear (pin) Reset has not occurred

SWR: Software Reset (Instruction) Flag bit

1= A RESETinstruction has been executed

0= A RESETinstruction has not been executed

SWDTEN: Software Enable/Disable of WDT bit⁽²⁾

1= WDT is enabled

0= WDT is disabled

WDTO: Watchdog Timer Time-out Flag bit

1= WDT time-out has occurred

0= WDT time-out has not occurred

SLEEP: Wake From Sleep Flag bit

1= Device has been in Sleep mode

0= Device has not been in Sleep mode

IDLE: Wake-up From Idle Flag bit

1= Device has been in Idle mode

0= Device has not been in Idle mode

BOR: Brown-out Reset Flag bit

1= A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset.

0= A Brown-out Reset has not occurred

POR: Power-on Reset Flag bit

1= A Power-up Reset has occurred

0= A Power-up Reset has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

DS39881D-page 56

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 6-1:

RESET FLAG BIT OPERATION

Setting Event

Flag Bit

Clearing Event

TRAPR (RCON<15>)

IOPUWR (RCON<14>)

CM (RCON<9>)

Trap Conflict Event

POR

Illegal Opcode or Uninitialized W Register Access

Configuration Mismatch Reset

MCLR Reset

POR

EXTR (RCON<7>)

SWR (RCON<6>)

WDTO (RCON<4>)

SLEEP (RCON<3>)

IDLE (RCON<2>)

BOR (RCON<1>)

POR (RCON<0>)

POR

RESETInstruction

POR

WDT Time-out

PWRSAVInstruction, POR

PWRSAV #SLEEPInstruction

PWRSAV #IDLEInstruction

POR, BOR

POR

—

POR

—

Note: All Reset flag bits may be set or cleared by the user software.

6.1

Clock Source Selection at Reset

6.2

Device Reset Times

If clock switching is enabled, the system clock source at

device Reset is chosen as shown in Table 6-2. If clock

switching is disabled, the system clock source is always

selected according to the oscillator Configuration bits.

Refer to Section 8.0 “Oscillator Configuration” for

further details.

The Reset times for various types of device Reset are

summarized in Table 6-3. Note that the system Reset

signal, SYSRST, is released after the POR and PWRT

delay times expire.

The time that the device actually begins to execute

code will also depend on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

TABLE 6-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the SYSRST signal is released.

Reset Type

Clock Source Determinant

POR

BOR

FNOS Configuration bits

(CW2<10:8>)

MCLR

WDTO

SWR

COSC Control bits

(OSCCON<14:12>)

 2010 Microchip Technology Inc.

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TABLE 6-3:

Reset Type

POR

RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

System Clock

Delay

FSCM

Delay

Clock Source

SYSRST Delay

Notes

1, 2, 3

EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST

—

TFSCM

—

ECPLL, FRCPLL

XT, HS, SOSC

XTPLL, HSPLL

EC, FRC, FRCDIV, LPRC

ECPLL, FRCPLL

XT, HS, SOSC

XTPLL, HSPLL

Any Clock

TPOR + TSTARTUP + TRST

TLOCK

TOST

1, 2, 3, 5, 6

1, 2, 3, 4, 6

TPOR + TSTARTUP + TRST TOST + TLOCK

1, 2, 3, 4, 5, 6

BOR

TSTARTUP + TRST

TRST

—

2, 3

TLOCK

TFSCM

—

2, 3, 5, 6

TOST

2, 3, 4, 6

TOST + TLOCK

2, 3, 4, 5, 6

MCLR

WDT

—

3

Any Clock

TRST

—

Software

Any clock

TRST

—

Illegal Opcode Any Clock

Uninitialized W Any Clock

TRST

—

TRST

—

Trap Conflict

Any Clock

TRST

—

Note 1: TPOR = Power-on Reset delay (10 s nominal).

2: TSTARTUP = TVREG (10 s nominal) if on-chip regulator is enabled or TPWRT (64 ms nominal) if on-chip

regulator is disabled.

3: TRST = Internal state Reset time.

4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the

oscillator clock to the system.

5: TLOCK = PLL lock time (2 ms nominal).

6: TFSCM = Fail-Safe Clock Monitor delay.

DS39881D-page 58

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PIC24FJ64GA004 FAMILY

6.2.1

POR AND LONG OSCILLATOR

START-UP TIMES

6.2.2.1

FSCM Delay for Crystal and PLL

Clock Sources

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) will have a relatively long

start-up time. Therefore, one or more of the following

conditions is possible after SYSRST is released:

When the system clock source is provided by a crystal

oscillator and/or the PLL, a small delay, TFSCM, will

automatically be inserted after the POR and PWRT

delay times. The FSCM will not begin to monitor the

system clock source until this delay expires. The FSCM

delay time is nominally 100 s and provides additional

time for the oscillator and/or PLL to stabilize. In most

cases, the FSCM delay will prevent an oscillator failure

trap at a device Reset when the PWRT is disabled.

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has not expired (if a

crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

6.3

Special Function Register Reset

States

The device will not begin to execute code until a valid

clock source has been released to the system. There-

fore, the oscillator and PLL start-up delays must be

considered when the Reset delay time must be known.

Most of the Special Function Registers (SFRs) associ-

ated with the PIC24F CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this manual.

6.2.2

FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

The Reset value for each SFR does not depend on the

type of Reset, with the exception of four registers. The

Reset value for the Reset Control register, RCON, will

depend on the type of device Reset. The Reset value

for the Oscillator Control register, OSCCON, will

depend on the type of Reset and the programmed

values of the FNOSC bits in the CW2 register (see

Table 6-2). The RCFGCAL and NVMCON registers are

only affected by a POR.

If the FSCM is enabled, it will begin to monitor the

system clock source when SYSRST is released. If a

valid clock source is not available at this time, the

device will automatically switch to the FRC oscillator

and the user can switch to the desired crystal oscillator

in the Trap Service Routine.

 2010 Microchip Technology Inc.

DS39881D-page 59

PIC24FJ64GA004 FAMILY

NOTES:

DS39881D-page 60

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

7.1.1

ALTERNATE INTERRUPT VECTOR

TABLE

7.0

INTERRUPT CONTROLLER

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 8. Interrupts” (DS39707).

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 7-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes will use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

The PIC24F interrupt controller reduces the numerous

peripheral interrupt request signals to a single interrupt

request signal to the PIC24F CPU. It has the following

features:

The AIVT supports emulation and debugging efforts by

providing a means to switch between an application

and a support environment without requiring the inter-

rupt vectors to be reprogrammed. This feature also

enables switching between applications for evaluation

of different software algorithms at run time. If the AIVT

is not needed, the AIVT should be programmed with

the same addresses used in the IVT.

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

7.2

Reset Sequence

• Alternate Interrupt Vector Table (AIVT) for debug

support

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24F devices clear their registers in response to

a Reset which forces the PC to zero. The micro-

controller then begins program execution at location

000000h. The user programs a GOTOinstruction at the

Reset address, which redirects program execution to

the appropriate start-up routine.

• Fixed interrupt entry and return latencies

7.1

Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 7-1.

The IVT resides in program memory, starting at location

000004h. The IVT contains 126 vectors, consisting of

8 non-maskable trap vectors, plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Note:

Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESETinstruction.

Interrupt vectors are prioritized in terms of their natural

priority; this is linked to their position in the vector table.

All other things being equal, lower addresses have a

higher natural priority. For example, the interrupt asso-

ciated with vector 0 will take priority over interrupts at

any other vector address.

PIC24FJ64GA004

family

devices

implement

non-maskable traps and unique interrupts. These are

summarized in Table 7-1 and Table 7-2.

 2010 Microchip Technology Inc.

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PIC24FJ64GA004 FAMILY

FIGURE 7-1:

PIC24F INTERRUPT VECTOR TABLE

Reset – GOTOInstruction

Reset – GOTOAddress

Reserved

000000h

000002h

000004h

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000014h

—

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00007Ch

00007Eh

000080h

(1)

Interrupt Vector Table (IVT)

—

Interrupt Vector 116

Interrupt Vector 117

Reserved

0000FCh

0000FEh

000100h

000102h

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000114h

—

(1)

Alternate Interrupt Vector Table (AIVT)

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00017Ch

00017Eh

000180h

—

Interrupt Vector 116

Interrupt Vector 117

Start of Code

0001FEh

000200h

Note 1: See Table 7-2 for the interrupt vector list.

TABLE 7-1:

TRAP VECTOR DETAILS

IVT Address

Vector Number

AIVT Address

Trap Source

0

1

2

3

4

5

6

7

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000104h

000106h

000108h

00010Ah

00010Ch

00010Eh

000110h

0001172h

Reserved

Oscillator Failure

Address Error

Stack Error

Math Error

Reserved

DS39881D-page 62

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PIC24FJ64GA004 FAMILY

TABLE 7-2:

IMPLEMENTED INTERRUPT VECTORS

Interrupt Bit Locations

Enable

Vector

Number

AIVT

Address

Interrupt Source

IVT Address

Flag

Priority

ADC1 Conversion Done

Comparator Event

CRC Generator

External Interrupt 0

External Interrupt 1

External Interrupt 2

I2C1 Master Event

I2C1 Slave Event

I2C2 Master Event

I2C2 Slave Event

Input Capture 1

Input Capture 2

Input Capture 3

Input Capture 4

Input Capture 5

Input Change Notification

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 4

Output Compare 5

Parallel Master Port

Real-Time Clock/Calendar

SPI1 Error

13

18

67

0

00002Eh

000038h

00009Ah

000014h

00003Ch

00004Eh

000036h

000034h

000078h

000076h

000016h

00001Eh

00005Eh

000060h

000062h

00003Ah

000018h

000020h

000046h

000048h

000066h

00006Eh

000090h

000026h

000028h

000054h

000056h

00001Ah

000022h

000024h

00004Ah

00004Ch

000096h

00002Ah

00002Ch

000098h

000050h

000052h

0000A4h

00012Eh

000138h

00019Ah

000114h

00013Ch

00014Eh

000136h

000034h

000178h

000176h

000116h

00011Eh

00015Eh

000160h

000162h

00013Ah

000118h

000120h

000146h

000148h

000166h

00016Eh

000190h

000126h

000128h

000154h

000156h

00011Ah

000122h

000124h

00014Ah

00014Ch

000196h

00012Ah

00012Ch

000198h

000150h

000152h

000124h

IFS0<13>

IFS1<2>

IFS4<3>

IFS0<0>

IFS1<4>

IFS1<13>

IFS1<1>

IFS1<0>

IFS3<2>

IFS3<1>

IFS0<1>

IFS0<5>

IFS2<5>

IFS2<6>

IFS2<7>

IFS1<3>

IFS0<2>

IFS0<6>

IFS1<9>

IFS1<10>

IFS2<9>

IFS2<13>

IFS3<14>

IFS0<9>

IFS0<10>

IFS2<0>

IFS2<1>

IFS0<3>

IFS0<7>

IFS0<8>

IFS1<11>

IFS1<12>

IFS4<1>

IFS0<11>

IFS0<12>

IFS4<2>

IFS1<14>

IFS1<15>

IFS4<8>

IEC0<13>

IEC1<2>

IEC4<3>

IEC0<0>

IEC1<4>

IEC1<13>

IEC1<1>

IEC1<0>

IEC3<2>

IEC3<1>

IEC0<1>

IEC0<5>

IEC2<5>

IEC2<6>

IEC2<7>

IEC1<3>

IEC0<2>

IEC0<6>

IEC1<9>

IEC1<10>

IEC2<9>

IEC2<13>

IEC3<13>

IEC0<9>

IEC0<10>

IEC0<0>

IEC2<1>

IEC0<3>

IEC0<7>

IEC0<8>

IEC1<11>

IEC1<12>

IEC4<1>

IEC0<11>

IEC0<12>

IEC4<2>

IEC1<14>

IEC1<15>

IEC4<8>

IPC3<6:4>

IPC4<10:8>

IPC16<14:12>

IPC0<2:0>

20

29

17

16

50

49

1

IPC5<2:0>

IPC7<6:4>

IPC4<6:4>

IPC4<2:0>

IPC12<10:8>

IPC12<6:4>

IPC0<6:4>

5

IPC1<6:4>

37

38

39

19

2

IPC9<6:4>

IPC9<10:8>

IPC9<14:12>

IPC4<14:12>

IPC0<10:8>

IPC1<10:8>

IPC6<6:4>

6

25

26

41

45

62

9

IPC6<10:8>

IPC10<6:4>

IPC11<6:4>

IPC15<10:8>

IPC2<6:4>

SPI1 Event

10

32

33

3

IPC2<10:8>

IPC8<2:0>

SPI2 Error

SPI2 Event

IPC8<6:4>

Timer1

IPC0<14:12>

IPC1<14:12>

IPC2<2:0>

Timer2

7

Timer3

8

Timer4

27

28

65

11

12

66

30

31

72

IPC6<14:12>

IPC7<2:0>

Timer5

UART1 Error

IPC16<6:4>

IPC2<14:12>

IPC3<2:0>

UART1 Receiver

UART1 Transmitter

UART2 Error

IPC16<10:8>

IPC7<10:8>

IPC7<14:12>

IPC17<2:0>

UART2 Receiver

UART2 Transmitter

LVD Low-Voltage Detect

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The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence that they are

listed in Table 7-2. For example, the INT0 (External

Interrupt 0) is shown as having a vector number and a

natural order priority of 0. Thus, the INT0IF status bit is

found in IFS0<0>, the INT0IE enable bit in IEC0<0>

and the INT0IP<2:0> priority bits in the first position of

IPC0 (IPC0<2:0>).

7.3

Interrupt Control and Status

Registers

The PIC24FJ64GA004 family of devices implements a

total of 28 registers for the interrupt controller:

• INTCON1

• INTCON2

• IFS0 through IFS4

Although they are not specifically part of the interrupt

control hardware, two of the CPU control registers con-

tain bits that control interrupt functionality. The ALU

STATUS register (SR) contains the IPL2:IPL0 bits

(SR<7:5>). These indicate the current CPU interrupt

priority level. The user may change the current CPU

priority level by writing to the IPL bits.

• IEC0 through IEC4

• IPC0 through IPC12, IPC15, IPC16 and IPC18

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the Inter-

rupt Nesting Disable (NSTDIS) bit, as well as the

control and status flags for the processor trap sources.

The INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

The CORCON register contains the IPL3 bit, which

together with IPL2:IPL0, also indicates the current CPU

priority level. IPL3 is a read-only bit so that trap events

cannot be masked by the user software.

The IFSx registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit which is

set by the respective peripherals, or external signal,

and is cleared via software.

All interrupt registers are described in Register 7-1

through Register 7-29, in the following pages.

The IECx registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

The IPCx registers are used to set the interrupt priority

level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

DS39881D-page 64

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REGISTER 7-1:

SR: ALU STATUS REGISTER (IN CPU)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0

DC⁽¹⁾

bit 15

bit 8

R/W-0

IPL2^(2,3)

bit 7

R/W-0

IPL1^(2,3)

R/W-0

IPL0^(2,3)

R-0

RA⁽¹⁾

R/W-0

N⁽¹⁾

R/W-0

OV⁽¹⁾

R/W-0

Z⁽¹⁾

R/W-0

C⁽¹⁾

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-5

IPL2:IPL0: CPU Interrupt Priority Level Status bits^(2,3)

111= CPU interrupt priority level is 7 (15). User interrupts disabled.

110= CPU interrupt priority level is 6 (14)

101= CPU interrupt priority level is 5 (13)

100= CPU interrupt priority level is 4 (12)

011= CPU interrupt priority level is 3 (11)

010= CPU interrupt priority level is 2 (10)

001= CPU interrupt priority level is 1 (9)

000= CPU interrupt priority level is 0 (8)

Note 1: See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control

functions.

2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.

The value in parentheses indicates the interrupt priority level if IPL3 = 1.

3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

REGISTER 7-2:

CORCON: CPU CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽²⁾

R/W-0

PSV⁽¹⁾

U-0

—

U-0

—

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 3

IPL3: CPU Interrupt Priority Level Status bit⁽²⁾

1= CPU interrupt priority level is greater than 7

0= CPU interrupt priority level is 7 or less

Note 1: See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control

functions.

2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level.

 2010 Microchip Technology Inc.

DS39881D-page 65

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REGISTER 7-3:

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 8

bit 0

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

MATHERR

ADDRERR

STKERR

OSCFAIL

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

NSTDIS: Interrupt Nesting Disable bit

1= Interrupt nesting is disabled

0= Interrupt nesting is enabled

bit 14-5

bit 4

Unimplemented: Read as ‘0’

MATHERR: Arithmetic Error Trap Status bit

1= Overflow trap has occurred

0= Overflow trap has not occurred

bit 3

bit 2

bit 1

bit 0

ADDRERR: Address Error Trap Status bit

1= Address error trap has occurred

0= Address error trap has not occurred

STKERR: Stack Error Trap Status bit

1= Stack error trap has occurred

0= Stack error trap has not occurred

OSCFAIL: Oscillator Failure Trap Status bit

1= Oscillator failure trap has occurred

0= Oscillator failure trap has not occurred

Unimplemented: Read as ‘0’

DS39881D-page 66

 2010 Microchip Technology Inc.

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REGISTER 7-4:

INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-0

ALTIVT

bit 15

R-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DISI

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

INT2EP

INT1EP

INT0EP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

ALTIVT: Enable Alternate Interrupt Vector Table bit

1= Use Alternate Interrupt Vector Table

0= Use standard (default) vector table

DISI: DISIInstruction Status bit

1= DISIinstruction is active

0= DISIinstruction is not active

bit 13-3

bit 2

Unimplemented: Read as ‘0’

INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

bit 1

bit 0

INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

 2010 Microchip Technology Inc.

DS39881D-page 67

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REGISTER 7-5:

IFS0: INTERRUPT FLAG STATUS REGISTER 0

U-0

—

U-0

—

R/W-0

AD1IF

R/W-0

SPI1IF

R/W-0

T3IF

U1TXIF

U1RXIF

SPF1IF

bit 15

bit 8

R/W-0

T2IF

R/W-0

OC2IF

R/W-0

IC2IF

U-0

—

R/W-0

T1IF

R/W-0

OC1IF

R/W-0

IC1IF

R/W-0

INT0IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

AD1IF: A/D Conversion Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12

bit 11

bit 10

bit 9

U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1RXIF: UART1 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI1IF: SPI1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPF1IF: SPI1 Fault Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

T3IF: Timer3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

T2IF: Timer2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4

bit 3

Unimplemented: Read as ‘0’

T1IF: Timer1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 2

bit 1

bit 0

OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT0IF: External Interrupt 0 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS39881D-page 68

 2010 Microchip Technology Inc.

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REGISTER 7-6:

IFS1: INTERRUPT FLAG STATUS REGISTER 1

R/W-0

U2TXIF

bit 15

R/W-0

INT2IF

R/W-0

T5IF

R/W-0

T4IF

R/W-0

OC4IF

R/W-0

OC3IF

U-0

—

U2RXIF

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

INT1IF

R/W-0

CNIF

R/W-0

CMIF

R/W-0

MI2C1IF

SI2C1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U2RXIF: UART2 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT2IF: External Interrupt 2 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T5IF: Timer5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T4IF: Timer4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IF: External Interrupt 1 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

bit 2

bit 1

bit 0

CNIF: Input Change Notification Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

CMIF: Comparator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

MI2C1IF: Master I2C1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

 2010 Microchip Technology Inc.

DS39881D-page 69

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REGISTER 7-7:

IFS2: INTERRUPT FLAG STATUS REGISTER 2

U-0

—

U-0

—

R/W-0

PMPIF

U-0

—

U-0

—

U-0

—

R/W-0

OC5IF

U-0

—

bit 15

bit 8

R/W-0

IC5IF

R/W-0

IC4IF

R/W-0

IC3IF

U-0

—

U-0

—

U-0

—

R/W-0

SPI2IF

R/W-0

SPF2IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

PMPIF: Parallel Master Port Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12-10

bit 9

Unimplemented: Read as ‘0’

OC5IF: Output Compare Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

bit 7

Unimplemented: Read as ‘0’

IC5IF: Input Capture Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

bit 5

IC4IF: Input Capture Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4-2

bit 1

Unimplemented: Read as ‘0’

SPI2IF: SPI2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 0

SPI2IF: SPI2 Fault Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS39881D-page 70

 2010 Microchip Technology Inc.

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REGISTER 7-8:

IFS3: INTERRUPT FLAG STATUS REGISTER 3

U-0

—

R/W-0

RTCIF

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

MI2C2IF

SI2C2IF

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13-3

bit 2

Unimplemented: Read as ‘0’

MI2C2IF: Master I2C2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 1

bit 0

SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39881D-page 71

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REGISTER 7-9:

IFS4: INTERRUPT FLAG STATUS REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

LVDIF

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CRCIF

R/W-0

U-0

—

U2ERIF

U1ERIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

LVDIF: Low-Voltage Detect Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7-4

bit 3

Unimplemented: Read as ‘0’

CRCIF: CRC Generator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 2

bit 1

bit 0

U2ERIF: UART2 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1ERIF: UART1 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

DS39881D-page 72

 2010 Microchip Technology Inc.

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REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

U-0

—

U-0

—

R/W-0

AD1IE

R/W-0

T3IE

U1TXIE

U1RXIE

SPI1IE

SPF1IE

bit 15

bit 8

R/W-0

T2IE

R/W-0

OC2IE

R/W-0

IC2IE

U-0

—

R/W-0

T1IE

R/W-0

OC1IE

R/W-0

IC1IE

R/W-0

INT0IE⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

AD1IE: A/D Conversion Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 12

bit 11

bit 10

bit 9

U1TXIE: UART1 Transmitter Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U1RXIE: UART1 Receiver Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPI1IE: SPI1 Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPF1IE: SPI1 Fault Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8

T3IE: Timer3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 7

T2IE: Timer2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 6

OC2IE: Output Compare Channel 2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 5

IC2IE: Input Capture Channel 2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 4

bit 3

Unimplemented: Read as ‘0’

T1IE: Timer1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 2

bit 1

bit 0

OC1IE: Output Compare Channel 1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC1IE: Input Capture Channel 1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

INT0IE: External Interrupt 0 Enable bit⁽¹⁾

1= Interrupt request enabled

0= Interrupt request not enabled

Note 1: If INTxIE = 1, this external interrupt input must be configured to an available RPn pin. See Section 10.4

”Peripheral Pin Select” for more information.

 2010 Microchip Technology Inc.

DS39881D-page 73

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REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

R/W-0

INT2IE⁽¹⁾

R/W-0

T5IE

R/W-0

T4IE

R/W-0

OC4IE

R/W-0

OC3IE

U-0

—

U2TXIE

U2RXIE

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

INT1IE⁽¹⁾

R/W-0

CNIE

R/W-0

CMIE

R/W-0

MI2C1IE

SI2C1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIE: UART2 Transmitter Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U2RXIE: UART2 Receiver Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

INT2IE: External Interrupt 2 Enable bit⁽¹⁾

1= Interrupt request enabled

0= Interrupt request not enabled

T5IE: Timer5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

T4IE: Timer4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC4IE: Output Compare Channel 4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC3IE: Output Compare Channel 3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IE: External Interrupt 1 Enable bit⁽¹⁾

1= Interrupt request enabled

0= Interrupt request not enabled

bit 3

bit 2

bit 1

bit 0

CNIE: Input Change Notification Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

CMIE: Comparator Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

MI2C1IE: Master I2C1 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SI2C1IE: Slave I2C1 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

Note 1: If INTxIE = 1, this external interrupt input must be configured to an available RPn pin. See Section 10.4

”Peripheral Pin Select” for more information.

DS39881D-page 74

 2010 Microchip Technology Inc.

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REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

OC5IE

U-0

—

PMPIE

bit 15

bit 8

R/W-0

IC5IE

R/W-0

IC4IE

R/W-0

IC3IE

U-0

—

U-0

—

U-0

—

R/W-0

SPI2IE

SPF2IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

PMPIE: Parallel Master Port Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 12-10

bit 9

Unimplemented: Read as ‘0’

OC5IE: Output Compare Channel 5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8

bit 7

Unimplemented: Read as ‘0’

IC5IE: Input Capture Channel 5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 6

bit 5

IC4IE: Input Capture Channel 4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC3IE: Input Capture Channel 3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 4-2

bit 1

Unimplemented: Read as ‘0’

SPI2IE: SPI2 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 0

SPF2IE: SPI2 Fault Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

 2010 Microchip Technology Inc.

DS39881D-page 75

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REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3

U-0

—

R/W-0

RTCIE

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

MI2C2IE

SI2C2IE

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIE: Real-Time Clock/Calendar Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 13-3

bit 2

Unimplemented: Read as ‘0’

MI2C2IE: Master I2C2 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 1

bit 0

SI2C2IE: Slave I2C2 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

Unimplemented: Read as ‘0’

DS39881D-page 76

 2010 Microchip Technology Inc.

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REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

LVDIE

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

CRCIE

U2ERIE

U1ERIE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

LVDIE: Low-Voltage Detect Interrupt Enable Status bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 7-4

bit 3

Unimplemented: Read as ‘0’

CRCIE: CRC Generator Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 2

U2ERIE: UART2 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 1

bit 0

U1ERIE: UART1 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39881D-page 77

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REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

U-0

—

R/W-1

T1IP2

R/W-0

T1IP1

R/W-0

T1IP0

U-0

—

R/W-1

R/W-0

OC1IP2

OC1IP1

OC1IP0

bit 15

bit 8

U-0

—

R/W-1

IC1IP2

R/W-0

IC1IP1

R/W-0

IC1IP0

U-0

—

R/W-1

R/W-0

INT0IP2

INT0IP1

INT0IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

T1IP2:T1IP0: Timer1 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC1IP2:OC1IP0: Output Compare Channel 1 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC1IP2:IC1IP0: Input Capture Channel 1 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

INT0IP2:INT0IP0: External Interrupt 0 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS39881D-page 78

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REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

U-0

—

R/W-1

T2IP2

R/W-0

T2IP1

R/W-0

T2IP0

U-0

—

R/W-1

R/W-0

OC2IP2

OC2IP1

OC2IP0

bit 15

bit 8

U-0

—

R/W-1

IC2IP2

R/W-0

IC2IP1

R/W-0

IC2IP0

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

T2IP2:T2IP0: Timer2 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC2IP2:OC2IP0: Output Compare Channel 2 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39881D-page 79

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REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

U1RXIP2

U1RXIP1

U1RXIP0

SPI1IP2

SPI1IP1

SPI1IP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

T3IP2

R/W-0

T3IP1

R/W-0

T3IP0

SPF1IP2

SPF1IP1

SPF1IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U1RXIP2:U1RXIP0: UART1 Receiver Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

SPI1IP2:SPI1IP0: SPI1 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SPF1IP2:SPF1IP0: SPI1 Fault Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T3IP2:T3IP0: Timer3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS39881D-page 80

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REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

AD1IP2

AD1IP1

AD1IP0

U1TXIP2

U1TXIP1

U1TXIP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

AD1IP2:AD1IP0: A/D Conversion Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

 2010 Microchip Technology Inc.

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REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

U-0

—

R/W-1

CNIP2

R/W-0

CNIP1

R/W-0

CNIP0

U-0

—

R/W-1

CMIP2

R/W-0

CMIP1

R/W-0

CMIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

MI2C1P2

MI2C1P1

MI2C1P0

SI2C1P2

SI2C1P1

SI2C1P0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CNIP2:CNIP0: Input Change Notification Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

CMIP2:CMIP0: Comparator Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

MI2C1P2:MI2C1P0: Master I2C1 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS39881D-page 82

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

INT1IP2

INT1IP1

INT1IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

INT1IP2:INT1IP0: External Interrupt 1 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

 2010 Microchip Technology Inc.

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REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6

U-0

—

R/W-1

T4IP2

R/W-0

T4IP1

R/W-0

T4IP0

U-0

—

R/W-1

R/W-0

OC4IP2

OC4IP1

OC4IP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

OC3IP2

OC3IP1

OC3IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

T4IP2:T4IP0: Timer4 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC4IP2:OC4IP0: Output Compare Channel 4 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS39881D-page 84

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

U2TXIP2

U2TXIP1

U2TXIP0

U2RXIP2

U2RXIP1

U2RXIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

T5IP2

R/W-0

T5IP1

R/W-0

T5IP0

INT2IP2

INT2IP1

INT2IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U2TXIP2:U2TXIP0: UART2 Transmitter Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2RXIP2:U2RXIP0: UART2 Receiver Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT2IP2:INT2IP0: External Interrupt 2 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T5IP2:T5IP0: Timer5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

 2010 Microchip Technology Inc.

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REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

SPI2IP2

SPI2IP1

SPI2IP0

SPF2IP2

SPF2IP1

SPF2IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

SPI2IP2:SPI2IP0: SPI2 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS39881D-page 86

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REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9

U-0

—

R/W-1

IC5IP2

R/W-0

IC5IP1

R/W-0

IC5IP0

U-0

—

R/W-1

IC4IP2

R/W-0

IC4IP1

R/W-0

IC4IP0

bit 15

bit 8

U-0

—

R/W-1

IC3IP2

R/W-0

IC3IP1

R/W-0

IC3IP0

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

IC5IP2:IC5IP0: Input Capture Channel 5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

IC4IP2:IC4IP0: Input Capture Channel 4 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39881D-page 87

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REGISTER 7-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

OC5IP2

OC5IP1

OC5IP0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

OC5IP2:OC5IP0: Output Compare Channel 5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

REGISTER 7-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

PMPIP2

PMPIP1

PMPIP0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

PMPIP2:PMPIP0: Parallel Master Port Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS39881D-page 88

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

MI2C2P2

MI2C2P1

MI2C2P0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

SI2C2P2

SI2C2P1

SI2C2P0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

MI2C2P2:MI2C2P0: Master I2C2 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39881D-page 89

PIC24FJ64GA004 FAMILY

REGISTER 7-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

RTCIP2

RTCIP1

RTCIP0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7-0

Unimplemented: Read as ‘0’

DS39881D-page 90

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 7-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

CRCIP2

CRCIP1

CRCIP0

U2ERIP2

U2ERIP1

U2ERIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U1ERIP2

U1ERIP1

U1ERIP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CRCIP2:CRCIP0: CRC Generator Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2ERIP2:U2ERIP0: UART2 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc.

DS39881D-page 91

PIC24FJ64GA004 FAMILY

REGISTER 7-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

LVDIP2

LVDIP1

LVDIP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

LVDIP2:LVDIP0: Low-Voltage Detect Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS39881D-page 92

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

7.4.3

TRAP SERVICE ROUTINE

7.4

Interrupt Setup Procedures

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

7.4.1

INITIALIZATION

To configure an interrupt source:

1. Set the NSTDIS Control bit (INTCON1<15>) if

nested interrupts are not desired.

7.4.4

INTERRUPT DISABLE

2. Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level will

depend on the specific application and type of

interrupt source. If multiple priority levels are not

desired, the IPCx register control bits for all

enabled interrupt sources may be programmed

to the same non-zero value.

All user interrupts can be disabled using the following

procedure:

1. Push the current SR value onto the software

stack using the PUSHinstruction.

2. Force the CPU to priority level 7 by inclusive

ORing the value OEh with SRL.

To enable user interrupts, the POPinstruction may be

Note: At a device Reset, the IPCx registers are

initialized, such that all user interrupt

sources are assigned to priority level 4.

used to restore the previous SR value.

Note that only user interrupts with a priority level of 7 or

less can be disabled. Trap sources (level 8-15) cannot

be disabled.

3. Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.

The DISI instruction provides a convenient way to

disable interrupts of priority levels 1-6 for a fixed period

of time. Level 7 interrupt sources are not disabled by

the DISIinstruction.

4. Enable the interrupt source by setting the

interrupt enable control bit associated with the

source in the appropriate IECx register.

7.4.2

INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address will depend on

the programming language (i.e., ‘C’ or assembler) and

the language development toolsuite that is used to

develop the application. In general, the user must clear

the interrupt flag in the appropriate IFSx register for the

source of the interrupt that the ISR handles. Otherwise,

the ISR will be re-entered immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

 2010 Microchip Technology Inc.

DS39881D-page 93

PIC24FJ64GA004 FAMILY

NOTES:

DS39881D-page 94

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

• Software-controllable switching between various

clock sources

8.0

OSCILLATOR

CONFIGURATION

• Software-controllable postscaler for selective

clocking of CPU for system power savings

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 6. Oscillator” (DS39700).

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and permits safe application recovery

or shutdown

A simplified diagram of the oscillator system is shown

in Figure 8-1.

The oscillator system for PIC24FJ64GA004 family

devices has the following features:

• A total of four external and internal oscillator options

as clock sources, providing 11 different clock modes

• On-chip 4x PLL to boost internal operating frequency

on select internal and external oscillator sources

FIGURE 8-1:

PIC24FJ64GA004 FAMILY CLOCK DIAGRAM

PIC24FJ64GA004 Family

Primary Oscillator

CLKO

XT, HS, EC

CLKDIV<14:12>

OSCO

OSCI

XTPLL, HSPLL

ECPLL,FRCPLL

CPU

4 x PLL

8 MHz

4 MHz

FRC

Oscillator

FRCDIV

Peripherals

8 MHz

(nominal)

CLKDIV<10:8>

FRC

LPRC

Oscillator

31 kHz (nominal)

Secondary Oscillator

SOSC

SOSCO

SOSCI

SOSCEN

Enable

Oscillator

Clock Control Logic

Fail-Safe

Clock

Monitor

WDT, PWRT

Clock Source Option

for Other Modules

 2010 Microchip Technology Inc.

DS39881D-page 95

PIC24FJ64GA004 FAMILY

8.1

CPU Clocking Scheme

8.2

Initial Configuration on POR

The system clock source can be provided by one of

four sources:

The oscillator source (and operating mode) that is

used at a device Power-on Reset event is selected

using Configuration bit settings. The oscillator Config-

uration bit settings are located in the Configuration

registers in the program memory (refer to

Section 24.1 “Configuration Bits” for further

details). The Primary Oscillator Configuration bits,

POSCMD1:POSCMD0 (Configuration Word 2<1:0>),

and the Initial Oscillator Select Configuration bits,

• Primary Oscillator (POSC) on the OSCI and

OSCO pins

• Secondary Oscillator (SOSC) on the SOSCI and

SOSCO pins

• Fast Internal RC (FRC) Oscillator

• Low-Power Internal RC (LPRC) Oscillator

FNOSC2:FNOSC0

(Configuration Word 2<10:8>),

The primary oscillator and FRC sources have the

option of using the internal 4x PLL. The frequency of

the FRC clock source can optionally be reduced by the

programmable clock divider. The selected clock source

generates the processor and peripheral clock sources.

select the oscillator source that is used at a Power-on

Reset. The FRC primary oscillator with postscaler

(FRCDIV) is the default (unprogrammed) selection.

The secondary oscillator, or one of the internal

oscillators, may be chosen by programming these bit

locations.

The processor clock source is divided by two to pro-

duce the internal instruction cycle clock, FCY. In this

document, the instruction cycle clock is also denoted

by FOSC/2. The internal instruction cycle clock, FOSC/2,

can be provided on the OSCO I/O pin for some

operating modes of the primary oscillator.

The Configuration bits allow users to choose between

the various clock modes, shown in Table 8-1.

8.2.1

CLOCK SWITCHING MODE

CONFIGURATION BITS

The FCKSM Configuration bits (Configuration

Word 2<7:6>) are used to jointly configure device clock

switching and the Fail-Safe Clock Monitor (FSCM).

Clock switching is enabled only when FCKSM1 is

programmed (‘0’). The FSCM is enabled only when

FCKSM1:FCKSM0 are both programmed (‘00’).

TABLE 8-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

POSCMD1:

POSCMD0

FNOSC2:

FNOSC0

Oscillator Mode

Oscillator Source

Note

1, 2

Fast RC Oscillator with Postscaler

(FRCDIV)

Internal

11

111

(Reserved)

Internal

xx

11

00

110

101

100

1

Low-Power RC Oscillator (LPRC)

Secondary (Timer1) Oscillator

(SOSC)

Secondary

Primary Oscillator (XT) with PLL

Module (XTPLL)

Primary

01

00

011

Primary Oscillator (EC) with PLL

Module (ECPLL)

Primary Oscillator (HS)

Primary Oscillator (XT)

Primary Oscillator (EC)

Primary

Internal

10

01

00

11

010

001

Fast RC Oscillator with PLL Module

(FRCPLL)

1

Fast RC Oscillator (FRC)

Internal

11

000

Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

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The Clock Divider register (Register 8-2) controls the

features associated with Doze mode, as well as the

postscaler for the FRC oscillator.

8.3

Control Registers

The operation of the oscillator is controlled by three

Special Function Registers:

The FRC Oscillator Tune register (Register 8-3) allows

the user to fine tune the FRC oscillator over a range of

approximately ±12%. Each bit increment or decrement

changes the factory calibrated frequency of the FRC

oscillator by a fixed amount.

• OSCCON

• CLKDIV

• OSCTUN

The OSCCON register (Register 8-1) is the main con-

trol register for the oscillator. It controls clock source

switching and allows the monitoring of clock sources.

REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R-0

U-0

—

R/W-x⁽¹⁾

NOSC2

R/W-x⁽¹⁾

NOSC1

R/W-x⁽¹⁾

NOSC0

COSC2

COSC1

COSC0

bit 15

bit 8

R/SO-0

R/W-0

IOLOCK⁽²⁾

R-0⁽³⁾

LOCK

U-0

—

R/CO-0

CF

U-0

—

R/W-0

CLKLOCK

bit 7

SOSCEN

OSWEN

bit 0

Legend:

CO = Clear Only bit

W = Writable bit

‘1’ = Bit is set

SO = Set Only bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC2:COSC0: Current Oscillator Selection bits

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with Postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC2:NOSC0: New Oscillator Selection bits⁽¹⁾

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with Postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In

addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.

3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

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REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)

bit 7

CLKLOCK: Clock Selection Lock Enabled bit

If FSCM is enabled (FCKSM1 = 1):

1= Clock and PLL selections are locked

0= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is disabled (FCKSM1 = 0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

bit 6

bit 5

IOLOCK: I/O Lock Enable bit⁽²⁾

1= I/O lock is active

0= I/O lock is not active

LOCK: PLL Lock Status bit⁽³⁾

1= PLL module is in lock or PLL module start-up timer is satisfied

0= PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4

bit 3

Unimplemented: Read as ‘0’

CF: Clock Fail Detect bit

1= FSCM has detected a clock failure

0= No clock failure has been detected

bit 2

bit 1

Unimplemented: Read as ‘0’

SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1= Enable secondary oscillator

0= Disable secondary oscillator

bit 0

OSWEN: Oscillator Switch Enable bit

1= Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits

0= Oscillator switch is complete

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In

addition, if the IOL1WAY Configuration bit is ‘1’ once the IOLOCK bit is set, it cannot be cleared.

3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

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REGISTER 8-2:

CLKDIV: CLOCK DIVIDER REGISTER

R/W-0

ROI

R/W-0

R/W-1

R/W-0

DOZEN⁽¹⁾

R/W-0

R/W-1

DOZE2

DOZE1

DOZE0

RCDIV2

RCDIV1

RCDIV0

bit 15

bit 8

U-0

—

U-1

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

ROI: Recover on Interrupt bit

1= Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1

0= Interrupts have no effect on the DOZEN bit

bit 14-12

DOZE2:DOZE0: CPU Peripheral Clock Ratio Select bits

111= 1:128

110= 1:64

101= 1:32

100= 1:16

011= 1:8

010= 1:4

001= 1:2

000= 1:1

bit 11

DOZEN: DOZE Enable bit⁽¹⁾

1= DOZE2:DOZE0 bits specify the CPU peripheral clock ratio

0= CPU peripheral clock ratio set to 1:1

bit 10-8

RCDIV2:RCDIV0: FRC Postscaler Select bits

111= 31.25 kHz (divide by 256)

110= 125 kHz (divide by 64)

101= 250 kHz (divide by 32)

100= 500 kHz (divide by 16)

011= 1 MHz (divide by 8)

010= 2 MHz (divide by 4)

001= 4 MHz (divide by 2)

000= 8 MHz (divide by 1)

bit 7

Unimplemented: Read as ‘0’

Unimplemented: Read as ‘1’

Unimplemented: Read as ‘0’

bit 6

bit 5-0

Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

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REGISTER 8-3:

OSCTUN: FRC Oscillator Tune Register

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

R/W-0

TUN5⁽¹⁾

R/W-0

TUN4⁽¹⁾

R/W-0

TUN3⁽¹⁾

R/W-0

TUN2⁽¹⁾

R/W-0

TUN1⁽¹⁾

R/W-0

TUN0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-0

Unimplemented: Read as ‘0’

TUN5:TUN0: FRC Oscillator Tuning bits

011111= Maximum frequency deviation

011110=



000001=

000000= Center frequency, oscillator is running at factory calibrated frequency

111111=



100001=

100000= Minimum frequency deviation

Note 1: Increments or decrements of TUN5:TUN0 may not change the FRC frequency in equal steps over the

FRC tuning range, and may not be monotonic.

8.4.1

ENABLING CLOCK SWITCHING

8.4

Clock Switching Operation

To enable clock switching, the FCKSM1 Configuration

bit in Flash Configuration Word 2 must be programmed

to ‘0’. (Refer to Section 24.1 “Configuration Bits” for

further details.) If the FCKSM1 Configuration bit is

unprogrammed (‘1’), the clock switching function and

Fail-Safe Clock Monitor function are disabled. This is

the default setting.

With few limitations, applications are free to switch

between any of the four clock sources (POSC, SOSC,

FRC and LPRC) under software control and at any

time. To limit the possible side effects that could result

from this flexibility, PIC24F devices have a safeguard

lock built into the switching process.

Note:

The primary oscillator mode has three

different submodes (XT, HS and EC)

which are determined by the POSCMDx

Configuration bits. While an application

can switch to and from primary oscillator

mode in software, it cannot switch

between the different primary submodes

without reprogramming the device.

The NOSCx control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is dis-

abled. However, the COSCx bits (OSCCON<14:12>)

will reflect the clock source selected by the FNOSCx

Configuration bits.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled. It is held at ‘0’ at all

times.

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A recommended code sequence for a clock switch

includes the following:

8.4.2

OSCILLATOR SWITCHING

SEQUENCE

1. Disable interrupts during the OSCCON register

unlock and write sequence.

At a minimum, performing a clock switch requires this

basic sequence:

2. Execute the unlock sequence for the OSCCON

high byte by writing 78h and 9Ah to

1. If

desired,

read

the

COSCx

bits

(OSCCON<14:12>), to determine the current

oscillator source.

OSCCON<15:8>

instructions.

in

two

back-to-back

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write new oscillator source to the NOSCx bits in

the instruction immediately following the unlock

sequence.

3. Write the appropriate value to the NOSCx bits

(OSCCON<10:8>) for the new oscillator source.

4. Execute the unlock sequence for the OSCCON

low byte by writing 46h and 57h to

OSCCON<7:0> in two back-to-back instructions.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

5. Set the OSWEN bit in the instruction immediately

following the unlock sequence.

Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

6. Continue to execute code that is not clock

sensitive (optional).

1. The clock switching hardware compares the

COSCx bits with the new value of the NOSCx

bits. If they are the same, then the clock switch

is a redundant operation. In this case, the

OSWEN bit is cleared automatically and the

clock switch is aborted.

7. Invoke an appropriate amount of software delay

(cycle counting) to allow the selected oscillator

and/or PLL to start and stabilize.

8. Check to see if OSWEN is ‘0’. If it is, the switch

was successful. If OSWEN is still set, then

check the LOCK bit to determine the cause of

failure.

2. If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and CF (OSCCON<3>)

bits are cleared.

The core sequence for unlocking the OSCCON register

and initiating a clock switch is shown in Example 8-1.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware will wait until

the OST expires. If the new source is using the

PLL, then the hardware waits until a PLL lock is

detected (LOCK = 1).

EXAMPLE 8-1:

BASIC CODE SEQUENCE

FOR CLOCK SWITCHING

;Place the new oscillator selection in W0

;OSCCONH (high byte) Unlock Sequence

MOV

MOV.b

#OSCCONH, w1

#0x78, w2

#0x9A, w3

w2, [w1]

4. The hardware waits for 10 clock cycles from the

new clock source and then performs the clock

switch.

w3, [w1]

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the

NOSCx bit values are transferred to the COSCx

bits.

;Set new oscillator selection

MOV.b WREG, OSCCONH

;OSCCONL (low byte) unlock sequence

MOV

MOV.b

#OSCCONL, w1

#0x46, w2

#0x57, w3

w2, [w1]

6. The old clock source is turned off at this time,

with the exception of LPRC (if WDT or FSCM

are enabled) or SOSC (if SOSCEN remains

set).

w3, [w1]

;Start oscillator switch operation

BSET OSCCON,#0

Note 1: The processor will continue to execute

code throughout the clock switching

sequence. Timing sensitive code should

not be executed during this time.

2: Direct clock switches between any

primary oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either direc-

tion. In these instances, the application

must switch to FRC mode as a transition

clock source between the two PLL

modes.

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8.4.3

SECONDARY OSCILLATOR

LOW-POWER OPERATION

8.4.4

OSCILLATOR LAYOUT

On low pin count devices, such as those in the

PIC24FJ64GA004 family, due to pinout limitations, the

SOSC is more susceptible to noise than other PIC24F

devices. Unless proper care is taken in the design and

layout of the SOSC circuit, it is possible for

inaccuracies to be introduced into the oscillator's

period.

Note:

This feature is implemented only on

PIC24FJ64GA004 family devices with a

major silicon revision level of B or later

(DEVREV register value is 3042h or

greater).

The Secondary Oscillator (SOSC) can operate in two

distinct levels of power consumption based on device

configuration. In Low-Power mode, the oscillator

operates in a low-gain, low-power state. By default, the

oscillator uses a higher gain setting, and therefore,

requires more power. The Secondary Oscillator Mode

Selection bits, SOSCSEL<1:0> (CW2<12:11>),

determine the oscillator’s power mode.

In general, the crystal circuit connections should be as

short as possible. It is also good practice to surround

the crystal circuit with a ground loop or ground plane.

For more detailed information on crystal circuit design,

please refer to the “PIC24F Family Reference Manual”,

Section 6. “Oscillator” (DS39700) and Microchip

Application Notes: AN826, “Crystal Oscillator Basics

and Crystal Selection for rfPIC^®and PICmicro^®

Devices” (DS00826) and AN849, “Basic PICmicro^®

Oscillator Design” (DS00849).

When Low-Power mode is used, care must be taken in

the design and layout of the SOSC circuit to ensure that

the oscillator will start up and oscillate properly. The

lower gain of this mode makes the SOSC more

sensitive to noise and requires a longer start-up time.

DS39881D-page 102

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and code execution, but allows peripheral modules to

continue operation. The assembly syntax of the

9.0

POWER-SAVING FEATURES

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 10. Power-Saving Features”

(DS39698). Additional power-saving tips

can also be found in Appendix B: “Addi-

tional Guidance for PIC24FJ64GA004

Family Applications” of this document.

PWRSAVinstruction is shown in Example 9-1.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset.

When the device exits these modes, it is said to

“wake-up”.

Note: SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include

file for the selected device.

9.2.1

SLEEP MODE

The PIC24FJ64GA004 family of devices provides the

ability to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in the

number of circuits being clocked constitutes lower

consumed power. All PIC24F devices manage power

consumption in four different ways:

Sleep mode has these features:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption will be reduced

to a minimum provided that no I/O pin is sourcing

current.

• Clock frequency

• The Fail-Safe Clock Monitor does not operate

during Sleep mode since the system clock source

is disabled.

• Instruction-based Sleep and Idle modes

• Software controlled Doze mode

• Selective peripheral control in software

• The LPRC clock will continue to run in Sleep

mode if the WDT is enabled.

Combinations of these methods can be used to selec-

tively tailor an application’s power consumption, while

still maintaining critical application features, such as

timing-sensitive communications.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

• Some device features or peripherals may

continue to operate in Sleep mode. This includes

items such as the input change notification on the

I/O ports, or peripherals that use an external clock

input. Any peripheral that requires the system

clock source for its operation will be disabled in

Sleep mode.

9.1

Clock Frequency and Clock

Switching

PIC24F devices allow for a wide range of clock

frequencies to be selected under application control. If

the system clock configuration is not locked, users can

choose low-power or high-precision oscillators by simply

changing the NOSC bits. The process of changing a sys-

tem clock during operation, as well as limitations to the

process, are discussed in more detail in Section 8.0

“Oscillator Configuration”.

The device will wake-up from Sleep mode on any of the

these events:

• On any interrupt source that is individually

enabled

• On any form of device Reset

• On a WDT time-out

On wake-up from Sleep, the processor will restart with

the same clock source that was active when Sleep

mode was entered.

9.2

Instruction-Based Power-Saving

Modes

PIC24F devices have two special power-saving modes

that are entered through the execution of a special

PWRSAVinstruction. Sleep mode stops clock operation

and halts all code execution; Idle mode halts the CPU

EXAMPLE 9-1:

PWRSAV INSTRUCTION SYNTAX

PWRSAV

#SLEEP_MODE

#IDLE_MODE

; Put the device into SLEEP mode

; Put the device into IDLE mode

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It is also possible to use Doze mode to selectively

reduce power consumption in event driven applica-

tions. This allows clock sensitive functions, such as

synchronous communications, to continue without

interruption while the CPU Idles, waiting for something

to invoke an interrupt routine. Enabling the automatic

return to full-speed CPU operation on interrupts is

enabled by setting the ROI bit (CLKDIV<15>). By

default, interrupt events have no effect on Doze mode

operation.

9.2.2

IDLE MODE

Idle mode has these features:

• The CPU will stop executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 9.4

“Selective Peripheral Module Control”).

• If the WDT or FSCM is enabled, the LPRC will

also remain active.

9.4

Selective Peripheral Module

Control

The device will wake from Idle mode on any of these

events:

Idle and Doze modes allow users to substantially

reduce power consumption by slowing or stopping the

CPU clock. Even so, peripheral modules still remain

clocked and thus consume power. There may be cases

where the application needs what these modes do not

provide: the allocation of power resources to CPU

processing with minimal power consumption from the

peripherals.

• Any interrupt that is individually enabled.

• Any device Reset.

• A WDT time-out.

On wake-up from Idle, the clock is reapplied to the CPU

and instruction execution begins immediately, starting

with the instruction following the PWRSAVinstruction or

the first instruction in the ISR.

PIC24F devices address this requirement by allowing

peripheral modules to be selectively disabled, reducing

or eliminating their power consumption. This can be

done with two control bits:

9.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAVinstruction will be held off until entry into Sleep

or Idle mode has completed. The device will then

wake-up from Sleep or Idle mode.

• The Peripheral Enable bit, generically named,

“XXXEN”, located in the module’s main control

SFR.

• The Peripheral Module Disable (PMD) bit,

generically named, “XXXMD”, located in one of

the PMD control registers.

9.3

Doze Mode

Generally, changing clock speed and invoking one of

the power-saving modes are the preferred strategies

for reducing power consumption. There may be cir-

cumstances, however, where this is not practical. For

example, it may be necessary for an application to

maintain uninterrupted synchronous communication,

even while it is doing nothing else. Reducing system

clock speed may introduce communication errors,

Both bits have similar functions in enabling or disabling

its associated module. Setting the PMD bit for a module

disables all clock sources to that module, reducing its

power consumption to an absolute minimum. In this

state, the control and status registers associated with

the peripheral will also be disabled, so writes to those

registers will have no effect and read values will be

invalid. Many peripheral modules have a corresponding

PMD bit.

while using

a

power-saving mode may stop

communications completely.

In contrast, disabling a module by clearing its XXXEN

bit disables its functionality, but leaves its registers

available to be read and written to. Power consumption

is reduced, but not by as much as the PMD bit does.

Most peripheral modules have an enable bit;

exceptions include capture, compare and RTCC.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock contin-

ues to operate from the same source and at the same

speed. Peripheral modules continue to be clocked at

the same speed while the CPU clock speed is reduced.

Synchronization between the two clock domains is

maintained, allowing the peripherals to access the

SFRs while the CPU executes code at a slower rate.

To achieve more selective power savings, peripheral

modules can also be selectively disabled when the

device enters Idle mode. This is done through the

control bit of the generic name format, “XXXIDL”. By

default, all modules that can operate during Idle mode

will do so. Using the disable on Idle feature allows fur-

ther reduction of power consumption during Idle mode,

enhancing power savings for extremely critical power

applications.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE2:DOZE0 bits

(CLKDIV<14:12>). There are eight possible

configurations, from 1:1 to 1:256, with 1:1 being the

default.

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When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

10.0 I/O PORTS

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 12. I/O Ports with Peripheral

Pin Select (PPS)” (DS39711).

All port pins have three registers directly associated

with their operation as digital I/O. The Data Direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the Output Latch register (LATx),

read the latch. Writes to the latch, write the latch.

Reads from the port (PORTx), read the port pins, while

writes to the port pins, write the latch.

All of the device pins (except VDD, VSS, MCLR and

OSCI/CLKI) are shared between the peripherals and

the parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

10.1 Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The periph-

eral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 10-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers and the port pin will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is, nevertheless,

regarded as a dedicated port because there is no

other competing source of outputs.

FIGURE 10-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

I/O

1

0

Output Enable

Output Data

1

0

PIO Module

Read TRIS

Data Bus

WR TRIS

D

Q

I/O Pin

CK

TRIS Latch

D

Q

WR LAT +

WR PORT

CK

Data Latch

Read LAT

Input Data

Read PORT

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10.1.1

OPEN-DRAIN CONFIGURATION

TABLE 10-1: INPUT VOLTAGE LEVELS

Tolerated

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can also be individually con-

figured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits con-

figures the corresponding pin to act as an open-drain

output.

Port or Pin

Description

Input

PORTA<4:0>

VDD

Only VDD input levels

tolerated.

PORTB<15:12>

PORTB<4:0>

PORTC<2:0>⁽¹⁾

PORTA<10:7>⁽¹⁾

PORTB<11:5>

PORTC<9:3>⁽¹⁾

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired

digital only pins by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

5.5V

Tolerates input levels

above VDD, useful for

most standard logic.

Note 1: Unavailable on 28-pin devices.

10.2 Configuring Analog Port Pins

10.3 Input Change Notification

The use of the AD1PCFG and TRIS registers control

the operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) will be

converted.

The input change notification function of the I/O ports

allows the PIC24FJ64GA004 family of devices to gen-

erate interrupt requests to the processor in response to

a change of state on selected input pins. This feature is

capable of detecting input change of states even in

Sleep mode, when the clocks are disabled. Depending

on the device pin count, there are up to 22 external sig-

nals that may be selected (enabled) for generating an

interrupt request on a change of state.

When reading the PORT register, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

There are four control registers associated with the CN

module. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

10.2.1

I/O PORT WRITE/READ TIMING

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source that is connected

to the pin, and eliminate the need for external resistors

when push button or keypad devices are connected.

The pull-ups are enabled separately using the CNPU1

and CNPU2 registers, which contain the control bits for

each of the CN pins. Setting any of the control bits

enables the weak pull-ups for the corresponding pins.

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP.

10.2.2

ANALOG INPUT PINS AND

VOLTAGE CONSIDERATIONS

The voltage tolerance of pins used as device inputs is

dependent on the pin’s input function. Pins that are used

as digital only inputs are able to handle DC voltages up

to 5.5V, a level typical for digital logic circuits. In contrast,

pins that also have analog input functions of any kind

can only tolerate voltages up to VDD. Voltage excursions

beyond VDD on these pins are always to be avoided.

Table 10-1 summarizes the input capabilities. Refer to

Section 27.1 “DC Characteristics” for more details.

When the internal pull-up is selected, the pin pulls up to

VDD – 0.7V (typical). Make sure that there is no external

pull-up source when the internal pull-ups are enabled,

as the voltage difference can cause a current path.

Note:

Pull-ups on change notification pins

should always be disabled whenever the

port pin is configured as a digital output.

EXAMPLE 10-1:

PORT WRITE/READ EXAMPLE

MOV

NOP

0xFF00, W0

W0, TRISBB

; Configure PORTB<15:8> as inputs

; and PORTB<7:0> as outputs

; Delay 1 cycle

BTSS PORTB, #13

; Next Instruction

DS39881D-page 106

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A key difference between pin select and non pin select

peripherals is that pin select peripherals are not asso-

10.4 Peripheral Pin Select

A major challenge in general purpose devices is provid-

ing the largest possible set of peripheral features while

minimizing the conflict of features on I/O pins. The chal-

lenge is even greater on low pin count devices similar

to the PIC24FJ64GA family. In an application that

needs to use more than one peripheral multiplexed on

single pin, inconvenient workarounds in application

code or a complete redesign may be the only option.

ciated with a default I/O pin. The peripheral must

always be assigned to a specific I/O pin before it can be

used. In contrast, non pin select peripherals are always

available on a default pin, assuming that the peripheral

is active and not conflicting with another peripheral.

10.4.2.1

Peripheral Pin Select Function

Priority

The peripheral pin select feature provides an alterna-

tive to these choices by enabling the user’s peripheral

set selection and their placement on a wide range of

I/O pins. By increasing the pinout options available on

When a pin selectable peripheral is active on a given

I/O pin, it takes priority over all other digital I/O and dig-

ital communication peripherals associated with the pin.

Priority is given regardless of the type of peripheral that

is mapped. Pin select peripherals never take priority

over any analog functions associated with the pin.

a

particular device, users can better tailor the

microcontroller to their entire application, rather than

trimming the application to fit the device.

10.4.3

CONTROLLING PERIPHERAL PIN

SELECT

The peripheral pin select feature operates over a fixed

subset of digital I/O pins. Users may independently

map the input and/or output of any one of many digital

peripherals to any one of these I/O pins. Peripheral pin

select is performed in software and generally does not

require the device to be reprogrammed. Hardware

safeguards are included that prevent accidental or

spurious changes to the peripheral mapping once it has

been established.

Peripheral pin select features are controlled through

two sets of Special Function Registers: one to map

peripheral inputs, and one to map outputs. Because

they are separately controlled, a particular peripheral’s

input and output (if the peripheral has both) can be

placed on any selectable function pin without

constraint.

The association of a peripheral to a peripheral select-

able pin is handled in two different ways, depending on

if an input or an output is being mapped.

10.4.1

AVAILABLE PINS

The peripheral pin select feature is used with a range

of up to 26 pins; the number of available pins is depen-

dent on the particular device and its pincount. Pins that

support the peripheral pin select feature include the

designation “RPn” in their full pin designation, where

“RP” designates a remappable peripheral and “n” is the

remappable pin number. See Table 1-2 for pinout

options in Each Package Offering.

10.4.3.1

Input Mapping

The inputs of the peripheral pin select options are

mapped on the basis of the peripheral; that is, a control

register associated with a peripheral dictates the pin it

will be mapped to. The RPINRx registers are used to

configure peripheral input mapping (see Register 10-1

through Register 10-14). Each register contains two

sets of 5-bit fields, with each set associated with one of

the pin selectable peripherals. Programming a given

peripheral’s bit field with an appropriate 5-bit value

maps the RPn pin with that value to that peripheral. For

any given device, the valid range of values for any of

the bit fields corresponds to the maximum number of

peripheral pin selections supported by the device.

10.4.2

AVAILABLE PERIPHERALS

The peripherals managed by the peripheral pin select

are all digital only peripherals. These include general

serial communications (UART and SPI), general pur-

pose timer clock inputs, timer related peripherals (input

capture and output compare) and external interrupt

inputs. Also included are the outputs of the comparator

module, since these are discrete digital signals.

The peripheral pin select module is not applied to

I²C™, change notification inputs, RTCC alarm outputs

or peripherals with analog inputs.

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TABLE 10-2:

SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)⁽¹⁾

Configuration

Bits

Input Name

Function Name

Register

External Interrupt 1

External Interrupt 2

Timer2 External Clock

Timer3 External Clock

Timer4 External Clock

Timer5 External Clock

Input Capture 1

INT1

INT2

RPINR0

RPINR1

RPINR3

RPINR4

RPINR7

RPINR8

RPINR9

RPINR11

RPINR18

RPINR19

RPINR20

RPINR21

RPINR22

RPINR23

INTR1<4:0>

INTR2R<4:0>

T2CKR<4:0>

T3CKR<4:0>

T4CKR<4:0>

T5CKR<4:0>

IC1R<4:0>

T2CK

T3CK

T4CK

T5CK

IC1

Input Capture 2

IC2

IC2R<4:0>

Input Capture 3

IC3

IC3R<4:0>

Input Capture 4

IC4

IC4R<4:0>

Input Capture 5

IC5

IC5R<4:0>

Output Compare Fault A

Output Compare Fault B

UART1 Receive

OCFA

OCFB

U1RX

U1CTS

U2RX

U2CTS

SDI1

OCFAR<4:0>

OCFBR<4:0>

U1RXR<4:0>

U1CTSR<4:0>

U2RXR<4:0>

U2CTSR<4:0>

SDI1R<4:0>

SCK1R<4:0>

SS1R<4:0>

SDI2R<4:0>

SCK2R<4:0>

SS2R<4:0>

UART1 Clear To Send

UART2 Receive

UART2 Clear To Send

SPI1 Data Input

SPI1 Clock Input

SCK1IN

SS1IN

SDI2

SPI1 Slave Select Input

SPI2 Data Input

SPI2 Clock Input

SCK2IN

SS2IN

SPI2 Slave Select Input

Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

Because of the mapping technique, the list of peripher-

als for output mapping also includes a null value of

‘00000’. This permits any given pin to remain discon-

nected from the output of any of the pin selectable

peripherals.

10.4.3.2

Output Mapping

In contrast to inputs, the outputs of the peripheral pin

select options are mapped on the basis of the pin. In

this case, a control register associated with a particular

pin dictates the peripheral output to be mapped. The

RPORx registers are used to control output mapping.

Like the RPINRx registers, each register contains two

5-bit fields; each field being associated with one RPn

pin (see Register 10-15 through Register 10-27). The

value of the bit field corresponds to one of the periph-

erals and that peripheral’s output is mapped to the pin

(see Table 10-3).

DS39881D-page 108

 2010 Microchip Technology Inc.

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TABLE 10-3: SELECTABLE OUTPUT

SOURCES (MAPS FUNCTION

TO OUTPUT)

10.4.4.1

Control Register Lock

Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes will

appear to execute normally, but the contents of the

registers will remain unchanged. To change these reg-

isters, they must be unlocked in hardware. The register

lock is controlled by the IOLOCK bit (OSCCON<6>).

Setting IOLOCK prevents writes to the control

registers; clearing IOLOCK allows writes.

OutputFunction

Function

Output Name

Number⁽¹⁾

NULL⁽²⁾

C1OUT

C2OUT

U1TX

0

1

NULL

Comparator 1 Output

Comparator 2 Output

UART1 Transmit

2

3

To set or clear IOLOCK, a specific command sequence

must be executed:

U1RTS⁽³⁾

4

UART1 Request To Send

UART2 Transmit

U2TX

5

1. Write 46h to OSCCON<7:0>.

U2RTS⁽³⁾

SDO1

6

UART2 Request To Send

SPI1 Data Output

2. Write 57h to OSCCON<7:0>.

3. Clear (or set) IOLOCK as a single operation.

7

SCK1OUT

SS1OUT

SDO2

8

SPI1 Clock Output

SPI1 Slave Select Output

SPI2 Data Output

Unlike the similar sequence with the oscillator’s LOCK

bit, IOLOCK remains in one state until changed. This

allows all of the peripheral pin selects to be configured

with a single unlock sequence followed by an update to

all control registers, then locked with a second lock

sequence.

9

10

11

12

18

19

20

21

22

SCK2OUT

SS2OUT

OC1

SPI2 Clock Output

SPI2 Slave Select Output

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 4

Output Compare 5

10.4.4.2

Continuous State Monitoring

OC2

OC3

In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are

constantly monitored in hardware by shadow registers.

If an unexpected change in any of the registers occurs

(such as cell disturbances caused by ESD or other

external events), a Configuration Mismatch Reset will

be triggered.

OC4

OC5

Note 1: Value assigned to the RPn<4:0> pins corre-

sponds to the peripheral output function

number.

2: The NULL function is assigned to all RPn

outputs at device Reset and disables the

RPn output function.

10.4.4.3

Configuration Bit Pin Select Lock

As an additional level of safety, the device can be con-

figured to prevent more than one write session to the

RPINRx and RPORx registers. The IOL1WAY

(CW2<4>) Configuration bit blocks the IOLOCK bit

from being cleared after it has been set once. If

IOLOCK remains set, the register unlock procedure will

not execute and the Peripheral Pin Select Control reg-

isters cannot be written to. The only way to clear the bit

and re-enable peripheral remapping is to perform a

device Reset.

3: IrDA^®BCLK functionality uses this output.

10.4.3.3

Mapping Limitations

The control schema of the peripheral pin select is

extremely flexible. Other than systematic blocks that

prevent signal contention caused by two physical pins

being configured as the same functional input or two

functional outputs configured as the same pin, there

are no hardware enforced lock outs. The flexibility

extends to the point of allowing a single input to drive

multiple peripherals or a single functional output to

drive multiple output pins.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session. Programming

IOL1WAY allows users unlimited access (with the

proper use of the unlock sequence) to the Peripheral

Pin Select registers.

10.4.4

CONTROLLING CONFIGURATION

CHANGES

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. PIC24F devices include three features to

prevent alterations to the peripheral map:

• Control register lock sequence

• Continuous state monitoring

• Configuration bit remapping lock

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A final consideration is that peripheral pin select func-

tions neither override analog inputs, nor reconfigure

pins with analog functions for digital I/O. If a pin is

configured as an analog input on device Reset, it must

be explicitly reconfigured as digital I/O when used with

a peripheral pin select.

10.4.5

CONSIDERATIONS FOR

PERIPHERAL PIN SELECTION

The ability to control peripheral pin selection introduces

several considerations into application design that

could be overlooked. This is particularly true for several

common peripherals that are available only as

remappable peripherals.

Example 10-2 shows a configuration for bidirectional

communication with flow control using UART1. The

following input and output functions are used:

The main consideration is that the peripheral pin

selects are not available on default pins in the device’s

default (Reset) state. Since all RPINRx registers reset

to ‘11111’ and all RPORx registers reset to ‘00000’, all

peripheral pin select inputs are tied to RP31 and all

peripheral pin select outputs are disconnected.

• Input Functions: U1RX, U1CTS

• Output Functions: U1TX, U1RTS

EXAMPLE 10-2:

CONFIGURING UART1

INPUT AND OUTPUT

FUNCTIONS

Note:

In tying peripheral pin select inputs to

RP31, RP31 does not have to exist on a

device for the registers to be reset to it.

//*************************************

// Unlock Registers

This situation requires the user to initialize the device

with the proper peripheral configuration before any

other application code is executed. Since the IOLOCK

bit resets in the unlocked state, it is not necessary to

execute the unlock sequence after the device has

come out of Reset. For application safety, however, it is

best to set IOLOCK and lock the configuration after

writing to the control registers.

//*************************************

asm volatile ( "MOV

#OSCCON, w1 \n"

"MOV

#0x46, w2

#0x57, w3

\n"

"MOV.b w2, [w1]

"MOV.b w3, [w1]

"BCLR OSCCON,#6");

//***************************

Because the unlock sequence is timing critical, it must

be executed as an assembly language routine in the

same manner as changes to the oscillator configura-

tion. If the bulk of the application is written in C or

another high-level language, the unlock sequence

should be performed by writing inline assembly.

// Configure Input Functions

// (See Table 10-2)

//***************************

// Assign U1RX To Pin RP0

//***************************

RPINR18bits.U1RXR = 0;

Choosing the configuration requires the review of all

peripheral pin selects and their pin assignments,

especially those that will not be used in the application.

In all cases, unused pin-selectable peripherals should

be disabled completely. Unused peripherals should

have their inputs assigned to an unused RPn pin

function. I/O pins with unused RPn functions should be

configured with the null peripheral output.

//***************************

// Assign U1CTS To Pin RP1

//***************************

RPINR18bits.U1CTSR = 1;

//***************************

// Configure Output Functions

// (See Table 10-3)

//***************************

// Assign U1TX To Pin RP2

//***************************

RPOR1bits.RP2R = 3;

The assignment of a peripheral to a particular pin does

not automatically perform any other configuration of the

pin’s I/O circuitry. In theory, this means adding a

pin-selectable output to a pin may mean inadvertently

driving an existing peripheral input when the output is

driven. Users must be familiar with the behavior of

other fixed peripherals that share a remappable pin and

know when to enable or disable them. To be safe, fixed

digital peripherals that share the same pin should be

disabled when not in use.

//***************************

// Assign U1RTS To Pin RP3

//***************************

RPOR1bits.RP3R = 4;

//*************************************

// Lock Registers

//*************************************

Along these lines, configuring a remappable pin for a

specific peripheral does not automatically turn that fea-

ture on. The peripheral must be specifically configured

for operation and enabled, as if it were tied to a fixed pin.

Where this happens in the application code (immediately

following device Reset and peripheral configuration or

inside the main application routine) depends on the

peripheral and its use in the application.

asm volatile ( "MOV

#OSCCON, w1 \n"

"MOV

"MOV.b w2, [w1]

"MOV.b w3, [w1]

#0x46, w2

#0x57, w3

\n"

"BSET

OSCCON, #6" );

DS39881D-page 110

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10.5 Peripheral Pin Select Registers

Note:

Input and output register values can only

be changed if OSCCON<IOLOCK> = 0.

See Section 10.4.4.1 “Control Register

Lock” for a specific command sequence.

The PIC24FJ64GA004 family of devices implements a

total of 27 registers for remappable peripheral

configuration:

• Input Remappable Peripheral Registers (14)

• Output Remappable Peripheral Registers (13)

REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0

U-0

—

U-0

—

U-0

—

R/W-1

INT1R4

INT1R3

INT1R2

INT1R1

INT1R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-0

Unimplemented: Read as ‘0’

INT1R4:INT1R0: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

INT2R4

INT2R3

INT2R2

INT2R1

INT2R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

INT2R4:INT2R0: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits

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REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3

U-0

—

U-0

—

U-0

—

R/W-1

T3CKR4

T3CKR3

T3CKR2

T3CKR1

T3CKR0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

T2CKR4

T2CKR3

T2CKR2

T2CKR1

T2CKR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

T3CKR4:T3CKR0: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

T2CKR4:T2CKR0: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits

REGISTER 10-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4

U-0

—

U-0

—

U-0

—

R/W-1

T5CKR0

bit 8

T5CKR4

T5CKR3

T5CKR2

T5CKR1

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

T4CKR4

T4CKR3

T4CKR2

T4CKR1

T4CKR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

T5CKR4:T5CKR0: Assign Timer5 External Clock (T5CK) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

T4CKR4:T4CKR0: Assign Timer4 External Clock (T4CK) to the Corresponding RPn Pin bits

DS39881D-page 112

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REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7

U-0

—

U-0

—

U-0

—

R/W-1

IC2R4

R/W-1

IC2R3

R/W-1

IC2R2

R/W-1

IC2R1

R/W-1

IC2R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

IC1R4

R/W-1

IC1R3

R/W-1

IC1R2

R/W-1

IC1R1

R/W-1

IC1R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

IC2R4:IC2R0: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

IC1R4:IC1R0: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits

REGISTER 10-6: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8

U-0

—

U-0

—

U-0

—

R/W-1

IC4R4

R/W-1

IC4R3

R/W-1

IC4R2

R/W-1

IC4R1

R/W-1

IC4R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

IC3R4

R/W-1

IC3R3

R/W-1

IC3R2

R/W-1

IC3R1

R/W-1

IC3R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

IC4R4:IC4R0: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

IC3R4:IC3R0: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits

 2010 Microchip Technology Inc.

DS39881D-page 113

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REGISTER 10-7: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

IC5R4

R/W-1

IC5R3

R/W-1

IC5R2

R/W-1

IC5R1

R/W-1

IC5R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

IC5R4:IC5R0: Assign Input Capture 5 (IC5) to the Corresponding RPn Pin bits

REGISTER 10-8: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11

U-0

—

U-0

—

U-0

—

R/W-1

OCFBR4

OCFBR3

OCFBR2

OCFBR1

OCFBR0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

OCFAR4

OCFAR3

OCFAR2

OCFAR1

OCFAR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

OCFBR4:OCFBR0: Assign Output Compare Fault B (OCFB) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

OCFAR4:OCFAR0: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits

DS39881D-page 114

 2010 Microchip Technology Inc.

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REGISTER 10-9: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18

U-0

—

U-0

—

U-0

—

R/W-1

U1CTSR4

U1CTSR3

U1CTSR2

U1CTSR1

U1CTSR0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

U1RXR4

U1RXR3

U1RXR2

U1RXR1

U1RXR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

U1CTSR4:U1CTSR0: Assign UART1 Clear to Send (U1CTS) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

U1RXR4:U1RXR0: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits

REGISTER 10-10: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19

U-0

—

U-0

—

U-0

—

R/W-1

U2CTSR0

bit 8

U2CTSR4

U2CTSR3

U2CTSR2

U2CTSR1

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

U2RXR4

U2RXR3

U2RXR2

U2RXR1

U2RXR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

U2CTSR4:U2CTSR0: Assign UART2 Clear to Send (U2CTS) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

U2RXR4:U2RXR0: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits

 2010 Microchip Technology Inc.

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REGISTER 10-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20

U-0

—

U-0

—

U-0

—

R/W-1

SCK1R4

SCK1R3

SCK1R2

SCK1R1

SCK1R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

SDI1R4

SDI1R3

SDI1R2

SDI1R1

SDI1R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

SCK1R4:SCK1R0: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

SDI1R4:SDI1R0: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits

REGISTER 10-12: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

SS1R4

SS1R3

SS1R2

SS1R1

SS1R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

SS1R4:SS1R0: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn Pin bits

DS39881D-page 116

 2010 Microchip Technology Inc.

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REGISTER 10-13: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22

U-0

—

U-0

—

U-0

—

R/W-1

SCK2R4

SCK2R3

SCK2R2

SCK2R1

SCK2R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

SDI2R4

SDI2R3

SDI2R2

SDI2R1

SDI2R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

bit 7-5

Unimplemented: Read as ‘0’

SCK2R4:SCK2R0: Assign SPI2 Clock Input (SCK2IN) to the Corresponding RPn Pin bits

Unimplemented: Read as ‘0’

bit 4-0

SDI2R4:SDI2R0: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits

REGISTER 10-14: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

SS2R4

SS2R3

SS2R2

SS2R1

SS2R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

SS2R4:SS2R0: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits

 2010 Microchip Technology Inc.

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REGISTER 10-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0

U-0

—

U-0

—

U-0

—

R/W-0

RP1R4

RP1R3

RP1R2

RP1R1

RP1R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP0R4

RP0R3

RP0R2

RP0R1

RP0R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP1R4:RP1R0: Peripheral Output Function is Assigned to RP1 Output Pin bits

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP0R4:RP0R0: Peripheral Output Function is Assigned to RP0 Output Pin bits

(see Table 10-3 for peripheral function numbers)

REGISTER 10-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0

RP3R4

RP3R3

RP3R2

RP3R1

RP3R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP2R4

RP2R3

RP2R2

RP2R1

RP2R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP3R4:RP3R0: Peripheral Output Function is Assigned to RP3 Output Pin bits

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP2R4:RP2R0: Peripheral Output Function is Assigned to RP2 Output Pin bits

(see Table 10-3 for peripheral function numbers)

DS39881D-page 118

 2010 Microchip Technology Inc.

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REGISTER 10-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2

U-0

—

U-0

—

U-0

—

R/W-0

RP5R4

RP5R3

RP5R2

RP5R1

RP5R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP4R4

RP4R3

RP4R2

RP4R1

RP4R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP5R4:RP5R0: Peripheral Output Function is Assigned to RP5 Output Pin bits

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP4R4:RP4R0: Peripheral Output Function is Assigned to RP4 Output Pin bits

(see Table 10-3 for peripheral function numbers)

REGISTER 10-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3

U-0

—

U-0

—

U-0

—

R/W-0

RP7R4

RP7R3

RP7R2

RP7R1

RP7R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP6R4

RP6R3

RP6R2

RP6R1

RP6R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP7R4:RP7R0: Peripheral Output Function is Assigned to RP7 Output Pin bits

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP6R4:RP6R0: Peripheral Output Function is Assigned to RP6 Output Pin bits

(see Table 10-3 for peripheral function numbers)

 2010 Microchip Technology Inc.

DS39881D-page 119

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REGISTER 10-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4

U-0

—

U-0

—

U-0

—

R/W-0

RP9R4

RP9R3

RP9R2

RP9R1

RP9R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP8R4

RP8R3

RP8R2

RP8R1

RP8R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP9R4:RP9R0: Peripheral Output Function is Assigned to RP9 Output Pin bits

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP8R4:RP8R0: Peripheral Output Function is Assigned to RP8 Output Pin bits

(see Table 10-3 for peripheral function numbers)

REGISTER 10-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5

U-0

—

U-0

—

U-0

—

R/W-0

RP11R4

RP11R3

RP11R2

RP11R1

RP11R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP10R4

RP10R3

RP10R2

RP10R1

RP10R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP11R4:RP11R0: Peripheral Output Function is Assigned to RP11 Output Pin bits

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP10R4:RP10R0: Peripheral Output Function is Assigned to RP10 Output Pin bits

(see Table 10-3 for peripheral function numbers)

DS39881D-page 120

 2010 Microchip Technology Inc.

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REGISTER 10-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6

U-0

—

U-0

—

U-0

—

R/W-0

RP13R4

RP13R3

RP13R2

RP13R1

RP13R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP12R4

RP12R3

RP12R2

RP12R1

RP12R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP13R4:RP13R0: Peripheral Output Function is Assigned to RP13 Output Pin bits

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP12R4:RP12R0: Peripheral Output Function is Assigned to RP12 Output Pin bits

(see Table 10-3 for peripheral function numbers)

REGISTER 10-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7

U-0

—

U-0

—

U-0

—

R/W-0

RP15R4

RP15R3

RP15R2

RP15R1

RP15R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP14R4

RP14R3

RP14R2

RP14R1

RP14R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP15R4:RP15R0: Peripheral Output Function is Assigned to RP15 Output Pin bits

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP14R4:RP14R0: Peripheral Output Function is Assigned to RP14 Output Pin bits

(see Table 10-3 for peripheral function numbers)

 2010 Microchip Technology Inc.

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REGISTER 10-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8

U-0

—

U-0

—

U-0

—

R/W-0

RP17R4⁽¹⁾

R/W-0

RP17R3⁽¹⁾

R/W-0

RP17R2⁽¹⁾

R/W-0

RP17R1⁽¹⁾

R/W-0

RP17R0⁽¹⁾

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP16R4⁽¹⁾

R/W-0

RP16R3⁽¹⁾

R/W-0

RP16R2⁽¹⁾

R/W-0

RP16R1⁽¹⁾

R/W-0

RP16R0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP17R4:RP17R0: Peripheral Output Function is Assigned to RP17 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP16R4:RP16R0: Peripheral Output Function is Assigned to RP16 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

Note 1: Bits are only available on the 44-pin devices; otherwise, they read as ‘0’.

REGISTER 10-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9

U-0

—

U-0

—

U-0

—

R/W-0

RP19R4

RP19R3

RP19R2

RP19R1

RP19R0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP18R4

RP18R3

RP18R2

RP18R1

RP18R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP19R4:RP19R0: Peripheral Output Function is Assigned to RP19 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP18R4:RP18R0: Peripheral Output Function is Assigned to RP18 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

Note 1: Bits are only available on the 44-pin devices; otherwise, they read as ‘0’.

DS39881D-page 122

 2010 Microchip Technology Inc.

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REGISTER 10-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10

U-0

—

U-0

—

U-0

—

R/W-0

RP21R4⁽¹⁾

R/W-0

RP21R3⁽¹⁾

R/W-0

RP21R2⁽¹⁾

R/W-0

RP21R1⁽¹⁾

R/W-0

RP21R0⁽¹⁾

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP20R4⁽¹⁾

R/W-0

RP20R3⁽¹⁾

R/W-0

RP20R2⁽¹⁾

R/W-0

RP20R1⁽¹⁾

R/W-0

RP20R0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP21R4:RP21R0: Peripheral Output Function is Assigned to RP21 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP20R4:RP20R0: Peripheral Output Function is Assigned to RP20 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

Note 1: Bits are only available on the 44-pin devices; otherwise, they read as ‘0’.

REGISTER 10-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11

U-0

—

U-0

—

U-0

—

R/W-0

RP23R4⁽¹⁾

R/W-0

RP23R3⁽¹⁾

R/W-0

RP23R2⁽¹⁾

R/W-0

RP23R1⁽¹⁾

R/W-0

RP23R0⁽¹⁾

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP22R4⁽¹⁾

R/W-0

RP22R3⁽¹⁾

R/W-0

RP22R2⁽¹⁾

R/W-0

RP22R1⁽¹⁾

R/W-0

RP22R0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP23R4:RP23R0: Peripheral Output Function is Assigned to RP23 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP22R4:RP22R0: Peripheral Output Function is Assigned to RP22 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

Note 1: Bits are only available on the 44-pin devices; otherwise, they read as ‘0’.

 2010 Microchip Technology Inc.

DS39881D-page 123

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REGISTER 10-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12

U-0

—

U-0

—

U-0

—

R/W-0

RP25R4⁽¹⁾

R/W-0

RP25R3⁽¹⁾

R/W-0

RP25R2⁽¹⁾

R/W-0

RP25R1⁽¹⁾

R/W-0

RP25R0⁽¹⁾

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

RP24R4⁽¹⁾

R/W-0

RP24R3⁽¹⁾

R/W-0

RP24R2⁽¹⁾

R/W-0

RP24R1⁽¹⁾

R/W-0

RP24R0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP25R4:RP25R0: Peripheral Output Function is Assigned to RP25 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP24R4:RP24R0: Peripheral Output Function is Assigned to RP24 Output Pin bits⁽¹⁾

(see Table 10-3 for peripheral function numbers)

Note 1: Bits are only available on the 44-pin devices; otherwise, they read as ‘0’.

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Figure 11-1 presents a block diagram of the 16-bit timer

module.

11.0 TIMER1

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 14. Timers” (DS39704).

To configure Timer1 for operation:

1. Set the TON bit (= 1).

2. Select the timer prescaler ratio using the

TCKPS1:TCKPS0 bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

The Timer1 module is a 16-bit timer which can serve as

the time counter for the Real-Time Clock (RTC), or

operate as a free-running, interval timer/counter.

Timer1 can operate in three modes:

4. Set or clear the TSYNC bit to configure

synchronous or asynchronous operation.

5. Load the timer period value into the PR1

register.

• 16-Bit Timer

6. If interrupts are required, set the interrupt enable

bit, T1IE. Use the priority bits, T1IP2:T1IP0, to

set the interrupt priority.

• 16-Bit Synchronous Counter

• 16-Bit Asynchronous Counter

Timer1 also supports these features:

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation during CPU Idle and Sleep

modes

• Interrupt on 16-Bit Period Register Match or

Falling Edge of External Gate Signal

FIGURE 11-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

TCKPS1:TCKPS0

TON

2

SOSCO/

1x

01

00

T1CK

Prescaler

1, 8, 64, 256

Gate

Sync

SOSCEN

SOSCI

TCY

TGATE

TCS

TGATE

1

0

Q

D

Set T1IF

CK

0

Reset

Equal

TMR1

Sync

1

TSYNC

Comparator

PR1

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REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS1

TCKPS0

TSYNC

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timer1 On bit

1= Starts 16-bit Timer1

0= Stops 16-bit Timer1

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

TCKPS1:TCKPS0: Timer1 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3

bit 2

Unimplemented: Read as ‘0’

TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1= Synchronize external clock input

0= Do not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1

bit 0

TCS: Timer1 Clock Source Select bit

1= External clock from T1CK pin (on the rising edge)

0= Internal clock (FOSC/2)

Unimplemented: Read as ‘0’

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To configure Timer2/3 or Timer4/5 for 32-bit operation:

12.0 TIMER2/3 AND TIMER4/5

1. Set the T32 bit (T2CON<3> or T4CON<3> = 1).

Note:

This data sheet summarizes the features

2. Select the prescaler ratio for Timer2 or Timer4

using the TCKPS1:TCKPS0 bits.

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 14. Timers” (DS39704).

3. Set the Clock and Gating modes using the TCS

and TGATE bits. If TCS is set to external clock,

RPINRx (TxCK) must be configured to an avail-

able RPn pin. See Section 10.4 “Peripheral

Pin Select” for more information.

The Timer2/3 and Timer4/5 modules are 32-bit timers,

which can also be configured as four independent 16-bit

timers with selectable operating modes.

4. Load the timer period value. PR3 (or PR5) will

contain the most significant word of the value

while PR2 (or PR4) contains the least significant

word.

As a 32-bit timer, Timer2/3 and Timer4/5 operate in

three modes:

5. If interrupts are required, set the interrupt enable

bit, T3IE or T5IE; use the priority bits,

T3IP2:T3IP0 or T5IP2:T5IP0, to set the interrupt

priority. Note that while Timer2 or Timer4 con-

trols the timer, the interrupt appears as a Timer3

or Timer5 interrupt.

• Two independent 16-bit timers (Timer2 and

Timer3) with all 16-bit operating modes (except

Asynchronous Counter mode)

• Single 32-bit timer

• Single 32-bit synchronous counter

They also support these features:

6. Set the TON bit (= 1).

• Timer gate operation

The timer value, at any point, is stored in the register

pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)

always contains the most significant word of the count,

while TMR2 (TMR4) contains the least significant word.

• Selectable prescaler settings

• Timer operation during Idle and Sleep modes

• Interrupt on a 32-Bit Period register match

• ADC Event Trigger (Timer4/5 only)

To configure any of the timers for individual 16-bit

operation:

Individually, all four of the 16-bit timers can function as

synchronous timers or counters. They also offer the

features listed above, except for the ADC Event

Trigger; this is implemented only with Timer5. The

operating modes and enabled features are determined

by setting the appropriate bit(s) in the T2CON, T3CON,

T4CON and T5CON registers. T2CON and T4CON are

shown in generic form in Register 12-1; T3CON and

T5CON are shown in Register 12-2.

1. Clear the T32 bit corresponding to that timer

(T2CON<3> for Timer2 and Timer3 or

T4CON<3> for Timer4 and Timer5).

2. Select the timer prescaler ratio using the

TCKPS1:TCKPS0 bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits. See Section 10.4 “Peripheral

Pin Select” for more information.

For 32-bit timer/counter operation, Timer2 and Timer4

are the least significant word; Timer3 and Timer4 are

the most significant word of the 32-bit timers.

4. Load the timer period value into the PRx register.

5. If interrupts are required, set the interrupt enable

bit, TxIE; use the priority bits, TxIP2:TxIP0, to

set the interrupt priority.

Note:

For 32-bit operation, T3CON and T5CON

control bits are ignored. Only T2CON and

T4CON control bits are used for setup and

control. Timer2 and Timer4 clock and gate

inputs are utilized for the 32-bit timer

modules, but an interrupt is generated with

the Timer3 or Timer5 interrupt flags.

6. Set the TON bit (TxCON<15> = 1).

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FIGURE 12-1:

TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM

TCKPS1:TCKPS0

2

TON

T2CK

(T4CK)

1x

Prescaler

1, 8, 64, 256

Gate

01

00

Sync

TCY

(2)

TGATE

(2)

TCS

1

0

Q

D

Set T3IF (T5IF)

Q

CK

PR3

PR2

(PR5)

(PR4)

(3)

ADC Event Trigger

Equal

MSB

Comparator

LSB

TMR2

(TMR4)

TMR3

(TMR5)

Sync

Reset

16

(1)

Read TMR2 (TMR4)

Write TMR2 (TMR4)

16

TMR3HLD

(TMR5HLD)

Data Bus<15:0>

Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are

respective to the T2CON and T4CON registers.

2: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section

10.4 “Peripheral Pin Select” for more information.

3: The ADC event trigger is available only on Timer2/3.

DS39881D-page 128

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FIGURE 12-2:

TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM

TCKPS1:TCKPS0

2

TON

T2CK

(T4CK)

1x

Prescaler

1, 8, 64, 256

Gate

Sync

01

00

TGATE

(1)

TCS

TGATE

TCY

(1)

Q

D

1

0

Set T2IF (T4IF)

Q

CK

Reset

Equal

TMR2 (TMR4)

Sync

Comparator

PR2 (PR4)

Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section

10.4 “Peripheral Pin Select” for more information.

FIGURE 12-3:

TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM

TCKPS1:TCKPS0

2

TON

T3CK

(T5CK)

1x

01

00

Sync

Prescaler

1, 8, 64, 256

TGATE

(1)

TCS

TGATE

TCY

(1)

Q

D

1

0

Set T3IF (T5IF)

CK

Reset

Equal

TMR3 (TMR5)

(2)

ADC Event Trigger

Comparator

PR3 (PR5)

Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section

10.4 “Peripheral Pin Select” for more information.

2: The ADC event trigger is available only on Timer3.

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REGISTER 12-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

T32⁽¹⁾

U-0

—

R/W-0

TCS⁽²⁾

U-0

—

TGATE

TCKPS1

TCKPS0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

TON: Timerx On bit

When TxCON<3> = 1:

1= Starts 32-bit Timerx/y

0= Stops 32-bit Timerx/y

When TxCON<3> = 0:

1= Starts 16-bit Timerx

0= Stops 16-bit Timerx

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

bit 3

TCKPS1:TCKPS0: Timerx Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

T32: 32-Bit Timer Mode Select bit⁽¹⁾

1= Timerx and Timery form a single 32-bit timer

0= Timerx and Timery act as two 16-bit timers

In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.

bit 2

bit 1

Unimplemented: Read as ‘0’

TCS: Timerx Clock Source Select bit⁽²⁾

1= External clock from pin, TxCK (on the rising edge)

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Note 1: In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.

2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see

Section 10.4 “Peripheral Pin Select”.

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REGISTER 12-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER

R/W-0

TON⁽¹⁾

U-0

—

R/W-0

TSIDL⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

TGATE⁽¹⁾

R/W-0

TCKPS1⁽¹⁾

R/W-0

TCKPS0⁽¹⁾

U-0

—

U-0

—

R/W-0

TCS^(1,2)

U-0

—

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

TON: Timery On bit⁽¹⁾

1= Starts 16-bit Timery

0= Stops 16-bit Timery

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit⁽¹⁾

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timery Gated Time Accumulation Enable bit⁽¹⁾

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

TCKPS1:TCKPS0: Timery Input Clock Prescale Select bits⁽¹⁾

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3-2

bit 1

Unimplemented: Read as ‘0’

TCS: Timery Clock Source Select bit^(1,2)

1= External clock from pin TyCK (on the rising edge)

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Note 1: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery

operation; all timer functions are set through T2CON and T4CON.

2: If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral

Pin Select” for more information.

 2010 Microchip Technology Inc.

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NOTES:

DS39881D-page 132

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13.0 INPUT CAPTURE

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 15. Input Capture” (DS39701).

FIGURE 13-1:

INPUT CAPTURE BLOCK DIAGRAM

From 16-Bit Timers

TMRy TMRx

16

ICTMR

(ICxCON<7>)

1

0

Prescaler

FIFO

R/W

Logic

Edge Detection Logic

and

Clock Synchronizer

Counter

(1, 4, 16)

ICx Pin

ICM<2:0> (ICxCON<2:0>)

3

Mode Select

ICOV, ICBNE (ICxCON<4:3>)

ICxBUF

ICI<1:0>

Interrupt

Logic

ICxCON

System Bus

Set Flag ICxIF

(in IFSn Register)

Note 1: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

2: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 10.4

“Peripheral Pin Select” for more information.

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13.1 Input Capture Registers

REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

ICSIDL

bit 15

bit 8

R/W-0

ICI1

R/W-0

ICI0

R-0, HC

ICOV

R-0, HC

ICBNE

R/W-0

ICM2⁽¹⁾

R/W-0

ICM1⁽¹⁾

R/W-0

ICM0⁽¹⁾

ICTMR

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15-14

bit 13

Unimplemented: Read as ‘0’

ICSIDL: Input Capture x Module Stop in Idle Control bit

1= Input capture module will halt in CPU Idle mode

0= Input capture module will continue to operate in CPU Idle mode

bit 12-8

bit 7

Unimplemented: Read as ‘0’

ICTMR: Input Capture x Timer Select bit

1= TMR2 contents are captured on capture event

0= TMR3 contents are captured on capture event

bit 6-5

ICI1:ICI0: Select Number of Captures per Interrupt bits

11= Interrupt on every fourth capture event

10= Interrupt on every third capture event

01= Interrupt on every second capture event

00= Interrupt on every capture event

bit 4

ICOV: Input Capture x Overflow Status Flag bit (read-only)

1= Input capture overflow occurred

0= No input capture overflow occurred

bit 3

ICBNE: Input Capture x Buffer Empty Status bit (read-only)

1= Input capture buffer is not empty, at least one more capture value can be read

0= Input capture buffer is empty

bit 2-0

ICM2:ICM0: Input Capture x Mode Select bits⁽¹⁾

111= Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge

detect only, all other control bits are not applicable)

110= Unused (module disabled)

101= Capture mode, every 16th rising edge

100= Capture mode, every 4th rising edge

011= Capture mode, every rising edge

010= Capture mode, every falling edge

001= Capture mode, every edge (rising and falling) – ICI<1:0> bits do not control interrupt generation

for this mode

000= Input capture module turned off

Note 1: RPINRx (ICxRx) must be configured to an available RPn pin. For more information, see Section 10.4

“Peripheral Pin Select”.

DS39881D-page 134

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10. To initiate another single pulse output, change the

Timer and Compare register settings, if needed,

and then issue a write to set the OCM bits to ‘100’.

14.0 OUTPUT COMPARE

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

Disabling and re-enabling of the timer and clear-

ing the TMRy register are not required, but may

be advantageous for defining a pulse from a

known event time boundary.

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section

16.

Output

Compare”

The output compare module does not have to be dis-

abled after the falling edge of the output pulse. Another

pulse can be initiated by rewriting the value of the

OCxCON register.

(DS39706).

14.1 Setup for Single Output Pulse

Generation

14.2 Setup for Continuous Output

Pulse Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘100’, the selected output compare channel initializes

the OCx pin to the low state and generates a single

output pulse.

When the OCM control bits (OCxCON<2:0>) are set to

‘101’, the selected output compare channel initializes

the OCx pin to the low state and generates output

pulses on each and every compare match event.

To generate a single output pulse, the following steps

are required (these steps assume the timer source is

initially turned off, but this is not a requirement for the

module operation):

For the user to configure the module for the generation

of a continuous stream of output pulses, the following

steps are required (these steps assume the timer

source is initially turned off, but this is not a requirement

for the module operation):

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

2. Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

3. Calculate the time to the falling edge of the pulse

based on the desired pulse width and the time to

the rising edge of the pulse.

4. Write the values computed in steps 2 and 3

above into the Output Compare x register,

OCxR, and the Output Compare x Secondary

register, OCxRS, respectively.

5. Set Timer Period register, PRy, to value equal to

or greater than value in OCxRS, the Output

Compare x Secondary register.

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

2. Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

3. Calculate the time to the falling edge of the pulse

based on the desired pulse width and the time to

the rising edge of the pulse.

4. Write the values computed in step 2 and 3 above

into the Output Compare x register, OCxR, and

the Output Compare x Secondary register,

OCxRS, respectively.

5. Set Timer Period register, PRy, to value equal to

or greater than value in OCxRS.

6. Set the OCM bits to ‘100’ and the OCTSEL

(OCxCON<3>) bit to the desired timer source.

The OCx pin state will now be driven low.

7. Set the TON (TyCON<15>) bit to ‘1’, which

enables the compare time base to count.

6. Set the OCM bits to ‘101’ and the OCTSEL bit to

the desired timer source. The OCx pin state will

now be driven low.

7. Enable the compare time base by setting the TON

(TyCON<15>) bit to ‘1’.

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

9. When the incrementing timer, TMRy, matches the

Output Compare x Secondary register, OCxRS,

the second and trailing edge (high-to-low) of the

pulse is driven onto the OCx pin. No additional

pulses are driven onto the OCx pin and it remains

at low. As a result of the second compare match

event, the OCxIF interrupt flag bit is set, which

will result in an interrupt if it is enabled, by set-

ting the OCxIE bit. For further information on

peripheral interrupts, refer to Section 7.0

“Interrupt Controller”.

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

9. When the compare time base, TMRy, matches the

OCxRS, the second and trailing edge (high-to-low)

of the pulse is driven onto the OCx pin.

10. As a result of the second compare match event,

the OCxIF interrupt flag bit set.

11. When the compare time base and the value in its

respective Timer Period register match, the TMRy

register resets to 0x0000and resumes counting.

12. Steps 8 through 11 are repeated and a continuous

stream of pulses is generated indefinitely. The

OCxIF flag is set on each OCxRS/TMRy compare

match event.

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EQUATION 14-1: CALCULATING THE PWM

14.3 Pulse-Width Modulation Mode

PERIOD⁽¹⁾

Note:

This peripheral contains input and output

functions that may need to be configured

by the peripheral pin select. See

Section 10.4 “Peripheral Pin Select” for

more information.

PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value)

where:

PWM Frequency = 1/[PWM Period]

Note 1: Based on TCY = 2 * TOSC, Doze mode

and PLL are disabled.

The following steps should be taken when configuring

the output compare module for PWM operation:

1. Set the PWM period by writing to the selected

Timer Period register (PRy).

Note:

A PRy value of N will produce a PWM

period of N + 1 time base count cycles. For

example, a value of 7 written into the PRy

register will yield a period consisting of

8 time base cycles.

2. Set the PWM duty cycle by writing to the OCxRS

register.

3. Write the OCxR register with the initial duty cycle.

4. Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin utilization.

14.3.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

OCxRS register. The OCxRS register can be written to

at any time, but the duty cycle value is not latched into

OCxR until a match between PRy and TMRy occurs

(i.e., the period is complete). This provides a double

buffer for the PWM duty cycle and is essential for glitch-

less PWM operation. In the PWM mode, OCxR is a

read-only register.

5. Configure the output compare module for one of

two PWM Operation modes by writing to the

Output Compare Mode bits, OCM<2:0>

(OCxCON<2:0>).

6. Set the TMRy prescale value and enable the time

base by setting TON (TxCON<15>) = 1.

Note:

The OCxR register should be initialized

before the output compare module is first

enabled. The OCxR register becomes a

Read-Only Duty Cycle register when the

module is operated in the PWM modes.

The value held in OCxR will become the

PWM duty cycle for the first PWM period.

The contents of the Output Compare x

Secondary register, OCxRS, will not be

transferred into OCxR until a time base

period match occurs.

Some important boundary parameters of the PWM duty

cycle include:

• If the Output Compare x register, OCxR, is loaded

with 0000h, the OCx pin will remain low (0% duty

cycle).

• If OCxR is greater than PRy (Timer Period

register), the pin will remain high (100% duty

cycle).

• If OCxR is equal to PRy, the OCx pin will be low

for one time base count value and high for all

other count values.

14.3.1

PWM PERIOD

See Example 14-1 for PWM mode timing details.

Table 14-1 shows example PWM frequencies and

resolutions for a device operating at 10 MIPS.

The PWM period is specified by writing to PRy, the

Timer Period register. The PWM period can be

calculated using Equation 14-1.

EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION⁽¹⁾

FCY

log₁₀

(

)

FPWM • (Timer Prescale Value)

bits

Maximum PWM Resolution (bits) =

log₁₀(2)

Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.

DS39881D-page 136

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EXAMPLE 14-1:

PWM PERIOD AND DUTY CYCLE CALCULATIONS⁽¹⁾

1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL

(32 MHz device clock rate) and a Timer2 prescaler setting of 1:1.

TCY = 2 * Tosc = 62.5 ns

PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s

PWM Period = (PR2 + 1) • TCY • (Timer 2 Prescale Value)

19.2 s

PR2

= (PR2 + 1) • 62.5 ns • 1

= 306

2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:

PWM Resolution = log₁₀(FCY/FPWM)/log₁₀2) bits

= (log₁₀(16 MHz/52.08 kHz)/log₁₀2) bits

= 8.3 bits

Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled.

TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)⁽¹⁾

PWM Frequency

7.6 Hz

61 Hz

122 Hz

977 Hz

3.9 kHz

31.3 kHz

125 kHz

Timer Prescaler Ratio

Period Register Value

Resolution (bits)

8

1

FFFFh

16

1

007Fh

7

1

001Fh

5

FFFFh

16

7FFFh

15

0FFFh

12

03FFh

10

Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.

TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)⁽¹⁾

PWM Frequency

30.5 Hz

244 Hz

488 Hz

3.9 kHz

15.6 kHz

125 kHz

500 kHz

Timer Prescaler Ratio

Period Register Value

Resolution (bits)

8

1

FFFFh

16

1

007Fh

7

1

001Fh

5

FFFFh

16

7FFFh

15

0FFFh

12

03FFh

10

Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.

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FIGURE 14-1:

OUTPUT COMPARE MODULE BLOCK DIAGRAM

Set Flag bit

(1)

OCxIF

(1)

OCxRS

(1)

Output

Logic

(1)

S

R

Q

OCxR

OCx

Output Enable

3

OCM2:OCM0

Mode Select

(2)

(4)

Comparator

OCFA or OCFB

OCTSEL

0

1

0

1

16

Period match signals

from time bases

(see Note 3).

TMR register inputs

from time bases

(see Note 3).

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1

through 5.

2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel.

3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time

bases associated with the module.

4: This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please see Section 10.4

“Peripheral Pin Select” section for more information.

DS39881D-page 138

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14.4 Output Compare Register

REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

OCSIDL

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R-0, HC

OCFLT

R/W-0

OCM2⁽¹⁾

R/W-0

OCM1⁽¹⁾

R/W-0

OCM0⁽¹⁾

OCTSEL

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15-14

bit 13

Unimplemented: Read as ‘0’

OCSIDL: Stop Output Compare x in Idle Mode Control bit

1= Output Compare x will halt in CPU Idle mode

0= Output Compare x will continue to operate in CPU Idle mode

bit 12-5

bit 4

Unimplemented: Read as ‘0’

OCFLT: PWM Fault Condition Status bit

1= PWM Fault condition has occurred (cleared in HW only)

0= No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)

bit 3

OCTSEL: Output Compare x Timer Select bit

1= Timer3 is the clock source for Output Compare x

0= Timer2 is the clock source for Output Compare x

Refer to the device data sheet for specific time bases available to the output compare module.

bit 2-0

OCM2:OCM0: Output Compare x Mode Select bits⁽¹⁾

111= PWM mode on OCx, Fault pin, OCFx, enabled⁽²⁾

110= PWM mode on OCx, Fault pin, OCFx, disabled⁽²⁾

101= Initialize OCx pin low, generate continuous output pulses on OCx pin

100= Initialize OCx pin low, generate single output pulse on OCx pin

011= Compare event toggles OCx pin

010= Initialize OCx pin high, compare event forces OCx pin low

001= Initialize OCx pin low, compare event forces OCx pin high

000= Output compare channel is disabled

Note 1: RPORx (OCx) must be configured to an available RPn pin. For more information, see Section 10.4

“Peripheral Pin Select”.

2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel.

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NOTES:

DS39881D-page 140

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The SPI serial interface consists of four pins:

15.0 SERIAL PERIPHERAL

INTERFACE (SPI)

• SDIx: Serial Data Input

• SDOx: Serial Data Output

• SCKx: Shift Clock Input or Output

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

• SSx: Active-Low Slave Select or Frame

Synchronization I/O Pulse

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 23. Serial Peripheral Interface

(SPI)” (DS39699)

The SPI module can be configured to operate using 2,

3 or 4 pins. In the 3-pin mode, SSx is not used. In the

2-pin mode, both SDOx and SSx are not used.

Block diagrams of the module in Standard and

Enhanced modes are shown in Figure 15-1 and

Figure 15-2.

The Serial Peripheral Interface (SPI) module is a

synchronous serial interface useful for communicating

with other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift reg-

isters, display drivers, A/D Converters, etc. The SPI

module is compatible with Motorola’s SPI and SIOP

interfaces.

Depending on the pin count, devices of the

PIC24FJ64GA004 family offer one or two SPI modules

on a single device.

Note:

In this section, the SPI modules are

referred to together as SPIx or separately

as SPI1 and SPI2. Special Function Reg-

isters will follow a similar notation. For

example, SPIxCON1 or SPIxCON2 refers

to the control register for the SPI1 or SPI2

module.

The module supports operation in two buffer modes. In

Standard mode, data is shifted through a single serial

buffer. In Enhanced Buffer mode, data is shifted

through an 8-level FIFO buffer.

Note:

Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register in either Standard or

Enhanced Buffer mode.

The module also supports a basic framed SPI protocol

while operating in either Master or Slave mode. A total

of four framed SPI configurations are supported.

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To set up the SPI module for the Standard Master mode

of operation:

To set up the SPI module for the Standard Slave mode

of operation:

1. If using interrupts:

1. Clear the SPIxBUF register.

2. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSx

register.

a) Clear the SPIxIF bit in the respective IFSx

register.

b) Set the SPIxIE bit in the respective IECx

register.

b) Set the SPIxIE bit in the respective IECx

register.

c) Write the SPIxIP bits in the respective IPCx

register to set the interrupt priority.

c) Write the SPIxIP bits in the respective IPCx

register to set the interrupt priority.

2. Write the desired settings to the SPIxCON1 and

SPIxCON2

(SPIxCON1<5>) = 1.

3. Clear the SPIROV bit (SPIxSTAT<6>).

registers

with

MSTEN

3. Write the desired settings to the SPIxCON1

and SPIxCON2 registers with MSTEN

(SPIxCON1<5>) = 0.

4. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

4. Clear the SMP bit.

5. If the CKE bit is set, then the SSEN bit

(SPIxCON1<7>) must be set to enable the SSx

pin.

5. Write the data to be transmitted to the SPIxBUF

register. Transmission (and reception) will start

as soon as data is written to the SPIxBUF

register.

6. Clear the SPIROV bit (SPIxSTAT<6>).

7. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

FIGURE 15-1:

SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)

SCKx

1:1 to 1:8

Secondary

Prescaler

1:1/4/16/64

Primary

Prescaler

FCY

SSx/FSYNCx

Sync

Control

Select

Edge

Control

Clock

SPIxCON1<1:0>

SPIxCON1<4:2>

Control

Shift

SDOx

SDIx

Enable

Master Clock

bit 0

SPIxSR

Transfer

SPIxBUF

Write SPIxBUF

Read SPIxBUF

16

Internal Data Bus

DS39881D-page 142

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To set up the SPI module for the Enhanced Buffer

Master mode of operation:

To set up the SPI module for the Enhanced Buffer

Slave mode of operation:

1. If using interrupts:

1. Clear the SPIxBUF register.

2. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSx

register.

• Clear the SPIxIF bit in the respective IFSx

register.

b) Set the SPIxIE bit in the respective IECx

register.

• Set the SPIxIE bit in the respective IECx

register.

c) Write the SPIxIP bits in the respective IPCx

register.

• Write the SPIxIP bits in the respective IPCx

register to set the interrupt priority.

2. Write the desired settings to the SPIxCON1 and

SPIxCON2

(SPIxCON1<5>) = 1.

3. Clear the SPIROV bit (SPIxSTAT<6>).

registers

with

MSTEN

3. Write the desired settings to the SPIxCON1 and

SPIxCON2

registers

with

MSTEN

(SPIxCON1<5>) = 0.

4. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

4. Clear the SMP bit.

5. If the CKE bit is set, then the SSEN bit must be

set, thus enabling the SSx pin.

5. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

6. Clear the SPIROV bit (SPIxSTAT<6>).

6. Write the data to be transmitted to the SPIxBUF

register. Transmission (and reception) will start

as soon as data is written to the SPIxBUF

register.

7. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

8. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

FIGURE 15-2:

SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)

SCKx

1:1/4/16/64

Primary

Prescaler

1:1 to 1:8

Secondary

Prescaler

FCY

SSx/FSYNCx

Sync

Control

Select

Edge

Control

Clock

SPIxCON1<1:0>

SPIxCON1<4:2>

Control

Shift

SDOx

SDIx

Enable

Master Clock

bit0

SPIxSR

Transfer

8-Level FIFO

Receive Buffer

8-Level FIFO

Transmit Buffer

SPIxBUF

Write SPIxBUF

Read SPIxBUF

16

Internal Data Bus

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REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

R/W-0

SPIEN⁽¹⁾

U-0

—

R/W-0

U-0

—

U-0

—

R-0

SPISIDL

SPIBEC2

SPIBEC1

SPIBEC0

bit 15

bit 8

R-0

R/C-0

R/W-0

R-0

SRMPT

SPIROV

SRXMPT

SISEL2

SISEL1

SISEL0

SPITBF

SPIRBF

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

SPIEN: SPIx Enable bit⁽¹⁾

1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0= Disables module

bit 14

bit 13

Unimplemented: Read as ‘0’

SPISIDL: Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-11

bit 10-8

Unimplemented: Read as ‘0’

SPIBEC2:SPIBEC0: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)

Master mode:

Number of SPI transfers pending.

Slave mode:

Number of SPI transfers unread.

bit 7

bit 6

SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)

1= SPIx Shift register is empty and ready to send or receive

0= SPIx Shift register is not empty

SPIROV: Receive Overflow Flag bit

1= A new byte/word is completely received and discarded. The user software has not read the previous

data in the SPIxBUF register.

0= No overflow has occurred

bit 5

SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)

1= Receive FIFO is empty

0= Receive FIFO is not empty

bit 4-2

SISEL2:SISEL0: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)

111= Interrupt when SPIx transmit buffer is full (SPITBF bit is set)

110= Interrupt when last bit is shifted into SPIxSR; as a result, the TX FIFO is empty

101= Interrupt when the last bit is shifted out of SPIxSR; now the transmit is complete

100= Interrupt when one data is shifted into the SPIxSR; as a result, the TX FIFO has one open spot

011= Interrupt when SPIx receive buffer is full (SPIRBF bit set)

010= Interrupt when SPIx receive buffer is 3/4 or more full

001= Interrupt when data is available in receive buffer (SRMPT bit is set)

000= Interrupt when the last data in the receive buffer is read; as a result, the buffer is empty

(SRXMPT bit is set)

Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4

“Peripheral Pin Select” for more information.

DS39881D-page 144

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REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)

bit 1

SPITBF: SPIx Transmit Buffer Full Status bit

1= Transmit not yet started, SPIxTXB is full

0= Transmit started, SPIxTXB is empty

In Standard Buffer mode:

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.

In Enhanced Buffer mode:

Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location.

Automatically cleared in hardware when a buffer location is available for a CPU write.

bit 0

SPIRBF: SPIx Receive Buffer Full Status bit

1= Receive complete, SPIxRXB is full

0= Receive is not complete, SPIxRXB is empty

In Standard Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.

In Enhanced Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread

buffer location.

Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.

Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4

“Peripheral Pin Select” for more information.

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REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0

DISSCK⁽¹⁾

R/W-0

DISSDO⁽²⁾

R/W-0

SMP

R/W-0

CKE⁽³⁾

MODE16

bit 15

bit 8

R/W-0

SSEN⁽⁴⁾

R/W-0

CKP

R/W-0

MSTEN

SPRE2

SPRE1

SPRE0

PPRE1

PPRE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

DISSCK: Disables SCKx pin bit (SPI Master modes only)⁽¹⁾

1= Internal SPI clock is disabled; pin functions as I/O

0= Internal SPI clock is enabled

bit 11

bit 10

bit 9

DISSDO: Disables SDOx pin bit⁽²⁾

1= SDOx pin is not used by module; pin functions as I/O

0= SDOx pin is controlled by the module

MODE16: Word/Byte Communication Select bit

1= Communication is word-wide (16 bits)

0= Communication is byte-wide (8 bits)

SMP: SPIx Data Input Sample Phase bit

Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8

bit 7

bit 6

bit 5

CKE: SPIx Clock Edge Select bit⁽³⁾

1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

SSEN: Slave Select Enable bit (Slave mode)⁽⁴⁾

1= SSx pin used for Slave mode

0= SSx pin not used by module; pin controlled by port function

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level; active state is a low level

0= Idle state for clock is a low level; active state is a high level

MSTEN: Master Mode Enable bit

1= Master mode

0= Slave mode

Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin

Select” for more information.

2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin

Select” for more information.

3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select”

for more information.

DS39881D-page 146

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REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)

bit 4-2

SPRE2:SPRE0: Secondary Prescale bits (Master mode)

111= Secondary prescale 1:1

110= Secondary prescale 2:1

...

000= Secondary prescale 8:1

bit 1-0

PPRE1:PPRE0: Primary Prescale bits (Master mode)

11= Primary prescale 1:1

10= Primary prescale 4:1

01= Primary prescale 16:1

00= Primary prescale 64:1

Note 1: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin

Select” for more information.

2: If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin

Select” for more information.

3: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

4: If SSEN = 1, SSx must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select”

for more information.

REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

FRMEN

SPIFSD

SPIFPOL

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SPIFE

R/W-0

SPIBEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

FRMEN: Framed SPIx Support bit

1= Framed SPIx support enabled

0= Framed SPIx support disabled

SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit

1= Frame sync pulse input (slave)

0= Frame sync pulse output (master)

SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)

1= Frame sync pulse is active-high

0= Frame sync pulse is active-low

bit 12-2

bit 1

Unimplemented: Read as ‘0’

SPIFE: Frame Sync Pulse Edge Select bit

1= Frame sync pulse coincides with first bit clock

0= Frame sync pulse precedes first bit clock

bit 0

SPIBEN: Enhanced Buffer Enable bit

1= Enhanced Buffer enabled

0= Enhanced Buffer disabled (Legacy mode)

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FIGURE 15-3:

SPI MASTER/SLAVE CONNECTION (STANDARD MODE)

PROCESSOR 1 (SPI Master)

PROCESSOR 2 (SPI Slave)

SDOx

SDIx

Serial Receive Buffer

(SPIxRXB)⁽²⁾

Serial Receive Buffer

(SPIxRXB)⁽²⁾

SDIx

SDOx

Shift Register

(SPIxSR)

Shift Register

(SPIxSR)

LSb

MSb

LSb

Serial Transmit Buffer

(SPIxTXB)⁽²⁾

Serial Clock

SCKx

SSx⁽¹⁾

SCKx

SPIx Buffer

(SPIxBUF)⁽²⁾

SSEN (SPIxCON1<7>) = 1and MSTEN (SPIxCON1<5>) = 0

MSTEN (SPIxCON1<5>) = 1)

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

FIGURE 15-4:

SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)

PROCESSOR 1 (SPI Enhanced Buffer Master)

PROCESSOR 2 (SPI Enhanced Buffer Slave)

SDOx

SDIx

SDOx

Shift Register

(SPIxSR)

Shift Register

(SPIxSR)

LSb

MSb

LSb

8-Level FIFO Buffer

Serial Clock

SPIx Buffer

SCKx

SSx

SCKx

SSx⁽¹⁾

(SPIxBUF)⁽²⁾

MSTEN (SPIxCON1<5>) = 1and

SPIBEN (SPIxCON2<0>) = 1

SSEN (SPIxCON1<7>) = 1,

MSTEN (SPIxCON1<5>) = 0and

SPIBEN (SPIxCON2<0>) = 1

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

DS39881D-page 148

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FIGURE 15-5:

FIGURE 15-6:

FIGURE 15-7:

FIGURE 15-8:

SPI MASTER, FRAME MASTER CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

(SPI Slave, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

SPI Master, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

(SPI Slave, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync.

Pulse

SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM

PIC24F

PROCESSOR 2

(SPI Master, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

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EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED⁽¹⁾

FCY

FSCK =

Primary Prescaler * Secondary Prescaler

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

TABLE 15-1: SAMPLE SCK FREQUENCIES^(1,2)

Secondary Prescaler Settings

FCY = 16 MHz

1:1

2:1

4:1

6:1

8:1

Primary Prescaler Settings

1:1

4:1

Invalid

4000

1000

250

8000

2000

500

4000

1000

250

63

2667

667

167

42

2000

500

125

31

16:1

64:1

125

FCY = 5 MHz

Primary Prescaler Settings

1:1

4:1

5000

1250

313

78

2500

625

156

39

1250

313

78

833

208

52

625

156

39

16:1

64:1

20

13

10

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

2: SCKx frequencies shown in kHz.

DS39881D-page 150

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16.2 Communicating as a Master in a

Single Master Environment

16.0 INTER-INTEGRATED CIRCUIT

2

(I C™)

The details of sending a message in Master mode

Note:

This data sheet summarizes the features

depends on the communications protocol for the device

being communicated with. Typically, the sequence of

events is as follows:

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 24. Inter-Integrated Circuit

(I²C™)” (DS39702).

1. Assert a Start condition on SDAx and SCLx.

2. Send the I²C device address byte to the slave

with a write indication.

The Inter-Integrated Circuit™ (I²C™) module is a serial

interface useful for communicating with other periph-

eral or microcontroller devices. These peripheral

devices may be serial EEPROMs, display drivers, A/D

Converters, etc.

3. Wait for and verify an Acknowledge from the

slave.

4. Send the first data byte (sometimes known as

the command) to the slave.

5. Wait for and verify an Acknowledge from the

slave.

The I²C module supports these features:

6. Send the serial memory address low byte to the

slave.

• Independent master and slave logic

• 7-bit and 10-bit device addresses

• General call address, as defined in the I²C protocol

7. Repeat steps 4 and 5 until all data bytes are

sent.

• Clock stretching to provide delays for the

processor to respond to a slave data request

8. Assert a Repeated Start condition on SDAx and

SCLx.

• Both 100 kHz and 400 kHz bus specifications.

• Configurable address masking

9. Send the device address byte to the slave with

a read indication.

• Multi-Master modes to prevent loss of messages

in arbitration

10. Wait for and verify an Acknowledge from the

slave.

• Bus Repeater mode, allowing the acceptance of

all messages as a slave regardless of the address

11. Enable master reception to receive serial

memory data.

• Automatic SCL

12. Generate an ACK or NACK condition at the end

of a received byte of data.

A block diagram of the module is shown in Figure 16-1.

13. Generate a Stop condition on SDAx and SCLx.

16.1 Peripheral Remapping Options

The I²C modules are tied to fixed pin assignments, and

cannot be reassigned to alternate pins using peripheral

pin select. To allow some flexibility with peripheral

multiplexing, the I2C1 module in all devices, can be

reassigned to the alternate pins, designated as ASCL1

and ASDA1 during device configuration.

Pin assignment is controlled by the I2C1SEL Configu-

ration bit; programming this bit (= 0) multiplexes the

module to the ASCL1 and ASDA1 pins.

 2010 Microchip Technology Inc.

DS39881D-page 151

PIC24FJ64GA004 FAMILY

FIGURE 16-1:

I²C™ BLOCK DIAGRAM

Internal

Data Bus

I2CxRCV

Read

Shift

Clock

SCLx

SDAx

I2CxRSR

LSB

Address Match

Write

Read

Match Detect

I2CxMSK

Write

Read

I2CxADD

Start and Stop

Bit Detect

Write

Start and Stop

Bit Generation

I2CxSTAT

I2CxCON

Read

Write

Collision

Detect

Acknowledge

Generation

Read

Clock

Stretching

Write

Read

I2CxTRN

LSB

Shift Clock

Reload

Control

Write

Read

BRG Down Counter

TCY/2

I2CxBRG

DS39881D-page 152

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16.3 Setting Baud Rate When

Operating as a Bus Master

16.4 Slave Address Masking

The I2CxMSK register (Register 16-3) designates

address bit positions as “don’t care” for both 7-Bit and

10-Bit Addressing modes. Setting a particular bit loca-

tion (= 1) in the I2CxMSK register causes the slave

module to respond whether the corresponding address

bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK

is set to ‘00100000’, the slave module will detect both

addresses, ‘0000000’ and ‘00100000’.

To compute the Baud Rate Generator reload value, use

Equation 16-1.

EQUATION 16-1: COMPUTING BAUD RATE

RELOAD VALUE⁽¹⁾

FCY

FSCL =

---------------------------------------------------------------------

To enable address masking, the IPMI (Intelligent

Peripheral Management Interface) must be disabled by

clearing the IPMIEN bit (I2CxCON<11>).

FCY

I2CxBRG + 1 +

-----------------------------

10 000 000

or

Note:

As a result of changes in the I²C™ proto-

col, the addresses in Table 16-2 are

reserved and will not be Acknowledged in

Slave mode. This includes any address

mask settings that include any of these

addresses.

FCY









I2CxBRG =

–

– 1

----------- -----------------------------

FSCL 10 000 000

Note 1: Based on FCY = FOSC/2; Doze mode and

PLL are disabled.

TABLE 16-1: I²C™ CLOCK RATES⁽¹⁾

Required

I2CxBRG Value

Actual

FSCL

System

FSCL

FCY

(Decimal)

(Hexadecimal)

100 kHz

400 kHz

1 MHz

16 MHz

8 MHz

4 MHz

16 MHz

8 MHz

4 MHz

2 MHz

16 MHz

8 MHz

4 MHz

157

78

39

37

18

9

9D

4E

27

25

12

9

100 kHz

99 kHz

404 kHz

385 kHz

1.026 MHz

0.909 MHz

4

13

6

D

1 MHz

6

1 MHz

3

Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.

TABLE 16-2: I²C™ RESERVED ADDRESSES⁽¹⁾

Slave

Address

R/W

Bit

Description

0000 000

0000 001

0000 010

0000 011

0000 1xx

1111 1xx

1111 0xx

0

1

x

General Call Address⁽²⁾

Start Byte

Cbus Address

Reserved

HS Mode Master Code

Reserved

10-Bit Slave Upper Byte⁽³⁾

Note 1: The address bits listed here will never cause an address match, independent of the address mask settings.

2: Address will be Acknowledged only if GCEN = 1.

3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode.

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REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER

R/W-0

I2CEN

U-0

—

R/W-0

R/W-1 HC

SCLREL

R/W-0

A10M

R/W-0

SMEN

I2CSIDL

IPMIEN

DISSLW

bit 15

bit 8

R/W-0

GCEN

R/W-0

R/W-0, HC

ACKEN

R/W-0, HC

RCEN

R/W-0, HC

PEN

R/W-0, HC

RSEN

R/W-0, HC

SEN

STREN

ACKDT

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

I2CEN: I2Cx Enable bit

1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0= Disables I2Cx module. All I²C™ pins are controlled by port functions.

bit 14

bit 13

Unimplemented: Read as ‘0’

I2CSIDL: Stop in Idle Mode bit

1= Discontinues module operation when device enters an Idle mode

0= Continues module operation in Idle mode

bit 12

SCLREL: SCLx Release Control bit (when operating as I²C Slave)

1= Releases SCLx clock

0= Holds SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at

beginning of slave transmission. Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave transmission.

bit 11

bit 10

bit 9

IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit

1= IPMI Support mode is enabled; all addresses Acknowledged

0= IPMI mode is disabled

A10M: 10-Bit Slave Addressing bit

1= I2CxADD is a 10-bit slave address

0= I2CxADD is a 7-bit slave address

DISSLW: Disable Slew Rate Control bit

1= Slew rate control disabled

0= Slew rate control enabled

bit 8

SMEN: SMBus Input Levels bit

1= Enables I/O pin thresholds compliant with SMBus specification

0= Disables SMBus input thresholds

bit 7

GCEN: General Call Enable bit (when operating as I²C slave)

1= Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for

reception)

0= General call address disabled

bit 6

STREN: SCLx Clock Stretch Enable bit (when operating as I²C slave)

Used in conjunction with SCLREL bit.

1= Enables software or receive clock stretching

0= Disables software or receive clock stretching

DS39881D-page 154

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REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)

bit 5

ACKDT: Acknowledge Data bit (When operating as I²C master. Applicable during master receive.)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1= Sends NACK during Acknowledge

0= Sends ACK during Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit (When operating as I²C master. Applicable during master

receive.)

1= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware

clear at end of master Acknowledge sequence.

0= Acknowledge sequence not in progress

bit 3

bit 2

bit 1

RCEN: Receive Enable bit (when operating as I²C master)

1= Enables Receive mode for I²C. Hardware clear at end of eighth bit of master receive data byte.

0= Receives sequence not in progress

PEN: Stop Condition Enable bit (when operating as I²C master)

1= Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

0= Stop condition not in progress

RSEN: Repeated Start Condition Enabled bit (when operating as I²C master)

1= Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master

Repeated Start sequence.

0= Repeated Start condition not in progress

bit 0

SEN: Start Condition Enabled bit (when operating as I²C master)

1= Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

0= Start condition not in progress

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DS39881D-page 155

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REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER

R-0, HSC

ACKSTAT

R-0, HSC

TRSTAT

U-0

—

U-0

—

U-0

—

R/C-0, HS

BCL

R-0, HSC

GCSTAT

R-0, HSC

ADD10

bit 15

bit 8

R/C-0, HS

IWCOL

R/C-0, HS

I2COV

R-0, HSC R/C-0, HSC R/C-0, HSC

R-0, HSC

R/W

R-0, HSC

RBF

R-0, HSC

TBF

D/A

P

S

bit 7

bit 0

Legend:

C = Clearable bit

HS = Hardware Settable bit

HSC = Hardware Settable,

Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ACKSTAT: Acknowledge Status bit

1= NACK was detected last

0= ACK was detected last

Hardware set or clear at end of Acknowledge.

bit 14

TRSTAT: Transmit Status bit

(When operating as I²C™ master. Applicable to master transmit operation.)

1= Master transmit is in progress (8 bits + ACK)

0= Master transmit is not in progress

Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.

bit 13-11

bit 10

Unimplemented: Read as ‘0’

BCL: Master Bus Collision Detect bit

1= A bus collision has been detected during a master operation

0= No collision

Hardware set at detection of bus collision.

bit 9

bit 8

bit 7

bit 6

bit 5

GCSTAT: General Call Status bit

1= General call address was received

0= General call address was not received

Hardware set when address matches general call address. Hardware clear at Stop detection.

ADD10: 10-Bit Address Status bit

1= 10-bit address was matched

0= 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.

IWCOL: Write Collision Detect bit

1= An attempt to write the I2CxTRN register failed because the I²C module is busy

0= No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

I2COV: Receive Overflow Flag bit

1= A byte was received while the I2CxRCV register is still holding the previous byte

0= No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

D/A: Data/Address bit (when operating as I²C slave)

1= Indicates that the last byte received was data

0= Indicates that the last byte received was device address

Hardware clear at device address match. Hardware set by write to I2CxTRN or by reception of slave byte.

DS39881D-page 156

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REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)

bit 4

bit 3

bit 2

bit 1

bit 0

P: Stop bit

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

S: Start bit

1= Indicates that a Start (or Repeated Start) bit has been detected last

0= Start bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

R/W: Read/Write Information bit (when operating as I²C slave)

1= Read – indicates data transfer is output from slave

0= Write – indicates data transfer is input to slave

Hardware set or clear after reception of I²C device address byte.

RBF: Receive Buffer Full Status bit

1= Receive complete, I2CxRCV is full

0= Receive not complete, I2CxRCV is empty

Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV.

TBF: Transmit Buffer Full Status bit

1= Transmit in progress, I2CxTRN is full

0= Transmit complete, I2CxTRN is empty

Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

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DS39881D-page 157

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REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

AMSK9

AMSK8

bit 15

bit 8

R/W-0

AMSK7

AMSK6

AMSK5

AMSK4

AMSK3

AMSK2

AMSK1

AMSK0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

AMSK9:AMSK0: Mask for Address Bit x Select bits

1= Enable masking for bit x of incoming message address; bit match not required in this position

0= Disable masking for bit x; bit match required in this position

16.5 Acknowledge Status

In both Master and Slave modes, the ACKSTAT bit is

only updated when transmitting data resulting in the

reception of an ACK or NACK from another device. Do

not check the state of ACKSTAT when receiving data,

either as a Slave or a Master. Reading ACKSTAT after

receiving address or data bytes returns an invalid

result.

DS39881D-page 158

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• Fully Integrated Baud Rate Generator with 16-Bit

Prescaler

17.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

• Baud Rates Ranging from 1 Mbps to 15 bps at

16 MIPS

• 4-Deep, First-In-First-Out (FIFO) Transmit Data

Buffer

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 21. UART” (DS39708).

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules available

in the PIC24F device family. The UART is a full-duplex

asynchronous system that can communicate with

peripheral devices, such as personal computers, LIN,

RS-232 and RS-485 interfaces. The module also sup-

ports a hardware flow control option with the UxCTS and

UxRTS pins and also includes an IrDA^®encoder and

decoder.

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UART is shown in

Figure 17-1. The UART module consists of these key

important hardware elements:

The primary features of the UART module are:

• Baud Rate Generator

• Full-Duplex, 8 or 9-Bit Data Transmission through

the UxTX and UxRX Pins

• Asynchronous Transmitter

• Asynchronous Receiver

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Hardware Flow Control Option with UxCTS and

UxRTS Pins

FIGURE 17-1:

UART SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA^®

BCLKx

Hardware Flow Control

UARTx Receiver

UxRTS

UxCTS

UxRX

UARTx Transmitter

UxTX

Note:

This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please

see Section 10.4 “Peripheral Pin Select” for more information.

 2010 Microchip Technology Inc.

DS39881D-page 159

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The maximum baud rate (BRGH = 0) possible is

FCY/16 (for UxBRG = 0) and the minimum baud rate

17.1 UART Baud Rate Generator (BRG)

The UART module includes a dedicated 16-bit Baud

Rate Generator. The UxBRG register controls the

period of a free-running, 16-bit timer. Equation 17-1

shows the formula for computation of the baud rate

with BRGH = 0.

possible is FCY/(16 * 65536).

Equation 17-2 shows the formula for computation of

the baud rate with BRGH = 1.

EQUATION 17-2: UART BAUD RATE WITH

BRGH = 1⁽¹⁾

EQUATION 17-1: UART BAUD RATE WITH

BRGH = 0⁽¹⁾

FCY

Baud Rate =

4 • (UxBRG + 1)

FCY

Baud Rate =

16 • (UxBRG + 1)

FCY

– 1

UxBRG =

4 • Baud Rate

FCY

16 • Baud Rate

– 1

UxBRG =

Note 1: Based on FCY = FOSC/2, Doze mode

and PLL are disabled.

Note 1: Based on FCY = FOSC/2, Doze mode

and PLL are disabled.

The maximum baud rate (BRGH = 1) possible is FCY/4

(for UxBRG = 0) and the minimum baud rate possible

is FCY/(4 * 65536).

Example 17-1 shows the calculation of the baud rate

error for the following conditions:

Writing a new value to the UxBRG register causes the

BRG timer to be reset (cleared). This ensures the BRG

does not wait for a timer overflow before generating the

new baud rate.

• FCY = 4 MHz

• Desired Baud Rate = 9600

EXAMPLE 17-1:

BAUD RATE ERROR CALCULATION (BRGH = 0)⁽¹⁾

Desired Baud Rate = FCY/(16 (UxBRG + 1))

Solving for UxBRG value:

UxBRG

= ((FCY/Desired Baud Rate)/16) – 1

= ((4000000/9600)/16) – 1

= 25

Calculated Baud Rate= 4000000/(16 (25 + 1))

= 9615

Error

= (Calculated Baud Rate – Desired Baud Rate)

Desired Baud Rate

= (9615 – 9600)/9600

= 0.16%

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

DS39881D-page 160

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17.2 Transmitting in 8-Bit Data Mode

17.5 Receiving in 8-Bit or 9-Bit Data

Mode

1. Set up the UART:

a) Write appropriate values for data, parity and

Stop bits.

1. Set up the UART (as described in Section 17.2

“Transmitting in 8-Bit Data Mode”).

b) Write appropriate baud rate value to the

UxBRG register.

2. Enable the UART.

3. A receive interrupt will be generated when one

or more data characters have been received as

per interrupt control bit, URXISELx.

c) Set up transmit and receive interrupt enable

and priority bits.

2. Enable the UART.

4. Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

3. Set the UTXEN bit (causes a transmit interrupt

2 cycles after being set).

5. Read UxRXREG.

4. Write data byte to lower byte of UxTXREG word.

The value will be immediately transferred to the

Transmit Shift Register (TSR), and the serial bit

stream will start shifting out with next rising edge

of the baud clock.

The act of reading the UxRXREG character will move

the next character to the top of the receive FIFO,

including a new set of PERR and FERR values.

5. Alternately, the data byte may be transferred

while UTXEN = 0, and then the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

17.6 Operation of UxCTS and UxRTS

Control Pins

UARTx Clear to Send (UxCTS) and Request to Send

(UxRTS) are the two hardware controlled pins that are

associated with the UART module. These two pins

allow the UART to operate in Simplex and Flow Control

mode. They are implemented to control the transmis-

sion and reception between the Data Terminal

Equipment (DTE). The UEN<1:0> bits in the UxMODE

register configure these pins.

6. A transmit interrupt will be generated as per

interrupt control bit, UTXISELx.

17.3 Transmitting in 9-Bit Data Mode

1. Set up the UART (as described in Section 17.2

“Transmitting in 8-Bit Data Mode”).

2. Enable the UART.

17.7 Infrared Support

3. Set the UTXEN bit (causes a transmit interrupt

2 cycles after being set).

The UART module provides two types of infrared UART

support: one is the IrDA clock output to support exter-

nal IrDA encoder and decoder device (legacy module

support), and the other is the full implementation of the

IrDA encoder and decoder. Note that because the IrDA

modes require a 16x baud clock, they will only work

when the BRGH bit (UxMODE<3>) is ‘0’.

4. Write UxTXREG as a 16-bit value only.

5. A word write to UxTXREG triggers the transfer

of the 9-bit data to the TSR. Serial bit stream will

start shifting out with the first rising edge of the

baud clock.

6. A transmit interrupt will be generated as per the

setting of control bit, UTXISELx.

17.7.1

EXTERNAL IrDA SUPPORT – IrDA

CLOCK OUTPUT

17.4 Break and Sync Transmit

Sequence

To support external IrDA encoder and decoder devices,

the BCLKx pin (same as the UxRTS pin) can be

configured to generate the 16x baud clock. With

UEN<1:0> = 11, the BCLKx pin will output the 16x

baud clock if the UART module is enabled. It can be

used to support the IrDA codec chip.

The following sequence will send a message frame

header made up of a Break, followed by an auto-baud

Sync byte.

1. Configure the UART for the desired mode.

17.7.2

BUILT-IN IrDA ENCODER AND

DECODER

2. Set UTXEN and UTXBRK – sets up the Break

character.

The UART has full implementation of the IrDA encoder

and decoder as part of the UART module. The built-in

IrDA encoder and decoder functionality is enabled

using the IREN bit (UxMODE<12>). When enabled

(IREN = 1), the receive pin (UxRX) acts as the input

from the infrared receiver. The transmit pin (UxTX) acts

as the output to the infrared transmitter.

3. Load the UxTXREG with a dummy character to

initiate transmission (value is ignored).

4. Write ‘55h’ to UxTXREG – loads the Sync

character into the transmit FIFO.

5. After the Break has been sent, the UTXBRK bit

is reset by hardware. The Sync character now

transmits.

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DS39881D-page 161

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REGISTER 17-1: UxMODE: UARTx MODE REGISTER

R/W-0

UARTEN⁽¹⁾

bit 15

U-0

—

R/W-0

USIDL

R/W-0

IREN⁽²⁾

R/W-0

U-0

—

R/W-0⁽³⁾

UEN1

R/W-0⁽³⁾

UEN0

RTSMD

bit 8

R/C-0, HC

WAKE

R/W-0

R/W-0, HC

ABAUD

R/W-0

RXINV

R/W-0

BRGH

R/W-0

LPBACK

PDSEL1

PDSEL0

STSEL

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HC = Hardware Clearable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 15

UARTEN: UARTx Enable bit⁽¹⁾

1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0= UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is

minimal

bit 14

bit 13

Unimplemented: Read as ‘0’

USIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12

bit 11

IREN: IrDA^®Encoder and Decoder Enable bit⁽²⁾

1= IrDA encoder and decoder enabled

0= IrDA encoder and decoder disabled

RTSMD: Mode Selection for UxRTS Pin bit

1= UxRTS pin in Simplex mode

0= UxRTS pin in Flow Control mode

bit 10

Unimplemented: Read as ‘0’

bit 9-8

UEN1:UEN0: UARTx Enable bits⁽³⁾

11= UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches

10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches

00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT

latches

bit 7

WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit

1= UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in

hardware on following rising edge

0= No wake-up enabled

bit 6

bit 5

LPBACK: UARTx Loopback Mode Select bit

1= Enable Loopback mode

0= Loopback mode is disabled

ABAUD: Auto-Baud Enable bit

1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h);

cleared in hardware upon completion

0= Baud rate measurement disabled or completed

Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select” for more information.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

3: Bit availability depends on pin availability.

DS39881D-page 162

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PIC24FJ64GA004 FAMILY

REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 4

RXINV: Receive Polarity Inversion bit

1= UxRX Idle state is ‘0’

0= UxRX Idle state is ‘1’

bit 3

BRGH: High Baud Rate Enable bit

1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)

0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)

bit 2-1

PDSEL1:PDSEL0: Parity and Data Selection bits

11= 9-bit data, no parity

10= 8-bit data, odd parity

01= 8-bit data, even parity

00= 8-bit data, no parity

bit 0

STSEL: Stop Bit Selection bit

1= Two Stop bits

0= One Stop bit

Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select” for more information.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

3: Bit availability depends on pin availability.

 2010 Microchip Technology Inc.

DS39881D-page 163

PIC24FJ64GA004 FAMILY

REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0

UTXISEL1

bit 15

R/W-0

U-0

—

R/W-0, HC

UTXBRK

R/W-0

UTXEN⁽¹⁾

R-0

R-1

UTXINV

UTXISEL0

UTXBF

TRMT

bit 8

R/W-0

URXISEL1

bit 7

R/W-0

R-1

R-0

R/C-0

R-0

URXISEL0

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HC = Hardware Clearable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 15,13

UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits

11= Reserved; do not use

10= Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the

transmit buffer becomes empty

01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operations are completed

00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at

least one character open in the transmit buffer)

bit 14

UTXINV: IrDA^®Encoder Transmit Polarity Inversion bit

If IREN = 0:

1= UxTX Idle ‘0’

0= UxTX Idle ‘1’

If IREN = 1:

1= UxTX Idle ‘1’

0= UxTX Idle ‘0’

bit 12

bit 11

Unimplemented: Read as ‘0’

UTXBRK: Transmit Break bit

1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

0= Sync Break transmission disabled or completed

bit 10

UTXEN: Transmit Enable bit⁽¹⁾

1= Transmit enabled, UxTX pin controlled by UARTx

0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by

the PORT register.

bit 9

UTXBF: Transmit Buffer Full Status bit (read-only)

1= Transmit buffer is full

0= Transmit buffer is not full, at least one more character can be written

bit 8

TRMT: Transmit Shift Register Empty bit (read-only)

1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

0= Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6

URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits

11= Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)

10= Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)

0x= Interrupt is set when any character is received and transferred from the RSR to the receive buffer.

Receive buffer has one or more characters.

Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select” for more information.

DS39881D-page 164

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PIC24FJ64GA004 FAMILY

REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

bit 5

bit 4

bit 3

bit 2

bit 1

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.

0= Address Detect mode disabled

RIDLE: Receiver Idle bit (read-only)

1= Receiver is Idle

0= Receiver is active

PERR: Parity Error Status bit (read-only)

1= Parity error has been detected for the current character (character at the top of the receive FIFO)

0= Parity error has not been detected

FERR: Framing Error Status bit (read-only)

1= Framing error has been detected for the current character (character at the top of the receive FIFO)

0= Framing error has not been detected

OERR: Receive Buffer Overrun Error Status bit (clear/read-only)

1= Receive buffer has overflowed

0= Receive buffer has not overflowed (clearing a previously set OERR bit (1 0transition) will reset

the receiver buffer and the RSR to the empty state)

bit 0

URXDA: Receive Buffer Data Available bit (read-only)

1= Receive buffer has data; at least one more character can be read

0= Receive buffer is empty

Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select” for more information.

 2010 Microchip Technology Inc.

DS39881D-page 165

PIC24FJ64GA004 FAMILY

REGISTER 17-3: UxTXREG: UARTx TRANSMIT REGISTER

U-x

—

U-x

—

U-x

—

U-x

—

U-x

—

U-x

—

U-x

—

W-x

UTX8

bit 15

bit 8

W-x

UTX7

UTX6

UTX5

UTX4

UTX3

UTX2

UTX1

UTX0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

UTX8: Data of the Transmitted Character bit (in 9-bit mode)

UTX7:UTX0: Data of the Transmitted Character bits

bit 7-0

REGISTER 17-4: UxRXREG: UARTx RECEIVE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0

URX8

bit 15

bit 8

R-0

URX7

URX6

URX5

URX4

URX3

URX2

URX1

URX0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

URX8: Data of the Received Character bit (in 9-bit mode)

URX7:URX0: Data of the Received Character bits

bit 7-0

DS39881D-page 166

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Key features of the PMP module include:

18.0 PARALLEL MASTER PORT

(PMP)

• Up to 16 Programmable Address Lines

• One Chip Select Line

Note:

This data sheet summarizes the features

• Programmable Strobe Options:

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 13. Parallel Master Port

(PMP)” (DS39713).

- Individual Read and Write Strobes or;

- Read/Write Strobe with Enable Strobe

• Address Auto-Increment/Auto-Decrement

• Programmable Address/Data Multiplexing

• Programmable Polarity on Control Signals

• Legacy Parallel Slave Port Support

• Enhanced Parallel Slave Support:

- Address Support

The Parallel Master Port (PMP) module is a parallel

8-bit I/O module, specifically designed to communicate

with a wide variety of parallel devices, such as commu-

nication peripherals, LCDs, external memory devices

and microcontrollers. Because the interface to parallel

peripherals varies significantly, the PMP is highly

configurable.

- 4-Byte Deep Auto-Incrementing Buffer

• Programmable Wait States

• Selectable Input Voltage Levels

Note:

A number of the pins for the PMP are not

present on PIC24FJ64GA004 devices.

Refer to the specific device’s pinout to

determine which pins are available.

FIGURE 18-1:

PMP MODULE OVERVIEW

Address Bus

Data Bus

Control Lines

PMA<0>

PMALL

PIC24F

Parallel Master Port

PMA<1>

PMALH

Up to 11-Bit Address

(1)

PMA<10:2>

PMCS1

EEPROM

PMBE

PMRD

PMRD/PMWR

FIFO

Buffer

Microcontroller

LCD

PMWR

PMENB

PMD<7:0>

PMA<7:0>

PMA<15:8>

8-Bit Data

Note 1: PMA<10:2> are not available on 28-pin devices.

 2010 Microchip Technology Inc.

DS39881D-page 167

PIC24FJ64GA004 FAMILY

REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER

R/W-0

U-0

—

R/W-0

PSIDL

R/W-0

(1)

PMPEN

ADRMUX1

ADRMUX0

PTBEEN

PTWREN

PTRDEN

bit 15

bit 8

R/W-0

CSF1

R/W-0

CSF0

R/W-0⁽²⁾

ALP

U-0

—

R/W-0⁽²⁾

CS1P

R/W-0

BEP

R/W-0

WRSP

R/W-0

RDSP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

PMPEN: Parallel Master Port Enable bit

1= PMP enabled

0= PMP disabled, no off-chip access performed

bit 14

bit 13

Unimplemented: Read as ‘0’

PSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-11

ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits⁽¹⁾

11= Reserved

10= All 16 bits of address are multiplexed on PMD<7:0> pins

01= Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on

PMA<10:8>

00= Address and data appear on separate pins

bit 10

bit 9

PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)

1= PMBE port enabled

0= PMBE port disabled

PTWREN: Write Enable Strobe Port Enable bit

1= PMWR/PMENB port enabled

0= PMWR/PMENB port disabled

bit 8

PTRDEN: Read/Write Strobe Port Enable bit

1= PMRD/PMWR port enabled

0= PMRD/PMWR port disabled

bit 7-6

CSF1:CSF0: Chip Select Function bits

11= Reserved

10= PMCS1 functions as chip set

01= Reserved

00= Reserved

bit 5

ALP: Address Latch Polarity bit⁽²⁾

1= Active-high (PMALL and PMALH)

0= Active-low (PMALL and PMALH)

bit 4

bit 3

Unimplemented: Read as ‘0’

CS1P: Chip Select 1 Polarity bit⁽²⁾

1= Active-high (PMCS1/PMCS1)

0= Active-low (PMCS1/PMCS1)

Note 1: PMA<10:2> are not available on 28-pin devices.

2: These bits have no effect when their corresponding pins are used as address lines.

DS39881D-page 168

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REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)

bit 2

BEP: Byte Enable Polarity bit

1= Byte enable active-high (PMBE)

0= Byte enable active-low (PMBE)

bit 1

WRSP: Write Strobe Polarity bit

For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):

1= Write strobe active-high (PMWR)

0= Write strobe active-low (PMWR)

For Master Mode 1 (PMMODE<9:8> = 11):

1= Enable strobe active-high (PMENB)

0= Enable strobe active-low (PMENB)

bit 0

RDSP: Read Strobe Polarity bit

For Slave modes and Master Mode 2 (PMMODE<9:8> = 00,01,10):

1= Read strobe active-high (PMRD)

0= Read strobe active-low (PMRD)

For Master Mode 1 (PMMODE<9:8> = 11):

1= Read/write strobe active-high (PMRD/PMWR)

0= Read/write strobe active-low (PMRD/PMWR)

Note 1: PMA<10:2> are not available on 28-pin devices.

2: These bits have no effect when their corresponding pins are used as address lines.

 2010 Microchip Technology Inc.

DS39881D-page 169

PIC24FJ64GA004 FAMILY

REGISTER 18-2: PMMODE: Parallel Port Mode Register

R-0

R/W-0

BUSY

IRQM1

IRQM0

INCM1

INCM0

MODE16

MODE1

MODE0

bit 15

bit 8

R/W-0

WAITB1⁽¹⁾

WAITB0⁽¹⁾

WAITM3

WAITM2

WAITM1

WAITM0

WAITE1⁽¹⁾

WAITE0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

BUSY: Busy bit (Master mode only)

1= Port is busy (not useful when the processor stall is active)

0= Port is not busy

bit 14-13

IRQM1:IRQM0: Interrupt Request Mode bits

11= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)

or on a read or write operation when PMA<1:0> = 11(Addressable PSP mode only)

10= No interrupt generated, processor stall activated

01= Interrupt generated at the end of the read/write cycle

00= No interrupt generated

bit 12-11

INCM1:INCM0: Increment Mode bits

11= PSP read and write buffers auto-increment (Legacy PSP mode only)

10= Decrement ADDR<10:0> by 1 every read/write cycle

01= Increment ADDR<10:0> by 1 every read/write cycle

00= No increment or decrement of address

bit 10

MODE16: 8/16-Bit Mode bit

1= 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers

0= 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer

bit 9-8

MODE1:MODE0: Parallel Port Mode Select bits

11= Master Mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)

10= Master Mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)

01= Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)

00= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)

bit 7-6

bit 5-2

bit 1-0

WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits⁽¹⁾

11= Data wait of 4 TCY; multiplexed address phase of 4 TCY

10= Data wait of 3 TCY; multiplexed address phase of 3 TCY

01= Data wait of 2 TCY; multiplexed address phase of 2 TCY

00= Data wait of 1 TCY; multiplexed address phase of 1 TCY

WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits

1111= Wait of additional 15 TCY

...

0001= Wait of additional 1 TCY

0000= No additional wait cycles (operation forced into one TCY)

WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits⁽¹⁾

11= Wait of 4 TCY

10= Wait of 3 TCY

01= Wait of 2 TCY

00= Wait of 1 TCY

Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.

DS39881D-page 170

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REGISTER 18-3: PMADDR: PARALLEL PORT ADDRESS REGISTER

U-0

—

R/W-0

CS1

U-0

—

U-0

—

U-0

—

R/W-0

ADDR<10:8>⁽¹⁾

R/W-0

bit 8

bit 15

R/W-0

bit 7

R/W-0

bit 0

ADDR<7:0>⁽¹⁾

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

CS1: Chip Select 1 bit

1= Chip select 1 is active

0= Chip select 1 is inactive

bit 13-11

bit 10-0

Unimplemented: Read as ‘0’

ADDR10:ADDR0: Parallel Port Destination Address bits⁽¹⁾

Note 1: PMA<10:2> are not available on 28-pin devices.

REGISTER 18-4: PMAEN: PARALLEL PORT ENABLE REGISTER

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

PTEN10⁽¹⁾

R/W-0

PTEN9⁽¹⁾

R/W-0

PTEN8⁽¹⁾

PTEN14

bit 15

bit 8

R/W-0

PTEN7⁽¹⁾

PTEN6⁽¹⁾

PTEN5⁽¹⁾

PTEN4⁽¹⁾

PTEN3⁽¹⁾

PTEN2⁽¹⁾

PTEN1

PTEN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

Unimplemented: Read as ‘0’

PTEN14: PMCS1 Strobe Enable bit

1= PMCS1 functions as chip select

0= PMCS1 pin functions as port I/O

bit 13-11

bit 10-2

Unimplemented: Read as ‘0’

PTEN10:PTEN2: PMP Address Port Enable bits⁽¹⁾

1= PMA<10:2> function as PMP address lines

0= PMA<10:2> function as port I/O

bit 1-0

PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits

1= PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL

0= PMA1 and PMA0 pads functions as port I/O

Note 1: PMA<10:2> are not available on 28-pin devices.

 2010 Microchip Technology Inc.

DS39881D-page 171

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REGISTER 18-5: PMSTAT: PARALLEL PORT STATUS REGISTER

R-0

IBF

R/W-0, HS

IBOV

U-0

—

U-0

—

R-0

IB3F

IB2F

IB1F

IB0F

bit 15

bit 8

R-1

R/W-0, HS

OBUF

U-0

—

U-0

—

R-1

OBE

OB3E

OB2E

OB1E

OB0E

bit 0

bit 7

Legend:

HS = Hardware Set bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

IBF: Input Buffer Full Status bit

1= All writable input buffer registers are full

0= Some or all of the writable input buffer registers are empty

IBOV: Input Buffer Overflow Status bit

1= A write attempt to a full input byte register occurred (must be cleared in software)

0= No overflow occurred

bit 13-12

bit 11-8

Unimplemented: Read as ‘0’

IB3F:IB0F Input Buffer x Status Full bits

1= Input buffer contains data that has not been read (reading buffer will clear this bit)

0= Input buffer does not contain any unread data

bit 7

bit 6

OBE: Output Buffer Empty Status bit

1= All readable output buffer registers are empty

0= Some or all of the readable output buffer registers are full

OBUF: Output Buffer Underflow Status bits

1= A read occurred from an empty output byte register (must be cleared in software)

0= No underflow occurred

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

OB3E:OB0E Output Buffer x Status Empty bits

1= Output buffer is empty (writing data to the buffer will clear this bit)

0= Output buffer contains data that has not been transmitted

DS39881D-page 172

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REGISTER 18-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

(1)

RTSECSEL

PMPTTL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-2

bit 1

Unimplemented: Read as ‘0’

RTSECSEL: RTCC Seconds Clock Output Select bit⁽¹⁾

1= RTCC seconds clock is selected for the RTCC pin

0= RTCC alarm pulse is selected for the RTCC pin

bit 0

PMPTTL: PMP Module TTL Input Buffer Select bit

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt Trigger input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.

 2010 Microchip Technology Inc.

DS39881D-page 173

PIC24FJ64GA004 FAMILY

FIGURE 18-2:

LEGACY PARALLEL SLAVE PORT EXAMPLE

Address Bus

Data Bus

Master

PMD<7:0>

PIC24F Slave

PMD<7:0>

Control Lines

PMCS1

PMRD

PMWR

PMCS1

PMRD

PMWR

FIGURE 18-3:

ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE

PIC24F Slave

Master

PMA<1:0>

Write

Address

Decode

Read

Address

Decode

PMD<7:0>

PMDOUT1L (0)

PMDIN1L (0)

PMDIN1H (1)

PMDIN2L (2)

PMDIN2H (3)

PMCS1

PMRD

PMWR

PMCS1

PMRD

PMWR

PMDOUT1H (1)

PMDOUT2L (2)

PMDOUT2H (3)

Address Bus

Data Bus

Control Lines

TABLE 18-1: SLAVE MODE ADDRESS RESOLUTION

PMA<1:0>

Output Register (Buffer)

Input Register (Buffer)

00

01

10

11

PMDOUT1<7:0> (0)

PMDOUT1<15:8> (1)

PMDOUT2<7:0> (2)

PMDOUT2<15:8> (3)

PMDIN1<7:0> (0)

PMDIN1<15:8> (1)

PMDIN2<7:0> (2)

PMDIN2<15:8> (3)

FIGURE 18-4:

MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, SINGLE CHIP SELECT)

PIC24F

PMA<10:0>

PMD<7:0>

PMCS1

PMRD

PMWR

Address Bus

Data Bus

Control Lines

DS39881D-page 174

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

FIGURE 18-5:

MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ

AND WRITE STROBES, SINGLE CHIP SELECT)

PIC24F

PMA<10:8>

PMD<7:0>

PMA<7:0>

PMCS1

PMALL

PMRD

PMWR

Address Bus

Multiplexed

Data and

Address Bus

Control Lines

FIGURE 18-6:

MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, SINGLE CHIP SELECT)

PMD<7:0>

PMA<7:0>

PMA<15:8>

PIC24F

PMCS1

PMALL

PMALH

PMRD

PMWR

Multiplexed

Data and

Address Bus

Control Lines

FIGURE 18-7:

EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION

PIC24F

A<7:0>

PMD<7:0>

PMALL

373

A<15:0>

D<7:0>

CE

A<15:8>

373

OE

WR

PMALH

PMCS1

PMRD

PMWR

Address Bus

Data Bus

Control Lines

FIGURE 18-8:

EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION

PIC24F

A<7:0>

373

PMD<7:0>

PMALL

A<10:0>

D<7:0>

CE

A<10:8>

PMA<10:8>

OE

WR

Address Bus

Data Bus

PMCS1

PMRD

PMWR

Control Lines

 2010 Microchip Technology Inc.

DS39881D-page 175

PIC24FJ64GA004 FAMILY

FIGURE 18-9:

EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION

PIC24F

PMD<7:0>

Parallel Peripheral

AD<7:0>

PMALL

PMCS1

PMRD

ALE

CS

Address Bus

Data Bus

RD

PMWR

WR

Control Lines

FIGURE 18-10:

PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA)

PIC24F

Parallel EEPROM

PMA<n:0>

A<n:0>

PMD<7:0>

D<7:0>

PMCS1

PMRD

PMWR

CE

OE

WR

Address Bus

Data Bus

Control Lines

FIGURE 18-11:

PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA)

PIC24F

Parallel EEPROM

A<n:1>

D<7:0>

PMA<n:0>

PMD<7:0>

PMBE

PMCS1

PMRD

A0

CE

OE

WR

Address Bus

Data Bus

PMWR

Control Lines

FIGURE 18-12:

LCD CONTROL EXAMPLE (BYTE MODE OPERATION)

PIC24F

LCD Controller

PM<7:0>

PMA0

D<7:0>

RS

PMRD/PMWR

PMCS1

R/W

E

Address Bus

Data Bus

Control Lines

DS39881D-page 176

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19.0 REAL-TIME CLOCK AND

CALENDAR (RTCC)

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 29. Real-Time Clock and

Calendar (RTCC)” (DS39696).

FIGURE 19-1:

RTCC BLOCK DIAGRAM

CPU Clock Domain

RTCC Clock Domain

32.768 kHz Input

from SOSC Oscillator

RCFGCAL

RTCC Prescalers

0.5s

ALCFGRPT

YEAR

MTHDY

WKDYHR

MINSEC

RTCVAL

RTCC Timer

Alarm

Event

Comparator

ALMTHDY

ALWDHR

Compare Registers

with Masks

ALRMVAL

ALMINSEC

Repeat Counter

RTCC Interrupt

RTCC Interrupt Logic

Alarm Pulse

RTCC Pin

RTCOE

 2010 Microchip Technology Inc.

DS39881D-page 177

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TABLE 19-2: ALRMVAL REGISTER

19.1 RTCC Module Registers

MAPPING

The RTCC module registers are organized into three

categories:

Alarm Value Register Window

ALRMPTR

<1:0>

• RTCC Control Registers

• RTCC Value Registers

• Alarm Value Registers

ALRMVAL<15:8> ALRMVAL<7:0>

00

01

10

11

ALRMMIN

ALRMWD

ALRMMNTH

—

ALRMSEC

ALRMHR

ALRMDAY

—

19.1.1

REGISTER MAPPING

To limit the register interface, the RTCC Timer and

Alarm Time registers are accessed through corre-

sponding register pointers. The RTCC Value register

window (RTCVALH and RTCVALL) uses the RTCPTR

bits (RCFGCAL<9:8>) to select the desired Timer

register pair (see Table 19-1).

Considering that the 16-bit core does not distinguish

between 8-bit and 16-bit read operations, the user must

be aware that when reading either the ALRMVALH or

ALRMVALL bytes will decrement the ALRMPTR<1:0>

value. The same applies to the RTCVALH or RTCVALL

bytes with the RTCPTR<1:0> being decremented.

By writing the RTCVALH byte, the RTCC Pointer value,

RTCPTR<1:0> bits, decrement by one until they reach

‘00’. Once they reach ‘00’, the MINUTES and SEC-

ONDS value will be accessible through RTCVALH and

RTCVALL until the pointer value is manually changed.

Note:

This only applies to read operations and

not write operations.

19.1.2

WRITE LOCK

In order to perform a write to any of the RTCC Timer

registers, the RTCWREN bit (RCFGCAL<13>) must be

set (refer to Example 19-1).

TABLE 19-1: RTCVAL REGISTER MAPPING

RTCC Value Register Window

RTCPTR

<1:0>

Note:

To avoid accidental writes to the timer, it is

recommended that the RTCWREN bit

(RCFGCAL<13>) is kept clear at any

other time. For the RTCWREN bit to be

set, there is only 1 instruction cycle time

window allowed between the 55h/AA

sequence and the setting of RTCWREN;

therefore, it is recommended that code

follow the procedure in Example 19-1.

RTCVAL<15:8> RTCVAL<7:0>

00

01

10

11

MINUTES

WEEKDAY

MONTH

—

SECONDS

HOURS

DAY

YEAR

The Alarm Value register window (ALRMVALH and

ALRMVALL) uses the ALRMPTR bits

(ALCFGRPT<9:8>) to select the desired Alarm register

pair (see Table 19-2).

By writing the ALRMVALH byte, the Alarm Pointer

value, ALRMPTR<1:0> bits, decrement by one until

they reach ‘00’. Once they reach ‘00’, the ALRMMIN

and ALRMSEC value will be accessible through

ALRMVALH and ALRMVALL until the pointer value is

manually changed.

EXAMPLE 19-1:

SETTING THE RTCWREN BIT

asm volatile("push w7");

asm volatile("push w8");

asm volatile("disi #5");

asm volatile("mov #0x55, w7");

asm volatile("mov w7, _NVMKEY");

asm volatile("mov #0xAA, w8");

asm volatile("mov w8, _NVMKEY");

asm volatile("bset _RCFGCAL, #13"); //set the RTCWREN bit

asm volatile("pop w8");

asm volatile("pop w7");

DS39881D-page 178

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19.1.3

RTCC CONTROL REGISTERS

REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER⁽¹⁾

R/W-0

RTCEN⁽²⁾

U-0

—

R/W-0

R-0

R/W-0

RTCWREN

RTCSYNC HALFSEC⁽³⁾

RTCOE

RTCPTR1

RTCPTR0

bit 15

bit 8

R/W-0

CAL7

R/W-0

CAL6

R/W-0

CAL5

R/W-0

CAL4

R/W-0

CAL3

R/W-0

CAL2

R/W-0

CAL1

R/W-0

CAL0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

RTCEN: RTCC Enable bit⁽²⁾

1= RTCC module is enabled

0= RTCC module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

RTCWREN: RTCC Value Registers Write Enable bit

1= RTCVALH and RTCVALL registers can be written to by the user

0= RTCVALH and RTCVALL registers are locked out from being written to by the user

bit 12

RTCSYNC: RTCC Value Registers Read Synchronization bit

1= RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple

resulting in an invalid data read. If the register is read twice and results in the same data, the data

can be assumed to be valid.

0= RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple

bit 11

bit 10

bit 9-8

HALFSEC: Half-Second Status bit⁽³⁾

1= Second half period of a second

0= First half period of a second

RTCOE: RTCC Output Enable bit

1= RTCC output enabled

0= RTCC output disabled

RTCPTR1:RTCPTR0: RTCC Value Register Window Pointer bits

Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL regis-

ters; the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.

RTCVAL<15:8>:

00= MINUTES

01= WEEKDAY

10= MONTH

11= Reserved

RTCVAL<7:0>:

00= SECONDS

01= HOURS

10= DAY

11= YEAR

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.

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REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER⁽¹⁾

bit 7-0

CAL7:CAL0: RTC Drift Calibration bits

01111111= Maximum positive adjustment; adds 508 RTC clock pulses every one minute

...

01111111= Minimum positive adjustment; adds 4 RTC clock pulses every one minute

00000000= No adjustment

11111111= Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute

...

10000000= Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.

REGISTER 19-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

(1)

RTSECSEL

PMPTTL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-2

bit 1

Unimplemented: Read as ‘0’

RTSECSEL: RTCC Seconds Clock Output Select bit⁽¹⁾

1= RTCC seconds clock is selected for the RTCC pin

0= RTCC alarm pulse is selected for the RTCC pin

bit 0

PMPTTL: PMP Module TTL Input Buffer Select bit

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt Trigger input buffers

Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.

DS39881D-page 180

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REGISTER 19-3:

ALCFGRPT: ALARM CONFIGURATION REGISTER

R/W-0

ALRMEN

bit 15

R/W-0

CHIME

AMASK3

AMASK2

AMASK1

AMASK0

ALRMPTR1 ALRMPTR0

bit 8

R/W-0

ARPT7

bit 7

R/W-0

ARPT6

ARPT5

ARPT4

ARPT3

ARPT2

ARPT1

ARPT0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

ALRMEN: Alarm Enable bit

1= Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and

CHIME = 0)

0= Alarm is disabled

bit 14

CHIME: Chime Enable bit

1= Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh

0= Chime is disabled; ARPT<7:0> bits stop once they reach 00h

bit 13-10

AMASK3:AMASK0: Alarm Mask Configuration bits

0000= Every half second

0001= Every second

0010= Every 10 seconds

0011= Every minute

0100= Every 10 minutes

0101= Every hour

0110= Once a day

0111= Once a week

1000= Once a month

1001= Once a year (except when configured for February 29th, once every 4 years)

101x= Reserved – do not use

11xx= Reserved – do not use

bit 9-8

ALRMPTR1:ALRMPTR0: Alarm Value Register Window Pointer bits

Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;

the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.

ALRMVAL<15:8>:

00= ALRMMIN

01= ALRMWD

10= ALRMMNTH

11= Unimplemented

ALRMVAL<7:0>:

00= ALRMSEC

01= ALRMHR

10= ALRMDAY

11= Unimplemented

bit 7-0

ARPT7:ARPT0: Alarm Repeat Counter Value bits

11111111= Alarm will repeat 255 more times

...

00000000= Alarm will not repeat

The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to

FFh unless CHIME = 1.

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DS39881D-page 181

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19.1.4

RTCVAL REGISTER MAPPINGS

REGISTER 19-4:

YEAR: YEAR VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-x

YRTEN3

bit 7

YRTEN2

YRTEN1

YRTEN0

YRONE3

YRONE2

YRONE1

YRONE0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

YRTEN3:YRTEN0: Binary Coded Decimal Value of Year’s Tens Digit; Contains a value from 0 to 9

YRONE3:YRONE0: Binary Coded Decimal Value of Year’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.

REGISTER 19-5:

MTHDY: MONTH AND DAY VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R-x

MTHTEN0

MTHONE3

MTHONE2

MTHONE1

MTHONE0

bit 15

bit 8

U-0

—

U-0

—

R/W-x

DAYTEN1

DAYTEN0

DAYONE3

DAYONE2

DAYONE1

DAYONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of ‘0’ or ‘1’

bit 11-8

bit 7-6

bit 5-4

bit 3-0

MTHONE3:MTHONE0: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9

Unimplemented: Read as ‘0’

DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3

DAYONE3:DAYONE0: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

DS39881D-page 182

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REGISTER 19-6:

WKDYHR: WEEKDAY AND HOURS VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

WDAY2

WDAY1

WDAY0

bit 15

bit 8

U-0

—

U-0

—

R/W-x

HRTEN1

HRTEN0

HRONE3

HRONE2

HRONE1

HRONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

bit 7-6

Unimplemented: Read as ‘0’

WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6

Unimplemented: Read as ‘0’

bit 5-4

HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2

HRONE3:HRONE0: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9

bit 3-0

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 19-7:

MINSEC: MINUTES AND SECONDS VALUE REGISTER

U-0

R/W-x

—

MINTEN2

MINTEN1

MINTEN0

MINONE3

MINONE2

MINONE1

MINONE0

bit 15

bit 8

U-0

—

R/W-x

SECTEN2

SECTEN1

SECTEN0

SECONE3

SECONE2

SECONE1

SECONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

bit 11-8

bit 7

MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5

MINONE3:MINONE0: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9

Unimplemented: Read as ‘0’

bit 6-4

bit 3-0

SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5

SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9

 2010 Microchip Technology Inc.

DS39881D-page 183

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19.1.5

ALRMVAL REGISTER MAPPINGS

REGISTER 19-8:

ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-x

MTHTEN0

MTHONE3

MTHONE2

MTHONE1

MTHONE0

bit 15

bit 8

U-0

—

U-0

—

R/W-x

DAYTEN1

DAYTEN0

DAYONE3

DAYONE2

DAYONE1

DAYONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of ‘0’ or ‘1’

bit 11-8

bit 7-6

bit 5-4

bit 3-0

MTHONE3:MTHONE0: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9

Unimplemented: Read as ‘0’

DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3

DAYONE3:DAYONE0: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 19-9:

ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

WDAY2

WDAY1

WDAY0

bit 15

bit 8

U-0

—

U-0

—

R/W-x

HRTEN1

HRTEN0

HRONE3

HRONE2

HRONE1

HRONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

bit 7-6

Unimplemented: Read as ‘0’

WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6

Unimplemented: Read as ‘0’

bit 5-4

HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2

HRONE3:HRONE0: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9

bit 3-0

Note 1: A write to this register is only allowed when RTCWREN = 1.

DS39881D-page 184

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER

U-0

—

R/W-x

MINTEN2

MINTEN1

MINTEN0

MINONE3

MINONE2

MINONE1

MINONE0

bit 15

bit 8

U-0

—

R/W-x

SECTEN2

SECTEN1

SECTEN0

SECONE3

SECONE2

SECONE1

SECONE0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

bit 11-8

bit 7

MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5

MINONE3:MINONE0: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9

Unimplemented: Read as ‘0’

bit 6-4

bit 3-0

SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5

SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9

3. a) If the oscillator is faster then ideal (negative

19.2 Calibration

result form step 2), the RCFGCAL register value

needs to be negative. This causes the specified

number of clock pulses to be subtracted from

the timer counter once every minute.

The real-time crystal input can be calibrated using the

periodic auto-adjust feature. When properly calibrated,

the RTCC can provide an error of less than 3 seconds

per month. This is accomplished by finding the number

of error clock pulses and storing the value into the

lower half of the RCFGCAL register. The 8-bit signed

value loaded into the lower half of RCFGCAL is multi-

plied by four and will be either added or subtracted from

the RTCC timer, once every minute. Refer to the steps

below for RTCC calibration:

b) If the oscillator is slower then ideal (positive

result from step 2) the RCFGCAL register value

needs to be positive. This causes the specified

number of clock pulses to be subtracted from

the timer counter once every minute.

4. Divide the number of error clocks per minute by

4 to get the correct CAL value and load the

RCFGCAL register with the correct value.

1. Using another timer resource on the device, the

user must find the error of the 32.768 kHz

crystal.

(Each 1-bit increment in CAL adds or subtracts

4 pulses).

2. Once the error is known, it must be converted to

the number of error clock pulses per minute.

Writes to the lower half of the RCFGCAL register

should only occur when the timer is turned off, or

immediately after the rising edge of the seconds pulse.

EQUATION 19-1:

Note:

It is up to the user to include in the error

value the initial error of the crystal, drift

due to temperature and drift due to crystal

aging.

(Ideal Frequency† – Measured Frequency) * 60 = Clocks

per Minute

†

Ideal frequency = 32,768 Hz

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DS39881D-page 185

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After each alarm is issued, the value of the ARPT bits

19.3 Alarm

is decremented by one. Once the value has reached

00h, the alarm will be issued one last time, after which

the ALRMEN bit will be cleared automatically and the

alarm will turn off.

• Configurable from half second to one year

• Enabled using the ALRMEN bit

(ALCFGRPT<15>, Register 19-3)

• One-time alarm and repeat alarm options

available

Indefinite repetition of the alarm can occur if the CHIME

bit = 1. Instead of the alarm being disabled when the

value of the ARPT bits reaches 00h, it rolls over to FFh

and continues counting indefinitely while CHIME is set.

19.3.1

CONFIGURING THE ALARM

The alarm feature is enabled using the ALRMEN bit.

This bit is cleared when an alarm is issued. Writes to

ALRMVAL should only take place when ALRMEN = 0.

19.3.2

ALARM INTERRUPT

At every alarm event, an interrupt is generated. In addi-

tion, an alarm pulse output is provided that operates at

half the frequency of the alarm. This output is

completely synchronous to the RTCC clock and can be

used as a trigger clock to other peripherals.

As shown in Figure 19-2, the interval selection of the

alarm is configured through the AMASK bits

(ALCFGRPT<13:10>). These bits determine which and

how many digits of the alarm must match the clock

value for the alarm to occur.

Note:

Changing any of the registers, other then

the RCFGCAL and ALCFGRPT registers

and the CHIME bit while the alarm is

enabled (ALRMEN = 1), can result in a

false alarm event leading to a false alarm

interrupt. To avoid a false alarm event, the

timer and alarm values should only be

changed while the alarm is disabled

(ALRMEN = 0). It is recommended that the

ALCFGRPT register and CHIME bit be

changed when RTCSYNC = 0.

The alarm can also be configured to repeat based on a

preconfigured interval. The amount of times this occurs

once the alarm is enabled is stored in the ARPT bits,

ARPT7:ARPT0 (ALCFGRPT<7:0>). When the value of

the ARPT bits equals 00h and the CHIME bit

(ALCFGRPT<14>) is cleared, the repeat function is

disabled and only a single alarm will occur. The alarm

can be repeated up to 255 times by loading

ARPT7:ARPT0 with FFh.

FIGURE 19-2:

ALARM MASK SETTINGS

Day of

the

Week

Alarm Mask Setting

(AMASK3:AMASK0)

Month

Day

Hours

Minutes

Seconds

0000– Every half second

0001– Every second

0010– Every 10 seconds

0011– Every minute

0100– Every 10 minutes

0101– Every hour

s

m

0110– Every day

h

0111– Every week

1000– Every month

d

(1)

1001– Every year

m

d

Note 1: Annually, except when configured for February 29.

DS39881D-page 186

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

Consider the CRC equation:

20.0 PROGRAMMABLE CYCLIC

REDUNDANCY CHECK (CRC)

GENERATOR

x

¹⁶+ x¹²+ x⁵+ 1

To program this polynomial into the CRC generator,

the CRC register bits should be set as shown in

Table 20-1.

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 30. Programmable Cyclic

Redundancy Check (CRC)” (DS39714).

TABLE 20-1: EXAMPLE CRC SETUP

Bit Name

Bit Value

PLEN3:PLEN0

X<15:1>

1111

000100000010000

The programmable CRC generator offers the following

features:

Note that for the value of X<15:1>, the 12th bit and the

5th bit are set to ‘1’, as required by the equation. The 0

bit required by the equation is always XORed. For a

16-bit polynomial, the 16th bit is also always assumed

to be XORed; therefore, the X<15:1> bits do not have

the 0 bit or the 16th bit.

• User-programmable polynomial CRC equation

• Interrupt output

• Data FIFO

The module implements a software configurable CRC

generator. The terms of the polynomial and its length

can be programmed using the CRCXOR (X<15:1>) bits

and the CRCCON (PLEN3:PLEN0) bits, respectively.

The topology of a standard CRC generator is shown in

Figure 20-2.

FIGURE 20-1:

CRC SHIFTER DETAILS

PLEN<3:0>

0

1

2

15

CRC Shift Register

Hold

X2

Hold

X1

X3

X15

0

XOR

OUT

IN

BIT 0

IN

BIT 1

IN

BIT 2

IN

BIT 15

DOUT

1

p_clk

CRC Read Bus

CRC Write Bus

 2010 Microchip Technology Inc.

DS39881D-page 187

PIC24FJ64GA004 FAMILY

FIGURE 20-2:

CRC GENERATOR RECONFIGURED FOR x¹⁶+ x¹²+ x⁵+ 1

XOR

D

Q

D

Q

D

Q

D

Q

D

Q

SDOx

BIT 0

BIT 4

BIT 5

BIT 12

BIT 15

p_clk

CRC Read Bus

CRC Write Bus

To empty words already written into a FIFO, the

CRCGO bit must be set to ‘1’ and the CRC shifter

allowed to run until the CRCMPT bit is set.

20.1 User Interface

20.1.1

DATA INTERFACE

Also, to get the correct CRC reading, it will be

necessary to wait for the CRCMPT bit to go high before

reading the CRCWDAT register.

To start serial shifting, a ‘1’ must be written to the

CRCGO bit.

The module incorporates a FIFO that is 8 deep when

PLEN (PLEN<3:0>) > 7, and 16 deep, otherwise. The

data for which the CRC is to be calculated must first be

written into the FIFO. The smallest data element that

can be written into the FIFO is one byte. For example,

if PLEN = 5, then the size of the data is PLEN + 1 = 6.

The data must be written as follows:

If a word is written when the CRCFUL bit is set, the

VWORD Pointer will roll over to 0. The hardware will

then behave as if the FIFO is empty. However, the con-

dition to generate an interrupt will not be met; therefore,

no interrupt will be generated (See Section 20.1.2

“Interrupt Operation”).

At least one instruction cycle must pass after a write to

CRCWDAT before a read of the VWORD bits is done.

data[5:0] = crc_input[5:0]

data[7:6] = ‘bxx

Once data is written into the CRCWDAT MSb (as

defined by PLEN), the value of the VWORD bits

(CRCCON<12:8>) increments by one. The serial

shifter starts shifting data into the CRC engine when

CRCGO = 1 and VWORD > 0. When the MSb is

shifted out, VWORD decrements by one. The serial

shifter continues shifting until the VWORD reaches 0.

Therefore, for a given value of PLEN, it will take

(PLEN + 1) * VWORD number of clock cycles to

complete the CRC calculations.

20.1.2

INTERRUPT OPERATION

When the VWORD4:VWORD0 bits make a transition

from a value of ‘1’ to ‘0’, an interrupt will be generated.

20.2 Operation in Power Save Modes

20.2.1

SLEEP MODE

If Sleep mode is entered while the module is operating,

the module will be suspended in its current state until

clock execution resumes.

When VWORD reaches 8 (or 16), the CRCFUL bit will

be set. When VWORD reaches 0, the CRCMPT bit will

be set.

20.2.2

IDLE MODE

To continue full module operation in Idle mode, the

CSIDL bit must be cleared prior to entry into the mode.

To continually feed data into the CRC engine, the rec-

ommended mode of operation is to initially “prime” the

FIFO with a sufficient number of words so no interrupt

is generated before the next word can be written. Once

that is done, start the CRC by setting the CRCGO bit to

‘1’. From that point onward, the VWORD bits should be

polled. If they read less than 8 or 16, another word can

be written into the FIFO.

If CSIDL = 1, the module will behave the same way as

it does in Sleep mode; pending interrupt events will be

passed on, even though the module clocks are not

available.

DS39881D-page 188

 2010 Microchip Technology Inc.

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20.3 Registers

There are four registers used to control programmable

CRC operation:

• CRCCON

• CRCXOR

• CRCDAT

• CRCWDAT

REGISTER 20-1:

CRCCON: CRC CONTROL REGISTER

U-0

—

U-0

—

R/W-0

CSIDL

R-0

VWORD4

VWORD3

VWORD2

VWORD1

VWORD0

bit 15

bit 8

R-0

R-1

U-0

—

R/W-0

CRCFUL

bit 7

CRCMPT

CRCGO

PLEN3

PLEN2

PLEN1

PLEN0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-14

bit 13

Unimplemented: Read as ‘0’

CSIDL: CRC Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-8

bit 7

VWORD4:VWORD0: Pointer Value bits

Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7,

or 16 when PLEN3:PLEN0 7.

CRCFUL: FIFO Full bit

1= FIFO is full

0= FIFO is not full

bit 6

CRCMPT: FIFO Empty Bit

1= FIFO is empty

0= FIFO is not empty

bit 5

bit 4

Unimplemented: Read as ‘0’

CRCGO: Start CRC bit

1= Start CRC serial shifter

0= CRC serial shifter turned off

bit 3-0

PLEN3:PLEN0: Polynomial Length bits

Denotes the length of the polynomial to be generated minus 1.

 2010 Microchip Technology Inc.

DS39881D-page 189

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REGISTER 20-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER

R/W-0

X15

R/W-0

X14

R/W-0

X13

R/W-0

X12

R/W-0

X11

R/W-0

X10

R/W-0

X9

R/W-0

X8

bit 15

bit 8

R/W-0

X7

R/W-0

X6

R/W-0

X5

R/W-0

X4

R/W-0

X3

R/W-0

X2

R/W-0

X1

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-1

bit 0

X15:X1: XOR of Polynomial Term XⁿEnable bits

Unimplemented: Read as ‘0’

DS39881D-page 190

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A block diagram of the A/D Converter is shown in

Figure 21-1.

21.0 10-BIT HIGH-SPEED A/D

CONVERTER

To perform an A/D conversion:

Note:

This data sheet summarizes the features

1. Configure the A/D module:

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 17. 10-Bit A/D Converter”

(DS39705).

a) Select port pins as analog inputs

(AD1PCFG<15:0>).

b) Select voltage reference source to match

expected range on analog inputs

(AD1CON2<15:13>).

c) Select the analog conversion clock to

match desired data rate with processor

clock (AD1CON3<7:0>).

The 10-bit A/D Converter has the following key

features:

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 500 ksps

• Up to 13 analog input pins

d) Select the appropriate sample/conversion

sequence

(AD1CON1<7:5>

and

AD1CON3<12:8>).

e) Select how conversion results are

presented in the buffer (AD1CON1<9:8>).

• External voltage reference input pins

• Automatic Channel Scan mode

f) Select interrupt rate (AD1CON2<5:2>).

g) Turn on A/D module (AD1CON1<15>).

2. Configure A/D interrupt (if required):

a) Clear the AD1IF bit.

• Selectable conversion trigger source

• 16-word conversion result buffer

• Selectable Buffer Fill modes

• Four result alignment options

b) Select A/D interrupt priority.

• Operation during CPU Sleep and Idle modes

Depending on the particular device pinout, the 10-bit

A/D Converter can have up to three analog input pins,

designated AN0 through AN12. In addition, there are

two analog input pins for external voltage reference

connections. These voltage reference inputs may be

shared with other analog input pins. The actual number

of analog input pins and external voltage reference

input configuration will depend on the specific device.

 2010 Microchip Technology Inc.

DS39881D-page 191

PIC24FJ64GA004 FAMILY

FIGURE 21-1:

10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM

Internal Data Bus

16

AVDD

AVSS

VR+

VR-

VREF+

VREF-

Comparator

VINH

VINL

VR- VR+

DAC

S/H

AN0

VINH

AN1

AN2

10-Bit SAR

Conversion Logic

Data Formatting

AN3

AN4

AN5

VINL

ADC1BUF0:

ADC1BUFF

(1)

AN6

AD1CON1

AD1CON2

AD1CON3

AD1CHS

(1)

AN7

(1)

VINH

AN8

AD1PCFG

AD1CSSL

AN9

VINL

AN10

AN11

AN12

Sample Control

Control Logic

Conversion Control

Input MUX Control

Pin Config. Control

(2)

VBG

Note 1: Analog channels AN6 through AN8 are available on 44-pin devices only.

2: Band gap voltage reference (VBG) is internally connected to analog channel AN15, which does not appear on any pin.

DS39881D-page 192

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REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1

R/W-0

ADON

U-0

—

R/C-0

U-0

—

U-0

—

U-0

—

R/W-0

ADSIDL

FORM1

FORM0

bit 15

bit 8

R/W-0

U-0

—

U-0

—

R/W-0

ASAM

R/W-0, HCS R/W-0, HCS

SAMP DONE

bit 0

SSRC2

SSRC1

SSRC0

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HCS = Hardware Clearable/Settable bit

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

ADON: A/D Operating Mode bit

1= A/D Converter module is operating

0= A/D Converter is off

bit 14

bit 13

Unimplemented: Read as ‘0’

ADSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-10

bit 9-8

Unimplemented: Read as ‘0’

FORM1:FORM0: Data Output Format bits

11= Signed fractional (sddd dddd dd00 0000)

10= Fractional (dddd dddd dd00 0000)

01= Signed integer (ssss sssd dddd dddd)

00= Integer (0000 00dd dddd dddd)

bit 7-5

SSRC2:SSRC0: Conversion Trigger Source Select bits

111= Internal counter ends sampling and starts conversion (auto-convert)

110= Reserved

10x= Reserved

011= Reserved

010= Timer3 compare ends sampling and starts conversion

001= Active transition on INT0 pin ends sampling and starts conversion

000= Clearing SAMP bit ends sampling and starts conversion

bit 4-3

bit 2

Unimplemented: Read as ‘0’

ASAM: A/D Sample Auto-Start bit

1= Sampling begins immediately after last conversion completes. SAMP bit is auto-set.

0= Sampling begins when SAMP bit is set

bit 1

bit 0

SAMP: A/D Sample Enable bit

1= A/D sample/hold amplifier is sampling input

0= A/D sample/hold amplifier is holding

DONE: A/D Conversion Status bit

1= A/D conversion is done

0= A/D conversion is NOT done

 2010 Microchip Technology Inc.

DS39881D-page 193

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REGISTER 21-2: AD1CON2: A/D CONTROL REGISTER 2

R/W-0

—

U-0

—

R/W-0

U-0

—

U-0

—

VCFG2

VCFG1

VCFG0

CSCNA

bit 15

bit 8

R-0

U-0

—

R/W-0

SMPI3

R/W-0

SMPI2

R/W-0

SMPI1

R/W-0

SMPI0

R/W-0

BUFM

R/W-0

ALTS

BUFS

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-13

VCFG2:VCFG0: Voltage Reference Configuration bits

VCFG2:VCFG0

VR+

VR-

000

001

010

011

1xx

AVDD*

External VREF+ pin

AVDD*

AVSS*

External VREF- pin

AVSS*

External VREF+ pin

AVDD*

*

AVDD and AVSS inputs are tied to VDD and VSS on 28-pin devices.

bit 12-11

bit 10

Unimplemented: Read as ‘0’

CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit

1= Scan inputs

0= Do not scan inputs

bit 9-8

bit 7

Unimplemented: Read as ‘0’

BUFS: Buffer Fill Status bit (valid only when BUFM = 1)

1= A/D is currently filling buffer 08-0F, user should access data in 00-07

0= A/D is currently filling buffer 00-07, user should access data in 08-0F

bit 6

Unimplemented: Read as ‘0’

bit 5-2

SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits

1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence

1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence

.....

0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence

0000 = Interrupts at the completion of conversion for each sample/convert sequence

bit 1

bit 0

BUFM: Buffer Mode Select bit

1 = Buffer configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>)

0 = Buffer configured as one 16-word buffer (ADC1BUFn<15:0>)

ALTS: Alternate Input Sample Mode Select bit

1= Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and

MUX A input multiplexer settings for all subsequent samples

0= Always uses MUX A input multiplexer settings

DS39881D-page 194

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REGISTER 21-3: AD1CON3: A/D CONTROL REGISTER 3

R/W-0

ADRC

U-0

—

U-0

—

R/W-0

SAMC4

SAMC3

SAMC2

SAMC1

SAMC0

bit 15

bit 8

R/W-0

ADCS7

ADCS6

ADCS5

ADCS4

ADCS3

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

ADRC: A/D Conversion Clock Source bit

1= A/D internal RC clock

0= Clock derived from system clock

bit 14-13

bit 12-8

Unimplemented: Read as ‘0’

SAMC4:SAMC0: Auto-Sample Time bits

11111= 31 TAD

·····

00001= 1 TAD

00000= 0 TAD (not recommended)

bit 7-0

ADCS7:ADCS0: A/D Conversion Clock Select bits

11111111

······ = Reserved

01000000

00111111= 64 • TCY

······

00000001= 2 • TCY

00000000= TCY

 2010 Microchip Technology Inc.

DS39881D-page 195

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REGISTER 21-4: AD1CHS: A/D INPUT SELECT REGISTER

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

CH0NB

CH0SB3^(1,2)CH0SB2^(1,2)CH0SB1^(1,2)CH0SB0^(1,2)

bit 15

bit 8

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

CH0NA

CH0SA3^(1,2)CH0SA2^(1,2)CH0SA1^(1,2)CH0SA0^(1,2)

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 14-12

bit 11-8

Unimplemented: Read as ‘0’

CH0SB3:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits^(1,2)

1111= Channel 0 positive input is AN15 (band gap voltage reference)

1100= Channel 0 positive input is AN12

1011= Channel 0 positive input is AN11

·····

0001= Channel 0 positive input is AN1

0000= Channel 0 positive input is AN0

bit 7

CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 6-4

bit 3-0

Unimplemented: Read as ‘0’

CH0SA3:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits^(1,2)

1111= Channel 0 positive input is AN15 (band gap voltage reference)

1100= Channel 0 positive input is AN12

1011= Channel 0 positive input is AN11

·····

0001= Channel 0 positive input is AN1

0000= Channel 0 positive input is AN0

Note 1: Combinations ‘1101’ and ‘1110’ are unimplemented; do not use.

2: Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; do not use.

DS39881D-page 196

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REGISTER 21-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER

R/W-0

U-0

—

U-0

—

R/W-0

PCFG8⁽¹⁾

PCFG15

PCFG12

PCFG11

PCFG10

PCFG9

bit 15

bit 8

R/W-0

PCFG7⁽¹⁾

PCFG6⁽¹⁾

PCFG5

PCFG4

PCFG3

PCFG2

PCFG1

PCFG0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

PCFG15: Analog Input Pin Configuration Control bits

1= Band gap voltage reference is disabled

0= Band gap voltage reference enabled

bit 14-13

bit 12-0

Unimplemented: Read as ‘0’

PCFG12:PCFG0: Analog Input Pin Configuration Control bits⁽¹⁾

1= Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled

0= Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage

Note 1: Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; leave these corresponding bits

set.

REGISTER 21-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER

R/W-0

U-0

—

U-0

—

R/W-0

CSSL8⁽¹⁾

CSSL15

CSSL12

CSSL11

CSSL10

CSSL9

bit 15

bit 8

R/W-0

CSSL7⁽¹⁾

CSSL6⁽¹⁾

CSSL5

CSSL4

CSSL3

CSSL2

CSSL1

CSSL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

CSSL15: Band Gap Reference Input Pin Scan Selection bits

1=Band gap voltage reference channel selected for input scan

0=Band gap voltage reference channel omitted from input scan

bit 14-13

bit 12-0

Unimplemented: Read as ‘0’

CSSL12:CSSL0: A/D Input Pin Scan Selection bits⁽¹⁾

1=Corresponding analog channel selected for input scan

0=Analog channel omitted from input scan

Note 1: Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; leave these corresponding bits

cleared.

 2010 Microchip Technology Inc.

DS39881D-page 197

PIC24FJ64GA004 FAMILY

EQUATION 21-1: A/D CONVERSION CLOCK PERIOD⁽¹⁾

TAD = TCY • (ADCS +1)

TAD

TCY

– 1

ADCS =

Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.

FIGURE 21-2:

10-BIT A/D CONVERTER ANALOG INPUT MODEL

VDD

RIC  250

RSS  5 k(Typical)

Sampling

Switch

VT = 0.6V

ANx

RSS

Rs

CHOLD

= DAC capacitance

= 4.4 pF (Typical)

VA

CPIN

ILEAKAGE

500 nA

6-11 pF

(Typical)

VSS

Legend: CPIN

VT

= Input Capacitance

= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to

various junctions

RIC

= Interconnect Resistance

RSS

CHOLD

= Sampling Switch Resistance

= Sample/Hold Capacitance (from DAC)

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs  5 k.

DS39881D-page 198

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FIGURE 21-3:

A/D TRANSFER FUNCTION

Output Code

(Binary (Decimal))

11 1111 1111(1023)

11 1111 1110(1022)

10 0000 0011(515)

10 0000 0010(514)

10 0000 0001(513)

10 0000 0000(512)

01 1111 1111(511)

01 1111 1110(510)

01 1111 1101(509)

00 0000 0001(1)

00 0000 0000(0)

Voltage Level

 2010 Microchip Technology Inc.

DS39881D-page 199

PIC24FJ64GA004 FAMILY

NOTES:

DS39881D-page 200

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

22.0 COMPARATOR MODULE

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section

16.

Output

Compare”

(DS39706).

FIGURE 22-1:

COMPARATOR I/O OPERATING MODES

C1NEG

C1EN

CMCON<6>

C1INV

C1IN+

C1IN-

VIN-

C1OUT⁽¹⁾

C1POS

C1

C1IN+

CVREF

VIN+

C1OUTEN

C2NEG

C2POS

CMCON<7>

C2EN

C2

C2INV

C2IN+

C2IN-

VIN-

VIN+

C2OUT⁽¹⁾

C2IN+

CVREF

C2OUTEN

Note 1: This peripheral’s outputs must be assigned to an available RPn pin before use. Please see

Section 10.4 “Peripheral Pin Select” for more information.

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DS39881D-page 201

PIC24FJ64GA004 FAMILY

REGISTER 22-1:

CMCON: COMPARATOR CONTROL REGISTER

R/W-0

CMIDL

bit 15

U-0

—

R/C-0

R/W-0

C2EN

R/W-0

C1EN

R/W-0

C2EVT

C1EVT

C2OUTEN⁽¹⁾C1OUTEN⁽²⁾

bit 8

R-0

C2OUT

bit 7

R-0

R/W-0

C2INV

R/W-0

C1INV

R/W-0

C1OUT

C2NEG

C2POS

C1NEG

C1POS

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

CMIDL: Stop in Idle Mode bit

1= When device enters Idle mode, module does not generate interrupts; module is still enabled

0= Continue normal module operation in Idle mode

bit 14

bit 13

Unimplemented: Read as ‘0’

C2EVT: Comparator 2 Event

1= Comparator output changed states

0= Comparator output did not change states

bit 12

bit 11

bit 10

bit 9

C1EVT: Comparator 1 Event

1= Comparator output changed states

0= Comparator output did not change states

C2EN: Comparator 2 Enable

1= Comparator is enabled

0= Comparator is disabled

C1EN: Comparator 1 Enable

1= Comparator is enabled

0= Comparator is disabled

C2OUTEN: Comparator 2 Output Enable⁽¹⁾

1= Comparator output is driven on the output pad

0= Comparator output is not driven on the output pad

bit 8

C1OUTEN: Comparator 1 Output Enable⁽²⁾

1= Comparator output is driven on the output pad

0= Comparator output is not driven on the output pad

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

1= C2 VIN+ > C2 VIN-

0= C2 VIN+ < C2 VIN-

When C2INV = 1:

0= C2 VIN+ > C2 VIN-

1= C2 VIN+ < C2 VIN-

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

1= C1 VIN+ > C1 VIN-

0= C1 VIN+ < C1 VIN-

When C1INV = 1:

0= C1 VIN+ > C1 VIN-

1= C1 VIN+ < C1 VIN-

DS39881D-page 202

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 22-1:

CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)

bit 5

bit 4

bit 3

C2INV: Comparator 2 Output Inversion bit

1= C2 output inverted

0= C2 output not inverted

C1INV: Comparator 1 Output Inversion bit

1= C1 output inverted

0= C1 output not inverted

C2NEG: Comparator 2 Negative Input Configure bit

1= Input is connected to VIN+

0= Input is connected to VIN-

See Figure 22-1 for the Comparator modes.

bit 2

bit 1

bit 0

C2POS: Comparator 2 Positive Input Configure bit

1= Input is connected to VIN+

0= Input is connected to CVREF

See Figure 22-1 for the Comparator modes.

C1NEG: Comparator 1 Negative Input Configure bit

1= Input is connected to VIN+

0= Input is connected to VIN-

See Figure 22-1 for the Comparator modes.

C1POS: Comparator 1 Positive Input Configure bit

1= Input is connected to VIN+

0= Input is connected to CVREF

See Figure 22-1 for the Comparator modes.

Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select” for more information.

2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See

Section 10.4 “Peripheral Pin Select” for more information.

 2010 Microchip Technology Inc.

DS39881D-page 203

PIC24FJ64GA004 FAMILY

NOTES:

DS39881D-page 204

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PIC24FJ64GA004 FAMILY

voltage, each with 16 distinct levels. The range to be

used is selected by the CVRR bit (CVRCON<5>). The

primary difference between the ranges is the size of the

steps selected by the CVREF Selection bits

23.0 COMPARATOR VOLTAGE

REFERENCE

Note:

This data sheet summarizes the features

(CVR3:CVR0), with one range offering finer resolution.

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F Family Reference Manual”,

”Section 20. Comparator Voltage

Reference Module” (DS39709).

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF-. The voltage source is selected by the CVRSS

bit (CVRCON<4>).

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output.

23.1 Configuring the Comparator

Voltage Reference

The voltage reference module is controlled through the

CVRCON register (Register 23-1). The comparator

voltage reference provides two ranges of output

FIGURE 23-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

CVRSS = 1

CVRSS = 0

VREF+

AVDD

8R

CVR3:CVR0

R

CVREN

R

16 Steps

CVREF

R

CVRR

VREF-

8R

CVRSS = 1

CVRSS = 0

AVSS

 2010 Microchip Technology Inc.

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PIC24FJ64GA004 FAMILY

REGISTER 23-1:

CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

CVREN

bit 7

R/W-0

CVRR

R/W-0

CVR3

R/W-0

CVR2

R/W-0

CVR1

R/W-0

CVR0

CVROE

CVRSS

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7

Unimplemented: Read as ‘0’

CVREN: Comparator Voltage Reference Enable bit

1= CVREF circuit powered on

0= CVREF circuit powered down

bit 6

CVROE: Comparator VREF Output Enable bit

1= CVREF voltage level is output on CVREF pin

0= CVREF voltage level is disconnected from CVREF pin

bit 5

CVRR: Comparator VREF Range Selection bit

1= CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size

0= CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size

bit 4

CVRSS: Comparator VREF Source Selection bit

1= Comparator reference source CVRSRC = VREF+ – VREF-

0= Comparator reference source CVRSRC = AVDD – AVSS

bit 3-0

CVR3:CVR0: Comparator VREF Value Selection 0  CVR3:CVR0  15 bits

When CVRR = 1:

CVREF = (CVR<3:0>/ 24)  (CVRSRC)

When CVRR = 0:

CVREF = 1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC)

DS39881D-page 206

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

24.1.1

CONSIDERATIONS FOR

CONFIGURING PIC24FJ64GA004

FAMILY DEVICES

24.0 SPECIAL FEATURES

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

following sections of the “PIC24F Family

Reference Manual”:

In PIC24FJ64GA004 family devices, the configuration

bytes are implemented as volatile memory. This means

that configuration data must be programmed each time

the device is powered up. Configuration data is stored

in the two words at the top of the on-chip program

memory space, known as the Flash Configuration

Words. Their specific locations are shown in

Table 24-1. These are packed representations of the

actual device Configuration bits, whose actual

locations are distributed among five locations in config-

uration space. The configuration data is automatically

loaded from the Flash Configuration Words to the

proper Configuration registers during device Resets.

•

Section 9. “Watchdog Timer (WDT)”

(DS39697)

Section 32. “High-Level Device

Integration” (DS39719)

Section 33. “Programming and

Diagnostics” (DS39716)

PIC24FJ64GA004 family devices include several

features intended to maximize application flexibility and

reliability, and minimize cost through elimination of

external components. These are:

Note:

Configuration data is reloaded on all types

of device Resets.

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection

TABLE 24-1: FLASH CONFIGURATION

WORD LOCATIONS FOR

PIC24FJ64GA004 FAMILY

DEVICES

• JTAG Boundary Scan Interface

• In-Circuit Serial Programming

• In-Circuit Emulation

Configuration Word

Addresses

Device

24.1 Configuration Bits

1

2

The Configuration bits can be programmed (read as ‘0’),

or left unprogrammed (read as ‘1’), to select various

device configurations. These bits are mapped starting at

program memory location F80000h. A complete list is

shown in Table 24-1. A detailed explanation of the vari-

ous bit functions is provided in Register 24-1 through

Register 24-4.

PIC24FJ16GA

PIC24FJ32GA

PIC24FJ48GA

PIC24FJ64GA

002BFEh

0057FEh

0083FEh

00ABFEh

002BFCh

0057FCh

0083FCh

00ABFCh

When creating applications for these devices, users

should always specifically allocate the location of the

Flash Configuration Word for configuration data. This is

to make certain that program code is not stored in this

address when the code is compiled.

Note that address F80000h is beyond the user program

memory space. In fact, it belongs to the configuration

memory space (800000h-FFFFFFh) which can only be

accessed using table reads and table writes.

The Configuration bits are reloaded from the Flash

Configuration Word on any device Reset.

The upper byte of both Flash Configuration Words in

program memory should always be ‘1111 1111’. This

makes them appear to be NOP instructions in the

remote event that their locations are ever executed by

accident. Since Configuration bits are not implemented

in the corresponding locations, writing ‘1’s to these

locations has no effect on device operation.

 2010 Microchip Technology Inc.

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PIC24FJ64GA004 FAMILY

REGISTER 24-1: CW1: FLASH CONFIGURATION WORD 1

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

r-x

r

R/PO-1

GCP

R/PO-1

GWRP

R/PO-1

DEBUG

r-1

r

R/PO-1

ICS1

R/PO-1

ICS0

JTAGEN

bit 15

bit 8

R/PO-1

WINDIS

U-1

—

R/PO-1

FWPSA

R/PO-1

FWDTEN

WDTPS3

WDTPS2

WDTPS1

WDTPS0

bit 7

bit 0

Legend:

r = Reserved bit

R = Readable bit

PO = Program Once bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared

-n = Value when device is unprogrammed

bit 23-16

bit 15

Unimplemented: Read as ‘1’

Reserved: The value is unknown; program as ‘0’

JTAGEN: JTAG Port Enable bit

bit 14

1= JTAG port is enabled

0= JTAG port is disabled

bit 13

bit 12

bit 11

GCP: General Segment Program Memory Code Protection bit

1= Code protection is disabled

0= Code protection is enabled for the entire program memory space

GWRP: General Segment Code Flash Write Protection bit

1= Writes to program memory are allowed

0= Writes to program memory are disabled

DEBUG: Background Debugger Enable bit

1= Device resets into Operational mode

0= Device resets into Debug mode

bit 10

Reserved: Always maintain as ‘1’

bit 9-8

ICS1:ICS0: Emulator Pin Placement Select bits

11= Emulator EMUC1/EMUD1 pins are shared with PGC1/PGD1

10= Emulator EMUC2/EMUD2 pins are shared with PGC2/PGD2

01= Emulator EMUC3/EMUD3 pins are shared with PGC3/PGD3

00= Reserved; do not use

bit 7

bit 6

FWDTEN: Watchdog Timer Enable bit

1= Watchdog Timer is enabled

0= Watchdog Timer is disabled

WINDIS: Windowed Watchdog Timer Disable bit

1= Standard Watchdog Timer enabled

0= Windowed Watchdog Timer enabled; FWDTEN must be ‘1’

bit 5

bit 4

Unimplemented: Read as ‘1’

FWPSA: WDT Prescaler Ratio Select bit

1= Prescaler ratio of 1:128

0= Prescaler ratio of 1:32

DS39881D-page 208

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 24-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)

bit 3-0 WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits

1111= 1:32,768

1110= 1:16,384

1101= 1:8,192

1100= 1:4,096

1011= 1:2,048

1010= 1:1,024

1001= 1:512

1000= 1:256

0111= 1:128

0110= 1:64

0101= 1:32

0100= 1:16

0011= 1:8

0010= 1:4

0001= 1:2

0000= 1:1

 2010 Microchip Technology Inc.

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PIC24FJ64GA004 FAMILY

REGISTER 24-2: CW2: FLASH CONFIGURATION WORD 2

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

R/PO-1

IESO

R/PO-1

WUTSEL1⁽¹⁾WUTSEL0⁽¹⁾SOSCSEL1⁽¹⁾SOSCSEL0⁽¹⁾

FNOSC2

FNOSC1

FNOSC0

bit 15

bit 8

R/PO-1

U-1

—

R/PO-1

FCKSM1

FCKSM0

OSCIOFCN

IOL1WAY

I2C1SEL

POSCMD1 POSCMD0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value when device is unprogrammed

r = Reserved bit

PO = Program Once bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 23-16

bit 15

Unimplemented: Read as ‘1’

IESO: Internal External Switchover bit

1= IESO mode (Two-Speed Start-up) enabled

0= IESO mode (Two-Speed Start-up) disabled

bit 14-13

bit 12-11

bit 10-8

WUTSEL1:WUTSEL0: Voltage Regulator Standby Mode Wake-up Time Select bits⁽¹⁾

11= Default regulator start-up time used

01= Fast regulator start-up time used

x0= Reserved; do not use

SOSCSEL1:SOSCSEL0: Secondary Oscillator Power Mode Select bits⁽¹⁾

11= Default (High Drive Strength) mode

01= Low-Power (Low Drive Strength) mode

x0= Reserved; do not use

FNOSC2:FNOSC0: Initial Oscillator Select bits

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 7-6

bit 5

FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits

1x= Clock switching and Fail-Safe Clock Monitor are disabled

01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled

OSCIOFCN: OSCO Pin Configuration bit

If POSCMD1:POSCMD0 = 11or 00:

1= OSCO/CLKO/RA3 functions as CLKO (FOSC/2)

0= OSCO/CLKO/RA3 functions as port I/O (RA3)

If POSCMD1:POSCMD0 = 10 or 01:

OSCIOFCN has no effect on OSCO/CLKO/RA3.

bit 4

bit 3

IOL1WAY: IOLOCK One-Way Set Enable bit

1= The OSCCON<IOLOCK> bit can be set once, provided the unlock sequence has been completed.

Once set, the Peripheral Pin Select registers cannot be written to a second time.

0= The OSCCON<IOLOCK> bit can be set and cleared as needed, provided the unlock sequence has

been completed

Unimplemented: Read as ‘1’

DS39881D-page 210

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

REGISTER 24-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED)

bit 2

I2C1SEL: I2C1 Pin Select bit

1= Use default SCL1/SDA1 pins

0= Use alternate SCL1/SDA1 pins

bit 1-0

POSCMD1:POSCMD0: Primary Oscillator Configuration bits

11= Primary oscillator disabled

10= HS Oscillator mode selected

01= XT Oscillator mode selected

00= EC Oscillator mode selected

Note 1: These bits are implemented only in devices with a major silicon revision level of B or later (DEVREV regis-

ter value is 3042h or greater). Refer to Section 28.0 “Packaging Information” in the device data sheet

for the location and interpretation of product date codes.

REGISTER 24-3: DEVID: DEVICE ID REGISTER

U

—

bit 23

bit 16

U

R

—

FAMID7

FAMID6

FAMID5

FAMID4

FAMID3

FAMID2

bit 8

bit 15

R

FAMID1

bit 7

FAMID0

DEV5

DEV4

DEV3

DEV2

DEV1

DEV0

bit 0

Legend: R = Read-only bit

U = Unimplemented bit

bit 23-14

bit 13-6

Unimplemented: Read as ‘1’

FAMID7:FAMID0: Device Family Identifier bits

00010001= PIC24FJ64GA004 family

bit 5-0

DEV5:DEV0: Individual Device Identifier bits

000100= PIC24FJ16GA002

000101= PIC24FJ32GA002

000110= PIC24FJ48GA002

000111= PIC24FJ64GA002

001100= PIC24FJ16GA004

001101= PIC24FJ32GA004

001110= PIC24FJ48GA004

001111= PIC24FJ64GA004

 2010 Microchip Technology Inc.

DS39881D-page 211

PIC24FJ64GA004 FAMILY

REGISTER 24-4: DEVREV: DEVICE REVISION REGISTER

U

—

bit 23

bit 15

bit 16

U

R

—

MAJRV2

bit 8

R

U

R

MAJRV1

bit 7

MAJRV0

—

DOT2

DOT1

DOT0

bit 0

Legend: R = Read-only bit

U = Unimplemented bit

bit 23-9

bit 8-6

bit 5-3

bit 2-0

Unimplemented: Read as ‘0’

MAJRV2:MAJRV0: Major Revision Identifier bits

Unimplemented: Read as ‘0’

DOT2:DOT0: Minor Revision Identifier bits

DS39881D-page 212

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

FIGURE 24-1:

CONNECTIONS FOR THE

ON-CHIP REGULATOR

24.2 On-Chip Voltage Regulator

All of the PIC24FJ64GA004 family of devices power

their core digital logic at a nominal 2.5V. This may

create an issue for designs that are required to operate

at a higher typical voltage, such as 3.3V. To simplify

system design, all devices in the PIC24FJ64GA004

family incorporate an on-chip regulator that allows the

device to run its core logic from VDD.

Regulator Enabled (DISVREG tied to VSS):

3.3V

PIC24FJ64GA

VDD

DISVREG

The regulator is controlled by the DISVREG pin. Tying

VSS to the pin enables the regulator, which in turn, pro-

vides power to the core from the other VDD pins. When

the regulator is enabled, a low-ESR capacitor (such as

ceramic) must be connected to the VDDCORE/VCAP pin

(Figure 24-1). This helps to maintain the stability of the

regulator. The recommended value for the filter capacitor

is provided in Section 27.1 “DC Characteristics”.

VDDCORE/VCAP

CEFC

(10 F typ)

VSS

Regulator Disabled (DISVREG tied to VDD):

(1)

2.5V

3.3V

If DISVREG is tied to VDD, the regulator is disabled. In

this case, separate power for the core logic at a nomi-

nal 2.5V must be supplied to the device on the

VDDCORE/VCAP pin to run the I/O pins at higher voltage

levels, typically 3.3V. Alternatively, the VDDCORE/VCAP

and VDD pins can be tied together to operate at a lower

nominal voltage. Refer to Figure 24-1 for possible

configurations.

PIC24FJ64GA

VDD

DISVREG

VDDCORE/VCAP

VSS

24.2.1

VOLTAGE REGULATOR TRACKING

MODE AND LOW-VOLTAGE

DETECTION

Regulator Disabled (VDD tied to VDDCORE):

(1)

2.5V

When it is enabled, the on-chip regulator provides a

constant voltage of 2.5V nominal to the digital core

logic.

PIC24FJ64GA

VDD

DISVREG

The regulator can provide this level from a VDD of about

2.5V, all the way up to the device’s VDDMAX. It does not

have the capability to boost VDD levels below 2.5V. In

order to prevent “brown out” conditions when the volt-

age drops too low for the regulator, the regulator enters

Tracking mode. In Tracking mode, the regulator output

follows VDD, with a typical voltage drop of 100 mV.

VDDCORE/VCAP

VSS

Note 1: These are typical operating voltages. Refer

to Section 27.1 “DC Characteristics” for

the full operating ranges of VDD and

VDDCORE.

When the device enters Tracking mode, it is no longer

possible to operate at full speed. To provide information

about when the device enters Tracking mode, the

on-chip regulator includes a simple, Low-Voltage

Detect circuit. When VDD drops below full-speed oper-

ating voltage, the circuit sets the Low-Voltage Detect

Interrupt Flag, LVDIF (IFS4<8>). This can be used to

generate an interrupt and put the application into a

low-power operational mode, or trigger an orderly

shutdown.

24.2.2

ON-CHIP REGULATOR AND POR

When the voltage regulator is enabled, it takes approxi-

mately 20 s for it to generate output. During this time,

designated as TSTARTUP, code execution is disabled.

TSTARTUP is applied every time the device resumes

operation after any power-down, including Sleep mode.

Low-Voltage Detection is only available when the

regulator is enabled.

If the regulator is disabled, a separate Power-up Timer

(PWRT) is automatically enabled. The PWRT adds a

fixed delay of 64 ms nominal delay at device start-up.

 2010 Microchip Technology Inc.

DS39881D-page 213

PIC24FJ64GA004 FAMILY

24.2.3

When

ON-CHIP REGULATOR AND BOR

the on-chip regulator is enabled,

24.3 Watchdog Timer (WDT)

For PIC24FJ64GA004 family devices, the WDT is

driven by the LPRC oscillator. When the WDT is

enabled, the clock source is also enabled.

PIC24FJ64GA004 family devices also have a simple

brown-out capability. If the voltage supplied to the reg-

ulator is inadequate to maintain the tracking level, the

regulator Reset circuitry will generate a Brown-out

Reset. This event is captured by the BOR flag bit

(RCON<1>). The brown-out voltage levels are speci-

fied in Section 27.1 “DC Characteristics”.

The nominal WDT clock source from LPRC is 31 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the FWPSA Configuration bit.

With a 31 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode, or

4 ms in 7-bit mode.

24.2.4

POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up

requirements for the device. If the application does not

use the regulator, then strict power-up conditions must

be adhered to. While powering up, VDDCORE must

never exceed VDD by 0.3 volts.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPS3:WDTPS0

Configuration bits (Flash Configuration Word 1<3:0>),

which allow the selection of a total of 16 settings, from

1:1 to 1:32,768. Using the prescaler and postscaler,

time-out periods ranging from 1 ms to 131 seconds can

be achieved.

Note:

For more information, see Section 27.0

“Electrical Characteristics”.

24.2.5

VOLTAGE REGULATOR STANDBY

MODE

The WDT, prescaler and postscaler are reset:

• On any device Reset

When enabled, the on-chip regulator always consumes

a small incremental amount of current over IDD/IPD,

including when the device is in Sleep mode, even

though the core digital logic does not require power. To

provide additional savings in applications where power

resources are critical, the regulator automatically

places itself into Standby mode whenever the device

goes into Sleep mode. This feature is controlled by the

VREGS bit (RCON<8>). By default, this bit is cleared,

which enables Standby mode.

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits), or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAVinstruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

• By a CLRWDTinstruction during normal execution

For select PIC24FJ64GA004 family devices, the time

required for regulator wake-up from Standby mode is

controlled by the WUTSEL<1:0> Configuration bits

(CW2<14:13>). The default wake-up time for all

devices is 190 s. Where the WUTSEL Configuration

bits are implemented, a fast wake-up option is also

available. When WUTSEL<1:0> = 01, the regulator

wake-up time is 25 s.

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the device will wake the device and code execution will

continue from where the PWRSAVinstruction was exe-

cuted. The corresponding SLEEP or IDLE bits

(RCON<3:2>) will need to be cleared in software after

the device wakes up.

The WDT Flag bit, WDTO (RCON<4>), is not auto-

matically cleared following a WDT time-out. To detect

subsequent WDT events, the flag must be cleared in

software.

Note:

This feature is implemented only on

PIC24FJ64GA004 family devices with a

major silicon revision level of B or later

(DEVREV register value is 3042h or

greater).

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

When the regulator’s Standby mode is turned off

(VREGS = 1), Flash program memory stays powered

in Sleep mode and the device can wake-up in less than

10 s. When VREGS is set, the power consumption

while in Sleep mode will be approximately 40 A higher

than power consumption when the regulator is allowed

to enter Standby mode.

DS39881D-page 214

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

24.3.1

WINDOWED OPERATION

24.3.2

CONTROL REGISTER

The Watchdog Timer has an optional Fixed Window

mode of operation. In this Windowed mode, CLRWDT

instructions can only reset the WDT during the last 1/4

of the programmed WDT period. A CLRWDTinstruction

executed before that window causes a WDT Reset,

similar to a WDT time-out.

The WDT is enabled or disabled by the FWDTEN

Configuration bit. When the FWDTEN Configuration bit

is set, the WDT is always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN

control bit is cleared on any device Reset. The software

WDT option allows the user to enable the WDT for

critical code segments and disable the WDT during

non-critical segments for maximum power savings.

Windowed WDT mode is enabled by programming the

WINDIS Configuration bit (CW1<6>) to ‘0’.

FIGURE 24-2:

WDT BLOCK DIAGRAM

SWDTEN

FWDTEN

LPRC Control

Wake from Sleep

FWPSA

WDTPS3:WDTPS0

Prescaler

(5-bit/7-bit)

WDT

Counter

Postscaler

WDT Overflow

1:1 to 1:32.768

LPRC Input

Reset

31 kHz

1 ms/4 ms

All Device Resets

Transition to

New Clock Source

Exit Sleep or

Idle Mode

CLRWDTInstr.

PWRSAVInstr.

Sleep or Idle Mode

24.5.1

CONFIGURATION REGISTER

PROTECTION

24.4 JTAG Interface

PIC24FJ64GA004 family devices implement a JTAG

interface, which supports boundary scan device

testing.

The Configuration registers are protected against

inadvertent or unwanted changes or reads in two ways.

The primary protection method is the same as that of

the RP registers – shadow registers contain a compli-

mentary value which is constantly compared with the

actual value.

24.5 Program Verification and

Code Protection

For all devices in the PIC24FJ64GA004 family of

devices, the on-chip program memory space is treated

as a single block. Code protection for this block is

controlled by one Configuration bit, GCP. This bit

inhibits external reads and writes to the program

memory space. It has no direct effect in normal

execution mode.

To safeguard against unpredictable events, Configura-

tion bit changes resulting from individual cell level

disruptions (such as ESD events) will cause a parity

error and trigger a device Reset.

The data for the Configuration registers is derived from

the Flash Configuration Words in program memory.

When the GCP bit is set, the source data for device

configuration is also protected as a consequence.

Write protection is controlled by the GWRP bit in the

Configuration Word. When GWRP is programmed to

‘0’, internal write and erase operations to program

memory are blocked.

 2010 Microchip Technology Inc.

DS39881D-page 215

PIC24FJ64GA004 FAMILY

24.6

In-Circuit Serial Programming

24.7 In-Circuit Debugger

PIC24FJ64GA004 family microcontrollers can be seri-

ally programmed while in the end application circuit.

This is simply done with two lines for clock (PGCx) and

data (PGDx) and three other lines for power, ground

and the programming voltage. This allows customers to

manufacture boards with unprogrammed devices and

then program the microcontroller just before shipping

the product. This also allows the most recent firmware

or a custom firmware to be programmed.

When MPLAB^®ICD 2 is selected as a debugger, the

in-circuit debugging functionality is enabled. This func-

tion allows simple debugging functions when used with

MPLAB IDE. Debugging functionality is controlled

through the EMUCx (Emulation/Debug Clock) and

EMUDx (Emulation/Debug Data) pins.

To use the in-circuit debugger function of the device,

the design must implement ICSP connections to

MCLR, VDD, VSS, PGCx, PGDx and the

EMUDx/EMUCx pin pair. In addition, when the feature

is enabled, some of the resources are not available for

general use. These resources include the first 80 bytes

of data RAM and two I/O pins.

DS39881D-page 216

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

25.1 MPLAB Integrated Development

Environment Software

25.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

 2010 Microchip Technology Inc.

DS39881D-page 217

PIC24FJ64GA004 FAMILY

25.2 MPASM Assembler

25.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

25.6 MPLAB SIM Software Simulator

25.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 and PIC24 families of microcontrol-

lers and the dsPIC30 and dsPIC33 family of digital sig-

nal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

25.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS39881D-page 218

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

25.7 MPLAB ICE 2000

High-Performance

25.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

25.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

25.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE probe is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB IDE, new devices will be supported,

and new features will be added, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

 2010 Microchip Technology Inc.

DS39881D-page 219

PIC24FJ64GA004 FAMILY

25.11 PICSTART Plus Development

Programmer

25.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

25.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash memory microcontrollers. The PICkit 2 Starter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler, and is designed to help get up to speed

quickly using PIC^®microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS39881D-page 220

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

The literal instructions that involve data movement may

use some of the following operands:

26.0 INSTRUCTION SET SUMMARY

Note:

This chapter is a brief summary of the

PIC24F instruction set architecture, and is

not intended to be a comprehensive

reference source.

• A literal value to be loaded into a W register or file

register (specified by the value of ‘k’)

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

The PIC24F instruction set adds many enhancements

to the previous PIC^®MCU instruction sets, while main-

taining an easy migration from previous PIC MCU

instruction sets. Most instructions are a single program

memory word. Only three instructions require two

program memory locations.

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand which is a register ‘Wb’

without any address modifier

• The second source operand which is a literal

value

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction. The instruction set is

highly orthogonal and is grouped into four basic

categories:

• The destination of the result (only if not the same

as the first source operand) which is typically a

register ‘Wd’ with or without an address modifier

The control instructions may use some of the following

operands:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• A program memory address

• The mode of the table read and table write

instructions

• Control operations

All instructions are a single word, except for certain

double-word instructions, which were made dou-

ble-word instructions so that all the required informa-

tion is available in these 48 bits. In the second word, the

8 MSbs are ‘0’s. If this second word is executed as an

instruction (by itself), it will execute as a NOP.

Table 26-1 shows the general symbols used in

describing the instructions. The PIC24F instruction set

summary in Table 26-2 lists all the instructions, along

with the status flags affected by each instruction.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles, with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all table

reads and writes, and RETURN/RETFIE instructions,

which are single-word instructions but take two or three

cycles.

• The first source operand which is typically a

register ‘Wb’ without any address modifier

• The second source operand which is typically a

register ‘Ws’ with or without an address modifier

• The destination of the result which is typically a

register ‘Wd’ with or without an address modifier

However, word or byte-oriented file register instructions

have two operands:

Certain instructions that involve skipping over the sub-

sequent instruction require either two or three cycles if

the skip is performed, depending on whether the

instruction being skipped is a single-word or two-word

instruction. Moreover, double-word moves require two

cycles. The double-word instructions execute in two

instruction cycles.

• The file register specified by the value ‘f’

• The destination, which could either be the file

register ‘f’ or the W0 register, which is denoted as

‘WREG’

Most bit-oriented instructions (including simple

rotate/shift instructions) have two operands:

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register

(specified by a literal value or indirectly by the

contents of register ‘Wb’)

 2010 Microchip Technology Inc.

DS39881D-page 221

PIC24FJ64GA004 FAMILY

TABLE 26-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

(text)

[text]

{ }

Means literal defined by “text”

Means “content of text”

Means “the location addressed by text”

Optional field or operation

<n:m>

.b

Register bit field

Byte mode selection

.d

Double-Word mode selection

.S

Shadow register select

.w

Word mode selection (default)

bit4

4-bit bit selection field (used in word addressed instructions) {0...15}

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Absolute address, label or expression (resolved by the linker)

File register address {0000h...1FFFh}

1-bit unsigned literal {0,1}

C, DC, N, OV, Z

Expr

f

lit1

lit4

4-bit unsigned literal {0...15}

lit5

5-bit unsigned literal {0...31}

lit8

8-bit unsigned literal {0...255}

lit10

lit14

lit16

lit23

None

PC

10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal {0...16384}

16-bit unsigned literal {0...65535}

23-bit unsigned literal {0...8388608}; LSB must be ‘0’

Field does not require an entry, may be blank

Program Counter

Slit10

Slit16

Slit6

Wb

10-bit signed literal {-512...511}

16-bit signed literal {-32768...32767}

6-bit signed literal {-16...16}

Base W register {W0..W15}

Wd

Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register 

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Wn

Dividend, Divisor working register pair (direct addressing)

One of 16 working registers {W0..W15}

Wnd

Wns

One of 16 destination working registers {W0..W15}

One of 16 source working registers {W0..W15}

WREG

Ws

W0 (working register used in file register instructions)

Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Wso

DS39881D-page 222

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 26-2: INSTRUCTION SET OVERVIEW

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

ADD

ADDC

AND

ASR

ADD

ADDC

AND

ASR

BCLR

BRA

BSET

BSW.C

BSW.Z

BTG

BTSC

f

f = f + WREG

1

C, DC, N, OV, Z

N, Z

f,WREG

WREG = f + WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

Wd = lit10 + Wd

1

Wd = Wb + Ws

1

Wd = Wb + lit5

1

f = f + WREG + (C)

1

f,WREG

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

Wd = Wb + lit5 + (C)

f = f .AND. WREG

1

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

f,WREG

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

Wd = Wb .AND. Ws

1

N, Z

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

N, Z

1

N, Z

Wd = Wb .AND. lit5

1

N, Z

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

1

C, N, OV, Z

N, Z

f,WREG

1

Ws,Wd

1

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

Ws,#bit4

C,Expr

1

N, Z

BCLR

BRA

1

None

Bit Clear Ws

1

None

Branch if Carry

1 (2)

2

None

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if Greater than or Equal

Branch if Unsigned Greater than or Equal

Branch if Greater than

Branch if Unsigned Greater than

Branch if Less than or Equal

Branch if Unsigned Less than or Equal

Branch if Less than

None

Branch if Unsigned Less than

Branch if Negative

None

NC,Expr

NN,Expr

NOV,Expr

NZ,Expr

OV,Expr

Expr

Branch if Not Carry

None

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

None

Branch if Overflow

None

Branch Unconditionally

Branch if Zero

None

Z,Expr

1 (2)

2

None

Wn

Computed Branch

None

BSET

BSW

f,#bit4

Ws,#bit4

Ws,Wb

Bit Set f

1

None

Bit Set Ws

1

None

Write C bit to Ws<Wb>

Write Z bit to Ws<Wb>

Bit Toggle f

1

None

Ws,Wb

1

None

BTG

f,#bit4

Ws,#bit4

f,#bit4

1

None

Bit Toggle Ws

1

None

BTSC

Bit Test f, Skip if Clear

1

None

(2 or 3)

BTSC

Ws,#bit4

Bit Test Ws, Skip if Clear

1

None

(2 or 3)

 2010 Microchip Technology Inc.

DS39881D-page 223

PIC24FJ64GA004 FAMILY

TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

f,#bit4

Description

Bit Test f, Skip if Set

Words Cycles

BTSS

1

None

(2 or 3)

Ws,#bit4

Bit Test Ws, Skip if Set

1

None

(2 or 3)

BTST

f,#bit4

Ws,#bit4

Ws,Wb

Bit Test f

1

2

1

2

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Bit Test Ws to C

C

Bit Test Ws to Z

Z

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call Subroutine

C

Ws,Wb

Z

BTSTS

f,#bit4

Z

BTSTS.C Ws,#bit4

BTSTS.Z Ws,#bit4

C

Z

CALL

CLR

CALL

CLR

lit23

Wn

None

Call Indirect Subroutine

f = 0x0000

None

f

None

CLR

WREG

Ws

WREG = 0x0000

Ws = 0x0000

None

CLR

None

CLRWDT

COM

CLRWDT

Clear Watchdog Timer

WDTO, Sleep

COM

CP

f

f = f

1

N, Z

f,WREG

Ws,Wd

f

WREG = f

N, Z

Wd = Ws

N, Z

CP

Compare f with WREG

Compare Wb with lit5

Compare Wb with Ws (Wb – Ws)

Compare f with 0x0000

Compare Ws with 0x0000

Compare f with WREG, with Borrow

Compare Wb with lit5, with Borrow

C, DC, N, OV, Z

CP

Wb,#lit5

Wb,Ws

f

CP

CP0

CPB

CP0

CPB

Ws

f

Wb,#lit5

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb – Ws – C)

CPSEQ

CPSGT

CPSLT

CPSNE

CPSEQ

CPSGT

CPSLT

CPSNE

Wb,Wn

Compare Wb with Wn, Skip if =

Compare Wb with Wn, Skip if >

Compare Wb with Wn, Skip if <

Compare Wb with Wn, Skip if 

1

None

(2 or 3)

1

(2 or 3)

1

(2 or 3)

1

(2 or 3)

DAW

DEC

DAW

Wn

Wn = Decimal Adjust Wn

f = f –1

1

C

DEC

f

C, DC, N, OV, Z

None

DEC

f,WREG

Ws,Wd

f

WREG = f –1

1

DEC

Wd = Ws – 1

1

DEC2

DISI

DIV.SW

DIV.SD

DIV.UW

DIV.UD

EXCH

FF1L

FF1R

f = f – 2

1

f,WREG

Ws,Wd

#lit14

Wm,Wn

Wns,Wnd

Ws,Wnd

WREG = f – 2

1

Wd = Ws – 2

1

DISI

DIV

Disable Interrupts for k Instruction Cycles

Signed 16/16-bit Integer Divide

Signed 32/16-bit Integer Divide

Unsigned 16/16-bit Integer Divide

Unsigned 32/16-bit Integer Divide

Swap Wns with Wnd

1

18

1

N, Z, C, OV

None

EXCH

FF1L

FF1R

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

1

C

1

C

DS39881D-page 224

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

GOTO

INC

Expr

Go to Address

Go to Indirect

f = f + 1

2

1

2

1

2

1

None

Wn

None

INC

f

C, DC, N, OV, Z

N, Z

INC

f,WREG

WREG = f + 1

Wd = Ws + 1

f = f + 2

INC

Ws,Wd

INC2

IOR

INC2

IOR

f

f,WREG

WREG = f + 2

Wd = Ws + 2

f = f .IOR. WREG

Ws,Wd

f

IOR

f,WREG

WREG = f .IOR. WREG

N, Z

IOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

#lit14

Wd = lit10 .IOR. Wd

N, Z

IOR

Wd = Wb .IOR. Ws

N, Z

IOR

Wd = Wb .IOR. lit5

N, Z

LNK

LSR

LNK

Link Frame Pointer

None

LSR

f

f = Logical Right Shift f

C, N, OV, Z

N, Z

LSR

f,WREG

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Move f to Wn

LSR

Ws,Wd

LSR

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,Wn

LSR

N, Z

MOV

None

MOV

[Wns+Slit10],Wnd

f

Move [Wns+Slit10] to Wnd

Move f to f

None

MOV

N, Z

MOV

f,WREG

Move f to WREG

N, Z

MOV

#lit16,Wn

#lit8,Wn

Wn,f

Move 16-bit Literal to Wn

None

MOV.b

MOV

Move 8-bit Literal to Wn

None

Move Wn to f

None

MOV

Wns,[Wns+Slit10]

Wso,Wdo

WREG,f

Move Wns to [Wns+Slit10]

Move Ws to Wd

MOV

None

N, Z

MOV

Move WREG to f

MOV.D

MUL.SS

MUL.SU

MUL.US

MUL.UU

MUL.SU

MUL.UU

MUL

Wns,Wd

Move Double from W(ns):W(ns+1) to Wd

Move Double from Ws to W(nd+1):W(nd)

{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)

{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)

{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)

{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)

{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)

{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)

W3:W2 = f * WREG

None

Ws,Wnd

MUL

Wb,Ws,Wnd

Wb,#lit5,Wnd

f

NEG

f

f = f + 1

1

2

1

C, DC, N, OV, Z

None

NEG

f,WREG

Ws,Wd

WREG = f + 1

NEG

Wd = Ws + 1

NOP

POP

NOP

No Operation

NOPR

POP

No Operation

None

f

Pop f from Top-of-Stack (TOS)

Pop from Top-of-Stack (TOS) to Wdo

Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)

Pop Shadow Registers

None

POP

Wdo

Wnd

None

POP.D

POP.S

None

All

PUSH

f

Push f to Top-of-Stack (TOS)

1

2

1

None

PUSH

Wso

Wns

Push Wso to Top-of-Stack (TOS)

Push W(ns):W(ns+1) to Top-of-Stack (TOS)

Push Shadow Registers

PUSH.D

PUSH.S

 2010 Microchip Technology Inc.

DS39881D-page 225

PIC24FJ64GA004 FAMILY

TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

PWRSAV

RCALL

PWRSAV

RCALL

REPEAT

RESET

RETFIE

RETLW

RETURN

RLC

#lit1

Expr

Wn

Go into Sleep or Idle mode

Relative Call

1

2

WDTO, Sleep

None

Computed Call

2

None

REPEAT

#lit14

Wn

Repeat Next Instruction lit14 + 1 times

Repeat Next Instruction (Wn) + 1 times

Software Device Reset

Return from Interrupt

1

None

1

None

RESET

RETFIE

RETLW

RETURN

RLC

1

None

3 (2)

1

None

#lit10,Wn

Return with Literal in Wn

Return from Subroutine

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Wnd = Sign-Extended Ws

f = FFFFh

None

f

C, N, Z

RLC

f,WREG

Ws,Wd

f

1

C, N, Z

RLC

1

C, N, Z

RLNC

RRC

RLNC

RRC

1

N, Z

f,WREG

Ws,Wd

f

1

N, Z

1

N, Z

1

C, N, Z

RRC

f,WREG

Ws,Wd

f

1

C, N, Z

RRC

1

C, N, Z

RRNC

SE

1

N, Z

f,WREG

Ws,Wd

Ws,Wnd

f

1

N, Z

1

N, Z

SE

1

C, N, Z

SETM

SL

1

None

WREG

WREG = FFFFh

1

None

Ws

Ws = FFFFh

1

None

SL

f

f = Left Shift f

1

C, N, OV, Z

N, Z

SL

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

f

WREG = Left Shift f

1

SL

Wd = Left Shift Ws

1

SL

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

f = f – WREG

1

SL

1

N, Z

SUB

1

C, DC, N, OV, Z

SUB

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f – WREG

1

SUB

Wn = Wn – lit10

1

SUB

Wd = Wb – Ws

1

SUB

Wd = Wb – lit5

1

SUBB

f = f – WREG – (C)

1

f,WREG

WREG = f – WREG – (C)

1

SUBB

SUBR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

Wn = Wn – lit10 – (C)

Wd = Wb – Ws – (C)

Wd = Wb – lit5 – (C)

f = WREG – f

1

C, DC, N, OV, Z

SUBR

f,WREG

WREG = WREG – f

Wd = Ws – Wb

Wb,Ws,Wd

Wb,#lit5,Wd

Wd = lit5 – Wb

SUBBR

f

f = WREG – f – (C)

1

C, DC, N, OV, Z

f,WREG

WREG = WREG – f – (C)

SUBBR

SWAP.b

SWAP

Wb,Ws,Wd

Wb,#lit5,Wd

Wn

Wd = Ws – Wb – (C)

1

2

C, DC, N, OV, Z

None

Wd = lit5 – Wb – (C)

SWAP

Wn = Nibble Swap Wn

Wn = Byte Swap Wn

Wn

None

TBLRDH

Ws,Wd

Read Prog<23:16> to Wd<7:0>

None

DS39881D-page 226

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

TBLRDL

TBLWTH

TBLWTL

ULNK

TBLRDL

TBLWTH

TBLWTL

ULNK

XOR

Ws,Wd

Read Prog<15:0> to Wd

1

2

1

None

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

Unlink Frame Pointer

f = f .XOR. WREG

None

N, Z

XOR

f

XOR

f,WREG

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

Wd = Wb .XOR. Ws

N, Z

XOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

N, Z

XOR

N, Z

XOR

Wd = Wb .XOR. lit5

N, Z

ZE

Wnd = Zero-Extend Ws

C, Z, N

 2010 Microchip Technology Inc.

DS39881D-page 227

PIC24FJ64GA004 FAMILY

NOTES:

DS39881D-page 228

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

27.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC24FJ64GA004 family electrical characteristics. Additional information will

be provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24FJ64GA004 family are listed below. Exposure to these maximum rating

conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other

conditions above the parameters indicated in the operation listings of this specification, is not implied.

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +135°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)

Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V

Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin (Note 1)................................................................................................................250 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports (Note 1)....................................................................................................200 mA

Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 27-1).

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

 2010 Microchip Technology Inc.

DS39881D-page 229

PIC24FJ64GA004 FAMILY

27.1 DC Characteristics

FIGURE 27-1:

3.00V

PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

2.75V

2.50V

2.75V

2.35V

PIC24FJ64GA004/32GA004/64GA002/32GA002

2.25V

2.00V

32 MHz

16 MHz

Frequency

For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE – 2V) + 16 MHz.

Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that

VDDCOREVDD3.6V.

FIGURE 27-2:

PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH

(EXTENDED TEMPERATURE)

3.00V

2.75V

2.50V

2.75V

2.35V

PIC24FJ64GA004/32GA004/64GA002/32GA002

2.25V

2.00V

16 MHz

Frequency

24 MHz

For frequencies between 16 MHz and 24 MHz, FMAX = (22.9 MHz/V) * (VDDCORE – 2V) + 16 MHz.

Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that

VDDCOREVDD3.6V.

DS39881D-page 230

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 27-1: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

PIC24FJ64GA004 Family:

Operating Junction Temperature Range

Operating Ambient Temperature Range

TJ

TA

-40

—

+140

+125

°C

Power Dissipation:

Internal Chip Power Dissipation:

PINT = VDD x (IDD –  IOH)

PD

PINT + PI/O

W

I/O Pin Power Dissipation:

PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)

Maximum Allowed Power Dissipation

PDMAX

(TJ – TA)/JA

TABLE 27-2: THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Notes

Package Thermal Resistance, 300 mil SOIC

Package Thermal Resistance, 6x6x0.9 mm QFN

Package Thermal Resistance, 8x8x1 mm QFN

Package Thermal Resistance, 10x10x1 mm TQFP

^JA

JA

^JA

49

33.7

28

—

°C/W (Note 1)

39.3

Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.

 2010 Microchip Technology Inc.

DS39881D-page 231

PIC24FJ64GA004 FAMILY

TABLE 27-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Symbol

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

Operating Voltage

DC10 Supply Voltage

VDD

2.2

VDDCORE

2.0

—

3.6

2.75

—

V

Regulator enabled

Regulator disabled

VDD

VDDCORE

DC12 VDR

RAM Data Retention

1.5

Voltage⁽²⁾

DC16 VPOR

VDD Start Voltage

to ensure internal

Power-on Reset signal

—

VSS

—

V

DC17 SVDD

VDD Rise Rate

to ensure internal

Power-on Reset signal

0.05

V/ms 0-3.3V in 0.1s

0-2.5V in 60 ms

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: This is the limit to which VDD can be lowered without losing RAM data.

DS39881D-page 232

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 27-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

(1)

Parameter No. Typical

Max

Units

Conditions

(2)

Operating Current (IDD): PMD Bits are Set

DC20

0.650

1.2

2.6

4.1

13.5

15

0.850

1.6

3.4

5.4

17.6

20

mA

A

-40°C

DC20a

DC20b

DC20c

DC20d

DC20e

DC20f

DC20g

DC23

+25°C

+85°C

+125°C

-40°C

(3)

(4)

(3)

(4)

(3)

(4)

(3)

(4)

2.0V

3.3V

2.0V

3.3V

2.5V

3.3V

2.0V

3.3V

1 MIPS

+25°C

+85°C

+125°C

-40°C

DC23a

DC23b

DC23c

DC23d

DC23e

DC23f

DC23g

DC24

+25°C

+85°C

+125°C

-40°C

4 MIPS

+25°C

+85°C

+125°C

-40°C

DC24a

DC24b

DC24c

DC24d

DC24e

DC24f

DC24g

DC31

+25°C

+85°C

+125°C

-40°C

16 MIPS

15

20

+25°C

+85°C

+125°C

-40°C

15

20

15

20

13

17

DC31a

DC31b

DC31c

DC31d

DC31e

DC31f

DC31g

13

17

A

+25°C

+85°C

+125°C

-40°C

20

26

A

40

50

A

LPRC (31 kHz)

54

70

A

54

70

A

+25°C

+85°C

+125°C

95

124

260

A

120

A

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the

current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square

wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD.

MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No

peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set.

3: On-chip voltage regulator disabled (DISVREG tied to VDD).

4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect

(BOD) are enabled.

 2010 Microchip Technology Inc.

DS39881D-page 233

PIC24FJ64GA004 FAMILY

TABLE 27-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Parameter

No.

(1)

Typical

Max

Units

Conditions

(2)

Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set

DC40

150

165

250

275

0.55

0.60

0.82

0.91

3

200

220

325

360

0.72

0.8

1.1

1.2

4

A

-40°C

+25°C

+85°C

+125°C

-40°C

DC40a

DC40b

DC40c

DC40d

DC40e

DC40f

DC40g

DC43

(3)

(4)

(3)

(4)

(3)

(4)

(3)

(4)

2.0V

3.3V

2.0V

3.3V

2.5V

3.3V

2.0V

3.3V

A

1 MIPS

A

+25°C

+85°C

+125°C

-40°C

A

mA

DC43a

DC43b

DC43c

DC43d

DC43e

DC43f

DC43g

DC47

+25°C

+85°C

+125°C

-40°C

4 MIPS

+25°C

+85°C

+125°C

-40°C

DC47a

DC47b

DC47c

DC47d

DC47e

DC47f

DC47g

DC50

3

4

+25°C

+85°C

+125°C

-40°C

3

4

3.3

4.4

4.6

5.1

1.1

1.2

1.6

1.8

16 MIPS

3.5

+25°C

+85°C

+125°C

-40°C

3.5

3.9

0.85

0.94

1.2

DC50a

DC50b

DC50c

DC50d

DC50e

DC50f

DC50g

+25°C

+85°C

+125°C

-40°C

FRC (4 MIPS)

1.2

+25°C

+85°C

+125°C

1.2

1.3

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from rail to

rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU,

SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the

Peripheral Module Disable (PMD) bits are set.

3: On-chip voltage regulator disabled (DISVREG tied to VDD).

4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect

(BOD) are enabled.

DS39881D-page 234

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 27-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Parameter

No.

(1)

Typical

Max

Units

Conditions

(2)

Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set

DC51

4

6

A

-40°C

+25°C

+85°C

+125°C

-40°C

DC51a

DC51b

DC51c

DC51d

DC51e

DC51f

DC51g

(3)

(4)

2.0V

3.3V

8

16

50

55

91

180

20

42

70

100

LPRC (31 kHz)

+25°C

+85°C

+125°C

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

2: The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from rail to

rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU,

SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the

Peripheral Module Disable (PMD) bits are set.

3: On-chip voltage regulator disabled (DISVREG tied to VDD).

4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect

(BOD) are enabled.

 2010 Microchip Technology Inc.

DS39881D-page 235

PIC24FJ64GA004 FAMILY

TABLE 27-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Parameter

Typical

No.

(1)

Max

Units

Conditions

(2)

Power-Down Current (IPD): PMD Bits are Set, VREGS Bit is ‘0’

DC60

0.1

0.15

2.2

3.7

15

1

A

-40°C

+25°C

+60°C

+85°C

+125°C

-40°C

DC60a

DC60m

DC60b

DC60j

DC60c

DC60d

DC60n

DC60e

DC60k

DC60f

DC60g

DC60o

DC60h

DC60l

DC61

(3)

7.4

12

50

1

2.0V

0.2

0.25

2.6

4.2

16

1

+25°C

+60°C

+85°C

+125°C

-40°C

(3)

(5)

15

25

100

9

2.5V

3.3V

2.0V

2.5V

3.3V

Base Power-Down Current

3.3

3.5

6.7

9

10

22

30

120

3

+25°C

+60°C

+85°C

+125°C

-40°C

(4)

(3)

(4)

36

1.75

3.5

2.4

4.8

2.8

5.6

DC61a

DC61m

DC61b

DC61j

DC61c

DC61d

DC61n

DC61e

DC61k

DC61f

DC61g

DC61o

DC61h

DC61l

3

+25°C

+60°C

+85°C

+125°C

-40°C

3

6

4

+25°C

+60°C

+85°C

+125°C

-40°C

(5)

4

Watchdog Timer Current: IWDT

4

8

5

+25°C

+60°C

+85°C

+125°C

5

10

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled

high. WDT, etc., are all switched off.

3: On-chip voltage regulator disabled (DISVREG tied to VDD).

4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect

(BOD) are enabled.

5: The  current is the additional current consumed when the module is enabled. This current should be added to

the base IPD current.

DS39881D-page 236

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 27-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Parameter

Typical

No.

(1)

Max

Units

Conditions

(2)

Power-Down Current (IPD): PMD Bits are Set, VREGS Bit is ‘0’

DC62

8

12

18

9

16

23

16

25

18

28

—

A

-40°C

+25°C

+60°C

+85°C

+125°C

-40°C

DC62a

DC62m

DC62b

DC62j

(3)

2.0V

DC62c

DC62d

DC62n

DC62e

DC62k

DC62f

DC62g

DC62o

DC62h

DC62l

12

12.5

20

10.3

13.4

14.0

14.2

23

2

+25°C

+60°C

+85°C

+125°C

-40°C

RTCC + Timer1 w/32 kHz Crystal:

RTCC ITI32

(3)

2.5V

3.3V

(5)

+25°C

+60°C

+85°C

+125°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

(4)

DC63

DC63a

DC63b

DC63c

DC63d

DC63e

DC63f

DC63g

DC63h

2

2.0V⁽³⁾

2.5V⁽³⁾

3.3V⁽⁴⁾

6

2

RTCC + Timer1 w/Low-Power

32 kHz Crystal (SOCSEL<1:0> =

01): RTCC ITI32

2

(5)

7

2

3

7

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled

high. WDT, etc., are all switched off.

3: On-chip voltage regulator disabled (DISVREG tied to VDD).

4: On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect

(BOD) are enabled.

5: The  current is the additional current consumed when the module is enabled. This current should be added to

the base IPD current.

 2010 Microchip Technology Inc.

DS39881D-page 237

PIC24FJ64GA004 FAMILY

TABLE 27-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

VIL

Input Low Voltage⁽⁴⁾

I/O Pins

DI10

VSS

—

0.2 VDD

0.15 VDD

0.2 VDD

0.3 VDD

0.8

V

DI11

DI15

DI16

DI17

DI18

DI19

PMP Pins

PMPTTL = 1

MCLR

OSCI (XT mode)

OSCI (HS mode)

I/O Pins with I²C™ Buffer

SMBus disabled

SMBus enabled

I/O Pins with SMBus

Buffer

VIH

Input High Voltage⁽⁴⁾

DI20

DI21

I/O Pins:

with Analog Functions

Digital Only

0.8 VDD

—

VDD

5.5

V

PMP Pins:

with Analog Functions

Digital Only

0.25 VDD + 0.8

—

VDD

5.5

V

PMPTTL = 1

DI25

DI26

DI27

DI28

MCLR

0.8 VDD

0.7 VDD

—

VDD

V

OSCI (XT mode)

OSCI (HS mode)

I/O Pins with I²C Buffer:

with Analog Functions

Digital Only

0.7 VDD

—

VDD

5.5

V

DI29

I/O Pins with SMBus

Buffer:

with Analog Functions

Digital Only

2.1

—

VDD

5.5

V

v

2.5V  VPIN  VDD

DI30

ICNPU CNxx Pull-up Current

50

250

400

A

VDD = 3.3V, VPIN = VSS

IIL

Input Leakage Current^(2,3)

DI50

DI51

I/O Ports

—

+1

A

VSS  VPIN  VDD,

Pin at high-impedance

Analog Input Pins

VSS  VPIN  VDD,

Pin at high-impedance

DI55

DI56

MCLR

OSCI

—

+1

A

VSS VPIN VDD

VSS VPIN VDD,

XT and HS modes

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Refer to Table 1-2 for I/O pin buffer types.

DS39881D-page 238

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 27-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

(1)

Sym

Characteristic

Min

Typ

Max

Units

Conditions

VOL

Output Low Voltage

DO10

DO16

All I/O pins

—

0.4

V

IOL = 8.5 mA, VDD = 3.6V

IOL = 5.0 mA, VDD = 2.0V

All I/O pins

IOL = 8.0 mA, VDD = 3.6V, 125°C

IOL = 4.5 mA, VDD = 2.0V, 125°C

VOH

Output High Voltage

DO20

DO26

All I/O pins

3

—

V

IOH = -3.0 mA, VDD = 3.6V

1.65

3

IOH = -1.0 mA, VDD = 2.0V

All I/O pins

IOH = -2.5 mA, VDD = 3.6V, 125°C

IOH = -0.5 mA, VDD = 2.0V, 125°C

1.65

Note 1: Data in “Typ” column is at 25°C unless otherwise stated. Parameters are for design guidance only and are not

tested.

TABLE 27-9: DC CHARACTERISTICS: PROGRAM MEMORY

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

Sym

No.

(1)

Characteristic

Min

Typ

Max

Units

Conditions

Program Flash Memory

Cell Endurance

D130

D131

D132B

EP

10000

VMIN

2.25

—

3.6

E/W -40C to +125C

VPR

VDD for Read

V

VMIN = Minimum operating voltage

VPEW VDDCORE for Self-Timed

Write

2.75

D133A

D134

D135

TIW

Self-Timed Write Cycle

Time

—

20

—

3

—

7

—

ms

TRETD Characteristic Retention

Year Provided no other specifications are

violated

IDDP

Supply Current during

Programming

mA

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

 2010 Microchip Technology Inc.

DS39881D-page 239

PIC24FJ64GA004 FAMILY

TABLE 27-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: -40°C < TA < +125°C (unless otherwise stated)

Param

No.

Symbol

Characteristics

Min

Typ

Max

Units

Comments

VRGOUT

VBG

Regulator Output Voltage

—

2.5

1.23

10

—

V

Band Gap Reference Voltage

External Filter Capacitor Value

CEFC

4.7

F

Series resistance < 3 Ohm

recommended;

< 5 Ohm required.

TVREG

Voltage Regulator Start-up

Time

—

10

25

—

s

ms

POR, BOR or when

VREGS = 1

VREGS = 0,

WUTSEL<1:0> = 01⁽¹⁾

190

VREGS = 0,

WUTSEL<1:0> = 11⁽²⁾

TPWRT

64

DISVREG = VDD

Note 1: Available only in devices with a major silicon revision level of B or later (DEVREV register value is 3042h

or greater).

2: WUTSEL Configuration bits setting is applicable only in devices with a major silicon revision level of B or

later. This specification also applies to all devices prior to revision level B whenever VREGS = 0.

DS39881D-page 240

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

27.2 AC Characteristics and Timing Parameters

The information contained in this section defines the PIC24FJ64GA004 family AC characteristics and timing

parameters.

TABLE 27-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

AC CHARACTERISTICS

-40°C  TA  +125°C for Extended

Operating voltage VDD range as described in Section 27.1 “DC Characteristics”.

FIGURE 27-3:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSCO

VDD/2

Load Condition 2 – for OSCO

CL

RL

VSS

CL

RL = 464

CL = 50 pF for all pins except OSCO

15 pF for OSCO output

VSS

TABLE 27-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param

Symbol

Characteristic

Min

Typ⁽¹⁾Max Units

Conditions

No.

DO50 COSC2

OSCO/CLKO pin

—

15

pF In XT and HS modes when

external clock is used to drive

OSCI.

DO56 CIO

DO58 CB

All I/O Pins and OSCO

SCLx, SDAx

—

50

pF EC mode.

pF In I²C™ mode.

400

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

 2010 Microchip Technology Inc.

DS39881D-page 241

PIC24FJ64GA004 FAMILY

FIGURE 27-4:

EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q3

Q2

OSCI

OS20

OS25

OS30 OS30

OS31 OS31

CLKO

OS40

OS41

TABLE 27-13: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.0 to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

AC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

OS10 FOSC External CLKI Frequency

(External clocks allowed

DC

4

DC

4

—

32

8

24

6

MHz EC, -40°C  TA  +85°C

MHz ECPLL, -40°C  TA  +85°C

MHz EC, -40°C  TA  +125°C

MHz ECPLL, -40°C  TA  +125°C

only in EC mode)

Oscillator Frequency

3

10

31

3

—

10

8

32

33

6

MHz XT

MHz XTPLL, -40°C  TA  +85°C

MHz HS, -40°C  TA  +85°C

kHz SOSC

MHz XTPLL, -40°C  TA  +125°C

MHz HS, -40°C  TA  +125°C

10

24

OS20 TOSC TOSC = 1/FOSC

—

See parameter OS10

for FOSC value

OS25 TCY

Instruction Cycle Time⁽²⁾

62.5

—

DC

—

ns

OS30 TosL, External Clock in (OSCI)

TosH High or Low Time

0.45 x TOSC

EC

OS31 TosR, External Clock in (OSCI)

TosF Rise or Fall Time

—

20

ns

OS40 TckR CLKO Rise Time⁽³⁾

OS41 TckF CLKO Fall Time⁽³⁾

—

6

10

ns

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with

the device executing code. Exceeding these specified limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an

external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time

limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the

Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

DS39881D-page 242

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 27-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

AC CHARACTERISTICS

Param

No.

Sym

Characteristic⁽¹⁾

Min

3

Typ⁽²⁾

—

Max

8

Units

Conditions

OS50 FPLLI PLL Input Frequency

Range

MHz ECPLL, HSPLL, XTPLL

modes, -40°C  TA  +85°C

MHz ECPLL, HSPLL, XTPLL

modes, -40°C  TA  +125°C

3

—

6

OS51 FSYS PLL Output Frequency

Range

8

—

32

24

MHz -40°C  TA  +85°C

MHz -40°C  TA  +125°C

OS52 TLOCK PLL Start-up Time

(Lock Time)

—

2

ms

OS53 DCLK CLKO Stability (Jitter)

-2

1

2

%

Measured over 100 ms period

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 27-15: AC CHARACTERISTICS: INTERNAL RC ACCURACY

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

Internal FRC Accuracy @ 8 MHz⁽¹⁾

F20

FRC

-2

-5

—

2

5

%

25°C

-40°C  TA +125°C

3.0V  VDD  3.6V

Note 1: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.

TABLE 27-16: INTERNAL RC ACCURACY

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

LPRC @ 31 kHz⁽¹⁾

F21

-15

-20

—

15

20

%

25°C

-40°C  TA +85°C

3.0V  VDD  3.6V

125°C

Note 1: Change of LPRC frequency as VDD changes.

 2010 Microchip Technology Inc.

DS39881D-page 243

PIC24FJ64GA004 FAMILY

FIGURE 27-5:

CLKO AND I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

(Output)

New Value

Old Value

DO31

DO32

Note: Refer to Figure 27-3 for load conditions.

TABLE 27-17: CLKO AND I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

AC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

DO31 TIOR Port Output Rise Time

DO32 TIOF Port Output Fall Time

—

20

10

—

25

—

ns

DI35

TINP

INTx pin High or Low

Time (output)

DI40

TRBP CNx High or Low Time

(input)

2

—

TCY

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

DS39881D-page 244

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

TABLE 27-18: ADC MODULE SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Device Supply

AD01 AVDD

AD02 AVSS

Module VDD Supply

Module VSS Supply

Greater of

VDD – 0.3

or 2.0

—

Lesser of

VDD + 0.3

or 3.6

V

VSS – 0.3

VSS + 0.3

Reference Inputs

AD05 VREFH

AD06 VREFL

AD07 VREF

Reference Voltage High

Reference Voltage Low

AVSS + 1.7

AVSS

—

AVDD

V

AVDD – 1.7

AVDD + 0.3

Absolute Reference

Voltage

AVSS – 0.3

Analog Input

AD10 VINH-VINL Full-Scale Input Span

VREFL

—

VREFH

AVDD + 0.3

AVDD/2

V

(Note 2)

AD11 VIN

AD12 VINL

Absolute Input Voltage

AVSS – 0.3

—

Absolute VINL Input

Voltage

AD17 RIN

RecommendedImpedance

of Analog Voltage Source

—

2.5K



10-bit

ADC Accuracy

AD20b Nr

Resolution

—

10

±1

—

bits

AD21b INL

Integral Nonlinearity

<±2

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

AD22b DNL

AD23b GERR

AD24b EOFF

AD25b —

Differential Nonlinearity

Gain Error

—

±1

—

<±1.25

±3

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

Offset Error

±2

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

Monotonicity⁽¹⁾

—

Guaranteed

Note 1: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.

2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference.

 2010 Microchip Technology Inc.

DS39881D-page 245

PIC24FJ64GA004 FAMILY

TABLE 27-19: ADC CONVERSION TIMING REQUIREMENTS⁽¹⁾

Standard Operating Conditions: 2.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Clock Parameters

AD50

AD51

TAD

tRC

ADC Clock Period

75

—

ns

TCY = 75 ns, AD1CON3

in default state

ADC Internal RC Oscillator

Period

250

Conversion Rate

AD55

AD56

AD57

tCONV

FCNV

tSAMP

Conversion Time

Throughput Rate

Sample Time

—

12

—

1

—

500

—

TAD

ksps

TAD

AVDD  2.7V

Clock Parameters

AD61

tPSS

Sample Start Delay from setting

Sample bit (SAMP)

2

—

3

TAD

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

DS39881D-page 246

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

28.0 PACKAGING INFORMATION

28.1 Package Marking Information

28-Lead SPDIP

Example

XXXXXXXXXXXXXXXXX

PIC24FJ16GA002

e

3

-I/SP

YYWWNNN

0810017

28-Lead SSOP

Example

24FJ16GA002

XXXXXXXXXXXX

e

3

/SS

YYWWNNN

0810017

28-Lead SOIC (.300”)

Example

e

3

XXXXXXXXXXXXXXXXXXXX

PIC24FJ16GA002/SO

0810017

YYWWNNN

28-Lead QFN

Example

XXXXXXXX

YYWWNNN

24FJ48GA

002/ML

0810017

e

3

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2010 Microchip Technology Inc.

DS39881D-page 247

PIC24FJ64GA004 FAMILY

44-Lead QFN

Example

XXXXXXXXXX

YYWWNNN

24FJ32GA

e

3

004-I/ML

0810017

44-Lead TQFP

Example

XXXXXXXXXX

YYWWNNN

24FJ32GA

004-I/PT

0810017

e

3

DS39881D-page 248

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

28.2 Package Details

The following sections give the technical details of the packages.

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N

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ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ

-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢁꢕꢀꢕ/ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ

ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ

1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢜꢕ1

 2010 Microchip Technology Inc.

DS39881D-page 249

PIC24FJ64GA004 FAMILY

ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇꢈ#$ꢊꢋꢉꢇꢈꢙꢅꢎꢎꢇ%ꢓꢐꢎꢊꢋꢄꢇꢕꢈꢈꢖꢇMꢇ&'ꢗꢘꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜꢈꢈ%ꢍ

!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ

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D

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e

c

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L1

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DS39881D-page 250

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

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1

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3

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ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ

ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ

-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ

ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ

1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢘꢎ1

 2010 Microchip Technology Inc.

DS39881D-page 251

PIC24FJ64GA004 FAMILY

ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ,ꢓꢅꢆꢇ-ꢎꢅꢐ)ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ.ꢄꢇꢕ/ꢃꢖꢇMꢇ010ꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ,-!

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ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

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ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ

ꢎꢁ ꢂꢆꢌ4ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ

-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ

1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢕꢘ1

DS39881D-page 252

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ,ꢓꢅꢆꢇ-ꢎꢅꢐ)ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ.ꢄꢇꢕ/ꢃꢖꢇMꢇ010ꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ,-!

2ꢊꢐ#ꢇꢘ'&&ꢇꢙꢙꢇ+ꢛꢋꢐꢅꢑꢐꢇꢃꢄꢋ.ꢐ#

!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ

ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

 2010 Microchip Technology Inc.

DS39881D-page 253

PIC24FJ64GA004 FAMILY

33ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ,ꢓꢅꢆꢇ-ꢎꢅꢐ)ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ.ꢄꢇꢕ/ꢃꢖꢇMꢇꢁ1ꢁꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ,-!

!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ

ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

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ꢎꢁ ꢂꢆꢌ4ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ

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1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ

ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢕ-1

DS39881D-page 254

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

33ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ,ꢓꢅꢆꢇ-ꢎꢅꢐ)ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ.ꢄꢇꢕ/ꢃꢖꢇMꢇꢁ1ꢁꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ,-!

!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ

ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

 2010 Microchip Technology Inc.

DS39881D-page 255

PIC24FJ64GA004 FAMILY

33ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ4#ꢊꢋꢇ,ꢓꢅꢆꢇ-ꢎꢅꢐ5ꢅꢑꢉꢇꢕꢍ4ꢖꢇMꢇ6ꢘ16ꢘ16ꢇꢙꢙꢇꢚꢛꢆꢌ)ꢇꢀ'ꢘꢘꢇꢙꢙꢇꢜ4,-ꢍ

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DS39881D-page 256

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

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 2010 Microchip Technology Inc.

DS39881D-page 257

PIC24FJ64GA004 FAMILY

NOTES:

DS39881D-page 258

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

APPENDIX A: REVISION HISTORY

Revision A (March 2007)

Original data sheet for the PIC24FJ64GA004 family of

devices.

Revision B (March 2007)

Changes to Table 26-8; packaging diagrams updated.

Revision C (January 2008)

• Update of electrical specifications to include DC

characteristics for Extended Temperature

devices.

• Update for A/D converter chapter to include

information on internal band gap voltage

reference.

• Added “Appendix B: “Additional Guidance for

PIC24FJ64GA004 Family Applications”.

• General revisions to incorporate corrections

included in document errata to date (DS80333).

Revision D (January 2010)

• Update of electrical specifications to include 60°C

specifications for power-down current to DC

characteristics.

• Removes references to JTAG programming

throughout the document.

• Other minor typographic corrections throughout.

 2010 Microchip Technology Inc.

DS39881D-page 259

PIC24FJ64GA004 FAMILY

FIGURE B-1: POWER REDUCTION

APPENDIX B: ADDITIONAL

GUIDANCE FOR

PIC24FJ64GA004

FAMILY

EXAMPLE FOR CONSTANT

VOLTAGE SUPPLIES

PIC24FJ64GA

APPLICATIONS

VDD

B.1

Additional Methods for Power

Reduction

DISVREG

D1

3.0V

Coin Cell

2.3V

VDDCORE

Devices in the PIC24FJ64GA004 family include a num-

ber of core features to significantly reduce the applica-

tion’s power requirements. For truly power-sensitive

applications, it is possible to further reduce the

application’s power demands by taking advantage of

the device’s regulator architecture. These methods

help decrease power in two ways: by disabling the

internal voltage regulator to eliminate its power con-

sumption, and by reducing the voltage on VDDCORE to

lower the device’s dynamic current requirements.

Using these methods, it is possible to reduce Sleep

currents (IPD) from 3.5 A to 250 nA (typical values,

refer to specifications DC60d and DC60g in

Table 27-6). For dynamic power consumption, the

reduction in VDDCORE from 2.5V, provided by the

regulator, to 2.0V can provide a power reduction of

about 30%.

VSS

A similar method can be used for non-regulated

sources (Figure B-2). In this case, it can be beneficial

to use a low quiescent current external voltage regula-

tor. Devices such as the MCP1700 consume only 1 A

to regulate to 2V or 2.5V, which is lower than the

current required to power the internal voltage regulator.

FIGURE B-2: POWER REDUCTION

EXAMPLE FOR

NON-REGULATED SUPPLIES

When using a regulated power source or a battery with

a constant output voltage, it is possible to decrease

power consumption by disabling the regulator. In this

case (Figure B-1), a simple diode can be used to

reduce the voltage from 3V or greater to the 2V-2.5V

required for VDDCORE. This method is only advised on

power supplies, such as Lithium Coin cells, which

maintain a constant voltage over the life of the battery.

PIC24FJ64GA

VDD

DISVREG

3.3V

2.0V

MCP1700

VDDCORE

VSS

‘AA’

DS39881D-page 260

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

INDEX

A

C

A/D Converter

C Compilers

Analog Input Model................................................... 198

Transfer Function...................................................... 199

MPLAB C18.............................................................. 218

MPLAB C30.............................................................. 218

Additional Guidance for Family Applications..................... 260

Assembler

Code Examples

Basic Clock Switching Example ............................... 101

Configuring UART 1 Input and Output

MPASM Assembler................................................... 218

Functions (PPS) ............................................... 110

Erasing a Program Memory Block.............................. 52

I/O Port Read/Write .................................................. 106

Initiating a Programming Sequence ........................... 53

Loading the Write Buffers........................................... 53

Single-Word Flash Programming ............................... 54

Code Protection................................................................ 214

Configuration Bits ............................................................. 207

Core Features....................................................................... 9

CPU

ALU............................................................................. 29

Control Registers........................................................ 28

Core Registers............................................................ 27

Programmer’s Model .................................................. 25

CRC

B

Block Diagrams

10-Bit High-Speed A/D Converter............................. 192

Accessing Program Memory with

Table Instructions ............................................... 47

Addressable PMP Example ...................................... 174

CALL Stack Frame...................................................... 45

Comparator Operating Modes .................................. 201

Comparator Voltage Reference ................................ 205

CPU Programmer’s Model.......................................... 27

CRC Reconfigured for Polynomial............................ 188

CRC Shifter Details................................................... 187

Data Access From Program Space

Address Generation............................................ 46

I C Module................................................................ 152

2

CRCXOR Register.................................................... 190

Operation in Power Save Modes.............................. 188

User Interface........................................................... 188

Customer Change Notification Service............................. 265

Customer Notification Service .......................................... 265

Customer Support............................................................. 265

Input Capture ............................................................ 133

Legacy PMP Example............................................... 174

On-Chip Regulator Connections............................... 212

Output Compare ....................................................... 138

PIC24F CPU Core ...................................................... 26

PIC24FJ64GA004 Family (General)........................... 12

PMP

D

Master Port Examples .............................. 174–176

PMP Module Overview ............................................. 167

PSV Operation............................................................ 48

Reset System.............................................................. 55

RTCC........................................................................ 177

Shared I/O Port Structure ......................................... 105

Simplified UART........................................................ 159

SPI Master/Frame Master Connection...................... 149

SPI Master/Frame Slave Connection........................ 149

SPI Master/Slave Connection (Enhanced

Buffer Mode)..................................................... 148

SPI Master/Slave Connection (Standard Mode)....... 148

SPI Slave/Frame Master Connection........................ 149

SPI Slave/Frame Slave Connection.......................... 149

SPIx Module (Enhanced Mode)................................ 143

SPIx Module (Standard Mode).................................. 142

System Clock Diagram ............................................... 95

Timer1....................................................................... 125

Timer2 and Timer4 (16-Bit Modes)........................... 129

Timer2/3 and Timer4/5 (32-Bit Mode)....................... 128

Timer3 and Timer5 (16-Bit Modes)........................... 129

Watchdog Timer (WDT)............................................ 214

Data Memory

Address Space ........................................................... 33

Memory Map............................................................... 33

Near Data Space........................................................ 34

Organization ............................................................... 34

SFR Space ................................................................. 34

Software Stack ........................................................... 45

Development Support....................................................... 217

Device Features (Summary)............................................... 11

DISVREG Pin ................................................................... 212

Doze Mode ....................................................................... 104

E

Electrical Characteristics

A/D Specifications .................................................... 244

Absolute Maximum Ratings...................................... 229

Current Specifications ...................................... 233–237

I/O Pin Specifications ....................................... 238–239

Internal Clock Specifications .................................... 242

Load Conditions and Requirements for

AC Characteristics............................................ 240

Program Memory Specifications............................... 239

Thermal Operating Conditions.................................. 231

V/F Graphs ............................................................... 230

Voltage Ratings ........................................................ 232

Voltage Regulator Specifications.............................. 239

 2010 Microchip Technology Inc.

DS39881D-page 261

PIC24FJ64GA004 FAMILY

Equations

N

A/D Clock Conversion Period ...................................198

Near Data Space ................................................................ 34

Baud Rate Reload Calculation..................................153

Calculating the PWM Period .....................................136

Calculation for Maximum PWM Resolution...............136

Device and SPI Clock Speed Relationship ...............150

UART Baud Rate with BRGH = 0 .............................160

UART Baud Rate with BRGH = 1 .............................160

Errata ....................................................................................8

O

Oscillator Configuration

Clock Switching ........................................................ 100

Sequence ......................................................... 101

Initial Configuration on POR ....................................... 96

Oscillator Modes......................................................... 96

Output Compare

F

PWM Mode............................................................... 136

Period and Duty Cycle Calculation................... 137

Single Output Pulse Generation ............................... 135

Flash Configuration Words.................................. 32, 207–210

Flash Program Memory

and Table Instructions.................................................49

Enhanced ICSP Operation..........................................50

Programming Algorithm ..............................................52

RTSP Operation..........................................................50

Single-Word Programming..........................................54

P

Packaging

Details....................................................................... 249

Marking..................................................................... 247

Parallel Master Port. See PMP......................................... 167

Peripheral Enable Bits ...................................................... 104

Peripheral Module Disable (PMD) bits.............................. 104

Peripheral Pin Select (PPS).............................................. 107

Available Peripherals and Pins................................. 107

Configuration Control................................................ 109

Considerations for Use ............................................. 110

Input Mapping........................................................... 107

Mapping Exceptions ................................................. 109

Output Mapping ........................................................ 108

Peripheral Priority ..................................................... 107

Registers .......................................................... 111–124

PICSTART Plus Development Programmer..................... 220

Pinout Descriptions....................................................... 13–18

PMP

Master Port Examples ...................................... 174–176

Power-Saving Features .................................................... 103

Power-up Requirements................................................... 213

Product Identification System ........................................... 267

Program Memory

Access Using Table Instructions................................. 47

Address Construction ................................................. 45

Address Space ........................................................... 31

Flash Configuration Words ......................................... 32

Memory Map............................................................... 31

Organization ............................................................... 32

Program Space Visibility............................................. 48

Pulse-Width Modulation. See PWM.................................. 136

I

I/O Ports

Analog Port Configuration.........................................106

Input Change Notification..........................................106

Open-Drain Configuration .........................................106

Parallel (PIO) ............................................................105

Peripheral Pin Select ................................................107

Pull-ups.....................................................................106

2

I C

Clock Rates...............................................................153

Peripheral Remapping Options.................................151

Reserved Addresses.................................................153

Slave Address Masking ............................................153

Idle Mode ..........................................................................104

Instruction Set

Overview ...................................................................223

Summary...................................................................221

Instruction-Based Power-Saving Modes...........................103

2

Inter-Integrated Circuit. See I C........................................151

Internet Address................................................................265

Interrupts

Alternate Interrupt Vector Table (AIVT) ......................61

and Reset Sequence ..................................................61

Implemented Vectors..................................................63

Interrupt Vector Table (IVT) ........................................61

Registers............................................................... 64–92

Setup and Service Procedures ...................................93

Trap Vectors ...............................................................62

Vector Table................................................................62

R

Reader Response............................................................. 266

Register Maps

J

JTAG Interface..................................................................214

A/D Converter (ADC).................................................. 41

Clock Control .............................................................. 44

CPU ............................................................................ 35

CRC............................................................................ 42

Dual Comparator ........................................................ 42

M

Microchip Internet Web Site..............................................265

MPLAB ASM30 Assembler, Linker, Librarian ...................218

MPLAB ICD 2 In-Circuit Debugger....................................219

MPLAB ICE 2000 High-Performance Universal

2

I C .............................................................................. 38

ICN ............................................................................. 35

Input Capture.............................................................. 37

Interrupt Controller...................................................... 36

NVM............................................................................ 44

Output Compare ......................................................... 38

Pad Configuration....................................................... 40

Parallel Master/Slave Port.......................................... 41

Peripheral Pin Select .................................................. 43

PMD............................................................................ 44

In-Circuit Emulator ....................................................219

MPLAB Integrated Development Environment

Software....................................................................217

MPLAB PM3 Device Programmer.....................................219

MPLAB REAL ICE In-Circuit Emulator System.................219

MPLINK Object Linker/MPLIB Object Librarian ................218

DS39881D-page 262

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

PORTA........................................................................ 40

UxRXREG (UARTx Receive) ................................... 166

UxSTA (UARTx Status and Control) ........................ 164

UxTXREG (UARTx Transmit)................................... 166

WKDYHR (RTCC Weekday and Hours Value) ........ 183

YEAR (RTCC Year Value)........................................ 182

PORTB........................................................................ 40

PORTC ....................................................................... 40

Real-Time Clock and Calendar (RTCC) ..................... 42

SPI .............................................................................. 39

Timers......................................................................... 37

UART .......................................................................... 39

Resets

Clock Source Selection .............................................. 57

Delay Times................................................................ 58

RCON Flags Operation .............................................. 57

SFR States ................................................................. 59

Revision History................................................................ 259

RTCC

Registers

AD1CHS (A/D Input Select)...................................... 196

AD1CON1 (A/D Control 1)........................................ 193

AD1CON2 (A/D Control 2)........................................ 194

AD1CON3 (A/D Control 3)........................................ 195

AD1CSSL (A/D Input Scan Select)........................... 197

AD1PCFG (A/D Port Configuration).......................... 197

ALCFGRPT (Alarm Configuration)............................ 181

ALMINSEC (Alarm Minutes and

Seconds Value) ................................................ 185

ALMTHDY (Alarm Month and Day Value) ................ 184

ALWDHR (Alarm Weekday and Hours Value).......... 184

CLKDIV (Clock Divider) .............................................. 99

CMCON (Comparator Control) ................................. 202

CORCON (Core Control) ............................................ 65

CORCON (CPU Control) ............................................ 29

CRCCON (CRC Control) .......................................... 189

CRCXOR (CRC XOR Polynomial)............................ 190

CVRCON (Comparator Voltage

Reference Control) ........................................... 206

CW1 (Flash Configuration Word 1)........................... 208

CW2 (Flash Configuration Word 2)........................... 210

DEVID (Device ID).................................................... 211

DEVREV (Device Revision)...................................... 211

I2CxCON (I2Cx Control) ........................................... 154

I2CxMSK (I2Cx Slave Mode Address Mask) ............ 158

I2CxSTAT (I2Cx Status) ........................................... 156

ICxCON (Input Capture x Control)............................ 134

IECn (Interrupt Enable Control 0-4) ...................... 73–77

IFSn (Interrupt Flag Status 0-4) ............................ 68–72

INTCON1 (Interrupt Control 1).................................... 66

INTCON2 (Interrupt Control 2).................................... 67

IPCn (Interrupt Priority Control 0-18) .................... 78–92

MINSEC (RTCC Minutes and Seconds Value)......... 183

MTHDY (RTCC Month and Day Value) .................... 182

NVMCON (Flash Memory Control) ............................. 51

OCxCON (Output Compare x Control) ..................... 139

OSCCON (Oscillator Control) ..................................... 97

OSCTUN (FRC Oscillator Tune)............................... 100

PADCFG1 (Pad Configuration Control) ............ 173, 180

PMADDR (PMP Address)......................................... 171

PMAEN (PMP Enable).............................................. 171

PMCON (PMP Control)............................................. 168

PMMODE (PMP Mode)............................................. 170

PMPSTAT (PMP Status)........................................... 172

RCFGCAL (RTCC Calibration

Alarm Configuration.................................................. 186

Calibration ................................................................ 185

Register Mapping ..................................................... 178

S

Serial Peripheral Interface. See SPI................................. 141

SFR Space ......................................................................... 34

Slective Peripheral Power Control.................................... 104

Sleep Mode ...................................................................... 103

Software Simulator (MPLAB SIM) .................................... 218

Software Stack ................................................................... 45

T

Timer1 .............................................................................. 125

Timer2/3 and Timer4/5 ..................................................... 127

Timing Diagrams

CLKO and I/O Timing ............................................... 243

External Clock Timing............................................... 241

U

UART

Baud Rate Generator (BRG) .................................... 160

Break and Sync Sequence....................................... 161

IrDA Support............................................................. 161

Operation of UxCTS and UxRTS Control Pins......... 161

Receiving.................................................................. 161

Transmitting.............................................................. 161

V

VDDCORE/VCAP pin............................................................ 212

Voltage Regulator (On-Chip) ............................................ 212

and BOR................................................................... 213

and POR................................................................... 212

Standby Mode .......................................................... 213

Tracking Mode.......................................................... 212

W

Watchdog Timer (WDT).................................................... 213

Winowed Operation.................................................. 214

WWW Address ................................................................. 265

WWW, On-Line Support ....................................................... 8

and Configuration) ............................................ 179

RCON (Reset Control)................................................ 56

RPINRn (PPS Input Mapping 0-23) .................. 111–117

RPORn (PPS Output Mapping 0-12) ................ 118–124

SPIxCON1 (SPIx Control 1)...................................... 146

SPIxCON2 (SPIx Control 2)...................................... 147

SPIxSTAT (SPIx Status and Control) ....................... 144

SR (ALU STATUS) ............................................... 28, 65

T1CON (Timer1 Control)........................................... 126

TxCON (Timer2 and Timer4 Control)........................ 130

TyCON (Timer3 amd Timer5 Control)....................... 131

UxMODE (UARTx Mode).......................................... 162

 2010 Microchip Technology Inc.

DS39881D-page 263

PIC24FJ64GA004 FAMILY

NOTES:

DS39881D-page 264

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THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

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Please list the following information, and use this outline to provide us with your comments about this document.

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PIC24FJ64GA004 Family

DS39881D

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS39881D-page 266

 2010 Microchip Technology Inc.

PIC24FJ64GA004 FAMILY

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PIC 24 FJ 64 GA0 04 T - I / PT - XXX

a)

b)

PIC24FJ32GA002-I/ML:

General purpose PIC24F, 32-Kbyte program

memory, 28-pin, Industrial temp.,

QFN package.

Microchip Trademark

Architecture

PIC24FJ64GA004-E/PT:

Flash Memory Family

General purpose PIC24F, 64-Kbyte program

memory, 44-pin, Extended temp.,

TQFP package.

Program Memory Size (KB)

Product Group

Pin Count

Tape and Reel Flag (if applicable)

Temperature Range

Package

Pattern

Architecture

24 = 16-bit modified Harvard without DSP

Flash Memory Family FJ = Flash program memory

Product Group

Pin Count

GA0 = General purpose microcontrollers

02 = 28-pin

04 = 44-pin

Temperature Range

Package

E

I

=

-40C to +125C (Extended)

-40C to +85C (Industrial)

SP = SPDIP

SO = SOIC

SS = SSOP

ML = QFN

PT = TQFP

Pattern

Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)

ES = Engineering Sample

 2010 Microchip Technology Inc.

DS39881D-page 267

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

01/05/10

DS39881D-page 268

 2010 Microchip Technology Inc.


型号：	48GA002
厂家：	MICROCHIP
描述：	28/44-Pin General Purpose, 16-Bit Flash Microcontrollers 44分之28引脚通用16位闪存微控制器闪存微控制器
文件：	总268页 (文件大小：1989K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

48GA002 [MICROCHIP]

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