5962-8858603XA [ETC]
Controller Miscellaneous - Datasheet Reference ; 控制器杂项 - 数据表参考\n
| 型号： | 5962-8858603XA |
| 厂家： | 
ETC |
| 描述： | Controller Miscellaneous - Datasheet Reference
|
| 文件： | 总34页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REVISIONS
LTR
A
DESCRIPTION
DATE (YR-MO-DA)
92-03-05
APPROVED
Alan Barone
Changes to reflect MIL-H-38534 processing. Correction to table I.
Editorial changes throughout.
B
C
Changes in accordance with NOR 5962-R015-96.
95-12-08
02-03-01
Kendall A. Cottongim
Raymond Monnin
Added device types 02 and 03 with cage code 88379. Made changes
to table I, figure 1, and figure 20. Renumbered figures 5 through 21
to figures 4 through 20. Changes to reflect MIL-PRF-38534
processing. -sld
REV
SHEET
REV
C
C
C
C
C
C
C
21
C
C
22
C
C
23
C
C
24
C
C
25
C
C
26
C
C
27
C
C
28
C
C
29
C
C
30
C
C
31
C
C
32
C
C
33
C
SHEET
15
16
17
18
19
20
REV STATUS
OF SHEETS
REV
C
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
Robert M. Heber
DEFENSE SUPPLY CENTER COLUMBUS
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Ray Monnin
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
APPROVED BY
Michael Frye
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
MICROCIRCUIT, HYBRID, LINEAR, MIL-STD-
1553, BUS TO MICROPROCESSOR
INTERFACE UNIT
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
88-12-20
AMSC N/A
REVISION LEVEL
C
SIZE
A
CAGE CODE
5962-88586
67268
SHEET
1 OF 33
DSCC FORM 2233
APR 97
5962-E240-02
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
1. SCOPE
1.1 Scope. This drawing describes device requirements for class H hybrid microcircuits to processed in accordance with
MIL-PRF-38534.
1.2 PIN. The PIN shall be as shown in the following example:
5962-88586
01
X
X
Drawing number
Device type
(see 1.2.1)
Case outline
(see 1.2.2)
Lead finish
(see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
01
02
03
BUS-66300II
CT2566-001
CT2566-002
MIL-STD-1553, BUS to microprocessor interface unit
MIL-STD-1553, BUS to microprocessor interface unit
MIL-STD-1553, BUS to microprocessor interface unit
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
X
Y
See figure 1
See figure 1
78
82
Dual-in-line
Flat pack
1.2.3 Lead finish. The lead finish shall be as specified in MIL-PRF-38534.
1.3 Absolute maximum ratings. 1/
Supply voltage range (VCC)................................................. -0.5 V dc to +7.0 V dc
Input voltage range (VIN)..................................................... -0.5 V dc to +7.0 V dc
Supply current (ICC)............................................................. 150 mA
Power dissipation (PD) ........................................................ 250 mW 2/
Storage temperature range................................................. -65°C to +150°C
Lead temperature (soldering, 10 seconds) ......................... +300°C
Thermal resistance, junction-to-case (ΘJC) ......................... 4.11°C/W
1.4 Recommended operating conditions.
Supply voltage range (VCC)................................................. 4.5 V dc to 5.5 V dc
Minimum logic high input voltage (VIH)................................ 2.0 V dc
Maximum logic low input voltage (VIL)................................. 0.8 V dc
Case operating temperature range (TC).............................. -55°C to +125°C
Operating frequency (FOP) .................................................. 12.0 MHz
1/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Applies up to TC = +125°C.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
2
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in
the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the
solicitation.
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38534 - Hybrid Microcircuits, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1553 - Aircraft Internal Time Division Command/Response Multiplex Data Bus.
MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbook are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in
accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 may include the performance of all tests herein or as
designated in the device manufacturer's Quality Management (QM) plan or as designated for the applicable device class.
Therefore, the tests and inspections herein may not be performed for the applicable device class (see MIL-PRF-38534).
Furthermore, the manufacturer may take exceptions or use alternate methods to the tests and inspections herein and not
perform them. However, the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device
class.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38534 and herein.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Block diagram. The block diagram shall be as specified on figure 3.
3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4 through 20.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full specified operating temperature range.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
3
DSCC FORM 2234
APR 97
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked
with the PIN listed in 1.2 herein. In addition, the manufacturer's vendor similar PIN may also be marked.
3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described
herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot
sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for
those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer
and be made available to the preparing activity (DSCC-VA) upon request.
3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this
drawing. The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturer's product meets
the performance requirements of MIL-PRF-38534 and herein.
3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of
microcircuits delivered to this drawing.
4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as
modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the
form, fit, or function as described herein.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
4
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
Group A
subgroups
1/
Device
types
Limits
Unit
-55°C ≤ T ≤+125°C
C
unless otherwise specified
Min
Max
150
Supply current
ICC
VCC = 5.5 V, IOH = -0.4 mA,
1,2,3
All
mA
I
OL = 4.0 mA, fIN = 12 MHz,
measured at pin 20
High level output voltage 2/
Low level output voltage 2/
High level input current 3/
VOH
VOL
IIH1
VCC = 4.5 V, IOH = -4.0 mA,
1,2,3
1,2,3
All
All
3.7
V
V
VIH = 2.5 V, VIL = 0.4 V
VCC = 4.5 V, IOL = 4.0 mA,
0.4
VIH = 2.5 V, VIL = 0.4 V
VCC = 5.5 V, VIN = 2.5 V
VCC = 5.5 V, VIH = 2.5 V
VCC = 5.5 V, VIN = 0.0V
VCC = 5.5 V, IIN = 0.0 V
1,2,3
1,2,3
1,2,3
1,2,3
7,8
All
All
All
All
All
-10
-107
-10
+10
-630
+10
µA
High level input current 4/ 5/ IIH2
Low level input current 3/ IIL1
µA
µA
Low level input current 4/ 5/ IIL2
Functional tests 6/
-134
-700
µA
VCC = 4.5 V, VIH = 2.5 V,
VIL = 0.4 V, IOH = -4.0 mA,
Pass/Fail
I
OL = 4.0 mA, f = 12 MHz
Delay timing:
tD1
V
CC = 4.5 V, VIH = 2.5 V,
VIL = 0.4 V, IOH = -4.0 mA,
OL = 4.0 mA, fIN = 12 MHz,
9,10,11
9,10,11
All
All
200
20
ns
ns
READY low delay
(CPU handshake)
I
See figures 4 through 20
tD2
IOEN high delay
(CPU handshake)
7/ 8/
tD3
9,10,11
9,10,11
9,10,11
9,10,11
All
All
All
All
120
115
130
30
ns
ns
ns
ns
CPU MEMWR low delay
tD4
CPU MEMOE low delay
tD5
EXTLD low delay
tD6
RESET low delay
Internal Register delay (read) tD7
Internal Register delay (write) tD8
9,10,11
9,10,11
9,10,11
All
All
All
60
60
40
ns
ns
ns
Register Data/Address setup
time
tD9
Register Data/Address hold
time
tD10
9,10,11
All
0
ns
tD11
tD12
9,10,11
9,10,11
All
All
120
50
ns
ns
BC , SOM cycle DMA mode
INT low delay
See footnotes at end of table.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
Group A
subgroups
1/
Device
types
Limits
Unit
-55°C ≤ T ≤+125°C
C
unless otherwise specified
Min
Max
200
Delay Timing - Continued:
tD13
VCC = 4.5 V, VIH = 2.5 V,
VIL = 0.4 V, IOH = -4.0 mA,
9,10,11
All
ns
RTU, SOM cycle DMA delay
I
OL = 4.0 mA, fIN = 12 MHz,
See figures 4 through 20
7/ 8/
1553 Command Word setup
time
tD14
tD15
tD16 9/
tD17
9,10,11
9,10,11
All
All
60
60
ns
ns
1553 Command Word hold
time
9,10,11
9,10,11
9,10,11
9,10,11
All
All
All
All
200
30
ns
ns
ns
ns
MT , SOM cycle DMA delay
CS low to MEMCS low delay
OE low to MEMOE low delay
tD18
30
tD19
30
WR low to MEMWR low
delay
tD20
tD21
tD22
tD23
9,10,11
9,10,11
9,10,11
9,10,11
All
All
All
All
25
45
ns
ns
ns
ns
BUSGRNT high delay
BUSACK low address delay
25
BUSACK high address delay
Address increment delay
Pulse Width Timing:
200
tPW1
VCC = 4.5 V, VIH = 2.5 V,
VIL = 0.4 V, IOH = -4.0 mA,
9,10,11
All
70
ns
READYD pulse width
(CPU handshake)
I
OL = 4.0 mA, fIN = 12 MHz,
See figures 4 through 20
8/
tPW2
9,10,11
9,10,11
All
All
70
70
ns
ns
CPU MEMWR low pulse
width
tPW3
CPU MEMCS low pulse
width
tPW4
tPW5
9,10,11
9,10,11
All
All
70
70
ns
ns
EXTLD low pulse width
RESET low pulse width
See footnotes at end of table.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
Group A
subgroups
1/
Device
types
Limits
Unit
-55°C ≤ T ≤+125°C
C
unless otherwise specified
Min
Max
Pulse Width Timing - Continued:
tPW6
VCC = 4.5 V, VIH = 2.5 V,
VIL = 0.4 V, IOH = -4.0 mA,
9,10,11
All
70
ns
DMA MEMWR low pulse
width
I
OL = 4.0 mA, fIN = 12 MHz,
See figures 4 through 20
8/
tPW7
tPW8
tPW9
tPW10
tPW11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
All
All
All
All
All
70
70
50
20
60
ns
ns
ns
ns
ns
DMAMEMCS low pulse width
BCSTART low pulse width
EOM low pulse width
200
200
INT low pulse width
INT low (BC EOM ) pulse
width
tPW12
tPW13
tPW14
tPW15
9,10,11
9,10,11
9,10,11
9,10,11
All
All
All
All
50
50
200
200
200
ns
ns
ns
ns
SOM low pulse width
NBGRNT low pulse width
ADRINC low pulse width
MSTRCLR low pulse width
50
150
DMA Cycle Data/Address set-up and hold timing:
DMA address setup time
tAS1
VCC = 4.5 V, VIH = 2.5 V,
VIL = 0.4 V, IOH = -4.0 mA,
9,10,11
All
40
83
ns
I
OL = 4.0 mA, fIN = 12 MHz,
See figures 4 through 20
7/ 8/
DMA data setup time
DMA address setup time
DMA data setup time
DMA address hold time
DMA data hold time
tDS1
tAS2
tDS2
tAH1
tDH1
tAH2
tDH2
fMAX
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
All
All
All
All
All
All
All
All
ns
45
83
ns
ns
60
30
0
ns
ns
DMA address hold time
DMA data hold time
ns
0
ns
Maximum clock frequency
50 percent duty cycle 7/
16.0
MHz
See footnotes on next page.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics -Continued.
1/ All group A subgroup testing may be performed concurrently.
2/ Measured at the following pins:
Case X: Pins 3 through 5, 14, 16, 21 through 39, 42, 43, 45 through 47, 50, 56, 57, and 59 through 77.
Case Y: Pins 5 through 8, 10, 11, 13, 15, 21, 28, 32, 33, 35, 39, and 45 through 81.
3/ Measured at the following pins:
Case X: Pins 7 through 9, 11 through 13, 17, 19, 21 through 28, 38, 39, 44, 48, 49, 51, 53 through 55, 60 through
67 and 77.
Case Y: Pins 9, 14, 16 through 19, 22 through 24, 26, 27,29, 31,34, 38, 45 through 47, and 66 through 81.
4/ Measured at the following pins:
Case X: Pins 1, 2, 6, 10, 41, and 52.
Case Y: Pins 2 through 4, 12, 20, and 25.
5/ For device type 03, case X, pin 52 and case Y, pin 25 have a 0.001 µf capacitor to ground.
6/ Functional tests performed to verify functionality of device as a handshake intermediary between MIL- STD-1750 Central
Processing Units (CPU) and MIL-STD-1553 Bus Controller (BC), Remote Terminal Unit (RTU) and Bus Monitor (MT).
7/ Parameter shall be tested as part of device intial characterization and after design and process changes. Parameter
shall be guaranteed to the limits specified in table I for all lots not specifically tested.
8/ All timing characterisitics measured at 50 percent of waveform, unless otherwise specified.
9/ For device types 02 and 03, t
is referenced from the rising edge of READYD as shown in figure 19.
D16
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
8
DSCC FORM 2234
APR 97
Case outline X
Symbol
Millimeters
Inches
Max
Min
Max
6.35
Min
A
Φb
D
D1
D2
E
E1
E2
e
.250
.023
0.33
0.58
.013
47.50
42.04
38.23
53.34
48.39
45.85
1.870
1.655
1.505
2.100
1.905
1.805
41.78
37.97
1.645
1.495
48.13
45.59
1.895
1.795
2.54 TYP
.100 TYP
e1
e2
L
2.41
1.14
0.61
1.78
2.67
1.40
0.66
2.03
.095
.045
.240
.070
.105
.055
.260
.080
S
S1
1.91 TYP
.075 TYP
NOTES:
1.The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound units of
measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound
units shall rule.
FIGURE 1. Case outline(s).
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
9
DSCC FORM 2234
APR 97
Case outline Y
Symbol
Millimeters
Inches
Min Max
Min
Max
4.72
A
A1
Φb
Φc
D
.186
2.03 REF
.080 REF
0.30
0.20
0.46
0.30
.012
.008
.018
.012
40.51
55.50
40.77
55.75
1.595
2.185
1.605
2.195
E
e
1.27 TYP
10.16
2.41 REF
.050 TYP
.400
.095 REF
L
S1
NOTES:
1.The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound units of
measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound
units shall rule.
FIGURE 1. Case outline(s) - Continued.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
10
DSCC FORM 2234
APR 97
Device
types
All
X
Device
types
All
X
Case
outline
Case
outline
Terminal
number
Terminal symbol
Terminal
number
Terminal symbol
Terminal
number
Terminal symbol
1
2
3
4
5
6
7
8
9
27
28
29
30
31
32
33
34
35
D03
D01
53
54
55
56
57
58
59
60
61
SELECT
RD/ WR
READYD
EXTEN
TAGEN
EOM
BUSACK
WR
SSFLAG
SSBUSY
CS
MEMOE
RTU/BC
A14
MEMWR
No connection
A12
A10
A08
A06
SOM
MT
D14
STATERR
ADRINC
D12
D10
10
36
62
MEM/ REG
CLOCKIN
11
12
37
38
A04
A02
63
64
D08
D06
LOOPERR
BUSREQ
13
14
15
16
17
18
19
20
21
22
39
40
41
42
43
44
45
46
47
48
49
50
51
52
A00 (LSB)
Ground
65
66
67
68
D04
D02
BUSGRNT
No connection
D00 (LSB)
STRBD
IOEN
MEMCS
SVCREQ
69
70
OE
EXTLD
DBAC
No connection
A15 (MSB)
CHB/ CHA
INT
A13
71
72
73
74
NBGRNT
VCC
A11
A09
BCSTART
RESET
D15 (MSB)
D13
A07
A05
A03
A01
MSGERR
CTLIN B/ A
CTLOUT B/ A
TIMEOUT
MSTRCLR
23
24
D11
D09
75
76
25
26
D07
D05
77
78
Chassis ground
FIGURE 2. Terminal connections.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
11
DSCC FORM 2234
APR 97
Device
types
All
Y
Device
types
All
Y
Case
outline
Case
outline
Terminal
number
Terminal symbol
Terminal
number
Terminal symbol
Terminal
number
Terminal symbol
1
No connection
29
30
31
57
58
59
A12
A13
A14
WR
SELECT
STRBD
2
3
No connection
CS
RD/ WR
IOEN
MEMCS
MEMOE
4
5
32
33
60
61
A15 (MSB)
RTU/BC
DBAC
READYD
EXTLD
OE
6
7
8
9
34
35
36
37
62
63
64
65
MEMWR
SSBUSY
SVCREQ
EXTEN
No connection
No connection
CHB/ CHA
SSFLAG
D00 (LSB)
D01
TAGEN
INT
NBGRNT
MT
10
11
12
13
14
15
16
17
18
38
39
40
41
42
43
44
45
46
66
67
68
69
70
71
72
73
74
EOM
VCC
D02
BCSTART
SOM
No connection
No connection
D03
D04
RESET
STATERR
MSGERR
ADRINC
Ground
D05
Chassis ground
D06
A00 (LSB)
A01
D07
D08
CTLIN B/ A
MEM/ REG
19
20
21
47
48
49
A02
A03
A04
75
76
77
D09
D10
D11
CTLOUT B/ A
CLOCKIN
22
23
50
51
A05
A06
78
79
D12
D13
TIMEOUT
LOOPERR
MSTRCLR
BUSREQ
BUSACK
24
25
26
27
28
52
53
54
55
56
A07
A08
A09
A10
A11
80
81
82
D14
D15 (MSB)
No connection
BUSGRNT
FIGURE 2. Terminal connections - Continued.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
12
DSCC FORM 2234
APR 97
FIGURE 3. Block diagram.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
13
DSCC FORM 2234
APR 97
NOTE: STRBD toIOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus.
FIGURE 4. Timing diagram - CPU reads from internal register.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
14
DSCC FORM 2234
APR 97
NOTE: STRBD toIOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus.
FIGURE 5. Timing diagram - CPU writes to internal register.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
15
DSCC FORM 2234
APR 97
NOTE: STRBD toIOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus.
FIGURE 6. Timing diagram - CPU reads from external register.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
16
DSCC FORM 2234
APR 97
NOTE: STRBD toIOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus.
FIGURE 7. Timing diagram - CPU writes to external register.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
17
DSCC FORM 2234
APR 97
NOTE: STRBD toIOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus.
FIGURE 8. Timing diagram - CPU read from RAM.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
18
DSCC FORM 2234
APR 97
NOTE: STRBD toIOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus.
FIGURE 9. Timing diagram - CPU writes to RAM.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
19
DSCC FORM 2234
APR 97
FIGURE 10. Timing diagram - 1553 terminal to interface unit handshaking.
FIGURE 11. Timing diagram - 1553 terminal I/O delay.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
20
DSCC FORM 2234
APR 97
FIGURE 12. Timing diagram - interface unit address increment.
NOTE: RESET (low) pulse width will be approximately equal to that of MSTRCLR (low).
FIGURE 13. Timing diagram - interface unit direct reset.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
21
DSCC FORM 2234
APR 97
NOTE: STRBD toIOEN (low) delay is two clock cycles. If contention occurs, delay is two cycles following release of bus.
FIGURE 14. Timing diagram - programmed interface unit reset.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
22
DSCC FORM 2234
APR 97
FIGURE 15. Timing diagram - RTU SOM (no connection).
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
23
DSCC FORM 2234
APR 97
FIGURE 16. Timing diagram - RTU EOM (no connection).
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
24
DSCC FORM 2234
APR 97
FIGURE 17. Timing diagram - BC SOM (no connection).
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
25
DSCC FORM 2234
APR 97
FIGURE 18. Timing diagram - BC EOM (no connection).
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
26
DSCC FORM 2234
APR 97
NOTE: For device types 02 and 03, tD16 is referenced from the rising edge of READYD.
FIGURE 19. Timing diagram - MT SOM (no connection).
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
27
DSCC FORM 2234
APR 97
FIGURE 20. Timing diagram - DMA read/write (SOM/EOM cycles).
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
28
DSCC FORM 2234
APR 97
TABLE II. Electrical test requirements.
MIL-PRF-38534 test requirements
Subgroups
(in accordance with
MIL-PRF-38534, group A
test table)
Interim electrical parameters
Final electrical parameters
Group A test requirements
1, 7, 9
1*, 2, 3, 7*, 8, 9*, 10, 11
1, 2, 3, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10, 11
Group C end-point electrical
parameters
End-point electrical parameters
for Radiation Hardness Assurance
(RHA) devices
Not applicable
* PDA applies to subgroup 1, 7, and 9.
4.2 Screening. Screening shall be in accordance with MIL-PRF-38534. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent
specified in test method 1015 of MIL-STD-883.
(2) T as specified in accordance with table I of method 1015 of MIL-STD-883.
A
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
tests prior to burn-in are optional at the discretion of the manufacturer.
4.3 Conformance and periodic inspections. Conformance inspection (CI) and periodic inspection (PI) shall be in accordance
with MIL-PRF-38534 and as specified herein.
4.3.1 Group A inspection (CI). Group A inspection shall be in accordance with MIL-PRF-38534 and as follows:
a. Tests shall be as specified in table II herein.
b. Subgroups 4, 5, and 6 shall be omitted.
4.3.2 Group B inspection (PI). Group B inspection shall be in accordance with MIL-PRF-38534.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
29
DSCC FORM 2234
APR 97
4.3.3 Group C inspection (PI). Group C inspection shall be in accordance with MIL-PRF-38534 and as follows:
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test, method 1005 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to either DSCC-VA or the acquiring activity upon request. Also, the test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent
specified in test method 1005 of MIL-STD-883.
(2) T as specified in accordance with table I of method 1005 of MIL-STD-883.
A
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.3.4 Group D inspection (PI). Group D inspection shall be in accordance with MIL-PRF-38534.
4.3.5 Radiation Hardness Assurance (RHA) inspection. RHA inspection is not currently applicable to this drawing.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38534.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated as specified in MIL-PRF-
38534.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application
requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for
coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962)
should contact DSCC-VA, telephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone
(614) 692-0514.
6.6 Sources of supply. Sources of supply are listed in MIL-HDBK-103 and QML-38534. The vendors listed in MIL-HDBK-103
and QML-38534 have submitted a certificate of compliance (see 3.7 herein) to DSCC-VA and have agreed to this drawing.
6.7 Pin functions. Microcircuits conforming to this drawing shall have the pin functions as specified in table III herein.
SIZE
STANDARD
5962-88586
A
MICROCIRCUIT DRAWING
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
30
DSCC FORM 2234
APR 97
TABLE III. Pin functions.
Description
Pin name
SELECT
I/O
I
I
Select. When active, selects interface unit for operation.
Read/Write. Controls CPU bus data direction.
RD/ WR
O
O
Ready Data. When active indicates data has been received from, or is available to
the CPU.
READYD
External Enable. Output from interface unit to enable output from external devices.
Same timing as MEMEO .
EXTEN
TAGEN
O
Tag Enable. Enables an external time tag counter for transfering the time tag word
into memory.
EOM
I
I
I
End of Message. Input from 1553 device indicating end of message.
Start of message. Input from 1553 device indicating start of message.
SOM
Status Error. Input from 1553 device when status word has either a bit set or
unexpected RTU address (in BC mode only).
STATERR
ADRINC
I
I
Address Increment. Send from 1553 device to increment address counter following
word transfer.
Memory/Register. Input from CPU to select memory or register data transfer.
MEM/ REG
CLOCKIN
I
I
Clock input; 50 percent duty cycle, 16 MHz, maximum.
Loop Error. Input from 1553 device if short loop BIT fails.
LOOPERR
BUSREQ
Bus Request. When active, indicates 1553 device requires use of the address/data
bus.
I
Bus Grant. Handshake output to 1553 device in response to Bus Request indicating
address/data bus available to 1553 device.
O
O
BUSGRNT
MEMCS
Memory Chip Select. Low from interface unit enable external RAM. Used with 4K x
4 RAM type device to read RAM or used in conjunction with MEMWR to write data
into RAM.
I
I
Output Enable. Input from 1553 device used to enable memory on the parallel bus.
OE
Low pulse from 1553 device preceding start of receiving new protocol sequence.
Used with superseding command to reset DMA in progress.
NBGRNT
VCC
I
Logic power supply (+5.0 V).
Data Bus Bit 15 (MSB).
Data Bus Bit 13.
D15
D13
D11
D09
I/O
I/O
I/O
Data Bus Bit 11.
I/O
I/O
I/O
I/O
Data Bus Bit 9.
Data Bus Bit 7.
Data Bus Bit 5.
Data Bus Bit 3.
D07
D05
D03
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
31
DSCC FORM 2234
APR 97
TABLE III. Pin functions - Continued.
Description
Pin name
D01
I/O
I/O Data Bus Bit 1.
O
O
O
Subsystem Flag. Output to 1553 device to set RTU subsystem flag status bit.
SSFLAG
SSBUSY
RTU/BC
Subsystem Busy. Output to 1553 device to set RTU subsystem busy flag.
Output to 1553 device used in conjunction with MT to set operating mode.
A14
A12
A10
A08
A06
A04
A02
A00
Ground
O
O
O
O
O
O
Address Bit 14.
Address Bit 12.
Address Bit 10
Address Bit 8.
Address Bit 6.
Address Bit 4.
I/O Address Bit 2.
I/O Address Bit 0 (LSB).
-
I
Signal return.
STRBD
Strobe Data. Used in conjunction with SELECT to indicate a data transfer cycle
to/from the CPU.
O
O
Input/Output Enable. Output from interface unit to enable external buffers/latches
connecting the hybrid to the address/data bus.
IOEN
External load. Used to load data into external device via the interface unit data bus.
Same timing as MEMWR .
EXTLD
Input from 1553 in RTU mode used to indicate received 1553 message came in
either channel A or B.
CHB/ CHA
O
Interrupt. Interrupt pulse line to CPU
INT
O
O
Bus Controller Start. Output to 1553 to initiate BC cycle.
BCSTART
RESET
Reset. Output to external device from interface unit consisting of the OR condition
of CPU reset and CPU Master Clear.
I
Message error. Input from 1553 device when an error occurs in message
sequence.
MSGERR
O
O
Input to change memory map area (0 = area A).
CTLIN B /A
CTLOUT B/ A
TIMEOUT
Output from interface unit selecting which area is to be active (0 = area A).
Input from 1553 device indicating no response time-out.
I
I
Master Clear. Power-on reset from CPU. Resets DMA in progress and internal
registers to logic "0".
MSTRCLR
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
32
DSCC FORM 2234
APR 97
TABLE III. Pin functions - Continued.
Pin name
BUSACK
I/O
Description
I
I
Bus Acknowledge. Input from 1553 device acknowledge receipt of BUSGRNT .
Write. Input from 1553 device for writing data into memory.
WR
CS
I
Chip Select. Input from 1553 device that is routed to MEMCS .
Memory Output Enable. Output from interface unit to enable memory output data.
O
MEMOE
MEMWR
O
O
Memory Write. Output pulse from interface unit to write data bus into memory.
Bus Monitor. Used in conjunction with RTU/BC to set operating mode.
MT
D14
I/O
Data Bus Bit 14.
D12
D10
D08
D06
I/O Data Bus Bit 12.
I/O Data Bus Bit 10.
I/O Data Bus Bit 8.
I/O Data Bus Bit 6.
I/O Data Bus Bit 4.
I/O Data Bus Bit 2.
I/O Data Bus Bit 0 (LSB).
D04
D02
D00
O
Service Request. Used to set service request bit in RTU Block Status Word.
Dynamic Bus Acceptance. Used to set status bit in RTU Block Status Word.
SVCREQ
O
O
DBAC
A15
Data Bus Bit 15 (MSB).
Data Bus Bit 13.
Data Bus Bit 11.
Data Bus Bit 9.
A13
O
O
O
A11
A09
A07
O
O
O
Data Bus Bit 7.
Data Bus Bit 5.
Data Bus Bit 3.
A05
A03
I/O Data Bus Bit 1.
-- Chassis Ground
A01
Chassis Ground
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88586
A
REVISION LEVEL
SHEET
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
C
33
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 02-03-01
Approved sources of supply for SMD 5962-88586 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38534 during the next revisions. MIL-HDBK-103 and QML-38534 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next
dated revisions of MIL-HDBK-103 and QML-38534.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8858601XA
5962-8858601XC
19645
19645
BUS-66300II-140
BUS-66300II-883B
5962-8858601YA
5962-8858601YC
19645
19645
BUS-66301II-140
BUS-66301II-883B
5962-8858602XA
5962-8858602XC
5962-8858602YA
5962-8858602YC
88379
88379
88379
88379
CT2566-001-2
CT2566-001-1
CT2566-201-2
CT2566-201-1
5962-8858603XA
5962-8858603XC
5962-8858603YA
5962-8858603YC
88379
88379
88379
88379
CT2566-002-2
CT2566-002-1
CT2566-202-2
CT2566-202-1
1/ The lead finish shown for each PIN representing a hermetic
package is the most readily available from the manufacturer
listed for that part. If the desired lead finish is not listed
contact the Vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items
acquired to this number may not satisfy the performance
requirements of this drawing.
Vendor CAGE
number
Vendor name
and address
19645
ILC Data Device Corporation
105 Wilbur Place
Bohemia, NY 11716
88379
Aeroflex Circuit Technology Corporation
35 South Service Road
Plainview, NY 11803-4101
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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