74F843SCX [ETC]
9-Bit D-Type Latch ; 9位D类锁存器\n
| 型号： | 74F843SCX |
| 厂家： | 
ETC |
| 描述： | 9-Bit D-Type Latch
|
| 文件： | 总6页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
Revised September 2000
74F843
9-Bit Transparent Latch
General Description
Features
■ 3-STATE output
The 74F843 bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and pro-
vide extra data width for wider address/data paths or buses
carrying parity.
Ordering Code:
Order Number Package Number
Package Description
74F843SC
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F843SPC
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE
© 2000 Fairchild Semiconductor Corporation
DS009453
www.fairchildsemi.com
Unit Loading/Fan Out
Input IIH/IIL
U.L.
Pin Names
Description
Data Inputs
Output IOH/IOL
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
D0–D8
OE
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA
Output Enable Input
Latch Enable
Clear
LE
CLR
PRE
O0–O8
Preset
3-STATE Data Outputs
Functional Description
Function Table
The 74F843 consists of nine D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion. On the LE HIGH-to-LOW transition, the data that
meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state. In addition to
the LE and OE pins, the 74F843 has a Clear (CLR) pin and
a Preset (PRE). These pins are ideal for parity bus interfac-
ing in high performance systems. When CLR is LOW, the
outputs are LOW if OE is LOW. When CLR is HIGH, data
can be entered into the latch. When PRE is LOW, the Out-
puts are HIGH if OE is LOW. Preset overrides CLR.
Inputs
Internal Output
Function
CLR PRE OE LE
D
X
L
Q
X
O
Z
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
X
H
H
H
L
X
H
H
L
High Z
High Z
L
Z
H
X
L
H
Z
High Z
NC
L
Z
Latched
Transparent
Transparent
Latched
Preset
H
H
L
L
L
H
X
X
X
X
X
X
H
H
NC
H
L
L
NC
H
L
X
X
X
L
H
L
L
L
Clear
L
L
H
H
Z
Preset
L
H
H
L
Latched
Latched
H
L
H
L
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−55°C to +125°C
−55°C to +150°C
−0.5V to +7.0V
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
VIL
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
VCD
VOH
−1.2
Min
Min
I
I
I
I
I
I
IN = −18 mA
OH = −1 mA
OH = −3 mA
OH = −1 mA
OH = −3 mA
OL = 24 mA
10% VCC
10% VCC
5% VCC
5% VCC
10% VCC
2.5
2.4
2.7
2.7
Voltage
V
VOL
IIH
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
0.5
5.0
V
Min
µA
Max
V
IN = 2.7V
IBVI
7.0
50
µA
µA
V
Max
Max
0.0
V
IN = 7.0V
ICEX
Output HIGH
V
OUT = VCC
Leakage Current
Input Leakage
VID
I
ID = 1.9 µA
All other pins grounded
IOD = 150 mV
All other pins grounded
4.75
Test
IOD
Output Leakage
V
3.75
µA
0.0
Circuit Current
IIL
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
−0.6
50
mA
µA
Max
Max
Max
Max
0.0V
Max
V
V
V
V
V
IN = 0.5V
IOZH
IOZL
IOS
IZZ
OUT = 2.7V
OUT = 0.5V
OUT = 0V
−50
−150
500
90
µA
−60
mA
µA
OUT = 5.25V
ICC
65
mA
3
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AC Electrical Characteristics
T
A = +25°C
T
A = 0°C to +70°C
CC = +5.0V
L = 50 pF
Max
VCC = +5.0V
V
Symbol
Parameter
Units
C
L = 50 pF
C
Min
2.5
1.5
5.0
2.0
Typ
5.4
4.2
8.5
4.7
Max
8.0
Min
2.0
1.5
4.5
2.0
tPLH
Propagation Delay
Dn to On
9.0
7.0
ns
ns
ns
ns
ns
ns
tPHL
tPLH
tPHL
tPLH
6.5
Propagation Delay
LE to On
12.0
7.5
13.5
8.0
Propagation Delay
PRE to On
3.0
3.0
7.3
6.9
10.0
10.0
2.5
2.5
11.0
11.0
tPHL
Propagation Delay
CLR to On
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
OE to On
2.5
2.5
1.0
1.0
5.0
6.1
3.6
3.4
8.5
9.0
6.5
6.5
2.0
2.0
1.0
1.0
9.5
10.0
7.5
Output Disable Time
OE to On
7.5
AC Operating Requirements
T
A = +25°C
CC = +5.0V
Max
T
A = 0°C to +70°C
CC = +5.0V
Max
Symbol
Parameter
V
V
Units
Min
2.0
2.0
2.5
3.0
4.0
Min
2.5
2.5
3.0
3.5
4.0
tS(H)
Setup Time, HIGH or LOW
Dn to LE
tS(L)
tH(H)
tH(L)
tW(H)
ns
Hold Time, HIGH or LOW
Dn to LE
LE Pulse Width, HIGH
ns
ns
ns
ns
ns
tW(L)
tW(L)
tREC
tREC
PRE Pulse Width, LOW
CLR Pulse Width, LOW
PRE Recovery Time
CLR Recovery Time
5.0
5.0
5.0
5.0
10.0
12.0
10.0
13.0
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4
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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