74LVC573AM [ETC]
LATCH|SINGLE|8-BIT|LVC-CMOS|SOP|20PIN|PLASTIC ;型号: | 74LVC573AM |
厂家: | ETC |
描述: | LATCH|SINGLE|8-BIT|LVC-CMOS|SOP|20PIN|PLASTIC 逻辑集成电路 光电二极管 驱动 |
文件: | 总10页 (文件大小:77K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LVC573A
OCTAL D-TYPE LATCH
HIGH PERFORMANCE
■
■
■
5V TOLERANT INPUTS
HIGH SPEED: t = 6.8ns (MAX.) at V = 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
PD
CC
■
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 24mA (MIN) at V = 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
OH
OL
CC
SOP
TSSOP
■
■
BALANCED PROPAGATION DELAYS:
t
t
PHL
PLH
ORDER CODES
PACKAGE
■
OPERATING VOLTAGE RANGE:
(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
V
CC
TUBE
T & R
SOP
74LVC573AM
74LVC573AMTR
74LVC573ATTR
■
■
■
TSSOP
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components. It has more speed performance at
3.3V than 5V AC/ACT family, combined with a
lower power consumption.
DESCRIPTION
The 74LVC573A is a low voltage CMOS OCTAL
D-TYPE LATCH fabricated with sub-micron silicon
gate and double-layer metal wiring C MOS
technology. It is ideal for 1.65 to 3.6 V
operations and low power and low noise
applications.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
2
CC
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2002
1/10
74LVC573A
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
PIN No
SYMBOL
NAME AND FUNCTION
INPUTS
OUTPUT
1
OE
3 State Output Enable
Input (Active LOW)
OE
LE
D
Q
H
X
X
Z
2, 3, 4, 5, 6,
7, 8, 9
D0 to D7
Q0 to Q7
Data Inputs
NO
CHANGE
L
L
X
12, 13, 14,
15, 16, 17,
18, 19
3-State Latch Outputs
L
L
H
H
L
L
H
H
11
10
20
LE
Latch Enable Input
Ground (0V)
X : Don’t Care
Z : High Impedance
GND
V
Positive Supply Voltage
CC
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
V
V
CC
V
DC Input Voltage
DC Output Voltage (V
I
V
= 0V)
CC
V
O
O
V
I
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
-0.5 to V
+ 0.5
CC
V
- 50
mA
mA
mA
mA
°C
°C
IK
I
DC Output Diode Current (note 2)
DC Output Current
- 50
± 50
OK
I
O
I
or I
T
DC V
or Ground Current per Supply Pin
CC
± 100
CC
GND
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I absolute maximum rating must be observed
O
2) V < GND
O
2/10
74LVC573A
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage (note 1)
Input Voltage
1.65 to 3.6
0 to 5.5
V
V
CC
V
I
V
Output Voltage (V
= 0V)
CC
0 to 5.5
V
O
V
Output Voltage (High or Low State)
0 to V
V
O
CC
I
I
I
I
, I
High or Low Level Output Current (V = 3.0 to 3.6V)
± 24
± 12
mA
mA
mA
mA
°C
ns/V
OH OL
CC
, I
High or Low Level Output Current (V = 2.7 to 3.0V)
OH OL
CC
, I
High or Low Level Output Current (V = 2.3 to 2.7V)
± 8
OH OL
CC
, I
High or Low Level Output Current (V = 1.65 to 2.3V)
± 4
OH OL
CC
T
Operating Temperature
-55 to 125
0 to 10
op
dt/dv
Input Rise and Fall Time (note 2)
1) Truth Table guaranteed: 1.2V to 3.6V
2) V from 0.8V to 2V at V = 3.0V
IN
CC
DC SPECIFICATIONS
Test Condition
Value
Symbol
Parameter
-40 to 85 °C
-55 to 125 °C
Unit
V
CC
(V)
Min.
Max.
Min.
Max.
V
High Level Input
Voltage
0.65V
0.65V
CC
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
IH
CC
V
V
1.7
2
1.7
2
V
Low Level Input
Voltage
0.35V
0.35V
CC
IL
CC
0.7
0.8
0.7
0.8
V
High Level Output
Voltage
I =-100 µA
V
-0.2
V
-0.2
CC
1.65 to 3.6
1.65
2.3
OH
O
CC
I =-4 mA
1.2
1.7
2.2
2.4
2.2
1.2
1.7
2.2
2.4
2.2
O
I =-8 mA
O
V
I =-12 mA
2.7
O
I =-18 mA
3.0
O
I =-24 mA
3.0
O
V
Low Level Output
Voltage
I =100 µA
1.65 to 3.6
1.65
2.3
0.2
0.2
0.45
0.7
OL
O
I =4 mA
0.45
0.7
O
I =8 mA
V
O
I =12 mA
2.7
0.4
0.4
O
I =24 mA
3.0
0.55
0.55
O
I
Input Leakage
Current
I
V = 0 to 5.5V
3.6
± 5
± 5
µA
I
I
Power Off Leakage
Current
off
V or V = 5.5V
0
10
10
µA
µA
I
O
I
High Impedance
Output Leakage
Current
3.6
V = V orV
± 5
± 5
OZ
I
IH
IL
V
= 0 to 5.5V
O
I
Quiescent Supply
Current
V = V or GND
I CC
10
± 10
500
10
CC
3.6
µA
µA
V or V = 3.6 to
I
O
± 10
500
5.5V
∆I
I
incr. per Input
V
= V -0.6V
2.7 to 3.6
CC
CC
IH
CC
3/10
74LVC573A
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Value
T = 25 °C
Symbol
Parameter
Unit
A
V
CC
(V)
Min.
Typ.
Max.
V
Dynamic Low Level Quiet
Output (note 1)
0.8
C = 50pF
OLP
L
3.3
V
V
= 0V, V = 3.3V
V
IL
IH
-0.8
OLV
1) Number of output defined as ”n”. Measured with ”n-1” outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
AC ELECTRICAL CHARACTERISTICS
Test Condition
Value
-55 to 125 °C
Symbol
Parameter
-40 to 85 °C
Unit
V
C
R
t = t
CC
L
L
s
r
(V)
(pF)
(Ω)
(ns)
Min.
Max.
Min.
Max.
t
t
Propagation Delay
Time D to Q
1.65 to 1.95
2.3 to 2.7
2.7
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
TBD
TBD
7.8
TBD
TBD
9.4
PLH PHL
ns
ns
ns
ns
ns
ns
1.5
1
1.5
1
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
6.8
8.2
t
t
Propagation Delay
Time LE to Q
TBD
TBD
7.8
TBD
TBD
9.4
PLH PHL
1.5
1
1.5
1
3.0 to 3.6
6.8
8.2
t
t
t
Output Enable Time 1.65 to 1.95
TBD
TBD
8.7
TBD
TBD
10.4
9.2
PZL PZH
2.3 to 2.7
2.7
1
1
1
1
3.0 to 3.6
7.7
t
Output Disable Time 1.65 to 1.95
TBD
TBD
7.6
TBD
TBD
9.1
PLZ PHZ
2.3 to 2.7
2.7
2
2
3.0 to 3.6
2
7.0
2
8.4
t
LE Pulse Width
HIGH
1.65 to 1.95
2.3 to 2.7
2.7
TBD
TBD
3.3
3.3
TBD
TBD
2
TBD
TBD
3.3
3.3
TDB
TBD
2
W
3.0 to 3.6
t
Setup Time D to LE, 1.65 to 1.95
(HIGH to LOW)
s
2.3 to 2.7
2.7
3.0 to 3.6
2
2
t
Hold Time LE (HIGH 1.65 to 1.95
to LOW) to D
TBD
TBD
1.5
1.5
TBD
TBD
1.5
1.5
h
2.3 to 2.7
ns
ns
2.7
3.0 to 3.6
t
Output To Output
Skew Time (note1,
2)
2.7 to 3.6
1
1
OSLH
t
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
2) Parameter guaranteed by design
= | t
- t
|, t
= | t
- t
|
OSLH
PLHm PLHn OSHL
PHLm PHLn
4/10
74LVC573A
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T = 25 °C
Symbol
Parameter
Unit
A
V
CC
(V)
Min.
Typ.
Max.
C
Input Capacitance
4
pF
IN
C
Power Dissipation Capacitance
(note 1)
1.8
2.5
3.3
f
= 10MHz
28
30
34
PD
IN
pF
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C xV x f +I /n (per circuit)
CC(opr)
PD CC IN CC
TEST CIRCUIT
R
= Z
of pulse generator (typically 50Ω)
T
OUT
TEST CIRCUIT AND WAVEFORM SYMBOL VALUE
V
CC
Symbol
1.65 to 1.95V
30pF
2.3 to 2.7V
2.7V
3.0 to 3.6V
50pF
500Ω
7V
C
30pF
50pF
500Ω
6V
L
R = R
1000Ω
500Ω
L
1
V
2 x V
2 x V
CC
S
CC
V
V
V
CC
2.7V
1.5V
3.0V
3.0V
IH
CC
V
V
/2
V /2
CC
1.5V
M
CC
V
V
V
CC
3.5V
OH
CC
V
V
+ 0.15V
- 0.15V
V
+ 0.15V
- 0.15V
V
+ 0.3V
V
OL
+ 0.3V
- 0.3V
X
Y
OL
OL
OL
V
V
V
V
- 0.3V
V
OH
OH
OH
OH
t = t
<2.0ns
<2.0ns
<2.5ns
<2.5ns
r
r
5/10
74LVC573A
WAVEFORM 1: PROPAGATION DELAY, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
6/10
74LVC573A
WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
7/10
74LVC573A
SO-20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
2.65
0.2
MIN.
TYP.
MAX.
0.104
0.008
0.096
0.019
0.012
A
a1
a2
b
0.1
0.004
2.45
0.49
0.32
0.35
0.23
0.014
0.009
b1
C
0.5
0.020
c1
D
45° (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.020
0.300
0.050
0.029
L
M
S
8° (max.)
PO13L
8/10
74LVC573A
TSSOP20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
1.2
MIN.
TYP.
MAX.
0.047
0.006
0.041
0.012
0.0089
0.260
0.260
0.176
A
A1
A2
b
0.05
0.8
0.15
1.05
0.30
0.20
6.6
0.002
0.031
0.007
0.004
0.252
0.244
0.169
0.004
0.039
1
0.19
0.09
6.4
c
D
6.5
6.4
0.256
0.252
E
6.2
6.6
E1
e
4.3
4.4
4.48
0.173
0.65 BSC
0.0256 BSC
K
0°
8°
0°
8°
L
0.45
0.60
0.75
0.018
0.024
0.030
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
0087225C
9/10
74LVC573A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use ofsuch information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent orpatent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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10/10
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