74VCX162245DT [ETC]
Dual 8-bit Bus Transceiver ; 双8位总线收发器\n
| 型号： | 74VCX162245DT |
| 厂家： | 
ETC |
| 描述： | Dual 8-bit Bus Transceiver
|
| 文件： | 总12页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VCX162245
Low-Voltage 1.8/2.5/3.3V
16-Bit Transceiver
With 26 W Series Resisters on A Outputs
and 3.6 V–Tolerant Inputs and Outputs
(3–State, Non–Inverting)
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The 74VCX162245 is an advanced performance, non–inverting
16–bit transceiver. It is designed for very high–speed, very low–power
operation in 1.8 V, 2.5 V or 3.3 V systems.
MARKING DIAGRAM
48
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3 V busses. It is guaranteed to be over–voltage tolerant to 3.6 V.
The VCX162245 is designed with byte control. It can be operated as
two separate octals, or with the controls tied together, as a 16–bit wide
function. It is designed with 26 W series resistors in each of the A
outputs to reduce noise. The Transmit/Receive (T/Rn) inputs
determine the direction of data flow through the bi–directional
transceiver. Transmit (active–HIGH) enables data from A ports to B
ports; Receive (active–LOW) enables data from B to A ports. The
Output Enable inputs (OEn), when HIGH, disable both A and B ports
by placing them in a HIGH Z condition.
48
74VCX162245DT
AWLYYWW
1
TSSOP–48
DT SUFFIX
CASE 1201
1
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• Designed for Low Voltage Operation: V = 1.65–3.6 V
CC
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.4 ns max for 3.0 to 3.6 V
4.3 ns max for 2.3 to 2.7 V
ORDERING INFORMATION
Device
Package
TSSOP
TSSOP
Shipping
39 / Rail
8.6 ns max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±18 mA Drive at 2.3 V
74VCX162245DT
74VCX162245DTR
2500 / Reel
±3 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• I
Specification Guarantees High Impedance When V = 0 V
OFF
CC
• Near Zero Static Supply Current in All Three Logic States (20 µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±300 mA @ 125°C
• ESD Performance: Human Body Model >2000 V; Machine Model >200 V
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
August, 2000 – Rev. 0
74VCX162245/D
This Material Copyrighted by Its Respective Manufacturer
74VCX162245
1
24
T/R1
T/R2
T/R1
B0
1
2
3
4
5
6
7
8
9
48 OE1
47 A0
46 A1
45 GND
44 A2
43 A3
48
25
OE1
OE2
B1
GND
B2
A0:7
B0:7
A8:15
B8:15
B3
V
CC
42 V
CC
B4
B5
41 A4
40 A5
39 GND
38 A6
37 A7
36 A8
35 A9
34 GND
33 A10
32 A11
One of Eight
GND 10
B6 11
Figure 2. Logic Diagram
B7 12
B8 13
1
EN1
48
T/R1
OE1
OE2
T/R2
B9 14
EN2
25
GND 15
B10 16
B11 17
EN3
24
EN4
2
3
47
1
1
2
B0
A0
A1
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
B1
V
CC
18
31 V
CC
5
B2
A2
B12 19
B13 20
GND 21
B14 22
B15 23
T/R2 24
30 A12
29 A13
28 GND
27 A14
26 A15
25 OE2
6
1
1
1
B3
B4
A3
A4
8
9
B5
A5
11
12
13
14
16
17
19
20
22
23
B6
A6
3
4
B7
B8
A7
A8
B9
A9
B10
B11
B12
B13
B14
B15
A10
A11
A12
A13
A14
A15
Figure 1. 48–Lead Pinout
(Top View)
PIN NAMES
Pins
Function
OEn
Output Enable Inputs
T/Rn
Transmit/Receive Inputs
A0–A15
B0–B15
Side A Inputs or 3–State Outputs
Side B Inputs or 3–State Outputs
Inputs
Inputs
Outputs
Outputs
OE1
T/R1
L
OE2
L
T/R2
L
L
Bus B0:7 Data to Bus A0:7
Bus A0:7 Data to Bus B0:7
High Z State on A0:7, B0:7
L
H
X
Bus B8:15 Data to Bus A8:15
Bus A8:15 Data to Bus B8:15
High Z State on A8:15, B8:15
H
L
H
X
H
H = High Voltage Level; L = Low Voltage Level; X = High or Low Voltage Level and Transitions Are Acceptable
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74VCX162245
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Value
Condition
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
–0.5 to +4.6
CC
–0.5 ≤ V ≤ +4.6
V
I
I
–0.5 ≤ V ≤ +4.6
Output in 3–State
V
O
O
–0.5 ≤ V ≤ V + 0.5
Note 1.; Outputs Active
V
O
CC
I
I
DC Input Diode Current
DC Output Diode Current
–50
V < GND
mA
mA
mA
mA
mA
mA
°C
IK
I
–50
+50
V < GND
O
OK
V
O
> V
CC
I
I
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
±50
O
±100
±100
CC
GND
T
–65 to +150
STG
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions
is not implied.
1. I absolute maximum rating must be observed.
O
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
Operating
Data Retention Only
1.65
1.2
3.3
3.3
3.6
3.6
V
V
V
Input Voltage
–0.3
3.6
V
V
I
Output Voltage
(Active State)
(3–State)
0
0
V
CC
3.6
O
A Outputs
I
I
I
I
I
I
HIGH Level Output Current, V = 3.0V – 3.6V
–12
12
–8
8
mA
mA
mA
mA
mA
mA
OH
OL
OH
OL
OH
OL
CC
LOW Level Output Current, V = 3.0V – 3.6V
CC
HIGH Level Output Current, V = 2.3V – 2.7V
CC
LOW Level Output Current, V = 2.3V – 2.7V
CC
HIGH Level Output Current, V = 1.65 – 1.95V
–3
3
CC
LOW Level Output Current, V = 1.65 – 1.95V
CC
B Outputs
I
I
I
I
I
I
HIGH Level Output Current, V = 3.0V – 3.6V
–24
24
mA
mA
mA
mA
mA
mA
°C
OH
OL
OH
OL
OH
OL
CC
LOW Level Output Current, V = 3.0V – 3.6V
CC
HIGH Level Output Current, V = 2.3V – 2.7V
–18
18
CC
LOW Level Output Current, V = 2.3V – 2.7V
CC
HIGH Level Output Current, V = 1.65 – 1.95V
–6
CC
LOW Level Output Current, V = 1.65 – 1.95V
6
CC
T
Operating Free–Air Temperature
–40
0
+85
10
A
∆t/∆V
Input Transition Rise or Fall Rate, V from 0.8V to 2.0V, V = 3.0V
ns/V
IN
CC
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74VCX162245
DC ELECTRICAL CHARACTERISTICS
T
A
= –40°C to +85°C
Symbol
Characteristic
Condition
Min
0.65 x V
1.6
Max
Unit
V
IH
HIGH Level Input Voltage (Note 2.)
V
1.65V ≤ V < 2.3V
CC
CC
2.3V ≤ V ≤ 2.7V
CC
2.7V < V ≤ 3.6V
2.0
CC
V
LOW Level Input Voltage (Note 2.)
V
V
1.65V ≤ V < 2.3V
0.35 x V
0.7
IL
CC
CC
2.3V ≤ V ≤ 2.7V
CC
2.7V < V ≤ 3.6V
0.8
CC
V
OH
HIGH Level Output Voltage
A Outputs
1.65V ≤ V ≤ 3.6V; I = –100µA
V
– 0.2
CC
OH
CC
V
= 1.65V; I = –3mA
1.4
CC
OH
V
= 2.3V; I = –4mA
2.0
1.8
1.7
2.2
2.4
2.2
CC
CC
CC
CC
CC
OH
V
= 2.3V; I = –6mA
OH
V
V
V
= 2.3V; I = –8mA
OH
= 2.7V; I = –6mA
OH
= 3.0V; I = –8mA
OH
V
CC
= 3.0V; I = –12mA
OH
V
OH
HIGH Level Output Voltage
B Outputs
1.65V ≤ V ≤ 3.6V; I = –100µA
V – 0.2
CC
V
CC
OH
V
CC
= 1.65V; I = –6mA
1.25
2.0
1.8
1.7
2.2
2.4
2.2
OH
V
= 2.3V; I = –6mA
OH
CC
CC
CC
CC
CC
CC
V
V
V
V
V
= 2.3V; I = –12mA
OH
= 2.3V; I = –18mA
OH
= 2.7V; I = –12mA
OH
= 3.0V; I = –18mA
OH
= 3.0V; I = –24mA
OH
V
LOW Level Output Voltage
A Output
1.65V ≤ V ≤ 3.6V; I = 100µA
0.2
0.3
0.4
0.6
0.4
0.55
0.8
0.2
0.3
0.4
0.6
0.4
0.4
0.55
±5.0
±10
V
OL
CC
OL
V
CC
= 1.65V; I = 3mA
OL
V
= 2.3V; I = 6mA
OL
CC
CC
CC
CC
V
= 2.3V; I = 8mA
OL
V
V
= 2.7V; I = 6mA
OL
= 3.0V; I = 8mA
OL
V
CC
= 3.0V; I = 12mA
OL
V
OL
LOW Level Output Voltage
B Output
1.65V ≤ V ≤ 3.6V; I = 100µA
V
CC
OL
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65V; I = 6mA
OL
= 2.3V; I = 12mA
OL
= 2.3V; I = 18mA
OL
= 2.7V; I = 12mA
OL
= 3.0V; I = 18mA
OL
= 3.0V; I = 24mA
OL
I
I
Input Leakage Current
3–State Output Current
1.65V ≤ V ≤ 3.6V; 0V ≤ V ≤ 3.6V
µA
µA
I
CC
I
1.65V ≤ V ≤ 3.6V; 0V ≤ V ≤ 3.6V;
OZ
CC
O
V = V or V
IL
I
IH
I
I
Power–Off Leakage Current
V
= 0V; V or V = 3.6V
10
20
µA
µA
µA
µA
OFF
CC
I
O
Quiescent Supply Current (Note 3.)
1.65V ≤ V ≤ 3.6V; V = GND or V
CC
CC
CC
I
1.65V ≤ V ≤ 3.6V; 3.6V ≤ V , V ≤ 3.6V
±20
750
CC
I
O
∆I
Increase in I per Input
2.7V < V ≤ 3.6V; V = V – 0.6V
CC IH CC
CC
CC
2. These values of V are used to test DC electrical characteristics only.
I
3. Outputs disabled or 3–state only.
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74VCX162245
AC CHARACTERISTICS (Note 4.; tR = tF = 2.0ns; CL = 30pF; RL = 500Ω)
Limits
T
A
= –40°C to +85°C
V
CC
= 3.0V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 1.65 to1.95V
Symbol
Parameter
Waveform
Min
Max
Min
Max
Min
1.5
Max
Unit
t
t
Propagation Delay
Input to Output (A > B)
1
0.8
0.8
2.5
2.5
1.0
1.0
3.0
3.0
6.0
6.0
ns
PLH
1.5
PHL
t
t
Propagation Delay
Input to Output (B > A)
1
2
2
2
2
0.8
0.8
3.4
3.4
1.0
1.0
4.3
4.3
1.5
1.5
8.6
8.6
ns
ns
ns
ns
ns
ns
PLH
PHL
t
t
Output Enable Time to
High and Low Level (A > B)
0.8
0.8
3.8
3.8
1.0
1.0
4.9
4.9
1.5
1.5
9.3
9.3
PZH
PZL
t
t
Output Enable Time to
High and Low Level (B > A)
0.8
0.8
4.2
4.2
1.0
1.0
5.7
5.7
1.5
1.5
9.8
9.8
PZH
PZL
t
t
Output Disable Time From
High and Low Level (A > B)
0.8
0.8
3.7
3.7
1.0
1.0
4.2
4.2
1.5
1.5
7.6
7.6
PHZ
PLZ
t
t
Output Disable Time From
High and Low Level (B > A)
0.8
0.8
4.1
4.1
1.0
1.0
4.8
4.8
1.5
1.5
8.6
8.6
PHZ
PLZ
t
t
Output–to–Output Skew
(Note 5.)
0.5
0.5
0.5
0.5
0.75
0.75
OSHL
OSLH
4. For C = 50pF, add approximately 300ps to the AC maximum specification.
L
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t
guaranteed by design.
) or LOW–to–HIGH (t
); parameter
OSHL
OSLH
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= +25°C
Symbol
Characteristic
Dynamic LOW Peak Voltage (A > B)
(Note 6.)
Condition
= 1.8V, C = 30pF, V = V , V = 0V
Typ
0.25
0.6
Unit
V
OLP
V
OLP
V
OLV
V
OLV
V
OHV
V
OHV
V
V
CC
L
IH
CC
IL
V
V
= 2.5V, C = 30pF, V = V , V = 0V
L IH CC IL
CC
CC
CC
= 3.3V, C = 30pF, V = V , V = 0V
0.8
L
IH
CC
IL
Dynamic LOW Peak Voltage (B > A)
(Note 6.)
V
= 1.8V, C = 30pF, V = V , V = 0V
0.15
0.25
0.35
–0.25
–0.6
–0.8
–0.15
–0.25
–0.35
1.5
V
V
V
V
V
L
IH
CC
IL
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 2.5V, C = 30pF, V = V , V = 0V
L IH CC IL
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 3.3V, C = 30pF, V = V , V = 0V
L
IH
CC
IL
Dynamic LOW Valley Voltage (A > B)
(Note 6.)
= 1.8V, C = 30pF, V = V , V = 0V
L IH CC IL
= 2.5V, C = 30pF, V = V , V = 0V
L
IH
CC
IL
= 3.3V, C = 30pF, V = V , V = 0V
L
IH
CC
IL
Dynamic LOW Valley Voltage (B > A)
(Note 6.)
= 1.8V, C = 30pF, V = V , V = 0V
L IH CC IL
= 2.5V, C = 30pF, V = V , V = 0V
L
IH
CC
IL
= 3.3V, C = 30pF, V = V , V = 0V
L
IH
CC
IL
Dynamic HIGH Valley Voltage (A > B)
(Note 7.)
= 1.8V, C = 30pF, V = V , V = 0V
L IH CC IL
= 2.5V, C = 30pF, V = V , V = 0V
1.9
L
IH
CC
IL
= 3.3V, C = 30pF, V = V , V = 0V
2.2
L
IH
CC
IL
Dynamic HIGH Valley Voltage (B > A)
(Note 7.)
= 1.8V, C = 30pF, V = V , V = 0V
1.55
2.05
2.65
L
IH
CC
IL
= 2.5V, C = 30pF, V = V , V = 0V
L
IH
CC
IL
= 3.3V, C = 30pF, V = V , V = 0V
L
IH
CC
IL
6. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is
measured in the LOW state.
7. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is
measured in the HIGH state.
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74VCX162245
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Condition
Note 8.
Typical
Unit
pF
C
C
C
6
7
IN
Output Capacitance
Note 8.
pF
OUT
PD
Power Dissipation Capacitance
Note 8., 10MHz
20
pF
8. V = 1.8, 2.5 or 3.3V; V = 0V or V
.
CC
I
CC
V
IH
Vm
Vm
An, Bn
Bn, An
0V
t
t
PHL
PLH
V
OH
OL
Vm
Vm
V
WAVEFORM 1 - PROPAGATION DELAYS
t = t = 2.0ns, 10% to 90%; f = 1MHz; t = 500ns
R
F
W
V
IH
Vm
Vm
OEn, T/Rn
0V
t
t
PHZ
PZH
V
OH
Vy
Vm
Vm
An, Bn
An, Bn
≈ 0V
t
t
PLZ
PZL
≈ V
CC
Vx
V
OL
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
t = t = 2.0ns, 10% to 90%; f = 1MHz; t = 500ns
R
F
W
Figure 3. AC Waveforms
V
CC
3.3V ±0.3V
2.5V ±0.2V
1.8V ±0.15V
Symbol
V
IH
2.7V
V
CC
V
CC
V
m
1.5V
V
CC
/2
V
CC
/2
V
V
+ 0.3V
– 0.3V
V
+ 0.15V
– 0.15V
V
+ 0.15V
– 0.15V
x
OL
OL
OL
V
y
V
OH
V
OH
V
OH
V
CC
6V or V × 2
CC
OPEN
GND
R
L
PULSE
GENERATOR
DUT
R
T
C
L
R
L
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74VCX162245
TEST
SWITCH
t
t
, t
Open
PLH PHL
, t
6V at V = 3.3 ±0.3V;
CC
× 2 at V = 2.5 ±0.2V; 1.8V ±0.15V
PZL PLZ
V
CC
CC
t
, t
GND
PZH PHZ
C = 30pF or equivalent (Includes jig and probe capacitance)
L
R = 500Ω or equivalent
L
R = Z
of pulse generator (typically 50Ω)
T
OUT
Figure 4. Test Circuit
V
IH
Vm
Vm
An, Bn
0V
t
t
PHL
PLH
V
OH
OL
Vm
Vm
Bn, An
V
WAVEFORM 3 - PROPAGATION DELAYS
t = t = 2.0ns, 10% to 90%; f = 1MHz; t = 500ns
R
F
W
V
IH
Vm
Vm
OEn, T/Rn
0V
t
t
PHZ
PZH
V
OH
Vy
Vm
Vm
An, Bn
An, Bn
≈ 0V
t
t
PLZ
PZL
≈ V
CC
Vx
V
OL
WAVEFORM 4 - OUTPUT ENABLE AND DISABLE TIMES
t = t = 2.0ns, 10% to 90%; f = 1MHz; t = 500ns
R
F
W
Figure 5. AC Waveforms
V
CC
3.3V ±0.3V
2.7V
Symbol
V
IH
2.7V
2.7V
V
m
1.5V
1.5V
V
V
+ 0.3V
– 0.3V
V
+ 0.3V
x
OL
OL
V
y
V
OH
V
OH
– 0.3V
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74VCX162245
V
CC
6V or V × 2
CC
OPEN
GND
R
L
PULSE
GENERATOR
DUT
R
T
C
L
R
L
TEST
SWITCH
t
t
, t
Open
PLH PHL
, t
6V at V = 3.3 ±0.3V;
CC
× 2 at V = 2.5 ±0.2V; 1.8 ±0.15V
PZL PLZ
V
CC
CC
t
, t
GND
PZH PHZ
C = 50pF or equivalent (Includes jig and probe capacitance)
L
R = 500Ω or equivalent
L
R = Z
of pulse generator (typically 50Ω)
T
OUT
Figure 6. Test Circuit
AC CHARACTERISTICS (tR = tF = 2.0ns; CL = 50pF; RL = 500Ω)
Limits
= –40°C to +85°C
T
A
V
CC
= 3.0V to 3.6V
V
CC
= 2.7V
Symbol
Parameter
Waveform
Min
Max
Min
Max
Unit
t
t
Propagation Delay
Input to Output
3
1.0
1.0
3.0
3.0
3.6
3.6
ns
PLH
(A > B)
(B > A)
(A > B)
(B > A)
(A > B)
(B > A)
PHL
t
t
Propagation Delay
Input to Output
3
4
4
4
4
1.0
1.0
4.2
4.2
4.7
4.7
ns
ns
ns
ns
ns
ns
PLH
PHL
t
t
Output Enable Time to
High and Low Level
1.0
1.0
4.4
4.4
5.4
5.4
PZH
PZL
t
t
Output Enable Time to
High and Low Level
1.0
1.0
5.6
5.6
6.7
6.7
PZH
PZL
t
t
Output Disable Time From
High and Low Level
1.0
1.0
4.1
4.1
4.6
4.6
PHZ
PLZ
t
t
Output Disable Time From
High and Low Level
1.0
1.0
5.5
5.5
5.7
5.7
PHZ
PLZ
t
t
Output–to–Output Skew
(Note 9.)
0.5
0.5
0.5
0.5
OSHL
OSLH
9. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t
guaranteed by design.
) or LOW–to–HIGH (t
); parameter
OSHL
OSLH
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8
This Material Copyrighted by Its Respective Manufacturer
74VCX162245
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(±0.008")
P
0
K
t
P
2
D
TOP
COVER
TAPE
E
A
B
SEE NOTE 2
+
0
F
W
+
+
K
0
B
1
0
SEE
NOTE 2
D
1
P
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
EMBOSSMENT
USER DIRECTION OF FEED
CENTER LINES
OF CAVITY
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B
0
*TOP COVER
TAPE THICKNESS (t )
1
0.10 mm
(0.004") MAX.
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
EMBOSSED
CARRIER
BENDING RADIUS
EMBOSSMENT
100 mm
(3.937")
MAXIMUM COMPONENT ROTATION
10°
1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE
TAPE
1 mm
(0.039") MAX
250 mm
(9.843")
TYPICAL
COMPONENT
CENTER LINE
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 7. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape
Size
B
1
Max
D
D
E
F
K
P
P
0
P
2
R
T
W
1
24mm
20.1mm 1.5 + 0.1mm
(0.791")
1.5mm
Min
(0.060")
1.75
11.5
11.9 mm
Max
(0.468")
16.0
±0.1 mm
(0.63
4.0
±0.1 mm
(0.157
2.0
±0.1 mm
(0.079
30 mm
(1.18")
0.6 mm
(0.024")
24.3 mm
(0.957")
-0.0
(0.059
+0.004" -0.0)
±0.1 mm ±0.10 mm
(0.069
±0.004")
(0.453
±0.004")
±0.004")
±0.004")
±0.004")
1. Metric Dimensions Govern–English are in parentheses for reference only.
2. A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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9
This Material Copyrighted by Its Respective Manufacturer
74VCX162245
t MAX
13.0 mm ±0.2 mm
(0.512" ±0.008")
1.5 mm MIN
(0.06")
20.2 mm MIN
(0.795")
50 mm MIN
(1.969")
A
FULL RADIUS
G
Figure 8. Reel Dimensions
REEL DIMENSIONS
Tape Size
A Max
G
t Max
24 mm
360 mm
(14.173")
24.4 mm + 2.0 mm, -0.0
(0.961" + 0.078", -0.00)
30.4 mm
(1.197")
DIRECTION OF FEED
BARCODE LABEL
POCKET
HOLE
Figure 9. Reel Winding Direction
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10
This Material Copyrighted by Its Respective Manufacturer
74VCX162245
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
CAVITY TOP TAPE
TAPE
DIRECTION OF FEED
Figure 10. Tape Ends for Finished Goods
User Direction of Feed
Figure 11. Reel Configuration
F
K
G
L
48 Leads
Package Footprint
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This Material Copyrighted by Its Respective Manufacturer
74VCX162245
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
CASE 1201–01
ISSUE A
48X K REF
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.12 (0.005)
T U
J
J1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
48
25
SECTION N–N
B
–U–
L
N
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
24
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
MILLIMETERS
INCHES
A
–V–
PIN 1
DIM MIN
MAX
12.60
6.20 0.236
1.10 ---
MIN
0.488
MAX
0.496
0.244
0.043
0.006
0.030
IDENT.
A
B
C
D
F
G
H
J
J1
K
K1
L
12.40
6.00
---
N
M
F
0.05
0.50
0.15 0.002
0.75 0.020
0.25 (0.010)
DETAIL E
0.50 BSC
0.0197 BSC
0.37
0.09
0.09
0.17
0.17
7.95
0
--- 0.015
0.20 0.004
0.16 0.004
0.27 0.007
0.23 0.007
8.25 0.313
---
0.008
0.006
0.011
0.009
0.325
8
D
C
–W–
0.076 (0.003)
M
8
0
_
_
_
_
DETAIL E
–T–
SEATING
PLANE
H
G
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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CENTRAL/SOUTH AMERICA:
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EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
For additional information, please contact your local
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*Available from Germany, France, Italy, UK
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