74VHV02N [ETC]
IC-74VHC SERIES ; IC- 74VHC系列\nNovember 1992
Revised March 1999
74VHC02
Quad 2-Input NOR Gate
as battery backup. This circuit prevents device destruction
due to mismatched supply and input voltages.
General Description
The VHC02 is an advanced high-speed CMOS 2-Input
NOR Gate fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The internal circuit is composed of 3
stages, including buffer output, which provide high noise
immunity and stable output. An input protection circuit
insures that 0V to 7V can be applied to the input pins with-
out regard to the supply voltage. This device can be used
to interface 5V to 3V systems and two supply systems such
Features
■ High Speed: tPD = 3.6 ns (typ) at VCC = 5V
■ Low power dissipation: ICC = 2 µA (max) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: VOLP = 0.8V (max)
■ Pin and function compatible with 74HC02
Ordering Code:
Order Number Package Number
Package Description
74VHC02M
74VHC02SJ
74VHC02MTC
74VHC02N
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Truth Table
Pin Names
Description
Inputs
Outputs
A
L
B
L
O
H
L
An, Bn
On
L
H
L
H
H
L
H
L
© 1999 Fairchild Semiconductor Corporation
DS011515.prf
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Input Diode Current (IIK
Output Diode Current (IOK
DC Output Current (IOUT
DC VCC/GND Current (ICC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to VCC + 0.5V
−20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
Input Rise and Fall Time (tr, tf)
)
2.0V to +5.5V
0V to +5.5V
)
)
)
)
0V to VCC
)
±20 mA
)
−40°C to +85°C
)
±25 mA
)
±50 mA
V
V
CC = 3.3V ± 0.3V
CC = 5.0V ± 0.5V
0
100 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
−65°C to +150°C
0 20 ns/V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
260°C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
Conditions
Min
Typ
Max
Min
1.50
0.7 V
Max
V
V
V
HIGH Level
2.0
1.50
IH
V
V
Input Voltage
LOW Level
3.0 − 5.5 0.7 V
2.0
CC
CC
0.50
0.50
IL
Input Voltage
HIGH Level
Output Voltage
3.0 − 5.5
0.3 V
0.3 V
CC
CC
2.0
3.0
1.9
2.0
3.0
4.5
1.9
2.9
V
V
= V I = −50 µA
IH OH
OH
IN
2.9
4.4
V
V
V
V
or V
IL
4.5
4.4
3.0
2.58
3.94
2.48
3.80
I
I
= −4 mA
= −8 mA
= 50 µA
OH
OH
4.5
V
LOW Level
2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
= V I
IH OL
OL
IN
Output Voltage
3.0
or V
IL
4.5
0.1
0.1
3.0
0.36
0.36
±0.1
2.0
0.44
0.44
±1.0
20.0
I
I
= 4 mA
= 8 mA
OL
OL
4.5
I
I
Input Leakage Current
0 − 5.5
5.5
µA
µA
V
V
= 5.5V or GND
IN
CC
IN
Quiescent Supply Current
= V or GND
CC
IN
Noise Characteristics
T
= 25°C
A
V
(V)
CC
Symbol
Parameter
Units
Conditions
Typ
Limits
V
Quiet Output Maximum
5.0
0.3
0.8
−0.8
3.5
V
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
OLP
L
L
L
L
(Note 3)
Dynamic V
OL
V
Quiet Output Minimum
Dynamic V
5.0
5.0
5.0
−0.3
V
V
V
C
C
C
OLV
(Note 3)
OL
V
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
IHD
(Note 3)
V
1.5
ILD
(Note 3)
Note 3: Parameter guaranteed by design.
www.fairchildsemi.com
2
AC Electrical Characteristics
T
= 25°C
T = −40°C to +85°C
A
V
(V)
A
CC
Symbol
Parameter
Units
ns
Conditions
Min
Typ
5.6
8.1
3.6
5.1
4
Max
7.9
11.4
5.5
7.5
10
Min
Max
9.5
13.0
6.5
8.5
10
t
t
Propagation Delay
3.3 ± 0.3
1.0
1.0
1.0
1.0
C
C
C
C
= 15 pF
= 50 pF
= 15 pF
= 50 pF
PHL
PLH
L
L
5.0 ± 0.5
L
ns
L
C
C
Input Capacitance
Power Dissipation
Capacitance
pF
pF
V
= Open
CC
IN
15
(Note 4)
PD
Note 4: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I (opr.) = C * V * f + I /4 (per gate).
CC
PD
CC
IN
CC
3
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package MTC14
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
相关型号:
![](http://pdffile.icpdf.com/pdf1/p00096/img/page/74VMEH22501ADGGRE4_513419_files/74VMEH22501ADGGRE4_513419_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00096/img/page/74VMEH22501ADGGRE4_513419_files/74VMEH22501ADGGRE4_513419_2.jpg)
74VMEH22501ADGGRE4
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
TI
![](http://pdffile.icpdf.com/pdf2/p00280/img/page/74VMEH22501A_1674535_files/74VMEH22501A_1674535_1.jpg)
![](http://pdffile.icpdf.com/pdf2/p00280/img/page/74VMEH22501A_1674535_files/74VMEH22501A_1674535_2.jpg)
74VMEH22501ADGGRG4
74V SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48
TI
![](http://pdffile.icpdf.com/pdf1/p00096/img/page/74VMEH22501ADGGRE4_513419_files/74VMEH22501ADGGRE4_513419_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00096/img/page/74VMEH22501ADGGRE4_513419_files/74VMEH22501ADGGRE4_513419_2.jpg)
74VMEH22501ADGVRE4
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
TI
![](http://pdffile.icpdf.com/pdf1/p00096/img/page/74VMEH22501ADGGRE4_513419_files/74VMEH22501ADGGRE4_513419_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00096/img/page/74VMEH22501ADGGRE4_513419_files/74VMEH22501ADGGRE4_513419_2.jpg)
74VMEH22501ADGVRG4
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
TI
![](http://pdffile.icpdf.com/pdf1/p00125/img/page/74VMEH22501DGGRE4_692684_files/74VMEH22501DGGRE4_692684_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00125/img/page/74VMEH22501DGGRE4_692684_files/74VMEH22501DGGRE4_692684_2.jpg)
74VMEH22501DGGRE4
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
TI
![](http://pdffile.icpdf.com/pdf1/p00125/img/page/74VMEH22501DGGRE4_692684_files/74VMEH22501DGGRE4_692684_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00125/img/page/74VMEH22501DGGRE4_692684_files/74VMEH22501DGGRE4_692684_2.jpg)
74VMEH22501DGGRG4
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
TI
![](http://pdffile.icpdf.com/pdf1/p00125/img/page/74VMEH22501DGGRE4_692684_files/74VMEH22501DGGRE4_692684_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00125/img/page/74VMEH22501DGGRE4_692684_files/74VMEH22501DGGRE4_692684_2.jpg)
74VMEH22501DGVRE4
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
TI
![](http://pdffile.icpdf.com/pdf1/p00125/img/page/74VMEH22501DGGRE4_692684_files/74VMEH22501DGGRE4_692684_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00125/img/page/74VMEH22501DGGRE4_692684_files/74VMEH22501DGGRE4_692684_2.jpg)
74VMEH22501DGVRG4
8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
TI
©2020 ICPDF网 联系我们和版权申明