7P064FLF1200C25 [ETC]

Peripheral Miscellaneous ; 周边其他\n


型号：	7P064FLF1200C25
厂家：	ETC
描述：	Peripheral Miscellaneous 周边其他\n 内存集成电路
文件：	总17页 (文件大小：204K)
中文：	中文翻译
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PCMCIA Flash Memory Card

FLF10 Series

High Density FLASH Memory Card 32, 64, 96, 128, 160, 192 MEGABYTE

General Description

Features

WEDC’s Flash memory cards - FLF10 Series - offer high density

linear Flash memory for code and data storage, high performance

disk emulation, mobile PC and embedded applications.

• Low cost, high density Linear Flash

Card

• Universal 3V to 5V operating range

providing full “plug and play”

exchangeability between different

systems

The WEDC FLF10 series is based on Intel’s Multi Level Cell

(MLC) Flash memory technology, providing high density Flash

components at a significantly lower cost per megabyte. MLC

technology allows for two bits of information to be stored in a single

cell. This leads to reduced die size and reduced cost per megabyte.

• Based on Intel 28F128J3A (MLC)

Components

WEDC’s FLF10 series cards are built with Intel’s 128Mb memory

component, 28F128J3A, with a manufacturer/device ID of 89/18_H.

The FLF10 series is available in densities of 32, 64, 96, 128, 160,

and 192MB.

• Fast Read Performance

- 250ns Maximum Access Time

- (200ns optional)

•PCMCIA compatible

WEDC’s FLF10 series provides densities from 32MB to 192MB, in

32MB increments. The cards up to the 64MB density operate in the

regular PCMCIA mode. The densities beyond the 64MB density

are implemented using a “paging scheme”, which is also supported

by the PCMCIA standard. By writing a page address to the

Configuration Option Register (address 4000H), an additional page

of memory can be accessed. The current FLF10 series supports

densities to 192MB: total of 3 pages: page 0 := 64MB, page 1 :=

64MB, and page 2 := 64MB.

- x8/ x16 Data Interface

• 32-Byte Write Buffer (per Memory

Device)

- 6µs per Byte Effective Write Time

•128-bit Protection Register (per Memory

Device)

-64-bit Unique Device Identifier

-64-bit User Programmable OTP

Cells

The FLF10 series card operates in a wide, universal voltage range,

from 3V to 5V, allowing full “plug and play” functionality and

upgrade solutions in all mobile, battery powered applications.

•Cross-Compatible Command Support

- Common Flash Interface (CFI)

- Intel Basic Command Set

Each memory component in the card also has a 128-bit Protection

Programmable) Cells. These cells can be programmed with a

numeric security measure, such as an electronic signature.

- Scaleable Command Set

• Power-Down Mode

- Reset, Power Down Registers

To provide a 16 bit word wide access supported by the PCMCIA

standard, devices are paired on the card. Therefore, the Flash array

is structured in 128K word (256kB) blocks. Write, read and block

erase operations can be performed as either a word or byte wide

operation.

• 100,000 Erase Cycles per Block

• 128K word symmetrical Block

Architecture

• PC Card Standard Type I Form Factor

The FLF10 series cards conform to the PC Card 95 Standard

supported by PCMCIA and JEIDA, providing electrical and

physical compatibility. The PC Card form factor offers an industry

standard pinout and mechanical outline, allowing density upgrades

without system design changes.

WEDC’s standard cards are shipped with WEDC’s Flash Logo.

Cards are also available with blank housings (no Logo). The blank

housings are available in both, a recessed (for label) or flat housing.

Please contact your WEDC sales representative for further

information on Custom artwork.

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

Block Diagram

N x 28F128J3A

Device Pair (N/2 - 1)

CLn

CH0

Device (N-1)

Device (N-2)

(B26)

A1-A23

ADDRESS BUS

A1-A25

(A1-A25)

ADDRESS

BUFFER

A24, A25, B26

B26, (B27..)

D5-D0=Page Number (PN)

SRes

LvReq

- Page Number (PN) -

D4 D3

M Res

/WRi

Configuration Option Register: A=4000h (Read/Write)

/RDi

/WE

CHn

/OE

control

logic

CH0

CLn

/CE2

/CE1

Device Pair 1

Ctrl

SR Clr

Reg Clr

CL0

CL1

CL0

/REG

Device 3

Device 2

Device 0

CH0

ADDRESS Register NAME

At/Reg enable

4008h

4006h

4004h

Device Pair 0

Management

4000h

0000h

4002h Config. and Status Reg.

4000h

Device 1

Registers

CH0

Configuration Option Register

attrib. mem

CIS

E²PROM 2kB

DATA

BUS

DATA

BUS

Q0-Q7

Q8-Q15

control

Q0-Q7

I/O buffer

DATA

BUS

D0-D7

DATA

BUS

D8-D15

Reset

M Res

SR Clr

reset circuit

220k

Reg Clr

Vcc

D0 - D15

Configuration Option Register: ADRS=4000h

Read/Write

CD1

CD2

SRes

- Page Number (PN) -

D4 D3 D2

LvReq

(3V-5V)

Vcc

Soft Reset, active High

1=Reset State

GND

0=End Reset State

WAIT

OPEN

R/B(N-1)

LevelReq (not supported)

D5-D0

Configuration index

D5-D2 reserved

R/BUSY

R/B1

R/B0

D0:D1

Page Number Config. (PN)

Power On default =0

VS1

VS2

OPEN

Configuration Status Register: ADRS=4002h

Read/Write

PwrDwn reserved

D2 D1 D0

OPEN

10k

BVD1

BVD2

Vcc

reserved

D6 D5

Power Down; active High

1 = Place all memory devices in power down mode

0 = normal operation Power On default=0

Vpp2

Vpp1

N.C.

/CE1, /CE2,/OE, /WE, /Reg:

pull up

typ 100k

A0:

pull down typ 100k

pull down typ 220k

Manufacturer ID

Intel 89_H

Reset:

Device ID 28F128J3A 18_H

R/Busy - Open Drain output

pull up

typ 100k

FLF10 Flash Card

based on Strata Flash 28F128J3A

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

Pinout

Signal name I/O

GND

Function

Ground

Data bit 3

Data bit 4

Data bit 5

Active

Signal name I/O

GND

Function

Ground

Card Detect 1

Data bit 11

Data bit 12

Data bit 13

Data bit 14

Data bit 15

Card Enable 2

Voltage Sense 1

Reserved

Active

LOW

DQ3

DQ4

DQ5

DQ6

DQ7

CE1#

A10

I/O

CD1#

DQ11

DQ12

DQ13

DQ14

DQ15

CE2#

VS1

I/O

Data bit 6

Data bit 7

Card enable 1

Address bit 10

Output enable

Address bit 11

Address bit 9

Address bit 8

Address bit 13

Address bit 14

Write Enable

Ready/Busy

Supply Voltage

Prog. Voltage

Address bit 16

Address bit 15

Address bit 12

Address bit 7

Address bit 6

Address bit 5

Address bit 4

Address bit 3

Address bit 2

Address bit 1

Address bit 0

Data bit 0

LOW

NC (2)

OE#

A11

RFU

Reserved

A17

A18

A19

A20

Address bit 17

Address bit 18

Address bit 19

Address bit 20

Address bit 21

Supply Voltage

Prog. Voltage

Address bit 22

Address bit 23

Address bit 24

Address bit 25

Voltage Sense 2

Card Reset

Extended Bus cycle LOW(3)

Reserved

Attrib Mem Select

Bat. Volt. Detect 2

Bat. Volt. Detect 1

Data bit 8

A13

A14

WE#

RDY/BSY#

Vcc

LOW

LOW(1)

A21

Vcc

Vpp1

A16

N.C.

Vpp2

A22

A23

N.C.

A15

A12

A24

A25

VS2

RST

N.C.

HIGH

Wait#

RFU

REG#

BVD2

BVD1

DQ8

DQ9

DQ10

CD2#

GND

I/O

(3)

DQ0

DQ1

DQ2

I/O

Data bit 1

Data bit 2

Write Potect

Ground

Data bit 9

Data bit 10

Card Detect 2

Ground

HIGH

LOW

GND

Notes:

1. RDY/BSY signal is an open drain type output, pull-up resistors are required on the host side.

2. VS1 is connected to GND.

3. Wait#, BVD1 and BVD2 are internally connected to Vcc by resistors for compatibility.

Mechanical

Interconnect area

1.6mm ± 0.05

10.0mm MIN

(0.400”)

3.0mm MIN

(0.063”)

1.0mm ± 0.05

(0.039”)

Substrate area

54.0mm ± 0.10

(2.126”)

85.6mm ± 0.20

(3.370”)

1.0mm ± 0.05

(0.039”)

10.0mm MIN

(0.400”)

3.3mm ± T1 (0.130”)

T1=0.10mm interconnect area

T1=0.20mm substrate area

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

Card Signal Description

Symbol

A0 - A25

Type

INPUT

Name and Function

ADDRESS INPUTS: A0 through A25 enable direct addressing of up

to 64MB of memory on the card. Signal A0 is not used in word access

mode. A25 is the most significant bit

DQ0 - DQ15

CE1#, CE2#

INPUT/OUTPUT DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the

bi-directional databus. DQ15 is the MSB.

INPUT

CARD ENABLE 1 AND 2: CE1#enables even byte accesses, CE2#

enables odd byte accesses. Multiplexing A0, CE1#and CE2#allows 8-

bit hosts to access all data on DQ0 - DQ7 (see truth table).

OUTPUT ENABLE: Active low signal gating read data from the

memory card.

OE#

INPUT

WE#

INPUT

WRITE ENABLE: Active low signal gating write data to the memory

card.

RDY/BSY#

OUTPUT

READY/BUSY OUTPUT: Indicates status of internally timed erase

or program algorithms. A high output indicates that the card is ready to

accept accesses. A low output indicates that one or more devices in the

memory card are busy with internally timed erase or write activities.

CARD DETECT 1 and 2: Provide card insertion detection. These

signals are internally connected to ground on the card. The host shall

monitor these signals to detect card insertion. Pulled up on host side.

WRITE PROTECT: Write protect reflects the status of the Write

Protect switch on the memory card. WP set to high = write protected,

providing internal hardware write lockout to the Flash array.

If card does not include optional write protect switch, this signal will be

pulled low internally indicating write protect = "off".

PROGRAMMING VOLTAGES: Not connected

CD1#, CD2#

OUTPUT

VPP1, VPP2

VCC

GND

N.C.

CARD POWER SUPPLY: Universal 3V to 5V Supply

CARD GROUND

REG#

INPUT

ATTRIBUTE MEMORY SELECT: Active low signal, enables

access to attribute memory space, occupied by the Card Information

Structure (CIS) and Card Registers.

RST

INPUT

RESET: Active high signal for placing card in Power-on default state.

Reset can be used as a Power-Down control for the memory array.

WAIT: This signal is pulled high internally for compatibility. No wait

states are generated.

BA TTERY VOLTAG E D ETEC T: These signals are pulled high to

maintain SRAM card compatibility.

VOLTAGE SENSE: Notifies the host socket of the card's VCC

requirements. VS1 grounded and VS2 is open to indicate a 3/5V card.

RESERVED FOR FUTURE USE

NO INTERNAL CONNECTION TO CARD: pin may be driven

or left floating.

WAIT#

BVD1, BVD2

VS1, VS2

OUTPUT

RFU

N.C.

Functional Truth Table

READ function

Common Memory

Attribute Memory

Function Mode

/CE2 /CE1 A0

/OE /WE

/REG D15-D8

D7-D0

High-Z

/REG D15-D8

D7-D0

High-Z

Standby Mode

Byte Access (8 bits)

High-Z

High-Z Even-Byte

High-Z Not Valid

Not Valid Even-Byte

Not Valid

High-Z Even-Byte

High-Z Odd-Byte

Odd-Byte Even-Byte

Word Access (16 bits)

Odd-Byte Only Access

WRITE function

Odd-Byte

High-Z

Standby Mode

Byte Access (8 bits)

Even-Byte

Odd-Byte

Even-Byte

Word Access (16 bits)

Odd-Byte Only Access

Odd-Byte Even-Byte

Odd-Byte

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

Card Interface

The FLF10 series flash card complies with PC Card standard (PCMCIA, March 1997). While maintaining

PCMCIA compatibility, the FLF10 series card has integrated special features to extend functionality.

The card has built-in 2 control registers:

- Configuration Option Register (COR)

- Configuration and Status Register (CSR)

Address = 4000_h

Address = 4002_h

COR register: provides a soft reset function (bit D7) and additional page bits (bits D0 and D1) to extend

card capacity beyond 64MB.

SReset

As defined by PCMCIA, setting the SReset bit to 1, places the card in the reset state. During this state

all memory devices are placed in power down mode, minimizing power consumption. Returning this bit

to 0 leaves the reset cycle and places the card in the same condition as following a power up or hardware

reset. This bit must be cleared to 0, to access any device on the card.

Complete soft reset cycle must consist of a 2 step write sequence to the SReset bit:

1. Initialization: write 1 to SReset

- reset cycle begin

- memory devices enters Power-Down mode aborting all operations and clearing all registers.

2. Write 0 to SReset

- Reset cycle ends

- memory devices and registers enter power on default state

The card can also be placed in Power Down mode by activating the Reset signal (pin58) or by

controlling the bit D2 (PwrDwn) in the CSR register.

LevlRequest

Not supported

Configuration Index

Configuration Index bits (D0 - D5) are defined to provide address extension bits -page address, to extend

card capacity beyond 64MB.

Only bits D0 and D1 are supported:

- D1D0 set to 00_bin(0_H) selects

- D1D0 set to 01_bin(1_H) selects:

page 0

page 1

- D1D0 set to10_bin(2_H) selects:page 2

- D1D0 set to11_bin(3_H) selects:page 3 (No Memory Access)

D1D0 is set to the value of 00_bin(0_H) during any reset cycle (Power on Reset, Hardware

Reset, and SReset). Attempting to access page 3 will not result in the writing or reading of

data.

CSR register: provides a power control of the memory array. Only bit D2 is supported; all other bits are

“don’t care”

PwrDwn

Writing 1 to PwrDwn bit (D2) forces each memory device on the card into a reset/power down mode by

asserting all the devices RP# pins. Writing 0 to the bit returns the array to stand by mode.

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

The Card Information Structure (CIS) contains information about Register addressing and Memory

structure.

Cards with memory capacity up to 64MB do not support Configuration Index bits.

Notes:

1. Reading from undefined address location or unsupported bits will return random data.

2. Writing to undefined address location may result in card malfunctioning due to limited

address decoding.

3. See block diagram for more details about control registers.

Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing

of the status register, and, when V_PEN= V_PENH, block erasure, program, and lock-bit configuration.

The Block Erase command requires appropriate command data and an address within the block to be erased.

The Byte/Word Program command requires the command and address of the location to be written. Set Block

Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits

command requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE#

is active. The address and data needed to execute a command are latched on the rising edge of WE# or the

first edge of CE₀, CE₁, or CE₂that disables the device. Standard microprocessor write timings are used.

For information regarding modes of operation, commands, and

programming details for the memory components, please consult the

Intel 28F128J3A data sheet.

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

Absolute Maximum Ratings ⁽²⁾

Note:

Stress greater than those listed under

“Absolute Maximum ratings” may cause

permanent damage to the device. This is a

stress rating only and functional operation at

these or any other conditions greater than

those indicated in the operational sections of

this specification is not implied. Exposure to

absolute maximum rating conditions for

extended periods may affect reliability.

Operating Temperature TA (ambient)

Commercial

Storage Temperature

Voltage on any pin relative to VSS

VCC supply Voltage relative to VSS

0°C to +60 °C

-10°C to +70 °C

-0.5V to VCC+0.5V

-0.5V to +7.0V

Recommended Supply Voltage

VCC

Tolerance

Note: The FLF10 Series Card will

3.3V

5.0V

0.3V

0.5V

function at either 3.3V or 5.0V

DC Characteristics ⁽¹⁾

Symbol Parameter

Density

Notes Typ⁽³⁾Max Units Test Conditions

(Mbytes)

ICCR

ICCW

ICCE

ICCD

VCC Read Current 32,64,96,128,

160,192

110 mA

120 mA

140 mA

VCC = VCCmax

tcycle = 200ns

2 memory devices

VCC Program

Current

32,64,96,128,

160, 192

VCC Erase Current 32,64,96,128,

160,192

2 memory devices

VCC Power-down

Current

100

200

300

400

500

600

0.1

0.2

0.3

0.4

0.5

0.6

200 µA

400

600

800

1000

1200

VCC = VCCmax

Control Signals = VCC

Reset = VCC (active)

128

160

192

ICCS

(CMOS) Current

VCC Standby

0.2

0.4

0.6

0.8

1.0

1.2

VCC = VCCmax

Control Signals = VCC

128

160

192

Reset = 0V (not active)

CMOS Test Conditions: VCC = 5V ± 5%, VIL = VSS ± 0.2V, VIH = VCC ± 0.2V

Notes:

1. All currents are RMS values unless otherwise specified. ICCR, ICCW and ICCE are based on Word wide

operations (2 memory devices activated).

2. Control Signals: CE₁#, CE₂#, OE#, WE#.

3. Typical: VCC = 5V or VCC = 3V, T = +25°C.

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

VCC = 3.3V or 5V

Symbol

ILI

Parameter

Notes

1, 2

Min

Max

±20

Units

µA

Test Conditions

Input Leakage Current

VCC = VCCMAX

Vin =VCC or GND

VCC = VCCMAX

Vin =VCC or GND

ILO

Output Leakage Current

±20

µA

VIL

VIH

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

0.8

0.7xVCC VCC+0.5

0.4

VOL

VOH

VLKO

IOL = 3.2mA

IOH = -2.0mA

VCC-0.4

2.0

VCC

VCC Erase/Program

Lock Voltage

Notes:

1. Values are the same for byte and word wide modes for all card densities.

2. Exception: Leakage current on control signals with internal pull up resistors (see block diag) will be < 500µA

when VIN=GND.

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

AC Characteristics

Read Timing Parameters

VCC = 3.3V or 5V

200ns

Min

250ns

Min

SYMBOL

(PCMCIA)

t_C(R)

Parameter

Max

Unit

Read Cycle Time

200

250

t_a(A)

Address Access Time

Card Enable Access Time

Output Enable Access Time

Address Setup Time

200

250

100

t_a(CE)

t_a(OE)

t_su(A)

t_su(CE)

t_h(A)

Card Enable Setup Time

Address Hold Time

t_h(CE)

t_v(A)

Card Enable Hold Time

Output Hold from Address

Change

t_dis(CE)

t_dis(OE)

t_en(CE)

t_en(OE)

t_rec(RST)

Output Disable Time from CE#

100

Output Disable Time from OE#

Output Enable Time from CE#

Output Enable Time from OE#

Power Down recovery to Output

Delay. VCC = 5V

500

Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications.

Read Timing Diagram

tc(R)

th(A)

ta(A)

A[25::0], /REG

tv(A)

ta(CE)

tsu(CE)

/CE1, /CE2

NOTE 1

th(CE)

ta(OE)

tsu(A)

tdis(CE)

/OE

tdis(OE)

ten(OE)

D[15::0]

DATA VALID

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

Write Timing Parameters

VCC = 3.3V or 5V

200ns

Min

250ns

Min

SYMBOL

(PCMCIA)

Parameter

Max

Unit

t_CW

Write Cycle Time

200

120

250

150

t_w(WE)

Write Pulse Width

t_su(A)

Address Setup Time

Address Setup Time for WE#

t_su(A-WEH)

140

180

t_su(CE-WEH) Card Enable Setup Time for WE#

t_su(D-WEH)

t_h(D)

Data Setup Time for WE#

Data Hold Time

t_rec(WE)

t_dis(WE)

t_dis(OE)

Write Recover Time/Address hold

Output Disable Time from WE#

Output Disable Time from OE#

Output Enable Time from WE#

Output Enable Time from OE#

Output Enable Setup from WE#

Output Enable Hold from WE#

Card Enable Setup Time from OE#

Card Enable Hold Time

100

t_en(WE)

t_en(OE)

t_su(OE-WE)

t_h(OE-WE)

t_su(CE)

t_h(CE)

t_rec(WEL)

Reset recovery to WE going low

Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications.

Write Timing Diagram

tc(W)

A[25::0], /REG

tsu(A-WEH)

trec(WE)

th(CE)

tsu(CE-WEH)

tsu(CE)

/CE1, /CE2

NOTE 1

/OE

th(OE-WE)

th(D)

tw(WE)

tsu(A)

/WE

tsu(OE-WE)

NOTE 2

tsu(D-WEH)

D[15::0](Din)

DATA INPUT

tdis(WE)

tdis(OE)

ten(OE)

ten(WE)

NOTE 2

D[15::0]( Dout)

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

Data Write and Erase Performance ^(1,3)

VCC = 5V ± 5%, T_A= 0C to + 70C

SYM

Parameter

Notes Min Typ⁽¹⁾Max Units Test Conditions

t_WHQV1Word/Byte Program time

2,4

6.3

180

0.8

µs

Effective time per Byte

(using Write Buffer)

t_WHQV3Byte Program Time (using

Byte program command)

Block Program Time (using

write to buffer command)

t_WHQV4Block Erase Time

µs

sec Word Program Mode

0.7

sec

µs

t_WHRH

Erase Suspend Latency

Time to Read

Notes:

1. Typical: Nominal voltages and T_A= 25C.

2. Excludes system overhead.

3. Valid for all speed options.

4. To maximize system performance RDY/BSY# signal should be polled.

Waveforms for Reset Operation

Write Operation

WE#

Read Operation

Valid Output

(RST)

rec

WHQV

WHRH

(WEL)

rec

RST

WHRL

tw(RST)

RDY/BSY

SYMBOL

Parameter

Min

Max

Unit

Reset pulse High time

w(RST)

RST Low to reset during

Erase/Program/Lock-bit

Reset Low to output delay

100

500

rec(RST)

rec(WEL)

WHRL

Reset Recovery to WE going Low

WE High to Rdy/Bsy going low

100

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

CIS DATA FOR FLF10 32MB & 64 MB CARDS BASED ON INTEL 28F128J3A

Address

00H

Value

01H

03H

51H

7EH

FEH

FFH

1CH

04H

02H

51H

7EH

FEH

Description

CISTPL_DEVICE

TPL_LINK

Address

48H

Value

05H

F6H

01H

00H

FFH

1AH

06H

01H

00H

40H

Description

TPL_LINK(05H)

02H

4AH

4CH

4EH

50H

TPLMID_MANF: LSB

TPLMID_MANF: MSB

EDI

04H

FLASH = 250ns (device writable)

CARD SIZE: 32MB

64MB

06H

LSB: Number Not Assigned

MSB: Number Not Assigned

END OF TUPLE

CISTPL_CONF

TPL_LINK

08H

0AH

0CH

0EH

10H

12H

END OF DEVICE

CISTPL_DEVICE_OC

TPL_LINK

52H

54H

56H

3 VOLT OPERATION

FLASH = 250ns (device writable)

CARD SIZE:32MB

64MB

58H

TPCC_SZ

5AH

5CH

5EH

TPCC_LAST

TPCC_RADR

14H

16H

END OF DEVICE

CISTPL_JEDEC_C

TPL_LINK

60H

62H

TPCC_RMSK

FFH

18H

00H

FFH

END OF TUPLE

18H

1AH

64H

66H

03H

89H

1BH

03H

CISTPL_CFTABLE_ENTRY

Manufacturer ID -INTEL

TPL_LINK

1CH

1EH

20H

22H

24H

26H

28H

2AH

2CH

2EH

30H

Device ID - 28F0128J3A

END OF DEVICE

CISTPL_DEVICE_A

TPL_LINK

68H

6AH

6CH

6EH

70H

72H

74H

76H

78H

7AH

7CH

TPCE_INDEX

18H

FFH

17H

03H

42H

01H

FFH

1DH

03H

02H

11H

00H

FFH

15H

7FH

04H

01H

37H

50H

30H

33H

TPCE_FS (no selection)

END OF TUPLE

CISTPL_VERS1

EEPROM - 200ns

Device Size = 2KBytes

END OF TUPLE

TPL_LINK

TPLLV1_MAJOR

TPLLV1_MINOR

CISTPL_DEVICE_OA

TPL_LINK

3 VOLT OPERATION

ROM - 250ns

32H

34H

36H

38H

3AH

3CH

3EH

40H

42H

END OF DEVICE

CISTPL_DEVICEGEO

TPL_LINK

7EH

80H

82H

84H

86H

88H

8AH

8CH

8EH

90H

92H

94H

FFH

1EH

07H

02H

12H

01H

32H

46H

4CH

46H

31H

32H

2DH

32H

35H

20H

DGTPL_BUS

DGTPL_EBS

DGTPL_RBS

DGTPL_WBS

DGTPL_PART

FLASH DEVICE

NON-INTERLEAVED

END OF TUPLE

CISTPL_MANFID

44H

46H

FFH

20H

SPACE

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

CIS DATA FOR FLF10 32MB & 64 MB CARDS BASED ON INTEL 28F128J3A (CONT.)

Address

96H

Value

00H

43H

4FH

50H

59H

52H

49H

47H

48H

54H

20H

57H

48H

49H

Description

Address

EAH

ECH

EEH

F0H

Value

41H

54H

49H

4FH

4EH

20H

00H

31H

39H

00H

FFH

Description

END TEXT

98H

9AH

9CH

9EH

A0H

A2H

A4H

A6H

A8H

AAH

ACH

AEH

B0H

F2H

F4H

SPACE

F6H

END TEXT

F8H

FAH

FCH

FEH

100H

102H

104H

SPACE

END TEXT

NULL

END OF LIST

B2H

B4H

54H

45H

B6H

B8H

BAH

BCH

BEH

C0H

C2H

C4H

C6H

C8H

CAH

CCH

CEH

D0H

D2H

D4H

D6H

D8H

DAH

DCH

DEH

E0H

E2H

E4H

E6H

E8H

SPACE

20H

45H

4CH

45H

43H

54H

52H

4FH

4EH

49H

43H

20H

44H

45H

53H

49H

47H

4EH

53H

20H

43H

4FH

52H

50H

4FH

52H

SPACE

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

CIS DATA FOR FLF10 96MB - 192MB CARDS BASED ON INTEL 28F128J3A

Address

00H

Value

01H

03H

51H

FEH

FFH

1CH

04H

02H

51H

7EH

FFH

09H

Description

CISTPL_DEVICE

Address

48H

Value

02H

12H

01H

Description

DGTPL_BUS

02H

TPL_LINK

4AH

DGTPL_EBS

04H

FLASH = 250ns (device writable)

CARD SIZE: 64MB (1^stpage)

END OF DEVICE

4CH

DGTPL_RBS

06H

4EH

DGTPL_WBS

08H

50H

DGTPL_PART

CISTPL_DEVICE_OC

TPL_LINK

0AH

0CH

0EH

10H

52H

FLASH DEVICE

NON-INTERLEAVED

END OF TUPLE

CISTPL_MANFID

TPL_LINK(05H)

TPLMID_MANF: LSB

TPLMID_MANF: MSB

FFH

20H

05H

F6H

01H

3 VOLT OPERATION

FLASH = 250ns (device writable)

CARD SIZE:64MB (1^stpage)

END OF DEVICE

54H

56H

58H

5AH

5CH

12H

EDI

14H

CISTPL_EXTDEVICE

16H

06H

0CH

00H

LSB: Number Not Assigned

MSB: Number Not Assigned

18H

1AH

TPL_LINK

5EH

60H

Mem Paging Info:2bit/COR/64MB

51H

07H

FFH

1AH

1CH

1EH

Flash = 250 ns

62H

64H

END OF TUPLE

CISTPL_CONF

Device Size Extender

01H

02H

06H

01H

00H

40H

03H

FFH

15H

7FH

04H

01H

20H

22H

1x64MB (for 96MB and 128MB)

2x64MB (for 160MB and 192MB)

66H

68H

6AH

6CH

6EH

70H

72H

74H

76H

78H

7AH

TPL_LINK

TPCC_SZ

TPCC_LAST

TPCC_RADR

TPCC_RMSK

END OF TUPLE

CISTPL_VERS1

TPL_LINK

7DH

FEH

FFH

18H

03H

89H

18H

FFH

+32MB (for 96MB and 160MB)

+64MB (for 128MB and 192 MB)

END OF TUPLE

24H

26H

28H

2AH

2CH

2EH

CISTPL_JEDEC_C

TPL_LINK

Manufacturer ID - INTEL

Device ID - 28F0128J3A

TPLLV1_MAJOR

TPLLV1_MINOR

END OF DEVICE

CISTPL_DEVICE_A

TPL_LINK

17H

03H

37H

50H

30H

32H

7CH

7EH

42H

01H

FFH

1DH

03H

02H

11H

FFH

1EH

07H

30H

39H

36H

46H

4CH

46H

31H

32H

2DH

34H

36H

38H

3AH

3CH

3EH

40H

42H

44H

46H

EEPROM - 200ns

Device Size = 2Kbytes

END OF TUPLE

CISTPL_DEVICE_OA

TPL_LINK

80H

82H

84H

86H

88H

8AH

8CH

8EH

90H

92H

3 VOLT OPERATION

ROM - 250ns

END OF DEVICE

CISTPL_DEVICEGEO

TPL_LINK

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

CIS DATA FOR FLF10 96MB - 192MB CARDS BASED ON INTEL 28F128J3A (CONT.)

Address

94H

Value

2DH

32H

35H

20H

00H

43H

4FH

50H

59H

52H

49H

47H

48H

54H

Description

Address

E8H

Value

52H

50H

4FH

52H

41H

54H

49H

4FH

4EH

20H

00H

31H

39H

00H

FFH

Description

96H

EAH

ECH

EEH

F0H

98H

9AH

9CH

9EH

A0H

A2H

A4H

A6H

A8H

AAH

ACH

AEH

SPACE

END TEXT

F2H

F4H

F6H

F8H

FAH

SPACE

FCH

FEH

END TEXT

100H

102H

104H

106H

108H

10AH

B0H

B2H

SPACE

20H

57H

END TEXT

NULL

B4H

B6H

B8H

BAH

BCH

BEH

C0H

C2H

C4H

C6H

C8H

CAH

CCH

CEH

D0H

D2H

D4H

D6H

D8H

DAH

DCH

DEH

E0H

E2H

E4H

E6H

48H

49H

54H

45H

20H

45H

4CH

45H

43H

54H

52H

4FH

4EH

49H

43H

20H

44H

45H

53H

49H

47H

4EH

53H

20H

43H

4FH

END OF LIST

SPACE

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

PRODUCT MARKING

WED7P032FLF1200C15 C995 9915

EDI

Date code

Lot code / trace number

Part number

Company Name

Note:

Some products are currently marked with our pre-merger company name/acronym (EDI). During our

transition period, some products will also be marked with our new company name/acronym (WED).

Starting October 2000 all PCMCIA products will be marked only with the WED prefix.

PART NUMBERING

7P032FLF1200C15

Card access time

150ns

250ns

Temperature range

Commercial 0°C to +70°C

Industrial -40°C to +85°C

Packaging option

Standard, type 1

Card family and version

- See Card Family and Version Info. for details (next page)

Card capacity

032 32MB

PC card

Standard PCMCIA

Ruggedized PCMCIA

Card technology

FLASH

SRAM

November 2000 Rev. 3 - ECO #13392

PC Card Products

PCMCIA Flash Memory Card

FLF10 Series

Ordering Information

7P XXX FLF YY SS T ZZ

where

XXX:

032

064

096

128

160

192

32MB

64MB

96MB

128MB

160MB

192MB

YY:

SS:

based on 28F128J3A

With Attribute Memory

based on 28F128J3A

With Attribute Memory and

Write Protect Switch (optional)

WEDC Logo

Blank Housing Type 1

Blank Housing T 1 (Recessed)

Commercial

ZZ:

200ns

250ns

REVISION HISTORY

Date of Revision

22-Jul-99

Version

-000

-001

-002

-003

Description

Initial Release

Add Pg. 16

31-May-00

01-Aug-00

06-Nov-00

Corrected Timing Errors, Pgs. 9 & 10

Corrected CIS Errors, Pg. 14, and Added Memory

Chip Information, Pg. 6

White Electronic Designs Corporation

One Research Drive, Westborough, MA 01581, USA

tel: (508) 366 5151

fax: (508) 836 4850

www.whiteedc.com

November 2000 Rev. 3 - ECO #13392

PC Card Products

7P064FLF1200C25 [ETC]

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SI9135_11

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SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E