ADSP-21MOD980 [ETC]
ADSP-21MOD980: MultiPort Internet Gateway Processor Data Sheet (Rev. 0. 9/00) ; ADSP - 21MOD980 ：多端口网络网关处理器数据手册（修订版0 9/00 ）\n
| 型号： | ADSP-21MOD980 |
| 厂家： | 
ETC |
| 描述： | ADSP-21MOD980: MultiPort Internet Gateway Processor Data Sheet (Rev. 0. 9/00)
|
| 文件： | 总31页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MultiPort Internet
Gateway Processor
a
ADSP-21mod980
FEATURES
INTEGRATION
PERFORMANCE
ADSP-2100 Family Code-Compatible, with Instruction
Set Extensions
2.00M Bytes of On-Chip SRAM, Configured as 1.125M
Bytes of Program Memory and 0.875M Bytes of Data
Memory
Complete Single-Chip MultiPort Internet Gateway
Processor (No External Memory Required)
Implements Sixteen Modem Channels or Forty Voice
Channels in One Package
Each Processor Can Implement One V.34/V.90 Data/
Fax Modem (Includes Datapump and Controller)
Standard Power Version: 600 MIPS Sustained Perfor-
mance, 13.3 ns Instruction Time @ 2.75 V (Internal)
Low Power Version: 600 MIPS Sustained Performance,
13.3 ns Instruction Time @ 1.80 V (Internal)
Open Architecture Extensible to Voice-over-Network
(VoN) and Other Applications
Dual-Purpose Program Memory, for Both Instruction
and Data Storage
352-Ball PBGA with a 1.9 Square Inch (1225 Square mm)
Footprint
SYSTEM CONFIGURATION
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode-Selectable)
Programmable Multichannel Serial Port Supports
24/32 Channels
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Separate RESET Pins for Each Internal Processor
Low Power Dissipation, 45 mW (Typical) Per Channel
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation
FUNCTIONAL BLOCK DIAGRAM
17
DATA<23:8>,
A<0>
CLKIN
20
20
3
IAD<15:0>,
IDMA CNTL
IAD<15:0>,
IDMA CNTL
PF<0:2>
/MODE A:C
218x
1
218x
2
218x
3
218x
4
218x
5
218x
6
218x
7
218x
8
4
4
SPORT0A
SPORT0B
4
8
SPORT1
EMULATOR
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADSP-21mod980
GENERAL DESCRIPTION
DEVELOPMENT SYSTEM
The ADSP-21mod980 is a multiport Internet gateway processor
optimized for implementation of a complete V.34/56K modem.
All data pump and controller functions can be implemented on a
single device, offering the lowest power consumption and high-
est possible modem port density.
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-21mod980. The System Builder provides a
high-level method for defining the architecture of systems under
development. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment.
The ADSP-21mod980 combines the ADSP-2100 Family base
architecture (three computational units, data address generators,
and a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and
data memory.
A PROM Splitter generates PROM programmer-compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-21mod980 assembly source
code. The source code debugger allows programs to be corrected
in the C environment. The Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.
The ADSP-218x EZ-ICE® Emulator aids in the hardware
debugging of an ADSP-21mod980 system. The EZ-ICE, in
conjunction with the required processor selection hardware, allows
the user to independently debug code on individual modem
processors. The emulator consists of hardware, host computer
resident software, and target board connector. The ADSP-
21mod980 integrates on-chip emulation support with a 14-pin
ICE-Port interface. The ADSP-21mod980 device need not be
removed from the target system when using the EZ-ICE, nor are
any adapters needed. Due to the small footprint of the EZ-ICE
connector, emulation can be supported in final board designs.
The ADSP-21mod980 integrates 2.0M bytes of on-chip memory,
configured as 384K words (24-bit) of program RAM, and 448K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to reduce the average and standby power consumption of
equipment which, in turn, reduces equipment cooling require-
ments. The ADSP-21mod980 is available in a 35 sq-mm., 352-lead
PBGA package.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-21mod980 operates with a 13.3 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The ADSP-21mod980’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple operations
in parallel. In one processor cycle, the ADSP-21mod980 can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
well as the Designing an EZ-ICE Compatible System section of
this data sheet, for the exact specifications of the EZ-ICE target
board connector.
Modem Software
The modem software executes general modem control, command
sets, error correction and data compression, data modulations
(for example, V.90 and V.34), and host interface functions. The
host interface allows system access to modem statistics, such as
call progress, connect speed, retrain count, symbol rate, and
other modulation parameters.
Additional Information
This data sheet provides a general overview of ADSP-21mod980
functionality. For specific information about the modem
processors, refer to the ADSP-2188M Preliminary data sheet.
For additional information on the architecture and instruction
set of the modem processors, refer to the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools data sheet.
The modem data pump and controller software resides in on-
chip SRAM and does not require additional memory. The
ADSP-21mod980 can be dynamically configured by download-
ing software from the host through the 16-bit DMA interface.
This SRAM-based architecture provides a software upgrade path
to other applications, such as Voice-Over-IP (VOIP), and to
future standards. The modem software is available as object code.
EZ-ICE is a registered trademark of Analog Devices, Inc.
–2–
REV. 0
ADSP-21mod980
17
DATA<23:8>,
A<0>
CLKIN
20
20
3
IAD<15:0>,
IDMA CNTL
IAD<15:0>,
IDMA CNTL
PF<0:2>
/MODE A:C
218x
1
218x
2
218x
3
218x
4
218x
5
218x
6
218x
7
218x
8
4
4
SPORT0A
SPORT0B
4
8
SPORT1
EMULATOR
SIGNALS ROUTED TO EACH RESPECTIVE DIE
IDMA CNTL = IAL, IRD, IWR, IACK
INTERRUPTS= IRQE (PF4), IRQL0 (PF5), IRQL1 (PF6), IRQ2 (PF7)
EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK, ELOUT, ERESET
SPORT 0A, SPORT 0B = RFS0, DR0, DT0. SCLK0
SPORT 1 = RFS1, TFS1, DR1, SCLK1
8
8
8
8
BR<8:1>
BG<8:1>
RESET<8:1>
CLKOUT<8:1>
8
EE<8:1>
8
IS<8:1>
TFS0<8:1>
8
8
DT1<8:1>
32
INTERRUPTS <8:1>
NOTE:
SUBTOTAL = 177 SIGNAL BALLS
1) PWD AND PF3/MODE D ARE TIED HIGH
109
44
22
GND
DDINT
V
V
DDEXT
SUBTOTAL = 175 POWER BALLS
TOTAL = 352 BALLS
Figure 1. ADSP-21mod980 Processor Pool
ARCHITECTURE OVERVIEW
Serial Ports
Figure 1 is an overall block diagram of the ADSP-21mod980
MultiPort Internet Gateway Processor. It contains eight inde-
pendent digital signal processors.
The ADSP-21mod980 has a multichannel serial port (SPORT)
connected to each internal digital modem processor for serial
communications.
Every modem processor has:
The following is a brief list of ADSP-21mod980 SPORT fea-
tures. For additional information on the internal Serial Ports,
refer to the ADSP-2100 Family User’s Manual. Each SPORT:
• A DSP core
• 256K bytes of RAM
• Two serial ports
• A DMA port
• Is bidirectional and has a separate, double-buffered transmit
and receive section.
• Can use an external serial clock or generate its own serial
clock internally.
The signals of each modem processor are accessed through the
external pins of the ADSP-21mod980. Some signals are bused
with the signals of the other processors and are accessed through
a single external pin. Other signals remain separate and are
accessed through separate external pins for each processor.
• Has independent framing for the receive and transmit sections.
Sections run in a frameless mode, or with frame synchroniza-
tion signals internally or externally generated. Frame sync
signals are active high or inverted, with either of two pulse-
widths and timings.
• Supports serial data word lengths from 3 to 16 bits and pro-
vides optional A-law and µ-law companding according to
CCITT recommendation G.711.
The arrangement of the eight modem processors in the
ADSP-21mod980 makes one basic configuration possible: a
slave configuration. In this configuration, the data pins of all
eight processors connect to a single bus structure.
• Receive and transmit sections can generate unique interrupts
on completing a data word transfer.
• Can receive and transmit an entire circular buffer of data with
one overhead cycle per data word. An interrupt is generated
after a data buffer transfer.
All eight modem processors have identical functions and equal
status. Each of the four modem processors are connected to a
common DMA bus and each modem processor is configured to
operate in the same mode (see the Slave Mode and the Memory
Mode descriptions in the Memory Architecture section. The
slave mode is considered to be the only mode of operation in the
ADSP-21mod980 modem pool.
A multichannel interface selectively receives and transmits a 24-
or 32-word, time-division multiplexed, serial bitstream.
–3–
REV. 0
ADSP-21mod980
PIN DESCRIPTIONS
Host Pins (Mode C = 1) Modem Processors 1–8
The ADSP-21mod980 is available in a 352-lead PBGA package.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some serial port, programmable flag,
interrupt, and external bus pins have dual, multiplexed func-
tionality. The external bus pins are configured during RESET
only, while serial port pins are software configurable during
program execution. Flag and interrupt functionality is retained
concurrently on multiplexed pins. In cases where pin functional-
ity is reconfigurable, the default state is shown in plain text;
alternate functionality is shown in italics.
#
of
Pins
Input/
Out-
put
Pin
Name(s)
Function
IAD15:0
A0
32
1
I/O
O
IDMA Port Address/Data Bus
Address Pin for External I/O, Program,
Data, or Byte Access
Data I/O Pins for Program, Data Byte
and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configurable
D23:8
16
I/O
IWR
IRD
IAL
IS
2
2
2
8
2
I
I
I
I
Common-Mode Pins
IACK
O
#
of
Input/
Out-
in Mode D; Open Drain
Pin
Name(s)
Pins put
Function
RESET
BR
BG
IRQ2/
PF7
IRQL0/
PF5
IRQL1/
PF6
IRQE/
PF4
8
8
8
8
I
I
O
I
I/O
I
I/O
I
I/O
I
I/O
I
Processor Reset Input
Bus Request Input
Bus Grant Output
INTERRUPTS
The interrupt controller allows each modem processor in the
modem pool to respond individually to 11 possible interrupts
and reset with minimum overhead. The ADSP-21mod980 pro-
vides four dedicated external interrupt input pins, IRQ2, IRQL1,
IRQL0, and IRQE (shared with the PF7:4 pins) for each modem
processor. The ADSP-21mod980 also supports internal inter-
rupts from the timer, the byte DMA port, the serial port, software,
and the power-down control circuit. The interrupt levels are
internally prioritized and individually maskable (except power-
down and reset). The IRQ2, IRQ1, and IRQ0 input pins can be
programmed to be either level- or edge-sensitive. IRQL0 and
IRQL1 are level-sensitive and IRQE is edge-sensitive. The pri-
orities and vector addresses of all interrupts are shown in Table I.
Edge- or Level-Sensitive Interrupt Request1
Programmable I/O Pin
Level-Sensitive Interrupt Request1
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests1
Programmable I/O Pin
Mode Select Input—Checked Only
During RESET
8
8
8
1
Mode C/
PF2
I/O
I
Programmable I/O Pin During Normal
Operation
Mode Select Input—Checked Only
During RESET
Programmable I/O Pin During Normal
Operation
Mode B/
PF1
1
1
Table I. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
I/O
I
Mode A/
PF0
Mode Select Input—Checked Only
During RESET
Source of Interrupt
Address (Hex)
I/O
Programmable I/O Pin During Normal
Operation
Clock Input
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable)
IRQ2
002C
0004
CLKIN
CLKOUT
SPORT
VDD and GND 175
1
8
28
I
O
I/O
I
I/O
Processor Clock Output
Serial Port I/O Pins2
IRQL1
0008
IRQL0
000C
Power and Ground
For Emulation Use
SPORT0 Transmit
SPORT0 Receive
IRQE
0010
0014
0018
EZ-Port
16
NOTES
1Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable
the corresponding interrupts, the modem pool will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices, or
set as a programmable flag.
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
001C
0020
0024
2SPORT configuration determined by the modem pool’s System Control Regis-
ter. Software configurable.
0028 (Lowest Priority)
When the modem pool is reset, interrupt servicing is disabled.
MEMORY INTERFACE PINS
The ADSP-21mod980 modem pool is used in slave mode. In
slave mode, the modem processors operate in host configura-
tion. The operating mode is determined by the state of the
Mode C pin during RESET and cannot be changed while the
modem pool is running. See the Memory Architecture section
for more information.
LOW POWER OPERATION
The ADSP-21mod980 has three low-power modes that signifi-
cantly reduce the power dissipation when the device operates
under standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
–4–
REV. 0
ADSP-21mod980
Power-Down
where n = 16, 32, 64, or 128. This instruction keeps the modem
pool fully functional, but operating at the slower clock rate.
While it is in this state, the modem pool’s other internal clock
signals, such as SCLK, CLKOUT, and timer clock, are reduced
by the same ratio. The default form of the instruction, when no
clock divisor is given, is the standard IDLE instruction.
The ADSP-21mod980 modem pool has a low-power feature
that lets the modem pool enter a very low-power dormant state
through software control. Here is a brief list of power-down fea-
tures. Refer to the ADSP-2100 Family User’s Manual, “System
Interface” chapter, for detailed information about the power-
down feature.
When the IDLE (n) instruction is used, it effectively slows down
the modem pool’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the ADSP-21mod980 will remain
in the idle state for up to a maximum of n modem pool cycles
(n = 16, 32, 64, or 128) before resuming normal operation.
• Quick recovery from power-down. The modem pool begins
executing instructions in as few as 200 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power-
down without affecting the lowest power rating and 200 CLKIN
cycle recovery.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the modem pool’s reduced internal clock
rate. Under these conditions, interrupts must not be generated
at a faster rate than can be serviced, due to the additional time
the modem pool takes to come out of the idle state (a maximum
of n cycles).
• Power-down is initiated by the software power-down force bit.
Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down.
• Context clear/save control allows the modem pool to continue
where it left off or start with a clean context when leaving the
power-down state.
• The RESET pin also can be used to terminate power-down.
SYSTEM CONFIGURATION
Idle
Figure 2 shows the hardware interfaces for a typical multichan-
nel modem configuration with the ADSP-21mod980. Other
system design considerations, such as host processing require-
ments, electrical loading, and overall bus timing, must all be
met. A line interface can be used to connect the multichannel
subscriber or client data stream to the multichannel serial
port of the ADSP-21mod980. The IDMA port of the ADSP-
21mod980 is used to give a host processor full access to the
internal memory of the ADSP-21mod980. This lets the host
dynamically configure the ADSP-21mod980 by loading code
and data into its internal memory. This configuration also lets
the host access server data directly from the ADSP-21mod980’s
internal memory. In this configuration, the Modem Processors
should be put into host memory mode where Mode C = 1,
Mode B = 0, and Mode A = 1.
When the ADSP-21mod980 is in the Idle Mode, the modem pool
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruc-
tion. In Idle mode IDMA, BDMA, and autobuffer cycle steals
still occur.
Slow Idle
The IDLE instruction is enhanced on the ADSP-21mod980 to
let the modem pool’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by
a selectable divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n);
T1/E1
LINE
INTERFACE
SPORT
SPORT
ADSP-21mod980
ADSP-21mod980
ST/CNTL IDMA
ST/CNTL IDMA
STATUS
AND CONTROL
HOST CONTROL
HOST ADDRESS
HOST DATA
STATUS
AND
CONTROL
PAL
HOST
MICRO
IDMA CONTROL
IDMA ADDRESS
IDMA
PAL
Figure 2. Multichannel Modem Configuration
REV. 0
–5–
ADSP-21mod980
CLOCK SIGNALS
The RESET inputs contains some hysteresis; however, if an RC
circuit is used to generate the RESET signals, the use of exter-
nal Schmitt triggers is recommended.
The ADSP-21mod980 is clocked by a TTL-compatible clock
signal that runs at half the instruction rate; a 37.5 MHz input
clock yields a 13.3 ns processor cycle, which is equivalent to
75 MHz. Normally, instructions are executed in a single proces-
sor cycle. All device timing is relative to the internal instruction
clock rate, which is indicated by the CLKOUT signal when
enabled. The clock input signal is connected to the processor’s
CLKIN input.
The reset for each individual modem processor sets the internal
stack pointers to the empty stack condition, masks all interrupts
and clears the MSTAT register. When a RESET is released, if
there is no pending bus request and the modem processor is
configured for booting, the boot-loading sequence is performed.
The first instruction is fetched from on-chip program memory
location 0x0000 once boot loading completes.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal operation.
The only exception is while the processor is in the power-down
state. For additional information, refer to Chapter 9, ADSP-
2100 Family User’s Manual for a detailed explanation of this
power-down feature.
MEMORY ARCHITECTURE
The ADSP-21mod980 provides a variety of memory and
peripheral interface options for Modem Processor 1. The key
functional groups are Program Memory, Data Memory, Byte
Memory, and I/O. Refer to the following figures and tables for
PM and DM memory allocations in the ADSP-21mod980.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate.
The ADSP-21mod980 modem pool operates in one memory
mode: Slave Mode. The following figures and tables describe
the memory of the ADSP-21mod980:
Reset
The RESET signals initiate a reset of each modem processor in
the ADSP-21mod980. The RESET signals must be asserted
during the power-up sequence to assure proper initialization.
RESET during initial power-up must be held long enough to let
the internal clocks stabilize. If RESETs are activated any time
after power up, the clocks continue to run and do not require
stabilization time.
• Figure 3 shows Program Memory.
• Figure 4 shows Data Memory.
• Table II explains the generation of address bits based on the
PMOVLAY values.
• Table III explains the generation of address bits based on the
DMOVLAY values. Access to external memory is not available.
The power-up sequence is defined as the total time required for
the oscillator circuits to stabilize after a valid VDD is applied to
the processors, and for the internal phase-locked loops (PLL) to
lock onto the specific frequency. A minimum of 2000 CLKIN
cycles ensures that the PLLs have locked, but this does not include
the oscillators’ start-up time. During this power-up sequence,
the RESET signals should be held low. On any subsequent
resets, the RESET signals must meet the minimum pulsewidth
specification, tRSP
.
–6–
REV. 0
ADSP-21mod980
PROGRAM MEMORY
PM MODE B = 0
PROGRAM MEMORY
MODE B = 0
ADDR
0x3FFF
8K INTERNAL
PMOVLAY =
0, 4, 5, 6, 7
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
0x2000
0x1FFF
8K
INTERNAL
0x2000 – 0x3FFF
0x0000
0x2000 – 0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 0
0x2000 – 0x3FFF
0x2000 – 0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 4
0x2000 – 0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 5
INTERNAL
MEMORY
ACCESSIBLE WHEN
PMOVLAY = 6
ACCESSIBLE WHEN
PMOVLAY = 7
Figure 3. Program Memory
Table II. PMOVLAY Bits
PMOVLAY
Memory
A13
A12:0
0, 4, 5, 6, 7
Internal
Not Applicable
Not Applicable
DATA MEMORY
DATA MEMORY
ADDR
0x3FFF
32 MEMORY
MAPPED
ALWAYS
REGISTERS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
0x3FE0
0x3FDF
INTERNAL 8160
WORDS
0x2000
0x1FFF
0x0000 – 0x1FFF
8K INTERNAL
DMOVLAY =
0, 4, 5, 6, 7, 8
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 0
0x0000 – 0x1FFF
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 4
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 5
ACCESSIBLE WHEN
DMOVLAY = 6
INTERNAL
MEMORY
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 7
ACCESSIBLE WHEN
DMOVLAY = 8
Figure 4. Data Memory Map
Table III. DMOVLAY Bits
DMOVLAY
Memory
A13
A12:0
Not Applicable
0, 4, 5, 6, 7, 8 Internal
Not Applicable
REV. 0
–7–
ADSP-21mod980
Memory-Mapped Registers (New to the ADSP-21mod980)
The ADSP-21mod980 has three memory-mapped registers that
differ from other ADSP-21xx Family DSPs. The slight modifi-
cations to these registers (Wait State Control, Programmable
Flag and Composite Select Control, and System Control) provide
the ADSP-21mod980’s wait state and BMS control features.
processor’s memory-mapped control registers. A typical IDMA
transfer process is described as follows:
1. Host starts IDMA transfer.
2. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the processor’s IDMA control registers.
Slave Mode
If IAD [15] = 1, the value of IAD [7:07] represents the IDMA
overlay: IAD[14:8] must be set to 0.
This section describes the Slave Mode memory configuration of
the Modem Processors.
If IAD [15] = 0, the value of IAD [13:0] represents the starting
address of internal memory to be accessed and IAD [14] reflects
PM or DM for access.
Internal Memory DMA Port (IDMA Port)
The IDMA Port provides an efficient way for a host system and
the ADSP-21mod980 to communicate. The port is used to
access the on-chip program memory and data memory of each
modem processor with only one processor cycle per word over-
head. The IDMA port cannot be used, however, to write to the
3. Host uses IS and IRD (or IWR) to read (or write) processor
internal memory (PM or DM).
4. Host ends IDMA transfer.
15
1
14
1
13
1
12
1
11
1
10
0
9
1
8
1
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM(0x3FFE)
DWAIT
IOWAIT3
IOWAIT2
IOWAIT1
IOWAIT0
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING FROM 0 TO 15)
Figure 5. Wait State Control Register
15
1
14
1
13
1
12
1
11
1
10
0
9
1
8
1
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM(0x3FE6)
BMWAIT
CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
PFTYPE
0 = INPUT
1 = OUTPUT
(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)
Figure 6. Programmable Flag and Composite Select
Control Register
NOTE: Since they are multiplexed within the ADSP-21mod980, PF[2:0] should be configured as an output for only one processor at a
time. Bit [3] of DM (0x3F36) must also be 0.
15
0
14
0
13
0
12
0
11
0
10
1
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
1
1
0
1
DM(0x3FFF)
RESERVED
SET TO 0
RESERVED
ALWAYS
SET TO 0
PWAIT
PROGRAM MEMORY
WAIT STATES
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
DISABLE BMS
0 = ENABLE BMS
1 = DISABLE BMS, EXCEPT WHEN
MEMORY STROBES ARE
THREE-STATED
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SPORT1
Figure 7. System Control Register
Table IV. ADSP-21mod980 Mode of Operation
MODE C MODE B MODE A Booting Method
1
0
1
IDMA feature is used to load internal memory as desired. Program execution is held off until
internal program memory location 0x0000 is written to. Chip is configured in Slave Mode.1
IACK requires external pull-down.1
1Considered standard operating settings. These configurations simplify your design and improve memory management. IDMA timing details and the correct
usage of IACK are described in the ADSP-2100 Family User’s Manual; refer to pages 11-18 thru 11-19.
–8–
REV. 0
ADSP-21mod980
and IWR respectively) signals the ADSP-21mod980 that a par-
ticular transaction is required. In either case, there is a one-
processor-cycle delay for synchronization. The memory access
consumes one additional processor cycle.
The IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to, while the
ADSP-21mod980 is operating at full speed.
Once an access has occurred, the latched address is automati-
cally incremented, and another access can occur.
The processor memory address is latched and then automati-
cally incremented after each IDMA transaction. An external
device can, therefore, access a block of sequentially addressed
memory by specifying only the starting address of the block.
This increases throughput as the address does not have to be
sent for each memory access.
Through the IDMAA register, the processor can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs
the ADSP-21mod980 to write the address onto the IAD [14:0]
bus into the IDMA Control Register. If IAD [15] is set to 0,
IDMA latches the address. If IAD [15] is set to 1, IDMA latches
OVLAY memory. The IDMAA register is memory mapped at
address DM (0x3FE0). Note that the latched address (IDMAA)
or overlay register cannot be read back by the host. The IDMA
OVERLAY register is memory mapped at address DM(0x3FE7).
See Figure 8 for more information on IDMA memory map-
ping. When Bit 14 in 0x3FE7 is set to 1, timing in Figure 25
applies for short reads. When Bit 14 in 0x3FE7 is set to zero
short reads, use the timing shown in Figure 26.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.
Once the address is stored, data can then be either read from, or
written to, the ADSP-21mod980’s on-chip memory. Asserting
the select line (IS) and the appropriate read or write line (IRD
15
0
14
0
13
0
12
0
11
0
10
1
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
1
1
0
1
DM(0x3FE7)
RESERVED
SET TO 0
ID DMOVLAY
ID PMOVLAY
SHORT READ ONLY
ENABLE
0 = DISABLE
1 = ENABLE
RESERVED
SET TO 0
a. IDMA Overlay
15
14
U
13
U
12
U
11
U
10
U
9
8
7
6
5
4
3
2
1
0
DM(0x3FE0)
U
U
U
U
U
U
U
U
U
U
IDMAA
ADDRESS
IDMAD
DESTINATION MEMORY TYPE:
0 = PM
1 = DM
b. IDMA Control (U = Undefined at Reset)
Figure 8. IDMA Control/OVLAY Registers
–9–
REV. 0
ADSP-21mod980
DMA
PROGRAM MEMORY
OVLAY
DMA
DATA MEMORY
OVLAY
ALWAYS
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
0x2000 – 0x3FFF
0x0000 – 0x1FFF
0x2000 – 0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 0
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 0
0x2000 – 0x3FFF
0x0000 – 0x1FFF
0x2000 – 0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 4
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 4
0x2000 – 0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 5
0x0000 – 0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 5
ACCESSIBLE WHEN
PMOVLAY = 6
ACCESSIBLE WHEN
DMOVLAY = 6
0x0000 – 0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 7
ACCESSIBLE WHEN
DMOVLAY = 7
ACCESSIBLE WHEN
DMOVLAY = 8
Figure 9. Direct Memory Access—PM and DM Memory Maps
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-21mod980 has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE.
These features allow in-circuit emulation, without replacing the
target system processor, by using only a 14-pin connection from
the target system to the EZ-ICE. Target systems must have a
14-pin connector to accept the EZ-ICE’s in-circuit probe, a
14-pin plug.
IDMA Port Booting
The ADSP-21mod980 boots programs through its Internal
DMA port. When Mode C = 1, Mode B = 0, and Mode A = 1,
the ADSP-21mod980 boots from the IDMA port. IDMA feature
can load as much on-chip memory as desired. Program execu-
tion is held off until on-chip program memory location 0 is
written to.
The EZ-ICE can emulate only one modem processor at a time.
You must include hardware to select which processor in the
ADSP-21mod980 you want to emulate. Figure 10 is a functional
representation of the modem processor selection hardware. One
ICE-Port connector can be used with two ADSP-21mod980
processors without using additional buffers.
Flag I/O Pins
Each modem processor has eight general-purpose program-
mable input/output flag pins. They are controlled by two
memory-mapped registers. The PFTYPE register determines
the direction, 1 = output and 0 = input. The PFDATA register
is used to read and write the values on the pins. Data being read
from a pin configured as an input is synchronized to the ADSP-
21mod980’s clock. Bits that are programmed as outputs will
read the value being output. The PF pins default to input dur-
ing reset.
Issuing the “chip reset” command during emulation causes the
modem processor to perform a full chip reset, including a reset
of its memory mode. Therefore, it is vital that the mode pins are
set correctly prior to issuing a chip reset command from the
emulator user interface. As the mode pins share functionality
with PF0:2 on the ADSP-21mod980, it may be necessary to
reset the target hardware separately to ensure the proper mode
selection state on emulator chip reset. See the ADSP-2100 Fam-
ily EZ-Tools data sheet for complete information on ICE products.
Note: Pins PF0, PF1, and PF2 are also used for device con-
figuration during reset. Since they are multiplexed within the
ADSP-21mod980, PF[0:2] should be configured as an output
for only one processor at a time.
–10–
REV. 0
ADSP-21mod980
ADSP-21
mod980
ELOUT
EBR
EBG
EINT
ELIN
ECLK
EMS
ERESET
GND
BG
BG0
1
3
5
7
2
4
BR0
RESET0
EE0
EBG
EBR
BR
BG1
BR1
RESET1
EE1
EINT
ELIN
ECLK
6
KEY
8
BG2
BR2
RESET2
EE2
ELOUT
EE
9
10
12
14
EMS
BG3
BR3
RESET3
EE3
11
13
RESET
ERESET
BG4
BR4
RESET4
EE4
BG5
BR5
RESET5
EE5
BG6
BR6
RESET6
EE6
BG7
BR7
RESET7
EE7
Figure 10. Selecting a Modem Processor in the ADSP-21mod980
The ICE-Port interface consists of the following ADSP-21mod980
pins:
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-21mod980 in the target system. This causes
the processor to use its ERESET, EBR, and EBG pins instead
of the RESET, BR, and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in a system.
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
EE
The EZ-ICE connects to the target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
These ADSP-21mod980 pins must be connected only to the
EZ-ICE connector in the target system. These pins have no
function except during emulation, and do not require pull-up or
pull-down resistors. The traces for these signals between the
ADSP-21mod980 and the connector must be kept as short as
possible, no longer that 3 inches.
The following pins are also used by the EZ-ICE:
BR RESET
BG GND
REV. 0
–11–
ADSP-21mod980
Target Board Connector for EZ-ICE Probe
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—Pin 7 must be removed from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
The EZ-ICE connector (a standard pin strip header) is shown
in Figure 10. This connector must be added to the target board
design in order to use the EZ-ICE. Be sure to allow enough
room in the system to fit the EZ-ICE probe onto the 14-pin
connector.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
1
2
GND
EBG
BG
Target Memory Interface
For a target system to be compatible with the EZ-ICE emulator,
it must comply with the memory interface guidelines listed below.
3
4
BR
5
6
EBR
EINT
ELIN
ECLK
EMS
ERESET
Target System Interface Signals
7
8
When the EZ-ICE board is installed, the performance on some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
KEY (NO PIN)
ELOUT
EE
9
10
12
14
11
13
• EZ-ICE emulation introduces an 8 ns propagation delay
between target circuitry and the processor on the
RESET signal.
RESET
• EZ-ICE emulation introduces an 8 ns propagation delay
between target circuitry and the processor on the BR signal.
TOP VIEW
Figure 11. Target Board Connector for EZ-ICE
• EZ-ICE emulation ignores RESET and BR when single-
stepping.
• EZ-ICE emulation ignores RESET and BR when in Emulator
Space (processor halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
processor’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s processor.
–12–
REV. 0
ADSP-21mod980
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
Min
Max
Unit
VDDEXT
VDDINT
TAMB
2.97
2.61
0
3.63
2.89
70
V
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Typ
Max
Unit
VIH, Hi-Level Input Voltage1, 2
VIH, Hi-Level CLKIN Voltage
VIL, Lo-Level Input Voltage1, 3
@ VDDINT = max
@ VDDINT = max
@ VDDINT = min
@ VDDEXT = min,
IOH = –0.5 mA
1.5
2.0
V
V
V
V
0.7
V
OH, Hi-Level Output Voltage1, 4 , 5
2.0
2.4
@ VDDEXT = 3.0 V,
V
V
I
OH = –0.5 mA
@ VDDEXT = min,
DDEXT – 0.3
OH = –100 µA6
@ VDDEXT = min,
OL = 2 mA
VDDEXT – 0.3
V
I
VOL, Lo-Level Output Voltage1, 4, 5
IIH, Hi-Level Input Current3
IIL, Lo-Level Input Current3
0.4
10
10
10
10
V
I
@ VDDINT = max,
VIN = 3.6 V
@ VDDINT = max,
VIN = 0 V
µA
µA
µA
µA
mA
mA
I
OZH, Three-State Leakage Current7
@ VDDEXT = max,
V
IN = 3.6 V8
IOZL, Three-State Leakage Current7
IDD, Supply Current (Idle)9
@ VDDEXT = max,
V
IN = 0 V8
@ VDDINT = 2.75,
tCK = 13.3 ns
80
I
DD, Supply Current (Dynamic)10
@ VDDINT = 2.75,
373
t
CK = 13.3 ns11,
TAMB = 25°C
I
DD, Supply Current (Power-Down)12
Lowest Power Mode
@ VIN = 2.5 V,
fIN = 1.0 MHz,
200
mA
pF
CI, Input Pin Capacitance1, 3, 6, 9
64
64
T
AMB = 25°C
CO, Output Pin Capacitance1, 6, 7, 12, 10
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = 25°C
pF
NOTES
1Bidirectional pins: RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD [15:0], PF[2:0], PF[7:4].
2Input only pins: RESET, BR, DR0, DR1, IS, IAL, IRD, IWR.
3Input only pins: CLKIN, RESET, BR, DR0, DR1.
4Output pins: BG, A0, DT0, DT1, CLKOUT, IACK.
5Although specified for TTL outputs, all ADSP-21mod980 outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no dc loads.
6Guaranteed but not tested.
7Three-statable pins: DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, IAD[15:0], RFS1.
80 V son BR.
9Applies to PBGA package type.
10Output pin capacitance is the capacitive load for any three-stated output pin.
11
V
= 0 V and 3 V. For typical supply current figures refer to Power Dissipation section.
IN
12See the ADSP-2100 Family User’s Manual for details.
Specifications subject to change without notice.
REV. 0
–13–
ADSP-21mod980
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Internal Supply Voltage (VDDINT
)
)
–0.3 V
–0.3 V
–0.5 V
–0.5 V
+3.0 V
+4.6 V
+4.6 V
VDDEXT + 0.5 V
External Supply Voltage (VDDEXT
Input Voltage1
Output Voltage Swing2
Storage Temperature Range
–65 °C +150 °C
NOTES
1Applies to bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1,
A1–A13, PF0–PF7) and input only pins (CLKIN, RESET, BR, DR0, DR1).
2Applies to Output pins (BG, PWDACK, A0, DT0, DT1, CLKOUT).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21mod980 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
MEMORY TIMING SPECIFICATIONS
The table below shows common memory device specifications
and the corresponding ADSP-21mod980 timing parameter.
TIMING PARAMETERS
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, the user
cannot meaningfully add up parameters to derive longer times.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
tCK is defined as 0.5 tCKI. The ADSP-21mod980 uses an input
clock with a frequency equal to half the instruction rate: a
37.5 MHz input clock (which is equivalent to 26.6 ns) yields a
13.3 ns processor cycle (equivalent to 75 MHz). tCK values
within the range of 0.5 tCKI period should be substituted for all
relevant timing parameters to obtain the specification value.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. The user has no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics tell
what the processor will do in a given circumstance. Switching
characteristics can also be used to ensure that any timing
requirement of a device connected to the processor (such as
memory) is satisfied.
Example: tCKH = 0.5 tCK – 5 ns = 0.5 (13.3 ns) – 5 ns = 1.67 ns
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
TAMB
TJ
PD
θJA
=
=
=
=
TCASE – (PD × θJA)
Junction Temperature in °C
Power Dissipation in W
Thermal Resistance (Junction-to-Ambient)
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
Package
JA
Airflow
PBGA
28.2°C/W
0 lfm
–14–
REV. 0
ADSP-21mod980
POWER DISSIPATION
CAPACITIVE LOADING
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
Figures 13 and 14 show the capacitive loading characteristics of
the ADSP-21mod980.
C × VDD2 × f
30
T
V
= 85؇C
C = load capacitance, f = output switching frequency.
A
= 0V TO 2.0V
DD
25
20
15
10
5
Example
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:
Assumptions:
• Data memory is accessed every fourth cycle with 50% of the
address pins switching.
• Data memory writes occur every fourth cycle with 50% of the
data pins switching.
• Each address and data pin has a 64 pF total load at the pin.
• The application operates at VDD = 3.3 V and tCK = 13.3 ns.
Total Power Dissipation = PINT + (C × VDD2 × f)
0
50
0
100
150
– pF
200
250
300
C
L
P
INT = internal power dissipation from Power vs. Frequency
Figure 13. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
graph (Figure 12).
(C × VDD2 × f) is calculated for each output:
18
16
14
12
10
Table V. Example of Calculating Power Dissipation
# of
Pins
؋
C 2
؋
VDD ؋
f 8
6
4
Address, DMS
Data Output, WR 9
8
× 64 pF × 3.32 V 18.8 MHz = 104.9 mW
× 64 pF × 3.32 V 18.8 MHz = 117.9 mW
222.8 m W
2
Total power dissipation for this example is PINT + 222.8 mW.
NOMINAL
–2
–4
–6
410
400mW
390
0
50
100
150
200
250
C
– pF
373mW
L
370
Figure 14. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
350
= 2.9V
340mW
DD
V
330
= 2.75V
D
D
V
310
= 2.6V
D
D
V
290
270
250
278mW
256mW
240mW
230
45
55
60
65
70
75
80
50
1/t – MHz
CK
VALID FOR ALL TEMPERATURE GRADES
1. POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2. TYPICAL POWER DISSIPATION AT 25؇C
3.
I
MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING
DD
FROM INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE
MULTIFUNCTION (TYPES 1,4,5,12,13,14), 30% ARE TYPE 2 AND
TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
Figure 12. Power vs. Frequency
REV. 0
–15–
ADSP-21mod980
TEST CONDITIONS
Output Disable Time
REFERENCE
SIGNAL
tMEASURED
tDIS
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high-impedance state. The out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY
as shown in Figure 16. The time is the interval from when a
reference signal reaches a high or low voltage level to when
the output voltages have changed by 0.5 V from the measured
output high or low voltage.
tENA
V
V
OH
(MEASURED)
OH
(MEASURED)
,
V
V
(MEASURED) –0.5V
2.0V
1.0V
OH
OUTPUT
(MEASURED) +0.5V
OL
V
V
OL
OL
(MEASURED)
tDECAY
(MEASURED)
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
The decay time, tDECAY, is dependent on the capacitive load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 16. Output Enable/Disable
CL ×0.5V
tDECAY
=
iL
I
OL
from which
t
DIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are
disabled, the measurement value is that of the last pin to
stop driving.
TO
OUTPUT
PIN
1.5V
50pF
1.5V
1.5V
I
OH
OUTPUT, INPUT
Figure 17. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
Figure 15. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, see Figure
16. If multiple pins (such as the data bus) are enabled, the mea-
surement value is that of the first pin to start driving.
–16–
REV. 0
ADSP-21mod980
TIMING PARAMETERS
75 MHz
Parameter
Min
Max
Unit
Clock Signals and Reset
Timing Requirements:
tCKI
CLKIN Period
26.6
8
8
80
ns
ns
ns
tCKIL
tCKIH
CLKIN Width Low
CLKIN Width High
Switching Characteristics:
tCKL
CLKOUT Width Low
0.5 tCK – 2
0.5 tCK – 2
0
ns
ns
ns
tCKH
tCKOH
CLKOUT Width High
CLKIN High to CLKOUT High
13
Control Signals
Timing Requirements:
1
tRSP
tMS
tMH
RESET Width Low
Mode Setup before RESET High
Mode Setup after RESET High
5 tCK
2
5
ns
ns
ns
NOTE
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF (2:0)*
tMH
tMS
RESET
*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 18. Clock Signals
REV. 0
–17–
ADSP-21mod980
Parameter
Min
Max
Unit
Interrupts and Flags
Timing Requirements:
tIFS
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
0.25 tCK + 10
0.25 tCK
ns
ns
tIFH
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
tFOD
Flag Output Delay from CLKOUT Low5
0.25 tCK – 5
ns
ns
0.5 tCK + 4
NOTES
1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the
following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further information
on interrupt servicing.)
2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4PFx = PF0, PF1, PF2, PF4, PF5, PF6, PF7.
5Flag outputs = PFx, Flag_out4.
CLKOUT
tIFH
IRQx
FI
PFx
tIFS
Figure 19. Interrupts and Flags
–18–
REV. 0
ADSP-21mod980
TIMING PARAMETERS
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
tSCK
tSCS
tSCH
tSCP
SCLK Period
26.67
4
7
12
ns
ns
ns
ns
DR/TFS/RFS Setup before SCLK Low
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
0.25 tCK
0
0.25 tCK + 6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE
tSCDV
tRH
12
12
0
tRD
tSCDH
tTDE
tTDV
tSCDD
tRDV
0
0
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
12
12
12
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCP
tSCS tSCH
DR
TFS
RFS
IN
IN
tRD
tRH
RFS
TFS
OUT
tSCDD
OUT
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
OUT
ALTERNATE
FRAME MODE
tRDV
RFS
OUT
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
tTDE
tTDV
TFS
IN
ALTERNATE
FRAME MODE
tRDV
RFS
IN
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 20. Serial Ports
REV. 0
–19–
ADSP-21mod980
Parameter
Min
Max
Unit
IDMA Address Latch
Timing Requirements:
tIALP
tIASU
tIAH
Duration of Address Latch1, 2
10
5
2
0
3
ns
ns
ns
ns
ns
ns
IAD15–0 Address Setup before Address Latch End2
IAD15–0 Address Hold after Address Latch End2
IACK Low before Start of Address Latch2, 3
tIKA
tIALS
tIALD
Start of Write or Read after Address Latch End1, 2
Address Latch Start after Address Latch End1, 2
2
NOTES
1Start of Address Latch = IS Low and IAL High.
2End of Address Latch = IS High or IAL Low.
3Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
tIALD
IAL
tIALP
tIALP
IS
IAD15–0
tIASU
tIASU
tIAH
tIAH
tIALS
IRD OR
IWD
Figure 21. IDMA Address Latch
–20–
REV. 0
ADSP-21mod980
TIMING PARAMETERS
Parameter
Min
Max
Unit
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW
tIWP
tIDSU
tIDH
IACK Low before Start of Write1
0
10
3
ns
ns
ns
ns
Duration of Write1, 2
IAD15–0 Data Setup before End of Write2, 3, 4
IAD15–0 Data Hold after End of Write2, 3, 4
2
Switching Characteristic:
tIKHW
Start of Write to IACK High
10
ns
NOTES
1Start of Write = IS Low and IWR Low.
2End of Write = IS High or IWR High.
3If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH
.
4If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH
.
tIKW
IACK
tIKHW
IS
IWR
tIWP
tIDH
tIDSU
DATA
IAD15–0
Figure 22. IDMA Write, Short Write Cycle
REV. 0
–21–
ADSP-21mod980
Parameter
Min
Max
Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW
tIKSU
tIKH
IACK Low before Start of Write1
0
ns
ns
ns
IAD15–0 Data Setup before End of Write2, 3, 4
IAD15–0 Data Hold after End of Write2, 3, 4
0.5 tCK + 5
0
Switching Characteristics:
tIKLW
Start of Write to IACK Low4
tIKHW Start of Write to IACK High
1.5 tCK
ns
ns
10
NOTES
1Start of Write = IS Low and IWR Low.
2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH
.
3If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH
.
4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKH
tIKSU
DATA
IAD15–0
Figure 23. IDMA Write, Long Write Cycle
–22–
REV. 0
ADSP-21mod980
TIMING PARAMETERS
Parameter
Min
Max
Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR
tIRK
IACK Low before Start of Read1
End of Read after IACK Low2
0
2
ns
ns
Switching Characteristics:
tIKHR
tIKDS
tIKDH
tIKDD
tIRDE
tIRDV
tIRDH1
tIRDH2
IACK High after Start of Read1
10
ns
ns
ns
ns
ns
ns
ns
ns
IAD15–0 Data Setup before IACK Low
0.5 tCK – 2
0
IAD15–0 Data Hold after End of Read2
IAD15–0 Data Disabled after End of Read2
10
10
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
IAD15–0 Previous Data Hold after Start of Read (PM2)4
0
2 tCK – 5
tCK – 5
NOTES
1Start of Read = IS Low and IRD Low.
2End of Read = IS High or IRD High.
3DM read or first half of PM read.
4Second half of PM read.
IACK
IS
tIKHR
tIKR
tIRK
IRD
tIKDS
tIKDH
tIRDE
PREVIOUS
DATA
READ
DATA
IAD15–0
tIRDV
tIKDD
tIRDH
Figure 24. IDMA Read, Long Read Cycle
REV. 0
–23–
ADSP-21mod980
Parameter
Min
Max
Unit
IDMA Read, Short Read Cycle1
Timing Requirements:
tIKR
tIRP
IACK Low before Start of Read2
Duration of Read
0
10
ns
ns
Switching Characteristics:
tIKHR
tIKDH
tIKDD
tIRDE
tIRDV
tIRDH1
tIRDH1
IACK High after Start of Read2
10
10
10
ns
ns
ns
ns
ns
ns
ns
IAD15–0 Data Hold after End of Read3
0
0
IAD15–0 Data Disabled after End of Read3
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)4
IAD15–0 Previous Data Hold after Start of Read (PM2)5
2tCK –5
tCK –5
NOTES
1Timing applies to ADSP-21mod980 when Short Read only is disabled. See next page.
2Start of Read = IS Low and IRD Low.
3End of Read = IS High or IRD High.
4DM read or first half of PM read.
5Second half of PM read.
IACK
tIKHR
tIKR
IS
IRD
tIKDH
tIRDE
PREVIOUS
DATA
NEW READ DATA
IAD15–0
tIRDV
tIKDD
tIRDH
Figure 25. IDMA Read, Short Read Cycle
–24–
REV. 0
ADSP-21mod980
TIMING PARAMETERS
Parameter
Min
Max
Unit
IDMA Read, Short Read Cycle in Short Read Only Mode1
Timing Requirements:
tIKR
tIRP
IACK Low before Start of Read2
0
10
ns
ns
Duration of Read1
Switching Characteristics:
tIKHR
tIKDH
tIKDD
tIRDE
tIRDV
IACK High after Start of Read2
10
10
10
ns
ns
ns
ns
ns
IAD15–0 Data Hold after End of Read3
0
0
IAD15–0 Data Disabled after End of Read3
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
NOTES
1Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the
register or by an external host writing to the register. Disabled by default.
2Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3End of Read = IS High or IRD High.
IACK
tIKHR
tIKR
IS
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
DATA
IAD15–0
tIKDD
tIRDV
Figure 26. IDMA Read, Short Read Cycle
REV. 0
–25–
ADSP-21mod980
Pinout—Top View Left
1
2
3
4
5
6
7
8
9
10
11
12
DT1_2 VDDEXT
GND BR_2
13
A
B
C
D
E
F
GND
A0
VDDINT
VDDINT
GND
VDDINT
IAD0_A
IRD_A
GND
GND
GND
GND
GND
PF0
PF1
PF2
IS_1
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
IAL_A
IWR_A
VDDEXT
VDDEXT
VDDEXT
VDDEXT
CLKOUT_2 GND
IAD1_A
IAD4_A
IAD14_A
DR0A
GND
PF6_2
PF4_2
PF5_2
GND
GND
GND
IAD2_A
IAD5_A
IAD13_A
GND
TFS0_2 EE_2
PF7_2 RESET_2
IAD3_A
CLKIN
BG_1
IAD15_A
GND
GND
G
H
J
CLKOUT_1
GND
GND
GND
BR_1
GND
GND
GND
RESET_1
VDDEXT
VDDEXT
PF4_1
TFS0_1
VDDEXT
VDDEXT
PF5_1
GND
RFS0A
VDDEXT
VDDEXT
PF6_1
GND
PF7_1
VDDEXT
VDDEXT
EE_1
K
L
M
N
P
R
T
U
V
W
Y
GND
GND
SCLK0A
VDDINT
PF4_6
DT0A
VDDINT
PF6_6
GND
DT1_1
VDDINT
GND
CLKOUT_6
BG_6
IACK_A
BR_6
GND
DT1_6
IAD11_A
GND
PF5_6
PF7_6
GND
IAD6_A
GND
GND
TFS0_6
EE_6
IAD9_A
IS_4
IAD7_A
IAD12_A
VDDINT
GND
AA RESET_6
AB VDDINT
AC CLKOUT_4
AD PF6_4
AE GND
AF GND
1
IAD10_A
VDDINT
PF4_4
GND
VDDINT
PF5_4
GND
BG_4
GND
IS_6
GND
DR1
GND
GND
GND
GND
8
BR_4
PF6_7
EE_4
PF7_7
9
GND
RESET_7 GND
EE_7
DT1_7
VDDINT
VDDINT
13
GND
GND
IAD8_A
CLKOUT_7 GND
GND
GND
GND
12
GND
PF7_4
TFS1
GND
TFS0_4 RFS1
GND
GND
10
PF5_7
TFS0_7
11
DT1_4
2
GND
SCLK1 RESET_4 PF4_7
3
4
5
6
7
–26–
REV. 0
ADSP-21mod980
Pinout—Top View Right
14
IS_2
15
16
17
18
19
20
21
22
23
24
25
26
VDDEXT
VDDEXT
VDDEXT
VDDEXT
GND
GND
GND
GND
VDDEXT
VDDEXT
VDDEXT
VDDEXT
PF7_3
PF6_3
PF5_3
PF4_3
GND
GND
GND
GND
GND
TFS0_3
GND
GND
D23
D22
D21
D18
GND
A
VDDEXT
VDDEXT
BG_2
VDDEXT
RESET_3
VDDEXT
D19
D17
GND
D15
D16
B
CLKOUT_3 GND
D20
GND
D13
D14
C
GND
DT1_3
GND
EMS
D12
D11
D
D10
D09
ERESET
EBG
E
D08
IS_3
BG_3
BR_3
GND
ELIN
VDDEXT
F
EE_3
PF5_5
GND
ELOUT
VDDEXT
EBR
G
GND
ECLK
VDDEXT
IAD11_B
IAD8_B
TFS0_5
VDDINT
GND
RESET_5
GND
IAD1_B
GND
IWR_B
GND
VDDINT
GND
GND
GND
GND
23
GND
H
EINT
VDDEXT
IAD10_B
IAD6_B
IAD7_B
VDDINT
PF6_5
EE_5
J
K
CLKOUT_5 PF4_5
L
IAD9_B
BR_5
IAD12_B
M
N
PF7_5
VDDINT
BG_5
DT1_5
GND
VDDINT
GND
P
R
GND
T
GND
GND
U
IAD2_B
IAD3_B
IRD_B
GND
IS_5
IAD0_B
IAD5_B
IS_8
V
IAD4_B
IAL_B
GND
W
Y
GND
AA
AB
AC
AD
AE
AF
VDDINT
IAD14_B
GND
VDDINT
IAD15_B
BG_8
GND
VDDINT
IACK_B
IAD13_B
BR_8
VDDEXT
VDDEXT
VDDEXT
VDDEXT
14
VDDEXT
BG_7
BR_7
IS-7
GND
GND
GND
GND
17
PF6_8
PF4_8
PF5_8
PF7_8
18
VDDEXT
VDDEXT
VDDEXT
VDDEXT
19
TFS0_8
RFS0B
DT1_8
DT0B
20
GND
GND
GND
GND
21
RESET_8
GND
EE_8
DR0B
22
GND
GND
SCLK0B
VDDINT
24
CLKOUT_8 GND
15 16
VDDINT
25
GND
26
REV. 0
–27–
ADSP-21mod980
The ADSP-21mod980 package pinout is shown in the table below.
352-Ball PBGA Package Pinout
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
A0
A2
D11
D26
EE_1
M4
GND
AC12
GND
AF1
BG_1
F3
D12
D25
EE_2
C13
GND
AC17
GND
AF4
BG_2
BG_3
BG_4
BG_5
BG_6
BG_7
BG_8
BR_1
D14
F25
AC5
R25
R4
D13
D24
C26
C25
B26
B24
A25
B23
C23
A24
A23
A22
E1
EE_3
EE_4
EE_5
EE_6
EE_7
EE_8
EINT
ELIN
ELOUT
EMS
G23
AE9
T26
Y2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AC21
AC23
AD2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AF8
AF10
AF12
AF16
AF17
AF21
AF23
AF26
B2
D14
D15
D16
AD3
D17
AC13
AE22
J26
AD4
AD15
AD25
G4
D18
AD5
D19
AD7
D20
J25
AD8
BR_2
B13
G25
AC9
N24
U4
D21
J24
AD11
AD12
AD16
AD17
AD21
AD22
AD23
AD24
AE1
BR_3
D22
E23
E26
A1
B5
BR_4
D23
ERESET
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B11
B12
B16
B19
B21
B25
C3
BR_5
DR0A
DR0B
DR1
BR_6
AF22
AE7
P2
A5
BR_7
AE15
AE26
E3
A11
A16
A19
A20
A21
A26
AA23
AA24
AA25
AA26
AC4
AC6
AC8
AC10
BR_8
DT0A
DT0B
DT1_1
DT1_2
DT1_3
DT1_4
DT1_5
DT1_6
DT1_7
DT1_8
EBG
CLKIN
CLKOUT1
AF20
P3
G1
CLKOUT_2 A10
CLKOUT_3 C20
CLKOUT_4 AC1
CLKOUT_5 L24
CLKOUT_6 P4
CLKOUT_7 AD10
CLKOUT_8 AF15
A12
D21
AF2
T25
U3
AE2
C5
AE4
C11
C16
C19
C21
C24
D4
AE8
AE10
AE12
AE16
AE17
AE21
AE23
AE25
AD13
AE20
F26
G26
J23
D08
D09
D10
F23
E25
E24
D5
EBR
D11
D16
ECLK
–28–
REV. 0
ADSP-21mod980
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D19
D20
D23
F1
GND
W23
T4
IAD8_B
IAD9_A
IAD9_B
IAL_A
IAL_B
IRD_A
IRD_B
IS_1
M23
Y3
PF5_5
G24
V1
SCLK0B
SCLK1
TFS0_1
TFS0_2
TFS0_3
TFS0_4
TFS0_5
TFS0_6
TFS0_7
TFS0_8
TFS1
AE24
AF5
J2
IACK_A
IACK_B
IAD0_A
IAD0_B
IAD1_A
IAD1_B
IAD10_A
IAD10_B
IAD11_A
IAD11_B
IAD12_A
IAD12_B
IAD13_A
IAD13_B
IAD14_A
IAD14_B
IAD15_A
IAD15_B
IAD2_A
IAD2_B
IAD3_A
IAD3_B
IAD4_A
IAD4_B
IAD5_A
IAD5_B
IAD6_A
IAD6_B
IAD7_A
IAD7_B
IAD8_A
PF5_6
AC26
B4
M24
C8
PF5_7
AE11
AE18
M3
PF5-8
C12
B20
AE5
N23
Y1
F2
V26
B1
Y25
C4
PF6_1
F4
PF6_2
B10
B18
AD1
R26
T2
G2
V23
AA2
L26
V3
Y24
D6
PF6_3
G3
PF6_4
H1
IS_2
A14
F24
AA3
V25
AC7
AC16
Y26
D8
PF6_5
AF11
AC20
AF3
A7
H2
IS_3
PF6_6
H3
L23
AA4
M25
E2
IS_4
PF6_7
AD9
AC18
J4
H4
IS_5
PF6_8
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
H23
H24
H25
H26
N1
IS_6
PF7_1
A8
IS_7
PF7_2
D12
A18
AE3
N25
V2
A9
AD26
D1
IS_8
PF7_3
A13
A15
A17
AC14
AC15
AC19
AD14
AD19
AE14
AE19
AF14
AF19
B7
IWR_A
IWR_B
PF0
PF7_4
AC24
E4
Y23
A6
PF7_5
N2
PF7_6
N3
AC25
C2
PF1
B6
PF7_7
AF9
AF18
J1
N4
PF2
C6
PF7_8
R23
R24
T3
V24
D3
PF4_1
PF4_2
PF4_3
PF4_4
PF4_5
PF4_6
PF4_7
PF4_8
PF5_1
PF5_2
PF5_3
PF5_4
M1
RESET_1
RESET_2
RESET_3
RESET_4
RESET_5
RESET_6
RESET_7
RESET_8
RFS0A
RFS0B
RFS1
C10
D18
AC2
L25
T1
D13
C22
AF6
T23
AA1
AC11
AC22
J3
W24
C1
T24
U1
W25
D2
U2
U23
U24
U25
U26
W1
W2
W3
W4
W26
V4
AF7
AD18
M2
B8
M26
Y4
B9
D10
C18
AC3
AD20
AE6
P1
B14
B15
B17
N26
AD6
SCLK0A
REV. 0
–29–
ADSP-21mod980
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
Signal
Name
Ball
Number
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
B22
C7
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
D17
D22
K1
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
K26
L1
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
AB3
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
AF25
B3
AB4
C9
L2
AB23
AB24
AB25
AB26
AE13
AF13
AF24
P23
P24
P25
P26
R1
C14
C15
C17
D7
K2
L3
K3
L4
K4
A3
K23
K24
K25
A4
D9
AB1
AB2
R2
D15
R3
ORDERING GUIDE
Ambient
Temperature
Range
Package
Description
Package
Option
Part Number
Processor Clock
ADSP-21mod980-000
0°C to 70°C
37.5 MHz
Plastic Ball Grid Array (PBGA)
B-352
RELATED DOCUMENTS
ADSP-21mod980-210 Multiport Internet Gateway Processor Solution.
ADSP-21mod Family Dynamic Internet Voice AccessTM (DIVA) Voice Over Network Solution.
DIVA is a trademark of Analog Devices, Inc.
–30–
REV. 0
ADSP-21mod980
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
352-Ball Grid Array (PBGA)
(B-352)
26 24 22 20 18 16 14 12 10
25 23 21 19 17 15 13 11
8
6
4
2
1.378 (35.00) SQ
9
7
5
3
1
A
B
C
BALL A1
INDICATOR
D
E
F
G
H
J
K
L
M
N
P
(0.05) 1.27
BSC
TOP VIEW
BOTTOM VIEW
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1.209 (30.70)
1.181 (30.00) SQ
1.161 (29.50)
(0.05) 1.27 BSC
1.25 (31.75) BSC
DETAIL A
0.103 (2.62)
0.093 (2.37)
0.083 (2.12)
DETAIL A
0.048 (1.22)
0.046 (1.17)
0.044 (1.12)
0.028 (0.70)
0.024 (0.60)
0.020 (0.50)
NOTES
1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.012 (0.30)
OF THE IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.
2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.006 (0.15) OF ITS
IDEAL POSITION RELATIVE TO THE BALL GRID.
3. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
4. CONTROLLING DIMENSIONS ARE IN MILLIMETERS
0.008 (0.20)
MAX
0.028 (0.70)
0.024 (0.60)
0.020 (0.50)
0.035 (0.90)
0.030 (0.75)
0.024 (0.60)
SEATING
PLANE
BALL DIAMETER
REV. 0
–31–
相关型号：
ADSP-21MOD980N-210
ADSP-21mod980N-210: MultiPort Internet Gateway Processor Preliminary Data Sheet (Rev. PrB. 9/01)
ETC
ADSP-21MSP55ABS-52
IC 24-BIT, 13 MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100, Digital Signal Processor
ADI
ADSP-21MSP55AKS-52
IC 24-BIT, 13 MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100, Digital Signal Processor
ADI
ADSP-21MSP56ABS-52
IC 24-BIT, 13 MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100, Digital Signal Processor
ADI
ADSP-21MSP56AKS-52
IC 24-BIT, 13 MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100, Digital Signal Processor
ADI
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