AFE1600X [ETC]

AFE1600X 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR|Data Sheet ; AFE1600X 16位AFE，用于CCD / CIS信号处理器|数据表\n


型号：	AFE1600X
厂家：	ETC
描述：	AFE1600X 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR\|Data Sheet AFE1600X 16位AFE，用于CCD / CIS信号处理器\|数据表\n CD
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16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

AFE16

GENERAL DESCRIPTION

FEATURES

The samsung analog front end(AFE) for CCD/CIS

image signal is an integrated analog signal

processor for color image signal.

- 16-bit 6MSPS A/D Converter

- Integrated Triple Correlated Double

Sampler

The AFE converts CCD/CIS output signal to digital

- 3-Channel 2 MSPS Color Mode

- 1 ~ 6.25x Analog Programmable Gain

Amplifier

data.

The

AFE

Double

includes

three-channel

circuit,

CDS(Correlated

Sampling)

PGA(Programmable Gain Amplifier), and 16-bit

analog to digital converter with reference generator.

The 16-bit digital output is multiplexed into an

8-bit output word that is accessed using 8+8

format two read cycles. The internal resgisters are

programmed through a 3-wire serial interface, and

provide adjustment of the gain, offset, and

operating mode.

- Internal Voltage Reference

- No Missing Code Guaranteed

- Multiplexed Byte-Wide Output

(8+8 Format)

- 3-Wire Serial Digital Interface

- Operation by Single 3.3V Supply

- CMOS Low Power Dissipation

- 28-SOP-375 Package

APPLICATIONS

- Color and B/W Scanner

KEY SPECIFICATION

- Resolution: 16-bit

- Digital Copiers

- Conversion Rate: 6 MHz(2 MHz*3)

- Supply Voltage: 3.3 V ± 5%

- Power Dissipation: 257 mW(Typical)

- General Purpose CCD/CIS imager

FUNCTIONAL BLOCK DIAGRAM

RED

PGA

CDS

REF

DAC

OEB

G R E E N

16b

ADC

16:8

CDS

D[7:0]

M U X

DAC

BLUE

CDS

G A IN

R E G IS T E R S

S C L K

M P U

PORT

S L O A D

S D A T A

DAC

IN P U T O FFS E T

R E G IS T E R S

Ver 1.0 (July, 2001)

This datasheet is

a preliminary version. No responsibility is

assumed by SEC for its use nor for any infringements of patents

or other rights of third parties that may result from its use. The

content of this datasheet is subject to change without any notice.

SAMSUNG ELECTRONICS Co. LTD

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

CORE PIN DESCRIPTION

NAME

AVDDA

AVSSA

AVDDD

AVSSD

AVBBA

AVBBD

REFT

I/O TYPE

I/O PAD

vdda

DESCRIPTION

3.3 V Analog Supply

vssa

Analog Ground

vdda

3.3 V Digital Supply

Digital Ground

vssa

vbba

Analog Substrate

vbba

Digital Substrate

poa_bb

piar10_bb

picc_bb

poa_bb

picc_bb

pot4_bb

Reference Decoupling

Analog Common Voltage

Analog Input; Red

REFB

VCOM

R_VIN

G_VIN

Analog Input; Green

B_VIN

Analog Input; Blue

OFFSET

CDS1_CLK

CDS2_CLK

ADCCLK

SDATA

SCLK

Clamp Bias Level Decoupling

CDS Reset Clock Pulse Input

CDS Data Clock Pulse Input

A/D Converter Sample Clock Input

Serial Interface Data Input/Output

Serial Interface Clock Input

Serial Interface Load Pulse

Output Enable; Active Low

Data Outputs

SLOAD

OEB

D[7:0]

I/O TYPE ABBR.

- DP : Digital Power

- DG : Digital Ground

- AB : Analog Bidirectional Port

- DB : Digital Bidirectional Port

- AI : Analog Input

- DI : Digital Input

- AO : Analog Output

- DO : Analog Output

- AP : Analog Power

- AG : Analog Ground

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

CORE PIN CONFIGURATION

REFT VCOM REFB

AVSSD

AVDDD

AVSSA

AVDDA

OEB

R_VIN

G_VIN

B_VIN

D[7:0]

afe16

SDATA

SCLK

SLOAD

OFFSET

AVBBA

AVBBD

ADCCLK

CDS1_CLK

CDS2_CLK

ABSOLUTE MAXIMUM RATINGS

Characteristic

Supply Voltage

Symbol

VDD

Value

Unit

4.5

Analog Input Voltage

AIN

VSS to VDD

-45 to 150

Digital Input Voltage

CLK

V_OH, V_OL

VRT/VRB

Tstg

Digital Output Voltage

Reference Voltage

Storage Temperature Range

Operating Temperature Range

º C

Topr

0 to 70

NOTES

1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged

permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect

reliability. Each condition value is applied with the other values kept within the following operating

conditions and function operation under any of these conditions is not implied.

2. All voltages are measured with respect to VSS unless otherwise specified.

3. 100pF capacitor is discharged through a 1.5k resistor (Human body model)

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

ANALOG SPECIFICATIONS_{(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=6MHz,}

CDS1_CLK=2MHz,CDS2_CLK=2MHz, PGA Gain=1

unless otherwise noted

)

Characteristics

Symbol

Min

Typ

Max

Unit

Comment

Resolution

Bits

Conversion Rate

3-Channel with CDS

1-Channel with CDS

MSPS

Signal-to-Noise & Distortion

Ratio @ 1MHz Input

SNDR

DNL

INL

Differential

Nonlinearity

LSB

±1.3

Entire

Signal Path

Integral

Nonlinearity

Unipolar Offset Error

Gain Error

1.5

3.0

%FSR

Analog Input

Full-Scale Input

Input Capacitance

Reference Top

Reference Bottom

0.04

2.4

Vp-p

2.2

1.0

Amplifier

PGA Gain

6.25

V/V

Bits

PGA Resolution

OFFSET Range

OFFSET Resolution

-200

+200

Power Supply

Analog Voltage

Digital Voltage

Analog Current

Digital Current

VDDA1

VDDA2

IDD1

3.3

3.3V 5%

IDD2

Power Consumption

Temperature Range

257

º C

Operating

DIGITAL SPECIFICATIONS_{(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=6MHz,}

CDS1_CLK=2MHz, CDS2_CLK=2MHz, C_L=20pF

unless otherwise noted)

Characteristics

Symbol

Min

Typ

Max

Unit

Comment

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

High Level Output Voltage

Low Level Output Voltage

V_IH

V_IL

I_IH

2.0

0.7

I_IL

V_oH

V_OL

3.0

I_oH= 0.5mA

I_oL= -0.5mA

0.3

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

TIMING SPECIFICATIONS

(VDDA1=3.3V, VDDA2=3.3V unless otherwise noted)

Characteristics

CLOCK CHARACTERISTICS

3-Channel Conversion Rate

1-Channel Conversion Rate

CDSCLK1 Pulse Width

Symbol

Min

Typ

Max

Unit

500

166

t_C1CLK

t_C2CLK

t_C2CLKB

t_C1C2A

t_C2C1A

t_ADCLK

t_C2ADA

t_C2ADB

t_ADC2A

t_AD

CDSCLK2 Pulse Width

CDSCLK2B Pulse Width

CDSCLK1 Falling to CDSCLK2 Rising

CDSCLK2 Falling to CDSCLK1 Rising

ADCCLK Pulse Width

CDSCLK2 Rising to ADCCLK Rising

CDSCLK2 Falling to ADCCLK Falling

ADCCLK Rising to CDS2CLK Falling

Aperture Delay

SERIAL INTERFACE

Maximum SCLK Frequency

SLOAD to SCLK Set-up Time

SCLK to SLOAD Hold Time

SDATA to SCLK Rising Set-up Time

SCLK Rising to SDATA Hold Time

SCLK Falling to SDATA Valid

DATA OUTPUT

f_CLK

t_LS

MHz

t_LH

t_DS

t_DH

t_RDV

ADC Output Delay

t_ADDT

t_DEV

t_HZ

Tri-State to Data Valid

Output Enable High to Tri-State

ADCCLK

Cycles

ADC Latency(Pipeline Delay)

* Aperture delay is a timing measurement between the sampling clocks and

CDS. It is measured from the falling edge of the CDS2_CLK input to when the

input signal is held for data conversion

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

TIMING DIAGRAM

3-Channel CDS Mode

Analog

Input

R0,G0,B0

R1,G1,B1

R2,G2,B2

tC1C2A

tC2C1A

tC1CLK

CDS1_CLK

tC2ADA

tADC2A

tC2CLKB

CDS2_CLK

ADCCLK

tADCLK

tADDT

OUTPUT

D[7:0]

R-2 R-2

G-2 G-2 B-2

B-2 R-1

R-1 G-1

G-1 B-1 B-1

3-Channel SHA Mode

Analog

Input

R0,G0,B0

R1,G1,B1

R2,G2,B2

tC2ADA

tADC2A

tC2CLKB

CDS2_CLK

ADCCLK

tADCLK

tADDT

R0 R0

OUTPUT

D[7:0]

R-2 R-2

G-2 G-2

B-2

B-2 R-1

R-1

G-1

B-1

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

1-Channel CDS Mode

Analog

Input

tC1CLK

tC1C2A

tC2C1A

CDS1_CLK

CDS2_CLK

ADCCLK

tC2CLK

tC2ADA

tADCLK

tC2ADB

1-Channel SHA Mode

Analog

Input

R0,G0,B0

tC2CLK

R1,G1,B1

R2,G2,B2

CDS2_CLK

ADCCLK

tC2ADA

tADCLK

tC2ADB

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

Digital Output Data Timing

ADCCLK

tADDT

Byte

High Byte Low

D13-D6

OUTPUT

D[7:0]

High

Low

High

Low

D5-D0

tHZ

tDEV

OEB

Serial Write Operation Timing

SDATA

R/Wb A2

A1 A0

XX XX XX

D7 D6

D5 D4

D3 D2 D1 D0

tDH

tDS

SCLK

tLH

tLS

SLOAD

Serial Read Operation Timing

SDATA

R/Wb A2

A1 A0

XX XX XX

D7 D6

D5 D4

tRDV

D3 D2 D1 D0

tDH

tDS

SCLK

tLH

tLS

SLOAD

'Read' means microcontroller reads SDATA

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

MAIN BLOCK DESCRIPTION

FUNCTIONAL DESCRIPTION

1) 3-Channel Operation with CDS

1) Programmable Gain Amplifier

This mode enables simultaneous sampling of a

triple output CCD. The CCD waveforms are ac

coupled to the R_VIN, G_VIN and B_VIN pins

where they are automatically biased at an

appropriate voltage using the on-chip clamp. The

internal CDSs take two samples of the incoming

pixel data; the first samples are taken during the

reset time while the second samples are taken

during data portion of the input pixels.

The analog programmable gain can accommodate

a wide range of input voltage spans. The transfer

function of the PGA is as follows.

H(X) = 1/12*X + 1,

where the range of X is 0 to 63.

Thus, the minimum gain value is equal to 1, and

the maximum gain value is equal to 6.25. The

transfer function has linearity in linear scale. The

overall gain is equal to analog gain multiplied

by digital gain. So, the multiplier should be

required in back end of AFE.

2) 3-Channel SHA Operation

This mode enables simultaneous sampling of

triple output CIS or something like that. The CDS

functions are replaced with the sample and hold

amplifiers. The input waveforms are either dc

coupled or dc restored to the R_VIN, G_VIN and

B_VIN pins. The input reference voltage in this

mode will be defined by external OFFSET pin.

3) 1-Channel Operation with CDS

This mode enables single channel or monochrome

sampling. The CCD waveforms are ac coupled to

the analog input pin where they are automatically

biased at an appropriate voltage using the on-chip

clamp.

PGA Register Value

Bit4, bit5 and bit6 in MUX register select the

desired input among red, green and blue.

4) 1-Channel SHA Operation

This mode enables single-channel or monochrome

sampling. The CDS function is replaced with the

sample and hold amplifier.

The input waveforms are either dc coupled or dc

restored to the analog input pin. The input

reference voltage in this mode will be defined by

clamp level control register.

Bit4, bit5 and bit6 in MUX register select the

desired input among red, green and blue.

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

BLOCK DIAGRAM

VDDA1 VSSA1 VDDA2

VSSDR

VSSA2 VDDDR

VCOM REFB

REFT

RED

R_VIN

CDS

PGA

CLAMP

R_OFFSET[8:0]

REF

DAC

R_GAIN[5:0]

PGA

GREEN

G_VIN

16-bit

ADC

16:8

MUX

CDS

MUX

CLAMP

D[7:0]

G_OFFSET[8:0]

DAC

G_GAIN[5:0]

OEB

BLUE

B_VIN

PGA

CDS

CLAMP

Configuration

B_OFFSET[8:0]

DAC

B_GAIN[5:0]

SDATA

SCLK

R_OFFSET[8:0]

Input Offset

MPU

PORT

G_OFFSET[8:0]

B_OFFSET[8:0]

(R,G,B)

SLOAD

OFFSET

R_GAIN[5:0]

G_GAIN[5:0]

PGA Gain

(R,G,B)

B_GAIN[5:0]

CDS2_CLK

ADCCLK

CDS1_CLK

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

2) INTERNAL REGISTER OVERVIEW

The internal register map is accessed through serial data pin SDATA's A0, A1 and A2.

Address

A1 A0

Data Bits

PWR Dn

Configuration

MUX

3Ch/1Ch CDS on

RGB/BGR Red

Green

MSB

Blue

Red PGA

LSB

Green PGA

Blue PGA

Red Offset

Green Offset

Blue Offset

MSB

Configuration Register

# of Channels

CDS Operation

Power Down

Set to

Set to 0

1=3-CH mode*

0=1-CH mode

1=CDS Mode*

0=SHA Mode*

1=On

0=Off (Operation)*

*Power-on Default Value, X: Don't care

MUX Register

3-CH Select

1-CH

Set to

Set to 0

1=R-G-B*

0=B-G-R

1=RED*

0=Off

1=Green

0=Off*

1=Blue

0=Off*

*Power-on Default Value

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

PGA Gain Register

Gain

(dB)

D6 D5(MSB)

D0(LSB)

(V/V)

1.083

1.167

0.693

1.341

. . .

6.167

6.25

15.801

15.918

*Power-on Default Value

Offset Register

D8(MSB)

Offset

D0(LSB)

Sign Bit

(mV)

0.781

1.563

. . .

200

-0.781

-1.563

. . .

-200

*Power-on Default Value

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

INPUT COUPLING CAPACITOR

OVERALL TRANSFER FUNCTION

Because of the DC offset present at the output of

The overall transfer function can be calculated as

follows.

CCD, some kind of DC restoration is

required. In case of CDS enable mode, to

simplify input level shifting, a DC decoupling

capacitor is used in conjuction with the

internal input circuitry.

ADC_out=[(Vin+Input_Offset)* PGA_Gain]/(2*REF)*65536,

where REF is equal to (REFT-REFB) and Input

_Offset means the DAC value of the input offset

offset register is varied between 200mV and -200

mV. The 9-bit data format for the input offset

To maximize the dynamic range of the ADC input,

The capacitor charging or discharging depends on

the clamping time, the analog input resistance of

the AFE and the output resistance of the circuit

driving the coupling capacitor.

it is necessary to program the input offset register

code to move the ADC code corresponding to

the black level towards 'zero'.

The clamping time is typically (n*T), where n is

the number of periods

CDSCLK1 is asserted

and T is the period of assertion. CDSCLK2

should not be asserted during clamping time. The

analog input resistance of the AFE's Clamp is

And also PGA_gain is to maximize the dynamic

range of the 16-bit ADC's input. The PGA_gain

range is varied between 1 and 6.25 by PGA gain

equal to 1 k . The recommended input coupling

capacitor is more than 0.1uF. The time constant

of the input clamp is determined by the internal

1K resistance and the external 0.1uF input

capacitance. Thus, to extend the clamping time,

the time a transport motor moves the scanner

carriage can be available, for example.

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

POWER-ON INITIALIZATION

CALIBRATION

Decide clamp level for SHA mode

(Refer to next page)

Write to configuration register

Set CDS or SHA operation

Set 3 or 1 channel mode

Set color pointer

Set PGA gain

(Input offset = 0 mV)

Set clamp mode

Scan dark line

Compute pixel offsets

Write to PGA gain register

Set to gain of one(000000)

Set input offset

Write to input offset register

Set to 0mV(100000000)

Set odd/even offset in back end

YES

Set another color

YES

Set another color

Set gain/offset bus size

in back end

Set external pixel offset

in back end

Scan white line

Compute pixel gains

in back end

YES

Adjust PGA gain

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

CORE EVALUATION GUIDE

0.1u

AVSSD

AVDDD

AVSSA

AVDDA

REFT VCOM REFB

OEB

R_VIN

G_VIN

B_VIN

D[7:0]

afe16

SDATA

SCLK

SLOAD

OFFSET

AVBBA

AVBBD

ADCCLK

CDS2_CLK

CDS1_CLK

TIMING GENERATOR

MPU INTERFACE

DSP ASIC

MUX

Externally forced digital input/output

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

APPLICATIONS INFORMATION

CDS Mode Applications

- The recommended input coupling capacitor value is 0.1uF.

- A single ground plane is recommended for the afe16. Thus the digital pins should be

well decoupled to the analog ground plane.

- If possible, a separate power supply should be used for VDDDR, but this supply pin

should still be decoupled to the same ground plane as the rest of the afe16.

- The loading of digital outputs should be minimized.

- All 0.1uF decoupling capacitors should be located as close as possible to the afe16

pins.

- When operating in single channel mode, the unused analog inputs must be grounded.

CDSCLK1

VDDA2

0.1u

CDSCLK2

ADCCLK

OEB

VSSA2

R_VIN

0.01u

OFFSET

VDDDR

VSSDR

D7(MSB)

G_VIN

VCOM

B_VIN

REFT

0.1u

1.0u

0.1u

0.01u

10u

afe16

0.1u

REFB

VSSA1

VDDA1

SLOAD

SCLK

0.1u

D0(LSB)

SDATA

Data Outputs

3-Channel CDS Mode Application Circuit Configuration

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

SHA Mode Applications

- All of the CDS mode's considerations also apply for this configuration, except that

analog inputs are directly connected to the afe16 without coupling capacitors.

- The OFFSET pin may be used in a CIS application for DC offset adjustment.

By connecting the appropriate dc voltage to the OFFSET pin, the CIS signal will be

restored to "zero".

CDSCLK1

VDDA2

0.1u

CDSCLK2

ADCCLK

OEB

VSSA2

R_VIN

OFFSET

VDDDR

VSSDR

D7(MSB)

G_VIN

VCOM

B_VIN

REFT

0.1u

afe16

0.1u

10u

0.1u

REFB

VSSA1

VDDA1

SLOAD

SCLK

0.1u

D0(LSB)

SDATA

Data Outputs

3-Channel SHA Mode Application Circuit Configuration

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

PACKAGE PIN DESCRIPTION

PIN NO.

PIN NAME

I/O TYPE

DESCRIPTION

CDS1_CLK

CDS2_CLK

ADCCLK

OEB

CDS Reference Sampling Clock

CDS Data Sampling Clock

A/D Converter Clock

Output Enable (Active Low)

Output Buffer Power

VDDDR

VSSDR

Output Buffer Ground

Digital Output (MSB)

D[7]

High Byte: D15, Low Byte: D7

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

Digital Output (D14, D6)

Digital Output (D13, D5)

Digital Output (D12, D4)

Digital Output (D11, D3)

Digital Output (D10, D2)

Digital Output (D9, D1)

Digital Output (LSB)

D[0]

High Byte: D8, Low Byte: D0

SDATA

SCLK

Serial Interface Data Input/Output

Serial Interface Clock Input

Serial Interface Load Pulse

Analog Power

SLOAD

VDDA1

VSSA1

REFB

Analog Ground

Reference Decoupling

Analog Input : Blue

Analog Common Voltage

Analog Input : Green

Clamp Bias Level Decoupling

Analog Input : Red

REFT

B_VIN

VCOM

G_VIN

OFFSET

R_VIN

VSSA2

VDDA2

Digital Ground

Digital Power

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

USER GUIDE

SYSTEM CONFIGURATION

It is necessary that output signal of analog front end be shading-compensated by back end

logic block including subtracter and multiplier.

(Shading-Compensation Block)

Memory

Subtracter

Multiplier

Controller

AFE

CCD/CIS

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

Questionnaire for Analog Core

Characteristics

Symbol

Min

Typ

Max

Unit

Comment

Resolution

Bits

Signal-to-Noise & Distortion

Ratio

SNDR

Conversion Rate

3-Channel with CDS

1-Channel with CDS

MSPS

Differential

Nonlinearity

DNL

INL

LSB

Integral

Nonlinearity

Unipolar Offset Error

Gain Error

%FSR

Anlog Input

Vp-p

Full-Scale Input

Power Supply

Analog Voltage

Digital Voltage

VDDA

VDDD

Power Consumption

Temperature Range

º C

- What do you want to choose as power supply voltages?

For example, the analog VDD needs to be 3.3V. The digital VDD can be 2.5V/3.3V.

- Which modes of AFE do you use for overall system ? (Refer to page 9)

For example: 3channel operation with CDS / 3channel SHI(CIS) operation

1channel operation with CDS / 1channel SHI(CIS) operation

- Would you define the gain range and input offset range ?

Could you explain external/internal pin configurations as required?

- If possible, present other requirements below.

SEC ASIC

MIXED

AFE16

16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR

HISTORY CARD

Version

Date

Modified Items

Comments

ver 1.0

2001.07 Original version published (preliminary)

SEC ASIC

MIXED

AFE1600X [ETC]

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