AMD-K6-2 [ETC]
AMD-K6-2 - AMD-K6-2 Processor Data Sheet ; AMD- K6-2 - AMD- K6-2处理器数据手册\n
| 型号： | AMD-K6-2 |
| 厂家： | 
ETC |
| 描述： | AMD-K6-2 - AMD-K6-2 Processor Data Sheet
|
| 文件： | 总330页 (文件大小：5291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
®
AMD-K6-2
Processor
Data Sheet
© 2000 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced Micro
Devices, Inc. ("AMD") products. AMD makes no representations or warranties with
respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any
time without notice. No license, whether express, implied, arising by estoppel or
otherwise, to any intellectual property rights is granted by this publication. Except
as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no
liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability,
fitness for a particular purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use as
components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or in any other application in which
the failure of AMD’s product could create a situation where personal injury, death,
or severe property or environmental damage may occur. AMD reserves the right to
discontinue or make changes to its products at any time without notice.
Trademarks
AMD, the AMD logo, K6, 3DNow!, and combinations thereof, K86, and Super7 are trademarks, and AMD-K6
and RISC86 are registered trademarks of Advanced Micro Devices, Inc.
Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation.
NetWare is a registered trademark of Novell, Inc.
MMX is a trademark of Intel Corporation.
The TAP State Diagram is reprinted from IEEE Std 1149.1-1990 “IEEE Standard Test Access Port and Bound-
ary-Scan Architecture,” Copyright © 1990 by the Institute of Electrical and Electronics Engineers, Inc. The
IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.
Information is reprinted with the permission of the IEEE.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Contents
Revision Historyxix
®
1
AMD-K6 -2 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
Super7™ Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Super7™ Platform Enhancements. . . . . . . . . . . . . . . . . . . . . . . 3
Super7™ Platform Advantages . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
®
AMD-K6 -2 Processor Microarchitecture Overview . . . . . . . . 5
®
Enhanced RISC86 Microarchitecture . . . . . . . . . . . . . . . . . . . 6
2.3
Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . . 9
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register X and Y Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Branch History Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Branch Target Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
2.5
2.6
2.7
3
Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Floating-Point Register Data Types. . . . . . . . . . . . . . . . . . . . . 28
MMX™/3DNow!™ Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MMX™ Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3DNow!™ Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . . 37
Contents
iii
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . 40
Task State Segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Descriptors and Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
®
3.2
AMD-K6 -2 Processor Model 8/[F:8] Registers . . . . . . . . . . . 50
Extended Feature Enable Register (EFER)–Model 8/[F:8] . 50
Write Handling Control Register (WHCR)–Model 8/[F:8] . . 51
UC/WC Cacheability Control Register
(UWCCR)52
Processor State Observability Register (PSOR). . . . . . . . . . . 53
Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . 53
®
3.3
Instructions Supported by the AMD-K6 -2 Processor . . . . . 54
4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
A20M# (Address Bit 20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 85
A[31:3] (Address Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADS# (Address Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ADSC# (Address Strobe Copy) . . . . . . . . . . . . . . . . . . . . . . . . 87
AHOLD (Address Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
AP (Address Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
APCHK# (Address Parity Check) . . . . . . . . . . . . . . . . . . . . . . 90
BE[7:0]# (Byte Enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.10 BF[2:0] (Bus Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.11 BOFF# (Backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.12 BRDY# (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.13 BRDYC# (Burst Ready Copy) . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.14 BREQ (Bus Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.15 CACHE# (Cacheable Access) . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.16 CLK (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.17 D/C# (Data/Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.18 D[63:0] (Data Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.19 DP[7:0] (Data Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.20 EADS# (External Address Strobe) . . . . . . . . . . . . . . . . . . . . 100
4.21 EWBE# (External Write Buffer Empty) . . . . . . . . . . . . . . . . 101
4.22 FERR# (Floating-Point Error) . . . . . . . . . . . . . . . . . . . . . . . 102
4.23 FLUSH# (Cache Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.24 HIT# (Inquire Cycle Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.25 HITM# (Inquire Cycle Hit To Modified Line) . . . . . . . . . . . 104
4.26 HLDA (Hold Acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.27 HOLD (Bus Hold Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.28 IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . 106
4.29 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.30 INTR (Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.31 INV (Invalidation Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.32 KEN# (Cache Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
iv
Contents
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
4.33 LOCK# (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.34 M/IO# (Memory or I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.35 NA# (Next Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.36 NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . 112
4.37 PCD (Page Cache Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.38 PCHK# (Parity Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.39 PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.40 RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.41 RSVD (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.42 SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.43 SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . 117
4.44 SMIACT# (System Management Interrupt Active) . . . . . . 118
4.45 STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.46 TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.47 TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.48 TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.49 TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.50 TRST# (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.51 VCC2DET (V
4.52 VCC2H/L# (V
Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
High/Low) . . . . . . . . . . . . . . . . . . . . . . . . . 121
CC2
CC2
4.53 W/R# (Write/Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.54 WB/WT# (Writeback or Writethrough) . . . . . . . . . . . . . . . . 123
5
Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.1
5.2
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 129
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Data-NA# Requested. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Pipeline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Pipeline Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Memory Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Single-Transfer Memory Read and Write . . . . . . . . . . . . . . . 132
Misaligned Single-Transfer Memory Read and Write . . . . . 134
Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . 136
Burst Writeback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Misaligned I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . 141
Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 142
Hold and Hold Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . 142
HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . 144
HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 146
AHOLD-Initiated Inquire Miss. . . . . . . . . . . . . . . . . . . . . . . . 148
AHOLD-Initiated Inquire Hit to Shared or Exclusive Line. 150
5.3
5.4
5.5
Contents
v
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
AHOLD-Initiated Inquire Hit to Modified Line. . . . . . . . . . 152
AHOLD Restriction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Bus Backoff (BOFF#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Locked Operation with BOFF# Intervention . . . . . . . . . . . . 160
Interrupt Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Basic Special Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Stop Grant and Stop Clock States . . . . . . . . . . . . . . . . . . . . . 167
INIT-Initiated Transition from Protected Mode to
5.6
Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6
Power-on Configuration and Initialization . . . . . . . . . . . . . . 173
6.1
Signals Sampled During the Falling Transition of RESET 173
FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
RESET Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
State of Processor After RESET . . . . . . . . . . . . . . . . . . . . . . 174
Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
State of Processor After INIT . . . . . . . . . . . . . . . . . . . . . . . . 177
6.2
6.3
6.4
7
Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
7.1
7.2
7.3
MESI States in the Data Cache . . . . . . . . . . . . . . . . . . . . . . . 180
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Cache-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Cache Disabling and Flushing . . . . . . . . . . . . . . . . . . . . . . . 183
Cache-Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Cache-Line Replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Write to a Cacheable Page . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Write to a Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Write Allocate Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Write Allocate Logic Mechanisms and Conditions . . . . . . . 189
Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Hardware Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Software Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Cache States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
7.4
7.5
7.6
7.7
7.8
7.9
7.10 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Internal Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
vi
Contents
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
WBINVD and INVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Cache-Line Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Cache Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.11 Writethrough versus Writeback Coherency States . . . . . . . 199
7.12 A20M# Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . 199
8
9
Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
8.1
8.2
EWBE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Memory Type Range Registers . . . . . . . . . . . . . . . . . . . . . . . 203
UC/WC Cacheability Control Register (UWCCR) . . . . . . . . 203
Floating-Point and Multimedia Execution Units . . . . . . . . . 207
9.1
Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . 207
Handling Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . 207
External Logic Support of Floating-Point Exceptions. . . . . 207
Multimedia and 3DNow!™ Execution Units . . . . . . . . . . . . 209
Floating-Point and MMX™/3DNow!™ Instruction Compatibili-
209
9.2
9.3
ty
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
FERR# and IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
10
System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . 211
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
10.2 SMM Operating Mode and Default Register Values . . . . . 211
10.3 SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
10.4 SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
10.5 SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
10.6 Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
10.7 I/O Trap Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
10.8 I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
10.9 Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . 220
11
Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.1 Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
11.2 Tri-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
11.3 Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . 223
Test Access Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
TAP Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . 232
11.4 L1 Cache Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
11.5 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Contents
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12
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
12.1 Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Enter Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Exit Halt State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
12.2 Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Enter Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Exit Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
12.3 Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Enter Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . 246
Exit Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . 246
12.4 Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Enter Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Exit Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
13
14
Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
13.1 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
13.2 Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . 250
13.3 Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . . 251
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
14.1 Electrical Data for OPN Suffixes AHX, 400AFQ, and AFR 253
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
14.2 Electrical Data for OPN Suffixes AGR, AFX, and 400AFR 258
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
15
16
I/O Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
15.1 Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
15.2 I/O Buffer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
15.3 I/O Model Application Note . . . . . . . . . . . . . . . . . . . . . . . . . 265
15.4 I/O Buffer AC and DC Characteristics . . . . . . . . . . . . . . . . . 265
Signal Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 267
16.1 CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 267
16.2 Clock Switching Characteristics for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
16.3 Clock Switching Characteristics for 66-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
16.4 Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . 269
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AMD-K6 -2 Processor Data Sheet
16.5 Output Delay Timings for 100-MHz Bus Operation . . . . . . 270
16.6 Input Setup and Hold Timings for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
16.7 Output Delay Timings for 66-MHz Bus Operation . . . . . . . 274
16.8 Input Setup and Hold Timings for 66-MHz Bus Operation 276
16.9 RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . 278
17
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
17.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 285
Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 290
17.2 Layout and Airflow Considerations . . . . . . . . . . . . . . . . . . . 291
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Airflow Management in a System Design. . . . . . . . . . . . . . . 292
18
19
20
Pin Description Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Pin Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
20.1 321-Pin Staggered CPGA Package Specification . . . . . . . . 299
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
21
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Contents
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Preliminary Information
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Contents
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
List of Figures
®
Figure 1. AMD-K6 -2 Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. The Instruction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
®
Figure 4. AMD-K6 -2 Processor Decode Logic . . . . . . . . . . . . . . . . . . . . . 12
®
Figure 5. AMD-K6 -2 Processor Scheduler . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Register X and Y Functional Units . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. EAX Register with 16-Bit and 8-Bit Name Components. . . . . . 22
Figure 8. Integer Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. FPU Status Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. FPU Control Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. FPU Tag Word Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Packed Decimal Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Precision Real Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. MMX™/3DNow!™ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. MMX™ Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. 3DNow!™ Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. EFLAGS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21. Control Register 4 (CR4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 22. Control Register 3 (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23. Control Register 2 (CR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 24. Control Register 1 (CR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 25. Control Register 0 (CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 26. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 27. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 28. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 29. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . . 36
Figure 30. Machine-Check Address Register (MCAR) . . . . . . . . . . . . . . . . 37
Figure 31. Machine-Check Type Register (MCTR). . . . . . . . . . . . . . . . . . . 38
Figure 32. Test Register 12 (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 33. Time Stamp Counter (TSC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 34. Extended Feature Enable Register (EFER)–Model 8[7:0] . . . 39
Figure 35. SYSCALL/SYSRET Target Address Register (STAR) . . . . . . . 39
Figure 36. Write Handling Control Register (WHCR)–Model 8/[7:0]. . . . 40
List of Figures
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Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Figure 37. Memory Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 38. Task State Segment (TSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 39. 4-Kbyte Paging Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 40. 4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 41. Page Directory Entry 4-Kbyte Page Table (PDE). . . . . . . . . . . 45
Figure 42. Page Directory Entry 4-Mbyte Page Table (PDE) . . . . . . . . . . 45
Figure 43. Page Table Entry (PTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 44. Application Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 45. System Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 46. Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 47. Extended Feature Enable Register (EFER)—Model 8/[F:8]. . 51
Figure 48. Write Handling Control Register (WHCR)—Model 8/[F:8] . . 52
Figure 49. UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . . 52
Figure 50. Processor State Observability Register (PSOR) . . . . . . . . . . . . 53
Figure 51. Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . . 53
Figure 52. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 53. Waveform Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 54. Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 55. Non-Pipelined Single-Transfer Memory Read/Write and
Write Delayed by EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 56. Misaligned Single-Transfer Memory Read and Write . . . . . . 135
Figure 57. Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . . 137
Figure 58. Burst Writeback due to Cache-Line Replacement . . . . . . . . . 139
Figure 59. Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 60. Misaligned I/O Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 61. Basic HOLD/HLDA Operation . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 62. HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . 145
Figure 63. HOLD-Initiated Inquire Hit to Modified Line. . . . . . . . . . . . . 147
Figure 64. AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 65. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line . . 151
Figure 66. AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 153
Figure 67. AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 68. BOFF# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 69. Basic Locked Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 70. Locked Operation with BOFF# Intervention. . . . . . . . . . . . . . 161
Figure 71. Interrupt Acknowledge Operation . . . . . . . . . . . . . . . . . . . . . . 163
Figure 72. Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . . . . . . . 165
Figure 73. Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 74. Stop Grant and Stop Clock Modes, Part 1 . . . . . . . . . . . . . . . . 168
xii
List of Figures
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Figure 75. Stop Grant and Stop Clock Modes, Part 2 . . . . . . . . . . . . . . . . 169
Figure 76. INIT-Initiated Transition from Protected Mode to
Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 77. Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 78. Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 79. Write Handling Control Register (WHCR) —
Model 8/[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 80. Write Handling Control Register (WHCR)—
Model 8/[F:8]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 81. Write Allocate Logic Mechanisms and Conditions . . . . . . . . . 190
Figure 82. Page Flush/Invalidate Register (PFIR)—
MSR C000_0088h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 83. UC/WC Cacheability Control Register (UWCCR)—
MSR C000_0085h (Model 8/[F:8]). . . . . . . . . . . . . . . . . . . . . . . 204
Figure 84. External Logic for Supporting Floating-Point Exceptions. . . 208
Figure 85. SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 86. TAP State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 87. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 88. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 89. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 90. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . 239
Figure 91. Clock Control State Transitions . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 92. Suggested Component Placement . . . . . . . . . . . . . . . . . . . . . . 250
Figure 93. K6STD Pulldown V/I Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 94. K6STD Pullup V/I Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 95. CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 96. Diagrams Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 97. Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 98. Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 99. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 100. Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 101. TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 102. TRST# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 103. Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 104. Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 105. Power Consumption versus Thermal Resistance . . . . . . . . . . 288
Figure 106. Processor Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 107. Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 108. Voltage Regulator Placement. . . . . . . . . . . . . . . . . . . . . . . . . . 291
List of Figures
xiii
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Figure 109. Airflow for a Heatsink with Fan. . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 110. Airflow Path in a Dual-Fan System . . . . . . . . . . . . . . . . . . . . . 293
Figure 111. Airflow Path in an ATX Form-Factor System . . . . . . . . . . . . . 293
®
Figure 112. AMD-K6 -2 Processor Top-Side View . . . . . . . . . . . . . . . . . . . 295
®
Figure 113. AMD-K6 -2 Processor Pin-Side View. . . . . . . . . . . . . . . . . . . . 296
Figure 114. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 300
xiv
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List of Tables
Table 1.
Table 2.
Table 3.
Execution Latency and Throughput of Execution Units . . . . . 16
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
General-Purpose Register Doubleword, Word, and
Byte Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4.
Table 5.
Table 6.
Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AMD-K6 -2 Processor Model 8/[7:0] MSRs . . . . . . . . . . . . . . . . 37
Extended Feature Enable Register (EFER)–
®
Model 8[7:0]Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7.
SYSCALL/SYSRET Target Address Register (STAR)
Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Memory Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . 40
Application Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 8.
Table 9.
Table 10. System Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 11. Summary of Exceptions and Interrupts. . . . . . . . . . . . . . . . . . . 49
®
Table 12. AMD-K6 -2 Processor Model 8/[F:8] MSRs . . . . . . . . . . . . . . . . 50
Table 13. Extended Feature Enable Register (EFER)–
Model 8/[F:8] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 14. Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 15. Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 16. MMX™ Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 17. 3DNow!™ Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 18. Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 19. Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 20. Input Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 21. Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 22. Input/Output Pin Float Conditions. . . . . . . . . . . . . . . . . . . . . . 125
Table 23. Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 24. Bus Cycle Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 25. Special Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 26. Bus-Cycle Order During Misaligned Transfers . . . . . . . . . . . . 134
Table 27. A[4:3] Address-Generation Sequence During Bursts . . . . . . . 136
Table 28. Bus-Cycle Order During Misaligned I/O Transfers . . . . . . . . . 141
Table 29. Interrupt Acknowledge Operation Definition. . . . . . . . . . . . . 162
Table 30. Encodings For Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . 164
Table 31. Output Signal State After RESET . . . . . . . . . . . . . . . . . . . . . . 174
Table 32. Register State After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 33. PWT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 34. PCD Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 35. CACHE# Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 36. Data Cache States for Read and Write Accesses . . . . . . . . . . 193
Table 37. Cache States for Inquire Cycles, Snoops, Flushes,
and Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
List of Tables
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Table 38. Snoop Action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 39. EWBEC Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 40. WC/UC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 41. Valid Masks and Range Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 42. Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 213
Table 43. SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 44. SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 45. I/O Trap Dword Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 46. I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 47. Boundary Scan Bit Definitions for Model 8/[7:0] . . . . . . . . . . 227
Table 48. Boundary Scan Bit Definitions for Model 8/[F:8] . . . . . . . . . . 229
Table 49. Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 50. Supported Tap Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 51. DR7 LEN and RW Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 52. Operating Ranges for OPN Suffixes AHX, 400AFQ,
and AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 53. Absolute Ratings for OPN Suffixes AHX, 400AFQ,
and AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 54. DC Characteristics for OPN Suffixes AHX, 400AFQ,
and AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 55. Typical and Maximum Power Dissipation for OPN
Suffixes AHX, 400AFQ, and AFR. . . . . . . . . . . . . . . . . . . . . . . 257
Table 56. Operating Ranges for OPN Suffixes AGR, AFX, and
400AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 57. Absolute Ratings for OPN Suffixes AGR, AFX,
and 400AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 58. DC Characteristics for OPN Suffixes AGR, AFX,
and 400AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 59. Typical and Maximum Power Dissipation for OPN
Suffixes AGR, AFX, and 400AFR. . . . . . . . . . . . . . . . . . . . . . . 262
Table 60. A[20:3], ADS#, HITM#, and W/R# Strength Selection . . . . . . 263
Table 61. CLK Switching Characteristics for 100-MHz Bus Operation . 268
Table 62. CLK Switching Characteristics for 66-MHz Bus Operation . . 268
Table 63. Output Delay Timings for 100-MHz Bus Operation . . . . . . . . 270
Table 64. Input Setup and Hold Timings for 100-MHz Bus Operation . 272
Table 65. Output Delay Timings for 66-MHz Bus Operation . . . . . . . . . 274
Table 66. Input Setup and Hold Timings for 66-MHz Bus Operation . . 276
Table 67. RESET and Configuration Signals for 100-MHz
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 68. RESET and Configuration Signals for 66-MHz
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 69. TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 280
Table 70. Test Signal Timing at 25 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 71. Package Thermal Specification for OPN Suffixes
AHX, AFQ, and AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
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List of Tables
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Table 72. Package Thermal Specification for OPN Suffixes
AGR, AFX, and 400AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Table 73. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 299
Table 74. Valid Ordering Part Number Combinations . . . . . . . . . . . . . . 301
List of Tables
xvii
Preliminary Information
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List of Tables
Preliminary Information
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AMD-K6 -2 Processor Data Sheet
Revision History
Date
Rev
Description
Feb 1999
F
Revised Replacement and Internal Snoop conditions in “Burst Writeback” on page 138.
Revised Chapter 7, “Cache Organization” and added Figure 82,”Page Flush/Invalidate Register
(PFIR)—MSR C000_0088h,” and PFIR’s bit descriptions.
Feb 1999
Feb 1999
F
F
Added 450 MHz (V = 2.4 V) specifications to tables in Chapter 14, “Electrical Data”.
CC2
Revised Table 71, “Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR,” on
page 285, Figure 105, “Power Consumption versus Thermal Resistance,” on page 288, and the
example on page 290.
Feb 1999
Feb 1999
F
F
Updated Chapter 21, “Ordering Information” on page 301.
Added 475 MHz specifications to Table 54, “DC Characteristics for OPN Suffixes AHX, 400AFQ, and
AFR,” on page 254, Table 55, “Typical and Maximum Power Dissipation for OPN Suffixes AHX,
400AFQ, and AFR,” on page 257, Table 71, “Package Thermal Specification for OPN Suffixes AHX,
AFQ, and AFR,” on page 285, and Chapter 21, “Ordering Information” on page 301.
Apr 1999
July 1999
July 1999
G
H
H
Added 500 MHz specifications. Rearranged Chapter 14, “Electrical Data” into 14.1 “Electrical Data
for OPN Suffixes AHX, 400AFQ, and AFR” on page 253 and 14.2 “Electrical Data for OPN Suffixes
AGR, AFX, and 400AFR” on page 258. In Chapter 17, “Thermal Design”, provided thermal
specifications in Table 71, “Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR”and
Table 72, “Package Thermal Specification for OPN Suffixes AGR, AFX, and 400AFR”. Updated
Chapter 21, “Ordering Information”.
Changed AMD-K6-2/400AFX to AMD-K6-2/400AFR in Chapter 14, “Electrical Data”, Chapter 17,
“Thermal Design”, and Chapter 21, “Ordering Information” to reflect the change to the maximum
T
temperature from 65°C to 70°C. Added definition of Boundary Scan Register (BSR) for Model
CASE
8/[F:8] in Table 48 on page 229.
Added 533 MHz specifications. Changed Stop Grant, Halt, and Stop Clock power specifications in
Table 55, “Typical and Maximum Power Dissipation for OPN Suffixes AHX, 400AFQ, and AFR,” on
page 257 and Table 71, “Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR,” on
page 285.
Dec 1999
Feb 2000
I
Added 550 MHz specifications. Added MOV to/from CRx, RDMSR, RDTSC, RSM, and WRMSR
instructions to Table 14, “Integer Instructions,” on page 55. Changed mem64 to mem32 for
PUNPCKLBW, PUNPCKLWD, and PUNPCKLDQ on page 81.
J
Revision History
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Revision History
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AMD-K6 -2 Processor Data Sheet
®
1
AMD-K6 -2 Processor
®
■ Advanced 6-Issue RISC86 Superscalar Microarchitecture
◆
◆
◆
◆
◆
◆
◆
Ten parallel specialized execution units
Multiple sophisticated x86-to-RISC86 instruction decoders
Advanced two-level branch prediction
Speculative execution
Out-of-order execution
Register renaming and data forwarding
Issues up to six RISC86 instructions per clock
■ Large Internal Split 64-Kbyte Level-One (L1) Cache
◆
◆
◆
◆
32-Kbyte instruction cache with additional 20-Kbytes of predecode cache
32-Kbyte writeback dual-ported data cache
Two-way set associative
MESI protocol support
■ 3DNow!™ Technology
◆
Additional instructions to improve 3D graphics and multimedia performance
Separate multiplier and ALU for superscalar instruction execution
◆
■ Compatible with Super7™ platform
◆
Leverages high-speed 100-MHz processor bus
Accelerated Graphic Port (AGP) support
◆
■ High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit
■ High-Performance Industry-Standard MMX™ Instructions
◆
Dual integer ALU for superscalar execution
■ 321-Pin Ceramic Pin Grid Array (CPGA) Package
■ Industry-Standard System Management Mode (SMM)
■ IEEE 1149.1 Boundary Scan
■ x86 Binary Software Compatibility
®
The innovative AMD-K6 -2 processor brings industry-leading performance to PC
systems running the extensive installed base of x86 software. Its Super7™
compatible, 321-pin ceramic pin grid array (CPGA) package enables the processor to
reduce time-to-market by leveraging today’s cost-effective industry-standard
infrastructure to deliver a superior-performing PC solution.
®
Chapter 1
AMD-K6 -2 Processor
1
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
The AMD-K6-2 processor is the first to incorporate 3DNow!™ technology, a significant
innovation to the x86 processor architecture that drives today’s personal computers.
With 3DNow! technology, new, more powerful hardware and software applications
enable a more entertaining and productive PC platform. Improvements include fast
frame rates on high-resolution scenes, superior modeling of real world environments
and physics, life-like images and graphics, and big-screen sound and video.
AMD has taken a leadership role in developing new instructions that enable exciting
new levels of performance and realism. 3DNow! technology was defined and
®
implemented in collaboration with Microsoft , application developers, and graphics
vendors, and has received an enthusiastic reception. It is compatible with today’s
existing x86 software, is supported by industry-standard APIs, and requires no
operating system support, thereby enabling a broad class of applications to benefit
from 3DNow! technology.
To provide state-of-the-art performance, the processor incorporates the innovative
®
and efficient RISC86 microarchitecture, a large 64-Kbyte level-one cache (32-Kbyte
dual-ported data cache, 32-Kbyte instruction cache with an additional 20-Kbytes of
predecode cache), a powerful IEEE 754-compatible and 854-compatible floating-point
execution unit, and a high-performance industry-standard multimedia execution unit
for executing MMX™ instructions. The processor includes additional
high-performance Single Instruction Multiple Data (SIMD) execution resources to
support the 3DNow! technology. These techniques have been combined to deliver
leading-edge performance on leading consumer and business applications in both the
®
®
Microsoft Windows 98 and Windows NT operating environments.
The AMD-K6-2 processor’s 6-issue RISC86 microarchitecture is a decoupled
decode/execution superscalar design that implements state-of-the-art design
techniques to achieve leading-edge performance. Advanced design techniques
implemented in the AMD-K6-2 processor include multiple x86 instruction decode,
single-clock internal RISC operations, ten execution units that support superscalar
operation, out-of-order execution, data forwarding, speculative execution, and
register renaming. In addition, the processor supports advanced branch prediction
logic by implementing an 8192-entry branch history table, a branch target cache, and
a return address stack, which combine to deliver better than a 95% prediction rate.
These design techniques enable the AMD-K6-2 processor to issue, execute, and retire
multiple x86 instructions per clock, resulting in excellent scaleable performance.
The AMD-K6-2 processor is x86 binary code compatible. AMD’s extensive experience
through six generations of x86 processors has been carefully integrated into the
processor to enable compatibility with Windows 98, Windows 95, Windows 3.x,
®
Windows NT, DOS, OS/2, Unix, Solaris, NetWare , Vines, and other leading x86
operating systems and applications. The AMD-K6-2 processor is Super7 and
Socket 7-compatible. The Super7 platform is an extension to today’s popular and
®
2
AMD-K6 -2 Processor
Chapter 1
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
robust Socket 7 platform. See “Super7™ Platform Initiative” on page 3 for more
information.
AMD is the world’s second-leading supplier of Windows-compatible PC processors,
having shipped more than 120 million x86 microprocessors, including more than 60
million Windows-compatible processors. With its combination of state-of-the-art
features, industry-leading performance, high-performance 3DNow! technology and
multimedia engines, x86 compatibility, and low-cost infrastructure, the AMD-K6-2 is
the superior choice for mainstream personal computers.
1.1
Super7™ Platform Initiative
AMD and its industry partners launched the Super7 platform initiative in order to
maintain the competitive vitality of the Socket 7 infrastructure through a series of
enhancements, including the development of an industry-standard, 100-MHz
processor bus protocol.
In addition to the 100-MHz processor bus protocol, the Super7 initiative includes the
introduction of chipsets that support the AGP specification, and support for a
backside L2 cache and frontside L3 cache. Currently, over 40 motherboard vendors
and all major BIOS and chipset vendors offer Super7 platform-based products.
Super7™ Platform Enhancements
The Super7 platform has the following enhancements:
■ 100-MHz processor bus—The AMD-K6-2 processor supports a 100-MHz, 800
Mbyte/second frontside bus to provide a high-speed interface to Super7
platform-based chipsets. The 100-MHz interface to the frontside Level 2 (L2)
cache and main system memory speeds up access to the frontside cache and main
memory by 50 percent over the 66-MHz Socket 7 interface—resulting in a
significant increase of 10% in overall system performance.
■ Accelerated graphics port support—AGP improves the performance of mid-range
PCs that have small amounts of video memory on the graphics card. The
industry-standard AGP specification enables a 133-MHz graphics interface and
will scale to even higher levels of performance.
■ Support for backside L2 and frontside L3 cache—The Super7 platform has the
‘headroom’ to support higher-performance AMD-K6 processors, with clock speeds
scaling to 550 MHz and beyond. The Super7 platform also supports the
AMD-K6-III processor which features a full-speed, internal backside 256-Kbyte L2
cache designed to enable new levels of performance to leading-edge desktop
systems. This processor also supports an optional 100-MHz external L3 cache for
even higher-performance system configurations.
®
Chapter 1
AMD-K6 -2 Processor
3
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Super7™ Platform Advantages
The Super7 platform has the following advantages:
■ Delivers performance and features competitive with alternate platforms at the
same clock speed, and at a significantly lower cost
■ Takes advantage of existing system designs for superior value
■ Enables OEMs and resellers to take advantage of mature, high-volume
infrastructure supported by multiple BIOS, chipset, graphics, and motherboard
suppliers
■ Reduces inventory and design costs with one motherboard for a wide range of
products
■ Builds on a huge installed base of more than 100 million motherboards
■ Provides an easy upgrade path for future PC users, as well as a bridge to legacy
users
By taking advantage of the low-cost, mature Socket 7 infrastructure, the Super7
platform will continue to provide superior value and leading-edge performance for
desktop PC systems.
®
4
AMD-K6 -2 Processor
Chapter 1
Preliminary Information
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
2
Internal Architecture
2.1
Introduction
The AMD-K6-2 processor implements advanced design
techniques known as the RISC86 microarchitecture. The RISC86
microarchitecture is a decoupled decode/execution design
approach that yields superior sixth-generation performance for
x86-based software. This chapter describes the techniques used
and the functional elements of the RISC86 microarchitecture.
2.2
AMD-K6®-2 Processor Microarchitecture Overview
When discussing processor design, it is important to understand
the terms architecture, microarchitecture, and design
implementation. The term architecture refers to the instruction
set and features of a processor that are visible to software
programs running on the processor. The architecture
determines what software the processor can run. The
architecture of the AMD-K6-2 processor is the
industry-standard x86 instruction set.
The term microarchitecture refers to the design techniques used
in the processor to reach the target cost, performance, and
functionality goals. The AMD-K6 family of processors are based
on a sophisticated RISC core known as the Enhanced RISC86
microarchitecture. The Enhanced RISC86 microarchitecture is
an advanced, second-order decoupled decode/execution design
approach that enables industry-leading performance for
x86-based software.
The term design implementation refers to the actual logic and
circuit designs from which the processor is created according to
the microarchitecture specifications.
Chapter 2
Internal Architecture
5
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
®
Enhanced RISC86
Microarchitecture
The Enhanced RISC86 microarchitecture defines the
characteristics of the AMD-K6 family. The innovative RISC86
microarchitecture approach implements the x86 instruction set
by internally translating x86 instructions into RISC86
operations. These RISC86 operations were specially designed to
include direct support for the x86 instruction set while
observing the RISC performance principles of fixed length
encoding, regularized instruction fields, and a large register
set. The Enhanced RISC86 microarchitecture used in the
AMD-K6-2 processor enables higher processor core
performance and promotes straightforward extensions, such as
those added in the current AMD-K6-2 processor and those
planned for the future. Instead of directly executing complex
x86 instructions, which have lengths of 1 to 15 bytes, the
AMD-K6-2 processor executes the simpler and easier
fixed-length RISC86 operations, while maintaining the
instruction coding efficiencies found in x86 programs.
The AMD-K6-2 processor contains parallel decoders, a
centralized RISC86 operation scheduler, and ten execution
units that support superscalar operation—multiple decode,
execution, and retirement—of x86 instructions. These elements
are packed into an aggressive and highly efficient six-stage
pipeline.
®
AMD-K6 -2 Processor Block Diagram. As shown in Figure 1 on page
7, the high-performance, out-of-order execution engine of the
AMD-K6-2 processor is mated to a split level-one 64-Kbyte
writeback cache with 32 Kbytes of instruction cache and 32
Kbytes of data cache. The instruction cache feeds the decoders
and, in turn, the decoders feed the scheduler. The ICU issues
and retires RISC86 operations contained in the scheduler. The
system bus interface is an industry-standard 64-bit Super7 and
Socket 7 demultiplexed bus.
The AMD-K6-2 processor combines the latest in processor
microarchitecture to provide the highest x86 performance for
today’s personal computers. The AMD-K6-2 processor offers
true sixth-generation performance and x86 binary software
compatibility.
6
Internal Architecture
Chapter 2
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
32-KByte Level-One Instruction Cache
20-KByte Predecode Cache
Predecode
Logic
64-Entry ITLB
16-Byte Fetch
Level-One Cache
Controller
Branch Logic
(8192-Entry BHT)
(16-Entry BTC)
(16-Entry RAS)
Multiple Instruction Decoders
x86 to RISC86
Four RISC86
Decode
100 MHz
Super7™
Bus
Out-of-Order
Scheduler
Execution Engine
Instruction
Control Unit
Buffer
Interface
(24 RISC86)
Six RISC86 ®
Operation Issue
Register X Functional Units
Integer/
Multimedia/3DNow!
Register Y Functional Units
Integer/
Multimedia /3DNow!
Load
Unit
Store
Unit
Branch
Unit
FPU
Store
Queue
32-KByte Level-One Dual-Port Data Cache
128-Entry DTLB
®
Figure 1. AMD-K6 -2 Processor Block Diagram
Decoders. Decoding of the x86 instructions begins when the
on-chip instruction cache is filled. Predecode logic determines
the length of an x86 instruction on a byte-by-byte basis. This
predecode information is stored, along with the x86
instructions, in the instruction cache, to be used later by the
decoders. The decoders translate on-the-fly, with no additional
latency, up to two x86 instructions per clock into RISC86
operations.
Note: In this chapter, “clock” refers to a processor clock.
The AMD-K6-2 processor categorizes x86 instructions into three
types of decodes—short, long, and vector. The decoders process
either two short, one long, or one vector decode at a time. The
three types of decodes have the following characteristics:
■ Short decodes—x86 instructions less than or equal to seven
bytes in length
■ Long decodes—x86 instructions less than or equal to 11
bytes in length
■ Vector decodes—complex x86 instructions
Chapter 2
Internal Architecture
7
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Short and long decodes are processed completely within the
decoders. Vector decodes are started by the decoders and then
completed by fetched sequences from an on-chip ROM. After
decoding, the RISC86 operations are delivered to the scheduler
for dispatching to the executions units.
Scheduler/Instruction Control Unit. The centralized scheduler or
buffer is managed by the Instruction Control Unit (ICU). The
ICU buffers and manages up to 24 RISC86 operations at a time.
This equals from 6 to 12 x86 instructions. This buffer size (24) is
perfectly matched to the processor’s six-stage RISC86 pipeline
and four RISC86-operations decode rate. The scheduler accepts
as many as four RISC86 operations at a time from the decoders
and retires up to four RISC86 operations per clock cycle. The
ICU is capable of simultaneously issuing up to six RISC86
operations at a time to the execution units. This consists of the
following types of operations:
■ Memory load operation
■ Memory store operation
■ Complex integer, MMX or 3DNow! register operation
■ Simple integer, MMX or 3DNow! register operation
■ Floating-point register operation
■ Branch condition evaluation
Registers. When managing the 24 RISC86 operations, the ICU
uses 69 physical registers contained within the RISC86
microarchitecture. 48 of the physical registers are located in a
general register file and are grouped as 24 committed or
architectural registers plus 24 rename registers. The 24
architectural registers consist of 16 scratch registers and 8
registers that correspond to the x86 general-purpose registers—
EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. There is an
analogous set of registers specifically for MMX and 3DNow!
operations. There are 9 MMX/3DNow! committed or
architectural registers plus 12 MMX/3DNow! rename registers.
The 9 architectural registers consist of one scratch register and
8 registers that correspond to the MMX registers (mm0–mm7),
as shown in Figure 17 on page 29.
Branch Logic. The AMD-K6-2 processor is designed with highly
sophisticated dynamic branch logic consisting of the following:
■ Branch history/Prediction table
■ Branch target cache
■ Return address stack
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The AMD-K6-2 processor implements a two-level branch
prediction scheme based on an 8192-entry branch history table.
The branch history table stores prediction information that is
used for predicting conditional branches. Because the branch
history table does not store predicted target addresses, special
address ALUs calculate target addresses on-the-fly during
instruction decode. The branch target cache augments
predicted branch performance by avoiding a one clock
cache-fetch penalty. This specialized target cache does this by
supplying the first 16 bytes of target instructions to the
decoders when branches are predicted. The return address
stack is a unique device specifically designed for optimizing
CALL and RETURN pairs. In summary, the AMD-K6-2
processor uses dynamic branch logic to minimize delays due to
the branch instructions that are common in x86 software.
3DNow!™ Technology. AMD has taken a lead role in improving the
multimedia and 3D capabilities of the x86 processor family with
the introduction of 3DNow! technology, which uses a packed,
single-precision, floating-point data format and Single
Instruction Multiple Data (SIMD) operations based on the
MMX technology model.
2.3
Cache, Instruction Prefetch, and Predecode Bits
The writeback level-one cache on the AMD-K6-2 processor is
organized as a separate 32-Kbyte instruction cache and a
32-Kbyte data cache with two-way set associativity. The cache
line size is 32 bytes and lines are prefetched from main memory
using an efficient pipelined burst transaction. As the
instruction cache is filled, each instruction byte is analyzed for
instruction boundaries using predecoding logic. Predecoding
annotates information (5 bits per byte) to each instruction byte
that later enables the decoders to efficiently decode multiple
instructions simultaneously.
Cache
The processor cache design takes advantage of a sectored
organization (see Figure 2 on page 10). Each sector consists of
64 bytes configured as two 32-byte cache lines. The two cache
lines of a sector share a common tag but have separate pairs of
MESI (Modified, Exclusive, Shared, Invalid) bits that track the
state of each cache line.
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Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill. In the case
of a tag-miss cache fill, the miss is due to a tag mismatch, in
which case the required cache line is filled from external
memory, and the cache line within the sector that was not
required is marked as invalid. In the case of a tag-hit cache fill,
the address matches the tag, but the requested cache line is
marked as invalid. The required cache line is filled from
external memory, and the cache line within the sector that is
not required remains in the same cache state.
Prefetching
The AMD-K6-2 processor conditionally performs cache
prefetching which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
pipelined cycles.
The 3DNow! technology includes an instruction called
PREFETCH that allows a cache line to be prefetched into the
data cache. The PREFETCH instruction format is defined in
Table 17, “3DNow!™ Instructions,” on page 81. For more
detailed information, see the 3DNow!™ Technology Manual,
order# 21928.
Predecode Bits
Decoding x86 instructions is particularly difficult because the
instructions are variable-length and can be from 1 to 15 bytes
long. Predecode logic supplies the five predecode bits that are
associated with each instruction byte. The predecode bits
indicate the number of bytes to the start of the next x86
instruction. The predecode bits are stored in an extended
instruction cache alongside each x86 instruction byte as shown
in Figure 2. The predecode bits are passed with the instruction
bytes to the decoders where they assist with parallel x86
instruction decoding.
Tag
Address
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Figure 2. Cache Sector Organization
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2.4
Instruction Fetch and Decode
Instruction Fetch
The processor can fetch up to 16 bytes per clock out of the
instruction cache or branch target cache. The fetched
information is placed into a 16-byte instruction buffer that
feeds directly into the decoders (see Figure 3). Fetching can
occur along a single execution stream with up to seven
outstanding branches taken.
The instruction fetch logic is capable of retrieving any 16
contiguous bytes of information within a 32-byte boundary.
There is no additional penalty when the 16 bytes of instructions
lie across a cache line boundary. The instruction bytes are
loaded into the instruction buffer as they are consumed by the
decoders. Although instructions can be consumed with byte
granularity, the instruction buffer is managed on a
memory-aligned word (two bytes) organization. Therefore,
instructions are loaded and replaced with word granularity.
When a control transfer occurs—such as a JMP instruction—
the entire instruction buffer is flushed and reloaded with a new
set of 16 instruction bytes.
Branch-Target Cache
16 Bytes
16 x 16 Bytes
32-Kbyte Level-One
Instruction Cache
16 Bytes
2:1
Branch Target
Address Adders
Return Address Stack
16 x 16 Bytes
Fetch Unit
16 Instruction Bytes
plus
16 Sets of Predecode Bits
Instruction Buffer
Figure 3. The Instruction Buffer
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Instruction Decode
The AMD-K6-2 processor decode logic is designed to decode
multiple x86 instructions per clock (see Figure 4). The decode
logic accepts x86 instruction bytes and their predecode bits
from the instruction buffer, locates the actual instruction
boundaries, and generates RISC86 operations from these x86
instructions.
RISC86 operations are fixed-length internal instructions. Most
RISC86 operations execute in a single clock. RISC86 operations
are combined to perform every function of the x86 instruction
set. Some x86 instructions are decoded into as few as zero
RISC86 operations—for instance a NOP—or one RISC86
operation—a register-to-register add. More complex x86
instructions are decoded into several RISC86 operations.
Instruction Buffer
Short Decoder #1
Short Decoder #2
Long Decoder
On-Chip ROM
Vector Decoder
RISC86® Sequencer
Vector Address
4 RISC86 Operations
®
Figure 4. AMD-K6 -2 Processor Decode Logic
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The AMD-K6-2 processor uses a combination of decoders to
convert x86 instructions into RISC86 operations. The hardware
consists of three sets of decoders—two parallel short decoders,
one long decoder, and one vector decoder. The two parallel
short decoders translate the most commonly-used x86
instructions (moves, shifts, branches, ALU, FPU) and the
extensions to the x86 instruction set (including MMX and
3DNow! instructions) into zero, one, or two RISC86 operations
each. The short decoders only operate on x86 instructions that
are up to seven bytes long. In addition, they are designed to
decode up to two x86 instructions per clock. The
commonly-used x86 instructions that are greater than seven
bytes but not more than 11 bytes long, and semi-commonly-used
x86 instructions that are up to seven bytes long are handled by
the long decoder.
The long decoder only performs one decode per clock and
generates up to four RISC86 operations. All other translations
(complex instructions, serializing conditions, interrupts and
exceptions, etc.) are handled by a combination of the vector
decoder and RISC86 operation sequences fetched from an
on-chip ROM. For complex operations, the vector decoder logic
provides the first set of RISC86 operations and a vector (initial
ROM address) to a sequence of further RISC86 operations. The
same types of RISC86 operations are fetched from the ROM as
those that are generated by the hardware decoders.
Note: Although all three sets of decoders are simultaneously fed a
copy of the instruction buffer contents, only one of the three
types of decoders is used during any one decode clock.
The decoders or the on-chip RISC86 ROM always generate a
group of four RISC86 operations. For decodes that cannot fill the
entire group with four RISC86 operations, RISC86 NOP
operations are placed in the empty locations of the grouping. For
example, a long-decoded x86 instruction that converts to only
three RISC86 operations is padded with a single RISC86 NOP
operation and then passed to the scheduler. Up to six groups or
24 RISC86 operations can be placed in the scheduler at a time.
All of the common, and a few of the uncommon, floating-point
instructions (also known as ESC instructions) are hardware
decoded as short decodes. This decode generates a RISC86
floating-point operation and, optionally, an associated
floating-point load or store operation. Floating-point or ESC
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instruction decode is only allowed in the first short decoder, but
non-ESC instructions can be decoded simultaneously by the
second short decoder along with an ESC instruction decode in
the first short decoder.
All of the MMX and 3DNow! instructions, with the exception of
the EMMS, FEMMS, and PREFETCH instructions, are
hardware decoded as short decodes. The MMX instruction
decode generates a RISC86 MMX operation and, optionally, an
associated MMX load or store operation. A 3DNow! instruction
decode generates a RISC86 3DNow! operation and, optionally,
an associated load or store operation. MMX and 3DNow!
instructions can be decoded in either or both of the short
decoders.
2.5
Centralized Scheduler
The scheduler is the heart of the AMD-K6-2 processor (see
Figure 5 on page 15). It contains the logic necessary to manage
out-of-order execution, data forwarding, register renaming,
simultaneous issue and retirement of multiple RISC86
operations, and speculative execution. The scheduler’s buffer
can hold up to 24 RISC86 operations. This equates to a maximum
of 12 x86 instructions. The scheduler can issue RISC86
operations from any of the 24 locations in the buffer. When
possible, the scheduler can simultaneously issue a RISC86
operation to any available execution unit (store, load, branch,
register X integer/multimedia, register Y integer/multimedia, or
floating-point). In total, the scheduler can issue up to six and
retire up to four RISC86 operations per clock.
The main advantage of the scheduler and its operation buffer is
the ability to examine an x86 instruction window equal to 12
x86 instructions at one time. This advantage is due to the fact
that the scheduler operates on the RISC86 operations in
parallel and allows the AMD-K6-2 processor to perform
dynamic on-the-fly instruction code scheduling for optimized
execution. Although the scheduler can issue RISC86 operations
for out-of-order execution, it always retires x86 instructions in
order.
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From Decode Logic
RISC86 #0
RISC86 #3
RISC86 #1
RISC86 #2
Centralized RISC86®
Operation Scheduler
RISC86 Issue Buses
RISC86 Operation Buffer
®
Figure 5. AMD-K6 -2 Processor Scheduler
2.6
Execution Units
The AMD-K6-2 processor contains ten parallel execution
units—store, load, integer X ALU, integer Y ALU, MMX ALU
(X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU,
floating-point, and branch condition. Each unit is independent
and capable of handling the RISC86 operations. Table 1 on
page 16 details the execution units, functions performed within
these units, operation latency, and operation throughput.
The store and load execution units are two-stage pipelined
designs. The store unit performs data writes and register
calculation for LEA/PUSH. Data memory and register writes
from stores are available after one clock. Store operations are
held in a store queue prior to execution. From there, they
execute in order. The load unit performs data memory reads.
Data is available from the load unit after two clocks.
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The Integer X execution unit can operate on all ALU
operations, multiplies, divides (signed and unsigned), shifts,
and rotates.
The Integer Y execution unit can operate on the basic word and
doubleword ALU operations—ADD, AND, CMP, OR, SUB,
XOR, zero-extend and sign-extend operands.
Table 1. Execution Latency and Throughput of Execution Units
Functional Unit
Store
Function
LEA/PUSH, Address (Pipelined)
Memory Store (Pipelined)
Memory Loads (Pipelined)
Integer ALU
Latency Throughput
1
1
1
1
Load
2
1
1
1
Integer X
Integer Multiply
2–3
1
2–3
1
Integer Shift
MMX ALU
1
1
Multimedia
(processes
MMX instructions)
MMX Shifts, Packs, Unpack
MMX Multiply
1
1
2
1
Integer Y
Branch
FPU
Basic ALU (16-bit and 32-bit operands)
Resolves Branch Conditions
FADD, FSUB, FMUL
3DNow! ALU
1
1
1
1
2
2
2
1
3DNow!
3DNow! Multiply
2
1
3DNow! Convert
2
1
Register X and Y
Pipelines
The functional units that execute MMX and 3DNow!
instructions share pipeline control with the Integer X and
Integer Y units.
The register X and Y functional units are attached to the issue
bus for the register X execution pipeline or the issue bus for the
register Y execution pipeline or both. Each register pipeline
has dedicated resources that consist of an integer execution
unit and an MMX ALU execution unit, therefore allowing
superscalar operation on integer and MMX instructions. In
addition, both the X and Y issue buses are connected to the
3DNow! ALU, the MMX/3DNow! multiplier and MMX shifter,
which allows the appropriate RISC86 operation to be issued
through either bus. Figure 6 on page 17 shows the details of the
X and Y register pipelines.
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Scheduler
Buffer
(24 RISC86® Operations)
Issue Bus
for the
Register X
Execution
Pipeline
Issue Bus
for the
Register Y
Execution
Pipeline
Integer X
MMX
ALU
MMX
Shifter
3DNow!
ALU
MMX
ALU
Integer Y
MMX/
3DNow!
Multiplier
ALU
ALU
Figure 6. Register X and Y Functional Units
The branch condition unit is separate from the branch
prediction logic in that it resolves conditional branches such as
JCC and LOOP after the branch condition has been evaluated.
2.7
Branch-Prediction Logic
Sophisticated branch logic that can minimize or hide the impact
of changes in program flow is designed into the AMD-K6-2
processor. Branches in x86 code fit into two categories—
unconditional branches, which always change program flow (that
is, the branches are always taken) and conditional branches,
which may or may not divert program flow (that is, the branches
are taken or not-taken). When a conditional branch is not taken,
the processor simply continues decoding and executing the next
instructions in memory.
Typical applications have up to 10% of unconditional branches
and another 10% to 20% conditional branches. The AMD-K6-2
processor branch logic has been designed to handle this type of
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program behavior and its negative effects on instruction
execution, such as stalls due to delayed instruction fetching and
the draining of the processor pipeline. The branch logic
contains an 8192-entry branch history table, a 16-entry by
16-byte branch target cache, a 16-entry return address stack,
and a branch execution unit.
Branch History Table
The AMD-K6-2 processor handles unconditional branches
without any penalty by redirecting instruction fetching to the
target address of the unconditional branch. However,
conditional branches require the use of the dynamic
branch-prediction mechanism built into the AMD-K6-2
processor. A two-level adaptive history algorithm is
implemented in an 8192-entry branch history table. This table
stores executed branch information, predicts individual
branches, and predicts the behavior of groups of branches. To
accommodate the large branch history table, the AMD-K6-2
processor does not store predicted target addresses. Instead,
the branch target addresses are calculated on-the-fly using
ALUs during the decode stage. The adders calculate all
possible target addresses before the instructions are fully
decoded and the processor chooses which addresses are valid.
Branch Target Cache
Return Address Stack
To avoid a one clock cache-fetch penalty when a branch is
predicted taken, a built-in branch target cache supplies the first
16 bytes of instructions directly to the instruction buffer
(assuming the target address hits this cache). (See Figure 3 on
page 11.) The branch target cache is organized as 16 entries of
16 bytes. In total, the branch prediction logic achieves branch
prediction rates greater than 95%.
The return address stack is a special device designed to
optimize CALL and RET pairs. Software is typically compiled
with subroutines that are frequently called from various places
in a program. This is usually done to save space. Entry into the
subroutine occurs with the execution of a CALL instruction. At
that time, the processor pushes the address of the next
instruction in memory following the CALL instruction onto the
stack (allocated space in memory). When the processor
encounters a RET instruction (within or at the end of the
subroutine), the branch logic pops the address from the stack
and begins fetching from that location. To avoid the latency of
main memory accesses during CALL and RET operations, the
return address stack caches the pushed addresses.
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Branch Execution
Unit
The branch execution unit enables efficient speculative
execution. This unit gives the processor the ability to execute
instructions beyond conditional branches before knowing
whether the branch prediction was correct. The AMD-K6-2
processor does not permanently update the x86 registers or
memory locations until all speculatively executed conditional
branch instructions are resolved. When a prediction is
incorrect, the processor backs out to the point of the
mispredicted branch instruction and restores all registers. The
AMD-K6-2 processor can support up to seven outstanding
branches.
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3
Software Environment
This chapter provides a general overview of the AMD-K6-2
processor’s x86 software environment and briefly describes the
data types, registers, operating modes, interrupts, and
instructions supported by the AMD-K6-2 architecture and
design implementation.
The stepping of the Model 8 determines the implementation
and format of five Model-Specific Registers (MSRs). This
document covers the following two stepping ranges of the
AMD-K6-2 processor:
■ Model 8/[7:0] is any of eight possible model/steppings—
Models 8/0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, or 8/7. Model 8/[7:0]
implements seven MSRs, and the bits and fields within these
seven MSRs are defined identically.
■ Model 8/[F:8] is any of eight possible model/steppings—
Models 8/8, 8/9, 8/A, 8/B, 8/C, 8/D, 8/E, or 8/F. Model 8/[F:8]
implements the same seven MSRs as the Model 8/[7:0], but
the bits and fields within two of these MSRs are not defined
identically. Also, Model 8/[F:8] supports three additional
MSRs for a total of ten MSRs.
The name AMD-K6-2 processor by itself refers to all steppings of
®
the Model 8. See “AMD-K6 -2 Processor Model 8/[F:8]
Registers” on page 50 for the MSRs that are implemented only
on the Model 8/[F:8].
3.1
Registers
The AMD-K6-2 processor contains all the registers defined by
the x86 architecture, including general-purpose, segment,
floating-point, MMX/3DNow!, EFLAGS, control, task, debug,
test, and descriptor/memory-management registers. In
addition, this chapter provides information on the AMD-K6-2
processor MSRs.
Note: Areas of the register designated as Reserved should not be
modified by software.
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General-Purpose
Registers
The eight 32-bit x86 general-purpose registers are used to hold
integer data or memory pointers used by instructions. Table 2
contains a list of the general-purpose registers and the
functions for which they are used.
Table 2. General-Purpose Registers
Register
EAX
EBX
Function
Commonly used as an accumulator
Commonly used as a pointer
ECX
Commonly used for counting in loop operations
Commonly used to hold I/O information and to pass parameters
Commonly used as a destination pointer by the ES segment
Commonly used as a source pointer by the DS segment
Used to point to the stack segment
EDX
EDI
ESI
ESP
EBP
Used to point to data within the stack segment
In order to support byte and word operations, EAX, EBX, ECX,
and EDX can also be used as 8-bit and 16-bit registers. The
shorter registers are overlaid on the longer ones. For example,
the name of the 16-bit version of EAX is AX (low 16 bits of
EAX) and the 8-bit names for AX are AH (high order bits) and
AL (low order bits). The same naming convention applies to
EBX, ECX, and EDX. EDI, ESI, ESP, and EBP can be used as
smaller 16-bit registers called DI, SI, SP, and BP respectively,
but these registers do not have 8-bit versions. Figure 7 shows the
EAX register with its name components, and Table 3 lists the
doubleword (32-bit) general-purpose registers and their
corresponding word (16-bit) and byte (8-bit) versions.
31
16 15
8
7
0
EAX
AX
AL
AH
Figure 7. EAX Register with 16-Bit and 8-Bit Name Components
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Table 3. General-Purpose Register Doubleword, Word, and Byte Names
32-Bit Name
(Doubleword)
16-Bit Name
(Word)
8-Bit Name
(High-order Bits) (Low-order Bits)
8-Bit Name
EAX
EBX
ECX
EDX
EDI
ESI
AX
BX
CX
DX
DI
AH
BH
CH
DH
–
AL
BL
CL
DL
–
SI
–
–
ESP
EBP
SP
BP
–
–
–
–
Integer Data Types
Four types of data are used in general-purpose registers—byte,
word, doubleword, and quadword integers. Figure 8 shows the
format of the integer data registers.
Byte Integer
7
0
Precision —
8 Bits
Word Integer
15
0
Precision — 16 Bits
Doubleword Integer
31
0
Precision — 32 Bits
Quadword Integer
63
0
Precision — 64 Bits
Figure 8. Integer Data Registers
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Segment Registers
The six 16-bit segment registers are used as pointers to areas
(segments) of memory. Table 4 lists the segment registers and
their functions. Figure 9 shows the format for all six segment
registers.
Table 4. Segment Registers
Segment
Segment Register Function
Register
CS
DS
ES
FS
GS
SS
Code segment, where instructions are located
Data segment, where data is located
Data segment, where data is located
Data segment, where data is located
Data segment, where data is located
Stack segment
15
0
Figure 9. Segment Register
Segment Usage
The operating system determines the type of memory model
that is implemented. The segment register usage is determined
by the operating system’s memory model. In a Real mode
memory model the segment register points to the base address
in memory. In a Protected mode memory model the segment
register is called a selector and it selects a segment descriptor
in a descriptor table. This descriptor contains a pointer to the
base of the segment, the limit of the segment, and various
protection attributes. For more information on descriptor
formats, see “Descriptors and Gates” on page 46. Figure 10 on
page 25 shows segment usage for Real mode and Protected
mode memory models.
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Physical Memory
Segment Base
Segment Register
Real Mode Memory Model
Descriptor Table
Physical Memory
Base
Limit
Base
Base
Limit
Segment Base
Segment Selector
Protected Mode Memory Model
Figure 10. Segment Usage
Instruction Pointer
The instruction pointer (EIP or IP) is used in conjunction with
the code segment register (CS). The instruction pointer is
either a 32-bit register (EIP) or a 16-bit register (IP) that keeps
track of where the next instruction resides within memory. This
register cannot be directly manipulated, but can be altered by
modifying return pointers when a JMP or CALL instruction is
used.
Floating-Point
Registers
The floating-point execution unit in the AMD-K6-2 processor is
designed to perform mathematical operations on non-integer
numbers. This floating-point unit conforms to the IEEE 754 and
854 standards and uses several registers to meet these
standards—eight numeric floating-point registers, a status
word register, a control word register, and a tag word register.
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The eight floating-point registers are physically 80 bits wide
and labeled FPR0–FPR7. Figure 11 shows the format of these
floating-point registers. See “Floating-Point Register Data
Types” on page 28 for information on allowable floating-point
data types.
79 78
Sign
64 63
0
Exponent
Significand
Figure 11. Floating-Point Register
The 16-bit FPU status word register contains information about
the state of the floating-point unit. Figure 12 shows the format
of this register.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
C
2
C
1
C
0
E
S
S
F
P
E
U
E
O
E
Z
E
I
E
C
3
D
E
B
TOSP
Symbol
B
C3
TOSP
C2
C1
C0
ES
SF
Description
FPU Busy
Bits
15
14
13–11
10
9
8
7
6
Condition Code
Top of Stack Pointer
Condition Code
Condition Code
Condition Code
Error Summary Status
Stack Fault
Exception Flags
Precision Error
Underflow Error
Overflow Error
Zero Divide Error
Denormalized Operation Error 1
Invalid Operation Error
TOSP Information
000 = FPR0
PE
UE
OE
ZE
DE
IE
5
4
3
2
0
111 = FPR7
Figure 12. FPU Status Word Register
26
Software Environment
Chapter 3
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
The FPU control word register allows a programmer to manage
the FPU processing options. Figure 13 shows the format of this
register.
15 14 13 12 11 10
9
8
7
6
5
P
4
3
2
Z
1
0
Y
R
C
P
C
U
O
I
M
D
M
M M M M
Reserved
Symbol
Description
Bits
Y
Infinity Bit (80287 compatibility) 12
RC
PC
Rounding Control
Precision Control
Exception Masks
Precision
Underflow
Overflow
Zero Divide
Denormalized Operation
Invalid Operation
11–10
9–8
PM
UM
OM
ZM
DM
IM
5
4
3
2
1
0
Rounding Control Information
00b = Round to the nearest or even number
01b = Round down toward negative infinity
10b = Round up toward positive infinity
11b = Truncate toward zero
Precision Control Information
00b = 24 bits Single Precision Real
01b = Reserved
10b = 53 bits Double Precision Real
11b = 64 bits Extended Precision Real
Figure 13. FPU Control Word Register
The FPU tag word register contains information about the
registers in the register stack. Figure 14 shows the format of this
register.
15
14 13
12 11
10 9
8 7
6 5
4 3
2 1
0
TAG
(FPR7)
TAG
TAG
TAG
TAG
TAG
TAG
TAG
(FPR6) (FPR5) (FPR4) (FPR3) (FPR2) (FPR1) (FPR0)
Tag Values
00 = Valid
01 = Zero
10 = Special
11 = Empty
Figure 14. FPU Tag Word Register
Chapter 3
Software Environment
27
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Floating-Point
Register Data Types
Floating-point registers use four different types of data—
packed decimal, single-precision real, double-precision real,
and extended-precision real. Figures 15 and 16 show the
formats for these registers.
79 78 72 71
0
Ignore
or
S
Precision — 18 Digits, 72 Bits Used, 4-Bits/Digit
Zero
Description
Ignored on Load, Zeros on Store 78-72
Sign Bit 79
Bits
Figure 15. Packed Decimal Data Register
31 30
23 22
0
Single-Precision Real
Biased
Exponent
Significand
S
S= Sign Bit
Double-Precision Real
63 62
S
52 51
0
Biased
Exponent
Significand
S = Sign Bit
Extended-Precision Real
79 78
S
64 63 62
0
Biased
Exponent
I
Significand
S= Sign Bit
I = Integer Bit
Figure 16. Precision Real Data Registers
28
Software Environment
Chapter 3
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
MMX™/3DNow!™
Registers
The AMD-K6-2 processor implements eight 64-bit
MMX/3DNow! registers for use by multimedia software. These
registers are mapped on the floating-point register stack. The
MMX and 3DNow! instructions refer to these registers as mm0
to mm7. Figure 17 shows the format of these registers. For more
®
information, see the AMD-K6 Processor Multimedia Technology
Manual, order# 20726 and the 3DNow!™ Technology Manual,
order# 21928.
63
0
mm0
mm1
mm2
mm3
mm4
mm5
mm6
mm7
Figure 17. MMX™/3DNow!™ Registers
MMX™ Data Types
For the MMX instructions, the MMX registers use three types of
data—packed eight-byte integer, packed quadword integer, and
packed dual doubleword integer. Figure 18 on page 30 shows
the format of these data types.
Chapter 3
Software Environment
29
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Packed Bytes Integer
63
56 55
48 47
40 39
32 31
32 31
32 31
24 23
16 15
8
7
0
0
0
Byte 7
Byte 6
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Byte 0
Packed Words Integer
63
48 47
16 15
Word 3
Word 2
Word 1
Word 0
Packed Doubleword Integer
63
Doubleword 1
Doubleword 0
Figure 18. MMX™ Data Types
3DNow!™ Data Types
For 3DNow! instructions, the MMX/3DNow! registers use
packed single-precision real data. Figure 19 shows the format of
the 3DNow! data type.
Packed Single Precision Floating Point
0
63 62
S
55 54
Biased
32 31 30
23 22
Biased
Exponent
S
Significand
Significand
Exponent
S = Sign Bit
S = Sign Bit
Figure 19. 3DNow!™ Data Types
30
Software Environment
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
EFLAGS Register
The EFLAGS register provides for three different types of
flags—system, control, and status. The system flags provide
operating system controls, the control flag provides directional
information for string operations, and the status flags provide
information resulting from logical and arithmetic operations.
Figure 20 shows the format of this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
I
V
I
P
V
I
F
O
P
L
I
D
A
C
V
M
R
F
N
T
O
F
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
Reserved
Symbol
ID
Description
ID Flag
Bits
21
20
19
18
17
16
14
13–12
11
10
9
VIP
VIF
AC
VM
RF
NT
IOPL
OF
DF
IF
Virtual Interrupt Pending
Virtual Interrupt Flag
Alignment Check
Virtual-8086 Mode
Resume Flag
Nested Task
I/O Privilege Level
Overflow Flag
Direction Flag
Interrupt Flag
Trap Flag
TF
8
SF
Sign Flag
7
ZF
Zero Flag
6
AF
PF
Auxiliary Flag
Parity Flag
4
2
CF
Carry Flag
0
Figure 20. EFLAGS Registers
Chapter 3
Software Environment
31
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Control Registers
The five control registers contain system control bits and
pointers. Figures 21 through 25 show the formats of these
registers.
31
7
6
5
4
3
2
1
0
M
C
E
P
S
E
T
S
D
P
V
I
V
M
E
D
E
Reserved
Symbol
MCE
PSE
Description
Machine Check Enable
Page Size Extensions
Bit
6
4
DE
TSD
PVI
Debugging Extensions
Time Stamp Disable
Protected Virtual Interrupts
Virtual-8086 Mode Extensions
3
2
1
0
VME
Figure 21. Control Register 4 (CR4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Page Directory Base
9
8
7
6
5
4
3
2
1
0
P
W
T
P
C
D
Reserved
Symbol
PCD
PWT
Description
Page Cache Disable
Page Writethrough
Bit
4
3
Figure 22. Control Register 3 (CR3)
31
0
Page Fault Linear Address
Figure 23. Control Register 2 (CR2)
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Software Environment
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
31
0
Reserved
Figure 24. Control Register 1 (CR1)
Symbol
PG
CD
Description
Paging
Cache Disable
Not Writethrough
Bit
31
30
29
NW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
P
G
C
N
A
M
W
P
N
E
E
T
T
S
E
M
M
P
P
E
D W
Reserved
Symbol
AM
WP
NE
ET
TS
EM
MP
PE
Description
Alignment Mask
Write Protect
Numeric Error
Extension Type
Task Switched
Emulation
Bit
18
16
5
4
3
2
1
0
Monitor Co-processor
Protection Enabled
Figure 25. Control Register 0 (CR0)
Chapter 3
Software Environment
33
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Debug Registers
Figures 26 through 29 show the 32-bit debug registers
supported by the processor.
Symbol
LEN 3
R/W 3
LEN 2
R/W 2
LEN 1
R/W 1
LEN 0
R/W 0
Description
Length of Breakpoint #3
Bits
31–30
Type of Transaction(s) to Trap 29–28
Length of Breakpoint #2 27–26
Type of Transaction(s) to Trap 25–24
Length of Breakpoint #1 23–22
Type of Transaction(s) to Trap 21–20
Length of Breakpoint #0 19–18
Type of Transaction(s) to Trap 17–16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G
D
G
E
L
E
G
3
L
3
L
2
L
2
G
1
L
1
G
0
L
0
LEN
3
R/W LEN R/W
LEN
1
R/W LEN
R/W
0
3
2
2
1
0
Reserved
Symbol
GD
GE
LE
Description
General Detect Enabled
Global Exact Breakpoint Enabled
Local Exact Breakpoint Enabled
Bit
13
9
8
G3
L3
G2
L2
G1
L1
G0
L0
Global Exact Breakpoint # 3 Enabled
Local Exact Breakpoint # 3 Enabled
Global Exact Breakpoint # 2 Enabled
Local Exact Breakpoint # 2 Enabled
Global Exact Breakpoint # 1 Enabled
Local Exact Breakpoint # 1 Enabled
Global Exact Breakpoint # 0 Enabled
Local Exact Breakpoint # 0 Enabled
7
6
5
4
3
2
1
0
Figure 26. Debug Register DR7
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Software Environment
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
B
D
B
S
B
3
B
2
B
1
B
0
B
T
Reserved
Symbol
BT
BS
Description
Breakpoint Task Switch
Breakpoint Single Step
Bit
15
14
BD
B3
B2
B1
B0
Breakpoint Debug Access Detected 13
Breakpoint #3 Condition Detected
Breakpoint #2 Condition Detected
Breakpoint #1 Condition Detected
Breakpoint #0 Condition Detected
3
2
1
0
Figure 27. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
Figure 28. Debug Registers DR5 and DR4
Chapter 3
Software Environment
35
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 3 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
DR2
DR1
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 2 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 1 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 0 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
Figure 29. Debug Registers DR3, DR2, DR1, and DR0
36
Software Environment
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Model-Specific
Registers (MSR)
The AMD-K6-2 processor Model 8/[7:0] provides seven MSRs.
The value in the ECX register selects the MSR to be addressed
by the RDMSR and WRMSR instructions. The values in EAX
and EDX are used as inputs and outputs by the RDMSR and
WRMSR instructions. Table 5 lists the MSRs and the
corresponding value of the ECX register. Figures 30 through 36
show the MSR formats.
®
Table 5. AMD-K6 -2 Processor Model 8/[7:0] MSRs
Model-Specific Register
Machine Check Address Register (MCAR)
Machine Check Type Register (MCTR)
Test Register 12 (TR12)
Value of ECX
00h
01h
0Eh
Time Stamp Counter (TSC)
10h
Extended Feature Enable Register (EFER)
C000_0080h
SYSCALL/SYSRET Target Address Register (STAR) C000_0081h
Write Handling Control Register (WHCR) C000_0082h
For more information about the RDMSR and WRMSR
instructions, see the AMD K86™ Family BIOS and Software Tools
Development Guide, order# 21062.
MCAR and MCTR. The AMD-K6-2 processor does not support the
generation of a machine check exception. However, the
processor does provide a 64-bit machine check address register
(MCAR), a 64-bit machine check type register (MCTR), and a
machine check enable (MCE) bit in CR4. Because the processor
does not support machine check exceptions, the contents of the
MCAR and MCTR are only affected by the WRMSR instruction
and by RESET being sampled asserted (where all bits in each
register are reset to 0).
63
0
MCAR
Figure 30. Machine-Check Address Register (MCAR)
Chapter 3
Software Environment
37
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
63
5
4
0
MCTR
Reserved
Figure 31. Machine-Check Type Register (MCTR)
Test Register 12 (TR12). Test register 12 provides a method for
disabling the L1 caches. Figure 32 shows the format of TR12.
63
4
2
1
0
3
C
I
Symbol Description
CI Cache Inhibit Bit
Bit
3
Reserved
Figure 32. Test Register 12 (TR12)
Time Stamp Counter. With each processor clock cycle, the
processor increments the 64-bit time stamp counter (TSC) MSR.
Figure 33 shows the format of the TSC.
63
0
TSC
Figure 33. Time Stamp Counter (TSC)
38
Software Environment
Chapter 3
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Extended Feature Enable Register (EFER)–Model 8[7:0]. The extended
feature enable register (EFER) contains the control bits that
enable the extended features of the AMD-K6-2 processor.
Figure 34 shows the format of the EFER register, and Table 6
defines the function of each bit in the EFER register.
Note: The EFER register as defined in the Model 8/[7:0] has
changed in the Model 8/[F:8]. See “Extended Feature Enable
Register (EFER)–Model 8/[F:8]” on page 50.
63
1
0
S
C
E
Reserved
Symbol
Description
Bit
SCE
System Call/Return Extension
0
Figure 34. Extended Feature Enable Register (EFER)–Model 8[7:0]
Table 6. Extended Feature Enable Register (EFER)–Model 8[7:0]Definition
Bit
Description
R/W
R
63–1 Reserved
0
System Call Extension (SCE)
R/W
SYSCALL/SYSRET Target Address Register (STAR).
The SYSCALL/SYSRET target address register (STAR)
contains the target EIP address used by the SYSCALL
instruction and the 16-bit code and stack segment selector
bases used by the SYSCALL and SYSRET instructions. Figure
35 shows the format of the STAR register, and Table 7 on
page 40 defines the function of each bit of the STAR register.
For more information, see the SYSCALL and SYSRET Instruction
Specification Application Note, order# 21086.
63
31
32
0
48 47
SYSRET CS Selector and SS
Selector Base
SYSCALL CS Selector and SS
Selector Base
Target EIP Address
Figure 35. SYSCALL/SYSRET Target Address Register (STAR)
Chapter 3
Software Environment
39
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 7. SYSCALL/SYSRET Target Address Register (STAR) Definition
Bit
Description
R/W
R/W
R/W
R/W
63–48 SYSRET CS and SS Selector Base
47–32 SYSCALL CS and SS Selector Base
31–0 Target EIP Address
Write Handling Control Register (WHCR)–Model 8/[7:0].
The write handling control register (WHCR) is a MSR that
contains three fields—the WCDE bit, write allocate enable
limit (WAELIM) field, and the write allocate enable
15-to-16-Mbyte (WAE15M) bit. Figure 36 shows the format of
WHCR. See “Write Allocate” on page 186 for more information.
Note: The WHCR register as defined in the Model 8/[7:0] has
changed in the Model 8/[F:8]. See “Write Handling Control
Register (WHCR)–Model 8/[F:8]” on page 51.
63
9
8
7
1
0
W
A
E
0
WAELIM
1
5
M
Reserved
Symbol
Description
Bits
WCDE
Always program to 0
8
WAELIM Write Allocate Enable Limit
7–1
WAE15M Write Allocate Enable 15-to-16-Mbyte 0
Note: Hardware RESET initializes this MSR to all zeros.
Figure 36. Write Handling Control Register (WHCR)–Model 8/[7:0]
Memory
Management
Registers
The AMD-K6-2 processor controls segmented memory
management with the registers listed in Table 8. Figure 37 on
page 41 shows the formats of these registers.
Table 8. Memory Management Registers
Register Name
Function
Global Descriptor Table Register
Contains a pointer to the base of the global descriptor table
Interrupt Descriptor Table Register Contains a pointer to the base of the interrupt descriptor table
Local Descriptor Table Register
Task Register
Contains a pointer to the local descriptor table of the current task
Contains a pointer to the task state segment of the current task
40
Software Environment
Chapter 3
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Global and Interrupt Descriptor Table Registers
47
16 15
0
32-Bit Linear Base Address
16-Bit Limit
Selector
Local Descriptor Table Register and Task Register
15
0
63
32 31
0
32-Bit Linear Base Address
32-Bit Limit
15
0
Attributes
Figure 37. Memory Management Registers
Chapter 3
Software Environment
41
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Task State Segment
Figure 38 shows the format of the task state segment (TSS).
31
0
TSS Limit
from TR
I/O Permission Bitmap (IOPB)
(up to 8 Kbytes)
Interrupt Redirection Bitmap (IRB)
(eight 32-bit locations)
Operating System
Data Structure
Base Address of IOPB
0000h
T
64h
0000h
0000h
0000h
0000h
0000h
LDT Selector
GS
FS
DS
SS
CS
0000h
0000h
ES
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
EFLAGS
EIP
CR3
SS2
0000h
0000h
0000h
0000h
ESP2
ESP1
ESP0
SS1
SS0
Link (Prior TSS Selector)
0
Figure 38. Task State Segment (TSS)
42
Software Environment
Chapter 3
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Paging
The AMD-K6-2 processor can physically address up to four
Gbytes of memory. This memory can be segmented into pages.
The size of these pages is determined by the operating system
design and the values set up in the page directory entries (PDE)
and page table entries (PTE). The processor can access both
4-Kbyte pages and 4-Mbyte pages, and the page sizes can be
intermixed within a page directory. When the page size
extension (PSE) bit in CR4 is set, the processor translates linear
addresses using either the 4-Kbyte translation lookaside buffer
(TLB) or the 4-Mbyte TLB, depending on the state of the page
size (PS) bit in the page directory entry. Figures 39 and 40 show
how 4-Kbyte and 4-Mbyte page translations work.
4-Kbyte
Page
Directory
Page
Table
Page
Frame
PTE
Physical
Address
PDE
CR3
31
22 21
12 11
0
Page Directory
Offset
Page Table
Offset
Page
Offset
Linear Address
Figure 39. 4-Kbyte Paging Mechanism
Chapter 3
Software Environment
43
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
4-Mbyte
Page
Frame
Page
Directory
Physical
Address
PDE
CR3
31
22 21
0
Page Directory
Offset
Page
Offset
Linear Address
Figure 40. 4-Mbyte Paging Mechanism
Figures 41 through 43 show the formats of the PDE and PTE.
These entries contain information regarding the location of
pages and their status.
44
Software Environment
Chapter 3
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
31
12 11 10
9
8
7
0
6
5
A
4
3
2
1
0
P
U
/
S
P
W
T
W
/
R
A
V
L
P
C
D
Page Table Base Address
Symbol
AVL
Description
Available to Software
Bits
11–9
Reserved
Page Size
Reserved
Accessed
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
8
7
6
5
4
3
2
1
0
PS
A
PCD
PWT
U/S
W/R
P
Present (valid)
Figure 41. Page Directory Entry 4-Kbyte Page Table (PDE)
31
22 21
12 11 10
9
8
7
1
6
5
A
4
3
2
1
0
P
U
/
S
P
W
T
W
/
R
A
V
L
P
C
D
Physical Page Base Address
Reserved
Symbol
AVL
Description
Available to Software
Reserved
Page Size
Reserved
Bits
11–9
8
7
6
5
4
3
2
1
0
PS
A
Accessed
PCD
PWT
U/S
W/R
P
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
Present (valid)
Figure 42. Page Directory Entry 4-Mbyte Page Table (PDE)
Chapter 3
Software Environment
45
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
31
12 11 10
9
8
7
6
5
A
4
3
2
1
0
P
U
/
S
P
W
T
W
/
R
A
V
L
P
C
D
D
Physical Page Base Address
Symbol
AVL
Description
Available to Software
Reserved
Bits
11–9
8–7
6
D
Dirty
A
Accessed
5
PCD
PWT
U/S
W/R
P
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
4
3
2
1
Present (valid)
0
Figure 43. Page Table Entry (PTE)
Descriptors and Gates There are various types of structures and registers in the x86
architecture that define, protect, and isolate code segments,
data segments, task state segments, and gates. These structures
are called descriptors.
Figure 44 on page 47 shows the application segment descriptor
format. Table 9 contains information describing the memory
segment type to which the descriptor points. The application
segment descriptor is used to point to either a data or code
segment.
Figure 45 on page 48 shows the system segment descriptor
format. Table 10 contains information describing the type of
segment or gate to which the descriptor points. The system
segment descriptor is used to point to a task state segment, a
call gate, or a local descriptor table.
The AMD-K6-2 processor uses gates to transfer control between
executable segments with different privilege levels. Figure 46
on page 49 shows the format of the gate descriptor types. Table
10 contains information describing the type of segment or gate
to which the descriptor points.
46
Software Environment
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Symbol
G
Description
Granularity
Bits
23
D
32-Bit/16-Bit
22
AVL
P
DPL
DT
Available to Software
Present/Valid Bit
Descriptor Privilege Level
Descriptor Type
20
15
14-13
12
Reserved
Type See Table 9
11-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A
9
8
7
6
5
4
3
2
1
0
Base Address 31–24
G
D
Segment
Limit
P
DPL
1
Type
Base Address 23–16
V
L
Base Address 15–0
Segment Limit 15–0
Figure 44. Application Segment Descriptor
Table 9. Application Segment Types
Type Data/Code
Description
0
1
2
Read-Only
Read-Only—Accessed
Read/Write
3
Read/Write—Accessed
Data
4
Read-Only—Expand-down
Read-Only—Expand-down, Accessed
Read/Write—Expand-down
Read/Write—Expand-down, Accessed
Execute-Only
5
6
7
8
9
A
Execute-Only—Accessed
Execute/Read
B
Execute/Read—Accessed
Code
C
Execute-Only—Conforming
Execute-Only—Conforming, Accessed
Execute/Read-Only—Conforming
D
E
F
Execute/Read-Only—Conforming, Accessed
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AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Symbol
G
Description
Granularity
Bits
23
X
Not Needed
22
AVL
P
DPL
DT
Availability to Software
Present/Valid Bit
Descriptor Privilege Level
Descriptor Type
20
15
14-13
12
Reserved
Type See Table 10
11-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A
9
8
7
6
5
4
3
2
1
0
Base Address 31–24
G
X
Segment
Limit
P
DPL
0
Type
Base Address 23–16
V
L
Base Address 15–0
Segment Limit 15–0
Figure 45. System Segment Descriptor
Table 10. System Segment and Gate Types
Type
0
Description
Reserved
1
Available 16-bit TSS
LDT
2
3
Busy 16-bit TSS
16-bit Call Gate
Task Gate
4
5
6
16-bit Interrupt Gate
16-bit Trap Gate
Reserved
7
8
9
Available 32-bit TSS
Reserved
A
B
Busy 32-bit TSS
32-bit Call Gate
Reserved
C
D
E
32-bit Interrupt Gate
32-bit Trap Gate
F
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Symbol
P
Description
Present/Valid Bit
Bits
15
DPL
DT
Descriptor Privilege Level
Descriptor Type
14-13
12
Reserved
Type See Table 10
11-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Offset 31–16
P
DPL
0
Type
Segment Selector
Offset 15–0
Figure 46. Gate Descriptor
Exceptions and
Interrupts
Table 11 summarizes the exceptions and interrupts.
Table 11. Summary of Exceptions and Interrupts
Interrupt
Interrupt Type
Number
Cause
0
1
Divide by Zero Error
Debug
DIV, IDIV
Debug trap or fault
2
Non-Maskable Interrupt NMI signal sampled asserted
3
Breakpoint
Int 3
4
Overflow
INTO
5
Bounds Check
Invalid Opcode
Device Not Available
Double Fault
BOUND
6
Invalid instruction
7
ESC and WAIT
8
Fault occurs while handling a fault
—
9
Reserved - Interrupt 13
Invalid TSS
10
11
12
13
14
16
Task switch to an invalid segment
Segment Not Present
Stack Segment
General Protection
Page Fault
Instruction loads a segment and present bit is 0 (invalid segment)
Stack operation causes limit violation or present bit is 0
Segment related or miscellaneous invalid actions
Page protection violation or a reference to missing page
Arithmetic error generated by floating-point instruction
Floating-Point Error
Data reference to an unaligned operand. (The AC flag and the AM bit of CR0 are
set to 1.)
17
Alignment Check
0–255 Software Interrupt
INT n
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AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
3.2
AMD-K6®-2 Processor Model 8/[F:8] Registers
AMD-K6-2 processor Model 8/[F:8] implements the same seven
MSRs as the Model 8/[7:0], but the bits and fields within the
EFER and WHCR MSRs are not defined identically. Model
8/[F:8] also supports three additional MSRs: UWCCR, PSOR,
®
and PFIR. For more information, see the AMD-K6 Processor
BIOS Design Application Note, order# 21329. Table 12 lists the
MSRs and the corresponding value of the ECX register.
®
Table 12. AMD-K6 -2 Processor Model 8/[F:8] MSRs
Model-Specific Register
Machine Check Address Register (MCAR)
Machine Check Type Register (MCTR)
Test Register 12 (TR12)
Value of ECX
00h
01h
0Eh
Time Stamp Counter (TSC)
10h
Extended Feature Enable Register (EFER)
C000_0080h
SYSCALL/SYSRET Target Address Register (STAR) C000_0081h
Write Handling Control Register (WHCR) C000_0082h
UC/WC Cacheability Control Register (UWCCR) C000_0085h
Processor State Observability Register (PSOR)
Page Flush/Invalidate Register (PFIR)
C000_0087h
C000_0088h
Extended Feature
Enable Register
(EFER)–Model 8/[F:8]
The Extended Feature Enable Register (EFER) contains the
control bits that enable the extended features of the processor.
Figure 47 shows the format of the EFER register, and Table 13
on page 51 defines the function of each bit of the EFER
register.
Note: The EFER register as defined in the Model 8/[7:0] has
changed in the Model 8/[F:8]. See “Extended Feature Enable
Register (EFER)–Model 8[7:0]” on page 39.
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AMD-K6 -2 Processor Data Sheet
63
4
3
2
1
0
S
C
E
D
P
E
EWBEC
Reserved
Symbol
EWBEC
DPE
Description
EWBE Control
Data Prefetch Enable
System Call Extension
Bit
3-2
1
SCE
0
Figure 47. Extended Feature Enable Register (EFER)—Model 8/[F:8]
Table 13. Extended Feature Enable Register (EFER)–Model 8/[F:8] Definition
Bit
Description
R/W
Function
Writing a 1 to any reserved bit causes a general protection
fault to occur. All reserved bits are always read as 0.
63–4
Reserved
R
This 2-bit field controls the behavior of the processor with
respect to the ordering of write cycles and the EWBE# signal.
EFER[3] and EFER[2] are Global EWBE Disable (GEWBED)
and Speculative EWBE Disable (SEWBED), respectively.
3-2
EWBE Control (EWBEC)
R/W
DPE must be set to 1 to enable data prefetching (this is the
default setting following reset). If enabled, cache misses
1
0
Data Prefetch Enable (DPE)
System Call Extension (SCE)
R/W initiated by a memory read within a 32-byte cache line are
conditionally followed by cache-line fetches of the other line
in the 64-byte sector.
SCE must be set to 1 to enable the usage of the SYSCALL and
R/W
SYSRET instructions.
For more information on EWBEC, see “EWBE Control” on page
201.
Write Handling
Control Register
(WHCR)–Model
8/[F:8]
The Write Handling Control Register (WHCR) is a MSR that
contains two fields —the Write Allocate Enable Limit
(WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte
(WAE15M) bit (see Figure 48). For more information, see
“Write Allocate” on page 186.
Note: The WHCR register as defined in the Model 8/[7:0] has
changed in the Model 8/[F:8]. See “Write Handling Control
Register (WHCR)–Model 8/[7:0]” on page 40.
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Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
63
32 31
22 21 17 16 15
0
W
A
E
WAELIM
1
5
M
Reserved
Symbol
WAELIM
WAE15M
Description
Write Allocate Enable Limit
Write Allocate Enable 15-to-16-Mbyte 16
Bits
31-22
Note: Hardware RESET initializes this MSR to all zeros.
Figure 48. Write Handling Control Register (WHCR)—Model 8/[F:8]
UC/WC Cacheability
Control Register
(UWCCR)
The AMD-K6-2 processor Model 8/[F:8] provides two variable-
range Memory Type Range Registers (MTRRs)—MTRR0 and
MTRR1—that each specify a range of memory. Each range can
be defined as uncacheable (UC) or write-combining (WC)
memory. For more detailed information on UWCCR, see
“UC/WC Cacheability Control Register (UWCCR)” on page
203.
.
Symbol Description
Bits
32
Symbol Description
Bits
0
UC1
Uncacheable Memory Type
UC0
Uncacheable Memory Type
WC1
Write-Combining Memory Type 33
WC0
Write-Combining Memory Type
1
63
49 48
34 33 32 31
17 16
2
1
0
W
C
1
U
C
1
W
C
0
U
C
0
Physical Base Address 1
Physical Address Mask 1
Physical Base Address 0
Physical Address Mask 0
MTRR1
MTRR0
Figure 49. UC/WC Cacheability Control Register (UWCCR)
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AMD-K6 -2 Processor Data Sheet
Processor State
Observability
The AMD-K6-2 processor Model 8/[F:8] provides the Processor
State Observability Register (PSOR) (see Figure 50).
Register (PSOR)
63
4
3
2
0
9
8
7
N
O
L
STEP
BF
2
Reserved
Symbol
NOL2
STEP
BF
Description
Bit
8
7-4
2-0
No L2 Functionality
Processor Stepping
Bus Frequency Divisor
Figure 50. Processor State Observability Register (PSOR)
Page Flush/Invalidate
Register (PFIR)
The AMD-K6-2 processor Model 8/[F:8] contains the Page
Flush/Invalidate Register (PFIR) (see Figure 51) that allows
cache invalidation and optional flushing of a specific 4-Kbyte
page from the linear address space. For more detailed
information on PFIR, see “PFIR” on page 195.
63
32 31
12 11 9 8 7
1 0
F
/
I
P
F
LINPAGE
Reserved
Symbol
Description
Bit
LINPAGE 20-bit Linear Page Address
31-12
PF
F/I
Page Fault Occurred
Flush/Invalidate Command
8
0
Figure 51. Page Flush/Invalidate Register (PFIR)
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Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
3.3
Instructions Supported by the AMD-K6®-2 Processor
This section documents all of the x86 instructions supported by
the AMD-K6-2 processor. The following tables show the
instruction mnemonic, opcode, modR/M byte, decode type, and
RISC86 operation(s) for each instruction. Tables 14 through 17
define the integer, floating-point, MMX, and 3DNow!
instructions for the AMD-K6-2 processor, respectively.
The first column in these tables indicates the instruction
mnemonic and operand types with the following notations:
■ reg8—byte integer register defined by instruction byte(s) or
bits 5, 4, and 3 of the modR/M byte
■ mreg8—byte integer register or byte integer value in
memory defined by the modR/M byte
■ reg16/32—word or doubleword integer register defined by
instruction byte(s) or bits 5, 4, and 3 of the modR/M byte
■ mreg16/32—word or doubleword integer register, or word or
doubleword integer value in memory defined by the
modR/M byte
■ mem8—byte integer value in memory
■ mem16/32—word or doubleword integer value in memory
■ mem32/48—doubleword or 48-bit integer value in memory
■ mem48—48-bit integer value in memory
■ mem64—64-bit value in memory
■ imm8—8-bit immediate value
■ imm16/32—16-bit or 32-bit immediate value
■ disp8—8-bit displacement value
■ disp16/32—16-bit or 32-bit displacement value
■ disp32/48—doubleword or 48-bit displacement value
■ eXX—register width depending on the operand size
■ mem32real—32-bit floating-point value in memory
■ mem64real—64-bit floating-point value in memory
■ mem80real—80-bit floating-point value in memory
■ mmreg—MMX/3DNow! register
■ mmreg1—MMX/3DNow! register defined by bits 5, 4, and 3
of the modR/M byte
■ mmreg2—MMX/3DNow! register defined by bits 2, 1, and 0
of the modR/M byte
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AMD-K6 -2 Processor Data Sheet
The second and third columns list all applicable opcode bytes.
The fourth column lists the modR/M byte when used by the
instruction. The modR/M byte defines the instruction as a
register or memory form. If modR/M bits 7 and 6 are documented
as mm (memory form), mm can only be 10b, 01b or 00b.
The fifth column lists the type of instruction decode—short,
long, and vector. The AMD-K6-2 processor decode logic can
process two short, one long, or one vector decode per clock.
The sixth column lists the type of RISC86 operation(s) required
for the instruction. The operation types and corresponding
execution units are as follows:
■ load, fload, mload—load unit
■ store, fstore, mstore—store unit
■ alu—either of the integer execution units
■ alux—integer X execution unit only
■ branch—branch condition unit
■ float—floating-point execution unit
■ meu—Multimedia execution units for MMX and 3DNow!
instructions
■ limm—load immediate, instruction control unit
Table 14. Integer Instructions
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
AAA
37h
D5h
D4h
3Fh
10h
10h
11h
11h
12h
12h
13h
13h
14h
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
AAD
0Ah
0Ah
AAM
AAS
ADC mreg8, reg8
ADC mem8, reg8
ADC mreg16/32, reg16/32
ADC mem16/32, reg16/32
ADC reg8, mreg8
ADC reg8, mem8
ADC reg16/32, mreg16/32
ADC reg16/32, mem16/32
ADC AL, imm8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
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AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
ADC EAX, imm16/32
15h
80h
80h
81h
81h
83h
83h
00h
00h
01h
01h
02h
02h
03h
03h
04h
05h
80h
80h
81h
81h
83h
83h
20h
20h
21h
21h
22h
22h
23h
23h
24h
25h
vector
vector
vector
vector
vector
vector
vector
short
long
ADC mreg8, imm8
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-xxx-xxx
ADC mem8, imm8
ADC mreg16/32, imm16/32
ADC mem16/32, imm16/32
ADC mreg16/32, imm8 (signed ext.)
ADC mem16/32, imm8 (signed ext.)
ADD mreg8, reg8
alux
ADD mem8, reg8
mm-xxx-xxx
11-xxx-xxx
load, alux, store
ADD mreg16/32, reg16/32
ADD mem16/32, reg16/32
ADD reg8, mreg8
short
long
alu
mm-xxx-xxx
11-xxx-xxx
load, alu, store
short
short
short
short
short
short
short
long
alux
ADD reg8, mem8
mm-xxx-xxx
11-xxx-xxx
load, alux
ADD reg16/32, mreg16/32
ADD reg16/32, mem16/32
ADD AL, imm8
alu
mm-xxx-xxx
load, alu
alux
ADD EAX, imm16/32
alu
ADD mreg8, imm8
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-xxx-xxx
alux
ADD mem8, imm8
load, alux, store
ADD mreg16/32, imm16/32
ADD mem16/32, imm16/32
ADD mreg16/32, imm8 (signed ext.)
ADD mem16/32, imm8 (signed ext.)
AND mreg8, reg8
short
long
alu
load, alu, store
alux
short
long
load, alux, store
alux
short
long
AND mem8, reg8
mm-xxx-xxx
11-xxx-xxx
load, alux, store
alu
AND mreg16/32, reg16/32
AND mem16/32, reg16/32
AND reg8, mreg8
short
long
mm-xxx-xxx
11-xxx-xxx
load, alu, store
alux
short
short
short
short
short
short
AND reg8, mem8
mm-xxx-xxx
11-xxx-xxx
load, alux
alu
AND reg16/32, mreg16/32
AND reg16/32, mem16/32
AND AL, imm8
mm-xxx-xxx
load, alu
alux
AND EAX, imm16/32
alu
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Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
RISC86
Operations
Type
short
long
AND mreg8, imm8
80h
80h
81h
81h
83h
83h
63h
63h
62h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-xxx-xxx
alux
AND mem8, imm8
load, alux, store
alu
AND mreg16/32, imm16/32
AND mem16/32, imm16/32
AND mreg16/32, imm8 (signed ext.)
AND mem16/32, imm8 (signed ext.)
ARPL mreg16, reg16
ARPL mem16, reg16
BOUND
short
long
load, alu, store
alux
short
long
load, alux, store
vector
vector
vector
vector
vector
vector
vector
long
mm-xxx-xxx
BSF reg16/32, mreg16/32
BSF reg16/32, mem16/32
BSR reg16/32, mreg16/32
BSR reg16/32, mem16/32
BSWAP EAX
BCh
BCh
BDh
BDh
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
A3h
A3h
BAh
BAh
BBh
BBh
BAh
BAh
B3h
B3h
BAh
BAh
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alu
alu
alu
alu
alu
alu
alu
alu
BSWAP ECX
long
BSWAP EDX
long
BSWAP EBX
long
BSWAP ESP
long
BSWAP EBP
long
BSWAP ESI
long
BSWAP EDI
long
BT mreg16/32, reg16/32
BT mem16/32, reg16/32
BT mreg16/32, imm8
BT mem16/32, imm8
BTC mreg16/32, reg16/32
BTC mem16/32, reg16/32
BTC mreg16/32, imm8
BTC mem16/32, imm8
BTR mreg16/32, reg16/32
BTR mem16/32, reg16/32
BTR mreg16/32, imm8
BTR mem16/32, imm8
11-xxx-xxx
mm-xxx-xxx
11-100-xxx
mm-100-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
mm-xxx-xxx
11-111-xxx
mm-111-xxx
11-xxx-xxx
mm-xxx-xxx
11-110-xxx
mm-110-xxx
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AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
BTS mreg16/32, reg16/32
BTS mem16/32, reg16/32
BTS mreg16/32, imm8
BTS mem16/32, imm8
CALL full pointer
0Fh
0Fh
0Fh
0Fh
9Ah
E8h
FFh
FFh
FFh
98h
F8h
FCh
FAh
0Fh
F5h
38h
38h
39h
39h
3Ah
3Ah
3Bh
3Bh
3Ch
3Dh
80h
80h
81h
81h
83h
83h
A6h
A7h
ABh
ABh
BAh
BAh
11-xxx-xxx
mm-xxx-xxx
11-101-xxx
mm-101-xxx
vector
vector
vector
vector
vector
short
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
short
short
short
short
short
short
short
short
short
short
short
short
short
long
CALL near imm16/32
CALL mem16:16/32
CALL near mreg32 (indirect)
CALL near mem32 (indirect)
CBW/CWDE EAX
store
11-011-xxx
11-010-xxx
mm-010-xxx
CLC
CLD
CLI
CLTS
06h
CMC
CMP mreg8, reg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alux
CMP mem8, reg8
load, alux
alu
CMP mreg16/32, reg16/32
CMP mem16/32, reg16/32
CMP reg8, mreg8
load, alu
alux
CMP reg8, mem8
load, alux
alu
CMP reg16/32, mreg16/32
CMP reg16/32, mem16/32
CMP AL, imm8
load, alu
alux
CMP EAX, imm16/32
CMP mreg8, imm8
CMP mem8, imm8
CMP mreg16/32, imm16/32
CMP mem16/32, imm16/32
CMP mreg16/32, imm8 (signed ext.)
CMP mem16/32, imm8 (signed ext.)
CMPSB mem8, mem8
CMPSW mem16, mem32
alu
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
alux
load, alux
alu
load, alu
load, alu
load, alu
long
vector
vector
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AMD-K6 -2 Processor Data Sheet
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
RISC86
Operations
Type
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
CMPSD mem32, mem32
CMPXCHG mreg8, reg8
CMPXCHG mem8, reg8
CMPXCHG mreg16/32, reg16/32
CMPXCHG mem16/32, reg16/32
CMPXCHG8B EDX:EAX
CMPXCHG8B mem64
CPUID
A7h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
99h
27h
2Fh
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
FEh
FEh
FFh
FFh
F6h
F6h
F7h
F7h
F6h
F6h
F7h
F7h
69h
B0h
B0h
B1h
B1h
C7h
C7h
A2h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
CWD/CDQ EDX, EAX
DAA
DAS
DEC EAX
alu
alu
alu
alu
alu
alu
alu
alu
DEC ECX
short
DEC EDX
short
DEC EBX
short
DEC ESP
short
DEC EBP
short
DEC ESI
short
DEC EDI
short
DEC mreg8
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-110-xxx
mm-110-xxx
11-110-xxx
mm-110-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-xxx-xxx
vector
long
DEC mem8
load, alux, store
load, alu, store
DEC mreg16/32
DEC mem16/32
DIV AL, mreg8
DIV AL, mem8
DIV EAX, mreg16/32
DIV EAX, mem16/32
IDIV mreg8
vector
long
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
IDIV mem8
IDIV EAX, mreg16/32
IDIV EAX, mem16/32
IMUL reg16/32, imm16/32
IMUL reg16/32, mreg16/32, imm16/32 69h
11-xxx-xxx
Chapter 3
Software Environment
59
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
IMUL reg16/32, mem16/32, imm16/32 69h
IMUL reg16/32, imm8 (sign extended) 6Bh
mm-xxx-xxx
11-xxx-xxx
vector
vector
IMUL reg16/32, mreg16/32, imm8
(signed)
6Bh
11-xxx-xxx
vector
vector
IMUL reg16/32, mem16/32, imm8
(signed)
6Bh
mm-xxx-xxx
IMUL AX, AL, mreg8
IMUL AX, AL, mem8
IMUL EDX:EAX, EAX, mreg16/32
IMUL EDX:EAX, EAX, mem16/32
IMUL reg16/32, mreg16/32
IMUL reg16/32, mem16/32
IN AL, imm8
F6h
F6h
F7h
F7h
0Fh
0Fh
E4h
E5h
E5h
ECh
EDh
EDh
40h
41h
42h
43h
44h
45h
46h
47h
FEh
FEh
FFh
FFh
0Fh
0Fh
70h
71h
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
AFh
AFh
mm-xxx-xxx
IN AX, imm8
IN EAX, imm8
IN AL, DX
IN AX, DX
IN EAX, DX
INC EAX
alu
alu
alu
alu
alu
alu
alu
alu
INC ECX
short
INC EDX
short
INC EBX
short
INC ESP
short
INC EBP
short
INC ESI
short
INC EDI
short
INC mreg8
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
vector
long
INC mem8
load, alux, store
load, alu, store
INC mreg16/32
INC mem16/32
INVD
vector
long
08h
01h
vector
vector
short
INVLPG
mm-111-xxx
JO short disp8
JB/JNAE short disp8
branch
branch
short
60
Software Environment
Chapter 3
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
RISC86
Operations
Type
short
short
short
short
short
short
short
short
short
short
short
short
short
short
vector
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
vector
JNO short disp8
71h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
E3h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
E9h
EAh
branch
JNB/JAE short disp8
JZ/JE short disp8
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
JNZ/JNE short disp8
JBE/JNA short disp8
JNBE/JA short disp8
JS short disp8
JNS short disp8
JP/JPE short disp8
JNP/JPO short disp8
JL/JNGE short disp8
JNL/JGE short disp8
JLE/JNG short disp8
JNLE/JG short disp8
JCXZ/JEC short disp8
JO near disp16/32
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
JNO near disp16/32
JB/JNAE near disp16/32
JNB/JAE near disp16/32
JZ/JE near disp16/32
JNZ/JNE near disp16/32
JBE/JNA near disp16/32
JNBE/JA near disp16/32
JS near disp16/32
JNS near disp16/32
JP/JPE near disp16/32
JNP/JPO near disp16/32
JL/JNGE near disp16/32
JNL/JGE near disp16/32
JLE/JNG near disp16/32
JNLE/JG near disp16/32
JMP near disp16/32 (direct)
JMP far disp32/48 (direct)
Chapter 3
Software Environment
61
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
JMP disp8 (short)
EBh
EFh
EFh
FFh
FFh
9Fh
0Fh
0Fh
C5h
8Dh
C9h
C4h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
ACh
ADh
ADh
E2h
E1h
E0h
0Fh
0Fh
0Fh
0Fh
0Fh
88h
88h
short
vector
vector
vector
vector
vector
vector
vector
vector
short
branch
JMP far mreg32 (indirect)
JMP far mem32 (indirect)
JMP near mreg16/32 (indirect)
JMP near mem16/32 (indirect)
LAHF
11-101-xxx
mm-101-xxx
11-100-xxx
mm-100-xxx
LAR reg16/32, mreg16/32
LAR reg16/32, mem16/32
LDS reg16/32, mem32/48
LEA reg16/32, mem16/32
LEAVE
02h
02h
11-xxx-xxx
mm-xxx-xxx
mm-xxx-xxx
mm-xxx-xxx
load, alu
long
load, alu, alu
LES reg16/32, mem32/48
LFS reg16/32, mem32/48
LGDT mem48
mm-xxx-xxx
mm-010-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
long
B4h
01h
B5h
01h
00h
00h
01h
01h
LGS reg16/32, mem32/48
LIDT mem48
mm-011-xxx
11-010-xxx
LLDT mreg16
LLDT mem16
mm-010-xxx
11-100-xxx
mm-100-xxx
LMSW mreg16
LMSW mem16
LODSB AL, mem8
load, alu
load, alu
load, alu
alu, branch
LODSW AX, mem16
LODSD EAX, mem32
LOOP disp8
long
long
short
LOOPE/LOOPZ disp8
LOOPNE/LOOPNZ disp8
LSL reg16/32, mreg16/32
LSL reg16/32, mem16/32
LSS reg16/32, mem32/48
LTR mreg16
vector
vector
vector
vector
vector
vector
vector
short
03h
03h
B2h
00h
00h
11-xxx-xxx
mm-xxx-xxx
mm-xxx-xxx
11-011-xxx
mm-011-xxx
11-xxx-xxx
LTR mem16
MOV mreg8, reg8
alux
MOV mem8, reg8
mm-xxx-xxx
short
store
62
Software Environment
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
RISC86
Operations
Type
short
short
short
short
short
short
long
MOV mreg16/32, reg16/32
MOV mem16/32, reg16/32
MOV reg8, mreg8
89h
89h
8Ah
8Ah
8Bh
8Bh
8Ch
8Ch
8Eh
8Eh
A0h
A1h
A2h
A3h
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C6h
C6h
C7h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alu
store
alux
load
alu
MOV reg8, mem8
MOV reg16/32, mreg16/32
MOV reg16/32, mem16/32
MOV mreg16, segment reg
MOV mem16, segment reg
MOV segment reg, mreg16
MOV segment reg, mem16
MOV AL, mem8
load
load
vector
vector
vector
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
long
load
load
store
store
MOV EAX, mem16/32
MOV mem8, AL
MOV mem16/32, EAX
MOV AL, imm8
limm
limm
limm
limm
limm
limm
limm
limm
limm
limm
limm
limm
limm
limm
limm
limm
limm
store
limm
MOV CL, imm8
MOV DL, imm8
MOV BL, imm8
MOV AH, imm8
MOV CH, imm8
MOV DH, imm8
MOV BH, imm8
MOV EAX, imm16/32
MOV ECX, imm16/32
MOV EDX, imm16/32
MOV EBX, imm16/32
MOV ESP, imm16/32
MOV EBP, imm16/32
MOV ESI, imm16/32
MOV EDI, imm16/32
MOV mreg8, imm8
MOV mem8, imm8
MOV mreg16/32, imm16/32
11-000-xxx
mm-000-xxx
11-000-xxx
short
Chapter 3
Software Environment
63
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
MOV mem16/32, imm16/32
MOV reg32, CR0
C7h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
A4h
A5h
A5h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
F6h
F6h
F7h
F7h
F6h
F6h
F7h
F7h
90h
F6h
F6h
F7h
F7h
mm-000-xxx
11-000-xxx
11-010-xxx
11-011-xxx
11-100-xxx
11-000-xxx
11-010-xxx
11-011-xxx
11-100-xxx
long
vector
vector
vector
vector
vector
vector
vector
vector
long
store
20h
20h
20h
20h
22h
22h
22h
22h
MOV reg32, CR2
MOV reg32, CR3
MOV reg32, CR4
MOV CR0, reg32
MOV CR2, reg32
MOV CR3, reg32
MOV CR4, reg32
MOVSB mem8,mem8
MOVSD mem16, mem16
MOVSW mem32, mem32
MOVSX reg16/32, mreg8
MOVSX reg16/32, mem8
MOVSX reg32, mreg16
MOVSX reg32, mem16
MOVZX reg16/32, mreg8
MOVZX reg16/32, mem8
MOVZX reg32, mreg16
MOVZX reg32, mem16
MUL AL, mreg8
load, store, alux, alux
long
load, store, alu, alu
long
load, store, alu, alu
BEh
BEh
BFh
BFh
B6h
B6h
B7h
B7h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
short
short
short
short
short
short
short
short
vector
vector
vector
vector
short
vector
short
vector
short
short
vector
short
vector
alu
load, alu
alu
mm-xxx-xxx
11-xxx-xxx
load, alu
alu
mm-xxx-xxx
11-xxx-xxx
load, alu
alu
mm-xxx-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
load, alu
MUL AL, mem8
MUL EAX, mreg16/32
MUL EAX, mem16/32
NEG mreg8
alux
alu
NEG mem8
NEG mreg16/32
NEG mem16/32
NOP (XCHG EAX, EAX)
NOT mreg8
limm
alux
11-010-xxx
mm-010-xxx
11-010-xxx
NOT mem8
NOT mreg16/32
alu
NOT mem16/32
mm-010-xxx
64
Software Environment
Chapter 3
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
RISC86
Operations
Type
short
long
OR mreg8, reg8
OR mem8, reg8
OR mreg16/32, reg16/32
OR mem16/32, reg16/32
OR reg8, mreg8
OR reg8, mem8
OR reg16/32, mreg16/32
OR reg16/32, mem16/32
OR AL, imm8
08h
08h
09h
09h
0Ah
0Ah
0Bh
0Bh
0Ch
0Dh
80h
80h
81h
81h
83h
83h
E6h
E7h
E7h
EEh
EFh
EFh
07h
17h
1Fh
0Fh
0Fh
58h
59h
5Ah
5Bh
5Ch
5Dh
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alux
load, alux, store
short
long
alu
load, alu, store
alux
short
short
short
short
short
short
short
long
load, alux
alu
load, alu
alux
OR EAX, imm16/32
OR mreg8, imm8
OR mem8, imm8
OR mreg16/32, imm16/32
OR mem16/32, imm16/32
OR mreg16/32, imm8 (signed ext.)
OR mem16/32, imm8 (signed ext.)
OUT imm8, AL
OUT imm8, AX
OUT imm8, EAX
OUT DX, AL
alu
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
alux
load, alux, store
alu
short
long
load, alu, store
alux
short
long
load, alux, store
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
short
short
short
short
short
OUT DX, AX
OUT DX, EAX
POP ES
POP SS
POP DS
POP FS
A1h
A9h
POP GS
POP EAX
load, alu
load, alu
load, alu
load, alu
load, alu
load, alu
POP ECX
POP EDX
POP EBX
POP ESP
POP EBP
Chapter 3
Software Environment
65
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
POP ESI
5Eh
5Fh
8Fh
8Fh
61h
9Dh
06h
0Eh
0Fh
0Fh
16h
1Eh
50h
51h
52h
53h
54h
55h
56h
57h
6Ah
68h
FFh
FFh
60h
9Ch
C0h
C0h
C1h
C1h
D0h
D0h
D1h
short
short
short
long
load, alu
POP EDI
load, alu
POP mreg 16/32
POP mem 16/32
POPA/POPAD
POPF/POPFD
PUSH ES
11-000-xxx
load, alu
mm-000-xxx
load, store, alu
vector
vector
long
load, store
PUSH CS
vector
vector
vector
vector
long
PUSH FS
A0h
A8h
PUSH GS
PUSH SS
PUSH DS
load, store
store
PUSH EAX
short
short
short
short
short
short
short
short
long
PUSH ECX
store
PUSH EDX
store
PUSH EBX
store
PUSH ESP
store
PUSH EBP
store
PUSH ESI
store
PUSH EDI
store
PUSH imm8
PUSH imm16/32
PUSH mreg16/32
PUSH mem16/32
PUSHA/PUSHAD
PUSHF/PUSHFD
RCL mreg8, imm8
RCL mem8, imm8
RCL mreg16/32, imm8
RCL mem16/32, imm8
RCL mreg8, 1
RCL mem8, 1
RCL mreg16/32, 1
store
long
store
11-110-xxx
vector
long
mm-110-xxx
load, store
vector
vector
vector
vector
vector
vector
vector
vector
vector
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
66
Software Environment
Chapter 3
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
RISC86
Operations
Type
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
RCL mem16/32, 1
RCL mreg8, CL
RCL mem8, CL
RCL mreg16/32, CL
RCL mem16/32, CL
RCR mreg8, imm8
RCR mem8, imm8
RCR mreg16/32, imm8
RCR mem16/32, imm8
RCR mreg8, 1
D1h
D2h
D2h
D3h
D3h
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
0Fh
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
RCR mem8, 1
RCR mreg16/32, 1
RCR mem16/32, 1
RCR mreg8, CL
RCR mem8, CL
RCR mreg16/32, CL
RCR mem16/32, CL
RDMSR
32h
31h
RDTSC
0Fh
RET near imm16
RET near
C2h
C3h
CAh
CBh
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
RET far imm16
RET far
ROL mreg8, imm8
ROL mem8, imm8
ROL mreg16/32, imm8
ROL mem16/32, imm8
ROL mreg8, 1
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
ROL mem8, 1
ROL mreg16/32, 1
ROL mem16/32, 1
ROL mreg8, CL
ROL mem8, CL
Chapter 3
Software Environment
67
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
ROL mreg16/32, CL
ROL mem16/32, CL
ROR mreg8, imm8
ROR mem8, imm8
ROR mreg16/32, imm8
ROR mem16/32, imm8
ROR mreg8, 1
D3h
D3h
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
0Fh
9Eh
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
18h
11-000-xxx
mm-000-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
ROR mem8, 1
ROR mreg16/32, 1
ROR mem16/32, 1
ROR mreg8, CL
ROR mem8, CL
ROR mreg16/32, CL
ROR mem16/32, CL
RSM
AAh
SAHF
SAR mreg8, imm8
SAR mem8, imm8
SAR mreg16/32, imm8
SAR mem16/32, imm8
SAR mreg8, 1
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-xxx-xxx
alux
alu
vector
short
vector
short
alux
alu
SAR mem8, 1
vector
short
SAR mreg16/32, 1
SAR mem16/32, 1
SAR mreg8, CL
vector
short
alux
alu
SAR mem8, CL
vector
short
SAR mreg16/32, CL
SAR mem16/32, CL
SBB mreg8, reg8
SBB mem8, reg8
SBB mreg16/32, reg16/32
SBB mem16/32, reg16/32
SBB reg8, mreg8
vector
vector
vector
vector
vector
vector
18h
mm-xxx-xxx
11-xxx-xxx
19h
19h
mm-xxx-xxx
11-xxx-xxx
1Ah
68
Software Environment
Chapter 3
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
RISC86
Operations
Type
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
SBB reg8, mem8
1Ah
1Bh
1Bh
1Ch
1Dh
80h
80h
81h
81h
83h
83h
AEh
AFh
AFh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
mm-xxx-xxx
11-xxx-xxx
SBB reg16/32, mreg16/32
SBB reg16/32, mem16/32
SBB AL, imm8
mm-xxx-xxx
SBB EAX, imm16/32
SBB mreg8, imm8
SBB mem8, imm8
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
SBB mreg16/32, imm16/32
SBB mem16/32, imm16/32
SBB mreg16/32, imm8 (signed ext.)
SBB mem16/32, imm8 (signed ext.)
SCASB AL, mem8
SCASW AX, mem16
SCASD EAX, mem32
SETO mreg8
90h
90h
91h
91h
92h
92h
93h
93h
94h
94h
95h
95h
96h
96h
97h
97h
98h
98h
99h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
SETO mem8
SETNO mreg8
SETNO mem8
SETB/SETNAE mreg8
SETB/SETNAE mem8
SETNB/SETAE mreg8
SETNB/SETAE mem8
SETZ/SETE mreg8
SETZ/SETE mem8
SETNZ/SETNE mreg8
SETNZ/SETNE mem8
SETBE/SETNA mreg8
SETBE/SETNA mem8
SETNBE/SETA mreg8
SETNBE/SETA mem8
SETS mreg8
SETS mem8
SETNS mreg8
Chapter 3
Software Environment
69
Preliminary Information
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AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
SETNS mem8
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
C0h
C0h
C1h
C1h
D0h
D0h
99h
9Ah
9Ah
9Bh
9Bh
9Ch
9Ch
9Dh
9Dh
9Eh
9Eh
9Fh
9Fh
01h
01h
mm-xxx-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
SETP/SETPE mreg8
SETP/SETPE mem8
SETNP/SETPO mreg8
SETNP/SETPO mem8
SETL/SETNGE mreg8
SETL/SETNGE mem8
SETNL/SETGE mreg8
SETNL/SETGE mem8
SETLE/SETNG mreg8
SETLE/SETNG mem8
SETNLE/SETG mreg8
SETNLE/SETG mem8
SGDT mem48
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
mm-000-xxx
mm-001-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
SIDT mem48
SHL/SAL mreg8, imm8
SHL/SAL mem8, imm8
SHL/SAL mreg16/32, imm8
SHL/SAL mem16/32, imm8
SHL/SAL mreg8, 1
alux
alu
vector
short
vector
short
alux
alu
SHL/SAL mem8, 1
vector
short
SHL/SAL mreg16/32, 1
SHL/SAL mem16/32, 1
SHL/SAL mreg8, CL
SHL/SAL mem8, CL
SHL/SAL mreg16/32, CL
SHL/SAL mem16/32, CL
SHR mreg8, imm8
SHR mem8, imm8
vector
short
alux
alu
vector
short
vector
short
alux
alu
vector
short
SHR mreg16/32, imm8
SHR mem16/32, imm8
SHR mreg8, 1
vector
short
alux
SHR mem8, 1
vector
70
Software Environment
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AMD-K6 -2 Processor Data Sheet
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
SHR mreg16/32, 1
D1h
D1h
D2h
D2h
D3h
D3h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
F9h
FDh
FBh
AAh
ABh
ABh
0Fh
0Fh
28h
28h
29h
29h
2Ah
2Ah
2Bh
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-xxx-xxx
short
alu
SHR mem16/32, 1
vector
short
SHR mreg8, CL
alux
alu
SHR mem8, CL
vector
short
SHR mreg16/32, CL
SHR mem16/32, CL
SHLD mreg16/32, reg16/32, imm8
SHLD mem16/32, reg16/32, imm8
SHLD mreg16/32, reg16/32, CL
SHLD mem16/32, reg16/32, CL
SHRD mreg16/32, reg16/32, imm8
SHRD mem16/32, reg16/32, imm8
SHRD mreg16/32, reg16/32, CL
SHRD mem16/32, reg16/32, CL
SLDT mreg16
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
long
A4h
A4h
A5h
A5h
ACh
ACh
ADh
ADh
00h
00h
01h
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-000-xxx
mm-000-xxx
11-100-xxx
mm-100-xxx
SLDT mem16
SMSW mreg16
SMSW mem16
01h
STC
STD
STI
STOSB mem8, AL
store, alux
store, alux
store, alux
STOSW mem16, AX
STOSD mem32, EAX
STR mreg16
long
long
00h
00h
11-001-xxx
mm-001-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
vector
vector
short
long
STR mem16
SUB mreg8, reg8
alux
SUB mem8, reg8
load, alux, store
alu
SUB mreg16/32, reg16/32
SUB mem16/32, reg16/32
SUB reg8, mreg8
short
long
load, alu, store
alux
short
SUB reg8, mem8
short
short
load, alux
alu
SUB reg16/32, mreg16/32
Chapter 3
Software Environment
71
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
SUB reg16/32, mem16/32
SUB AL, imm8
2Bh
2Ch
2Dh
80h
80h
81h
81h
83h
83h
0Fh
0Fh
84h
84h
85h
85h
A8h
A9h
F6h
F6h
F7h
F7h
0Fh
0Fh
0Fh
0Fh
9Bh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
86h
mm-xxx-xxx
short
short
short
short
long
load, alu
alux
SUB EAX, imm16/32
SUB mreg8, imm8
SUB mem8, imm8
SUB mreg16/32, imm16/32
SUB mem16/32, imm16/32
SUB mreg16/32, imm8 (signed ext.)
SUB mem16/32, imm8 (signed ext.)
SYSCALL
alu
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
alux
load, alux, store
alu
short
long
load, alu, store
alux
short
long
load, alux, store
05h
07h
vector
vector
short
vector
short
vector
long
SYSRET
TEST mreg8, reg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
alux
alu
TEST mem8, reg8
TEST mreg16/32, reg16/32
TEST mem16/32, reg16/32
TEST AL, imm8
mm-xxx-xxx
alux
TEST EAX, imm16/32
TEST mreg8, imm8
TEST mem8, imm8
TEST mreg16/32, imm16/32
TEST mem16/32, imm16/32
VERR mreg16
long
alu
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-100-xxx
mm-100-xxx
11-101-xxx
long
alux
long
load, alux
alu
long
long
load, alu
00h
00h
00h
00h
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
VERR mem16
VERW mreg16
VERW mem16
mm-101-xxx
WAIT
WBINVD
09h
30h
C0h
C0h
C1h
C1h
WRMSR
XADD mreg8, reg8
XADD mem8, reg8
XADD mreg16/32, reg16/32
XADD mem16/32, reg16/32
XCHG reg8, mreg8
11-100-xxx
mm-100-xxx
11-101-xxx
mm-101-xxx
11-xxx-xxx
72
Software Environment
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Preliminary Information
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 14. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
RISC86
Operations
Type
vector
vector
vector
short
long
XCHG reg8, mem8
XCHG reg16/32, mreg16/32
XCHG reg16/32, mem16/32
XCHG EAX, EAX
86h
87h
87h
90h
91h
92h
93h
94h
95h
96h
97h
D7h
30h
30h
31h
31h
32h
32h
33h
33h
34h
35h
80h
80h
81h
81h
83h
83h
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
limm
XCHG EAX, ECX
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
XCHG EAX, EDX
long
XCHG EAX, EBX
long
XCHG EAX, ESP
long
XCHG EAX, EBP
long
XCHG EAX, ESI
long
XCHG EAX, EDI
long
XLAT
vector
short
long
XOR mreg8, reg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alux
XOR mem8, reg8
load, alux, store
XOR mreg16/32, reg16/32
XOR mem16/32, reg16/32
XOR reg8, mreg8
short
long
alu
load, alu, store
alux
short
short
short
short
short
short
short
long
XOR reg8, mem8
load, alux
alu
XOR reg16/32, mreg16/32
XOR reg16/32, mem16/32
XOR AL, imm8
load, alu
alux
XOR EAX, imm16/32
XOR mreg8, imm8
alu
11-110-xxx
mm-110-xxx
11-110-xxx
mm-110-xxx
11-110-xxx
mm-110-xxx
alux
XOR mem8, imm8
load, alux, store
alu
XOR mreg16/32, imm16/32
XOR mem16/32, imm16/32
XOR mreg16/32, imm8 (signed ext.)
XOR mem16/32, imm8 (signed ext.)
short
long
load, alu, store
alux
short
long
load, alux, store
Chapter 3
Software Environment
73
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 15. Floating-Point Instructions
Instruction Mnemonic
First Second ModR/M Decode
RISC86
Operations
Note
Byte
Byte
Byte
Type
F2XM1
D9h
D9h
D8h
D8h
DCh
DCh
DEh
DFh
DFh
D9h
DBh
D8h
D8h
DCh
D8h
D8h
DCh
DEh
D9h
D9h
D8h
D8h
D8h
DCh
DCh
DCh
D8h
DCh
DEh
D8h
DCh
F0h
short float
short float
short float
FABS
F1h
FADD ST(0), ST(i)
11-000-xxx
*
*
*
FADD ST(0), mem32real
FADD ST(i), ST(0)
mm-000-xxx short fload, float
11-000-xxx short float
mm-000-xxx short fload, float
11-000-xxx short float
FADD ST(0), mem64real
FADDP ST(i), ST(0)
FBLD
mm-100-xxx vector
mm-110-xxx vector
FBSTP
FCHS
E0h
E2h
short float
FCLEX
vector
FCOM ST(0), ST(i)
FCOM ST(0), mem32real
FCOM ST(0), mem64real
FCOMP ST(0), ST(i)
FCOMP ST(0), mem32real
FCOMP ST(0), mem64real
FCOMPP
11-010-xxx
short float
*
*
mm-010-xxx short fload, float
mm-010-xxx short fload, float
11-011-xxx
short float
mm-011-xxx short fload, float
mm-011-xxx short fload, float
D9h
FFh
F6h
11-011-001
short float
short float
short float
short float
short float
short float
short float
short float
short float
FCOS
FDECSTP
FDIV ST(0), ST(i) (single precision)
FDIV ST(0), ST(i) (double precision)
FDIV ST(0), ST(i) (extended precision)
FDIV ST(i), ST(0) (single precision)
FDIV ST(i), ST(0) (double precision)
FDIV ST(i), ST(0) (extended precision)
FDIV ST(0), mem32real
FDIV ST(0), mem64real
FDIVP ST(0), ST(i)
FDIVR ST(0), ST(i)
FDIVR ST(i), ST(0)
Note:
11-110-xxx
11-110-xxx
11-110-xxx
11-111-xxx
11-111-xxx
11-111-xxx
*
*
*
*
*
*
mm-110-xxx short fload, float
mm-110-xxx short fload, float
11-111-xxx
11-110-xxx
11-111-xxx
short float
short float
short float
*
*
*
*
The last three bits of the modR/M byte select the stack entry ST(i).
74
Software Environment
Chapter 3
Preliminary Information
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 15. Floating-Point Instructions (continued)
First Second ModR/M Decode
RISC86
Note
Instruction Mnemonic
FDIVR ST(0), mem32real
Byte
D8h
DCh
DEh
DDh
DAh
DEh
DAh
DEh
DAh
DEh
DAh
DEh
DAh
DEh
DFh
DBh
DFh
DAh
DEh
D9h
DBh
DFh
DBh
DFh
DBh
DFh
DAh
DEh
DAh
DEh
D9h
Byte
Byte
Type
Operations
mm-111-xxx short fload, float
mm-111-xxx short fload, float
FDIVR ST(0), mem64real
FDIVRP ST(i), ST(0)
FFREE ST(i)
11-110-xxx
11-000-xxx
short float
short float
*
*
FIADD ST(0), mem32int
FIADD ST(0), mem16int
FICOM ST(0), mem32int
FICOM ST(0), mem16int
FICOMP ST(0), mem32int
FICOMP ST(0), mem16int
FIDIV ST(0), mem32int
FIDIV ST(0), mem16int
FIDIVR ST(0), mem32int
FIDIVR ST(0), mem16int
FILD mem16int
mm-000-xxx short fload, float
mm-000-xxx short fload, float
mm-010-xxx short fload, float
mm-010-xxx short fload, float
mm-011-xxx short fload, float
mm-011-xxx short fload, float
mm-110-xxx short fload, float
mm-110-xxx short fload, float
mm-111-xxx short fload, float
mm-111-xxx short fload, float
mm-000-xxx short fload, float
mm-000-xxx short fload, float
mm-101-xxx short fload, float
mm-001-xxx short fload, float
mm-001-xxx short fload, float
short
FILD mem32int
FILD mem64int
FIMUL ST(0), mem32int
FIMUL ST(0), mem16int
FINCSTP
F7h
E3h
FINIT
vector
FIST mem16int
mm-010-xxx short fload, float
mm-010-xxx short fload, float
mm-011-xxx short fload, float
mm-011-xxx short fload, float
mm-111-xxx short fload, float
mm-100-xxx short fload, float
mm-100-xxx short fload, float
mm-101-xxx short fload, float
mm-101-xxx short fload, float
FIST mem32int
FISTP mem16int
FISTP mem32int
FISTP mem64int
FISUB ST(0), mem32int
FISUB ST(0), mem16int
FISUBR ST(0), mem32int
FISUBR ST(0), mem16int
FLD ST(i)
11-000-xxx
short fload, float
*
Note:
*
The last three bits of the modR/M byte select the stack entry ST(i).
Chapter 3
Software Environment
75
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 15. Floating-Point Instructions (continued)
First Second ModR/M Decode
RISC86
Operations
Instruction Mnemonic
FLD mem32real
Note
Byte
D9h
DDh
DBh
D9h
D9h
D9h
D9h
D9h
D9h
D9h
D9h
D9h
D8h
DCh
D8h
DCh
DEh
D9h
D9h
D9h
D9h
D9h
D9h
DDh
DDh
D9h
D9h
D9h
D9h
D9h
D9h
Byte
Byte
Type
mm-000-xxx short fload, float
mm-000-xxx short fload, float
mm-101-xxx vector
short fload, float
mm-101-xxx vector
mm-100-xxx short fload, float
short float
FLD mem64real
FLD mem80real
FLD1
E8h
FLDCW
FLDENV
FLDL2E
EAh
E9h
ECh
EDh
EBh
EEh
FLDL2T
short float
FLDLG2
short float
FLDLN2
short float
FLDPI
short float
FLDZ
short float
FMUL ST(0), ST(i)
FMUL ST(i), ST(0)
FMUL ST(0), mem32real
FMUL ST(0), mem64real
FMULP ST(0), ST(i)
FNOP
11-001-xxx
11-001-xxx
short float
short float
*
*
mm-001-xxx short fload, float
mm-001-xxx short fload, float
11-001-xxx
short float
short float
short float
short float
short float
vector
*
D0h
F3h
F8h
F5h
F2h
FCh
FPATAN
FPREM
FPREM1
FPTAN
FRNDINT
short float
FRSTOR
mm-100-xxx vector
mm-110-xxx vector
FSAVE
FSCALE
FDh
FEh
FBh
FAh
FAh
FAh
short float
FSIN
short float
vector
FSINCOS
FSQRT (single precision)
FSQRT (double precision)
FSQRT (extended precision)
Note:
short float
short float
short float
*
The last three bits of the modR/M byte select the stack entry ST(i).
76
Software Environment
Chapter 3
Preliminary Information
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 15. Floating-Point Instructions (continued)
First Second ModR/M Decode
RISC86
Note
Instruction Mnemonic
FST mem32real
Byte
D9h
DDh
DDh
D9h
D9h
D9h
DDh
D9h
DDh
DFh
DDh
D8h
DCh
D8h
DCh
DEh
D8h
DCh
D8h
DCh
DEh
D9h
DDh
DDh
DAh
D9h
D9h
D9h
D9h
D9h
9Bh
Byte
Byte
Type
Operations
mm-010-xxx short fstore
mm-010-xxx short fstore
FST mem64real
FST ST(i)
11-010-xxx
short fstore
*
FSTCW
mm-111-xxx vector
FSTENV
mm-110-xxx vector
FSTP mem32real
FSTP mem64real
FSTP mem80real
FSTP ST(i)
mm-011-xxx short fstore
mm-011-xxx short fstore
mm-111-xxx vector
11-011-xxx
short float
vector
*
FSTSW AX
E0h
FSTSW mem16
FSUB ST(0), mem32real
FSUB ST(0), mem64real
FSUB ST(0), ST(i)
FSUB ST(i), ST(0)
FSUBP ST(0), ST(i)
FSUBR ST(0), mem32real
FSUBR ST(0), mem64real
FSUBR ST(0), ST(i)
FSUBR ST(i), ST(0)
FSUBRP ST(i), ST(0)
FTST
mm-111-xxx vector
mm-100-xxx short fload, float
mm-100-xxx short fload, float
11-100-xxx
11-101-xxx
11-101-xxx
short float
short float
short float
*
*
*
mm-101-xxx short fload, float
mm-101-xxx short fload, float
11-100-xxx
11-101-xxx
11-100-xxx
short float
short float
short float
short float
short float
short float
short float
short float
short float
vector
*
*
*
E4h
FUCOM
11-100-xxx
11-101-xxx
FUCOMP
FUCOMPP
E9h
E5h
FXAM
FXCH
11-001-xxx
FXTRACT
F4h
F1h
F9h
FYL2X
short float
short float
vector
FYL2XP1
FWAIT
Note:
*
The last three bits of the modR/M byte select the stack entry ST(i).
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Table 16. MMX™ Instructions
Prefix First ModR/M Decode
RISC86
Operations
Instruction Mnemonic
Note
Byte(s) Byte
77h
6Eh 11-xxx-xxx
6Eh mm-xxx-xxx short mload
Byte
Type
EMMS
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
vector
MOVD mmreg, mreg32
MOVD mmreg, mem32
MOVD mreg32, mmreg
MOVD mem32, mmreg
MOVQ mmreg1, mmreg2
MOVQ mmreg, mem64
MOVQ mmreg2, mmreg1
MOVQ mem64, mmreg
PACKSSDW mmreg1, mmreg2
PACKSSDW mmreg, mem64
PACKSSWB mmreg1, mmreg2
PACKSSWB mmreg, mem64
PACKUSWB mmreg1, mmreg2
PACKUSWB mmreg, mem64
PADDB mmreg1, mmreg2
PADDB mmreg, mem64
PADDD mmreg1, mmreg2
PADDD mmreg, mem64
PADDSB mmreg1, mmreg2
PADDSB mmreg, mem64
PADDSW mmreg1, mmreg2
PADDSW mmreg, mem64
PADDUSB mmreg1, mmreg2
PADDUSB mmreg, mem64
PADDUSW mmreg1, mmreg2
PADDUSW mmreg, mem64
PADDW mmreg1, mmreg2
PADDW mmreg, mem64
PAND mmreg1, mmreg2
PAND mmreg, mem64
Note:
short meu
**
**
7Eh 11-xxx-xxx
short mstore, load
7Eh mm-xxx-xxx short mstore
6Fh 11-xxx-xxx
6Fh mm-xxx-xxx short mload
7Fh 11-xxx-xxx short meu
7Fh mm-xxx-xxx short mstore
6Bh 11-xxx-xxx short meu
6Bh mm-xxx-xxx short mload, meu
63h 11-xxx-xxx short meu
63h mm-xxx-xxx short mload, meu
67h 11-xxx-xxx short meu
67h mm-xxx-xxx short mload, meu
FCh 11-xxx-xxx short meu
FCh mm-xxx-xxx short mload, meu
FEh 11-xxx-xxx short meu
FEh mm-xxx-xxx short mload, meu
ECh 11-xxx-xxx short meu
ECh mm-xxx-xxx short mload, meu
EDh 11-xxx-xxx short meu
EDh mm-xxx-xxx short mload, meu
DCh 11-xxx-xxx short meu
DCh mm-xxx-xxx short mload, meu
DDh 11-xxx-xxx short meu
DDh mm-xxx-xxx short mload, meu
FDh 11-xxx-xxx short meu
FDh mm-xxx-xxx short mload, meu
DBh 11-xxx-xxx short meu
DBh mm-xxx-xxx short mload, meu
short meu
** Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 16. MMX™ Instructions (continued)
Prefix First ModR/M Decode
Byte(s) Byte Byte Type
DFh 11-xxx-xxx
DFh mm-xxx-xxx short mload, meu
74h 11-xxx-xxx short meu
74h mm-xxx-xxx short mload, meu
76h 11-xxx-xxx short meu
76h mm-xxx-xxx short mload, meu
75h 11-xxx-xxx short meu
75h mm-xxx-xxx short mload, meu
64h 11-xxx-xxx short meu
64h mm-xxx-xxx short mload, meu
66h 11-xxx-xxx short meu
66h mm-xxx-xxx short mload, meu
65h 11-xxx-xxx short meu
65h mm-xxx-xxx short mload, meu
F5h 11-xxx-xxx short meu
F5h mm-xxx-xxx short mload, meu
E5h 11-xxx-xxx short meu
E5h mm-xxx-xxx short mload, meu
D5h 11-xxx-xxx short meu
D5h mm-xxx-xxx short mload, meu
EBh 11-xxx-xxx short meu
EBh mm-xxx-xxx short mload, meu
F2h 11-xxx-xxx short meu
F2h mm-xxx-xxx short mload, meu
RISC86
Operations
Instruction Mnemonic
Note
PANDN mmreg1, mmreg2
PANDN mmreg, mem64
PCMPEQB mmreg1, mmreg2
PCMPEQB mmreg, mem64
PCMPEQD mmreg1, mmreg2
PCMPEQD mmreg, mem64
PCMPEQW mmreg1, mmreg2
PCMPEQW mmreg, mem64
PCMPGTB mmreg1, mmreg2
PCMPGTB mmreg, mem64
PCMPGTD mmreg1, mmreg2
PCMPGTD mmreg, mem64
PCMPGTW mmreg1, mmreg2
PCMPGTW mmreg, mem64
PMADDWD mmreg1, mmreg2
PMADDWD mmreg, mem64
PMULHW mmreg1, mmreg2
PMULHW mmreg, mem64
PMULLW mmreg1, mmreg2
PMULLW mmreg, mem64
POR mmreg1, mmreg2
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
short meu
POR mmreg, mem64
PSLLD mmreg1, mmreg2
PSLLD mmreg, mem64
PSLLD mmreg, imm8
72h 11-110-xxx
F3h 11-xxx-xxx
short meu
short meu
PSLLQ mmreg1, mmreg2
PSLLQ mmreg, mem64
PSLLQ mmreg, imm8
F3h mm-xxx-xxx short mload, meu
73h 11-110-xxx
F1h 11-xxx-xxx
short meu
short meu
PSLLW mmreg1, mmreg2
PSLLW mmreg, mem64
PSLLW mmreg, imm8
F1h mm-xxx-xxx short mload, meu
71h 11-110-xxx short meu
Note:
** Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 16. MMX™ Instructions (continued)
Prefix First ModR/M Decode
Byte(s) Byte Byte Type
E2h 11-xxx-xxx
E2h mm-xxx-xxx short mload, meu
RISC86
Operations
Instruction Mnemonic
Note
PSRAD mmreg1, mmreg2
PSRAD mmreg, mem64
PSRAD mmreg, imm8
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
short meu
72h 11-100-xxx
E1h 11-xxx-xxx
short meu
short meu
PSRAW mmreg1, mmreg2
PSRAW mmreg, mem64
PSRAW mmreg, imm8
E1h mm-xxx-xxx short mload, meu
71h 11-100-xxx
D2h 11-xxx-xxx
short meu
short meu
PSRLD mmreg1, mmreg2
PSRLD mmreg, mem64
PSRLD mmreg, imm8
D2h mm-xxx-xxx short mload, meu
72h 11-010-xxx
D3h 11-xxx-xxx
short meu
short meu
PSRLQ mmreg1, mmreg2
PSRLQ mmreg, mem64
PSRLQ mmreg, imm8
D3h mm-xxx-xxx short mload, meu
73h 11-010-xxx
D1h 11-xxx-xxx
short meu
short meu
PSRLW mmreg1, mmreg2
PSRLW mmreg, mem64
PSRLW mmreg, imm8
D1h mm-xxx-xxx short mload, meu
71h 11-010-xxx
F8h 11-xxx-xxx
short meu
short meu
PSUBB mmreg1, mmreg2
PSUBB mmreg, mem64
PSUBD mmreg1, mmreg2
PSUBD mmreg, mem64
PSUBSB mmreg1, mmreg2
PSUBSB mmreg, mem64
PSUBSW mmreg1, mmreg2
PSUBSW mmreg, mem64
PSUBUSB mmreg1, mmreg2
PSUBUSB mmreg, mem64
PSUBUSW mmreg1, mmreg2
PSUBUSW mmreg, mem64
PSUBW mmreg1, mmreg2
PSUBW mmreg, mem64
PUNPCKHBW mmreg1, mmreg2
PUNPCKHBW mmreg, mem64
Note:
F8h mm-xxx-xxx short mload, meu
FAh 11-xxx-xxx short meu
FAh mm-xxx-xxx short mload, meu
E8h 11-xxx-xxx short meu
E8h mm-xxx-xxx short mload, meu
E9h 11-xxx-xxx short meu
E9h mm-xxx-xxx short mload, meu
D8h 11-xxx-xxx short meu
D8h mm-xxx-xxx short mload, meu
D9h 11-xxx-xxx short meu
D9h mm-xxx-xxx short mload, meu
F9h 11-xxx-xxx short meu
F9h mm-xxx-xxx short mload, meu
68h 11-xxx-xxx short meu
68h mm-xxx-xxx short mload, meu
** Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 16. MMX™ Instructions (continued)
Prefix First ModR/M Decode
Byte(s) Byte Byte Type
6Ah 11-xxx-xxx
6Ah mm-xxx-xxx short mload, meu
69h 11-xxx-xxx short meu
69h mm-xxx-xxx short mload, meu
60h 11-xxx-xxx short meu
60h mm-xxx-xxx short mload, meu
62h 11-xxx-xxx short meu
62h mm-xxx-xxx short mload, meu
61h 11-xxx-xxx short meu
61h mm-xxx-xxx short mload, meu
EFh 11-xxx-xxx short meu
EFh mm-xxx-xxx short mload, meu
RISC86
Operations
Instruction Mnemonic
Note
PUNPCKHDQ mmreg1, mmreg2
PUNPCKHDQ mmreg, mem64
PUNPCKHWD mmreg1, mmreg2
PUNPCKHWD mmreg, mem64
PUNPCKLBW mmreg1, mmreg2
PUNPCKLBW mmreg, mem32
PUNPCKLDQ mmreg1, mmreg2
PUNPCKLDQ mmreg, mem32
PUNPCKLWD mmreg1, mmreg2
PUNPCKLWD mmreg, mem32
PXOR mmreg1, mmreg2
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
short meu
PXOR mmreg, mem64
Note:
** Bits 2, 1, and 0 of the modR/M byte select the integer register.
Table 17. 3DNow!™ Instructions
Prefix Opcode ModR/M Decode
RISC86
Operations
Instruction Mnemonic
FEMMS
Note
Byte(s)
Byte
0Eh
BFh
BFh
Byte
Type
0Fh
vector
PAVGUSB mmreg1, mmreg2
PAVGUSB mmreg, mem64
PF2ID mmreg1, mmreg2
PF2ID mmreg, mem64
PFACC mmreg1, mmreg2
PFACC mmreg, mem64
PFADD mmreg1, mmreg2
PFADD mmreg, mem64
PFCMPEQ mmreg1, mmreg2
PFCMPEQ mmreg, mem64
PFCMPGE mmreg1, mmreg2
Notes:
0Fh, 0Fh
0Fh, 0Fh
11-xxx-xxx
short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
0Fh, 0Fh 1Dh
0Fh, 0Fh 1Dh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
AEh
AEh
9Eh
9Eh
B0h
B0h
90h
1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be
prefetched.
2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2 processor, this instruction performs in
the same manner as the PREFETCH instruction.
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Table 17. 3DNow!™ Instructions (continued)
Prefix Opcode ModR/M Decode
Byte Type
RISC86
Operations
Instruction Mnemonic
Note
Byte(s)
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
Byte
90h
A0h
A0h
A4h
A4h
94h
94h
B4h
B4h
96h
96h
A6h
A6h
B6h
B6h
A7h
A7h
97h
97h
9Ah
9Ah
PFCMPGE mmreg, mem64
PFCMPGT mmreg1, mmreg2
PFCMPGT mmreg, mem64
PFMAX mmreg1, mmreg2
PFMAX mmreg, mem64
PFMIN mmreg1, mmreg2
PFMIN mmreg, mem64
PFMUL mmreg1, mmreg2
PFMUL mmreg, mem64
PFRCP mmreg1, mmreg2
PFRCP mmreg, mem64
PFRCPIT1 mmreg1, mmreg2
PFRCPIT1 mmreg, mem64
PFRCPIT2 mmreg1, mmreg2
PFRCPIT2 mmreg, mem64
PFRSQIT1 mmreg1, mmreg2
PFRSQIT1 mmreg, mem64
PFRSQRT mmreg1, mmreg2
PFRSQRT mmreg, mem64
PFSUB mmreg1, mmreg2
PFSUB mmreg, mem64
PFSUBR mmreg1, mmreg2
PFSUBR mmreg, mem64
PI2FD mmreg1, mmreg2
PI2FD mmreg, mem64
PMULHRW mmreg1, mmreg2
PMULHRW mmreg1, mem64
PREFETCH mem8
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
0Fh, 0Fh AAh
0Fh, 0Fh AAh
0Fh, 0Fh 0Dh
0Fh, 0Fh 0Dh
0Fh, 0Fh
0Fh, 0Fh
0Fh
B7h
B7h
0Dh
0Dh
mm-xxx-xxx short mload, meu
mm-000-xxx vector load
mm-001-xxx vector load
1
PREFETCHW mem8
0Fh
1, 2
Notes:
1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be
prefetched.
2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2 processor, this instruction performs in
the same manner as the PREFETCH instruction.
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4
Signal Descriptions
4.1
Signal Terminology
The following terminology is used in this chapter:
■ Driven—The processor actively pulls the signal up to the
High-voltage state or pulls the signal down to the
Low-voltage state.
■ Floated—The the signal is not being driven by the processor
(high-impedance state), which allows another device to
drive this signal.
■ Asserted—For all active-High signals, the term asserted
means the signal is in the High-voltage state. For all
active-Low signals, the term asserted means the signal is in
the Low-voltage state.
■ Negated—For all active-High signals, the term negated
means the signal is in the Low-voltage state. For all
active-Low signals, the term negated means the signal is in
the High-voltage state.
■ Sampled—The processor has measured the state of a signal
at predefined points in time and will take the appropriate
action based on the state of the signal. If a signal is not
sampled by the processor, its assertion or negation has no
effect on the operation of the processor.
Figure 52 on page 84 shows the signals grouped by function. The
arrows in the figure indicate the direction of the signal, either
into or out of the processor. Signals with double-headed arrows
are bidirectional. Signals with pound signs (#) are active Low.
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Clock
Voltage Detection
BF[2:0]
VCC2H/L#
VCC2DET
CLK
AHOLD
BOFF#
BREQ
HLDA
HOLD
BRDY#
BRDYC#
D[63:0]
DP[7:0]
PCHK#
Data
and
Data
Parity
Bus
Arbitration
A20M#
A[31:3]
AP
Address
and
Address
Parity
EADS#
HIT#
HITM#
INV
Inquire
Cycles
ADS#
ADSC#
APCHK#
BE[7:0]#
®
D/C#
AMD-K6 -2
FERR#
IGNNE#
Floating-Point
Error Handling
EWBE#
LOCK#
M/IO#
NA#
Processor
Cycle
Definition
and
Control
SCYC
W/R#
FLUSH#
INIT
INTR
NMI
RESET
SMI#
External
Interrupts,
SMM, Reset and
Initialization
CACHE#
KEN#
PCD
Cache
Control
PWT
SMIACT#
STPCLK#
WB/WT#
TCK TDI TDO TMS TRST#
JTAG Test
Figure 52. Logic Symbol Diagram
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4.2
A20M# (Address Bit 20 Mask)
Input
Summary
A20M# is used to simulate the behavior of the 8086 when
running in Real mode. The assertion of A20M# causes the
processor to force bit 20 of the physical address to 0 prior to
accessing the cache or driving out a memory bus cycle. The
clearing of address bit 20 maps addresses that extend above the
8086 1-Mbyte limit to below 1 Mbyte.
Sampled
The processor samples A20M# as a level-sensitive input on
every clock edge. The system logic can drive the signal either
synchronously or asynchronously. If it is asserted
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
The following list explains the effects of the processor sampling
A20M# asserted under various conditions:
■ Inquire cycles and writeback cycles are not affected by the
state of A20M#.
■ The assertion of A20M# in System Management Mode
(SMM) is ignored.
■ When A20M# is sampled asserted in Protected mode, it
causes unpredictable processor operation. A20M# is only
defined in Real mode.
■ To ensure that A20M# is recognized before the first ADS#
occurs following the negation of RESET, A20M# must be
sampled asserted on the same clock edge that RESET is
sampled negated or on one of the two subsequent clock
edges.
■ To ensure A20M# is recognized before the execution of an
instruction, a serializing instruction must be executed
between the instruction that asserts A20M# and the
targeted instruction.
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4.3
A[31:3] (Address Bus)
A[31:5] Bidirectional, A[4:3] Output
Summary
A[31:3] contain the physical address for the current bus cycle.
The processor drives addresses on A[31:3] during memory and
I/O cycles, and cycle definition information during special bus
cycles. The processor samples addresses on A[31:5] during
inquire cycles.
Driven, Sampled, and
Floated
As Outputs: A[31:3] are driven valid off the same clock edge as
ADS# and remain in the same state until the clock edge on
which NA# or the last expected BRDY# of the cycle is sampled
asserted. A[31:3] are driven during memory cycles, I/O cycles,
special bus cycles, and interrupt acknowledge cycles. The
processor continues to drive the address bus while the bus is
idle.
As Inputs: The processor samples A[31:5] during inquire cycles
on the clock edge on which EADS# is sampled asserted. Even
though A4 and A3 are not used during the inquire cycle, they
must be driven to a valid state and must meet the same timings
as A[31:5].
A[31:3] are floated off the clock edge that AHOLD or BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD.
The processor resumes driving A[31:3] off the clock edge on
which the processor samples AHOLD or BOFF#negated and off
the clock edge on which the processor negates HLDA.
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4.4
ADS# (Address Strobe)
Output
Summary
The assertion of ADS# indicates the beginning of a new bus
cycle. The address bus and all cycle definition signals
corresponding to this bus cycle are driven valid off the same
clock edge as ADS#.
Driven and Floated
ADS# is asserted for one clock at the beginning of each bus
cycle. For non-pipelined cycles, ADS# can be asserted as early
as the clock edge after the clock edge on which the last
expected BRDY#of the cycle is sampled asserted, resulting in a
single idle state between cycles. For pipelined cycles if the
processor is prepared to start a new cycle, ADS#can be asserted
as early as one clock edge after NA#is sampled asserted.
If AHOLD is sampled asserted, ADS# is only driven in order to
perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
The processor floats ADS# off the clock edge that BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD.
4.5
ADSC# (Address Strobe Copy)
Output
Summary
ADSC# has the identical function and timing as ADS#. In the
event ADS# becomes too heavily loaded due to a large fanout in
a system, ADSC# can be used to split the load across two
outputs, which can improve system timing.
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4.6
AHOLD (Address Hold)
Input
Summary
AHOLD can be asserted by the system to initiate one or more
inquire cycles. To allow the system to drive the address bus
during an inquire cycle, the processor floats A[31:3] and AP off
the clock edge on which AHOLD is sampled asserted. The data
bus and all other control and status signals remain under the
control of the processor and are not floated. This allows a bus
cycle that is in progress when AHOLD is sampled asserted to
continue to completion. The processor resumes driving the
address bus off the clock edge on which AHOLD is sampled
negated.
If AHOLD is sampled asserted, ADS# is only asserted in order
to perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
Sampled
The processor samples AHOLD on every clock edge. AHOLD is
recognized while INIT and RESET are sampled asserted.
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4.7
AP (Address Parity)
Bidirectional
Summary
AP contains the even parity bit for cache line addresses driven
and sampled on A[31:5]. Even parity means that the total
number of 1 bits on AP and A[31:5] is even. (A4 and A3 are not
used for the generation or checking of address parity because
these bits are not required to address a cache line.) AP is driven
by the processor during processor-initiated cycles and is
sampled by the processor during inquire cycles. If AP does not
reflect even parity during an inquire cycle, the processor
asserts APCHK# to indicate an address bus parity check. The
processor does not take an internal exception as the result of
detecting an address bus parity check, and system logic must
respond appropriately to the assertion of this signal.
Driven, Sampled, and
Floated
As an Output: The processor drives AP valid off the clock edge
on which ADS#is asserted until the clock edge on which NA#or
the last expected BRDY# of the cycle is sampled asserted. AP is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles. The processor continues to drive
AP while the bus is idle.
As an Input: The processor samples AP during inquire cycles on
the clock edge on which EADS#is sampled asserted.
The processor floats AP off the clock edge that AHOLD or
BOFF# is sampled asserted and off the clock edge that the
processor asserts HLDA in recognition of HOLD.
The processor resumes driving AP off the clock edge on which
the processor samples AHOLD or BOFF# negated and off the
clock edge on which the processor negates HLDA.
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4.8
APCHK# (Address Parity Check)
Output
Summary
If the processor detects an address parity error during an
inquire cycle, APCHK# is asserted for one clock. The processor
does not take an internal exception as the result of detecting an
address bus parity check, and system logic must respond
appropriately to the assertion of this signal.
The processor is designed so that APCHK# does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
APCHK# is driven valid off the clock edge after the clock edge
on which the processor samples EADS# asserted. It is negated
off the next clock edge.
APCHK# is always driven except in the Tri-State Test mode.
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4.9
BE[7:0]# (Byte Enables)
Output
Summary
BE[7:0]# are used by the processor to indicate the valid data
bytes during a write cycle and the requested data bytes during
a read cycle. The byte enables can be used to derive address bits
A[2:0], which are not physically part of the processor’s address
bus. The processor checks and generates valid data parity for
the data bytes that are valid as defined by the byte enables. The
eight byte enables correspond to the eight bytes of the data bus
as follows:
■ BE7#: D[63:56]
■ BE6#: D[55:48]
■ BE5#: D[47:40]
■ BE4#: D[39:32]
■ BE3#: D[31:24]
■ BE2#: D[23:16]
■ BE1#: D[15:8]
■ BE0#: D[7:0]
The processor expects data to be driven by the system logic on
all eight bytes of the data bus during a burst cache-line read
cycle, independent of the byte enables that are asserted.
The byte enables are also used to distinguish between special
bus cycles as defined in Table 25 on page 126.
Driven and Floated
BE[7:0]# are driven off the same clock edge as ADS# and
remain in the same state until the clock edge on which NA# or
the last expected BRDY# of the cycle is sampled asserted.
BE[7:0]# are driven during memory cycles, I/O cycles, special
bus cycles, and interrupt acknowledge cycles.
The processor floats BE[7:0]# off the clock edge that BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD. Unlike the address bus,
BE[7:0]# are not floated in response to AHOLD.
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4.10
BF[2:0] (Bus Frequency)
Inputs, Internal Pullups
Summary
BF[2:0] determine the internal operating frequency of the
processor. The frequency of the CLK input signal is multiplied
internally by a ratio determined by the state of these signals as
defined in Table 18. BF[2:0] have weak internal pullups and
default to the 3.5 multiplier if left unconnected.
Table 18. Processor-to-Bus Clock Ratios
State of BF[2:0] Inputs
Processor-Clock to Bus-Clock Ratio
100b
101b
2.5x
3.0x
110b
2.0x or 6.0x*
3.5x
111b
000b
4.5x
001b
5.0x
010b
4.0x
011b
5.5x
Note:
*
The ratio selected is dependent on the stepping of the Model 8. The 2.0x
ratio is supported on the Model 8/[7:0], whereas the 6.0x ratio is supported
on the Model 8/[F:8].
Sampled
BF[2:0] are sampled during the falling transition of RESET.
They must meet a minimum setup time of 1.0 ms and a
minimum hold time of two clocks relative to the negation of
RESET.
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4.11
BOFF# (Backoff)
Input
Summary
If BOFF# is sampled asserted, the processor unconditionally
aborts any cycles in progress and transitions to a bus hold state
by floating the following signals: A[31:3], ADS#, ADSC#, AP,
BE[7:0]#, CACHE#, D[63:0], D/C#, DP[7:0], LOCK#, M/IO#,
PCD, PWT, SCYC, and W/R#. These signals remain floated until
BOFF# is sampled negated. This allows an alternate bus master
or the system to control the bus.
When BOFF# is sampled negated, any processor cycle that was
aborted due to the assertion of BOFF# is restarted from the
beginning of the cycle, regardless of the number of transfers
that were completed. If BOFF# is sampled asserted on the same
clock edge as BRDY# of a bus cycle of any length, then BOFF#
takes precedence over the BRDY#. In this case, the cycle is
aborted and restarted after BOFF#is sampled negated.
Sampled
BOFF# is sampled on every clock edge. The processor floats its
bus signals off the clock edge on which BOFF# is sampled
asserted. These signals remain floated until the clock edge on
which BOFF#is sampled negated.
BOFF# is recognized while INIT and RESET are sampled
asserted.
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4.12
BRDY# (Burst Ready)
Input, Internal Pullup
Summary
BRDY# is asserted to the processor by system logic to indicate
either that the data bus is being driven with valid data during a
read cycle or that the data bus has been latched during a write
cycle. If necessary, the system logic can insert bus cycle wait
states by negating BRDY# until it is ready to continue the data
transfer. BRDY# is also used to indicate the completion of
special bus cycles.
Sampled
BRDY# is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS#.
BRDY# is ignored while the bus is idle. The processor samples
the following inputs on the clock edge on which BRDY# is
sampled asserted: D[63:0], DP[7:0], and KEN# during read
cycles, EWBE# during write cycles (if not masked off), and
WB/WT# during read and write cycles. If NA# is sampled
asserted prior to BRDY#, then KEN# and WB/WT# are sampled
on the clock edge on which NA#is sampled asserted.
The number of times the processor expects to sample BRDY#
asserted depends on the type of bus cycle, as follows:
■ One time for a single-transfer cycle, a special bus cycle, or
each of two cycles in an interrupt acknowledge sequence
■ Four times for a burst cycle (once for each data transfer)
BRDY# can be held asserted for four consecutive clocks
throughout the four transfers of the burst, or it can be negated
to insert wait states.
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4.13
BRDYC# (Burst Ready Copy)
Input, Internal Pullup
Summary
BRDYC# has the identical function as BRDY#. In the event
BRDY# becomes too heavily loaded due to a large fanout or
loading in a system, BRDYC# can be used to reduce this
loading, which improves timing.
In addition, BRDYC# is sampled when RESET is negated to
configure the drive strength of A[20:3], ADS#, HITM#, and
W/R#. If BRDYC# is 0 during the falling transition of RESET,
these particular outputs are configured using higher drive
strengths than the standard strength. If BRDYC#is 1 during the
falling transition of RESET, the standard strength is selected.
Sampled
BRDYC#is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS#.
BRDYC#is also sampled during the falling transition of RESET.
If RESET is driven synchronously, BRDYC# must meet the
specified hold time relative to the negation of RESET. If
RESET is driven asynchronously, the minimum setup and hold
time for BRDYC# relative to the negation of RESET is two
clocks.
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4.14
BREQ (Bus Request)
Output
Summary
BREQ is asserted by the processor to request the bus in order to
complete an internally pending bus cycle. The system logic can
use BREQ to arbitrate among the bus participants. If the
processor does not own the bus, BREQ is asserted until the
processor gains access to the bus in order to begin the pending
cycle or until the processor no longer needs to run the pending
cycle. If the processor currently owns the bus, BREQ is asserted
with ADS#. The processor asserts BREQ for each assertion of
ADS#but does not necessarily assert ADS#for each assertion of
BREQ.
Driven
BREQ is asserted off the same clock edge on which ADS# is
asserted. BREQ can also be asserted off any clock edge,
independent of the assertion of ADS#. BREQ can be negated
one clock edge after it is asserted.
The processor always drives BREQ except in the Tri-State Test
mode.
4.15
CACHE# (Cacheable Access)
Output
Summary
For reads, CACHE# is asserted to indicate the cacheability of
the current bus cycle. In addition, if the processor samples
KEN # asserted, which indicates the driven address is
cacheable, the cycle is a 32-byte burst read cycle. For write
cycles, CACHE#is asserted to indicate the current bus cycle is a
modified cache-line writeback. KEN# is ignored during
writebacks. If CACHE# is not asserted, or if KEN# is sampled
negated during a read cycle, the cycle is not cacheable and
defaults to a single-transfer cycle.
Driven and Floated
CACHE#is driven off the same clock edge as ADS#and remains
in the same state until the clock edge on which NA# or the last
expected BRDY#of the cycle is sampled asserted.
CACHE# is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
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4.16
CLK (Clock)
Input
Summary
The CLK signal is the bus clock for the processor and is the
reference for all signal timings under normal operation (except
for TDI, TDO, TMS, and TRST#). BF[2:0] determine the internal
frequency multiplier applied to CLK to obtain the processor’s
core operating frequency. See “BF[2:0] (Bus Frequency)” on
page 92 for a list of the processor-to-bus clock ratios.
Sampled
The CLK signal must be stable a minimum of 1.0 ms prior to the
negation of RESET to ensure the proper operation of the
processor. See “CLK Switching Characteristics” on page 267 for
details regarding the CLK specifications.
4.17
D/C# (Data/Code)
Output
Summary
The processor drives D/C# during a memory bus cycle to
indicate whether it is addressing data or executable code. D/C#
is also used to define other bus cycles, including interrupt
acknowledge and special cycles. See Table 25 on page 126 for
more details.
Driven and Floated
D/C# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. D/C# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
D/C# is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
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4.18
D[63:0] (Data Bus)
Bidirectional
Summary
D[63:0] represent the processor’s 64-bit data bus. Each of the
eight bytes of data that comprise this bus is qualified as valid
by its corresponding byte enable. See “BE[7:0]# (Byte
Enables)” on page 91.
Driven, Sampled, and
Floated
As Outputs: For single-transfer write cycles, the processor drives
D[63:0] with valid data one clock edge after the clock edge on
which ADS# is asserted and D[63:0] remain in the same state
until the clock edge on which BRDY#is sampled asserted. If the
cycle is a writeback—in which case four, 8-byte transfers
occur—D[63:0] are driven one clock edge after the clock edge
on which ADS# is asserted and are subsequently changed off
the clock edge on which each BRDY# assertion of the burst
cycle is sampled.
If the assertion of ADS# represents a pipelined write cycle that
follows a read cycle, the processor does not drive D[63:0] until it
is certain that contention on the data bus will not occur. In this
case, D[63:0] are driven the clock edge after the last expected
BRDY#of the previous cycle is sampled asserted.
As Inputs: During read cycles, the processor samples D[63:0] on
the clock edge on which BRDY#is sampled asserted.
The processor always floats D[63:0] except when they are being
driven during a write cycle as described above. In addition,
D[63:0] are floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts
HLDA in recognition of HOLD.
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4.19
DP[7:0] (Data Parity)
Bidirectional
Summary
DP[7:0] are even parity bits for each valid byte of data—as
defined by BE[7:0]#—driven and sampled on the D[63:0] data
bus. Even parity means that the total number of 1 bits within
each byte of data and its respective data parity bit is an even
number. DP[7:0] are driven by the processor during write cycles
and sampled by the processor during read cycles. If the
processor detects bad parity on any valid byte of data during a
read cycle, PCHK#is asserted for one clock beginning the clock
edge after BRDY# is sampled asserted. The processor does not
take an internal exception as the result of detecting a data
parity check, and system logic must respond appropriately to
the assertion of this signal.
The eight data parity bits correspond to the eight bytes of the
data bus as follows:
■ DP7: D[63:56]
■ DP6: D[55:48]
■ DP5: D[47:40]
■ DP4: D[39:32]
■ DP3: D[31:24]
■ DP2: D[23:16]
■ DP1: D[15:8]
■ DP0: D[7:0]
For systems that do not support data parity, DP[7:0] should be
connected to V through pullup resistors.
CC3
Driven, Sampled, and
Floated
As Outputs: For single-transfer write cycles, the processor drives
DP[7:0] with valid parity one clock edge after the clock edge on
which ADS# is asserted and DP[7:0] remain in the same state
until the clock edge on which BRDY# is sampled asserted. If the
cycle is a writeback, DP[7:0] are driven one clock edge after the
clock edge on which ADS# is asserted and are subsequently
changed off the clock edge on which each BRDY# assertion of
the burst cycle is sampled.
As Inputs: During read cycles, the processor samples DP[7:0] on
the clock edge BRDY# is sampled asserted.
The processor always floats DP[7:0] except when they are being
driven during a write cycle as described above. In addition,
DP[7:0] are floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts
HLDA in recognition of HOLD.
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4.20
EADS# (External Address Strobe)
Input
Summary
System logic asserts EADS# during a cache inquire cycle to
indicate that the address bus contains a valid address. EADS#
can only be driven after the system logic has taken control of
the address bus by asserting AHOLD or BOFF# or by receiving
HLDA. The processor responds to the sampling of EADS# and
the address bus by driving HIT#, which indicates if the inquired
cache line exists in the processor’s cache, and HITM#, which
indicates if it is in the modified state.
Sampled
If AHOLD or BOFF# is asserted by the system logic in order to
execute a cache inquire cycle, the processor begins sampling
EADS# two clock edges after AHOLD or BOFF# is sampled
asserted. If the system logic asserts HOLD in order to execute a
cache inquire cycle, the processor begins sampling EADS# two
clock edges after the clock edge HLDA is asserted by the
processor.
EADS#is ignored during the following conditions:
■ One clock edge after the clock edge on which EADS# is
sampled asserted
■ Two clock edges after the clock edge on which ADS# is
asserted
■ When the processor is driving the address bus
■ When the processor asserts HITM#
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4.21
EWBE# (External Write Buffer Empty)
Input
Summary
The system logic can negate EWBE#to the processor to indicate
that its external write buffers are full and that additional data
cannot be stored at this time. This causes the processor to delay
the following activities until EWBE# is sampled asserted:
■ The commitment of write hit cycles to cache lines in the
modified state or exclusive state in the processor’s cache
■ The decode and execution of an instruction that follows a
currently-executing serializing instruction
■ The assertion or negation of SMIACT#
■ The entering of the Halt state and the Stop Grant state
Negating EWBE# does not prevent the completion of any type
of cycle that is currently in progress.
Sampled
The processor samples EWBE# on each clock edge that BRDY#
is sampled asserted during all memory write cycles (except
writeback cycles), I/O write cycles, and special bus cycles.
If EWBE# is sampled negated, it is sampled on every clock edge
until it is asserted, and then it is ignored until BRDY# is
sampled asserted in the next write cycle or special cycle.
On the AMD-K6-2 Model 8/[F:8] processor, if EFER[3] is set to
1, then EWBE# is ignored by the processor. For more
information on the EFER settings and EWBE#, see “EWBE
Control” on page 201.
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4.22
FERR# (Floating-Point Error)
Output
Summary
The assertion of FERR# indicates the occurrence of an
unmasked floating-point exception resulting from the
execution of a floating-point instruction. This signal is provided
to allow the system logic to handle this exception in a manner
consistent with IBM-compatible PC/AT systems. See “Handling
Floating-Point Exceptions” on page 207 for a system logic
implementation that supports floating-point exceptions.
The state of the numeric error (NE) bit in CR0 does not affect
the FERR# signal.
The processor is designed so that FERR# does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
The processor asserts FERR# on the instruction boundary of
the next floating-point instruction, MMX instruction, 3DNow!
instruction, or WAIT instruction that occurs following the
floating-point instruction that caused the unmasked
floating-point exception—that is, FERR# is not asserted at the
time the exception occurs. The IGNNE# signal does not affect
the assertion of FERR#.
FERR#is negated during the following conditions:
■ Following the successful execution of the floating-point
instructions FCLEX, FINIT, FSAVE, and FSTENV
■ Under certain circumstances, following the successful
execution of the floating-point instructions FLDCW,
FLDENV, and FRSTOR, which load the floating-point status
word or the floating-point control word
■ Following the falling transition of RESET
FERR#is always driven except in the Tri-State Test mode.
See “IGNNE# (Ignore Numeric Exception)” on page 106 for
more details on floating-point exceptions.
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4.23
FLUSH# (Cache Flush)
Input
Summary
In response to sampling FLUSH# asserted, the processor writes
back any data cache lines that are in the modified state,
invalidates all lines in the instruction and data caches, and then
executes a flush acknowledge special cycle. See Table 25 on
page 126 for the bus definition of special cycles.
In addition, FLUSH# is sampled when RESET is negated to
determine if the processor enters the Tri-State Test mode. If
FLUSH# is 0 during the falling transition of RESET, the
processor enters the Tri-State Test mode instead of performing
the normal RESET functions.
Sampled
FLUSH# is sampled and latched as a falling edge-sensitive
signal. During normal operation (not RESET), FLUSH# is
sampled on every clock edge but is not recognized until the next
instruction boundary. If FLUSH# is asserted synchronously, it
can be asserted for a minimum of one clock. If FLUSH# is
asserted asynchronously, it must have been negated for a
minimum of two clocks, followed by an assertion of a minimum
of two clocks.
FLUSH#is also sampled during the falling transition of RESET.
If RESET and FLUSH# are driven synchronously, FLUSH# is
sampled on the clock edge prior to the clock edge on which
RESET is sampled negated. If RESET is driven asynchronously,
the minimum setup and hold time for FLUSH#, relative to the
negation of RESET, is two clocks.
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4.24
HIT# (Inquire Cycle Hit)
Output
Summary
The processor asserts HIT# during an inquire cycle to indicate
that the cache line is valid within the processor’s instruction or
data cache (also known as a cache hit). The cache line can be in
the modified, exclusive, or shared state.
Driven
HIT# is always driven—except in the Tri-State Test mode—and
only changes state the clock edge after the clock edge on which
EADS# is sampled asserted. It is driven in the same state until
the next inquire cycle.
4.25
HITM# (Inquire Cycle Hit To Modified Line)
Output
Summary
The processor asserts HITM# during an inquire cycle to
indicate that the cache line exists in the processor’s data cache
in the modified state. The processor performs a writeback cycle
as a result of this cache hit. If an inquire cycle hits a cache line
that is currently being written back, the processor asserts
HITM# but does not execute another writeback cycle. The
system logic must not expect the processor to assert ADS# each
time HITM#is asserted.
Driven
HITM# is always driven—except in the Tri-State Test mode—
and, in particular, is driven to represent the result of an inquire
cycle the clock edge after the clock edge on which EADS# is
sampled asserted. If HITM# is negated in response to the
inquire address, it remains negated until the next inquire cycle.
If HITM# is asserted in response to the inquire address, it
remains asserted throughout the writeback cycle and is negated
one clock edge after the last BRDY# of the writeback is
sampled asserted.
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4.26
HLDA (Hold Acknowledge)
Output
Summary
When HOLD is sampled asserted, the processor completes the
current bus cycles, floats the processor bus, and asserts HLDA
in an acknowledgment that these events have been completed.
The processor does not assert HLDA until the completion of a
locked sequence of cycles. While HLDA is asserted, another bus
master can drive cycles on the bus, including inquire cycles to
the processor. The following signals are floated when HLDA is
asserted: A[31:3], ADS#, ADSC#, AP, BE[7:0]#, CACHE#,
D[63:0], D/C#, DP[7:0], LOCK#, M/IO#, PCD, PWT, SCYC, and
W/R#.
The processor is designed so that HLDA does not glitch.
Driven
HLDA is always driven except in the Tri-State Test mode. If a
processor cycle is in progress while HOLD is sampled asserted,
HLDA is asserted one clock edge after the last BRDY# of the
cycle is sampled asserted. If the bus is idle, HLDA is asserted
one clock edge after HOLD is sampled asserted. HLDA is
negated one clock edge after the clock edge on which HOLD is
sampled negated.
The assertion of HLDA is independent of the sampled state of
BOFF#.
The processor floats the bus every clock in which HLDA is
asserted.
4.27
HOLD (Bus Hold Request)
Input
Summary
The system logic can assert HOLD to gain control of the
processor’s bus. When HOLD is sampled asserted, the processor
completes the current bus cycles, floats the processor bus, and
asserts HLDA in an acknowledgment that these events have
been completed.
Sampled
The processor samples HOLD on every clock edge. If a
processor cycle is in progress while HOLD is sampled asserted,
HLDA is asserted one clock edge after the last BRDY# of the
cycle is sampled asserted. If the bus is idle, HLDA is asserted
one clock edge after HOLD is sampled asserted. HOLD is
recognized while INIT and RESET are sampled asserted.
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4.28
IGNNE# (Ignore Numeric Exception)
Input
Summary
IGNNE#, in conjunction with the numeric error (NE) bit in CR0,
is used by the system logic to control the effect of an unmasked
floating-point exception on a previous floating-point instruction
during the execution of a floating-point instruction, MMX
instruction, 3DNow! instruction, or the WAIT instruction—
hereafter referred to as the target instruction.
If an unmasked floating-point exception is pending and the
target instruction is considered error-sensitive, then the
relationship between NE and IGNNE# is as follows:
■ If NE = 0, then:
•
If IGNNE# is sampled asserted, the processor ignores the
floating-point exception and continues with the
execution of the target instruction.
•
If IGNNE# is sampled negated, the processor waits until
it samples IGNNE#, INTR, SMI#, NMI, or INIT asserted.
If IGNNE# is sampled asserted while waiting, the
processor ignores the floating-point exception and
continues with the execution of the target instruction.
If INTR, SMI#, NMI, or INIT is sampled asserted while
waiting, the processor handles its assertion
appropriately.
■ If NE = 1, the processor invokes the INT 10h exception
handler.
If an unmasked floating-point exception is pending and the
target instruction is considered error-insensitive, then the
processor ignores the floating-point exception and continues
with the execution of the target instruction.
FERR# is not affected by the state of the NE bit or IGNNE#.
FERR# is always asserted at the instruction boundary of the
target instruction that follows the floating-point instruction
that caused the unmasked floating-point exception.
This signal is provided to allow the system logic to handle
exceptions in a manner consistent with IBM-compatible PC/AT
systems.
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Sampled
The processor samples IGNNE# as a level-sensitive input on
every clock edge. The system logic can drive the signal either
synchronously or asynchronously. If it is asserted
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
4.29
INIT (Initialization)
Input
Summary
The assertion of INIT causes the processor to empty its
pipelines, to initialize most of its internal state, and to branch
to address FFFF_FFF0h—the same instruction execution
starting point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
MMX state, Model-Specific Registers, the CD and NW bits of
the CR0 register, and other specific internal resources.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
Sampled
INIT is sampled and latched as a rising edge-sensitive signal.
INIT is sampled on every clock edge but is not recognized until
the next instruction boundary. During an I/O write cycle, it must
be sampled asserted a minimum of three clock edges before
BRDY# is sampled asserted if it is to be recognized on the
boundary between the I/O write instruction and the following
instruction.
If INIT is asserted synchronously, it can be asserted for a
minimum of one clock. If it is asserted asynchronously, it must
have been negated for a minimum of two clocks, followed by an
assertion of a minimum of two clocks.
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4.30
INTR (Maskable Interrupt)
Input
Summary
INTR is the system’s maskable interrupt input to the processor.
When the processor samples and recognizes INTR asserted, the
processor executes a pair of interrupt acknowledge bus cycles
and then jumps to the interrupt service routine specified by the
interrupt number that was returned during the interrupt
acknowledge sequence. The processor only recognizes INTR if
the interrupt flag (IF) in the EFLAGS register equals 1.
Sampled
The processor samples INTR as a level-sensitive input on every
clock edge, but the interrupt request is not recognized until the
next instruction boundary. The system logic can drive INTR
either synchronously or asynchronously. If it is asserted
asynchronously, it must be asserted for a minimum pulse width
of two clocks. In order to be recognized, INTR must remain
asserted until an interrupt acknowledge sequence is complete.
4.31
INV (Invalidation Request)
Input
Summary
During an inquire cycle, the state of INV determines whether
an addressed cache line that is found in the processor’s
instruction or data cache transitions to the invalid state or the
shared state.
If INV is sampled asserted during an inquire cycle, the
processor transitions the cache line (if found) to the invalid
state, regardless of its previous state. If INV is sampled negated
during an inquire cycle, the processor transitions the cache line
(if found) to the shared state. In either case, if the cache line is
found in the modified state, the processor writes it back to
memory before changing its state.
Sampled
INV is sampled on the clock edge on which EADS# is sampled
asserted.
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4.32
KEN# (Cache Enable)
Input
Summary
If KEN# is sampled asserted, it indicates that the address
presented by the processor is cacheable. If KEN# is sampled
asserted and the processor intends to perform a cache-line fill
(signified by the assertion of CACHE#), the processor executes
a 32-byte burst read cycle and expects to sample BRDY#
asserted a total of four times. If KEN# is sampled negated
during a read cycle, a single-transfer cycle is executed and the
processor does not cache the data. For write cycles, CACHE# is
asserted to indicate the current bus cycle is a modified
cache-line writeback. KEN#is ignored during writebacks.
If PCD is asserted during a bus cycle, the processor does not
cache any data read during that cycle, regardless of the state of
KEN#. See “PCD (Page Cache Disable)” on page 113 for more
details.
If the processor has sampled the state of KEN# during a cycle,
and that cycle is aborted due to the sampling of BOFF#
asserted, the system logic must ensure that KEN# is sampled in
the same state when the processor restarts the aborted cycle.
Sampled
KEN# is sampled on the clock edge on which the first BRDY# or
NA# of a read cycle is sampled asserted. If the read cycle is a
burst, KEN# is ignored during the last three assertions of
BRDY#. KEN# is sampled during read cycles only when
CACHE# is asserted.
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4.33
LOCK# (Bus Lock)
Output
Summary
The processor asserts LOCK# during a sequence of bus cycles to
ensure that the cycles are completed without allowing other bus
masters to intervene. Locked operations consist of two to five
bus cycles. LOCK# is asserted during the following operations:
■ An interrupt acknowledge sequence
■ Descriptor Table accesses
■ Page Directory and Page Table accesses
■ XCHG instruction
■ An instruction with an allowable LOCK prefix
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s cache are
flushed and invalidated from the cache prior to the locked
operation. If the cache line is in the modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any data read during a locked operation is not cached.
The processor is designed so that LOCK# does not glitch.
Driven and Floated
During a locked cycle, LOCK# is asserted off the same clock
edge on which ADS# is asserted and remains asserted until the
last BRDY# of the last bus cycle is sampled asserted. The
processor negates LOCK# for at least one clock between
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
LOCK# is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD. When LOCK# is floated due to BOFF#
sampled asserted, the system logic is responsible for preserving
the lock condition while LOCK# is in the high-impedance state.
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4.34
M/IO# (Memory or I/O)
Output
Summary
The processor drives M/IO# during a bus cycle to indicate
whether it is addressing the memory or I/O space. If M/IO# = 1,
the processor is addressing memory or a memory-mapped I/O
port as the result of an instruction fetch or an instruction that
loads or stores data. If M/IO# = 0, the processor is addressing an
I/O port during the execution of an I/O instruction. In addition,
M/IO# is used to define other bus cycles, including interrupt
acknowledge and special cycles. See Table 25 on page 126 for
more details.
Driven and Floated
M/IO# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. M/IO# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
M/IO# is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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4.35
NA# (Next Address)
Input
Summary
System logic asserts NA# to indicate to the processor that it is
ready to accept another bus cycle pipelined into the previous
bus cycle. ADS#, along with address and status signals, can be
asserted as early as one clock edge after NA# is sampled
asserted if the processor is prepared to start a new cycle.
Because the processor allows a maximum of two cycles to be in
progress at a time, the assertion of NA# is sampled while two
cycles are in progress but ADS# is not asserted until the
completion of the first cycle.
Sampled
NA# is sampled every clock edge during bus cycles, starting one
clock edge after the clock edge that negates ADS#, until the last
expected BRDY# of the last executed cycle is sampled asserted
(with the exception of the clock edge after the clock edge that
negates the ADS# for a second pending cycle). Because the
processor latches NA# when sampled, the system logic only
needs to assert NA# for one clock.
4.36
NMI (Non-Maskable Interrupt)
Input
Summary
When NMI is sampled asserted, the processor jumps to the
interrupt service routine defined by interrupt number 02h.
Unlike the INTR signal, software cannot mask the effect of NMI
if it is sampled asserted by the processor. However, NMI is
temporarily masked upon entering System Management Mode
(SMM). In addition, an interrupt acknowledge cycle is not
executed because the interrupt number is predefined.
If NMI is sampled asserted while the processor is executing the
interrupt service routine for a previous NMI, the subsequent
NMI remains pending until the completion of the execution of
the IRET instruction at the end of the interrupt service routine.
Sampled
NMI is sampled and latched as a rising edge-sensitive signal.
During normal operation, NMI is sampled on every clock edge
but is not recognized until the next instruction boundary. If it is
asserted synchronously, it can be asserted for a minimum of one
clock. If it is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an assertion
of a minimum of two clocks.
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4.37
PCD (Page Cache Disable)
Output
Summary
The processor drives PCD to indicate the operating system’s
specification of cacheability for the page being addressed.
System logic can use PCD to control external caching. If PCD is
asserted, the addressed page is not cached. If PCD is negated,
the cacheability of the addressed page depends upon the state
of CACHE# and KEN#.
The state of PCD depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
■ In Real mode, or in Protected and Virtual-8086 modes while
paging is disabled (PG bit in CR0 set to 0):
PCD output = CD bit in CR0
■ In Protected and Virtual-8086 modes while caching is
enabled (CD bit in CR0 set to 0) and paging is enabled (PG
bit in CR0 set to 1):
•
•
•
For accesses to I/O space, page directory entries, and
other non-paged accesses:
PCD output = PCD bit in CR3
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PCD output = PCD bit in page directory entry
For accesses to 4-Kbyte pages:
PCD output = PCD bit in page table entry
Driven and Floated
PCD is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
PCD is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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4.38
PCHK# (Parity Check)
Output
Summary
The processor asserts PCHK# during read cycles if it detects an
even parity error on one or more valid bytes of D[63:0] during a
read cycle. (Even parity means that the total number of 1 bits
within each byte of data and its respective data parity bit is
even.) The processor checks data parity for the data bytes that
are valid, as defined by BE[7:0]#, the byte enables.
PCHK# is always driven but is only asserted for memory and I/O
read bus cycles and the second cycle of an interrupt
acknowledge sequence. PCHK# is not driven during any type of
write cycles or special bus cycles. The processor does not take
an internal exception as the result of detecting a data parity
error, and system logic must respond appropriately to the
assertion of this signal.
The processor is designed so that PCHK# does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
PCHK# is always driven except in the Tri-State Test mode. For
each BRDY# returned to the processor during a read cycle with
a parity error detected on the data bus, PCHK# is asserted for
one clock, one clock edge after BRDY# is sampled asserted.
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4.39
PWT (Page Writethrough)
Output
Summary
The processor drives PWT to indicate the operating system’s
specification of the writeback state or writethrough state for
the page being addressed. PWT, together with WB/WT#,
specifies the data cache-line state during cacheable read misses
and write hits to shared cache lines. See “WB/WT# (Writeback
or Writethrough)” on page 123 for more details.
The state of PWT depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
■ In Real mode, or in Protected and Virtual-8086 modes while
paging is disabled (PG bit in CR0 set to 0):
PWT output = 0 (writeback state)
■ In Protected and Virtual-8086 modes while paging is
enabled (PG bit in CR0 set to 1):
•
•
•
For accesses to I/O space, page directory entries, and
other non-paged accesses:
PWT output = PWT bit in CR3
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PWT output = PWT bit in page directory entry
For accesses to 4-Kbyte pages:
PWT output = PWT bit in page table entry
Driven and Floated
PWT is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
PWT is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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4.40
RESET (Reset)
Input
Summary
When the processor samples RESET asserted, it immediately
flushes and initializes all internal resources and its internal
state including its pipelines and caches, the floating-point
state, the MMX state, the 3DNow! state, and all registers, and
then the processor jumps to address FFFF_FFF0h to start
instruction execution.
The signals BRDYC# and FLUSH# are sampled during the
falling transition of RESET to select the drive strength of
selected output signals and to invoke the Tri-State Test mode,
respectively. See these signal descriptions for more details.
Sampled
RESET is sampled as a level-sensitive input on every clock
edge. System logic can drive the signal either synchronously or
asynchronously.
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V
CC
reach specification before it is negated.
During a warm reset, while CLK and V
are within their
CC
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
4.41
RSVD (Reserved)
Summary
Reserved signals are a special class of pins that can be treated
in one of the following ways:
■ As no-connect (NC) pins, in which case these pins are left
unconnected
■ As pins connected to the system logic as defined by the
industry-standard Super7 and Socket 7 interface
■ Any combination of NC and Socket 7 pins
In any case, if the RSVD pins are treated accordingly, the
normal operation of the AMD-K6-2 processor is not adversely
affected in any manner.
See “Pin Designations” on page 297 for a list of the locations of
the RSVD pins.
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4.42
SCYC (Split Cycle)
Output
Summary
The processor asserts SCYC during misaligned, locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
For purposes of bus cycles, the term aligned means:
■ Any 1-byte transfers
■ 2-byte and 4-byte transfers that lie within 4-byte address
boundaries
■ 8-byte transfers that lie within 8-byte address boundaries
Driven and Floated
SCYC is asserted off the same clock edge as ADS#, and negated
off the clock edge on which NA# or the last expected BRDY# of
the entire locked sequence is sampled asserted. SCYC is only
valid during locked memory cycles.
SCYC is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
4.43
SMI# (System Management Interrupt)
Input, Internal Pullup
Summary
The assertion of SMI# causes the processor to enter System
Management Mode (SMM). Upon recognizing SMI#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the interrupt by asserting SMIACT# after
sampling EWBE# asserted (if EWBE# is masked off, then
SMIACT# is not affected by EWBE#)
4. Saves the internal processor state in SMM memory
5. Disables interrupts by clearing the interrupt flag (IF) in
EFLAGS and disables NMI interrupts
6. Jumps to the entry point of the SMM service routine at the
SMM base physical address which defaults to 0003_8000h in
SMM memory
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See “System Management Mode (SMM)” on page 211 for more
details regarding SMM.
Sampled
SMI# is sampled and latched as a falling edge-sensitive signal.
SMI# is sampled on every clock edge but is not recognized until
the next instruction boundary. If SMI# is to be recognized on
the instruction boundary associated with a BRDY#, it must be
sampled asserted a minimum of three clock edges before the
BRDY# is sampled asserted. If it is asserted synchronously, it
can be asserted for a minimum of one clock. If it is asserted
asynchronously, it must have been negated for a minimum of
two clocks followed by an assertion of a minimum of two clocks.
A second assertion of SMI# while in SMM is latched but is not
recognized until the SMM service routine is exited.
4.44
SMIACT# (System Management Interrupt Active)
Output
Summary
The processor acknowledges the assertion of SMI# with the
assertion of SMIACT# to indicate that the processor has
entered System Management Mode (SMM). The system logic
can use SMIACT# to enable SMM memory. See “SMI# (System
Management Interrupt)” on page 117 for more details.
See “System Management Mode (SMM)” on page 211 for more
details regarding SMM.
Driven
The processor asserts SMIACT# after the last BRDY# of the last
pending bus cycle is sampled asserted (including all pending
write cycles) and after EWBE# is sampled asserted (if EWBE#
is masked off, then SMIACT# is not affected by EWBE#).
SMIACT# remains asserted until after the last BRDY# of the
last pending bus cycle associated with exiting SMM is sampled
asserted.
SMIACT# remains asserted during any flush, internal snoop, or
writeback cycle due to an inquire cycle.
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4.45
STPCLK# (Stop Clock)
Input, Internal Pullup
Summary
The assertion of STPCLK# causes the processor to enter the
Stop Grant state, during which the processor’s internal clock is
stopped. From the Stop Grant state, the processor can
subsequently transition to the Stop Clock state, in which the
bus clock CLK is stopped. Upon recognizing STPCLK#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the STPCLK# assertion by executing a Stop
Grant special bus cycle (see Table 25 on page 126)
4. Stops its internal clock after BRDY# of the Stop Grant
special bus cycle is sampled asserted and after EWBE# is
sampled asserted (if EWBE# is masked off, then entry into
the Stop Grant state is not affected by EWBE#)
5. Enters the Stop Clock state if the system logic stops the bus
clock CLK (optional)
See “Clock Control” on page 243 for more details regarding
clock control.
Sampled
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
System logic can drive the signal either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks.
STPCLK# must remain asserted until recognized, which is
indicated by the completion of the Stop Grant special cycle.
4.46
TCK (Test Clock)
Input, Internal Pullup
Summary
TCK is the clock for boundary-scan testing using the Test
Access Port (TAP). See “Boundary-Scan Test Access Port
(TAP)” on page 223 for details regarding the operation of the
TAP controller.
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Sampled
4.47
The processor always samples TCK, except while TRST# is
asserted.
TDI (Test Data Input)
Input, Internal Pullup
Summary
TDI is the serial test data and instruction input for
boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 223 for details
regarding the operation of the TAP controller.
Sampled
4.48
The processor samples TDI on every rising TCK edge but only
while in the Shift-IR and Shift-DR states.
TDO (Test Data Output)
Output
Summary
TDO is the serial test data and instruction output for
boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 223 for details
regarding the operation of the TAP controller.
Driven and Floated
The processor drives TDO on every falling TCK edge but only
while in the Shift-IR and Shift-DR states. TDO is floated at all
other times.
4.49
TMS (Test Mode Select)
Input, Internal Pullup
Summary
TMS specifies the test function and sequence of state changes
for boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 223 for details
regarding the operation of the TAP controller.
Sampled
The processor samples TMS on every rising TCK edge. If TMS is
sampled High for five or more consecutive clocks, the TAP
controller enters its Test-Logic-Reset state, regardless of the
controller state. This action is the same as that achieved by
asserting TRST#.
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4.50
TRST# (Test Reset)
Input, Internal Pullup
Summary
The assertion of TRST# initializes the Test Access Port (TAP) by
resetting its state machine to the Test-Logic-Reset state. See
“Boundary-Scan Test Access Port (TAP)” on page 223 for details
regarding the operation of the TAP controller.
Sampled
TRST# is a completely asynchronous input that does not
require a minimum setup and hold time relative to TCK. See
Table 69 on page 280 for the minimum pulse width requirement.
4.51
VCC2DET (VCC2 Detect)
Output
Summary
VCC2DET is internally tied to V (logic level 0) to indicate to
the system logic that it must supply the specified dual-voltage
SS
requirements to the V
and V
pins. The V
pins supply
CC2
CC3
CC2
voltage to the processor core, independent of the voltage
supplied to the I/O buffers on the V pins. Upon sampling
CC3
VCC2DET Low, system logic should sample VCC2H/L# to
identify core voltage requirements.
Driven
VCC2DET always equals 0 and is never floated—even during
the Tri-State Test mode.
4.52
VCC2H/L# (VCC2 High/Low)
Output
Summary
VCC2H/L# is internally tied to V (logic level 0) to indicate to
the system logic that it must supply the specified processor core
SS
voltage to the V
pins. The V
pins supply voltage to the
CC2
CC2
processor core, independent of the voltage supplied to the I/O
buffers on the V pins. Upon sampling VCC2DET Low to
CC3
identify dual-voltage processor requirements, system logic
should sample VCC2H/L# to identify the core voltage
requirements for 2.9V and 3.2V products (High) or 2.2V and
2.4 V products (Low).
Driven
VCC2H/L# always equals 0 and is never floated for 2.2V and
2.4 V products—even during the Tri-State Test mode. To ensure
proper operation for 2.9V and 3.2V products, system logic that
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samples VCC2H/L# should design a weak pullup resistor for
this signal.
Table 19. Output Pin Float Conditions
Name
VCC2DET
VCC2H/L#
Note:
Floated At:
Always Driven
Always Driven
Note
*
*
*
All outputs except VCC2DET, VCC2H/L#, and TDO float
during the Tri-State Test mode.
4.53
W/R# (Write/Read)
Output
Summary
The processor drives W/R# to indicate whether it is performing
a write or a read cycle on the bus. In addition, W/R# is used to
define other bus cycles, including interrupt acknowledge and
special cycles. See Table 25 on page 126 for more details.
Driven and Floated
W/R# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. W/R# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
W/R# is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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4.54
WB/WT# (Writeback or Writethrough)
Input
Summary
WB/WT#, together with PWT, specifies the data cache-line state
during cacheable read misses and write hits to shared cache
lines.
If WB/WT# = 0 or PWT = 1 during a cacheable read miss or write
hit to a shared cache line, the accessed line is cached in the
shared state. This is referred to as the writethrough state
because all write cycles to this cache line are driven externally
on the bus.
If WB/WT# = 1 and PWT = 0 during a cacheable read miss or a
write hit to a shared cache line, the accessed line is cached in
the exclusive state. Subsequent write hits to the same line
cause its state to transition from exclusive to modified. This is
referred to as the writeback state because the data cache can
contain modified cache lines that are subject to be written
back—referred to as a writeback cycle—as the result of an
inquire cycle, an internal snoop, a flush operation, or the
WBINVD instruction.
Sampled
WB/WT# is sampled on the clock edge that the first BRDY# or
NA# of a bus cycle is sampled asserted. If the cycle is a burst
read, WB/WT# is ignored during the last three assertions of
BRDY#. WB/WT# is sampled during memory read and
non-writeback write cycles and is ignored during all other types
of cycles.
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Table 20. Input Pin Types
Name
A20M#
Type
Note
Name
IGNNE#
Type
Note
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock
1
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
1
2
1
AHOLD
BF[2:0]
BOFF#
BRDY#
BRDYC#
CLK
INIT
4
7
INTR
INV
KEN#
NA#
NMI
2
5, 6
2
EADS#
EWBE#
FLUSH#
HOLD
Synchronous
Synchronous
Asynchronous
Synchronous
RESET
SMI#
STPCLK#
WB/WT#
8
2, 3
1
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
3. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be
sampled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which
RESET is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative
to the negation of RESET.
4. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold
time of two clocks relative to the negation of RESET.
5. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach
specification before it is negated.
6. During a warm reset, while CLK and VCC are within their specification, RESET must remain asserted for a minimum of 15 clocks
prior to its negation.
7. BRDYC# is also sampled during the falling transition of RESET. If RESET is driven synchronously, BRDYC# must meet the specified
hold time relative to the negation of RESET. If asserted asynchronously, BRDYC# must meet a minimum setup and hold time of
two clocks relative to the negation of RESET.
8. On the AMD-K6-2 processor Model 8/[F:8], if EFER[3] is set to 1, then EWBE# is ignored by the processor.
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Table 21. Output Pin Float Conditions
Name
A[4:3]
Floated At: (Note 1)
HLDA, AHOLD, BOFF#
HLDA, BOFF#
Note
2, 3
2
Name
HLDA
Floated At: (Note 1)
Note
Always Driven
HLDA, BOFF#
HLDA, BOFF#
HLDA, BOFF#
Always Driven
HLDA, BOFF#
HLDA, BOFF#
Always Driven
Always Driven
Always Driven
HLDA, BOFF#
ADS#
LOCK#
M/IO#
PCD
2
2
2
ADSC#
APCHK#
BE[7:0]#
BREQ
HLDA, BOFF#
2
Always Driven
HLDA, BOFF#
2
PCHK#
PWT
Always Driven
HLDA, BOFF#
2
2
CACHE#
D/C#
2
2
SCYC
HLDA, BOFF#
SMIACT#
VCC2DET
VCC2H/L#
W/R#
FERR#
HIT#
Always Driven
Always Driven
Always Driven
HITM#
Notes:
2
1. All outputs except VCC2DET, VCC2H/L#, and TDO float during the Tri-State Test mode.
2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.
3. Floated off the clock edge that AHOLD is sampled asserted.
Table 22. Input/Output Pin Float Conditions
Name
Floated At: (Note 1)
HLDA, AHOLD, BOFF#
HLDA, AHOLD, BOFF#
HLDA, BOFF#
Note
2,3
2,3
2
A[31:5]
AP
D[63:0]
DP[7:0]
Notes:
HLDA, BOFF#
2
1. All outputs except VCC2DET and TDO float during the Tri-State Test mode.
2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.
3. Floated off the clock edge that AHOLD is sampled asserted.
Table 23. Test Pins
Name
TCK
Type
Clock
Input
Output
Input
Input
Note
TDI
Sampled on the rising edge of TCK
Driven on the falling edge of TCK
Sampled on the rising edge of TCK
Asynchronous (Independent of TCK)
TDO
TMS
TRST#
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Table 24. Bus Cycle Definition
Bus Cycle Initiated
Generated
by the System
Generated by the Processor
M/IO#
D/C#
W/R#
CACHE#
KEN#
Code Read, Instruction Cache Line Fill
Code Read, Noncacheable
Code Read, Noncacheable
Encoding for Special Cycle
Interrupt Acknowledge
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
x
0
x
1
x
x
x
x
0
x
1
x
x
1
1
1
1
0
1
x
I/O Read
I/O Write
Memory Read, Data Cache Line Fill
Memory Read, Noncacheable
Memory Read, Noncacheable
Memory Write, Data Cache Writeback
Memory Write, Noncacheable
0
1
Note:
x means “don’t care”
Table 25. Special Cycles
Special Cycle
Stop Grant
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
x
x
Flush Acknowledge
(FLUSH# sampled asserted)
Writeback
(WBINVD instruction)
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
x
x
x
Halt
Flush (INVD, WBINVD
instruction)
Shutdown
Note:
x means “don’t care”
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5
Bus Cycles
The following sections describe and illustrate the timing and
relationship of bus signals during various types of bus cycles. A
representative set of bus cycles is illustrated.
5.1
Timing Diagrams
The timing diagrams illustrate the signals on the external local
bus as a function of time, as measured by the bus clock (CLK).
Throughout this chapter, the term clock refers to a single
bus-clock cycle. A clock extends from one rising CLK edge to
the next rising CLK edge. The processor samples and drives
most signals relative to the rising edge of CLK. The exceptions
to this rule include the following:
■ BF[2:0]—Sampled on the falling edge of RESET
■ FLUSH#, BRDYC#—Sampled on the falling edge of RESET,
also sampled on the rising edge of CLK
■ All inputs and outputs are sampled relative to TCK in
Boundary-Scan Test Mode. Inputs are sampled on the rising
edge of TCK, outputs are driven off of the falling edge of
TCK.
For each signal in the timing diagrams, the High level
represents 1, the Low level represents 0, and the Middle level
represents the floating (high-impedance) state. When both the
High and Low levels are shown, the meaning depends on the
signal. A single signal indicates ‘don’t care’. In the case of bus
activity, if both High and Low levels are shown, it indicates the
processor, alternate master, or system logic is driving a value,
but this value may or may not be valid. (For example, the value
on the address bus is valid only during the assertion of ADS#,
but addresses are also driven on the bus at other times.) Figure
53 defines the different waveform representations.
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Waveform
Description
Don’t care or bus is driven
Signal or bus is changing from Low to High
Signal or bus is changing from High to Low
Bus is changing
Bus is changing from valid to invalid
Signal or bus is floating
Denotes multiple clock periods
Figure 53. Waveform Definitions
For all active-High signals, the term asserted means the signal is
in the High-voltage state and the term negated means the signal
is in the Low-voltage state. For all active-Low signals, the term
asserted means the signal is in the Low-voltage state and the
term negated means the signal is in the High-voltage state.
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5.2
Bus State Machine Diagram
Bus State
Branch Condition
Addr
Yes
No
Pending
Request?
Address
Data
Data
Idle
Idle
No
Yes
Yes
No
Last BRDY#
Asserted?
NA# Sampled
Asserted?
Yes
Data-NA#
Data-NA#
Requested
Last BRDY#
Asserted?
No
Yes
Pending
Request?
No
No
NA# Sampled
Asserted?
Yes
Pipe-A
Pipeline
Address
Pipe-D
Trans
Pipeline
Data
No
Yes
Last BRDY#
Asserted?
Yes
Yes
No
NA# Sampled
Asserted?
Transition
Bus Transition?
No
Note: The processor transitions to the IDLE state on the clock edge on which BOFF# or RESET is sampled asserted.
Figure 54. Bus State Machine Diagram
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Idle
The processor does not drive the system bus in the Idle state
and remains in this state until a new bus cycle is requested. The
processor enters this state off the clock edge on which the last
BRDY# of a cycle is sampled asserted during the following
conditions:
■ The processor is in the Data state
■ The processor is in the Data-NA# Requested state and no
internal pending cycle is requested
In addition, the processor is forced into this state when the
system logic asserts RESET or BOFF#. The transition to this
state occurs on the clock edge on which RESET or BOFF# is
sampled asserted.
Address
Data
In this state, the processor drives ADS# to indicate the
beginning of a new bus cycle by validating the address and
control signals. The processor remains in this state for one clock
and unconditionally enters the Data state on the next clock
edge.
In the Data state, the processor drives the data bus during a
write cycle or expects data to be returned during a read cycle.
The processor remains in this state until either NA# or the last
BRDY# is sampled asserted. If the last BRDY# is sampled
asserted or both the last BRDY# and NA# are sampled asserted
on the same clock edge, the processor enters the Idle state. If
NA# is sampled asserted first, the processor enters the
Data-NA# Requested state.
Data-NA# Requested
If the processor samples NA# asserted while in the Data state
and the current bus cycle is not completed (the last BRDY# is
not sampled asserted), it enters the Data-NA# Requested state.
The processor remains in this state until either the last BRDY#
is sampled asserted or an internal pending cycle is requested. If
the last BRDY# is sampled asserted before the processor drives
a new bus cycle, the processor enters the Idle state (no internal
pending cycle is requested) or the Address state (processor has
a internal pending cycle).
In this state, the processor drives ADS# to indicate the
beginning of a new bus cycle by validating the address and
control signals. In this state, the processor is still waiting for the
current bus cycle to be completed (until the last BRDY# is
Pipeline Address
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sampled asserted). If the last BRDY# is not sampled asserted,
the processor enters the Pipeline Data state.
If the processor samples the last BRDY# asserted in this state, it
determines if a bus transition is required between the current
bus cycle and the pipelined bus cycle. A bus transition is
required when the data bus direction changes between bus
cycles, such as a memory write cycle followed by a memory read
cycle. If a bus transition is required, the processor enters the
Transition state for one clock to prevent data bus contention. If
a bus transition is not required, the processor enters the Data
state.
The processor does not transition to the Data-NA# Requested
state from the Pipeline Address state because the processor
does not begin sampling NA# until it has exited the Pipeline
Address state.
Pipeline Data
Two bus cycles are concurrently executing in this state. The
processor cannot issue any additional bus cycles until the
current bus cycle is completed. The processor drives the data
bus during write cycles or expects data to be returned during
read cycles for the current bus cycle until the last BRDY# of the
current bus cycle is sampled asserted.
If the processor samples the last BRDY# asserted in this state, it
determines if a bus transition is required between the current
bus cycle and the pipelined bus cycle. If the bus transition is
required, the processor enters the Transition state for one clock
to prevent data bus contention. If a bus transition is not
required, the processor enters the Data state (NA# was not
sampled asserted) or the Data-NA# Requested state (NA# was
sampled asserted).
Transition
The processor enters this state for one clock during data bus
transitions and enters the Data state on the next clock edge if
NA# is not sampled asserted. The sole purpose of this state is to
avoid bus contention caused by bus transitions during pipeline
operation.
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5.3
Memory Reads and Writes
The AMD-K6-2 processor performs single or burst memory bus
cycles. The single-transfer memory bus cycle transfers 1, 2, 4, or
8 bytes and requires a minimum of two clocks. Misaligned
instructions or operands result in a split cycle, which requires
multiple transactions on the bus. A burst cycle consists of four
back-to-back 8-byte (64-bit) transfers on the data bus.
Single-Transfer
Memory Read and
Write
Figure 55 shows a single-transfer read from memory, followed by
two single-transfer writes to memory. For the memory read
cycle, the processor asserts ADS# for one clock to validate the
bus cycle and also drives A[31:3], BE[7:0]#, D/C#, W/R#, and
M/IO# to the bus. The processor then waits for the system logic
to return the data on D[63:0] (with DP[7:0] for parity checking)
and assert BRDY#. The processor samples BRDY# on every clock
edge starting with the clock edge after the clock edge that
negates ADS#. See “BRDY# (Burst Ready)” on page 94.
During the read cycle, the processor drives PCD, PWT, and
CACHE# to indicate its caching and cache-coherency intent for
the access. The system logic returns KEN# and WB/WT# to
either confirm or change this intent. If the processor asserts
PCD and negates CACHE#, the accesses are noncacheable, even
though the system logic asserts KEN# during the BRDY# to
indicate its support for cacheability. The processor (which
drives CACHE#) and the system logic (which drives KEN#) must
agree in order for an access to be cacheable.
The processor can drive another cycle (in this example, a write
cycle) by asserting ADS# off the next clock edge after BRDY# is
sampled asserted. Therefore, an idle clock is guaranteed
between any two bus cycles. The processor drives D[63:0] with
valid data one clock edge after the clock edge on which ADS# is
asserted. To minimize processor idle times, the system logic
stores the address and data in write buffers, returns BRDY#, and
performs the store to memory later. If the processor samples
EWBE# negated during a write cycle, it suspends certain
activities until EWBE# is sampled asserted. See “EWBE#
(External Write Buffer Empty)” on page 101. In Figure 55, the
second write cycle occurs during the execution of a serializing
instruction. The processor delays the following cycle until
EWBE# is sampled asserted.
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Write Cycle (Next Cycle Delayed by EWBE#)
Write Cycle
Read Cycle
DATA IDLE ADDR DATA
ADDR DATA IDLE ADDR DATA
DATA IDLE
IDLE
IDLE
IDLE ADDR
IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BREQ
D[63:0]
DP[7:0]
CACHE#
EWBE#
KEN#
BRDY#
WB/WT#
Figure 55. Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE#
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Misaligned
Figure 56 shows a misaligned (split) memory read followed by a
misaligned memory write. Any cycle that is not aligned as
defined in “SCYC (Split Cycle)” on page 117 is considered
misaligned. When the processor encounters a misaligned
access, it determines the appropriate pair of bus cycles—each
with its own ADS# and BRDY#— required to complete the
access.
Single-Transfer
Memory Read and
Write
The AMD-K6-2 processor performs misaligned memory reads
and memory writes using least-significant bytes (LSBs) first
followed by most-significant bytes (MSBs). Table 26 shows the
order. In the first memory read cycle in Figure 56, the processor
reads the least-significant bytes. Immediately after the
processor samples BRDY# asserted, it drives the second bus
cycle to read the most-significant bytes to complete the
misaligned transfer.
Table 26. Bus-Cycle Order During Misaligned Transfers
Type of Access
Memory Read
Memory Write
First Cycle
LSBs
Second Cycle
MSBs
LSBs
MSBs
Similarly, the misaligned memory write cycle in Figure 56 on
page 135 transfers the LSBs to the memory bus first. In the next
cycle, after the processor samples BRDY# asserted, the MSBs
are written to the memory bus.
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Memory Write (Misaligned)
Memory Read (Misaligned)
DATA IDLE ADDR DATA
DATA IDLE
DATA
ADDR DATA DATA DATA IDLE
DATA IDLE ADDR DATA
ADDR DATA
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
LSB
MSB
LSB
MSB
D[63:0]
BRDY#
Figure 56. Misaligned Single-Transfer Memory Read and Write
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Burst Reads and
Pipelined Burst Reads
Figure 57 shows normal burst read cycles and a pipelined burst
read cycle. The AMD-K6-2 processor drives CACHE# and ADS#
together to specify that the current bus cycle is a burst cycle. If
the processor samples KEN# asserted with the first BRDY#, it
performs burst transfers. During the burst transfers, the system
logic must ignore BE[7:0]# and must return all eight bytes
beginning at the starting address the processor asserts on
A[31:3]. Depending on the starting address, the system logic
must determine the successive quadword addresses (A[4:3]) for
each transfer in a burst, as shown in Table 27. The processor
expects the second, third, and fourth quadwords to occur in the
sequences shown in Table 27.
Table 27. A[4:3] Address-Generation Sequence During Bursts
Address Driven By
Processor on A[4:3]
A[4:3] Addresses of Subsequent
Quadwords* Generated By System Logic
Quadword 1
Quadword 2
Quadword 3
Quadword 4
00b
01b
10b
11b
01b
00b
11b
10b
10b
11b
00b
01b
11b
10b
01b
00b
Note:
*
quadword = 8 bytes
In Figure 57, the processor drives CACHE# throughout all burst
read cycles. In the first burst read cycle, the processor drives
ADS# and CACHE#, then samples BRDY# on every clock edge
starting with the clock edge after the clock edge that negates
ADS#. The processor samples KEN# asserted on the clock edge
on which the first BRDY# is sampled asserted, executes a
32-byte burst read cycle, and expects a total of four BRDY#
signals. An ideal no-wait state access is shown in Figure 57,
whereas most system logic solutions add wait states between
the transfers.
The second burst read cycle illustrates a similar sequence, but
the processor samples NA# asserted on the same clock edge
that the first BRDY# is sampled asserted. NA# assertion
indicates the system logic is requesting the processor to output
the next address early (also known as a pipeline transfer
request). Without waiting for the current cycle to complete, the
processor drives ADS# and related signals for the next burst
cycle. Pipelining can reduce processor cycle-to-cycle idle times.
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Burst Read
Burst Read
Pipelined Burst Read
DATA PIPE
ADDR DATA DATA DATA DATA IDLE ADDR DATA DATA
DATA DATA DATA DATA IDLE
-NA -ADDR
CLK
ADDR1
ADDR2
ADDR3
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
NA#
DATA1
DATA2
DATA3
D[63:0]
CACHE#
KEN#
BRDY#
Figure 57. Burst Reads and Pipelined Burst Reads
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Burst Writeback
Figure 58 shows a burst read followed by a writeback
transaction. The AMD-K6-2 processor initiates writebacks
under the following conditions:
■ Replacement—If a cache-line fill is initiated for a cache line
currently filled with valid entries, the processor selects a
line for replacement based on a least-recently-used (LRU)
algorithm
for
the
instruction
cache,
and
a
least-recently-allocated (LRA) algorithm for the data cache.
Before a replacement is made to a L1 data cache line that is
in the modified state, the modified line is scheduled to be
written back to memory.
■ Internal Snoop—The processor snoops its instruction cache
during read or write misses to its data cache, and it snoops
its data cache during read misses to its instruction cache.
This snooping is performed to determine whether the same
address is stored in both caches, a situation that is taken to
imply the occurrence of self-modifying code. If a snoop hits a
data cache line in the modified state, the line is written back
to memory before being invalidated.
■ WBINVD Instruction—When the processor executes a
WBINVD instruction, it writes back all modified lines in the
data cache and then invalidates all lines in both caches.
■ Cache Flush—When the processor samples FLUSH#
asserted, it executes a flush acknowledge special cycle and
writes back all modified lines in the data cache and then
invalidates all lines in both caches.
The processor drives writeback cycles during inquire or cache
flush cycles. The writeback shown in Figure 58 is caused by a
cache-line replacement. The processor completes the burst read
cycle that fills the cache line. Immediately following the burst
read cycle is the burst writeback cycle that represents the
modified line to be written back to memory. D[63:0] are driven
one clock edge after the clock edge on which ADS# is asserted
and are subsequently changed off the clock edge on which each
of the four BRDY# signals of the burst cycle are sampled
asserted.
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Burst Read
Burst Writeback from L1 Cache
DATA
DATA DATA
DATA
DATA DATA
ADDR
DATA
IDLE
ADDR
DATA
IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
CACHE#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
WB/WT#
Figure 58. Burst Writeback due to Cache-Line Replacement
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5.4
I/O Read and Write
Basic I/O Read and
Write
The processor accesses I/O when it executes an I/O instruction
(for example, IN or OUT). Figure 59 shows an I/O read followed
by an I/O write. The processor drives M/IO# Low and D/C# High
during I/O cycles. In this example, the first cycle shows a single
wait state I/O read cycle. It follows the same sequence as a
single-transfer memory read cycle. The processor drives ADS#
to initiate the bus cycle, then it samples BRDY# on every clock
edge starting with the clock edge after the clock edge that
negates ADS#. The system logic must return BRDY# to
complete the cycle. When the processor samples BRDY#
asserted, it can assert ADS# for the next cycle off the next clock
edge. (In this example, an I/O write cycle.)
The I/O write cycle is similar to a memory write cycle, but the
processor drives M/IO# low during an I/O write cycle. The
processor asserts ADS# to initiate the bus cycle. The processor
drives D[63:0] with valid data one clock edge after the clock
edge on which ADS# is asserted. The system logic must assert
BRDY# when the data is properly stored to the I/O destination.
The processor samples BRDY# on every clock edge starting with
the clock edge after the clock edge that negates ADS#. In this
example, two wait states are inserted while the processor waits
for BRDY# to be asserted.
I/O Write Cycle
I/O Read Cycle
DATA
IDLE
IDLE
DATA
DATA
DATA
DATA
ADDR
ADDR
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
BRDY#
Figure 59. Basic I/O Read and Write
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Misaligned I/O Read
and Write
Table 28 shows the misaligned I/O read and write cycle order
executed by the AMD-K6-2 processor. In Figure 60, the
least-significant bytes (LSBs) are transferred first. Immediately
after the processor samples BRDY# asserted, it drives the
second bus cycle to transfer the most-significant bytes (MSBs)
to complete the misaligned bus cycle.
Table 28. Bus-Cycle Order During Misaligned I/O Transfers
Type of Access
I/O Read
First Cycle
LSBs
Second Cycle
MSBs
I/O Write
LSBs
MSBs
Misaligned I/O Write
Misaligned I/O Read
ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA
DATA
IDLE ADDR DATA
DATA
DATA
DATA IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
SCYC
D[63:0]
BRDY#
LSB
MSB
LSB
MSB
Figure 60. Misaligned I/O Transfer
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5.5
Inquire and Bus Arbitration Cycles
The AMD-K6-2 processor provides built-in level-one data and
instruction caches. Each cache is 32 Kbytes and two-way
set-associative. The system logic or other bus master devices
can initiate an inquire cycle to maintain cache/memory
coherency. In response to the inquire cycle, the processor
compares the inquire address with its cache tag addresses in
both caches, and, if necessary, updates the MESI state of the
cache line and performs writebacks to memory.
An inquire cycle can be initiated by asserting AHOLD, BOFF#,
or HOLD. AHOLD is exclusively used to support inquire cycles.
During AHOLD-initiated inquire cycles, the processor only
floats the address bus. BOFF# provides the fastest access to the
bus because it aborts any processor cycle that is in-progress,
whereas AHOLD and HOLD both permit an in-progress bus
cycle to complete. During HOLD-initiated and BOFF#-initiated
inquire cycles, the processor floats all of its bus-driving signals.
Hold and Hold
Acknowledge Cycle
The system logic or another bus device can assert HOLD to
initiate an inquire cycle or to gain full control of the bus. When
the AMD-K6-2 processor samples HOLD asserted, it completes
any in-progress bus cycle and asserts HLDA to acknowledge
release of the bus. The processor floats the following signals off
the same clock edge that HLDA is asserted:
■ A[31:3]
■ ADS#
■ DP[7:0]
■ LOCK#
■ M/IO#
■ PCD
■ AP#
■ BE[7:0]#
■ CACHE#
■ D[63:0]
■ D/C#
■ PWT
■ SCYC
■ W/R#
Figure 61 shows a basic HOLD/HLDA operation. In this
example, the processor samples HOLD asserted during the
memory read cycle. It continues the current memory read cycle
until BRDY# is sampled asserted. The processor drives HLDA
and floats its outputs one clock edge after the last BRDY# of the
cycle is sampled asserted. The system logic can assert HOLD for
as long as it needs to utilize the bus. The processor samples
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HOLD on every clock edge but does not assert HLDA until any
in-progress cycle or sequence of locked cycles is completed.
When the processor samples HOLD negated during a hold
acknowledge cycle, it negates HLDA off the next clock edge.
The processor regains control of the bus and can assert ADS#
off the same clock edge on which HLDA is negated.
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
HOLD
HLDA
BRDY#
Figure 61. Basic HOLD/HLDA Operation
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HOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
Figure 62 shows a HOLD-initiated inquire cycle. In this
example, the processor samples HOLD asserted during the
burst memory read cycle. The processor completes the current
cycle (until the last expected BRDY# is sampled asserted),
asserts HLDA and floats its outputs as described on page 142.
The system logic drives an inquire cycle within the hold
acknowledge cycle. It asserts EADS#, which validates the
inquire address on A[31:5]. If EADS# is sampled asserted
before HOLD is sampled negated, the processor recognizes it as
a valid inquire cycle.
In Figure 62, the processor asserts HIT# and negates HITM# on
the clock edge after the clock edge on which EADS# is sampled
asserted, indicating the current inquire cycle hit a shared or
exclusive cache line. (Shared and exclusive cache lines have not
been modified and do not need to be written back.) During an
inquire cycle, the processor samples INV to determine whether
the addressed cache line found in the processor’s instruction or
data cache transitions to the invalid state or the shared state. In
this example, the processor samples INV asserted with EADS#,
which invalidates the cache line.
The system logic can negate HOLD off the same clock edge on
which EADS# is sampled asserted. The processor continues
driving HIT# in the same state until the next inquire cycle.
HITM# is not asserted unless HIT# is asserted.
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Burst Memory Read
Inquire
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
HOLD
HLDA
EADS#
INV
Figure 62. HOLD-Initiated Inquire Hit to Shared or Exclusive Line
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HOLD-Initiated
Inquire Hit to
Modified Line
Figure 63 shows the same sequence as Figure 62, but in Figure
63 the inquire cycle hits a modified line and the processor
asserts both HIT# and HITM#. In this example, the processor
performs a writeback cycle immediately after the inquire cycle.
It updates the modified cache line to external memory
(normally, external cache or DRAM). The processor uses the
address (A[31:5]) that was latched during the inquire cycle to
perform the writeback cycle. The processor asserts HITM#
throughout the writeback cycle and negates HITM# one clock
edge after the last expected BRDY# of the writeback is sampled
asserted.
When the processor samples EADS# during the inquire cycle, it
also samples INV to determine the cache line MESI state after
the inquire cycle. If INV is sampled asserted during an inquire
cycle, the processor transitions the line (if found) to the invalid
state, regardless of its previous state. The cache line
invalidation operation is not visible on the bus. If INV is
sampled negated during an inquire cycle, the processor
transitions the line (if found) to the shared state. In Figure 63
the processor samples INV asserted during the inquire cycle.
In a HOLD-initiated inquire cycle, the system logic can negate
HOLD off the same clock edge on which EADS# is sampled
asserted. The processor drives HIT# and HITM# on the clock
edge after the clock edge on which EADS# is sampled asserted.
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Burst Memory Read
Writeback Cycle
Inquire
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
HOLD
HLDA
EADS#
INV
Figure 63. HOLD-Initiated Inquire Hit to Modified Line
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AHOLD-Initiated
Inquire Miss
AHOLD can be asserted by the system to initiate one or more
inquire cycles. To allow the system to drive the address bus
during an inquire cycle, the processor floats A[31:3] and AP off
the clock edge on which AHOLD is sampled asserted. The data
bus and all other control and status signals remain under the
control of the processor and are not floated. This functionality
allows a bus cycle in progress when AHOLD is sampled asserted
to continue to completion. The processor resumes driving the
address bus off the clock edge on which AHOLD is sampled
negated.
In Figure 64, the processor samples AHOLD asserted during the
memory burst read cycle, and it floats the address bus off the
same clock edge on which it samples AHOLD asserted. While
the processor still controls the bus, it completes the current
cycle until the last expected BRDY# is sampled asserted. The
system logic drives EADS# with an inquire address on A[31:5]
during an inquire cycle. The processor samples EADS# asserted
and compares the inquire address to its tag address in both the
instruction and data caches. In Figure 64, the inquire address
misses the tag address in the processor (both HIT# and HITM#
are negated). Therefore, the processor proceeds to the next
cycle when it samples AHOLD negated. (The processor can
drive a new cycle by asserting ADS# off the same clock edge that
it samples AHOLD negated.)
For an AHOLD-initiated inquire cycle to be recognized, the
processor must sample AHOLD asserted for at least two
consecutive clocks before it samples EADS# asserted. If the
processor detects an address parity error during an inquire
cycle, APCHK# is asserted for one clock. The system logic must
respond appropriately to the assertion of this signal.
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Inquire
Read
CLK
A[31:3]
BE[7:0]#
AP
APCHK#
ADS#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 64. AHOLD-Initiated Inquire Miss
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AHOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
In Figure 65, the processor asserts HIT# and negates HITM# off
the clock edge after the clock edge on which EADS# is sampled
asserted, indicating the current inquire cycle hits either a
shared or exclusive line. (HIT# is driven in the same state until
the next inquire cycle.) The processor samples INV asserted
during the inquire cycle and transitions the line to the invalid
state regardless of its previous state.
During an AHOLD-initiated inquire cycle, the processor
samples AHOLD on every clock edge until it is negated. In
Figure 65, the processor asserts ADS# off the same clock on
which AHOLD is sampled negated. If the inquire cycle hits a
modified line, the processor performs a writeback cycle before
it drives a new bus cycle. The next section describes the
AHOLD-initiated inquire cycle that hits a modified line.
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Inquire
Burst Memory Read
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 65. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
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AHOLD-Initiated
Inquire Hit to
Modified Line
Figure 66 shows an AHOLD-initiated inquire cycle that hits a
modified line. During the inquire cycle in this example, the
processor asserts both HIT# and HITM# on the clock edge after
the clock edge that it samples EADS# asserted. This condition
indicates that the cache line exists in the processor’s data cache
in the modified state.
If the inquire cycle hits a modified line, the processor performs
a writeback cycle immediately after the inquire cycle to update
the modified cache line to shared memory (normally external
cache or DRAM). In Figure 66, the system logic holds AHOLD
asserted throughout the inquire cycle and the processor
writeback cycle. In this case, the processor is not driving the
address bus during the writeback cycle because AHOLD is
sampled asserted. The system logic writes the data to memory
by using its latched copy of the inquire cycle address. If the
processor samples AHOLD negated before it performs the
writeback cycle, it drives the writeback cycle by using the
address (A[31:5]) that it latched during the inquire cycle.
If INV is sampled asserted during an inquire cycle, the
processor transitions the line (if found) to the invalid state,
regardless of its previous state (the cache invalidation
operation is not visible on the bus). If INV is sampled negated
during an inquire cycle, the processor transitions the line (if
found) to the shared state. In either case, if the line is found in
the modified state, the processor writes it back to memory
before changing its state. Figure 66 shows that the processor
samples INV asserted during the inquire cycle and invalidates
the cache line after the inquire cycle.
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Burst Memory Read
Inquire
Writeback
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 66. AHOLD-Initiated Inquire Hit to Modified Line
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AHOLD Restriction
When the system logic drives an AHOLD-initiated inquire
cycle, it must assert AHOLD for at least two clocks before it
asserts EADS#. This requirement guarantees the processor
recognizes and responds to the inquire cycle properly. The
processor’s 32 address bus drivers turn on almost immediately
after AHOLD is sampled negated. If the processor switches the
data bus (D[63:0] and DP[7:0]) during a write cycle off the same
clock edge that switches the address bus (A[31:3] and AP), the
processor switches 102 drivers simultaneously, which can lead
to ground-bounce spikes. Therefore, before negating AHOLD
the following restrictions must be observed by the system logic:
■ When the system logic negates AHOLD during a write cycle,
it must ensure that AHOLD is not sampled negated on the
clock edge on which BRDY# is sampled asserted (See Figure
67).
■ When the system logic negates AHOLD during a writeback
cycle, it must ensure that AHOLD is not sampled negated on
the clock edge on which ADS# is negated (See Figure 67).
■ When a write cycle is pipelined into a read cycle, AHOLD
must not be sampled negated on the clock edge after the
clock edge on which the last BRDY# of the read cycle is
sampled asserted to avoid the processor simultaneously
driving the data bus (for the pending write cycle) and the
address bus off this same clock edge.
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CLK
ADS#
W/R#
HITM#
EADS#
D[63:0]
BRDY#
Legal AHOLD negation during write cycle
AHOLD
Illegal AHOLD negation during write cycle
The system must ensure that AHOLD is not sampled negated on the clock edge that ADS# is negated.
The system must ensure that AHOLD is not sampled negated on the clock edge on which BRDY# is sampled
asserted.
Figure 67. AHOLD Restriction
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Bus Backoff (BOFF#)
BOFF# provides the fastest response among bus-hold inputs.
Either the system logic or another bus master can assert BOFF#
to gain control of the bus immediately. BOFF# is also used to
resolve potential deadlock problems that arise as a result of
inquire cycles. The processor samples BOFF# on every clock
edge. If BOFF# is sampled asserted, the processor
unconditionally aborts any cycles in progress and transitions to
a bus hold state. (See “BOFF# (Backoff)” on page 93.) Figure 68
shows a read cycle that is aborted when the processor samples
BOFF# asserted even though BRDY# is sampled asserted on the
same clock edge. The read cycle is restarted after BOFF# is
sampled negated (KEN# must be in the same state during the
restarted cycle as its state during the aborted cycle).
During a BOFF#-initiated inquire cycle that hits a shared or
exclusive line, the processor samples BOFF# negated and
restarts any bus cycle that was aborted when BOFF# was
asserted. If a BOFF#-initiated inquire cycle hits a modified line,
the processor performs a writeback cycle before it restarts the
aborted cycle.
If the processor samples BOFF# asserted on the same clock
edge that it asserts ADS#, ADS# is floated but the system logic
may erroneously interpret ADS# as asserted. In this case, the
system logic must properly interpret the state of ADS# when
BOFF# is negated.
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Read
Restart Read Cycle
Back Off Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BOFF#
D[63:0]
BRDY#
Figure 68. BOFF# Timing
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Locked Cycles
The processor asserts LOCK# during a sequence of bus cycles to
ensure the cycles are completed without allowing other bus
masters to intervene. Locked operations can consist of two to
five cycles. LOCK# is asserted during the following operations:
■ An interrupt acknowledge sequence
■ Descriptor Table accesses
■ Page Directory and Page Table accesses
■ XCHG instruction
■ An instruction with an allowable LOCK prefix
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s cache are
flushed and invalidated from the cache prior to the locked
operation. If the cache line is in the modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any data read during a locked operation is not cached. The
processor negates LOCK# for at least one clock between
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
The processor asserts SCYC during misaligned locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
Basic Locked
Operation
Figure 69 shows a pair of read-write bus cycles. It represents a
typical read-modify-write locked operation. The processor
asserts LOCK# off the same clock edge that it asserts ADS# of
the first bus cycle in the locked operation and holds it asserted
until the last expected BRDY# of the last bus cycle in the locked
operation is sampled asserted. (The processor negates LOCK#
off the same clock edge.)
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Locked Write Cycle
Locked Read Cycle
ADDR
IDLE IDLE
IDLE IDLE ADDR DATA DATA DATA
ADDR DATA DATA DATA
CLK
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
SCYC
D[63:0]
BRDY#
Figure 69. Basic Locked Operation
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Locked Operation
with BOFF#
Intervention
Figure 70 shows BOFF# asserted within a locked read-write pair
of bus cycles. In this example, the processor asserts LOCK#
with ADS# to drive a locked memory read cycle followed by a
locked memory write cycle. During the locked memory write
cycle in this example, the processor samples BOFF# asserted.
The processor immediately aborts the locked memory write
cycle and floats all its bus-driving signals, including LOCK#.
The system logic or another bus master can initiate an inquire
cycle or drive a new bus cycle one clock edge after the clock
edge on which BOFF# is sampled asserted. If the system logic
drives a BOFF#-initiated inquire cycle and hits a modified line,
the processor performs a writeback cycle before it restarts the
locked cycle (the processor asserts LOCK# during the
writeback cycle).
In Figure 70, the processor immediately restarts the aborted
locked write cycle by driving the bus off the clock edge on
which BOFF# is sampled negated. The system logic must ensure
the processor results for interrupted and uninterrupted locked
cycles are consistent. That is, the system logic must guarantee
the memory accessed by the processor is not modified during
the time another bus master controls the bus.
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Locked Read Cycle
Restart Write Cycle
Aborted Write Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
BOFF#
D[63:0]
BRDY#
Figure 70. Locked Operation with BOFF# Intervention
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Interrupt
Acknowledge
In response to recognizing the system’s maskable interrupt
(INTR), the processor drives an interrupt acknowledge cycle at
the next instruction boundary. During an interrupt
acknowledge cycle, the processor drives a locked pair of read
cycles as shown in Figure 71. The first read cycle is not
functional, and the second read cycle returns the interrupt
number on D[7:0] (00h–FFh). Table 29 shows the state of the
signals during an interrupt acknowledge cycle.
Table 29. Interrupt Acknowledge Operation Definition
Processor Outputs
D/C#
First Bus Cycle
Second Bus Cycle
Low
Low
Low
Low
M/IO#
W/R#
Low
Low
BE[7:0]#
A[31:3]
EFh
FEh (low byte enabled)
0000_0000h
0000_0000h
Interrupt number expected from interrupt
controller on D[7:0]
D[63:0]
(ignored)
The system logic can drive INTR either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. To ensure it
is recognized, INTR must remain asserted until an interrupt
acknowledge sequence is complete.
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Interrupt Acknowledge Cycles
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
LOCK#
INTR
Interrupt Number
D[63:0]
KEN#
BRDY#
Figure 71. Interrupt Acknowledge Operation
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5.6
Special Bus Cycles
The AMD-K6-2 processor drives special bus cycles that include
stop grant, flush acknowledge, cache writeback invalidation,
halt, cache invalidation, and shutdown cycles. During all
special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1. BE[7:0]# and
A[31:3] are driven to differentiate among the special cycles, as
shown in Table 30. The system logic must return BRDY# in
response to all processor special cycles.
Table 30. Encodings For Special Bus Cycles
BE[7:0]#
FBh
A[4:3]*
10b
Special Bus Cycle
Cause
Stop Grant
STPCLK# sampled asserted
EFh
00b
Flush Acknowledge FLUSH# sampled asserted
F7h
00b
Writeback
Halt
WBINVD instruction
HLT instruction
FBh
00b
FDh
00b
Flush
INVD,WBINVD instruction
Triple fault
FEh
00b
Shutdown
Note:
*
A[31:5] = 0
Basic Special Bus
Cycle
Figure 72 shows a basic special bus cycle. The processor drives
D/C# = 0, M/IO# = 0, and W/R# = 1 off the same clock edge that
it asserts ADS#. In this example, BE[7:0]# = FBh and A[31:3] =
0000_0000h, which indicates that the special cycle is a halt
special cycle (See Table 30). A halt special cycle is generated
after the processor executes the HLT instruction.
If the processor samples FLUSH# asserted, it writes back any
data cache lines that are in the modified state and invalidates
all lines in the instruction and data cache. The processor then
drives a flush acknowledge special cycle.
If the processor executes a WBINVD instruction, it drives a
writeback special cycle after the processor completes
invalidating and writing back the cache lines.
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Halt Cycle
CLK
A[31:3]
A[4:3] = 00b
FBh
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BRDY#
Figure 72. Basic Special Bus Cycle (Halt Cycle)
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Shutdown Cycle
In Figure 73, a shutdown (triple fault) occurs in the first half of
the waveform, and a shutdown special cycle follows in the
second half. The processor enters shutdown when an interrupt
or exception occurs during the handling of a double fault (INT
8), which amounts to a triple fault. When the processor
encounters a triple fault, it stops its activity on the bus and
generates the shutdown special bus cycle (BE[7:0]# = FEh).
The system logic must assert NMI, INIT, RESET, or SMI# to get
the processor out of the shutdown state.
Shutdown Occurs
(Triple Fault)
Shutdown Special Cycle
CLK
A[4:3] = 00b
FEh
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
Figure 73. Shutdown Cycle
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Stop Grant and Stop
Clock States
Figure 74 and Figure 75 show the processor transition from
normal execution to the Stop Grant state, then to the Stop
Clock state, back to the Stop Grant state, and finally back to
normal execution. The series of transitions begins when the
processor samples STPCLK# asserted. On recognizing a
STPCLK# interrupt at the next instruction retirement
boundary, the processor performs the following actions, in the
order shown:
1. Its instruction pipelines are flushed
2. All pending and in-progress bus cycles are completed
3. The STPCLK# assertion is acknowledged by executing a
Stop Grant special bus cycle
4. Its internal clock is stopped after BRDY# of the Stop Grant
special bus cycle is sampled asserted and after EWBE# is
sampled asserted (if EWBE# is masked off, then entry into
the Stop Grant state is not affected by EWBE#)
5. The Stop Clock state is entered if the system logic stops the
bus clock CLK (optional)
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
The system logic drives the signal either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. STPCLK#
must remain asserted until recognized, which is indicated by
the completion of the Stop Grant special cycle.
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Stop Clock
Stop Grant Special Cycle
STPCLK# Sampled Asserted
CLK
A[4:3] = 10b
FBh
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
CACHE#
STPCLK#
D[63:0]
KEN#
BRDY#
Figure 74. Stop Grant and Stop Clock Modes, Part 1
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Stop Clock
STPCLK# Sampled Negated Normal
Stop Grant State
(Re-entered after PLL stabilization)
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
CACHE#
STPCLK#
D[63:0]
KEN#
BRDY#
Figure 75. Stop Grant and Stop Clock Modes, Part 2
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INIT-Initiated
Transition from
Protected Mode to
Real Mode
INIT is typically asserted in response to a BIOS interrupt that
writes to an I/O port. This interrupt is often in response to a
Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar
to port 64h in the keyboard controller) that asserts INIT. INIT is
also used to support 80286 software that must return to Real
mode after accessing extended memory in Protected mode.
The assertion of INIT causes the processor to empty its
pipelines, initialize most of its internal state, and branch to
address FFFF_FFF0h—the same instruction execution starting
point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
MMX state, Model-Specific Registers (MSRs), the CD and NW
bits of the CR0 register, the time stamp counter, and other
specific internal resources.
Figure 76 shows an example in which the operating system
writes to an I/O port, causing the system logic to assert INIT.
The sampling of INIT asserted starts an extended microcode
sequence that terminates with a code fetch from FFFF_FFF0h,
the reset location. INIT is sampled on every clock edge but is
not recognized until the next instruction boundary. During an
I/O write cycle, it must be sampled asserted a minimum of three
clock edges before BRDY# is sampled asserted if it is to be
recognized on the boundary between the I/O write instruction
and the following instruction. If INIT is asserted synchronously,
it can be asserted for a minimum of one clock. If it is asserted
asynchronously, it must have been negated for a minimum of
two clocks, followed by an assertion of a minimum of two clocks.
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INIT Sampled Asserted
Code Fetch
FFFF_FFF0h
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
INIT
Figure 76. INIT-Initiated Transition from Protected Mode to Real Mode
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6
Power-on Configuration and Initialization
On power-on the system logic must reset the AMD-K6-2
processor by asserting the RESET signal. When the processor
samples RESET asserted, it immediately flushes and initializes
all internal resources and its internal state, including its
pipelines and caches, the floating-point state, the MMX and
3DNow! states, and all registers. Then the processor jumps to
address FFFF_FFF0h to start instruction execution.
6.1
Signals Sampled During the Falling Transition of RESET
FLUSH# FLUSH# is sampled on the falling transition of RESET to
determine if the processor begins normal instruction execution
or enters Tri-State Test mode. If FLUSH# is High during the
falling transition of RESET, the processor unconditionally runs
its Built-In Self Test (BIST), performs the normal reset
functions, then jumps to address FFFF_FFF0h to start
instruction execution. (See “Built-In Self-Test (BIST)” on page
221 for more details.) If FLUSH# is Low during the falling
transition of RESET, the processor enters Tri-State Test mode.
(See “Tri-State Test Mode” on page 222 and “FLUSH# (Cache
Flush)” on page 103 for more details.)
BF[2:0] The internal operating frequency of the processor is
determined by the state of the bus frequency signals BF[2:0]
when they are sampled during the falling transition of RESET.
The frequency of the CLK input signal is multiplied internally
by a ratio defined by BF[2:0]. (See “BF[2:0] (Bus Frequency)”
on page 92 for the processor-clock to bus-clock ratios.)
BRDYC# BRDYC# is sampled on the falling transition of RESET to
configure the drive strength of A[20:3], ADS#, HITM#, and
W/R#. If BRDYC# is Low during the fall of RESET, these
outputs are configured using higher drive strengths than the
standard strength. If BRDYC# is High during the fall of RESET,
the standard strength is selected. (See “BRDYC# (Burst Ready
Copy)” on page 95 for more details.)
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6.2
RESET Requirements
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V
CC
reach specification. (See “CLK Switching Characteristics” on
page 267 for clock specifications. See “Electrical Data” on page
253 for V specifications.)
CC
During a warm reset while CLK and V
are within
CC
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
6.3
State of Processor After RESET
Output Signals
Table 31 shows the state of all processor outputs and
bidirectional signals immediately after RESET is sampled
asserted.
Table 31. Output Signal State After RESET
Signal
A[31:3], AP
State
Floating
High
Signal
State
High
Low
Low
High
Low
Low
High
Floating
Low
Low
Low
–
LOCK#
M/IO#
PCD
ADS#, ADSC#
APCHK#
BE[7:0]#
BREQ
High
Floating
Low
PCHK#
PWT
CACHE#
D/C#
High
SCYC
Low
SMIACT#
TDO
D[63:0], DP[7:0]
FERR#
Floating
High
VCC2DET
VCC2H/L#
W/R#
HIT#
High
HITM#
High
HLDA
Low
–
Registers
Table 32 on page 175 shows the state of all architecture
registers and Model-Specific Registers (MSRs) after the
processor has completed its initialization due to the recognition
of the assertion of RESET.
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Table 32. Register State After RESET
Register
State (hex)
Notes
GDTR
base:0000_0000h limit:0FFFFh
base:0000_0000h limit:0FFFFh
0000h
IDTR
TR
LDTR
0000h
EIP
FFFF_FFF0h
0000_0002h
0000_0000h
0000_0000h
0000_0000h
0000_058Xh
0000_0000h
0000_0000h
0000_0000h
0000_0000h
F000h
EFLAGS
EAX
1
2
EBX
ECX
EDX
ESI
EDI
EBP
ESP
CS
SS
DS
0000h
0000h
ES
0000h
FS
0000h
GS
0000h
FPU Stack R7–R0
FPU Control Word
FPU Status Word
FPU Tag Word
FPU Instruction Pointer
FPU Data Pointer
FPU Opcode Register
0000_0000_0000_0000_0000h
0040h
3
3
3
3
3
3
3
0000h
5555h
0000_0000_0000h
0000_0000_0000h
000_0000_0000b
Notes:
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful.
If EAX is non-zero, BIST failed.
2. EDX contains the AMD-K6-2 processor signature, where X indicates the processor Stepping ID.
3. The contents of these registers are preserved following the recognition of INIT.
4. The CD and NW bits of CR0 are preserved following the recognition of INIT.
5. UWCCR, PSOR, and PFIR are implemented only on AMD-K6-2 processor Model 8/[F:8].
6. “S” represents the Stepping. “B” represents PSOR[3:0], where PSOR[3] equals 0, and
PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of
RESET.
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Table 32. Register State After RESET (continued)
Register
CR0
State (hex)
Notes
6000_0010h
0000_0000h
4
CR2
CR3
0000_0000h
CR4
0000_0000h
DR7
0000_0400h
DR6
FFFF_0FF0h
DR3
0000_0000h
DR2
0000_0000h
DR1
0000_0000h
DR0
0000_0000h
MCAR
MCTR
TR12
TSC
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
3
3
3
3
0000_0000_0000_0000h (Model 8/[7:0])
0000_0000_0000_0002h (Model 8/[F:8])
0000_0000_0000_0000h
EFER
3
STAR
WHCR
UWCCR
PSOR
3
3
0000_0000_0000_0000h
0000_0000_0000_0000h
3, 5
3, 5, 6
3, 5
0000_0000_0000_01SBh
PFIR
0000_0000_0000_0000h
Notes:
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful.
If EAX is non-zero, BIST failed.
2. EDX contains the AMD-K6-2 processor signature, where X indicates the processor Stepping ID.
3. The contents of these registers are preserved following the recognition of INIT.
4. The CD and NW bits of CR0 are preserved following the recognition of INIT.
5. UWCCR, PSOR, and PFIR are implemented only on AMD-K6-2 processor Model 8/[F:8].
6. “S” represents the Stepping. “B” represents PSOR[3:0], where PSOR[3] equals 0, and
PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of
RESET.
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6.4
State of Processor After INIT
The recognition of the assertion of INIT causes the processor to
empty its pipelines, to initialize most of its internal state, and to
branch to address FFFF_FFF0h—the same instruction
execution starting point used after RESET. Unlike RESET, the
processor preserves the contents of its caches, the
floating-point state, the MMX and 3DNow! states, MSRs, and
the CD and NW bits of the CR0 register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
and preserved during the INIT process and are handled
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
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7
Cache Organization
The following sections describe the basic architecture and
resources of the AMD-K6-2 processor internal caches.
The performance of the AMD-K6-2 processor is enhanced by a
writeback level-one (L1) cache. The cache is organized as a
separate 32-Kbyte instruction cache and a 32-Kbyte data cache,
each with two-way set associativity (See Figure 77). The cache
line size is 32 bytes, and lines are fetched from main memory
using an efficient, pipelined burst transaction. As the
instruction cache is filled, each instruction byte is analyzed for
instruction boundaries using predecode logic. Predecoding
annotates each instruction byte with information that later
enables the decoders to efficiently decode multiple instructions
simultaneously. Translation lookaside buffers (TLB) are also
used to translate linear addresses to physical addresses. The
instruction cache is associated with a 64-entry TLB while the
data cache is associated with a 128-entry TLB.
32-Kbyte Instruction Cache
Tag
RAM
State Tag
Bit RAM
State
Bit
Way 0
Way 1
64-Entry TLB
System Bus
Interface Unit
Processor
Core
Pre-Decode Instruction Cache
128-Entry TLB
MESI Tag
Tag
RAM
MESI
Bits
Way 0
Way 1
Bits RAM
32-Kbyte Data Cache
Figure 77. Cache Organization
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The processor cache design takes advantage of a sectored
organization (See Figure 78). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate MESI (modified,
exclusive, shared, invalid) bits that track the state of each cache
line.
Instruction Cache Line
Tag
Address
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits 1 MESI Bit
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits 1 MESI Bit
Data Cache Line
Tag
Address
Cache Line 0
Cache Line 1
Byte 31
Byte 31
Byte 30
Byte 30
........
........
........
........
Byte 0
Byte 0
2 MESI Bits
2 MESI Bits
Note: Instruction-cache lines have only two coherency states (valid or invalid) rather than
the four MESI coherency states of data-cache lines. Only two states are needed for the
instruction cache because these lines are read-only.
Figure 78. Cache Sector Organization
7.1
MESI States in the Data Cache
The state of each line in the caches is tracked by the MESI bits.
The coherency of these states or MESI bits is maintained by
internal processor snoops and external inquire cycles by the
system logic. The following four states are defined for the data
cache:
■ Modified—This line has been modified and is different from
main memory.
■ Exclusive—This line is not modified and is the same as main
memory. If this line is written to, it becomes Modified.
■ Shared—If a cache line is in the shared state it means that
the same line can exist in more than one cache system.
■ Invalid—The information in this line is not valid.
7.2
Predecode Bits
Decoding x86 instructions is particularly difficult because the
instructions vary in length, ranging from 1 to 15 bytes long.
Predecode logic supplies the predecode bits associated with
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each instruction byte. The predecode bits indicate the number
of bytes to the start of the next x86 instruction. The predecode
bits are passed with the instruction bytes to the decoders where
they assist with parallel x86 instruction decoding. The
predecode bits use memory separate from the 32-Kbyte
instruction cache. The predecode bits are stored in an extended
instruction cache alongside each x86 instruction byte as shown
in Figure 78.
7.3
Cache Operation
The operating modes for the caches are configured by software
using the not writethrough (NW) and cache disable (CD) bits of
control register 0 (CR0 bits 29 and 30, respectively). These bits
are used in all operating modes.
When the CD and NW bits are both set to 0, the cache is fully
enabled. This is the standard operating mode for the cache. If a
read miss occurs when the processor reads from the cache, a
line fill (32-byte burst read) on the system bus occurs in order to
fetch the cache line. Write hits to the cache are updated, while
write misses and writes to shared lines cause external memory
updates. Refer to Table 36 on page 193 for a summary of cache
read and write cycles and the effect of these operations on the
cache MESI state.
Note: A write allocate operation can modify the behavior of write
misses to the cache. See “Write Allocate” on page 186.
When CD is set to 0 and NW is set to 1, an invalid mode of
operation exists that causes a general protection fault to occur.
When CD is set to 1 (disabled) and NW is set to 0, the cache fill
mechanism is disabled but the contents of the cache are still
valid. The processor reads from the cache and, if a read miss
occurs, no line fill takes place. Write hits to the cache are
updated, while write misses and writes to shared lines cause
external memory updates. If PWT is driven Low and WB/WT# is
sampled High, a write hit to a shared line changes the cache-
line state to exclusive.
When the CD and NW bits are both set to 1, the cache is fully
disabled. Even though the cache is disabled, the contents are
not necessarily invalid. The processor reads from the cache and,
if a read miss occurs, no line fill takes place. If a write hit
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occurs, the cache is updated but an external memory update
does not occur. If a data line is in the exclusive state during a
write hit, the cache-line state is changed to modified. Cache
lines in the shared state remain in the shared state after a write
hit. Write misses access external memory directly.
The operating system can control the cacheability of a page.
The paging mechanism is controlled by CR3, the Page Directory
Entry (PDE), and the Page Table Entry (PTE). Within CR3,
PDE, and PTE are Page Cache Disable (PCD) and Page
Writethrough (PWT) bits. The values of the PCD and PWT bits
used in Table 33 and Table 34 are taken from either the PTE or
PDE. For more information see the descriptions of PCD and
PWT on pages 113 and 115, respectively.
Table 33 describes how the PWT signal is driven based on the
values of the PWT bits and the PG bit of CR0.
Table 33. PWT Signal Generation
PWT Bit*
PG Bit of CR0
PWT Signal
High
1
0
1
0
1
1
0
0
Low
Low
Low
Note:
* PWT is taken from PTE or PDE
Table 34 describes how the PCD signal is driven based on the
values of the CD bit of CR0, the PCD bits, and the PG bit of
CR0.
Table 34. PCD Signal Generation
CD Bit of CR0
PCD Bit*
PG Bit of CR0
PCD Signal
High
1
X
1
0
1
0
X
1
1
0
0
0
High
0
Low
0
0
Low
Low
Note:
* PCD is taken from PTE or PDE
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Table 35 describes how the CACHE# signal is driven based on
the cycle type, the CI bit of TR12, the PCD signal, and the
UWCCR model-specific register.
Table 35. CACHE# Signal Generation
Access Within
WC/UC Range*
Cycle Type
CI Bit of TR12
PCD Signal
CACHE#
Writebacks
Unlocked Reads
X
0
X
X
1
X
X
X
0
X
X
X
1
X
X
0
X
X
X
X
1
Low
Low
High
High
High
High
High
Locked Reads
Single Writes
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Note:
*
WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR, and only
applies to the AMD-K6-2 processor Model 8/[F:8].
Cache-Related Signals
Complete descriptions of the signals that control cacheability
and cache coherency are given on the following pages:
■ CACHE#—page 96
■ EADS#—page 100
■ FLUSH#—page 103
■ HIT#—page 104
■ HITM#—page 104
■ INV—page 108
■ KEN#—page 109
■ PCD—page 113
■ PWT—page 115
■ WB/WT#—page 123
7.4
Cache Disabling and Flushing
To completely disable all cache accesses, the CD bit must be set
to 1 and the cache must be completely flushed.
There are three different methods for flushing the cache. The
first method relies on the system logic and other two methods
rely on software.
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For the system logic to flush the cache, the processor must
sample FLUSH# asserted. In this method, the processor writes
back any data cache lines that are in the modified state,
invalidates all lines in the instruction and data caches, and then
executes a flush acknowledge special cycle (See Table 25 on
page 126).
The second method for flushing the caches is for software to
execute the WBINVD instruction which causes all modified
lines to first be written back to memory, then marks all cache
lines as invalid. Alternatively, if writing modified lines back to
memory is not necessary, the INVD instruction can be used to
invalidate all cache lines.
The third and final method for flushing the caches is to make
use of the Page Flush/Invalidate Register (PFIR), which allows
cache invalidation and optional flushing of a specific 4-Kbyte
page from the linear address space. The PFIR is only supported
on the AMD-K6-2 processor Model 8/[F:8] (see “PFIR” on page
195). Unlike the previous two methods of flushing the caches,
this particular method requires the software to be aware of
which specific pages must be flushed and invalidated.
7.5
Cache-Line Fills
The processor performs a cache-line fill for any area of system
memory defined as cacheable. If an area of system memory is
not explicitly defined as uncacheable by the software or system
logic, or implicitly treated as uncacheable by the processor,
then the memory access is assumed to be cacheable.
Software can prevent caching of certain pages by setting the
PCD bit in the PDE or PTE. Additionally, for the AMD-K6-2
processor Model 8/[F:8], software can define regions of memory
as uncacheable or write combinable by programming the
MTRRs in the UWCCR MSR (see “Memory Type Range
Registers” on page 203). Write-combinable memory is defined
as uncacheable.
The system logic also has control of the cacheability of bus
cycles. If it determines the address is not cacheable, system
logic negates the KEN# signal when asserting the first BRDY#
or NA# of a cycle.
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The processor does not cache certain memory accesses such as
locked operations. In addition, the processor does not cache
PDE or PTE memory reads in the L1 cache (referred to as page
table walks).
When the processor needs to read memory, the processor drives
a read cycle onto the bus. If the cycle is cacheable, the
processor asserts CACHE#. If the cycle is not cacheable, a
non-burst, single-transfer read takes place. The processor waits
for the system logic to return the data and assert a single
BRDY# (See Figure 55 on page 133). If the cycle is cacheable,
the processor executes a 32-byte burst read cycle. The processor
expects a total of four BRDY# signals for a burst read cycle to
take place (See Figure 57 on page 137).
Cache-line fills initiate 32-byte burst read cycles from memory
on the system bus for the instruction cache and the data cache.
If a data-cache line being filled replaces a modified line, the
modified contents of the line are copied to a 32-byte writeback
(copyback) buffer in the bus interface unit while the new line is
being read.
7.6
Cache-Line Replacements
As programs execute and task switches occur, some cache lines
eventually require replacement.
Instruction cache lines are replaced using a Least Recently
Used (LRU) algorithm. If line replacement is required, lines are
replaced when read cache misses occur.
The data cache uses a slightly different approach to line
replacement. If a miss occurs, and a replacement is required,
lines are replaced by using a Least Recently Allocated (LRA)
algorithm.
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill. In the case
of a tag-miss cache fill, the miss is due to a tag mismatch, in
which case the required cache line is filled from external
memory, and the cache line within the sector that was not
required is marked as invalid. In the case of a tag-hit cache fill,
the address matches the tag, but the requested cache line is
marked as invalid. The required cache line is filled from
external memory, and the cache line within the sector that is
not required remains in the same cache state.
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7.7
Write Allocate
Write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the data cache. In this case, the
processor performs a 32-byte burst read cycle to fetch the
data-cache line addressed by the pending write cycle. The data
associated with the pending write cycle is merged with the
recently-allocated data-cache line and stored in the processor’s
data cache. The final MESI state of the cache line depends on
the state of the WB/WT# and PWT signals during the burst read
cycle and the subsequent L1 data cache write hit (See Table 36
on page 193 to determine the cache-line states and the access
types following a cache read miss and cache write hit).
If a data-cache line fetch from memory is attempted because
the write allocate misses the data cache, and KEN# is sampled
negated, the processor does not perform an allocation. In this
case, the pending write cycle is executed as a single write cycle
on the system bus.
During write allocates, a 32-byte burst read cycle is executed in
place of a non-burst write cycle. While the burst read cycle
generally takes longer to execute than the non-burst write
cycle, performance gains are realized on subsequent write cycle
hits to the write-allocated cache line. Due to the nature of
software, memory accesses tend to occur in proximity of each
other (principle of locality). The likelihood of additional write
hits to the write-allocated cache line is high.
The following is a description of three mechanisms by which the
AMD-K6-2 processor performs write allocations. A write
allocate is performed when any one or more of these
mechanisms indicates that a pending write is to a cacheable
area of memory.
Write to a Cacheable
Page
Every time the processor performs a cache line fill, the address
of the page in which the cache line resides is saved in the
Cacheability Control Register (CCR). The page address of
subsequent write cycles is compared with the page address
stored in the CCR. If the two addresses are equal, then the
processor performs a write allocate because the page has
already been determined to be cacheable.
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When the processor performs a cache line fill from a different
page than the address saved in the CCR, the CCR is updated
with the new page address.
Write to a Sector
If the address of a pending write cycle matches the tag address
of a valid cache sector, but the addressed cache line within the
sector is marked invalid (a sector hit but a cache line miss),
then the processor performs a write allocate. The pending write
cycle is determined to be cacheable because the sector hit
indicates the presence of at least one valid cache line in the
sector. The two cache lines within a sector are guaranteed by
design to be within the same page.
Write Allocate Limit
The AMD-K6-2 processor uses two mechanisms that are
programmable within the Write Handling Control Register
(WHCR) to enable write allocations for write cycles that
address a definable area, or a special 1-Mbyte memory area.
The format of the WHCR differs between the AMD-K6-2
processor Model 8/[7:0] and the AMD-K6-2 processor Model
8/[F:8].
WHCR – Model 8/[7:0]. This WHCR contains three fields—the
WCDE bit, the Write Allocate Enable Limit (WAELIM) field,
and the Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit
(See Figure 79 on page 187).
For proper functionality, always program the WCDE bit to 0.
0
63
9
8
7
1
W
A
E
0
WAELIM
1
5
M
Reserved
Symbol
WCDE
Description
Always program to 0
Bits
8
WAELIM Write Allocate Enable Limit
7–1
WAE15M Write Allocate Enable 15-to-16-Mbyte 0
Note: Hardware RESET initializes this MSR to all zeros.
Figure 79. Write Handling Control Register (WHCR) — Model 8/[7:0]
Write Allocate Enable Limit – Model 8/[7:0]. The WAELIM field is 7
bits wide. This field, multiplied by 4 Mbytes, defines an upper
memory limit. Any pending write cycle that addresses memory
below this limit causes the processor to perform a write allocate
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(assuming the address is not within a range where write
allocates are disallowed). Write allocate is disabled for memory
accesses at and above this limit unless the processor determines
a pending write cycle is cacheable by means of one of the other
write allocate mechanisms—“Write to a Cacheable Page” and
“Write to a Sector.” The maximum value of this memory limit is
7
((2 – 1) · 4 Mbytes) = 508 Mbytes. When all the bits in this field
are set to 0, all memory is above this limit and the write allocate
mechanism is disabled (even if all bits in the WAELIM field are
set to 0, write allocates can still occur due to the “Write to a
Cacheable Page” and “Write to a Sector” mechanisms).
WHCR – Model 8/[F:8]. This WHCR contains two fields—the Write
Allocate Enable Limit (WAELIM) field, and the Write Allocate
Enable 15-to-16-Mbyte (WAE15M) bit (see Figure 80).
63
32 31
22 21 17 16 15
0
W
A
E
WAELIM
1
5
M
Reserved
Symbol
WAELIM
WAE15M
Description
Write Allocate Enable Limit
Write Allocate Enable 15-to-16-Mbyte 16
Bits
31-22
Note: Hardware RESET initializes this MSR to all zeros.
Figure 80. Write Handling Control Register (WHCR)— Model 8/[F:8]
Write Allocate Enable Limit – Model 8/[F:8]. The WAELIM field is 10
bits wide. This field, multiplied by 4 Mbytes, defines an upper
memory limit. Any pending write cycle that addresses memory
below this limit causes the processor to perform a write allocate
(assuming the address is not within a range where write
allocates are disallowed). Write allocate is disabled for memory
accesses at and above this limit unless the processor determines
a pending write cycle is cacheable by means of one of the other
write allocate mechanisms—“Write to a Cacheable Page” and
10
“Write to a Sector.” The maximum value of this limit is ((2 –1)
· 4 Mbytes) = 4092 Mbytes. When all the bits in this field are set
to 0, all memory is above this limit and the write allocate
mechanism is disabled (even if all bits in the WAELIM field are
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set to 0, write allocates can still occur due to the “Write to a
Cacheable Page” and “Write to a Sector” mechanisms).
Write Allocate Enable 15-to-16-Mbyte –All Steppings. The Write Allocate
Enable 15-to-16-Mbyte (WAE15M) bit is used to enable write
allocations for memory write cycles that address the 1 Mbyte of
memory between 15 Mbytes and 16 Mbytes. This bit must be set
to 1 to allow write allocate in this memory area. This bit is
provided to account for a small number of uncommon
memory-mapped I/O adapters that use this particular memory
address space. If the system contains one of these peripherals,
the bit should be set to 0 (even if the WAE15M bit is set to 0,
write allocates can still occur between 15 Mbytes and 16
Mbytes due to the “Write to a Cacheable Page” and “Write to a
Sector” mechanisms). The WAE15M bit is ignored if the value
in the WAELIM field is set to less than 16 Mbytes.
By definition a write allocate is not performed in the memory
area between 640 Kbytes and 1 Mbyte unless the processor
determines a pending write cycle is cacheable by means of one
of the other write allocate mechanisms—“Write to a Cacheable
Page” and “Write to a Sector.” It is not considered safe to
perform write allocations between 640 Kbytes and 1 Mbyte
(000A_0000h to 000F_FFFFh) because it is considered a
noncacheable region of memory.
For AMD-K6-2 processor Model 8/[F:8], if a memory region is
defined as write-combinable or uncacheable by a MTRR, write
allocates are not performed in that region.
Write Allocate Logic
Mechanisms and
Conditions
Figure 81 shows the logic flow for all the mechanisms involved
with write allocate for memory bus cycles. The left side of the
diagram (the text) describes the conditions that need to be true
in order for the value of that line to be a 1. Items 1 to 4 of the
diagram are related to general cache operation and items 5 to
10 are related to the write allocate mechanisms.
For more information about write allocate, see the
Implementation of Write Allocate in the K86™ Processors
Application Note, order# 21326.
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Perform
Write Allocate
1) CD Bit of CR0
2) PCD Signal
3) CI Bit of TR12
4) UC or WC
5) Write to Cacheable Page (CCR)
6) Write to a Sector
7) Less Than Limit (WAELIM)
8) Between 640 Kbytes and 1 Mbyte
9) Between 15–16 Mbytes
10) Write Allocate Enable 15–16 Mbyte (WAE15M)
Figure 81. Write Allocate Logic Mechanisms and Conditions
The following list describes the corresponding items in Figure
81:
1. CD Bit of CR0—When the cache disable (CD) bit within
control register 0 (CR0) is set to 1, the cache fill mechanism
for both reads and writes is disabled and write allocate does
not occur.
2. PCD Signal—When the PCD (page cache disable) signal is
driven High, caching for that page is disabled, even if KEN#
is sampled asserted, and write allocate does not occur.
3. CI Bit of TR12—When the cache inhibit bit of Test Register
12 is set to 1, L1 cache fills are disabled and write allocate
does not occur.
4. UC or WC—If a pending write cycle addresses a region of
memory defined as write combinable or uncacheable by an
MTRR, write allocates are not performed in that region.
MTRRs are only supported in the AMD-K6-2 processor
Model 8/[F:8]. For all other steppings, treat this condition as
equal to 0.
5. Write to a Cacheable Page (CCR)—A write allocate is
performed if the processor knows that a page is cacheable.
The CCR is used to store the page address of the last cache
fill for a read miss. See “Write to a Cacheable Page” on page
186 for a detailed description of this condition.
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6. Write to a Sector—A write allocate is performed if the
address of a pending write cycle matches the tag address of a
valid cache sector but the addressed cache line within the
sector is invalid. See “Write to a Sector” on page 187 for a
detailed description of this condition.
7. Less Than Limit (WAELIM)—The write allocate limit
mechanism determines if the memory area being addressed
is less than the limit set in the WAELIM field of WHCR. If
the address is less than the limit, write allocate for that
memory address is performed as long as conditions 8
through 10 do not prevent write allocate (even if conditions
8 and 10 attempt to prevent write allocate, condition 5 or 6
allows write allocate to occur).
8. Between 640 Kbytes and 1 Mbyte—Write allocate is not
performed in the memory area between 640 Kbytes and 1
Mbyte. It is not considered safe to perform write allocations
between 640 Kbytes and 1 Mbyte (000A_0000h to
000F_FFFFh) because this area of memory is considered a
noncacheable region of memory (even if condition 8
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
9. Between 15–16 Mbytes—If the address of a pending write
cycle is in the 1 Mbyte of memory between 15 Mbytes and 16
Mbytes, and the WAE15M bit is set to 1, write allocate for
this cycle is enabled.
10.Write Allocate Enable 15–16 Mbytes (WAE15M)—This
condition is associated with the Write Allocate Limit
mechanism and affects write allocate only if the limit
specified by the WAELIM field is greater than or equal to
16 Mbytes. If the memory address is between 15 Mbytes and
16 Mbytes, and the WAE15M bit in the WHCR is set to 0,
write allocate for this cycle is disabled (even if condition 10
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
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7.8
Prefetching
Hardware
Prefetching
The AMD-K6-2 processor conditionally performs cache
prefetching which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
pipelined cycles. The burst read cycles do not occur
back-to-back (wait states occur) if the processor is not ready to
start a new cycle, if higher priority data read or write requests
exist, or if NA# (next address) was sampled negated. Wait states
can also exist between burst cycles if the processor samples
AHOLD or BOFF# asserted.
Software Prefetching
The 3DNow! technology includes an instruction called
PREFETCH that allows a cache line to be prefetched into the
data cache. Unlike prefetching under hardware control,
software prefetching only fetches the cache line specified by
the operand of the PREFETCH instruction, and does not
attempt to fetch the other cache line in the sector. The
PREFETCH instruction format is defined in Table 17,
“3DNow!™ Instructions,” on page 81. For more detailed
information, see the 3DNow!™ Technology Manual, order#
21928.
7.9
Cache States
Table 36 shows all the possible cache-line states before and
after program-generated accesses to individual cache lines. The
table includes the correspondence between MESI states and
writethrough or writeback states for lines in the data cache.
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Table 36. Data Cache States for Read and Write Accesses
Cache State After Access
Access
Type
Cache State Before
Access
Type
1
Writeback
8
MESI State
Writethrough State
invalid
single read from bus
invalid
–
Read Miss
burst read from bus, fill
shared or
writethrough or
invalid
2
3
3
cache
exclusive
writeback
Cache
Read
exclusive
modified
shared
–
–
–
exclusive
modified
shared
writeback
writeback
writethrough
–
Read Hit
Write Miss
Write Hit
4
invalid
invalid
single write to bus
burst read from bus, fill
6
invalid
invalid
–
–
modified
5
cache, write to cache
burst read from bus, fill
cache, write to cache,
Cache
Write
7
shared
5
single write to bus
exclusive or modified
shared
write to cache
modified
shared or
writeback
writethrough or
write to cache, single
write to bus
3
3
exclusive
writeback
Notes:
1. Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32-byte burst read.
2. If CACHE# is driven Low and KEN# is sampled asserted.
3. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If PWT is driven High or
WB/WT# is sampled Low, the line is cached in the shared (writethrough) state.
4. Assumes the write allocate conditions as specified in “Write Allocate” on page 186 are not met.
5. Assumes the write allocate conditions as specified in “Write Allocate” on page 186 are met.
6. Assumes PWT is driven Low and WB/WT# is sampled High.
7. Assumes PWT is driven High or WB/WT# is sampled Low.
8. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a particular cache line.
–
Not applicable or none.
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7.10
Cache Coherency
Different ways exist to maintain coherency between the system
memory and cache memories. Inquire cycles, internal snoops,
FLUSH#, WBINVD, INVD, and line replacements all prevent
inconsistencies between memories.
Inquire Cycles
Inquire cycles are bus cycles initiated by system logic which
ensure coherency between the caches and main memory. In
systems with multiple bus masters, system logic maintains
cache coherency by driving inquire cycles to the processor.
System logic initiates inquire cycles by asserting AHOLD,
BOFF#, or HOLD to obtain control of the address bus and then
driving EADS#, INV (optional), and an inquire address
(A[31:5]). This type of bus cycle causes the processor to
compare the tags for both its instruction and data caches with
the inquire address. If there is a hit to a shared or exclusive line
in the data cache or a valid line in the instruction cache, the
processor asserts HIT#. If the compare hits a modified line in
the data cache, the processor asserts HIT# and HITM#. If
HITM# is asserted, the processor writes the modified line back
to memory. If INV was sampled asserted with EADS#, a hit
invalidates the line. If INV was sampled negated with EADS#, a
hit leaves the line in the shared state or transitions it from the
exclusive or modified state to the shared state.
Table 37 on page 197 shows the effects of inquire cycles—
performed with INV equal to 0 (non-invalidating) and INV
equal to 1 (invalidating)—snoops, and invalidations.
Internal Snooping
Internal snooping is initiated by the processor (rather than
system logic) during certain cache accesses. It is used to
maintain coherency between the instruction cache and the data
cache.
The processor automatically snoops its instruction cache during
read or write misses to its data cache, and it snoops its data
cache during read misses to its instruction cache. Table 37
summarizes the actions taken during this internal snooping.
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If an internal snoop hits its target, the processor does the
following:
■ Data cache snoop during an instruction-cache read miss—If
modified, the line in the data cache is written back on the
system bus to external memory. Regardless of its state, the
data-cache line is invalidated and the instruction cache
performs a burst read cycle from external memory.
■ Instruction cache snoop during a data cache miss—The line in
the instruction cache is marked invalid, and the data-cache
read or write is performed as defined in Table 36 on
page 193.
FLUSH#
PFIR
In response to sampling FLUSH# asserted, the processor writes
back any data cache lines that are in the modified state and
then marks all lines in the instruction and data caches as
invalid.
The AMD-K6-2 processor Model 8/[F:8] processor contains the
Page Flush/Invalidate Register (PFIR) that allows cache
invalidation and optional flushing of a specific 4-Kbyte page
from the linear address space (see Figure 82). When the PFIR is
written to (using the WRMSR instruction), the invalidation
and, optionally, the flushing begins. The total amount of cache
in the AMD-K6-2 processor is 64 Kbytes. Using this register can
result in a much lower cycle count for flushing particular pages
versus flushing the entire cache.
63
32 31
12 11 9 8 7
1 0
F
/
I
P
F
LINPAGE
Reserved
Description
Symbol
LINPAGE 20-bit Linear Page Address
Bit
31-12
PF
F/I
Page Fault Occurred
Flush/Invalidate Command
8
0
Figure 82. Page Flush/Invalidate Register (PFIR)—MSR C000_0088h
LINPAGE. This 20-bit field must be written with bits 31:12 of the
linear address of the 4-Kbyte page that is to be invalidated and
optionally flushed from the L1 cache.
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PF. If an attempt to invalidate or flush a page results in a page
fault, the processor sets the PF bit to 1, and the invalidate or
flush operation is not performed (even though invalidate
operations do not normally generate page faults). In this case,
an actual page fault exception is not generated. If the PF bit
equals 0 after an invalidate or flush operation, then the
operation executed successfully. The PF bit must be read after
every write to the PFIR register to determine if the invalidate
or flush operation executed successfully.
F/I. This bit is used to control the type of action that occurs to
the specified linear page. If a 0 is written to this bit, the
operation is a flush, in which case all cache lines in the
modified state within the specified page are written back to
memory, after which the entire page is invalidated. If a 1 is
written to this bit, the operation is an invalidation, in which
case the entire page is invalidated without the occurrence of
any writebacks.
WBINVD and INVD
These x86 instructions cause all cache lines to be marked as
invalid. WBINVD writes back modified lines before marking all
cache lines invalid. INVD does not write back modified lines.
Cache-Line
Replacement
Replacing lines in the instruction or data cache, according to
the line replacement algorithms described in “Cache-Line
Fills” on page 184, ensures coherency between main memory
and the caches.
Table 37 on page 197 shows all possible cache-line states before
and after various cache-related operations.
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Table 37. Cache States for Inquire Cycles, Snoops, Flushes, and Invalidation
Cache State After Operation
Cache State
Before Operation
Type of Operation
Memory Access
Writeback
MESI State
Writethrough State
INV=0
shared
invalid
shared
invalid
writethrough
invalid
shared or
exclusive
–
INV=1
INV=0
INV=1
Inquire
Cycle
writethrough
invalid
modified
writeback to bus
shared or
exclusive
–
Internal
Snoop
invalid
invalid
invalid
invalid
modified
writeback to bus
shared or
exclusive
–
FLUSH#
Signal
modified
writeback to bus
shared or
exclusive
–
PFIR*
(F/I = 0)
invalid
invalid
invalid
invalid
invalid
invalid
invalid
modified
writeback to bus
–
PFIR*
(F/I = 1)
–
shared or
exclusive
–
WBINVD
Instruction
modified
writeback to bus
–
INVD
Instruction
–
invalid
Notes:
All writebacks are 32-byte burst write cycles.
– Not applicable or none.
*
The AMD-K6-2 processor Model 8/[F:8] supports the PFIR.
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Cache Snooping
Table 38 shows the conditions under which snooping occurs in
the AMD-K6-2 processor and the resources that are snooped.
Table 38. Snoop Action
Snooping Action
Type of Event
Type of Access
Instruction
Cache
Data Cache
1
1
Inquire Cycle
System Logic
yes
yes
Read
Miss
2
–
–
yes
Instruction
Cache
Read
Hit
no
–
Read
Miss
3
yes
Internal Snoop
Read
Hit
no
–
Data
Cache
Write
Miss
3
–
yes
Write
Hit
no
–
Notes:
1. The processor’s response to an inquire cycle depends on the state of the INV input signal
and the state of the cache line as follows:
For the instruction cache, if INV is sampled negated, the line remains invalid or valid, but
if INV is sampled asserted, the line is invalidated.
For the data cache, if INV is sampled negated, valid lines remain in or transition to the
shared state, a modified data cache line is written back before the line is marked shared
(with HITM# asserted), and invalid lines remain invalid. For the data cache, if INV is
sampled asserted, the line is marked invalid. Modified lines are written back before
invalidation.
2. If an internal snoop hits a modified line in the data cache, the line is written back and
invalidated. Then the instruction cache performs a burst read from memory.
3. If an internal snoop hits a line in the instruction cache, the instruction cache line is
invalidated and the data-cache read or write is performed from memory.
– Not applicable.
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7.11
Writethrough versus Writeback Coherency States
The terms writethrough and writeback apply to two related
concepts in a read-write cache like the AMD-K6-2 processor L1
data cache. The following conditions apply to both the
writethrough and writeback modes:
■ Memory Writes—A relationship exists between external
memory writes and their concurrence with cache updates:
•
An external memory write that occurs concurrently with
a cache update to the same location is a writethrough.
Writethroughs are driven as single cycles on the bus.
•
An external memory write that occurs after the processor
has modified a cache line is a writeback. Writebacks are
driven as burst cycles on the bus.
■ Coherency State—A relationship exists between MESI
coherency states and writethrough-writeback coherency
states of lines in the cache as follows:
•
Shared and invalid MESI lines are in the writethrough
state.
•
Modified and exclusive MESI lines are in the writeback
state.
7.12
A20M# Masking of Cache Accesses
Although the processor samples A20M# as a level-sensitive
input on every clock edge, it should only be asserted in Real
mode. The processor applies the A20M# masking to its tags,
through which all programs access the caches. Therefore,
assertion of A20M# affects all addresses (cache and external
memory), including the following:
■ Cache-line fills (caused by read misses or write allocates)
■ Cache writethroughs (caused by write misses or write hits to
lines in the shared state)
However, A20M# does not mask writebacks or invalidations
caused by the following actions:
■ Internal snoops
■ Inquire cycles
■ The FLUSH# signal
■ Writing to the PFIR (AMD-K6-2/[F:8] only)
■ The WBINVD instruction
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8
Write Merge Buffer
The AMD-K6-2 processor Model 8/[F:8] contains an 8-byte write
merge buffer that allows the processor to conditionally combine
data from multiple noncacheable write cycles into this merge
buffer. The merge buffer operates in conjunction with the
Memory Type Range Registers (MTRRs). Refer to “Memory
Type Range Registers” on page 203 for a description of the
MTRRs.
Merging multiple write cycles into a single write cycle reduces
processor bus utilization and processor stalls, thereby
increasing the overall system performance.
8.1
EWBE Control
The presence of the merge buffer creates the potential to
perform out-of-order write cycles relative to the processor’s L1
cache. In general, the ordering of write cycles that are driven
externally on the system bus and those that hit the processor’s
cache can be controlled by the EWBE# signal. See “EWBE#
(External Write Buffer Empty)” on page 101 for more
information. If EWBE# is sampled negated, the processor
delays the commitment of write cycles to cache lines in the
modified state or exclusive state in the processor’s cache.
Therefore, the system logic can enforce strong ordering by
negating EWBE# until the external write cycle is complete,
thereby ensuring that a subsequent write cycle that hits the
cache does not complete ahead of the external write cycle.
However, the addition of the write merge buffer introduces the
potential for out-of-order write cycles to occur between writes
to the merge buffer and writes to the processor’s cache. Because
these writes occur entirely within the processor and are not
sent out to the processor bus, the system logic is not able to
enforce strong ordering with the EWBE# signal.
The EWBE control (EWBEC) bits in the EFER register provide
a mechanism for enforcing three different levels of write
ordering in the presence of the write merge buffer:
■ EFER[3] is defined as the Global EWBE Disable (GEWBED).
When GEWBED equals 1, the processor does not attempt to
enforce any write ordering internally or externally (the
EWBE# signal is ignored). This is the maximum performance
setting.
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■ EFER[2] is defined as the Speculative EWBE Disable
(SEWBED). SEWBED only affects the processor when
GEWBED equals 0. If GEWBED equals 0 and SEWBED
equals 1, the processor enforces strong ordering for all
internal write cycles with the exception of write cycles
addressed to a range of memory defined as uncacheable
(UC) or write-combining (WC) by the MTRRs. In addition,
the processor samples the EWBE# signal. If EWBE# is
sampled negated, the processor delays the commitment of
write cycles to processor cache lines in the modified state or
exclusive state until EWBE# is sampled asserted.
This setting provides performance comparable to, but
slightly less than, the performance obtained when
GEWBED equals 1 because some degree of write ordering is
maintained.
■ If GEWBED equals 0 and SEWBED equals 0, the processor
enforces strong ordering for all internal and external write
cycles. In this setting, the processor assumes, or speculates,
that strong order must be maintained between writes to the
merge buffer and writes that hit the processor’s cache. Once
the merge buffer is written out to the processor’s bus, the
EWBE# signal is sampled. If EWBE# is sampled negated, the
processor delays the commitment of write cycles to
processor cache lines in the modified state or exclusive state
until EWBE# is sampled asserted.
This setting is the default after RESET and provides the
lowest performance of the three settings because full write
ordering is maintained.
Table 39 summarizes the three settings of the EWBEC field for
the EFER register, along with the effect of write ordering and
performance. For more information on the EFER register, see
“Extended Feature Enable Register (EFER)–Model 8/[F:8]” on
page 50.
Table 39. EWBEC Settings
EFER[3]
(GEWBED) (SEWBED)
EFER[2]
Write
Ordering
Performance
1
0
0
0 or 1
None
All except UC/WC Close-to-Best
All Slowest
Best
1
0
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8.2
Memory Type Range Registers
The AMD-K6-2 processor Model 8/[F:8] provides two variable-
range Memory Type Range Registers (MTRRs)—MTRR0 and
MTRR1—that each specify a range of memory. Each range can
be defined as one of the following memory types:
■ Uncacheable (UC) memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. Memory write
cycles are targeted at the specified memory address and a
write allocation does not occur.
■ Write-Combining (WC) memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. The processor
conditionally combines data from multiple noncacheable
write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single
write cycle reduces processor bus utilization and processor
stalls, thereby increasing the overall system performance.
This memory type is applicable for linear video frame
buffers.
UC/WC Cacheability
Control Register
(UWCCR)
The MTRRs are accessed by addressing the 64-bit MSR known
as the UC/WC Cacheability Control Register (UWCCR). The
MSR address of the UWCCR is C000_0085h. Following reset, all
bits in the UWCCR register are set to 0. MTRR0 (lower 32 bits
of the UWCCR register) defines the size and memory type of
range 0 and MTRR1 (upper 32 bits) defines the size and
memory type of range 1 (see Figure 83).
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.
Symbol Description
Bits
32
Symbol Description
Bits
0
UC1
Uncacheable Memory Type
UC0
Uncacheable Memory Type
WC1
Write-Combining Memory Type 33
WC0
Write-Combining Memory Type
1
63
49 48
34 33 32 31
17 16
2
1
0
W
C
1
U
C
1
W
C
0
U
C
0
Physical Base Address 1
Physical Address Mask 1
Physical Base Address 0
Physical Address Mask 0
MTRR1
MTRR0
Figure 83. UC/WC Cacheability Control Register (UWCCR)—MSR C000_0085h (Model 8/[F:8])
Physical Base Address n (n=0, 1). This address is the 15 most-
significant bits of the physical base address of the memory
range. The least-significant 17 bits of the base address are not
needed because the base address is by definition always aligned
on a 128-Kbyte boundary.
Physical Address Mask n (n=0, 1). This value is the 15 most-
significant bits of a physical address mask that is used to define
the size of the memory range. This mask is logically ANDed
with both the physical base address field of the UWCCR
register and the physical address generated by the processor. If
the results of the two AND operations are equal, then the
generated physical address is considered within the range. That
is, if:
Mask & Physical Base Address = Mask & Physical Address Generated
then the physical address generated by the processor is in the
range.
WCn (n=0, 1). When set to 1, this memory range is defined as
write combinable (refer to Table 40). Write-combinable
memory is uncacheable.
UCn (n=0, 1). When set to 1, this memory range is defined as
uncacheable (refer to Table 40).
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Table 40. WC/UC Memory Type
WCn
UCn
Memory Type
0
1
0
0
1
No effect on cacheability or write combining
Write-combining memory range (uncacheable)
Uncacheable memory range
0 or 1
Memory-Range Restrictions. The following rules regarding the
address alignment and size of each range must be adhered to
when programming the physical base address and physical
address mask fields of the UWCCR register:
■ The minimum size of each range is 128 Kbytes.
■ The physical base address must be aligned on a 128-Kbyte
boundary.
■ The physical base address must be range-size aligned. For
example, if the size of the range is 1 Mbyte, then the
physical base address must be aligned on a 1-Mbyte
boundary.
■ All bits set to 1 in the physical address mask must be
contiguous. Likewise, all bits set to 0 in the physical address
mask must be contiguous. For example:
111_1111_1100_0000b is a valid physical address mask
111_1111_1101_0000b is invalid
Table 41 lists the valid physical address masks and the resulting
range sizes that can be programmed in the UWCCR register.
Table 41. Valid Masks and Range Sizes
Masks
Size
128 Kbytes
256 Kbytes
512 Kbytes
1 Mbyte
111_1111_1111_1111b
111_1111_1111_1110b
111_1111_1111_1100b
111_1111_1111_1000b
111_1111_1111_0000b
111_1111_1110_0000b
111_1111_1100_0000b
2 Mbytes
4 Mbytes
8 Mbytes
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Table 41. Valid Masks and Range Sizes (continued)
Masks
Size
16 Mbytes
32 Mbytes
64 Mbytes
128 Mbytes
256 Mbytes
512 Mbytes
1 Gbyte
111_1111_1000_0000b
111_1111_0000_0000b
111_1110_0000_0000b
111_1100_0000_0000b
111_1000_0000_0000b
111_0000_0000_0000b
110_0000_0000_0000b
100_0000_0000_0000b
000_0000_0000_0000b
2 Gbytes
4 Gbytes
Example. Suppose that the range of memory from 16 Mbytes to
32 Mbytes is uncacheable, and the 8-Mbyte range of memory on
top of 1 Gbyte is write-combinable. Range 0 is defined as the
uncacheable range, and range 1 is defined as the write-
combining range.
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 16 Mbytes (0100_0000h) yields
a physical base address 0 field of 000_0000_1000_0000b.
Because the uncacheable range size is 16 Mbytes, the physical
mask value 0 field is 111_1111_1000_0000b, according to Table
41. Bit 1 of the UWCCR register (WC0) is set to 0 and bit 0 of
the UWCCR register is set to 1 (UC0).
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 1 Gbyte (4000_0000h) yields a
physical base address 1 field of 010_0000_0000_0000b. Because
the write-combining range size is 8 Mbytes, the physical mask
value 1 field is 111_1111_1100_0000b, according to Table 41. Bit
33 of the UWCCR register (WC1) is set to 1 and bit 32 of the
UWCCR register is set to 0 (UC1).
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9
Floating-Point and Multimedia Execution Units
9.1
Floating-Point Execution Unit
The AMD-K6-2 processor contains an IEEE 754-compatible and
854-compatible floating-point execution unit designed to
accelerate the performance of software that utilizes the x86
floating-point instruction set. Floating-point software is
typically written to manipulate numbers that are very large or
very small, that require a high degree of precision, or that result
from complex mathematical operations such as
transcendentals. Applications that take advantage of
floating-point operations include geometric calculations for
graphics acceleration, scientific, statistical, and engineering
applications, and business applications that use large amounts
of high-precision data.
The high-performance floating-point execution unit contains an
adder unit, a multiplier unit, and a divide/square root unit.
These low-latency units can execute floating-point instructions
in as few as two processor clocks. To increase performance, the
processor is designed to simultaneously decode most
floating-point instructions with most short-decodeable
instructions.
See “Software Environment” on page 21 for a description of the
floating-point data types, registers, and instructions.
Handling
Floating-Point
Exceptions
The AMD-K6-2 processor provides the following two types of
exception handling for floating-point exceptions:
■ If the numeric error (NE) bit in CR0 is set to 1, the processor
invokes the interrupt 10h handler. In this manner, the
floating-point exception is completely handled by software.
■ If the NE bit in CR0 is set to 0, the processor requires
external logic to generate an interrupt on the INTR signal in
order to handle the exception.
External Logic
Support of
Floating-Point
Exceptions
The processor provides the FERR# (Floating-Point Error) and
IGNNE# (Ignore Numeric Error) signals to allow the external
logic to generate the interrupt in a manner consistent with
IBM-compatible PC/AT systems. The assertion of FERR#
indicates the occurrence of an unmasked floating-point
exception resulting from the execution of a floating-point
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instruction. IGNNE# is used by the external hardware to control
the effect of an unmasked floating-point exception. Under
certain circumstances, if IGNNE# is sampled asserted, the
processor ignores the floating-point exception.
Figure 84 illustrates an implementation of external logic for
supporting floating-point exceptions. The following example
explains the operation of the external logic in Figure 84:
As the result of a floating-point exception, the processor
asserts FERR#. The assertion of FERR# and the
sampling of IGNNE# negated indicates the processor has
stopped instruction execution and is waiting for an
interrupt. The assertion of FERR# leads to the assertion
of INTR by the interrupt controller. The processor
acknowledges the interrupt and jumps to the
corresponding interrupt service routine in which an I/O
write cycle to address port F0h leads to the assertion of
IGNNE#. When IGNNE# is sampled asserted, the
processor ignores the floating-point exception and
continues instruction execution. When the processor
negates FERR#, the external logic negates IGNNE#.
See “FERR# (Floating-Point Error)” on page 102 and “IGNNE#
(Ignore Numeric Exception)” on page 106 for more details.
I/O Address
Port F0h
®
AMD-K6 -2
Processor
IGNNE#
Flip-Flop
CLOCK
Q
Q
RESET
“1”
DATA
CLEAR
FERR#
Interrupt
Controller
FERR#
Flip-Flop
CLOCK
Q
Q
IRQ13
DATA
CLEAR
INTR
IGNNE#
Figure 84. External Logic for Supporting Floating-Point Exceptions
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9.2
Multimedia and 3DNow!™ Execution Units
The multimedia and 3DNow! execution units of the AMD-K6-2
processor are designed to accelerate the performance of
software written using the industry-standard MMX instructions
and the new 3DNow! instructions. Applications that can take
advantage of the MMX and 3DNow! instructions include
graphics, video and audio compression and decompression,
speech recognition, and telephony applications.
The multimedia execution unit can execute MMX instructions
in a single processor clock. All MMX and 3DNow! arithmetic
instructions are pipelined for higher performance. To increase
performance, the processor is designed to simultaneously
decode all MMX and 3DNow! instructions with most other
instructions.
®
For more information on MMX instructions, see the AMD-K6
Processor Multimedia Technology Manual, order# 20726. For
more information on 3DNow! instructions, see the 3DNow!™
Technology Manual, order# 21928.
9.3
Floating-Point and MMX™/3DNow!™ Instruction Compatibility
Registers
The eight 64-bit MMX registers (which are also utilized by
3DNow! instructions) are mapped on the floating-point stack.
This enables backward compatibility with all existing software.
For example, the register saving event that is performed by
operating systems during task switching requires no changes to
the operating system. The same support provided in an
operating system’s interrupt 7 handler (Device Not Available)
for saving and restoring the floating-point registers also
supports saving and restoring the MMX registers.
Exceptions
There are no new exceptions defined for supporting the MMX
and 3DNow! instructions. All exceptions that occur while
decoding or executing an MMX or 3DNow! instruction are
handled in existing exception handlers without modification.
FERR# and IGNNE#
MMX instructions and 3DNow! instructions do not generate
floating-point exceptions. However, if an unmasked
floating-point exception is pending, the processor asserts
FERR# at the instruction boundary of the next floating-point
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instruction, MMX instruction, 3DNow! instruction or WAIT
instruction.
The sampling of IGNNE# asserted only affects processor
operation during the execution of an error-sensitive
floating-point instruction, MMX instruction, 3DNow!
instruction or WAIT instruction when the NE bit in CR0 is set to
0.
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10
System Management Mode (SMM)
10.1
Overview
SMM is an alternate operating mode entered by way of a system
management interrupt (SMI#) and handled by an interrupt
service routine. SMM is designed for system control activities
such as power management. These activities appear
transparent to conventional operating systems like DOS and
Windows. SMM is primarily targeted for use by the Basic Input
Output System (BIOS) and specialized low-level device drivers.
The code and data for SMM are stored in the SMM memory
area, which is isolated from main memory.
The processor enters SMM by the assertion of the SMI#
interrupt and the processor’s acknowledgment by the assertion
of SMIACT#. At this point the processor saves its state into the
SMM memory state-save area and jumps to the SMM service
routine. The processor returns from SMM when it executes the
RSM (resume) instruction from within the SMM service
routine. Subsequently, the processor restores its state from the
SMM save area, negates SMIACT#, and resumes execution with
the instruction following the point where it entered SMM.
The following sections summarize the SMM state-save area,
entry into and exit from SMM, exceptions and interrupts in
SMM, memory allocation and addressing in SMM, and the SMI#
and SMIACT# signals.
10.2
SMM Operating Mode and Default Register Values
The software environment within SMM has the following
characteristics:
■ Addressing and operation in Real mode
■ 4-Gbyte segment limits
■ Default 16-bit operand, address, and stack sizes, although
instruction prefixes can override these defaults
■ Control transfers that do not override the default operand
size truncate the EIP to 16 bits
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■ Far jumps or calls cannot transfer control to a segment with
a base address requiring more than 20 bits, as in Real mode
segment-base addressing
■ A20M# is masked
■ Interrupt vectors use the Real-mode interrupt vector table
■ The IF flag in EFLAGS is cleared (INTR not recognized)
■ The TF flag in EFLAGS is cleared
■ The NMI and INIT interrupts are disabled
■ Debug register DR7 is cleared (debug traps disabled)
Figure 85 shows the default map of the SMM memory area. It
consists of a 64-Kbyte area, between 0003_0000h and
0003_FFFFh, of which the top 32 Kbytes (0003_8000h to
0003_FFFFh) must be populated with RAM. The default
code-segment (CS) base address for the area—called the SMM
base address — is at 0003_0000h. The top 512 bytes
(0003_FE00h to 0003_FFFFh) contain a fill-down SMM
state-save area. The default entry point for the SMM service
routine is 0003_8000h.
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Fill Down
0003_FFFFh
SMM
State-Save
Area
0003_FE00h
32-Kbyte
Minimum RAM
SMM
Service Routine
Service Routine Entry Point
0003_8000h
0003_0000h
SMM Base Address (CS)
Figure 85. SMM Memory
Table 42 shows the initial state of registers when entering SMM.
Table 42. Initial State of Registers in SMM
Registers
General Purpose Registers
EFLAGS
SMM Initial State
unmodified
0000_0002h
PE, EM, TS, and PG are cleared (bits 0, 2, 3,
and 31). The other bits are unmodified.
CR0
DR7
0000_0400h
unmodified
0000_8000h
0003_0000h
0000_0000h
GDTR, LDTR, IDTR, TSSR, DR6
EIP
CS
DS, ES, FS, GS, SS
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10.3
SMM State-Save Area
When the processor acknowledges an SMI# interrupt by
asserting SMIACT#, it saves its state in a 512-byte SMM
state-save area shown in Table 43. The save begins at the top of
the SMM memory area (SMM base address + FFFFh) and fills
down to SMM base address + FE00h.
Table 43 shows the offsets in the SMM state-save area relative
to the SMM base address. The SMM service routine can alter
any of the read/write values in the state-save area.
Table 43. SMM State-Save Area Map
Address Offset
FFFCh
FFF8h
Contents Saved
CR0
CR3
EFLAGS
EIP
FFF4h
FFF0h
FFECh
FFE8h
FFE4h
FFE0h
FFDCh
FFD8h
FFD4h
FFD0h
FFCCh
FFC8h
FFC4h
FFC0h
FFBCh
FFB8h
FFB4h
FFB0h
FFACh
FFA8h
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
DR6
DR7
TR
LDTR Base
GS
FS
DS
SS
CS
ES
Notes:
— No data dump at that address
*
Only contains information if SMI# is asserted during a valid I/O bus cycle.
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Table 43. SMM State-Save Area Map (continued)
Address Offset
FFA4h
FFA0h
FF9Ch
FF98h
FF94h
FF90h
FF8Ch
FF88h
FF84h
FF80h
FF7Ch
FF78h
FF74h
FF70h
FF6Ch
FF68h
FF64h
FF60h
FF5Ch
FF58h
FF54h
FF50h
FF4Ch
FF48h
FF44h
FF40h
FF3Ch
FF38h
FF34h
FF30h
FF2Ch
Contents Saved
I/O Trap Dword
—
I/O Trap EIP*
—
—
IDT Base
IDT Limit
GDT Base
GDT Limit
TSS Attr
TSS Base
TSS Limit
—
LDT High
LDT Low
GS Attr
GS Base
GS Limit
FS Attr
FS Base
FS Limit
DS Attr
DS Base
DS Limit
SS Attr
SS Base
SS Limit
CS Attr
CS Base
CS Limit
ES Attr
Notes:
— No data dump at that address
*
Only contains information if SMI# is asserted during a valid I/O bus cycle.
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Table 43. SMM State-Save Area Map (continued)
Address Offset
FF28h
Contents Saved
ES Base
FF24h
ES Limit
FF20h
—
—
FF1Ch
FF18h
—
FF14h
CR2
FF10h
CR4
FF0Ch
I/O Restart ESI*
I/O Restart ECX*
I/O Restart EDI*
HALT Restart Slot
I/O Trap Restart Slot
SMM RevID
SMM Base
—
FF08h
FF04h
FF02h
FF00h
FEFCh
FEF8h
FEF7h–FE00h
Notes:
— No data dump at that address
*
Only contains information if SMI# is asserted during a valid I/O bus cycle.
10.4
SMM Revision Identifier
The SMM revision identifier at offset FEFCh in the SMM
state-save area specifies the version of SMM and the extensions
that are available on the processor. The SMM revision identifier
fields are as follows:
■ Bits 31–18—Reserved
■ Bit 17—SMM base address relocation (1 = enabled)
■ Bit 16—I/O trap restart (1 = enabled)
■ Bits 15–0—SMM revision level for the AMD-K6-2 processor
= 0002h
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Table 44 shows the format of the SMM Revision Identifier.
Table 44. SMM Revision Identifier
31–18
Reserved
0
17
16
15–0
SMM Revision Level
0002h
SMM Base Relocation I/O Trap Extension
1
1
10.5
SMM Base Address
During RESET, the processor sets the base address of the
code-segment (CS) for the SMM memory area—the SMM base
address—to its default, 0003_0000h. The SMM base address at
offset FEF8h in the SMM state-save area can be changed by the
SMM service routine to any address that is aligned to a
32-Kbyte boundary. (Locations not aligned to a 32-Kbyte
boundary cause the processor to enter the Shutdown state when
executing the RSM instruction.)
In some operating environments it may be desirable to relocate
the 64-Kbyte SMM memory area to a high memory area in order
to provide more low memory for legacy software. During system
initialization, the base of the 64-Kbyte SMM memory area is
relocated by the BIOS. To relocate the SMM base address, the
system enters the SMM handler at the default address. This
handler changes the SMM base address location in the SMM
state-save area, copies the SMM handler to the new location,
and exits SMM.
The next time SMM is entered, the processor saves its state at
the new base address. This new address is used for every SMM
entry until the SMM base address in the SMM state-save area is
changed or a hardware reset occurs.
10.6
Halt Restart Slot
During entry into SMM, the halt restart slot at offset FF02h in
the SMM state-save area indicates if SMM was entered from the
Halt state. Before returning from SMM, the halt restart slot
(offset FF02h) can be written to by the SMM service routine to
specify whether the return from SMM takes the processor back
to the Halt state or to the next instruction after the HLT
instruction.
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Upon entry into SMM, the halt restart slot is defined as follows:
■ Bits 15–1—Reserved
■ Bit 0—Point of entry to SMM:
1 = entered from Halt state
0 = not entered from Halt state
After entry into the SMI handler and before returning from
SMM, the halt restart slot can be written using the following
definition:
■ Bits 15–1—Reserved
■ Bit 0—Point of return when exiting from SMM:
1 = return to Halt state
0 = return to next instruction after the HLT instruction
If the return from SMM takes the processor back to the Halt
state, the HLT instruction is not re-executed, but the Halt
special bus cycle is driven on the bus after the return.
10.7
I/O Trap Dword
If the assertion of SMI# is recognized during the execution of an
I/O instruction, the I/O trap dword at offset FFA4h in the SMM
state-save area contains information about the instruction. The
fields of the I/O trap dword are configured as follows:
■ Bits 31–16—I/O port address
■ Bits 15–4—Reserved
■ Bit 3—REP (repeat) string operation
(1 = REP string, 0 = not a REP string)
■ Bit 2—I/O string operation
(1 = I/O string, 0 = not an I/O string)
■ Bit 1—Valid I/O instruction (1 = valid, 0 = invalid)
■ Bit 0—Input or output instruction (1 = INx, 0 = OUTx)
Table 45 shows the format of the I/O trap dword.
Table 45. I/O Trap Dword Configuration
31—16
15—4
3
2
1
0
I/O Port
Address
REP String
Operation
I/O String
Operation
Valid I/O
Instruction
Input or
Output
Reserved
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The I/O trap dword is related to the I/O trap restart slot (see “I/O
Trap Restart Slot”). If bit 1 of the I/O trap dword is set by the
processor, it means that SMI# was asserted during the
execution of an I/O instruction. The SMI handler tests bit 1 to
see if there is a valid I/O instruction trapped. If the I/O
instruction is valid, the SMI handler is required to ensure the
I/O trap restart slot is set properly. The I/O trap restart slot
informs the processor whether it should re-execute the I/O
instruction after the RSM or execute the instruction following
the trapped I/O instruction.
Note: If SMI# is sampled asserted during an I/O bus cycle a
minimum of three clock edges before BRDY# is sampled
asserted, the associated I/O instruction is guaranteed to be
trapped by the SMI handler.
10.8
I/O Trap Restart Slot
The I/O trap restart slot at offset FF00h in the SMM state-save
area specifies whether the trapped I/O instruction should be
re-executed on return from SMM. This slot in the state-save area
is called the I/O instruction restart function. Re-executing a
trapped I/O instruction is useful, for example, if an I/O write
occurs to a disk that is powered down. The system logic
monitoring such an access can assert SMI#. Then the SMM
service routine would query the system logic, detect a failed I/O
write, take action to power-up the I/O device, enable the I/O
trap restart slot feature, and return from SMM.
The fields of the I/O trap restart slot are defined as follows:
■ Bits 31–16—Reserved
■ Bits 15–0—I/O instruction restart on return from SMM:
0000h = execute the next instruction after the trapped
I/O instruction
00FFh = re-execute the trapped I/O instruction
Table 46 shows the format of the I/O trap restart slot.
Table 46. I/O Trap Restart Slot
31–16
15–0
I/O Instruction restart on return from SMM:
Reserved
■
■
0000h = execute the next instruction after the trapped I/O
00FFh = re-execute the trapped I/O instruction
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The processor initializes the I/O trap restart slot to 0000h upon
entry into SMM. If SMM was entered due to a trapped I/O
instruction, the processor indicates the validity of the I/O
instruction by setting or clearing bit 1 of the I/O trap dword at
offset FFA4h in the SMM state-save area. The SMM service
routine should test bit 1 of the I/O trap dword to determine if a
valid I/O instruction was being executed when entering SMM
and before writing the I/O trap restart slot. If the I/O instruction
is valid, the SMM service routine can safely rewrite the I/O trap
restart slot with the value 00FFh, which causes the processor to
re-execute the trapped I/O instruction when the RSM
instruction is executed. If the I/O instruction is invalid, writing
the I/O trap restart slot has undefined results.
If a second SMI# is asserted and a valid I/O instruction was
trapped by the first SMM handler, the processor services the
second SMI# prior to re-executing the trapped I/O instruction.
The second entry into SMM never has bit 1 of the I/O trap dword
set, and the second SMM service routine must not rewrite the
I/O trap restart slot.
During a simultaneous SMI# I/O instruction trap and debug
breakpoint trap, the AMD-K6-2 processor first responds to the
SMI# and postpones recognizing the debug exception until
after returning from SMM via the RSM instruction. If the debug
registers DR3–DR0 are used while in SMM, they must be saved
and restored by the SMM handler. The processor automatically
saves and restores DR7–DR6. If the I/O trap restart slot in the
SMM state-save area contains the value 00FFh when the RSM
instruction is executed, the debug trap does not occur until
after the I/O instruction is re-executed.
10.9
Exceptions, Interrupts, and Debug in SMM
During an SMI# I/O trap, the exception/interrupt priority of the
AMD-K6-2 processor changes from its normal priority. The
normal priority places the debug traps at a priority higher than
the sampling of the FLUSH# or SMI# signals. However, during
an SMI# I/O trap, the sampling of the FLUSH# or SMI# signals
takes precedence over debug traps.
The processor recognizes the assertion of NMI within SMM
immediately after the completion of an IRET instruction. Once
NMI is recognized within SMM, NMI recognition remains
enabled until SMM is exited, at which point NMI masking is
restored to the state it was in before entering SMM.
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11
Test and Debug
The AMD-K6-2 processor implements various test and debug
modes to enable the functional and manufacturing testing of
systems and boards that use the processor. In addition, the
debug features of the processor allow designers to debug the
instruction execution of software components. This chapter
describes the following test and debug features:
■ Built-In Self-Test (BIST)—The BIST, which is invoked after
the falling transition of RESET, runs internal tests that
exercise most on-chip RAM structures.
■ Tri-State Test Mode—A test mode that causes the processor
to float its output and bidirectional pins.
■ Boundary-Scan Test Access Port (TAP)—The Joint Test Action
Group (JTAG) test access function defined by the IEEE
Standard Test Access Port and Boundary-Scan Architecture
(IEEE 1149.1-1990) specification.
■ Level-One (L1) Cache Inhibit—A feature that disables the
processor’s internal L1 instruction and data caches.
■ Debug Support—Consists of all x86-compatible software
debug features, including the debug extensions.
11.1
Built-In Self-Test (BIST)
Following the falling transition of RESET, the processor
unconditionally runs its BIST. The internal resources tested
during BIST include the following:
■ L1 instruction and data caches
■ Instruction and Data Translation Lookaside Buffers (TLBs)
The contents of the EAX general-purpose register after the
completion of reset indicate if the BIST was successful. If EAX
contains 0000_0000h, then BIST was successful. If EAX is
non-zero, the BIST failed. Following the completion of the BIST,
the processor jumps to address FFFF_FFF0h to start
instruction execution, regardless of the outcome of the BIST.
The BIST takes approximately 295,000 processor clocks to
complete.
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11.2
Tri-State Test Mode
The Tri-State Test mode causes the processor to float its output
and bidirectional pins, which is useful for board-level
manufacturing testing. In this mode, the processor is
electrically isolated from other components on a system board,
allowing automated test equipment (ATE) to test components
that drive the same signals as those the processor floats.
If the FLUSH# signal is sampled Low during the falling
transition of RESET, the processor enters the Tri-State Test
mode. (See “FLUSH# (Cache Flush)” on page 103 for the
specific sampling requirements.) The signals floated in the
Tri-State Test mode are as follows:
■ A[31:3]
■ ADS#
■ D/C#
■ M/IO#
■ PCD
■ D[63:0]
■ DP[7:0]
■ FERR#
■ HIT#
■ ADSC#
■ AP
■ PCHK#
■ PWT
■ APCHK#
■ BE[7:0]#
■ BREQ
■ CACHE#
■ SCYC
■ SMIACT#
■ W/R#
■ HITM#
■ HLDA
■ LOCK#
The VCC2DET, VCC2H/L#, and TDO signals are the only
outputs not floated in the Tri-State Test mode. VCC2DET and
VCC2H/L# must remain Low to ensure the system continues to
supply the specified processor core voltage to the V
pins.
CC2
TDO is never floated because the Boundary-Scan Test Access
Port must remain enabled at all times, including during the
Tri-State Test mode.
The Tri-State Test mode is exited when the processor samples
RESET asserted.
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11.3
Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP) is an IEEE standard
that defines synchronous scanning test methods for complex
logic circuits, such as boards containing a processor. The
AMD-K6-2 processor supports the TAP standard defined in the
IEEE Standard Test Access Port and Boundary-Scan Architecture
(IEEE 1149.1-1990) specification.
Boundary scan testing uses a shift register consisting of the
serial interconnection of boundary-scan cells that correspond to
each I/O buffer of the processor. This non-inverting register
chain, called a Boundary Scan Register (BSR), can be used to
capture the state of every processor pin and to drive every
processor output and bidirectional pin to a known state.
Each BSR of every component on a board that implements the
boundary-scan architecture can be serially interconnected to
enable component interconnect testing.
Test Access Port
The TAP consists of the following:
■ Test Access Port (TAP) Controller—The TAP controller is a
synchronous, finite state machine that uses the TMS and
TDI input signals to control a sequence of test operations.
See “TAP Controller State Machine” on page 232 for a list
of TAP states and their definition.
■ Instruction Register (IR)—The IR contains the instructions
that select the test operation to be performed and the Test
Data Register (TDR) to be selected. See “TAP Registers” on
page 224 for more details on the IR.
■ Test Data Registers (TDR)—The three TDRs are used to
process the test data. Each TDR is selected by an
instruction in the Instruction Register (IR). See “TAP
Registers” on page 224 for a list of these registers and their
functions.
TAP Signals
The test signals associated with the TAP controller are as
follows:
■ TCK—The Test Clock for all TAP operations. The rising edge
of TCK is used for sampling TAP signals, and the falling
edge of TCK is used for asserting TAP signals. The state of
the TMS signal sampled on the rising edge of TCK causes
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the state transitions of the TAP controller to occur. TCK can
be stopped in the logic 0 or 1 state.
■ TDI—The Test Data Input represents the input to the most
significant bit of all TAP registers, including the IR and all
test data registers. Test data and instructions are serially
shifted by one bit into their respective registers on the rising
edge of TCK.
■ TDO—The Test Data Output represents the output of the
least significant bit of all TAP registers, including the IR and
all test data registers. Test data and instructions are serially
shifted by one bit out of their respective registers on the
falling edge of TCK.
■ TMS—The Test Mode Select input specifies the test
function and sequence of state changes for boundary-scan
testing. If TMS is sampled High for five or more consecutive
clocks, the TAP controller enters its reset state.
■ TRST#—The Test Reset signal is an asynchronous reset that
unconditionally causes the TAP controller to enter its reset
state.
Refer to “Electrical Data” on page 253 and “Signal Switching
Characteristics” on page 267 to obtain the electrical
specifications of the test signals.
TAP Registers
The AMD-K6-2 processor provides an Instruction Register (IR)
and three Test Data Registers (TDR) to support the
boundary-scan architecture. The IR and one of the TDRs—the
Boundary-Scan Register (BSR)—consist of a shift register and
an output register. The shift register is loaded in parallel in the
Capture states. (See “TAP Controller State Machine” on page
232 for a description of the TAP controller states.) In addition,
the shift register is loaded and shifted serially in the Shift
states. The output register is loaded in parallel from its
corresponding shift register in the Update states.
Instruction Register (IR). The IR is a 5-bit register, without parity,
that determines which instruction to run and which test data
register to select. When the TAP controller enters the
Capture-IR state, the processor loads the following bits into the
IR shift register:
■ 01b—Loaded into the two least significant bits, as specified
by the IEEE 1149.1 standard
■ 000b—Loaded into the three most significant bits
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Loading 00001b into the IR shift register during the Capture-IR
state results in loading the SAMPLE/PRELOAD instruction.
For each entry into the Shift-IR state, the IR shift register is
serially shifted by one bit toward the TDO pin. During the shift,
the most significant bit of the IR shift register is loaded from
the TDI pin.
TheIRoutputregisterisloadedfromtheIRshiftregisterinthe
Update-IRstate,andthecurrentinstructionisdefinedbytheIR
outputregister.See“TAPInstructions”onpage231foralistand
definition of the instructions supported by the AMD-K6-2
processor.
Boundary Scan Register (BSR). The BSR is a Test Data Register
consisting of the interconnection of 152 boundary-scan cells.
Each output and bidirectional pin of the processor requires a
two-bit cell, where one bit corresponds to the pin and the other
bit is the output enable for the pin. When a 0 is shifted into the
enable bit of a cell, the corresponding pin is floated, and when a
1 is shifted into the enable bit, the pin is driven valid. Each
input pin requires a one-bit cell that corresponds to the pin. The
last cell of the BSR is reserved and does not correspond to any
processor pin.
The total number of bits that comprise the BSR is 281. The
order of the bits in the BSR differs between the Model 8/[7:0]
and the Model 8/[F:8] processors. Table 47 on page 227 and
Table 48 on page 229 list the order of these bits, respectively,
where TDI is the input to bit 280, and TDO is driven from the
output of bit 0. The entries listed as pin_E (where pin is an
output or bidirectional signal) are the enable bits.
If the BSR is the register selected by the current instruction
and the TAP controller is in the Capture-DR state, the processor
loads the BSR shift register as follows:
■ If the current instruction is SAMPLE/PRELOAD, then the
current state of each input, output, and bidirectional pin is
loaded. A bidirectional pin is treated as an output if its
enable bit equals 1, and it is treated as an input if its enable
bit equals 0.
■ If the current instruction is EXTEST, then the current state
of each input pin is loaded. A bidirectional pin is treated as
an input, regardless of the state of its enable.
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While in the Shift-DR state, the BSR shift register is serially
shifted toward the TDO pin. During the shift, bit 280 of the BSR
is loaded from the TDI pin.
The BSR output register is loaded with the contents of the BSR
shift register in the Update-DR state. If the current instruction
is EXTEST, the processor’s output pins, as well as those
bidirectional pins that are enabled as outputs, are driven with
their corresponding values from the BSR output register.
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Table 47. Boundary Scan Bit Definitions for Model 8/[7:0]
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
280 D35_E
279 D35
247 D21
246 D18_E
245 D18
244 D19_E
243 D19
242 D16_E
241 D16
214 D4_E
213 D4
181 A3
148 A20
115 A16
180 A31_E
179 A31
147 A13_E
146 A13
114 FERR_E
113 FERR#
112 HIT_E
111 HIT#
278 D29_E
277 D29
212 DP0_E
211 DP0
178 A21_E
177 A21
145 DP7_E
144 DP7
276 D33_E
275 D33
210 HOLD
209 BOFF#
208 AHOLD
207 STPCLK#
206 INIT
176 A30_E
175 A30
143 BE6_E
142 BE6#
141 A12_E
140 A12
110 BE7_E
109 BE7#
108 NA#
274 D27_E
273 D27
240 D17_E
239 D17
174 A7_E
173 A7
272 DP3_E
271 DP3
107 ADSC_E
106 ADSC#
105 BE5_E
104 BE5#
103 WB/WT#
102 PWT_E
101 PWT
238 D15_E
237 D15
236 DP1_E
235 DP1
234 D13_E
233 D13
232 D6_E
231 D6
205 IGNNE#
204 BF1
172 A24_E
171 A24
139 CLK
270 D25_E
269 D25
138 BE4_E
137 BE4#
136 A10_E
135 A10
203 BF2
170 A18_E
169 A18
268 D0_E
267 D0
202 RESET
201 BF0
168 A5_E
167 A5
266 D30_E
265 D30
200 FLUSH#
199 INTR
198 NMI
134 D63_E
133 D63
166 A22_E
165 A22
100 BE3_E
99 BE3#
264 DP2_E
263 DP2
132 BE2_E
131 BE2#
130 A15_E
129 A15
230 D14_E
229 D14
228 D11_E
227 D11
226 D1_E
225 D1
197 SMI#
196 A25_E
195 A25
164 EADS#
163 A4_E
162 A4
98 BREQ_E
97 BREQ
262 D2_E
261 D2
96 PCD_E
95 PCD
260 D28_E
259 D28
194 A23_E
193 A23
161 HITM_E
160 HITM#
159 A9_E
158 A9
128 BRDY#
127 BE1_E
126 BE1#
125 A14_E
124 A14
94 WR_E
93 W/R#
258 D24_E
257 D24
192 A26_E
191 A26
224 D12_E
223 D12
222 D10_E
221 D10
92 SMIACT_E
91 SMIACT#
90 EWBE#
89 DC_E
256 D26_E
255 D26
190 A29_E
189 A29
157 SCYC_E
156 SCYC
155 A8_E
154 A8
123 BRDYC#
122 BE0_E
121 BE0#
120 A17_E
119 A17
254 D22_E
253 D22
188 A28_E
187 A28
220 D7_E
219 D7
88 D/C#
252 D23_E
251 D23
186 A27_E
185 A27
153 A19_E
152 A19
87 APCHK_E
86 APCHK#
85 CACHE_E
84 CACHE#
83 ADS_E
218 D8_E
217 D8
250 D20_E
249 D20
184 A11_E
183 A11
151 A6_E
150 A6
118 KEN#
117 A20M#
116 A16_E
216 D9_E
215 D9
248 D21_E
182 A3_E
149 A20_E
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Table 47. Boundary Scan Bit Definitions for Model 8/[7:0] (continued)
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
82 ADS#
81 AP_E
80 AP
68 DP6_E
67 DP6
54 D53_E
53 D53
40 D43_E
39 D43
26 D38_E
25 D38
12 D3_E
11 D3
66 D54_E
65 D54
52 D47_E
51 D47
38 D62_E
37 D62
24 D58_E
23 D58
10 D39_E
79 INV
9
8
7
6
5
4
3
2
1
0
D39
78 HLDA_E
77 HLDA
76 PCHK_E
75 PCHK#
74 LOCK_E
73 LOCK#
72 MIO_E
71 M/IO#
70 D52_E
69 D52
64 D50_E
63 D50
50 D59_E
49 D59
36 D49_E
35 D49
22 D42_E
21 D42
D32_E
D32
62 D56_E
61 D56
48 D51_E
47 D51
34 DP4_E
33 DP4
20 D36_E
19 D36
D5_E
D5
60 D55_E
59 D55
46 D45_E
45 D45
32 D46_E
31 D46
18 D60_E
17 D60
D37_E
D37
58 D48_E
57 D48
44 D61_E
43 D61
30 D41_E
29 D41
16 D40_E
15 D40
D31_E
D31
56 D57_E
55 D57
42 DP5_E
41 DP5
28 D44_E
27 D44
14 D34_E
13 D34
Reserved
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Table 48. Boundary Scan Bit Definitions for Model 8/[F:8]
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
280 D35_E
279 D35
247 D19
214 BF1
181 A24
148 A14
115 BE7#
246 D16_E
245 D16
213 BF2
180 A18_E
179 A18
147 A17_E
146 A17
114 PCD_E
113 PCD
278 D29_E
277 D29
212 RESET
211 BF0
244 D17_E
243 D17
178 A5_E
177 A5
145 A16_E
144 A16
112 DC_E
276 D33_E
275 D33
210 FLUSH#
209 INTR
208 NMI
207 SMI#
206 A25_E
205 A25
111 D/C#
242 D15_E
241 D15
176 EADS#
175 A22_E
174 A22
143 HIT_E
142 HIT#
141 ADS_E
140 ADS#
139 CLK
110 WR_E
109 W/R#
108 NA#
274 D27_E
273 D27
240 DP1_E
239 DP1
238 D13_E
237 D13
272 DP0_E
271 DP0
173 AHOLD
172 HITM_E
171 HITM#
170 A4_E
169 A4
107 PWT_E
106 PWT
270 DP3_E
269 DP3
204 A26_E
203 A26
138 ADSC_E
137 ADSC#
136 BE0_E
135 BE0#
134 AP_E
133 AP
105 CACHE_E
104 CACHE#
103 WB/WT#
102 MIO_E
101 M/IO#
100 BREQ_E
99 BREQ
236 D6_E
235 D6
268 D25_E
267 D25
202 A29_E
201 A29
234 D14_E
233 D14
168 A9_E
167 A9
266 D0_E
265 D0
200 A28_E
199 A28
232 D11_E
231 D11
166 A8_E
165 A8
264 D30_E
263 D30
198 A23_E
197 A23
132 BE1_E
131 BE1#
130 BE2_E
129 BE2#
128 BRDY#
127 BE3_E
126 BE3#
125 BE4_E
124 BE4#
123 BRDYC#
122 BE5_E
121 BE5#
120 BE6_E
119 BE6#
118 KEN#
117 INV
230 D1_E
229 D1
164 A19_E
163 A19
98 SCYC_E
97 SCYC
262 DP2_E
261 DP2
196 A27_E
195 A27
228 D12_E
227 D12
162 BOFF#
161 A6_E
160 A6
96 LOCK_E
95 LOCK#
94 APCHK_E
93 APCHK#
92 PCHK_E
91 PCHK#
90 EWBE#
89 SMIACT_E
88 SMIACT#
87 FERR_E
86 FERR#
85 D20_E
84 D20
260 D2_E
259 D2
194 A11_E
193 A11
226 D10_E
225 D10
258 D28_E
257 D28
192 A3_E
191 A3
159 A20_E
158 A20
224 D7_E
223 D7
256 D24_E
255 D24
190 A31_E
189 A31
157 A13_E
156 A13
222 D8_E
221 D8
254 D26_E
253 D26
188 A21_E
187 A21
155 A12_E
154 A12
220 D9_E
219 D9
252 D21_E
251 D21
186 A30_E
185 A30
153 A10_E
152 A10
218 HOLD
217 STPCLK#
216 INIT
215 IGNNE#
250 D18_E
249 D18
184 A7_E
183 A7
151 A15_E
150 A15
248 D19_E
182 A24_E
149 A14_E
116 BE7_E
83 D22_E
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Table 48. Boundary Scan Bit Definitions for Model 8/[F:8] (continued)
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
82 D22
68 D54_E
67 D54
54 D47_E
53 D47
40 D62_E
39 D62
26 D38_E
25 D38
12 D3_E
11 D3
81 D23_E
80 D23
66 D50_E
65 D50
52 D59_E
51 D59
38 D49_E
37 D49
24 D58_E
23 D58
10 D39_E
79 A20M#
78 HLDA_E
77 HLDA
76 DP7_E
75 DP7
9
8
7
6
5
4
3
2
1
0
D39
64 D56_E
63 D56
50 D51_E
49 D51
36 DP4_E
35 DP4
22 D42_E
21 D42
D32_E
D32
62 D55_E
61 D55
48 D45_E
47 D45
34 D4_E
33 D4
20 D36_E
19 D36
D5_E
D5
74 D63_E
73 D63
60 D48_E
59 D48
46 D61_E
45 D61
32 D46_E
31 D46
18 D60_E
17 D60
D37_E
D37
72 D52_E
71 D52
58 D57_E
57 D57
44 DP5_E
43 DP5
30 D41_E
29 D41
16 D40_E
15 D40
D31_E
D31
70 DP6_E
69 DP6
56 D53_E
55 D53
42 D43_E
41 D43
28 D44_E
27 D44
14 D34_E
13 D34
Reserved
Device Identification Register (DIR). The DIR is a 32-bit Test Data
Register selected during the execution of the IDCODE
instruction. The fields of the DIR and their values are shown in
Table 49 and are defined as follows:
■ Version Code—This 4-bit field is incremented by AMD
manufacturing for each major revision of silicon.
■ Part Number—This 16-bit field identifies the specific
processor model.
■ Manufacturer—This 11-bit field identifies the manufacturer
of the component (AMD).
■ LSB—The least significant bit (LSB) of the DIR is always set
to 1, as specified by the IEEE 1149.1 standard.
Table 49. Device Identification Register
Version Code
(Bits 31–28)
Part Number
(Bits 27–12)
Manufacturer
(Bits 11–1)
LSB
(Bit 0)
Xh
0580h
00000000001b
1b
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Bypass Register (BR). The BR is a Test Data Register consisting of
a 1-bit shift register that provides the shortest path between
TDI and TDO. When the processor is not involved in a test
operation, the BR can be selected by an instruction to allow the
transfer of test data through the processor without having to
serially scan the test data through the BSR. This functionality
preserves the state of the BSR and significantly reduces test
time.
The BR register is selected by the BYPASS and HIGHZ
instructions as well as by any instructions not supported by the
AMD-K6-2 processor.
TAP Instructions
The processor supports the three instructions required by the
IEEE 1149.1 standard—EXTEST, SAMPLE/PRELOAD, and
BYPASS—as well as two additional optional instructions—
IDCODE and HIGHZ.
Table 50 shows the complete set of TAP instructions supported
by the processor along with the 5-bit Instruction Register
encoding and the register selected by each instruction.
Table 50. Supported Tap Instructions
Instruction
Encoding
00000b
Register
BSR
BSR
DIR
Description
Sample inputs and drive outputs
Sample inputs and outputs, then load the BSR
Read DIR
1
EXTEST
SAMPLE / PRELOAD
IDCODE
00001b
00010b
HIGHZ
00011b
BR
Float outputs and bidirectional pins
Undefined instruction, execute the BYPASS instruction
2
00100b–11110b
BR
BYPASS
3
11111b
BR
Connect TDI to TDO to bypass the BSR
BYPASS
Notes:
1. Following the execution of the EXTEST instruction, the processor must be reset in order to return to normal, non-test operation.
2. These instruction encodings are undefined on the AMD-K6-2 processor and default to the BYPASS instruction.
3. Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open
during an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.
EXTEST. When the EXTEST instruction is executed, the
processor loads the BSR shift register with the current state of
the input and bidirectional pins in the Capture-DR state and
drives the output and bidirectional pins with the corresponding
values from the BSR output register in the Update-DR state.
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SAMPLE/PRELOAD. The SAMPLE/PRELOAD instruction performs
two functions. These functions are as follows:
■ During the Capture-DR state, the processor loads the BSR
shift register with the current state of every input, output,
and bidirectional pin.
■ During the Update-DR state, the BSR output register is
loaded from the BSR shift register in preparation for the
next EXTEST instruction.
The SAMPLE/PRELOAD instruction does not affect the normal
operational state of the processor.
BYPASS. The BYPASS instruction selects the BR register, which
reduces the boundary-scan length through the processor from
281 to one (TDI to BR to TDO). The BYPASS instruction does
not affect the normal operational state of the processor.
IDCODE. The IDCODE instruction selects the DIR register,
allowing the device identification code to be shifted out of the
processor. This instruction is loaded into the IR when the TAP
controller is reset. The IDCODE instruction does not affect the
normal operational state of the processor.
HIGHZ. The HIGHZ instruction forces all output and
bidirectional pins to be floated. During this instruction, the BR
is selected and the normal operational state of the processor is
not affected.
TAP Controller State
Machine
The TAP controller state diagram is shown in Figure 86 on page
233. State transitions occur on the rising edge of TCK. The logic
0 or 1 next to the states represents the value of the TMS signal
sampled by the processor on the rising edge of TCK.
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AMD-K6 -2 Processor Data Sheet
Test-Logic-Reset
1
0
0
1
1
1
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0
0
Capture-IR
0
1
1
Capture-DR
0
Shift-DR
Shift-IR
0
0
1
1
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
0
0
1
1
Exit2-DR
0
Exit2-IR
0
1
1
Update-DR
Update-IR
1
0
1
0
IEEE Std 1149.1-1990, Copyright © 1990. IEEE. All rights reserved
Figure 86. TAP State Diagram
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The states of the TAP controller are described as follows:
Test-Logic-Reset. This state represents the initial reset state of the
TAP controller and is entered when the processor samples
RESET asserted, when TRST# is asynchronously asserted, and
when TMS is sampled High for five or more consecutive clocks.
In addition, this state can be entered from the Select-IR-Scan
state. The IR is initialized with the IDCODE instruction, and
the processor’s normal operation is not affected in this state.
Capture-DR. During the SAMPLE/PRELOAD instruction, the
processor loads the BSR shift register with the current state of
every input, output, and bidirectional pin. During the EXTEST
instruction, the processor loads the BSR shift register with the
current state of every input and bidirectional pin.
Capture-IR. When the TAP controller enters the Capture-IR state,
the processor loads 01b into the two least significant bits of the
IR shift register and loads 000b into the three most significant
bits of the IR shift register.
Shift-DR. While in the Shift-DR state, the selected TDR shift
register is serially shifted toward the TDO pin. During the shift,
the most significant bit of the TDR is loaded from the TDI pin.
Shift-IR. While in the Shift-IR state, the IR shift register is
serially shifted toward the TDO pin. During the shift, the most
significant bit of the IR is loaded from the TDI pin.
Update-DR. During the SAMPLE/PRELOAD instruction, the BSR
output register is loaded with the contents of the BSR shift
register. During the EXTEST instruction, the output pins, as
well as those bidirectional pins defined as outputs, are driven
with their corresponding values from the BSR output register.
Update-IR. In this state, the IR output register is loaded from the
IR shift register, and the current instruction is defined by the
IR output register.
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The following states have no effect on the normal or test
operation of the processor other than as shown in Figure 86 on
page 233:
■ Run-Test/Idle—This state is an idle state between scan
operations.
■ Select-DR-Scan—This is the initial state of the test data
register state transitions.
■ Select-IR-Scan—This is the initial state of the Instruction
Register state transitions.
■ Exit1-DR—This state is entered to terminate the shifting
process and enter the Update-DR state.
■ Exit1-IR—This state is entered to terminate the shifting
process and enter the Update-IR state.
■ Pause-DR—This state is entered to temporarily stop the
shifting process of a Test Data Register.
■ Pause-IR—This state is entered to temporarily stop the
shifting process of the Instruction Register.
■ Exit2-DR—This state is entered in order to either terminate
the shifting process and enter the Update-DR state or to
resume shifting following the exit from the Pause-DR state.
■ Exit2-IR—This state is entered in order to either terminate
the shifting process and enter the Update-IR state or to
resume shifting following the exit from the Pause-IR state.
11.4
L1 Cache Inhibit
Purpose
The AMD-K6-2 processor provides a means for inhibiting the
normal operation of its L1 instruction and data caches while
still supporting an external cache. This capability allows system
designers to disable the L1 cache during the testing and debug
of an external cache.
If the Cache Inhibit bit (bit 3) of Test Register 12 (TR12) is set
to 0, the processor’s L1 cache is enabled and operates as
described in “Cache Organization” on page 179. If the Cache
Inhibit bit is set to 1, the L1 cache is disabled and no new cache
lines are allocated. Even though new allocations do not occur,
valid L1 cache lines remain valid and are read by the processor
when a requested address hits a cache line. In addition, the
processor continues to support inquire cycles initiated by the
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system logic, including the execution of writeback cycles when
a modified cache line is hit.
While the L1 is inhibited, the processor continues to drive the
PCD output signal appropriately, which system logic can use to
control external caching.
In order to completely disable the L1 cache so no valid lines
exist in the cache, the Cache Inhibit bit must be set to 1 and the
cache must be flushed in one of the following ways:
■ Asserting the FLUSH# input signal
■ Executing the WBINVD instruction
■ Executing the INVD instruction (modified cache lines are
not written back to memory)
■ Make use of the Page Flush/Invalidate Register (PFIR)
(AMD-K6-2/[F:8] only)(see “PFIR” on page 195)
11.5
Debug
The AMD-K6-2 processor implements the standard x86 debug
functions, registers, and exceptions. In addition, the processor
supports the I/O breakpoint debug extension. The debug
feature assists programmers and system designers during
software execution tracing by generating exceptions when one
or more events occur during processor execution. The exception
handler, or debugger, can be written to perform various tasks,
such as displaying the conditions that caused the breakpoint to
occur, displaying and modifying register or memory contents, or
single-stepping through program execution.
The following sections describe the debug registers and the
various types of breakpoints and exceptions that the processor
supports.
Debug Registers
Figures 87 through 90 show the 32-bit debug registers
supported by the processor.
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Symbol
Description
Bits
LEN 3
R/W 3
LEN 2
R/W 2
LEN 1
R/W 1
LEN 0
R/W 0
Length of Breakpoint #3
31–30
Type of Transaction(s) to Trap 29–28
Length of Breakpoint #2 27–26
Type of Transaction(s) to Trap 25–24
Length of Breakpoint #1 23–22
Type of Transaction(s) to Trap 21–20
Length of Breakpoint #0 19–18
Type of Transaction(s) to Trap 17–16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G
D
G
E
L
E
G
3
L
3
L
2
L
2
G
1
L
1
G
0
L
0
LEN
3
R/W LEN R/W
LEN
1
R/W LEN
R/W
0
3
2
2
1
0
Reserved
Symbol
GD
GE
LE
Description
General Detect Enabled
Global Exact Breakpoint Enabled
Local Exact Breakpoint Enabled
Bit
13
9
8
G3
L3
G2
L2
G1
L1
G0
L0
Global Exact Breakpoint # 3 Enabled
Local Exact Breakpoint # 3 Enabled
Global Exact Breakpoint # 2 Enabled
Local Exact Breakpoint # 2 Enabled
Global Exact Breakpoint # 1 Enabled
Local Exact Breakpoint # 1 Enabled
Global Exact Breakpoint # 0 Enabled
Local Exact Breakpoint # 0 Enabled
7
6
5
4
3
2
1
0
Figure 87. Debug Register DR7
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
B
D
B
1
B
S
B
2
B
0
B
T
B
3
Reserved
Symbol
BT
BS
Description
Breakpoint Task Switch
Breakpoint Single Step
Bit
15
14
BD
B3
B2
B1
B0
Breakpoint Debug Access Detected 13
Breakpoint #3 Condition Detected
Breakpoint #2 Condition Detected
Breakpoint #1 Condition Detected
Breakpoint #0 Condition Detected
3
2
1
0
Figure 88. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
Figure 89. Debug Registers DR5 and DR4
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DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 3 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
DR2
DR1
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 2 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 1 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 0 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
Figure 90. Debug Registers DR3, DR2, DR1, and DR0
DR3–DR0. The processor allows the setting of up to four
breakpoints. DR3–DR0 contain the linear addresses for
breakpoint 3 through breakpoint 0, respectively, and are
compared to the linear addresses of processor cycles to
determine if a breakpoint occurs. Debug register DR7 defines
the specific type of cycle that must occur in order for the
breakpoint to occur.
DR5–DR4. When debugging extensions are disabled (bit 3 of CR4
is set to 0), the DR5 and DR4 registers are mapped to DR7 and
DR6, respectively, in order to be software compatible with
previous generations of x86 processors. When debugging
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extensions are enabled (bit 3 of CR4 is set to 1), any attempt to
load DR5 or DR4 results in an undefined opcode exception.
Likewise, any attempt to store DR5 or DR4 also results in an
undefined opcode exception.
DR6. If a breakpoint is enabled in DR7, and the breakpoint
conditions as defined in DR7 occur, then the corresponding
B-bit (B3–B0) in DR6 is set to 1. In addition, any other
breakpoints defined using these particular breakpoint
conditions are reported by the processor by setting the
appropriate B-bits in DR6, regardless of whether these
breakpoints are enabled or disabled. However, if a breakpoint is
not enabled, a debug exception does not occur for that
breakpoint.
If the processor decodes an instruction that writes or reads DR7
through DR0, the BD bit (bit 13) in DR6 is set to 1 (if enabled in
DR7) and the processor generates a debug exception. This
operation allows control to pass to the debugger prior to debug
register access by software.
If the Trap Flag (bit 8) of the EFLAGS register is set to 1, the
processor generates a debug exception after the successful
execution of every instruction (single-step operation) and sets
the BS bit (bit 14) in DR6 to indicate the source of the
exception.
When the processor switches to a new task and the debug trap
bit (T-bit) in the corresponding Task State Segment (TSS) is set
to 1, the processor sets the BT bit (bit 15) in DR6 and generates
a debug exception.
DR7. When set to 1, L3–L0 locally enable breakpoints 3 through
0, respectively. L3–L0 are set to 0 whenever the processor
executes a task switch. Setting L3–L0 to 0 disables the
breakpoints and ensures that these particular debug exceptions
are only generated for a specific task.
When set to 1, G3–G0 globally enable breakpoints 3 through 0,
respectively. Unlike L3–L0, G3–G0 are not set to 0 whenever the
processor executes a task switch. Not setting G3–G0 to 0 allows
breakpoints to remain enabled across all tasks. If a breakpoint
is enabled globally but disabled locally, the global enable
overrides the local enable.
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The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the
operation of the processor and are provided in order to be
software compatible with previous generations of x86
processors.
When set to 1, the GD bit in DR7 (bit 13) enables the debug
exception associated with the BD bit (bit 13) in DR6. This bit is
set to 0 when a debug exception is generated.
LEN3–LEN0 and RW3–RW0 are two-bit fields in DR7 that
specify the length and type of each breakpoint as defined in
Table 51.
Table 51. DR7 LEN and RW Definitions
1
RW Bits
Breakpoint
LEN Bits
00b
00b
01b
2
Instruction Execution
One-byte Data Write
00b
01b
Two-byte Data Write
11b
Four-byte Data Write
00b
01b
One-byte I/O Read or Write
Two-byte I/O Read or Write
Four-byte I/O Read or Write
One-byte Data Read or Write
Two-byte Data Read or Write
Four-byte Data Read or Write
3
10b
11b
00b
01b
11b
11b
Notes:
1. LEN bits equal to 10b is undefined.
2. When RW equals 00b, LEN must be equal to 00b.
3. When RW equals 10b, debugging extensions (DE) must be enabled (bit 3 of CR4 must be set
to 1). If DE is set to 0, then RW equal to 10b is undefined.
Debug Exceptions
A debug exception is categorized as either a debug trap or a
debug fault. A debug trap calls the debugger following the
execution of the instruction that caused the trap. A debug fault
calls the debugger prior to the execution of the instruction that
caused the fault. All debug traps and faults generate either an
Interrupt 01h or an Interrupt 03h exception.
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Interrupt 01h. The following events are considered debug traps
that cause the processor to generate an Interrupt 01h
exception:
■ Enabled breakpoints for data and I/O cycles
■ Single Step Trap
■ Task Switch Trap
The following events are considered debug faults that cause the
processor to generate an Interrupt 01h exception:
■ Enabled breakpoints for instruction execution
■ BD bit in DR6 set to 1
Interrupt 03h. The INT 3 instruction is defined in the x86
architecture as a breakpoint instruction. This instruction
causes the processor to generate an Interrupt 03h exception.
This exception is a debug trap because the debugger is called
following the execution of the INT 3 instruction.
The INT 3 instruction is a one-byte instruction (opcode CCh)
typically used to insert a breakpoint in software by writing CCh
to the address of the first byte of the instruction to be trapped
(the target instruction). Following the trap, if the target
instruction is to be executed, the debugger must replace the
INT 3 instruction with the first byte of the target instruction.
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12
Clock Control
The AMD-K6-2 processor supports five modes of clock control.
The processor can transition between these modes to maximize
performance, to minimize power dissipation, or to provide a
balance between performance and power. (See “Power
Dissipation” on page 257 for the maximum power dissipation of
the AMD-K6-2 processor within the normal and reduced-power
states.)
The five clock-control states supported are as follows:
■ Normal State: The processor is running in Real Mode,
Virtual-8086 Mode, Protected Mode, or System Management
Mode (SMM). In this state, all clocks are running—including
the external bus clock CLK and the internal processor
clock—and the full features and functions of the processor
are available.
■ Halt State: This low-power state is entered following the
successful execution of the HLT instruction. During this
state, the internal processor clock is stopped.
■ Stop Grant State: This low-power state is entered following
the recognition of the assertion of the STPCLK# signal.
During this state, the internal processor clock is stopped.
■ Stop Grant Inquire State: This state is entered from the Halt
state and the Stop Grant state as the result of a
system-initiated inquire cycle.
■ Stop Clock State: This low-power state is entered from the
Stop Grant state when the CLK signal is stopped.
The following sections describe each of the four low-power
states. Figure 91 on page 248 illustrates the clock control state
transitions.
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12.1
Halt State
Enter Halt State
During the execution of the HLT instruction, the AMD-K6-2
processor executes a Halt special cycle. After BRDY# is
sampled asserted during this cycle, and then EWBE# is also
sampled asserted (if not masked off), the processor enters the
Halt state in which the processor disables most of its internal
clock distribution. In order to support the following operations,
the internal phase-lock loop (PLL) still runs, and some internal
resources are still clocked in the Halt state:
■ Inquire Cycles: The processor continues to sample AHOLD,
BOFF#, and HOLD in order to support inquire cycles that
are initiated by the system logic. The processor transitions to
the Stop Grant Inquire state during the inquire cycle. After
returning to the Halt state following the inquire cycle, the
processor does not execute another Halt special cycle.
■ Flush Cycles: The processor continues to sample FLUSH#. If
FLUSH# is sampled asserted, the processor performs the
flush operation in the same manner as it is performed in the
Normal state. Upon completing the flush operation, the
processor executes the Halt special cycle which indicates
the processor is in the Halt state.
■ Time Stamp Counter (TSC): The TSC continues to count in
the Halt state.
■ Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
After entering the Halt state, all signals driven by the processor
retain their state as they existed following the completion of
the Halt special cycle.
Exit Halt State
The AMD-K6-2 processor remains in the Halt state until it
samples INIT, INTR (if interrupts are enabled), NMI, RESET, or
SMI# asserted. If any of these signals is sampled asserted, the
processor returns to the Normal state and performs the
corresponding operation. All of the normal requirements for
recognition of these input signals apply within the Halt state.
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12.2
Stop Grant State
Enter Stop Grant
State
After recognizing the assertion of STPCLK#, the AMD-K6-2
processor flushes its instruction pipelines, completes all
pending and in-progress bus cycles, and acknowledges the
STPCLK# assertion by executing a Stop Grant special bus cycle.
After BRDY# is sampled asserted during this cycle, and then
EWBE# is also sampled asserted (if not masked off), the
processor enters the Stop Grant state. The Stop Grant state is
like the Halt state in that the processor disables most of its
internal clock distribution in the Stop Grant state. In order to
support the following operations, the internal PLL still runs,
and some internal resources are still clocked in the Stop Grant
state:
■ Inquire cycles: The processor transitions to the Stop Grant
Inquire state during an inquire cycle. After returning to the
Stop Grant state following the inquire cycle, the processor
does not execute another Stop Grant special cycle.
■ Time Stamp Counter (TSC): The TSC continues to count in
the Stop Grant state.
■ Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
FLUSH# is not recognized in the Stop Grant state (unlike while
in the Halt state).
Upon entering the Stop Grant state, all signals driven by the
processor retain their state as they existed following the
completion of the Stop Grant special cycle.
Exit Stop Grant State
The AMD-K6-2 processor remains in the Stop Grant state until
it samples STPCLK# negated or RESET asserted. If STPCLK#
is sampled negated, the processor returns to the Normal state in
less than 10 bus clock (CLK) periods. After the transition to the
Normal state, the processor resumes execution at the
instruction boundary on which STPCLK# was initially
recognized.
If STPCLK# is recognized as negated in the Stop Grant state
and subsequently sampled asserted prior to returning to the
Normal state, the AMD-K6-2 processor guarantees that a
minimum of one instruction is executed prior to re-entering the
Stop Grant state.
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If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or
SMI# are sampled asserted in the Stop Grant state, the
processor latches the edge-sensitive signals (INIT, FLUSH#,
NMI, and SMI#), but otherwise does not exit the Stop Grant
state to service the interrupt. When the processor returns to the
Normal state due to sampling STPCLK# negated, any pending
interrupts are recognized after returning to the Normal state.
To ensure their recognition, all of the normal requirements for
these input signals apply within the Stop Grant state.
If RESET is sampled asserted in the Stop Grant state, the
processor immediately returns to the Normal state and the
reset process begins.
12.3
Stop Grant Inquire State
Enter Stop Grant
Inquire State
The Stop Grant Inquire state is entered from the Stop Grant
state or the Halt state when EADS# is sampled asserted during
an inquire cycle initiated by the system logic. The AMD-K6-2
processor responds to an inquire cycle in the same manner as in
the Normal state by driving HIT# and HITM#. If the inquire
cycle hits a modified data cache line, the processor performs a
writeback cycle.
Exit Stop Grant
Inquire State
Following the completion of any writeback, the processor
returns to the state from which it entered the Stop Grant
Inquire state.
12.4
Stop Clock State
Enter Stop Clock
State
If the CLK signal is stopped while the AMD-K6-2 processor is in
the Stop Grant state, the processor enters the Stop Clock state.
Because all internal clocks and the PLL are not running in the
Stop Clock state, the Stop Clock state represents the
minimum-power state of all clock control states. The CLK signal
must be held Low while it is stopped.
The Stop Clock state cannot be entered from the Halt state.
INTR is the only input signal that is allowed to change states
while the processor is in the Stop Clock state. However, INTR is
not sampled until the processor returns to the Stop Grant state.
All other input signals must remain unchanged in the Stop
Clock state.
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Exit Stop Clock State
The AMD-K6-2 processor returns to the Stop Grant state from
the Stop Clock state after the CLK signal is started and the
internal PLL has stabilized. PLL stabilization is achieved after
the CLK signal has been running within its specification for a
minimum of 1.0 ms.
The frequency of CLK when exiting the Stop Clock state can be
different than the frequency of CLK when entering the Stop
Clock state.
The state of the BF[2:0] signals when exiting the Stop Clock
state is ignored because the BF[2:0] signals are only sampled
during the falling transition of RESET.
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STPCLK# Asserted
HLT Instruction
Normal Mode
- Real
- Virtual-8086
- Protected
- SMM
STPCLK# Negated,
or RESET Asserted
RESET, SMI#, INIT,
or INTR Asserted
EADS# Asserted
EADS# Asserted
Stop Grant
Inquire
State
Halt
State
Stop Grant
State
Writeback
Completed
Writeback
Completed
CLK
Stopped
CLK
Started
Stop Clock
State
Figure 91. Clock Control State Transitions
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13
Power and Grounding
13.1
Power Connections
The AMD-K6-2 processor is a dual voltage device. Two separate
supply voltages are required: V and V . V provides the
CC2
CC3
CC2
core voltage for the processor and V
provides the I/O voltage.
CC3
See “Electrical Data” on page 253 for the value and range of
V
and V
.
CC3
CC2
There are 28 V
, 32 V
, and 68 V pins on the AMD-K6-2
CC3 SS
CC2
processor. (See “Pin Designations” on page 297 for all power
and ground pin designations.) The large number of power and
ground pins are provided to ensure that the processor and
package maintain a clean and stable power distribution
network.
For proper operation and functionality, all V
, V
, and V
CC3 SS
CC2
pins must be connected to the appropriate planes in the circuit
board. The power planes have been arranged in a pattern to
simplify routing and minimize crosstalk on the circuit board.
The isolation region between two voltage planes must be at
least 0.254mm if they are in the same layer of the circuit board.
(See Figure 92 on page 250.) In order to maintain a
low-impedance current sink and reference, the ground plane
must never be split.
Although the AMD-K6-2 processor has two separate supply
voltages, there are no special power sequencing requirements.
The best procedure is to minimize the time between which V
CC2
and V
are either both on or both off.
CC3
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0.254mm (min.) for
isolation region
C20
C17
C18
C5
C6
C21
C22
C23
C24
C25
C19
C7
CC3
CC4
+
+
C1
C2
+
+
CC5
CC6
+
C27
C28
C11
C12
C13
C29
C30
C31
C26
VCC3 (I/O) Plane
VCC2 (Core) Plane
CC1
CC2
Figure 92. Suggested Component Placement
13.2
Decoupling Recommendations
In addition to the isolation region mentioned in “Power
Connections” on page 249, adequate decoupling capacitance is
required between the two system power planes and the ground
plane to minimize ringing and to provide a low-impedance path
for return currents. Suggested decoupling capacitor placement
is shown in Figure 92.
Surface mounted capacitors should be used under the
processor’s ZIF socket to minimize resistance and inductance in
the lead lengths while maintaining minimal height. For
information and recommendations about the specific value,
®
quantity, and location of the capacitors, see the AMD-K6
Processor Power Supply Design Application Note, order# 21103.
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13.3
Pin Connection Requirements
For proper operation, the following requirements for signal pin
connections must be met:
■ Do not drive address and data signals into large capacitive
loads at high frequencies. If necessary, use buffer chips to
drive large capacitive loads.
■ Leave all NC (no-connect) pins unconnected.
■ Unused inputs should always be connected to an
appropriate signal level.
•
•
Active Low inputs that are not being used should be
connected to V through a 20-kohm pullup resistor.
CC3
Active High inputs that are not being used should be
connected to GND through a pulldown resistor.
■ Reserved signals can be treated in one of the following ways:
•
•
•
As no-connect (NC) pins, in which case these pins are left
unconnected
As pins connected to the system logic as defined by the
industry-standard Super7 and Socket 7 interface
Any combination of NC and Socket 7 pins
■ Keep trace lengths to a minimum.
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14
Electrical Data
This chapter consists of two sections, where each section
provides the electrical specifications of the AMD-K6-2
processor based on specific Ordering Part Number (OPN)
suffixes. See “Ordering Information” on page 301 for a
complete list and description of the valid OPN combinations.
14.1
Electrical Data for OPN Suffixes AHX, 400AFQ, and AFR
The electrical specifications provided in this section pertain to
the following OPNs:
■ AMD-K6-2/475AHX
■ AMD-K6-2/380AFR
■ AMD-K6-2/333AFR
■ AMD-K6-2/450AHX
■ AMD-K6-2/366AFR
■ AMD-K6-2/300AFR
■ AMD-K6-2/400AFQ
■ AMD-K6-2/350AFR
■ AMD-K6-2/266AFR
Note: The electrical specifications for the AMD-K6-2/400AFR OPN
are provided in “Electrical Data for OPN Suffixes AGR,
AFX, and 400AFR” on page 258.
Operating Ranges
The AMD-K6-2 processor is designed to provide functional
operation if the voltage and temperature parameters are within
the limits defined in Table 52.
Table 52. Operating Ranges for OPN Suffixes AHX, 400AFQ, and AFR
Parameter
Minimum
2.1 V
Typical
2.2 V
Maximum
2.3 V
Comments
Note 1, 2
Note 1, 3
Note 1
V
V
CC2
CC3
2.3 V
2.4 V
2.5 V
3.135 V
3.30 V
3.6 V
70°C
Note 4
T
65°C
Note 5
0°C
CASE
60°C
Note 6
Notes:
1. VCC2 and VCC3 are referenced from VSS.
2. VCC2 specification for 2.2 V component.
3. VCC2 specification for 2.4 V component.
4. Case temperature range required for AMD-K6-2/xxxAFR valid ordering part number
combinations, where “xxx” represents the processor core frequency.
5. Case temperature range required for AMD-K6-2/xxxAHX valid ordering part number
combinations, where “xxx” represents the processor core frequency.
6. Case temperature range required for AMD-K6-2/xxxAFQ valid ordering part number
combinations, where “xxx” represents the processor core frequency.
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Absolute Ratings
The AMD-K6-2 processor is not designed to be operated beyond
the operating ranges listed in Table 52. Exposure to conditions
outside these operating ranges for extended periods of time can
affect long-term reliability. Permanent damage can occur if the
absolute ratings listed in Table 53 are exceeded.
Table 53. Absolute Ratings for OPN Suffixes AHX, 400AFQ, and AFR
Parameter
Minimum
–0.5 V
Maximum
2.6 V
Comments
V
CC2
V
–0.5 V
3.6 V
CC3
V
+ 0.5 V and
≤ 4.0 V
CC3
V
–0.5 V
Note
PIN
T
(under bias)
–65°C
–65°C
+110°C
+150°C
CASE
T
STORAGE
Note:
VPIN (the voltage on any I/O pin) must not be greater than 0.5 V above the voltage being
applied to VCC3. In addition, the VPIN voltage must never exceed 4.0 V.
DC Characteristics
The DC characteristics of the AMD-K6-2 processor are shown in
Table 54.
Table 54. DC Characteristics for OPN Suffixes AHX, 400AFQ, and AFR
Preliminary Data
Symbol
Parameter Description
Comments
Min
Max
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3 V
2.0 V
+0.8 V
IL
V
V
+0.3V
CC3
Note 1
IH
V
I
= 4.0-mA load
= 3.0-mA load
0.4 V
OL
OL
V
I
OH
2.4 V
OH
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.3 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC2 = 2.5 V — The maximum power supply current must be taken into account when designing a power supply.
4. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
5. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
6. Refers to inputs with an internal pullup and VIL = 0.4 V.
7. Refers to inputs with an internal pulldown and VIH = 2.4 V.
8. This specification applies to components using a CLK frequency of 66 MHz.
9. This specification applies to components using a CLK frequency of 95 MHz.
10. This specification applies to components using a CLK frequency of 100 MHz.
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Table 54. DC Characteristics for OPN Suffixes AHX, 400AFQ, and AFR (continued)
Preliminary Data
Symbol
Parameter Description
2.2 V Power Supply Current
2.4 V Power Supply Current
Comments
Min
Max
7.35 A
8.45 A
9.40 A
9.85 A
10.30 A
10.70 A
11.25 A
12.50 A
13.00 A
0.54 A
0.56 A
0.58 A
0.60 A
0.60 A
0.61 A
0.62 A
0.66 A
0.67 A
±15 µA
266 MHz, Note 2, 8
300 MHz, Note 2, 8, 10
333 MHz, Note 2, 8, 9
350 MHz, Note 2, 10
366 MHz, Note 2, 8
380 MHz, Note 2, 9
400 MHz, Note 2, 8, 10
450 MHz, Note 3, 10
475 MHz, Note 3, 9
266 MHz, Note 4, 8
300 MHz, Note 4, 8, 10
333 MHz, Note 4, 8, 9
350 MHz, Note 4, 10
366 MHz, Note 4, 8
380 MHz, Note 4, 9
400 MHz, Note 4, 8, 10
450 MHz, Note 4, 10
475 MHz, Note 4, 9
Note 5
I
CC2
I
3.3 V Power Supply Current
CC3
I
Input Leakage Current
Output Leakage Current
LI
I
±15 µA
–400 µA
200 µA
10 pF
Note 5
Note 6
Note 7
LO
I
Input Leakage Current Bias with Pullup
Input Leakage Current Bias with Pulldown
Input Capacitance
IL
I
IH
C
IN
C
Output Capacitance
15 pF
OUT
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.3 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC2 = 2.5 V — The maximum power supply current must be taken into account when designing a power supply.
4. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
5. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
6. Refers to inputs with an internal pullup and VIL = 0.4 V.
7. Refers to inputs with an internal pulldown and VIH = 2.4 V.
8. This specification applies to components using a CLK frequency of 66 MHz.
9. This specification applies to components using a CLK frequency of 95 MHz.
10. This specification applies to components using a CLK frequency of 100 MHz.
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Table 54. DC Characteristics for OPN Suffixes AHX, 400AFQ, and AFR (continued)
Preliminary Data
Symbol
Parameter Description
Comments
Min
Max
C
I/O Capacitance
CLK Capacitance
20 pF
10 pF
10 pF
15 pF
10 pF
OUT
C
CLK
C
Test Input Capacitance (TDI, TMS, TRST#)
Test Output Capacitance (TDO)
TCK Capacitance
TIN
C
TOUT
C
TCK
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.3 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC2 = 2.5 V — The maximum power supply current must be taken into account when designing a power supply.
4. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
5. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
6. Refers to inputs with an internal pullup and VIL = 0.4 V.
7. Refers to inputs with an internal pulldown and VIH = 2.4 V.
8. This specification applies to components using a CLK frequency of 66 MHz.
9. This specification applies to components using a CLK frequency of 95 MHz.
10. This specification applies to components using a CLK frequency of 100 MHz.
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Power Dissipation
Table 55 contains the typical and maximum power dissipation
of the AMD-K6-2 processor during normal and reduced power
states.
Table 55. Typical and Maximum Power Dissipation for OPN Suffixes AHX, 400AFQ, and AFR
266
300
333
350
366
380
400
450
475
Clock Control
State
Notes
6
6,8
6,7
8
6
7
6,8
8
7
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Thermal Power
(Maximum)
14.70 W 17.20 W 19.00 W 19.95 W 20.80 W 21.60 W 22.70 W 28.40 W 29.60 W
8.85 W 10.35 W 11.40 W 11.98 W 12.48 W 12.95 W 13.65 W 17.05 W 17.75 W
3.90 W 3.92 W 3.94 W 3.96 W 3.96 W 3.97 W 3.98 W 6.50 W 6.51 W
3.50 W 3.50 W 3.50 W 3.50 W 3.50 W 3.50 W 3.50 W 6.00 W 6.00 W
1, 2
3
Thermal Power
(Typical)
Stop Grant / Halt
(Maximum)
4
Stop Clock
(Maximum)
5
Notes:
1. The maximum power dissipated in the normal clock control state must be taken into account when designing a solution for thermal
dissipation for the AMD-K6-2 processor.
2. Maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with
VCC2 = 2.2 V (for the 2.2 V component) or VCC2 = 2.4 V (for the 2.4 V component) and VCC3 = 3.3 V.
3. Typical power is determined for the typical instruction sequences or functions associated with normal system operation with
VCC2 = 2.2 V (for the 2.2 V component) or VCC2 = 2.4 V (for the 2.4 V component) and VCC3 = 3.3 V.
4. The CLK signal and the internal PLL are still running but most internal clocking has stopped.
5. The CLK signal, the internal PLL, and all internal clocking has stopped.
6. This specification applies to components using a CLK frequency of 66 MHz.
7. This specification applies to components using a CLK frequency of 95 MHz.
8. This specification applies to components using a CLK frequency of 100 MHz.
Chapter 14
Electrical Data
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14.2
Electrical Data for OPN Suffixes AGR, AFX, and 400AFR
The electrical specifications provided in this section pertain to
the following OPNs:
■ AMD-K6-2/550AGR ■ AMD-K6-2/533AFX
■ AMD-K6-2/475AFX ■ AMD-K6-2/450AFX
■ AMD-K6-2/500AFX
■ AMD-K6-2/400AFR
Note: The electrical specifications for all frequencies of the OPN
suffix AFR other than 400 MHz are provided in “Electrical
Data for OPN Suffixes AHX, 400AFQ, and AFR” on
page 253.
Operating Ranges
The AMD-K6-2 processor is designed to provide functional
operation if the voltage and temperature parameters are within
the limits defined in Table 56.
Table 56. Operating Ranges for OPN Suffixes AGR, AFX, and 400AFR
Parameter
Minimum
2.1 V
Typical
2.2 V
Maximum
2.3 V
Comments
Note 1, 2
Note 1, 3
Note 1
V
CC2
V
2.2 V
2.3 V
2.4 V
CC2
V
3.135 V
0°C
3.30 V
3.6 V
CC3
T
70°C
Note 4
CASE
T
0°C
65°C
Note 5
CASE
Notes:
1. VCC2 and VCC3 are referenced from VSS.
2. VCC2 specification for 2.2 V components.
3. VCC2 specification for 2.3 V components.
4. Case temperature range required for AMD-K6-2/550AGR and AMD-K6-2/400AFR ordering
part numbers.
5. Case temperature range required for AMD-K6-2/xxxAHX valid ordering part number
combinations, where “xxx” represents the processor core frequency.
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AMD-K6 -2 Processor Data Sheet
Absolute Ratings
The AMD-K6-2 processor is not designed to be operated beyond
the operating ranges listed in Table 56. Exposure to conditions
outside these operating ranges for extended periods of time can
affect long-term reliability. Permanent damage can occur if the
absolute ratings listed in Table 57 are exceeded.
Table 57. Absolute Ratings for OPN Suffixes AGR, AFX, and 400AFR
Parameter
Minimum
–0.5 V
Maximum
2.5 V
Comments
V
CC2
V
–0.5 V
3.6 V
CC3
V
+ 0.5 V and
≤ 4.0 V
CC3
V
–0.5 V
Note
PIN
T
(under bias)
–65°C
–65°C
+110°C
+150°C
CASE
T
STORAGE
Note:
VPIN (the voltage on any I/O pin) must not be greater than 0.5 V above the voltage being
applied to VCC3. In addition, the VPIN voltage must never exceed 4.0 V.
DC Characteristics
The DC characteristics of the AMD-K6-2 processor are shown in
Table 58.
Table 58. DC Characteristics for OPN Suffixes AGR, AFX, and 400AFR
Preliminary Data
Symbol
Parameter Description
Comments
Min
Max
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3 V
2.0 V
+0.8 V
IL
V
V
+0.3V
CC3
Note 1
IH
V
I
= 4.0-mA load
= 3.0-mA load
0.4 V
OL
OL
V
I
OH
2.4 V
OH
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.3 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC2 = 2.4 V — The maximum power supply current must be taken into account when designing a power supply.
4. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
5. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
6. Refers to inputs with an internal pullup and VIL = 0.4 V.
7. Refers to inputs with an internal pulldown and VIH = 2.4 V.
8. This specification applies to components using a CLK frequency of 66 MHz.
9. This specification applies to components using a CLK frequency of 95 MHz.
10. This specification applies to components using a CLK frequency of 100 MHz.
11. This specification applies to components using a CLK frequency of 97 MHz.
12. The specifications provided for the 533 MHz component are identical to the specifications of the 500 MHz component.
Chapter 14
Electrical Data
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Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 58. DC Characteristics for OPN Suffixes AGR, AFX, and 400AFR (continued)
Preliminary Data
Symbol
Parameter Description
Comments
Min
Max
10.00 A
11.25 A
11.90 A
400 MHz, Note 2, 8, 10
450 MHz, Note 2, 10
475 MHz, Note 2, 9
500 MHz, Note 2, 10
533 MHz, Note 2, 11, 12
550 MHz, Note 3, 10
400 MHz, Note 4, 8, 10
450 MHz, Note 4, 10
475 MHz, Note 4, 9
500 MHz, Note 4, 10
533 MHz, Note 4, 11, 12
550 MHz, Note 4, 10
Note 5
2.2 V Power Supply Current
2.3 V Power Supply Current
I
I
CC2
12.50 A
13.00 A
0.62 A
0.66 A
0.67 A
3.3 V Power Supply Current
CC3
0.69 A
I
Input Leakage Current
Output Leakage Current
±15 µA
±15 µA
–400 µA
200 µA
10 pF
LI
I
Note 5
Note 6
Note 7
LO
I
Input Leakage Current Bias with Pullup
Input Leakage Current Bias with Pulldown
Input Capacitance
IL
I
IH
C
IN
C
C
Output Capacitance
15 pF
OUT
OUT
I/O Capacitance
20 pF
C
CLK Capacitance
10 pF
CLK
C
Test Input Capacitance (TDI, TMS, TRST#)
Test Output Capacitance (TDO)
10 pF
TIN
C
15 pF
TOUT
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.3 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC2 = 2.4 V — The maximum power supply current must be taken into account when designing a power supply.
4. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
5. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
6. Refers to inputs with an internal pullup and VIL = 0.4 V.
7. Refers to inputs with an internal pulldown and VIH = 2.4 V.
8. This specification applies to components using a CLK frequency of 66 MHz.
9. This specification applies to components using a CLK frequency of 95 MHz.
10. This specification applies to components using a CLK frequency of 100 MHz.
11. This specification applies to components using a CLK frequency of 97 MHz.
12. The specifications provided for the 533 MHz component are identical to the specifications of the 500 MHz component.
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AMD-K6 -2 Processor Data Sheet
Table 58. DC Characteristics for OPN Suffixes AGR, AFX, and 400AFR (continued)
Preliminary Data
Symbol
Parameter Description
Comments
Min
Max
C
TCK Capacitance
10 pF
TCK
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.3 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC2 = 2.4 V — The maximum power supply current must be taken into account when designing a power supply.
4. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
5. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ VIN ≤ VCC3.
6. Refers to inputs with an internal pullup and VIL = 0.4 V.
7. Refers to inputs with an internal pulldown and VIH = 2.4 V.
8. This specification applies to components using a CLK frequency of 66 MHz.
9. This specification applies to components using a CLK frequency of 95 MHz.
10. This specification applies to components using a CLK frequency of 100 MHz.
11. This specification applies to components using a CLK frequency of 97 MHz.
12. The specifications provided for the 533 MHz component are identical to the specifications of the 500 MHz component.
Chapter 14
Electrical Data
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®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Power Dissipation
Table 59 contains the typical and maximum power dissipation
of the AMD-K6-2 processor during normal and reduced power
states.
Table 59. Typical and Maximum Power Dissipation for OPN Suffixes AGR, AFX, and 400AFR
400
450
475
500
533
550
Clock Control
State
Notes
6,8
8
7
8
9,10
8
MHz
MHz
MHz
MHz
MHz
MHz
Thermal Power
(Maximum)
16.90 W 18.80 W 19.80 W
10.15 W 11.30 W 11.90 W
4.40 W 4.44 W 4.45 W
4.00 W 4.00 W 4.00 W
20.75 W
12.45 W
4.46 W
4.00 W
25.00 W
15.00 W
4.87 W
4.37 W
1, 2
3
Thermal Power
(Typical)
Stop Grant / Halt
(Maximum)
4
Stop Clock
(Maximum)
5
Notes:
1. The maximum power dissipated in the normal clock control state must be taken into account when
designing a solution for thermal dissipation for the AMD-K6-2 processor.
2. Maximum power is determined for the worst-case instruction sequence or function for the listed
clock control states with VCC2 = 2.2 V (for 2.2 V components) or VCC2 = 2.3 V (for 2.3 V components)
and VCC3 = 3.3 V.
3. Typical power is determined for the typical instruction sequences or functions associated with
normal system operation with VCC2 = 2.2 V (for 2.2 V components) or VCC2 = 2.3 V (for 2.3 V
components) and VCC3 = 3.3 V.
4. The CLK signal and the internal PLL are still running but most internal clocking has stopped.
5. The CLK signal, the internal PLL, and all internal clocking has stopped.
6. This specification applies to components using a CLK frequency of 66 MHz.
7. This specification applies to components using a CLK frequency of 95 MHz.
8. This specification applies to components using a CLK frequency of 100 MHz.
9. This specification applies to components using a CLK frequency of 97 MHz.
10. The specifications provided for the 533 MHz component are identical to the specifications of the 500
MHz component.
262
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AMD-K6 -2 Processor Data Sheet
15
I/O Buffer Characteristics
All of the AMD-K6-2 processor inputs, outputs, and
bidirectional buffers are implemented using a 3.3V buffer
design. In addition, a subset of the processor I/O buffers include
a second, higher drive strength option. These buffers can be
configured to provide the higher drive strength for applications
that place a heavier load on these I/O signals.
AMD has developed two I/O buffer models that represent the
characteristics of each of the two possible drive strength
configurations supported by the AMD-K6-2 processor. These
two models are called the Standard I/O Model and the Strong
I/O Model.
AMD developed the two models to allow system designers to
perform analog simulations of AMD-K6-2 processor signals that
interface with the system logic. Analog simulations are used to
determine a signal’s time of flight from source to destination
and to ensure that the system’s signal quality requirements are
met. Signal quality measurements include overshoot,
undershoot, slope reversal, and ringing.
15.1
Selectable Drive Strength
The AMD-K6-2 processor samples the BRDYC# input during the
falling transition of RESET to configure the drive strength of
A[20:3], ADS#, HITM# and W/R#. If BRDYC# is 0 during the fall
of RESET, these particular outputs are configured using the
higher drive strength. If BRDYC# is 1 during the fall of RESET,
the standard drive strength is selected for all I/O buffers.
Table 60 shows the relationship between BRDYC# and the two
available drive strengths — K6STD and K6STG.
Table 60. A[20:3], ADS#, HITM#, and W/R# Strength Selection
Drive Strength
Strength 1 (standard)
Strength 2 (strong)
BRDYC#
I/O Buffer Name
K6STD
1
0
K6STG
Chapter 15
I/O Buffer Characteristics
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®
AMD-K6 -2 Processor Data Sheet
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15.2
I/O Buffer Model
AMD provides models of the AMD-K6-2 processor I/O buffers
for system designers to use in board-level simulations. These I/O
buffer models conform to the I/O Buffer Information
Specification (IBIS). The Standard I/O Model uses K6STD, the
standard I/O buffer representation, for all I/O buffers. The
Strong I/O Model uses K6STG, the stronger I/O buffer
representation for A[20:3], ADS#, HITM#, and W/R#, and uses
K6STD for the remainder of the I/O buffers.
Both I/O models contain voltage versus current (V/I) and
voltage versus time (V/T) data tables for accurate modeling of
I/O buffer behavior.
The following list characterizes the properties of each I/O
buffer model:
■ All data tables contain minimum, typical, and maximum
values to allow for worst-case, typical, and best-case
simulations, respectively.
■ The pullup, pulldown, power clamp, and ground clamp
device V/I tables contain enough data points to accurately
represent the nonlinear nature of the V/I curves. In addition,
the voltage ranges provided in these tables extend beyond
the normal operating range of the AMD-K6-2 processor for
those simulators that yield more accurate results based on
this wider range. Figure 93 and Figure 94 on page 265
illustrate the min/typ/max pulldown and pullup V/I curves
for K6STD between 0V and 3.3V.
■ The rising and falling ramp rates are specified.
■ The min/typ/max V
operating range is specified as
CC3
3.135V, 3.3V, and 3.6V, respectively.
■ V = 0.8V, V = 2.0V, and V = 1.5V
il
ih
meas
■ The R/L/C of the package is modeled.
■ The capacitance of the silicon die is modeled.
■ The model assumes a test load resistance of 50Ω.
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I/O Buffer Characteristics
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AMD-K6 -2 Processor Data Sheet
70
60
50
40
30
20
10
0
Voutput (V)
Figure 93. K6STD Pulldown V/I Curves
0
-10
-20
-30
-40
-50
-60
-70
Voutput (V)
Figure 94. K6STD Pullup V/I Curves
15.3
15.4
I/O Model Application Note
For the AMD-K6-2 processor I/O Buffer IBIS Models and their
application, refer to the AMD-K6 Processor I/O Model (IBIS)
Application Note, order# 21084.
®
I/O Buffer AC and DC Characteristics
See “Signal Switching Characteristics” on page 267 for the
AMD-K6-2 processor AC timing specifications.
See “Electrical Data” on page 253 for the AMD-K6-2 processor
DC specifications.
Chapter 15
I/O Buffer Characteristics
265
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
266
I/O Buffer Characteristics
Chapter 15
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
16
Signal Switching Characteristics
The AMD-K6-2 processor signal switching characteristics are
presented in Table 61 through Table 70. Valid delay, float,
setup, and hold timing specifications are listed. These
specifications are provided for the system designer to
determine if the timings necessary for the processor to
interface with the system logic are met. Table 61 and Table 62
contain the switching characteristics of the CLK input. Table 63
through Table 66 contain the timings for the normal operation
signals. Table 67 and Table 68 contain the timings for RESET
and the configuration signals. Table 69 and Table 70 contain the
timings for the test operation signals.
All signal timings provided are:
■ Measured between CLK, TCK, or RESET at 1.5 V and the
corresponding signal at 1.5 V—this applies to input and
output signals that are switching from Low to High, or from
High to Low
■ Based on input signals applied at a slew rate of 1 V/ns
between 0 V and 3 V (rising) and 3 V to 0 V (falling)
■ Valid within the operating ranges given in “Operating
Ranges” on page 253
■ Based on a load capacitance (C ) of 0 pF
L
16.1
CLK Switching Characteristics
Table 61 and Table 62 contain the switching characteristics of
the CLK input to the AMD-K6-2 processor for 100-MHz and
66-MHz bus operation, respectively, as measured at the voltage
levels indicated by Figure 95 on page 269.
The CLK Period Stability specifies the variance (jitter) allowed
between successive periods of the CLK input measured at 1.5 V.
This parameter must be considered as one of the elements of
clock skew between the AMD-K6-2 processor and the system
logic.
Chapter 16
Signal Switching Characteristics
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Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
16.2
Clock Switching Characteristics for 100-MHz Bus Operation
Table 61. CLK Switching Characteristics for 100-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
Frequency
33.3 MHz
10.0 ns
100 MHz
In Normal Mode
In Normal Mode
t
CLK Period
95
95
95
95
95
1
t
CLK High Time
CLK Low Time
CLK Fall Time
CLK Rise Time
CLK Period Stability
3.0 ns
3.0 ns
0.15 ns
0.15 ns
2
t
3
t
1.5 ns
1.5 ns
4
t
5
± 250 ps
Note
Note:
Jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz.
16.3
Clock Switching Characteristics for 66-MHz Bus Operation
Table 62. CLK Switching Characteristics for 66-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
Frequency
33.3 MHz
15.0 ns
66.6 MHz
30.0 ns
In Normal Mode
In Normal Mode
t
CLK Period
95
95
95
95
95
1
t
CLK High Time
CLK Low Time
CLK Fall Time
CLK Rise Time
CLK Period Stability
4.0 ns
4.0 ns
0.15 ns
0.15 ns
2
t
3
t
1.5 ns
1.5 ns
4
t
5
± 250 ps
Note
Note:
Jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz.
268
Signal Switching Characteristics
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AMD-K6 -2 Processor Data Sheet
t2
2.0 V
1.5 V
t3
0.8 V
t4
t5
t1
Figure 95. CLK Waveform
16.4
Valid Delay, Float, Setup, and Hold Timings
Valid delay and float timings are given for output signals during
functional operation and are given relative to the rising edge of
CLK. During boundary-scan testing, valid delay and float
timings for output signals are with respect to the falling edge of
TCK. The maximum valid delay timings are provided to allow a
system designer to determine if setup times to the system logic
can be met. Likewise, the minimum valid delay timings are used
to analyze hold times to the system logic.
The setup and hold time requirements for the AMD-K6-2
processor input signals must be met by the system logic to
assure the proper operation of the AMD-K6-2 processor. The
setup and hold timings during functional and boundary-scan
test mode are given relative to the rising edge of CLK and TCK,
respectively.
Chapter 16
Signal Switching Characteristics
269
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
16.5
Output Delay Timings for 100-MHz Bus Operation
Table 63. Output Delay Timings for 100-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
t
A[31:3] Valid Delay
1.1 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
5.5 ns
7.0 ns
4.5 ns
4.0 ns
7.0 ns
4.0 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.5 ns
7.0 ns
4.5 ns
7.0 ns
4.5 ns
4.0 ns
4.0 ns
4.0 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
97
98
97
98
97
98
97
98
97
97
98
97
97
98
97
98
97
98
97
98
97
97
97
97
97
98
97
98
6
t
A[31:3] Float Delay
ADS# Valid Delay
7
t
1.0 ns
1.0 ns
1.0 ns
8
t
ADS# Float Delay
9
t
ADSC# Valid Delay
ADSC# Float Delay
AP Valid Delay
10
t
11
t
12
t
AP Float Delay
13
t
APCHK# Valid Delay
BE[7:0]# Valid Delay
BE[7:0]# Float Delay
BREQ Valid Delay
1.0 ns
1.0 ns
14
t
15
t
16
t
1.0 ns
1.0 ns
17
t
CACHE# Valid Delay
CACHE# Float Delay
D/C# Valid Delay
18
t
19
t
1.0 ns
1.3 ns
1.3 ns
20
t
D/C# Float Delay
21
t
D[63:0] Write Data Valid Delay
D[63:0] Write Data Float Delay
DP[7:0] Write Data Valid Delay
DP[7:0] Write Data Float Delay
FERR# Valid Delay
HIT# Valid Delay
22
t
23
t
24
t
25
t
1.0 ns
1.0 ns
1.1 ns
1.0 ns
1.1 ns
26
t
27
t
HITM# Valid Delay
HLDA Valid Delay
28
t
29
t
LOCK# Valid Delay
LOCK# Float Delay
M/IO# Valid Delay
M/IO# Float Delay
30
t
31
t
1.0 ns
32
t
33
270
Signal Switching Characteristics
Chapter 16
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 63. Output Delay Timings for 100-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
t
PCD Valid Delay
1.0 ns
4.0 ns
7.0 ns
4.5 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.0 ns
4.0 ns
7.0 ns
97
98
97
97
98
97
98
97
97
98
34
t
PCD Float Delay
PCHK# Valid Delay
PWT Valid Delay
PWT Float Delay
SCYC Valid Delay
SCYC Float Delay
SMIACT# Valid Delay
W/R# Valid Delay
W/R# Float Delay
35
t
1.0 ns
1.0 ns
36
t
37
t
38
t
1.0 ns
39
t
40
t
1.0 ns
1.0 ns
41
t
42
t
43
Chapter 16
Signal Switching Characteristics
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Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
16.6
Input Setup and Hold Timings for 100-MHz Bus Operation
Table 64. Input Setup and Hold Timings for 100-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
t
A[31:5] Setup Time
3.0 ns
1.0 ns
3.0 ns
1.0 ns
3.5 ns
1.0 ns
1.7 ns
1.0 ns
3.5 ns
1.0 ns
3.0 ns
1.0 ns
3.0 ns
1.0 ns
1.7 ns
1.5 ns
1.7 ns
1.5 ns
3.0 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
44
t
A[31:5] Hold Time
45
t
A20M# Setup Time
A20M# Hold Time
Note 1
Note 1
46
t
47
t
AHOLD Setup Time
AHOLD Hold Time
48
t
49
t
AP Setup Time
50
t
AP Hold Time
51
t
BOFF# Setup Time
BOFF# Hold Time
52
t
53
t
BRDY# Setup Time
BRDY# Hold Time
54
t
55
t
BRDYC# Setup Time
BRDYC# Hold Time
D[63:0] Read Data Setup Time
D[63:0] Read Data Hold Time
DP[7:0] Read Data Setup Time
DP[7:0] Read Data Hold Time
EADS# Setup Time
EADS# Hold Time
56
t
57
t
58
t
59
t
60
t
61
t
62
t
63
t
EWBE# Setup Time
EWBE# Hold Time
64
t
65
t
FLUSH# Setup Time
FLUSH# Hold Time
Note 2
Note 2
66
t
67
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
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Signal Switching Characteristics
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®
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AMD-K6 -2 Processor Data Sheet
Table 64. Input Setup and Hold Timings for 100-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
t
HOLD Setup Time
1.7 ns
1.5 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
3.0 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
68
t
HOLD Hold Time
IGNNE# Setup Time
IGNNE# Hold Time
INIT Setup Time
INIT Hold Time
69
t
Note 1
Note 1
Note 2
Note 2
Note 1
Note 1
70
t
71
t
72
t
73
t
INTR Setup Time
INTR Hold Time
74
t
75
t
INV Setup Time
76
t
INV Hold Time
77
t
KEN# Setup Time
KEN# Hold Time
NA# Setup Time
NA# Hold Time
78
t
79
t
80
t
81
t
NMI Setup Time
NMI Hold Time
Note 2
Note 2
Note 2
Note 2
Note 1
Note 1
82
t
83
t
SMI# Setup Time
SMI# Hold Time
STPCLK# Setup Time
STPCLK# Hold Time
WB/WT# Setup Time
WB/WT# Hold Time
84
t
85
t
86
t
87
t
88
t
89
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
Chapter 16
Signal Switching Characteristics
273
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
16.7
Output Delay Timings for 66-MHz Bus Operation
Table 65. Output Delay Timings for 66-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
6.3 ns
10.0 ns
6.0 ns
10.0 ns
7.0 ns
t
A[31:3] Valid Delay
1.1 ns
97
98
97
98
97
98
97
98
97
97
98
97
97
98
97
98
97
98
97
98
97
97
97
97
97
98
97
98
6
t
A[31:3] Float Delay
ADS# Valid Delay
7
t
1.0 ns
1.0 ns
1.0 ns
8
t
ADS# Float Delay
9
t
ADSC# Valid Delay
ADSC# Float Delay
AP Valid Delay
10
t
10.0 ns
8.5 ns
10.0 ns
8.3 ns
7.0 ns
11
t
12
t
AP Float Delay
13
t
APCHK# Valid Delay
BE[7:0]# Valid Delay
BE[7:0]# Float Delay
BREQ Valid Delay
1.0 ns
1.0 ns
14
t
15
t
10.0 ns
8.0 ns
7.0 ns
16
t
1.0 ns
1.0 ns
17
t
CACHE# Valid Delay
CACHE# Float Delay
D/C# Valid Delay
18
t
10.0 ns
7.0 ns
19
t
1.0 ns
1.3 ns
1.3 ns
20
t
D/C# Float Delay
10.0 ns
7.5 ns
21
t
D[63:0] Write Data Valid Delay
D[63:0] Write Data Float Delay
DP[7:0] Write Data Valid Delay
DP[7:0] Write Data Float Delay
FERR# Valid Delay
HIT# Valid Delay
22
t
10.0 ns
7.5 ns
23
t
24
t
10.0 ns
8.3 ns
6.8 ns
6.0 ns
6.8 ns
7.0 ns
25
t
1.0 ns
1.0 ns
1.1 ns
1.0 ns
1.1 ns
26
t
27
t
HITM# Valid Delay
HLDA Valid Delay
28
t
29
t
LOCK# Valid Delay
LOCK# Float Delay
M/IO# Valid Delay
M/IO# Float Delay
30
t
10.0 ns
5.9 ns
10.0 ns
31
t
1.0 ns
32
t
33
274
Signal Switching Characteristics
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 65. Output Delay Timings for 66-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
7.0 ns
10.0 ns
7.0 ns
7.0 ns
10.0 ns
7.0 ns
10.0 ns
7.3 ns
7.0 ns
10.0 ns
t
PCD Valid Delay
1.0 ns
97
98
97
97
98
97
98
97
97
98
34
t
PCD Float Delay
PCHK# Valid Delay
PWT Valid Delay
PWT Float Delay
SCYC Valid Delay
SCYC Float Delay
SMIACT# Valid Delay
W/R# Valid Delay
W/R# Float Delay
35
t
1.0 ns
1.0 ns
36
t
37
t
38
t
1.0 ns
39
t
40
t
1.0 ns
1.0 ns
41
t
42
t
43
Chapter 16
Signal Switching Characteristics
275
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
16.8
Input Setup and Hold Timings for 66-MHz Bus Operation
Table 66. Input Setup and Hold Timings for 66-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
t
A[31:5] Setup Time
6.0 ns
1.0 ns
5.0 ns
1.0 ns
5.5 ns
1.0 ns
5.0 ns
1.0 ns
5.5 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
2.8 ns
1.5 ns
2.8 ns
1.5 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
44
t
A[31:5] Hold Time
45
t
A20M# Setup Time
A20M# Hold Time
Note 1
Note 1
46
t
47
t
AHOLD Setup Time
AHOLD Hold Time
48
t
49
t
AP Setup Time
50
t
AP Hold Time
51
t
BOFF# Setup Time
BOFF# Hold Time
52
t
53
t
BRDY# Setup Time
BRDY# Hold Time
54
t
55
t
BRDYC# Setup Time
BRDYC# Hold Time
D[63:0] Read Data Setup Time
D[63:0] Read Data Hold Time
DP[7:0] Read Data Setup Time
DP[7:0] Read Data Hold Time
EADS# Setup Time
EADS# Hold Time
56
t
57
t
58
t
59
t
60
t
61
t
62
t
63
t
EWBE# Setup Time
EWBE# Hold Time
64
t
65
t
FLUSH# Setup Time
FLUSH# Hold Time
Note 2
Note 2
66
t
67
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
276
Signal Switching Characteristics
Chapter 16
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 66. Input Setup and Hold Timings for 66-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
t
HOLD Setup Time
5.0 ns
1.5 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
4.5 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
4.5 ns
1.0 ns
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
99
68
t
HOLD Hold Time
IGNNE# Setup Time
IGNNE# Hold Time
INIT Setup Time
INIT Hold Time
69
t
Note 1
Note 1
Note 2
Note 2
Note 1
Note 1
70
t
71
t
72
t
73
t
INTR Setup Time
INTR Hold Time
74
t
75
t
INV Setup Time
76
t
INV Hold Time
77
t
KEN# Setup Time
KEN# Hold Time
NA# Setup Time
NA# Hold Time
78
t
79
t
80
t
81
t
NMI Setup Time
NMI Hold Time
Note 2
Note 2
Note 2
Note 2
Note 1
Note 1
82
t
83
t
SMI# Setup Time
SMI# Hold Time
STPCLK# Setup Time
STPCLK# Hold Time
WB/WT# Setup Time
WB/WT# Hold Time
84
t
85
t
86
t
87
t
88
t
89
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
Chapter 16
Signal Switching Characteristics
277
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
16.9
RESET and Test Signal Timing
Table 67. RESET and Configuration Signals for 100-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
1.7 ns
Max
t
RESET Setup Time
100
100
100
100
100
100
100
100
100
100
100
100
100
90
t
RESET Hold Time
1.0 ns
91
t
RESET Pulse Width, V and CLK Stable
15 clocks
1.0 ms
1.0 ms
2 clocks
1.0 ns
92
CC
t
RESET Active After V and CLK Stable
93
CC
t
BF[2:0] Setup Time
BF[2:0] Hold Time
BRDYC# Hold Time
BRDYC# Setup Time
BRDYC# Hold Time
FLUSH# Setup Time
FLUSH# Hold Time
FLUSH# Setup Time
FLUSH# Hold Time
Note 3
Note 3
Note 4
Note 2
Note 2
Note 1
Note 1
Note 2
Note 2
94
t
95
t
96
t
2 clocks
2 clocks
1.7 ns
97
t
98
t
99
t
1.0 ns
100
t
2 clocks
2 clocks
101
t
102
Notes:
1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET
is sampled negated.
2. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
3. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
4. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET.
278
Signal Switching Characteristics
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Table 68. RESET and Configuration Signals for 66-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
5.0 ns
Max
t
RESET Setup Time
100
100
100
100
100
100
100
100
100
100
100
100
100
90
t
RESET Hold Time
1.0 ns
91
t
RESET Pulse Width, V and CLK Stable
15 clocks
1.0 ms
1.0 ms
2 clocks
1.0 ns
92
CC
t
RESET Active After V and CLK Stable
93
CC
t
BF[2:0] Setup Time
BF[2:0] Hold Time
BRDYC# Hold Time
BRDYC# Setup Time
BRDYC# Hold Time
FLUSH# Setup Time
FLUSH# Hold Time
FLUSH# Setup Time
FLUSH# Hold Time
Note 3
Note 3
Note 4
Note 2
Note 2
Note 1
Note 1
Note 2
Note 2
94
t
95
t
96
t
2 clocks
2 clocks
5.0 ns
97
t
98
t
99
t
1.0 ns
100
t
2 clocks
2 clocks
101
t
102
Notes:
1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET
is sampled negated.
2. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
3. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
4. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET.
Chapter 16
Signal Switching Characteristics
279
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Table 69. TCK Waveform and TRST# Timing at 25 MHz
Preliminary Data
Symbol
Parameter Description
TCK Frequency
Figure
Comments
Min
Max
25 MHz
101
101
101
101
101
101
102
t
TCK Period
40.0 ns
14.0 ns
14.0 ns
103
t
TCK High Time
TCK Low Time
TCK Fall Time
TCK Rise Time
TRST# Pulse Width
104
t
105
t
5.0 ns
5.0 ns
Note 1, 2
Note 1, 2
106
t
107
t
30.0 ns
Asynchronous
108
Notes:
1. Rise/Fall times can be increased by 1.0 ns for each 10 MHz that TCK is run below its maximum frequency of 25 MHz.
2. Rise/Fall times are measured between 0.8 V and 2.0 V.
Table 70. Test Signal Timing at 25 MHz
Preliminary Data
Symbol
Parameter Description
Figure
Notes
Min
Max
t
TDI Setup Time
5.0 ns
9.0 ns
5.0 ns
9.0 ns
3.0 ns
103
103
103
103
103
103
103
103
103
103
Note 2
Note 2
Note 2
Note 2
Note 1
Note 1
Note 1
Note 1
Note 2
Note 2
109
t
TDI Hold Time
110
t
TMS Setup Time
111
t
TMS Hold Time
112
t
TDO Valid Delay
13.0 ns
16.0 ns
13.0 ns
16.0 ns
113
t
TDO Float Delay
114
t
All Outputs (Non-Test) Valid Delay
All Outputs (Non-Test) Float Delay
All Inputs (Non-Test) Setup Time
All Inputs (Non-Test) Hold Time
3.0 ns
115
t
116
t
5.0 ns
9.0 ns
117
t
118
Notes:
1. Parameter is measured from the TCK falling edge.
2. Parameter is measured from the TCK rising edge.
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
WAVEFORM
INPUTS
OUTPUTS
Steady
Must be steady
Can change from
High to Low
Changing from High to Low
Changing from Low to High
Changing, State Unknown
Can change
from Low to High
Don’t care, any
change permitted
(Does not apply)
Center line is high
impedance state
Figure 96. Diagrams Key
Tx
Tx
1.5 V
CLK
Max
tv
Min
Output Signal
Valid n
Valid n +1
v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42
Figure 97. Output Valid Delay Timing
Chapter 16
Signal Switching Characteristics
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Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Tx
Tx
Tx
Tx
1.5 V
CLK
tf
Output Signal
Valid
tv
Min
v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42
f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43
Figure 98. Maximum Float Delay Timing
Tx
Tx
Tx
Tx
1.5 V
CLK
ts
th
Input Signal
s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88
h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89
Figure 99. Input Setup and Hold Timing
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Signal Switching Characteristics
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Tx
Tx
1.5 V
CLK
• • •
• • •
t90
t91
RESET
1.5 V
1.5 V
t92, 93
t99
t100
FLUSH#
(Synchronous)
• • •
FLUSH#, BRDYC#
(Asynchronous)
• • •
t97, 101
t98, 102
BF[2:0]
(Asynchronous)
• • •
t94
t95
Figure 100. Reset and Configuration Timing
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Signal Switching Characteristics
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Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
t104
2.0 V
1.5 V
t105
0.8 V
t106
t107
t103
Figure 101. TCK Waveform
t108
1.5 V
Figure 102. TRST# Timing
t103
1.5 V
TCK
TDI, TMS
TDO
t109, 111 t110, 112
t114
t113
t116
t115
Output
Signals
Input
Signals
t117
t118
Figure 103. Test Signal Timing Diagram
284 Signal Switching Characteristics
Chapter 16
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
17
Thermal Design
17.1
Package Thermal Specifications
The AMD-K6-2 processor operating specification calls for the
case temperature (T ) to be in the range of 0°C to 70°C, 0°C to
C
65°C, or 0°C to 60°C. The ambient temperature (T ) is not
A
specified as long as the case temperature is not violated. The
case temperature must be measured on the top center of the
package. Table 71 and Table 72 show the AMD-K6-2 processor
thermal specifications for all valid OPN suffixes.
Table 71. Package Thermal Specification for OPN Suffixes AHX, AFQ, and AFR
Maximum Thermal Power
θ
JC
2.2 V Component
2.4 V Component
Junction-Case
266 MHz 300 MHz 333 MHz 350 MHz 366 MHz 380 MHz 400 MHz* 450 MHz 475 MHz
1.0 °C/W
14.70 W 17.20 W 19.00 W 19.95 W 20.80 W 21.60 W 22.70 W 28.40 W 29.60 W
3.90 W 3.92 W 3.94 W 3.96 W 3.96 W 3.97 W 3.98 W 6.50 W 6.51 W
3.50 W 3.50 W 3.50 W 3.50 W 3.50 W 3.50 W 3.50 W 6.00 W 6.00 W
Stop Grant Mode
Stop Clock Mode
T Case Temperature
0°C–70°C
0°C–60°C
0°C–65°C
C
Note:
* Not applicable to OPN AMD-K6-2/400AFR. Refer to Table 72 on page 287 for the AMD-K6-2/400AFR specifications.
Chapter 17
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Table 72. Package Thermal Specification for OPN Suffixes AGR, AFX, and 400AFR
Maximum Thermal Power
θ
JC
2.2 V Component
2.3 V Component
Junction-Case
1
2
450 MHz 475 MHz 500 MHz
400 MHz
533 MHz
550 MHz
1.0 °C/W
16.90 W 18.80 W 19.80 W
20.75 W
25.00 W
4.40 W
4.00 W
4.44 W
4.00 W
4.45 W
4.00 W
4.46 W
4.00 W
4.87 W
4.37 W
Stop Grant Mode
Stop Clock Mode
T Case Temperature
0°C–70°C
0°C–65°C
0°C–70°C
C
Notes:
1. Specifications are applicable to OPN AMD-K6-2/400AFR.
2. The specifications provided for the 533 MHz component are identical to the specifications of the 500 MHz
component.
Figure 104 on page 288 shows the thermal model of a processor
with a passive thermal solution. The case-to-ambient
temperature (T ) can be calculated from the following
CA
equation:
T
= P
= P
• θ
CA
CA
MAX
MAX
• ( θ
+ θ
)
SA
IF
Where:
P
= Maximum Power Consumption
MAX
CA
θ
θ
θ
= Case-to-Ambient Thermal Resistance
= Interface Material Thermal Resistance
= Sink-to-Ambient Thermal Resistance
IF
SA
Chapter 17
Thermal Design
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21850J/0—February 2000
Thermal
Resistance
(°C/W)
Temperature
(Ambient)
TCA
θSA
θCA
Sink
Case
θIF
Figure 104. Thermal Model
Figure 105 illustrates the case-to-ambient temperature (T ) in
CA
relation to the power consumption (X-axis) and the thermal
resistance (Y-axis). If the power consumption and case
temperature are known, the thermal resistance (θ
)
CA
requirement can be calculated for a given ambient temperature
(T ) value.
A
3.0
2.5
2.0
1.5
1.0
0.5
0.0
T = T - T
A
CA
C
30 deg C
25 deg C
20 deg C
15 deg C
10 W
12 W 14 W
16 W
18 W 20 W
22 W 24 W
26 W
28 W 30 W
32 W
Power Consumption (Watts)
Figure 105. Power Consumption versus Thermal Resistance
288
Thermal Design
Chapter 17
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
The thermal resistance of a heatsink is determined by the heat
dissipation surface area, the material and shape of the
heatsink, and the airflow volume across the heatsink. In
general, the larger the surface area the lower the thermal
resistance.
The required thermal resistance of a heatsink (θSA) can be
calculated using the following example:
If:
T
T
P
= 65°C
= 45°C
C
A
= 29.60W at 475MHz
MAX
Then:
T – T
C
A
20°C
(°C⁄ W)
≤ ------------------ = --------------------- = 0.676
θ
CA
29.60W
P
MAX
Chapter 17
Thermal Design
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Preliminary Information
®
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21850J/0—February 2000
Thermal grease is recommended as interface material because
it provides the lowest thermal resistance ( 0.20°C/W). The
required thermal resistance (θ ) of the heatsink in this
SA
example is calculated as follows:
θSA = θCA – θIF = 0.676 – 0.20 = 0.476(°C/W)
Heat Dissipation Path
Figure 106 illustrates the heat dissipation path of the processor.
Due to the lower thermal resistance between the processor die
junction and case, most of the heat generated by the processor
is transferred from the top surface of the case. The small
amount of heat generated from the bottom side of the processor
where the processor socket blocks the convection can be safely
ignored.
Ambient Temperature
Thin Lid
Case temperature
Figure 106. Processor Heat Dissipation Path
Measuring Case
Temperature
The processor case temperature is measured to ensure that the
thermal solution meets the processor’s operational
specification. This temperature should be measured on the top
center of the package, where most of the heat is dissipated.
Figure 107 shows the correct location for measuring the case
temperature. If a heatsink is installed while measuring, the
thermocouple must be installed into the heatsink via a small
hole drilled through the heatsink base (for example, 1/16 of an
inch). The thermocouple is then attached to the base of the
heatsink and the small hole filled using thermal epoxy, allowing
the tip of the thermocouple to touch the top of the processor
case.
290
Thermal Design
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AMD-K6 -2 Processor Data Sheet
Thermally Conductive Epoxy
Thermocouple
Figure 107. Measuring Case Temperature
17.2
Layout and Airflow Considerations
Voltage Regulator
A voltage regulator is required to support the lower voltage
(3.3 V and lower) to the processor. In most applications, the
voltage regulator is designed with power transistors. As a
result, additional heatsinks are required to dissipate the heat
from the power transistors. Figure 108 shows the voltage
regulator placed parallel to the processor with the airflow
aligned with the devices. With this alignment, the heat
generated by the voltage regulator has minimal effect on the
processor.
Voltage Regulator
Airflow
Processor
Figure 108. Voltage Regulator Placement
Chapter 17
Thermal Design
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Preliminary Information
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A heatsink and fan combination can deliver much better
thermal performance than a heatsink alone. More importantly,
with a fan/sink the airflow requirements in a system design are
not as critical. A unidirectional heatsink with a fan moves air
from the top of the heatsink to the side. In this case, the best
location for the voltage regulator is on the side of the processor
in the path of the airflow exiting the fan sink (see Figure 109).
This location guarantees that the heatsinks on both the
processor and the regulator receive adequate air circulation.
Airflow
Ideal areas for voltage regulator
Figure 109. Airflow for a Heatsink with Fan
Airflow Management
in a System Design
Complete airflow management in a system is important. In
addition to the volume of air, the path of the air is also
important. Figure 110 shows the airflow in a dual-fan system.
The fan in the front end pulls cool air into the system through
intake slots in the chassis. The power supply fan forces the hot
air out of the chassis. The thermal performance of the heatsink
can be maximized if it is located in the shaded area, where it
receives greatest benefit from this air exchange system.
292
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Fan
P/S
Main Board
V
e
n
t
Drive Bays
s
Fan
Vents
Front
Figure 110. Airflow Path in a Dual-Fan System
Figure 111 shows the airflow management in a system using the
ATX form-factor. The orientation of the power supply fan and
the motherboard are modified in the ATX platform design. The
power supply fan pulls cool air through the chassis and across
the processor. The processor is located near the power supply
fan, where it can receive adequate airflow without an auxiliary
fan. The arrangement significantly improves the airflow across
the processor with minimum installation cost.
Main Board
F
P/S
a
n
Drive Bays
Figure 111. Airflow Path in an ATX Form-Factor System
Chapter 17
Thermal Design
293
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
For more information about thermal design considerations, see
®
the AMD-K6 Processor Thermal Solution Design Application
Note, order# 21085.
294
Thermal Design
Chapter 17
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21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
18
Pin Description Diagram
®
Figure 112. AMD-K6 -2 Processor Top-Side View
Chapter 18 Pin Description Diagram
295
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
®
Figure 113. AMD-K6 -2 Processor Pin-Side View
296
Pin Description Diagram
Chapter 18
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
19
Pin Designations
®
AMD-K6 -2 Processor Functional Grouping
Address
Data
Control
Test
NC
Vcc2
Vcc3
Vss
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
No.
Pin
No.
Pin
No.
Pin
No.
A3
AL-35
D0
K-34
A20M#
ADS#
ADSC#
AHOLD
APCHK#
BE0#
AK-08
TCK
M-34
A-37
A-07
A-19
A-03
AM-20
A4
AM-34
AK-32
AN-33
AL-33
AM-32
AK-30
AN-31
AL-31
AL-29
AK-28
AL-27
AK-26
AL-25
AK-24
AL-23
AK-22
AL-21
AF-34
AH-36
AE-33
AG-35
AJ-35
D1
G-35
J-35
AJ-05
AM-02
V-04
TDI
N-35
N-33
P-34
Q-33
E-17
A-09
A-21
B-06
AM-22
AM-24
AM-26
AM-28
AM-30
AN-37
A5
D2
TDO
TMS
TRST#
E-25
A-11
A-23
B-08
A6
D3
G-33
F-36
F-34
E-35
E-33
D-34
C-37
C-35
B-36
D-32
B-34
C-33
A-35
B-32
C-31
A-33
D-28
B-30
C-29
A-31
D-26
C-27
C-23
D-24
C-21
D-22
C-19
D-20
C-17
C-15
D-16
C-13
D-14
C-11
D-12
C-09
D-10
D-08
A-05
E-09
B-04
D-06
C-05
E-07
C-03
D-04
E-05
D-02
F-04
E-03
G-05
E-01
G-03
H-04
J-03
R-34
A-13
A-25
B-10
A7
D4
AE-05
AL-09
AK-10
AL-11
AK-12
AL-13
AK-14
AL-15
AK-16
Y-33
S-33
A-15
A-27
B-12
A8
D5
S-35
A-17
A-29
B-14
A9
D6
BE1#
W-33
AJ-15
AJ-23
AL-19
AN-35
B-02
E-21
B-16
Parity
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
D7
BE2#
E-15
E-27
B-18
D8
BE3#
G-01
J-01
E-37
B-20
D9
BE4#
G-37
J-37
B-22
AP
AK-02
D-36
D-30
C-25
D-18
C-07
F-06
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
BE5#
L-01
B-24
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
BE6#
N-01
Q-01
S-01
L-33
B-26
BE7#
L-37
B-28
INC
BF0
N-37
Q-37
S-37
E-11
BF1
X-34
U-01
W-01
Y-01
E-13
BF2
W-35
Z-04
E-19
C-01
BOFF#
BRDY#
BRDYC#
BREQ
T-34
E-23
F-02
N-05
H-34
Y-35
X-04
AA-01
AC-01
AE-01
AG-01
AJ-11
AN-09
AN-11
AN-13
AN-15
AN-17
AN-19
U-33
U-37
W-37
Y-37
E-29
Y-03
E-31
Z-34
AJ-01
U-03
H-02
H-36
K-02
AC-35
AL-07
AN-01
AN-03
CACHE#
CLK
D/C#
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IGNNE#
INIT
INTR
INV
AK-18
AK-04
AM-04
W-03
Q-05
AA-37
AC-37
AE-37
AG-37
AJ-19
AJ-29
AN-21
AN-23
AN-25
AN-27
AN-29
K-36
AH-34
AG-33
AK-36
AK-34
AM-36
AJ-33
M-02
M-36
P-02
RSVD
AN-07
AK-06
AL-05
AJ-03
AB-04
AA-35
AA-33
AD-34
U-05
P-36
R-02
R-36
J-33
T-02
L-35
T-36
P-04
U-35
V-02
Q-03
Q-35
R-04
V-36
X-02
S-03
S-05
KEN#
LOCK#
M/IO#
NA#
W-05
AH-04
T-04
X-36
Z-02
AA-03
AC-03
AC-05
AD-04
AE-03
AE-35
Z-36
Y-05
AB-02
AB-36
AD-02
AD-36
AF-02
AF-36
AH-02
AJ-07
AJ-09
AJ-13
AJ-17
AJ-21
AJ-25
AJ-27
AJ-31
AJ-37
AL-37
AM-08
AM-10
AM-12
AM-14
AM-16
AM-18
NMI
PCD
AC-33
AG-05
AF-04
AL-03
AK-20
AL-17
AB-34
AG-03
V-34
PCHK#
PWT
RESET
SCYC
KEY
SMI#
SMIACT#
STPCLK#
VCC2DET
VCC2H/L#
W/R#
WB/WT#
AH-32
AL-01
AN-05
AM-06
AA-05
J-05
K-04
L-05
L-03
M-04
N-03
Chapter 19
Pin Designations
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Preliminary Information
®
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298
Pin Designations
Chapter 19
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
20
Package Specifications
20.1
321-Pin Staggered CPGA Package Specification
Table 73. 321-Pin Staggered CPGA Package Specification
Millimeters
Symbol
Inches
Min
49.28
45.59
31.01
44.90
2.91
1.30
3.05
0.43
2.29
1.14
Max
49.78
45.85
32.89
45.10
3.63
1.52
Notes
Min
1.940
1.795
1.221
1.768
0.115
0.051
0.120
0.017
0.090
0.045
0.060
0.060
—
Max
1.960
1.805
1.295
1.776
0.143
0.060
0.130
0.020
0.110
0.055
0.090
0.100
0.005
Notes
A
B
C
D
E
F
G
H
M
N
d
e
3.30
0.51
2.79
1.40
1.52
1.52
—
2.29
2.54
0.13
f
Flatness
Flatness
Chapter 20
Package Specifications
299
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
Figure 114. 321-Pin Staggered CPGA Package Specification
300
Package Specifications
Chapter 20
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
21
Ordering Information
Standard AMD-K6®-2 Processor Model 8 Products
AMD standard products are available in several operating ranges. The ordering part
number (OPN) is formed by a combination of the elements below.
AMD-K6-2/550
A G R
Case Temperature
Q = 0°C–60°C
R = 0°C–70°C
X = 0°C–65°C
Operating Voltage
F = 2.1 V–2.3 V (Core) / 3.135 V–3.6 V (I/O)
G = 2.2 V–2.4 V (Core) / 3.135 V–3.6 V (I/O)
H = 2.3 V–2.5 V (Core) / 3.135 V–3.6 V (I/O)
Package Type
A = 321-pin CPGA
Performance Rating
/550
/475
/380
/300
/533
/450
/350
/266
/500
/400
/333
Family/Core
AMD-K6-2
Table 74. Valid Ordering Part Number Combinations
OPN
Package Type
Operating Voltage
2.2V–2.4V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
Case Temperature
AMD-K6-2/550AGR
321-pin CPGA
0°C–70°C
0°C–65°C
0°C–65°C
AMD-K6-2/533AFX
AMD-K6-2/500AFX
321-pin CPGA
321-pin CPGA
Note:
This table lists configurations planned to be supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific valid combinations and to check on newly-released
combinations.
Chapter 21
Ordering Information
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®
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21850J/0—February 2000
Table 74. Valid Ordering Part Number Combinations (continued)
OPN
Package Type
Operating Voltage
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.3V–2.5V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.3V–2.5V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
2.1V–2.3V (Core)
3.135V–3.6V (I/O)
Case Temperature
AMD-K6-2/475AFX
321-pin CPGA
0°C–65°C
0°C–65°C
0°C–65°C
0°C–65°C
0°C–70°C
0°C–60°C
0°C–70°C
0°C–70°C
0°C–70°C
0°C–70°C
0°C–70°C
0°C–70°C
AMD-K6-2/475AHX
AMD-K6-2/450AFX
AMD-K6-2/450AHX
AMD-K6-2/400AFR
AMD-K6-2/400AFQ
AMD-K6-2/380AFR
AMD-K6-2/366AFR
AMD-K6-2/350AFR
AMD-K6-2/333AFR
AMD-K6-2/300AFR
AMD-K6-2/266AFR
321-pin CPGA
321-pin CPGA
321-pin CPGA
321-pin CPGA
321-pin CPGA
321-pin CPGA
321-pin CPGA
321-pin CPGA
321-pin CPGA
321-pin CPGA
321-pin CPGA
Note:
This table lists configurations planned to be supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific valid combinations and to check on newly-released
combinations.
302
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®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Index
BIST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Bits, Predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 180
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BOFF# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93, 156
locked operation with . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Boundary Scan
register (BSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
test access port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
BR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Branch
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
history table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2, 9, 19
prediction logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–18
target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
BRDY#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 173, 263
BREQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
BSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Buffer Characteristics, I/O . . . . . . . . . . . . . . . . . . . . . . . . . 263
Buffer Model, I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Burst
reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
reads, pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Numerics
100-MHz Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3
clock switching characteristics . . . . . . . . . . . . . . . . . . . . 268
input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 272
output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
321-Pin Staggered CPGA Package . . . . . . . . . . . . . . . . . . . . . 1
specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
3DNow! Technology . . . . . .1–3, 7, 9–10, 13–17, 21, 54, 116,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173, 177, 192
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17
instruction compatibility, floating-point and. . . . . . . . . 209
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81, 210
register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
66-MHz Bus
clock switching characteristics . . . . . . . . . . . . . . . . . . . . 268
input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 276
output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
A
A[20:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263–264
A[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
A20M# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85, 212
A20M# Masking of Cache Accesses . . . . . . . . . . . . . . . . . . 199
Absolute Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254, 259
ready copy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 173
writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Bus
100-MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 3
Accelerated Graphic Port (AGP). . . . . . . . . . . . . . . . . . . . .1, 3
Acknowledge, Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Address
bus . . . . . . . . . . . . . . . 86–91, 100, 127, 148, 152, 154, 194
hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
parity check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
stack, return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
address . . . . . . . . . . . . 88–91, 100, 127, 148, 152, 154, 194
arbitration cycles, inquire and . . . . . . . . . . . . . . . . . . . . 142
backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
cycles, special. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87, 263–264
ADSC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
AGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3
AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88, 244
-initiated inquire hit to modified line. . . . . . . . . . . . . . . 152
-initiated inquire hit to shared or exclusive line . . . . . . 150
-initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Airflow
consideration, layout and. . . . . . . . . . . . . . . . . . . . . . . . . 291
management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Allocate, Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
AP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
APCHK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
data . 88, 91, 94, 98–99, 114, 117, 130–132, 148, 154, 158
enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
hold request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Bus States
address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
data-NA# requested. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
pipeline address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
BYPASS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
Asserted. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
C
B
Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
branch target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Base Address, SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92, 173, 247
Index
303
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
inhibit, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
D[63:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Data
L1 . . . . . . . . . . . . . . . . . . . . . 1, 38, 179, 190, 194, 199, 221
MESI states in the data . . . . . . . . . . . . . . . . . . . . . . . . . . 180
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179, 201
snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
writeback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6, 9
CACHE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96, 183
Cacheable
bus . . 88, 91, 94, 98–99, 114, 117, 130–132, 148, 154, 158
cache, MESI states in the . . . . . . . . . . . . . . . . . . . . . . . . 180
parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Data Types
3DNow! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data/Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 254, 259
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
page, write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Cache-Line
Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 236
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Decode, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Decoupling Recommendations. . . . . . . . . . . . . . . . . . . . . . 250
Descriptions, Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Design, Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Designations, Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Device Identification Register . . . . . . . . . . . . . . . . . . . . . . 230
Diagram, Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Diagrams, Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Disabling, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Dissipation, Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257, 262
DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Drive Strength, Selectable . . . . . . . . . . . . . . . . . . . . . . . . . 263
Driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185, 196
Cache-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Capture-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Capture-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ceramic Pin Grid Array (CPGA) . . . . . . . . . . . . . . . . . . .1, 299
Characteristics
I/O buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
I/O Buffer AC and DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Clock States
halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
stop clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167, 246–247
stop grant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167, 245
stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Coherency States, Writethrough vs. Writeback. . . . . . . . . 199
Coherency, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Compatibility, Floating-Point, MMX, and 3DNow!
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Configuration and Initialization, Power-on . . . . . . . . . . . . 173
Connection Requirements, Pin . . . . . . . . . . . . . . . . . . . . . . 251
Connections, Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Control
register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
unit, scheduler/instruction. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Counter, Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 299, 302
Cycle
hold and hold acknowledge . . . . . . . . . . . . . . . . . . . . . . . 142
shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Cycles
bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
inquire . . . . . . . .85–90, 100, 104–105, 118, 123, 138, 142,
. . . . . . . 144, 146, 148, 150–152, 154, 156, 160, 194,
E
EADS#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 39, 50, 176, 201
EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Environment, Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EWBE Control (EWBEC) . . . . . . . . . . . . . . . . . . . . . . . . . . 201
EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 201, 244
Exception . . . . 89–90, 99, 102, 114, 166, 209, 220, 240–242
flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26–27
floating-point . . . . . . . . . . . . . . . . . . . . . . 102, 106, 207–209
handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
machine check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Exceptions
and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
handling floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . 207
interrupts, and debug in SMM . . . . . . . . . . . . . . . . . . . . 220
MMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Execution Unit
. . . . . . . . . . . . . . . . . . . . . . . . . 197–199, 235, 243–246
inquire and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . 142
interrupt acknowledge . . . . . . . . . .86, 89, 91, 97, 112, 122
locked. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10, 87
pipelined write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
special bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
writeback. . . . . . 85, 87–88, 101, 104, 123, 138, 146, 150,
. . . . . . . . . . . . . . . . 152, 154, 156, 160, 183, 236, 246
3DNow! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 16–17
branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 14, 19
floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . .2, 7, 14, 207
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 14
D
D/C# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
304
Index
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
multimedia . . . . . . . . . . . . . . . . . . . . . . 2, 7, 14, 16–17, 209
register X. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 14, 16–17
register Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 14, 16–17
store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7, 14
Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 6–8, 15
External
address strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
write buffer empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
I
I/O
buffer AC and DC characteristics . . . . . . . . . . . . . . . . . 265
buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
buffer model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
misaligned read and write . . . . . . . . . . . . . . . . . . . . . . . 141
model application note . . . . . . . . . . . . . . . . . . . . . . . . . . 265
read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
IBIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
F
IEEE 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 223
FERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102, 208–209
Fetch, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IEEE 754. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 25, 207
IEEE 854. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
IGNNE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106, 208–209
Ignore Numeric Exception . . . . . . . . . . . . . . . . . . . . . . . . . 106
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107, 244
-initiated transition from protected mode to real mode 170
state of processor after . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
power-on configuration and . . . . . . . . . . . . . . . . . . . . . . 173
Input Setup and Hold Timings for
Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122, 125
Floated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Floating-Point
and MMX/3DNow! instruction compatibility. . . . . . . . . 209
and multimedia execution units . . . . . . . . . . . . . . . . . . . 207
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
handling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . 103, 173, 195, 222, 244
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247, 268, 280
operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92, 97, 173
Frequency Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Functional Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
multimedia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . 272
66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145, 147, 149, 243
and bus arbitration cycles. . . . . . . . . . . . . . . . . . . . . . . . 142
cycle hit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
cycle hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . 104
cycles.85–90, 100, 104–105, 118, 123, 138, 142, 144, 146,
148, . . . . 150–152, 154, 156, 160, 194, 197–199, 235,
243–. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
miss, AHOLD-initiated . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Instruction
decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Instructions
G
Gate Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46, 49
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Global EWBE Disable (GEWBED) . . . . . . . . . . . . . . . . . . . 201
Grounding, Power and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
3DNow! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81, 209
EMMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FEMMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
H
Halt State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Handling Floating-Point Exceptions. . . . . . . . . . . . . . . . . . 207
Heat Dissipation Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
History Table, Branch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Hit to
MMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78, 209
PREFETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 192
supported by the AMD-K6-2 processor . . . . . . . . . . . . . . 54
TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
WBINVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Integer Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Internal
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–19
snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Interrupt . . . . . . . . . . . . . . 108, 117, 162, 166–167, 170, 177,
. . . . . . . . . . . . . . . . . . . . . 207–209, 212, 220, 241, 246
acknowledge. . . . . . . . .86, 94, 97, 108, 110, 114, 158, 162
acknowledge cycles . . . . . . . . . . . . 86, 89, 91, 97, 112, 122
descriptor table register . . . . . . . . . . . . . . . . . . . . . . . 40–41
flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 117
flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
redirection bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
modified line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
modified line, AHOLD-initiated inquire . . . . . . . . . . . . 152
modified line, HOLD-initiated inquire. . . . . . . . . . . . . . 146
shared or exclusive line, AHOLD-initiated inquire. . . . 150
shared or exclusive line, HOLD-initiated inquire . . . . . 144
HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
HITM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104, 263–264
HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
-initiated inquire hit to modified line. . . . . . . . . . . . . . . 146
-initiated inquire hit to shared or exclusive line . . . . . . 144
Hold
acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . .105, 142–144
and hold acknowledge cycle . . . . . . . . . . . . . . . . . . . . . . 142
timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267, 282
service routine . . . . . . . . . . . . . . . . . . . . .108, 112, 208, 211
system management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Index
305
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
type of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupts
MTRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 189–190, 203
Multimedia
01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
exceptions and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
INTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
IRQ13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
NMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
INTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108, 244
INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Invalidation Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
INVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 16–17, 209
functional unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
N
NA# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Negated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Next Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112, 244
No-Connect Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116, 251
Non-Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Non-Pipelined. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
K
KEN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109, 186
O
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253, 258
L
Operation, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Organization, Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . 179, 201
Output Delay Timings
for 100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . 270
for 66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 274
Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
L1 Cache . . . . . . . . . . . . . . . . . . . . . .1, 38, 179, 190, 199, 221
inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Limit, Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Line Fills, Cache- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
LOCK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Locked
cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
operation with BOFF# intervention . . . . . . . . . . . . . . . . 160
operation, basic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Logic
branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–18
external support of floating-point exceptions . . . . . . . . 207
P
Package
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
thermal specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Page
cache disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
directory entry (PDE) . . . . . . . . . . . . . . . . . . . . . 44–45, 182
table entry (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . 44, 46, 182
writethrough. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Parity. . . . . . . . . . . . . . . . . . . . . . . . . . 84, 89, 91, 99, 114, 132
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89, 99, 114
check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89–90, 99, 114
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90, 114, 148, 224
flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113, 182, 190
PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
M
M/IO# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Machine Check Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
MCAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 50, 176
MCTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37–38, 50, 176
Memory
or I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
read and write, misaligned single-transfer . . . . . . . . . . 134
read and write, single-transfer . . . . . . . . . . . . . . . . . . . . 132
reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
type range register (MTRR) . . . . . . . . . . 52, 189–190, 203
MESI. . . . . . . . . . . . . . . . . . 1, 9, 142, 146, 180, 192, 197, 199
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10, 180
states in the data cache . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
enhanced RISC86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
overview, AMD-K6-2 processor . . . . . . . . . . . . . . . . . . . . . . 5
Misaligned
PFIR . . . . . . . . . . . .50, 53, 175–176, 184, 195–197, 199, 236
Pin
connection requirements . . . . . . . . . . . . . . . . . . . . . . . . 251
description diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 130–131, 136
control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
register X and Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
six-stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 8
Pipelined. . . . . . . . . .9, 16, 112, 131, 136–137, 154, 179, 192
burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
I/O read and write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
single-transfer memory read and write . . . . . . . . . . . . . 134
cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 87, 98
design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pointer, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power
and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257, 262
Power-on Configuration and Initialization . . . . . . . . . . . . 173
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10, 180
MMX Technology . . . . . . . . . . . .13–17, 21, 54, 116, 173, 177
exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
instruction compatibility, floating-point and. . . . . . . . . 209
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78, 210
register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Mode, Tri-State Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . 37
MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
306
Index
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10, 192
PSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 53, 175–176
PWT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
S
SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . . . . . 232
Sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Scheduler
centralized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
instruction control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SCYC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Sector, Write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Segment
R
Ranges, Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . .253, 258
Ratings, Absolute . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254, 259
Read and Write
descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 46–48
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
task state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Selectable Drive Strength. . . . . . . . . . . . . . . . . . . . . . . . . . 263
Shift-DR state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Shift-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Signal
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 267
terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
timing, RESET and test. . . . . . . . . . . . . . . . . . . . . . . . . . 278
Signals
basic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
misaligned I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Reads, Burst Reads and Pipelined Burst . . . . . . . . . . . . . . 136
Register
boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
bypass (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
data Types, floating-point . . . . . . . . . . . . . . . . . . . . . . . . . 28
debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34, 236
floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
general-purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SYSCALL/SYSRET Target Address (STAR) . . . . . . . . . . 39
Register X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register X and Y
pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
A[20:3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263–264
A[31:3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
A20M#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85, 212
ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87, 263–264
ADSC#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 21, 174, 209
AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88, 244
AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
APCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3DNow!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21, 29
descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
device identification (DIR) . . . . . . . . . . . . . . . . . . . . . . . 230
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
DR6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
DR7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
extended feature enable register (EFER) . . . . . . . . .39, 50
IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
MCAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MMX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21, 29
PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
TR12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
UWCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
BF[2:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92, 247
BOFF# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93, 156
BRDY#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 263
BREQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
CACHE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96, 183
cache-related . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
D/C#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
D[63:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
EADS#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 201, 244
FERR#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 209
FLUSH# . . . . . . . . . . . . . . . . . . . . . 103, 173, 195, 222, 244
HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
HITM#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104, 263–264
HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
IGNNE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106, 209
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107, 244
WHCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40, 51
X and Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–16
Regulator, Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Replacement, Cache-Line . . . . . . . . . . . . . . . . . . . . . .185, 196
Requirements, Pin Connection . . . . . . . . . . . . . . . . . . . . . . 251
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116, 174, 244
and Test Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 278
signals sampled during. . . . . . . . . . . . . . . . . . . . . . . . . . . 173
state of processor after. . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Return Address Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision Identifier, SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
RISC86 Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 244
INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
KEN#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
LOCK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
M/IO#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
NA# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112, 244
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
PWT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
RSM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217, 220
RSVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Index
307
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
output delay timings for 100-MHz bus. . . . . . . . . . . . . . 270
output delay timings for 66-MHz bus. . . . . . . . . . . . . . . 274
signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
valid delay, float, setup, and hold timings. . . . . . . . . . . 269
SYSCALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SYSCALL/SYSRET Target Address Register (STAR) . . . . 37,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39–40, 50, 176
SYSRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
System
design, airflow management in a . . . . . . . . . . . . . . . . . . 292
management interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 117
management interrupt active. . . . . . . . . . . . . . . . . . . . . 118
management mode (SMM) . . . . . . . . . . . . . . . . . . . . . . . 211
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116, 244
RSVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
sampled during RESET . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SCYC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SMI# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117, 211, 244
SMIACT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118, 211
STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119, 245
TAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
VCC2H/L# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
W/R#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122, 263–264
WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SIMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2, 9
Single Instruction Multiple Data (SIMD). . . . . . . . . . . . . .2, 9
Single-Transfer Memory Read and Write. . . . . . . . . . . . . . 132
SMI# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117, 211, 244
SMIACT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118, 211
SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
default register values . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
I/O trap DWORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
I/O trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
state-save area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
T
Table, Branch History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
TAP Controller States
capture-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
capture-IR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
shift-DR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
shift-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
test-logic-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
update-DR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
update-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
BYPASS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
HIGHZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
TAP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
instruction register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . 224
TAP Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Target Cache, Branch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Task State Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
TDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Temperature . . . . . . . . . . . . . . . . . . . . . . . . .253, 258, 285, 288
case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Terminology, Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Test
access port, boundary-scan . . . . . . . . . . . . . . . . . . . . . . . 223
and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
-logic-reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
mode select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
mode, tri-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
register 12 (TR12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Snoop . . . . . . . . . . . . . . . . . . . . . . 118, 123, 138, 195, 197–198
Snooping
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Special
bus cycle . . . . . . . . . . . . . . . . . . 94, 119, 164–167, 218, 245
cycle . . . . . . . 101, 103, 119, 126, 138, 164, 166–167, 184,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244–245
Specifications
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
package thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Speculative EWBE Disable (SEWBED) . . . . . . . . . . . . . . . 202
Split Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Stack, Return Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
State Machine Diagram, Bus . . . . . . . . . . . . . . . . . . . . . . . . 129
State of Processor
after INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
after RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
States, Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
State-Save Area, SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Stop
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . .257, 262, 288, 292
design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
heat dissipation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
layout and airflow consideration . . . . . . . . . . . . . . . . . . 291
measuring case temperature . . . . . . . . . . . . . . . . . . . . . 290
package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Timing Diagram
clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167, 246–247
grant inquire state . . . . . . . . . . . . . . . . . . . . . . . . . . 243–246
grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167, 245–246
STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119, 245
Super7 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3–4
initiative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 267
100-MHz bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 268
66-MHz bus operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
input setup and hold timings for 100-MHz bus . . . . . . . 272
input setup and hold timings for 66-MHz bus . . . . . . . . 276
test signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 127, 133–171
TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
TR12 . . . . . . . . . . . . . . . . . . . . . 37–38, 50, 176, 183, 190, 235
308
Index
Preliminary Information
®
21850J/0—February 2000
AMD-K6 -2 Processor Data Sheet
Transition from Protected Mode to Real Mode, INIT-Initi-
ated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Translation Lookaside Buffer (TLB) . . . . . . . . . . . . . . . . . . 179
Trap Dword, I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Tri-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
TSC. . . . . . . . . . . . . . . . . . . . . . . . . . . 37–38, 50, 176, 244–245
TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42, 48–49, 215, 240
U
Uncacheable Memory. . . . . . . . . . . . . . . . . . . . . . .52, 202–203
UWCCR . . . . . . . . . . . . . .50, 52, 174–176, 183–184, 203–206
V
VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
VCC2H/L# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Voltage . . . . . . . . 121, 128, 249, 253–254, 258–259, 264, 267
ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291–292
W
W/R#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122, 263–264
WAE15M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
WAELIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
WBINVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
WCDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40, 187
WHCR . . . . . . . . . . . . . . . . . . . . .37, 40, 50–51, 176, 187, 191
Write
handling control register (WHCR) . . . . . . . . . . . . . . . . . . 40
to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Write Allocate. . . . . . . . . . . . . . . . . . . 181, 186–187, 190–191
enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40, 187
enable limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40, 187
limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
logic mechanisms and conditions . . . . . . . . . . . . . . . . . . 190
Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Write/Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Writeback . . . 96, 98–99, 109, 115, 118, 123, 126, 138–139,
. . . . . . . . . . . . . . . . . . . . .164, 179, 185, 192, 199, 248
burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6, 9
cycles . . . . . 85, 87–88, 101, 104, 123, 138, 146, 150, 152,
. . . . . . . . . . . . . . . . . . . . .154, 156, 160, 183, 236, 246
or writethrough. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Write-combining Memory . . . . . . . . . . . . . . . . . . .52, 202–203
Writethrough vs. Writeback Coherency States . . . . . . . . . 199
Index
309
Preliminary Information
®
AMD-K6 -2 Processor Data Sheet
21850J/0—February 2000
310
Index
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