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AN-16 [ETC]

TOPSwitch Flyback Design Methodology ; TOPSwitch的反激式设计方法\n
AN-16
型号： AN-16
厂家： ETC    ETC
描述：

TOPSwitch Flyback Design Methodology
TOPSwitch的反激式设计方法\n
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®
TOPSwitch® Flyback  
Design Methodology  
Application Note AN-16  
Designing an off-line switching power supply involves many  
aspects of electrical engineering: analog and digital circuits,  
bipolar and MOS power device characteristics, magnetics,  
thermal considerations, safety requirements, control loop  
stability, etc. This presents an enormous challenge involving  
complex trade-offs with a large number of design variables.  
However, with TOPSwitch’s high level of integration, this  
design task has been greatly simplified. Because of the  
significantly reduced number of design variables and built-in  
loop stability, it is possible to develop a simple step-by-step  
design method that is easy to follow and quickly leads to  
satisfactory results.  
simplifiedversionofthedesignmethodwhich,atimplementation  
level,guidesthereaderfromasetofgivensystemrequirements/  
specifications all the way to the completion of the desired  
TOPSwitchflybackpower supplyusingrules ofthumb, lookup  
tables and a simple spread sheet program. The information  
section, at optimization level, makes available the key  
backgroundinformationforthedesignmethod,suchasequations  
and guidelines. Cross references are provided among the three  
which allow the reader to switch among conceptual,  
implementation and optimization levels at any given stage for  
an in-depth understanding and/or further optimization.  
Basic circuit configuration  
Introduction  
Because of the high level integration of TOPSwitch, many  
power supply design issues are resolved in the chip. Far fewer  
issues are left to be addressed externally, resulting in one basic  
circuit configuration remaining unchanged from application to  
application. Different output power levels may require the use  
of different values for some circuit components, but the circuit  
configuration itself stays valid. Application specific issues  
outside of the basic flyback converter requirements (such as  
constant current, constant power outputs, etc.) are beyond the  
The design of a switching power supply, by nature, is an  
iterative processwithmanyvariablesthat have tobe adjustedto  
optimize the design. The design method described below  
consistsofthreeparts:acompletedesignflowchart,asimplified  
step-by-step design procedure and an in-depth information  
section. The flow chart, at conceptual level, serves as a map  
providing an overall picture and guideline for the complete  
design methodology. The step-by-step design procedure is a  
Output Post Filter L, C  
Clamp Zener  
Output Capacitor  
+V  
+V  
-
V+  
D
+
-
V
O
FUSE  
+
-
V
B
DB  
CM  
CHOKE  
-
V
C
X
AC  
Blocking Diode  
Bias Capacitor  
TOPSwitch  
C
IN  
DRAIN  
SOURCE  
CONTROL  
Feedback Circuit  
Control Pin Capacitor  
and Series Resistor  
V-  
PI-1849-050696  
Figure 1. Typical TOPSwitch Flyback Power Supply.  
June 1996  
AN-16  
1. System Requirements  
VACMIN, VACMAX, fL, VO, PO, η, Z  
Step 1-2  
Determine System Level Requirements  
and Choose Feedback Circuit  
2. Choose Feedback Circuit & VB  
3. Determine CIN, VMIN  
4. Determine VOR, VCLO  
5. Determine DMAX  
6. Set KRP  
7. Determine IAVG, IP, IR, IRMS  
8. Choose TOPSwitch  
Step 3-11  
Choose The Smallest TOPSwitch  
For The Required Power  
9. Calculate TOPSwitch loss PD  
Y
10. PD Too High  
N
11. IP= 0.9 x ILIMIT  
or  
N
KRP= 1  
Y
To Step 12  
PI-1868-052896  
Figure 2A. TOPSwitch Flyback Design Flow Chart, Step 1 to 11.  
scope of this application note. However, such requirements are  
usually implemented by adding additional circuitry to the basic  
converterconfiguration. Theonlypartofthecircuitconfiguration  
that may change is the feedback circuitry. Depending on the  
power supply outputrequirement, one of four possible circuits,  
shown in Figures 3-6, will be chosen for the application.  
Design Flow  
Figure 2A, B and C present a design flow chart showing the  
complete design procedure in 35 steps. With the basic circuit  
configuration shown in Figure 1 as its foundation, the logic  
behind this design approach can be summarized as following:  
ThebasiccircuitconfigurationusedinmostTOPSwitchflyback  
power supplies is shown in Figure 1 which also serves as the  
reference circuit for component identifications used in the  
descriptions throughout this application note.  
1. Determine system requirements and decide on feedback  
circuit accordingly.  
2. Find the smallest TOPSwitch capable for the application.  
3. DesignthesmallesttransformerfortheTOPSwitch chosen.  
4. Select all other components in Figure 1 to complete the  
design.  
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From Step 11  
12. Determine LP  
13. Choose Core & Bobbin  
Determine Ae, Le,AL, BW  
Y
N
14. Set NS, L  
22. NS, L Iterated  
15. Calculate NP, NB  
16. Calculate BM  
N
N
N
17. 2000 ≤ BM≤ 3000  
Y
Step 12-24  
Design The Smallest Transformer  
To Work with The TOPSwitch Chosen  
18. Calculate Lg  
19. Lg  
>
0.051 mm  
Y
20. Calculate OD, DIA, CMA  
21. 200 ≤ CMA ≤ 500  
Y
23. Calculate ISP, ISRMS, IRIPPLE  
DIAS, ODS  
24. Calculate PIVS, PIVB  
To Step 25  
PI-1869-052896  
Figure 2B. TOPSwitch Flyback Design Flow Chart, Step 12 to 24.  
The overriding objective of this procedure is “design for cost  
effectiveness”. Using smaller components will usually lead to  
a less expensive power supply. However, for applications with  
stringent size or weight limitations, the designer may need to  
strike a compromise between cost and specific design  
requirements in order to achieve the ultimate cost effectiveness  
at the end product.  
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From Step 24  
25. Select Clamp Zener & Blocking Diode  
26. Select Output Rectifier  
27. Select Output Capacitor  
N
28. Switching Ripple  
Too High  
Y
29. Select Output Post Filter L, C  
Step 25-35  
Select Other Components  
30. Select Bias Rectifier  
31. Select Bias Capacitor  
32. Select Control Pin Capacitor  
& Series Resistor  
33. Select Feedback Circuit Compenents  
According to Reference Designs:  
RD1, ST202A, ST204A  
34. Select Bridge Rectifier  
35. Design  
Complete  
PI-1870-052896  
Figure 2C. TOPSwitch Flyback Design Flow Chart, Step 25 to 35.  
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Step by Step Design Procedure  
This design procedure uses the AN-17 spreadsheet (available from Power Integrations), which contains all the important equations  
required for a TOPSwitch flyback power supply design, and automates most calculations. Designers therefore are relieved from the  
tediouscalculationsinvolvedinthecomplicatedandhighlyiterativedesignprocess. Anytimeaparameterisinvolvedinacalculation,  
whether it is an input or an output, a cell location for the parameter will be shown in parenthesis at the right side of the page. For  
example (A1) denotes column A and row 1. Note that all user provided inputs are in column B and all spreadsheet calculated results  
are in column D. Column C is reserved for intermediate variables needed in some complicated calculations. Look up tables and rules  
of thumb are also provided wherever appropriate, to facilitate the design task. For questions regarding any particular step of this  
procedure, please refer to the corresponding step in the information section, where in-depth explanation is provided.  
Step 1.  
Determine system requirements: VACMAX, VACMIN, fL, fS, VO, PO, η, Z  
• Set minimum AC input voltage, VACMIN, per Table 1  
• Set maximum AC input voltage, VACMAX, per Table 1  
(B3)  
(B4)  
Input (VAC)  
100/115  
Universal  
230  
VACMIN (VAC)  
VACMAX (VAC)  
85  
132  
265  
265  
85  
195  
Table 1  
• Line frequency, fL: 50Hz or 60Hz  
• TOPSwitch switching frequency, fS: 100KHz  
• Output voltage, VO: in Volts  
• Output power, PO: in Watts  
• Power supply efficiency, η: 0.8 if no better reference data available  
• Loss allocation factor, Z: 0.5 if no better reference data available  
(B5)  
(B6)  
(B7)  
(B8)  
(B9)  
(B10)  
Step 2.  
Choose feedback circuit and bias voltage VB based on output requirements:  
• Select a feedback circuit (Figures 3-6) based on output specification:  
Feedback  
Circuit  
Output  
Load  
Line  
Regulation  
Reference  
Design  
VB (V) Accuracy Regulation  
Primary/basic  
5.7  
±10%  
±5%  
±5%  
±1%  
±5%  
±1.5%  
±1.5%  
±0.5%  
±0.2%  
RD1  
Primary/enhanced 27.7  
±2.5%  
±1%  
RD1  
Opto/Zener  
Opto/TL431  
12  
12  
ST202A  
ST204A  
±0.2%  
Table 2  
• Choose required bias voltage, VB , per Table 2  
(B11)  
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Step 3.  
Determine input storage capacitor CIN and minimum DC input voltage VMIN based on input voltage and PO:  
• Set bridge rectifier conduction time, tC = 3 mS  
• Choose input storage capacitor, CIN, per Table 3  
• Derive minimum DC input voltage, VMIN  
(B12)  
(B13)  
(D33)  
Input (VAC) CIN (µF/Watt of PO) VMIN (V)  
100/115  
Universal  
230  
2~3  
2~3  
1
≥90  
≥90  
≥240  
Table 3  
Step 4.  
Determine reflected output voltage VOR and clamp Zener voltage VCLO based on input voltage:  
• Set VOR based on input voltages per Table 4  
(B16)  
VOR (V)  
60  
Input (VAC)  
100/115  
Universal  
230  
VCLO (V)  
90  
135  
200  
135  
200  
Table 4  
Note : VCLO is to be used in Step 25 for clamp Zener selection  
Step 5.  
Determine DMAX based on VMIN and VOR:  
• Set TOPSwitch Drain to Source voltage, VDS = 10 V  
• Determine maximum duty cycle at low line, DMAX  
(B17)  
(D37)  
Step 6.  
Set value for primary ripple current IR to primary peak current IP ratio, KRP:  
• Starting with: KRP = 0.4 for 100/115 VAC or universal input  
0.6 for 230 VAC  
(B20)  
• KRP must be kept within the range specified in Table 5 throughout iteration  
KRP  
Input (VAC)  
Minimum  
Maximum  
(Most Continuous) (Discontinuous)  
100/115  
Universal  
230  
0.4  
0.4  
0.6  
1.0  
1.0  
1.0  
Table 5  
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Step 7.  
Determine primary waveform parameters IAVG, IP, IR, IRMS  
:
• Calculate average input current, IAVG : in Amps  
• Calculate primary Peak current, IP : in Amps  
• Calculate primary ripple current, IR : in Amps  
• Calculate primary RMS current, IRMS : in Amps  
(D38)  
(D39)  
(D40)  
(D41)  
Step 8 to Step 10.  
Choose the smallest possible TOPSwitch for the job under practical thermal limitation  
• Start with the smallest TOPSwitch based on minimum current limit spec such that 0.9 x ILIMIT(minimum) ≥ IP  
• Refer to AN-14 Table 2 for thermal considerations. Select larger TOPSwitch if necessary.  
Step 11.  
Check minimum ILIMIT of the selected TOPSwitch against required peak current IP. Increase KRP until KRP = 1.0 or  
IP = 0.9 x ILIMIT(minimum)  
• Enter new value of KRP  
• Monitor IP  
(B20)  
(D39)  
• Iterate until KRP = 1.0 or IP = 0.9 x ILIMIT(minimum)  
Step 12.  
Calculate primary inductance LP  
(D44)  
Step 13.  
Choose core and bobbin based on PO using AN-18 Appendix A, Table 2 anddetermine Ae, Le, AL and BW from core  
and bobbin catalog:  
• Core effective cross sectional area, Ae: in cm2  
• Core effective path length, Le: in cm  
(B24)  
(B25)  
(B26)  
(B27)  
• Core ungapped effective inductance, AL: in nH/turn2  
• Bobbin width, BW : in mm  
Step 14.  
Set value for number of primary layers L and number of secondary turns NS (may need iteration):  
• Starting with L = 2 (Keep 1.0 ≤ L ≤ 2.0 throughout iteration)  
• Starting with NS= 1 turn/volt for 100/115 VAC  
0.6 turn/volt for 230 VAC and universal inputs  
• Both L and NS may need iteration  
(B29)  
(B30)  
Step 15.  
Calculate number of primary turns NP and number of bias turns NB:  
• Diode voltages: use 0.7V for P/N diode and 0.4V for schottky diode  
• Set output rectifier forward voltage, VD  
• Set bias rectifier forward voltage, VDB  
• Calculate number of primary turns NP  
• Calculate number of bias turns NB  
(B18)  
(B19)  
(D45)  
(D46)  
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Step 16 to Step 22.  
Check BM, CMA and Lg. Iterate if necessary by changing L, NS or core/bobbin until within specified range:  
• Set safety margin, M. Use 3 mm (118 mils) for margin wound  
with 230 VAC or universal input and 1.5 mm (59 mils) for  
110/115 VAC input. Set to zero for triple insulated secondary.  
• Maximum flux density, BM: 3000 ≥ BM ≥ 2000; in Gauss  
• Gap length, Lg: Lg ≥ 0.051 mm  
(B28)  
(D48)  
(D51)  
(D58)  
• Primary winding current capacity, CMA: 500 ≥ CMA ≥ 200;  
in circular mils per Amp  
• Iterate by changing L, NS, core/bobbin according to Table 6  
• Primary minimum conductor diameter, DIA: in mm  
• Primary maximum wire outside diameter, OD: in mm  
(D55)  
(D53)  
BM  
Lg  
CMA  
L
↑
↑
↑
-
-
↑
↓
↑
(B29)  
NS  
↓
↓
↑
↑
(B30)  
Core  
Table 6  
(B24/25/26/27)  
Step 23.  
Determine secondary parameters ISP, ISRMS, IRIPPLE, DIAS, ODS:  
• Secondary Peak current, ISP : in Amps  
• Secondary RMS current, ISRMS : in Amps  
• Output capacitor ripple current, IRIPPLE : in Amps  
• Secondary minimum conductor diameter, DIAS : in mm  
• Secondary maximum wire outside diameter, ODS : in mm  
(D61)  
(D62)  
(D64)  
(D68)  
(D69)  
Step 24.  
Determine maximum peak inverse voltages PIVS, PIVB for secondary and bias windings:  
• Secondary winding maximum peak inverse voltage PIVS: in Volts  
• Bias winding maximum peak inverse voltage PIVB: in Volts  
(D74)  
(D75)  
Step 25.  
Select clamp Zener and blocking diode for primary clamping per Table 7 based on input voltage and VCLO (from Step 4):  
Input (VAC)  
VCLO (V)  
Zener  
Diode  
100/115  
Universal  
230  
90  
P6KE91  
P6KE200  
P6KE200  
BYV26B  
BYV26C  
BYV26C  
200  
200  
Table 7  
Notes: 1. P6KE91:  
91V/5W; Motorola  
P6KE200:  
BYV26B:  
BYV26C:  
200V/5W; Motorola  
400V/1A, UFR; Philips  
600V/1A, UFR; Philips  
2. Ishizuka 180V Zener may be used for lower power TOP210, TOP200, TOP201 applications  
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Step 26.  
Select output rectifier per Table 8 such that:  
• VR ≥ 1.25 x PIVS; where PIVS is from Step 24 and VR is the rated reverse voltage of the rectifier diode  
• ID ≥ 3 x IO; where ID is the diode rated DC current and IO = PO/VO  
Rectifier Diode  
VR (V) ID (A) Manufacturer  
Schottky 1N5819  
1N5822  
40  
40  
45  
45  
1.0  
3.0  
7.5  
10  
Motorola  
Motorola  
Motorola  
Motorola  
Motorola  
GI  
Motorola  
Motorola  
GI  
Philips, GI  
GI  
GI  
Motorola  
Motorola  
Motorola  
Motorola  
Philips, GI  
Philips  
MBR745  
MBR1045  
MBR1645  
45  
16  
UFR  
UF4002  
100  
100  
200  
200  
200  
100  
200  
100  
200  
100  
200  
200  
200  
1.0  
1.0  
1.0  
1.0  
2.0  
3.0  
3.0  
4.0  
4.0  
8.0  
8.0  
8.0  
20  
MUR110  
MUR120  
UF4003  
BYV27-200  
UF5401  
UF5402  
MUR410  
MUR420  
MUR810  
MUR820  
BYW29-200  
BYV32-200  
Table 8  
Step 27.  
Select output capacitor based on IRIPPLE (from Step 23):  
• Capacitor ripple current specified @ 105 OC, 100KHz must be equal or larger than IRIPPLE, where IRIPPLE is from Step 23.  
• Use low ESR, electrolytic capacitor. Output switching ripple voltage is ISP x ESR , where ISP is from Step 23.  
• Use parallel capacitors to increase ripple current capacity for high current outputs.  
• Examples:  
Output  
Output Capacitor  
5V to 24V, 1A  
330uF, 35V, low ESR, electrolytic  
United Chemicon LXF35VB331M10X20LL  
Nichicon UPL1V331MRH  
Panasonic ECA-1VFQ331L  
5V to 24V, 2A  
1000uF, 35V, low ESR, electrolytic  
UnitedChemicon LXF35VB102M12.5X30LL  
Nichicon UPL1V102MRH  
Panasonic ECA-1VFQ102L  
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Step 28. to Step 29.  
Add output LC post filter if and only if output switching ripple voltage is not within specification:  
• Inductor L: 2.2 to 4.7µH. Use ferrite bead for low current (≤ 1A) output and standard off the shelf choke for higher current  
output. Increase choke current rating or wire size if necessary to avoid significant DC voltage drop.  
• Capacitor, C: 120uF, 35V, low ESR electrolytic  
United Chemicon LXF35VB121M8X12LL  
Nichicon UPL1V121MRH  
Panasonic ECA-1VFQ121L  
Step 30.  
Select bias rectifier per Table 9 such that VR ≥ 1.25 x PIVB; where PIVB is from Step 24 and VR is the rated reverse  
voltage of the rectifier diode.  
Rectifier  
VR (V)  
Manufacturer  
1N4148  
BAV21  
UF4003  
75  
Motorola  
Philips  
GI  
200  
200  
Table 9  
Step 31.  
Select bias capacitor:  
• Use 0.1uF, 50V, ceramic  
Step 32.  
Select Control pin capacitor and series resistor:  
• Control pin capacitor: use 47uF, 10V, low cost electrolytic (Do not use low ESR capacitor).  
• Series resistor: use 6.2 Ω, 1/4 Watt (Not needed if KRP = 1, e.g. discontinuous mode).  
Step 33.  
Select feedback circuit components according to applicable Reference Design: RD1, ST202A, ST204A.  
• Applicable reference design: identified in Step 2.  
• Detailed component information: refer to appropriate reference design board documentation.  
Step 34.  
Select input bridge rectifier such that:  
• VR ≥ 1.25 x (1.414 x VACMAX); where VACMAX is from Step 1.  
• IACRMS ≥ 2 x ID; where ID is the bridge rectifier rated RMS current and IACRMS is the input RMS current.  
P
O
Note: IACRMS  
=
; where VACMIN is from step 1 and PF is the power factorof the power supply which  
η × VACMIN × PF  
is typically between 0.5 and 0.7. If no better reference data is available, use 0.5.  
Step 35. TOPSwitch flyback power supply design complete.  
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For a power supply with an output power PO and an efficiency  
η, PO x (1-η)/η watts of power is lost somewhere in the system:  
part in the secondary circuits, and the balance in the primary  
circuits. It is important to know the loss distribution between  
primary and secondary because only the secondary losses  
represent power that must be processed by the transformer and  
considered in the transformer design. Note that the power  
dissipated at the primary clamp is considered as secondary loss  
becausethispowerisprocessedbythetransformerbeforebeing  
delivered to the clamp circuit. The ratio of the secondary loss  
to the total loss is defined as the loss allocation factor, Z, which  
shouldbesetbasedonexperience.Avalueof0.5shouldbeused  
if no reference data is available.  
In-depth Information  
Step 1. Determinesystemrequirements:VACMAX,VACMIN  
fL, fS, VO, PO, η, Z  
,
Thestep-by-stepprocedureusespredeterminedparametervalues  
such as VACMAX, VACMIN, VMIN, VOR and VCLO for most commonly  
encountered input voltage ranges: 85 to 132 VAC for 100/115  
VAC, 195 to 265 VAC for 230 VAC and 85 to 265 VAC for  
universalinput. A ±15%linevoltagevariationisassumedinall  
cases. Applications with a different input voltage range can be  
handled by following the information and methods provided in  
Step 3, 4 and 5 of this in-depth information section to derive  
appropriate values for CIN, VOR, VCLO and VMIN  
.
Step 2. Decide on a Feedback/sense circuit and bias  
voltage VB  
Efficiency η is the ratio of output power to input power. Since  
efficiency can vary significantly with output voltage due to  
secondary diode loss, it is best to use a number that is  
representative of similar power supplies. Switching power  
supply efficiencies typically range from 75% for supplies  
delivering most of their power at low voltage outputs (5 or  
3.3V) to 85% for those supplying most of their power through  
higher voltage outputs (12V and above). If this data is not  
available, 80% is a reasonable choice.  
Four types of feedback/sense circuits are recommended. The  
primaryfeedbackcircuit,showninFigure3,istheleastexpensive  
but has lower absolute accuracy and regulation and is suitable  
onlyforlowpowerandhigheroutputvoltage(VO >5V). Output  
accuracy can be improved for the primary feedback circuit by  
adding a 22V Zener and a capacitor as shown in Figure 4. The  
D2  
1N5822  
L1  
3.3 µH  
1
+5V  
8
5
+
C2  
330 µF  
10 V  
C3  
100 µF  
10 V  
VR1  
RTN  
D1  
D3  
1N4148  
2
4
3
C1  
10 nF  
400 V  
DC  
INPUT  
R1  
15 Ω  
T1  
TRD1  
U1  
D
C
TOP  
210  
C5  
47 µF  
S
S
10 V  
-
PI-1850-050696  
Figure 3. RD1 Reference Design Board.  
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11  
AN-16  
D2  
1N5822  
L1  
3.3 µH  
1
+5V  
8
5
+
C2  
330 µF  
10 V  
C3  
100 µF  
10 V  
VR1  
D1  
RTN  
D3  
BAV21  
2
4
3
C1  
10nF  
400 V  
DC  
INPUT  
R1  
15 Ω  
T1  
TRD1-1  
U1  
D
C
VR 2  
1N5251D  
22 V  
TOP  
210  
C5  
47 µF  
10 V  
1%  
S
S
C4  
100 nF  
50 V  
-
PI-1851-050696  
Figure 4. RD1 Reference Design Board (Enhanced).  
D2  
L1  
UG8BT  
3.3 µH  
7.5 V  
R1  
39 Ω  
R2  
68 Ω  
C2  
680 µF  
25 V  
C3  
120 µF  
25 V  
VR1  
D1  
U2  
NEC2501  
VR2  
1N5234B  
6.2 V  
BR1  
C1  
400 V  
RTN  
33 µF  
L2  
22 mH  
400 V  
D3  
1N4148  
C7  
1 nF  
Y1  
C6  
0.1 µF  
C5  
47µF  
T1  
DRAIN  
SOURCE  
F1  
3.15 A  
CONTROL  
L
C4  
U1  
0.1 µF  
TOP202YAI  
N
J1  
PI-1852-050696  
Figure 5. ST202A Reference Design Board.  
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12  
AN-16  
D2  
L1  
3.3 µH  
MUR610CT  
15 V  
R2  
200 Ω  
1/2 W  
C3  
120 µF  
25 V  
C2  
1000 µF  
35 V  
VR1  
D1  
RTN  
C1  
47 µF  
400 V  
D3  
1N4148  
U2  
NEC2501  
BR1  
400 V  
L2  
C4  
0.1 µF  
33 mH  
R1  
510 Ω  
T1  
R4  
49.9 kΩ  
C9  
0.1 µF  
C6  
0.1 µF  
C5  
47 µF  
R3  
6.2 Ω  
U3  
TL431  
F1  
3.15 A  
DRAIN  
SOURCE  
R5  
10 kΩ  
L
CONTROL  
N
C7  
U1  
1 nF  
Y1  
TOP204YAI  
J1  
PI-1853-050696  
Figure 6. ST204A Reference Design Board.  
opto-coupler feedback using an accurate reference/comparator  
(Figure6)suchastheTL431forsensingprovideshighaccuracy  
and regulation at a slightly added cost and is applicable to all  
power and voltage ranges. An intermediate solution is to use an  
opto-coupler with a Zener sense circuit (Figure 5). This  
technique is suitable for medium power levels (up to 30W) and  
isreasonablyaccurate, especiallyatoutputvoltageshigherthan  
5V.  
a corresponding pay back in terms of higher VMIN or lower  
ripple, whereas lower values of CIN result in significantly lower  
VMIN increasingTOPSwitchcostduetoincreasedpeakoperating  
current demand. Lower values of CIN also increase input ripple  
voltage, which could increase output ripple voltage if the  
control loop gain is a limiting factor.  
The accurate calculation of VMIN for a given CIN (or vice versa)  
is a very complicated task which involves the solving of an  
equation with no closed form solution. The equation shown  
below represents a good first order approximation which is  
accurate enough for most situations.  
Step 3. Determine input capacitor CIN and minimum  
DC input voltage VMIN  
When the full wave rectified AC line is filtered with an input  
capacitance CIN (Figure 1), the resulting High Voltage DC bus  
(V+) has a ripple voltage as shown in Figure 7. The minimum  
DC voltage VMIN occurring at the lowest line voltage VACMIN is  
an important parameter for the design of the power supply. A  
rule of thumb on choosing the CIN value is to use 2 to 3 µF per  
watt of output power for 100/115 VAC or universal input, and  
1 µF/Watt for 230VAC. This results in a VMIN of 90VDC for  
100/115VAC or universal input and 240VDC for 230VAC,  
respectively. TheCIN valueobtainedbyusingthisrulerepresents  
a nearly optimum design in terms of system cost in most  
applications.HighervaluesofCIN increasecapacitorcostwithout  
1
2 × P ×  
− tC  
O
2 × fL  
η × CIN  
VMIN = (2 × VA2CMIN ) −  
tC is typically 3 ms, and can be verified by direct measurement.  
Step 4. Determine reflected output voltage VOR and  
clamp Zener voltage VCLO  
:
A
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13  
AN-16  
VACMIN × 2  
V+  
VMIN  
t
C
P = Output Power  
O
f = Line Frequency  
L
(50 or 60Hz)  
t = Conduction Angle  
C
Use 3ms if unknown  
1
2 × P × (  
− tC )  
O
2 × fL  
η × CIN  
VMIN = (2 × VA2CMIN ) − (  
)
η = Efficiency - Assume  
0.8 if unknown  
PI-1854-050696  
Figure 7. Input Voltage Waveform.  
A typical flyback circuit using TOPSwitch is shown in Figure  
1. When the TOPSwitch is off and the secondary is conducting,  
the voltage on the secondary is reflected to the primary side of  
the transformer by the turns ratio. This reflected voltage VOR  
adds to the input DC voltage at the TOPSwitch drain node.  
Worst case voltage at the drain occurs at high line when the DC  
input voltage is at its maximum value. The maximum DC input  
voltage can be calculated as:  
clamp voltage should not be used, because part of the stored  
energyinthecorewouldbedeliveredtotheZener, dramatically  
increasing Zener dissipation.  
The nominal clamp Zener voltage VCLO is usually specified at  
low current values and at room temperature. High voltage  
Zeners have a strong positive temperature coefficient and are  
quiteresistive. Consequently, theclampvoltageathighcurrent  
and high temperature VCLM can be much higher. Experimental  
data has shown that the VCLM can be as high as 40% above the  
specified VCLO  
VMAX = 2 × VACMAX  
InadditiontoVMAX+VOR thedrainalsoseesalargevoltagespike  
at turn off that is caused by the energy stored in the leakage  
inductance of the primary winding (see Figures 8 and 9). To  
keep this voltage spike from exceeding the rated minimum  
drain breakdown voltage BVDSS, a clamp circuit is needed  
across the primary winding. A Zener clamp as shown in  
Figure 1 is highly recommended over the usual RC clamp as it  
is much more effective in clamping the leakage energy during  
start up transients. The nominal value of Zener clamp voltage  
VCLO needs to be 50% (determined empirically) greater than the  
reflected voltage so that the Zener clamps only the leakage  
energy and does not impede the switch-over of current from the  
primary to the secondary. Experimental measurements show  
that this voltage margin is needed for the secondary current to  
be quickly established through the leakage inductance. Lower  
VCLM = 1.4 × VCLO  
This needs to be taken into consideration when choosing a  
clamp Zener. In addition, it is important to allow an additional  
20V for the spike due to the forward recovery time of the  
blocking diode in series with the clamp Zener. With all those  
factors considered, the maximum voltage that the TOPSwitch  
drain may experience is:  
VDRAIN = VMAX + (1.4 ×1.5 × VOR ) + 20V  
To minimize power supply cost, it is important to maximize the  
VOR consistent with the TOPSwitch breakdown voltage rating  
aftertakingintoaccountalloftheaboveeffects. Aswillbeseen  
A
6/96  
14  
AN-16  
BV  
350 V  
333 V  
313 V  
DSS  
MARGIN = 17 V  
BLOCKING DIODE FORWARD RECOVERY = 20 V  
277 V  
247 V  
V
V
CLM  
CLO  
V
= 60 V  
OR  
V
MAX  
187 V  
V
V
= 1.5 x V  
= 1.4 x V  
= 90V  
CLO  
CLM  
OR  
=126V  
CLO  
D
24%  
0 V  
0 V  
For 100/115 VAC Input Using 350 V TOPSwitch  
Use V = 60 V and 90 V Zener Clamp  
OR  
PI-1855-050696  
Figure 8. Reflected Voltage (VOR) and Clamp Zener Voltage (VCLO) - 100/115 VAC Input.  
BV  
700 V  
675 V  
655V  
DSS  
MARGIN = 25 V  
BLOCKING DIODE FORWARD RECOVERY = 20 V  
575 V  
510 V  
V
V
CLM  
CLO  
V
= 135 V  
OR  
V
MAX  
375 V  
V
= 1.5 x V  
= 200V  
= 280V  
CLO  
CLM  
OR  
V
= 1.4 x V  
CLO  
D
26%  
0 V  
0 V  
For Universal/230 VAC Input Using 700 V TOPSwitch  
Use V = 135 V and 200 V Zener Clamp  
OR  
PI-1856-050696  
Figure 9. Reflected Voltage (VOR) and Clamp Zener Voltage (VCLO) - Universal/230 VAC Input.  
A
6/96  
15  
AN-16  
later, a higher VOR will result in a larger DMAX which reduces  
TOPSwitch operating current for the same output power. If  
DMAX comes close to the maximum allowable duty cycle of the  
TOPSwitch(64%)thenVOR shouldnotbeincreasedanyfurther.  
Step 5. Determine maximum duty cycle at low line  
DMAX using VOR and VMIN  
Once the VOR and VMIN are known, it is easy to calculate the  
DMAX  
:
For a 100/115 VAC power supply the VACMAX based on  
115 VAC would be 132 VAC which corresponds to:  
VOR  
DMAX  
=
VOR + (VMIN − VDS )  
VMAX = 2 ×132 = 187V  
VDS is the average Drain to Source voltage during TOPSwitch  
ON time. As shown in Figures 10 and 11, with VDS set to zero,  
thevalueofDMAX rangesfrom36%/40%forsingleinputvoltage  
applications to 60% for the universal input application. In  
reality, VDS shouldbe set toapproximately10V whichresultsin  
Ascanbe seeninFigure 8, goingthroughthe above exercise for  
a VMAX of 187V using a 350V TOPSwitch results in a standard  
clamp Zener voltage of 90V and VOR of 60V and a margin of  
17V. Likewise in 230VAC or Universal application, a VACMAX  
of 265VAC corresponds to a VMAX of 375V. At this value of  
VMAX, a 700V TOPSwitch will allow for a standard Zener value  
of 200V with corresponding VOR of 135V leaving a margin of  
25V (see Figure 9). If these margins seem too small, it is  
important to remember that this analysis uses all worst case  
valuesaddedtogetherandtypicalmarginswillbemuchgreater.  
Also, TOPSwitch breakdown voltage increases at high  
temperature, providing additional margin.  
a slight increase in DMAX  
.
Higher VMIN directly increases the output power capability of a  
given TOPSwitch, while lower VMAX allows larger VOR and  
consequently larger DMAX, also increasing the output power of  
a given TOPSwitch. Therefore, a narrower input voltage range  
always leads to either a higher output power or a lower power  
supply cost.  
BV  
DSS  
350 V (700 V)  
236 V (540 V)  
216 V (520 V)  
BLOCKING DIODE FORWARD RECOVERY = 20 V  
180 V (440 V)  
150 V (375 V)  
V
V
CLM  
CLO  
V
= 60 V  
(135 V)  
OR  
V
MIN  
0 V  
90 V (240 V)  
V
= 1.4 x V  
=126V  
(200 V)  
CLM  
CLO  
D
40%  
(36%)  
MAX  
0 V  
PI-1857-050696  
Figure 10. Determine DMAX - 100/115 VAC (230 VAC) Input  
A
6/96  
16  
AN-16  
BV  
DSS  
700 V  
390 V  
370 V  
BLOCKING DIODE FORWARD RECOVERY = 20 V  
290 V  
V
V
CLM  
CLO  
225 V  
90 V  
V
= 135 V  
OR  
V
MIN  
0 V  
D
60%  
MAX  
0 V  
PI-1858-050696  
Figure 11. Determine DMAX - Universal Input  
Step 6. Set ripple current IR to peak current IP ratio KRP  
(see Figure 12)  
A KRP of 0.6 is recommended for 230VAC (compared to 0.4 for  
100/115 VAC and universal input) to accommodate a  
significantly taller and wider leading edge current spike caused  
by the discharge of the drain node capacitance at the higher  
voltage levels.  
IR  
KRP =  
IP  
Step 7. DetermineprimarywaveformparametersIAVG  
,
IP, IR andIRMS  
• StartingwithKRP = 0.4for100/115VACoruniversalinput  
0.6 for 230 VAC  
The average DC current IAVG at low line is simply the input  
power divided by VMIN, where the input power is equal to the  
output power divided by the efficiency.  
for most continuous operation  
• KRP may be increased to higher values for less continuous  
operation  
`
• KRP, by definition, can not be larger than 1.0 and may not  
be set smaller than above values  
P
O
IAVG  
=
η × VMIN  
Manypowersupplydesignengineersprefertousediscontinuous  
mode (KRP =1) design as the control loop is easier to stabilize.  
With TOPSwitch, because of the built-in loop compensation, it  
is possible to use one simple external RC network to stabilize  
the loop independent of operating mode. Setting KRP to the values  
recommended above allows continuous mode operation at low  
input line voltage, minimizing the peak primary current for a  
given output power, and allowing the use of the smallest  
possible TOPSwitch for the application.  
With KRP and DMAX already determined, the shape of the current  
waveform is known. Due to the simple geometry of the  
waveform, the Primary peak current IP, ripple current IR and  
RMS current IRMS can be easily derived as a function of IAVG  
:
A
6/96  
17  
AN-16  
P = IR2MS × RDS(ON)(100°C)  
IR  
DRAIN CURRENT WAVEFORM SHAPES  
• Calculate TOPSwitch switching loss at low line:  
I
R
K
=
< 1.0  
RP  
1
× CXT × (VMAX + VOR )2 × fS  
I
P
P
CXT  
I
P
}
I
2
R
where CXT is the external capacitance at the drain node.  
Continuous Mode  
(a)  
• Calculate junction temperature Tj of TOPSwitch as a  
function of total loss  
K
= 1.0  
RP  
I
P
TJ = 25°C + (P + P ) ×θJA  
IR  
CXT  
I
R
}
• If Tj > 100oC, choose bigger TOPSwitch.  
Discontinuous Mode  
(b)  
• For non-critical applications, refer to AN-14 Table 2  
for TOPSwitch recommendations with practical  
heatsinking.  
PI-1902-61096  
Figure 12. Primary Current Waveform.  
TOPSwitch thermal environment can vary significantly from  
application to application. Fully enclosed lap top adapters with  
no ventilation pose significant limitations on the power that can  
be dissipated inside the box without exceeding acceptable  
surface temperatures on the outside of the box. Heat sinks in  
this application only help to distribute the heat across the  
surface of the box. The actual power capability at a given  
surface temperature is determined largely by the surface area of  
the box. In contrast, a PC power supply has a fan which  
provides forced air cooling. Here a larger heat sink could be the  
answer to higher power dissapation.  
IAVG  
KRP  
IP =  
1−  
× DMAX  
2
IR = IP × KRP  
KR2P  
IRMS = IP × DMAX  
×
− KRP +1  
3
It is therefore important to first estimate the losses in the  
TOPSwitchtoseewhetheritisacceptableinagivenapplication.  
The conduction losses (PIR) at low line tend to be the dominant  
loss factor and can be calculated using the IRMS and the RDS(ON)  
at 100°C from the output characteristic curve in the TOPSwitch  
data sheet. If the losses are unacceptable, a larger TOPSwitch  
with a lower RDS(ON) could be chosen to lower the power  
dissipation.  
Step 8. Select TOPSwitch based on TOPSwitch data  
sheet minimum ILIMIT specification and required IP  
(from Step 7) such that:  
0.9 × minimum ILIMIT ≥ IP  
The minimum value of current limit ILIMIT in TOPSwitch data  
sheet is specified at room temperature. To accommodate the  
slight reduction of this parameter at high temperature, the room  
temperature limit should be derated by 10%. This can be  
accomplishedbydividingtheIP by0.9andcomparingthisvalue  
totheminimumILIMIT inthedatasheet. Thesmallest TOPSwitch  
that has an ILIMIT higher than this value should be selected as the  
first choice for the lowest cost.  
Switching losses at low line due to internal drain capacitance  
are negligible and can be ignored. If significant external  
capacitance CXT is present, the switching losses (PCXT) should  
also be estimated. Even though low line is usually the worst case  
forTOPSwitch losses, itisprudenttoverifythisbycalculatingthe  
conduction and switching losses at high line, especially if there is  
significant external capacitance on the drain.  
Step 9 to Step 10. Check thermal limitation - Use  
bigger TOPSwitch if necessary to reduce power loss  
Once the worst case loss in the TOPSwitch is known, the  
maximum die temperature at worst case ambient (internal  
ambient should be used for enclosed supplies) can be estimated  
using the thermal impedance from die to tab/heat sink of the  
• Calculate TOPSwitch conduction loss at low line:  
A
6/96  
18  
AN-16  
package, ØJC (specified in the TOPSwitch datasheet), and from  
heat sink to ambient, ØCA (usually specified in the heat sink data  
sheet). If a package without a heatsink tab is used, such as an  
8pinDIP, thenatypicaldietoambientthermalimpedance,ØJA,  
for a board mounted part can be found in the data sheet for these  
calculations. Itisrecommendedthatthedietemperaturebekept  
below 100°C under all conditions.  
Step 13. Chose core and bobbin as a function of PO  
based on AN-18, Appendix A, Table 2 and determine  
Ae, Le, AL and BW from core and bobbin catalog  
AN-18 Appendix A provides a table of recommended core  
types for various power ranges. Notice that there are two  
transformer construction types shown in the table. For single  
output designs, a triple insulated secondary simplifies  
transformer construction and allows the use of the smallest size  
core and bobbin for a given output power. Margin winding,  
whichissuitableforbothsingleandmultipleoutputsecondaries,  
will require wider bobbins and therefore, longer/taller cores. If  
there is no specific form factor requirement, it is best to start  
with the smallest EE type core for the power level. EE cores are  
usuallytheleastexpensivetype. Thetwodigitnumberfollowing  
the core type indicates the core size in mm. For 100KHz  
operation, the selection of core material is not very critical.  
TDK PC40 material is a good first choice. Other ferrite  
materials with similar characteristics are available from many  
manufacturers. LowerfrequencycorematerialssuchasPhilips  
3C85 and its equivalents will also work at 100 KHz, and could  
be used if there is a cost advantage.  
Step 11. Check minimum ILIMIT of the selected  
TOPSwitch against required IP. Increase KRP, if  
possible, for least continuous operation.  
Usingcontinuousmodeoperationatlowlinedecreasesthepeak  
current required for a given output power, allowing the use of  
a smaller TOPSwitch. However, if so desired, a trade-off  
between TOPSwitch and core size can be accomplished by  
increasing the KRP value. Larger KRP allows the use of a smaller  
core at the price of a larger TOPSwitch, as larger KRP implies  
less continuous operation and lower inductance LP, but higher  
peak current IP. This is very important when the best suited  
(smallest possible) TOPSwitch that can be chosen for a design  
still ends up with significant extra current capability. It is then  
best to trade this extra current capability for a reduced core size  
by using a higher KRP. In addition to affecting the size of the  
transformer core, KRP also influences supply efficiency. Larger  
KRP results in higher primary RMS current IRMS and higher  
TOPSwitch conduction loss while lower KRP results in lower  
IRMS and lower TOPSwitch loss. For applications with tight  
physical size/weight limitation and/or efficiency requirements,  
an intermediate KRP value can offer the optimum solution  
between cost and performance.  
Once a core has been selected from the catalog, a suitable  
bobbin can be easily identified.  
Manufacturer specified core parameters Ae, Le, AL and bobbin  
parameter BW are usually found in the same catalog.  
Step 14. Set number of primary layers L and number  
of secondary turns NS  
Although this design method is designed to use the highest  
possible KRP once TOPSwitch is first chosen, the flexibility is  
certainly available for other design options. Experienced  
engineers should make their own judgment on KRP value based  
on the specific requirements of their application.  
(see Step 16 to 22)  
Step 15. Calculate number of primary turns NP and  
number of bias turns NB  
(see Step 16 to 22)  
Step 12. Determine primary inductance LP  
Step 16 to Step 22. Check BM, CMA and Lg. Iterate if  
necessarybychangingL, NS,core/bobbinuntilwithin  
specified range  
Because the energy transferred from primary to secondary each  
2
switching cycle is simply the difference between 1/2 x LP x IP  
and 1/2 x LP x (IP - IR)2. The primary inductance LP can be  
expressed as a function of IP, KRP, fS, PO, η and Z:  
In addition to the selection of core and bobbin, a total of nine  
parametersmustbespecifiedintheconstructionofatransformer:  
primary inductance Lp, core gap length Lg, number of turns for  
primaryNP,secondaryNS andbiasNB,wireoutsidediameterfor  
primary OD and secondary ODS, bare conductor diameter for  
primary DIA and secondary DIAS. Because the bias winding  
carries very little current (typically less than 10 mA), the wire  
size of the bias winding is never a problem.  
106 × P  
Z × (1−η) +η  
O
LP =  
×
KRP  
η
IP2 × KRP × 1−  
× fS  
2
η is the efficiency and Z is the loss allocation factor. If Z=1, all  
losses are on the secondary side. If Z = 0, all losses are on the  
primary side. Z is simply the ratio of secondary loss to total loss. If no  
better reference information is available, Z should be set to 0.5.  
Except for LP, the above parameters are all interdependent. A  
good starting point is to pick a number for the secondary turns.  
Using1turn/voltfor100/115VACand0.6turn/voltfor230 VAC  
A
6/96  
19  
AN-16  
or universal inputs is a good assumption. As an example, for a  
115VAC input and an output voltage VO of 15V plus the  
rectifier forward drop VD of 0.7V, a 16 turn secondary would  
be used as the initial value. The primary number of turns NP is  
related to the secondary number of turns NS by the ratio  
between VOR and VO + VD  
second layer if there is only one existing layer and/or by using  
a larger core/bobbin and/or a smaller NP. On the other hand, a  
CMA greater than 500 would indicate that a smaller core/  
bobbin and/or a larger NP could be used.  
Note that in the AN-17 spreadsheet, DIA is actually derived  
from OD using an empirical equation. A practical wire size,  
AWG(AmericanWireGauge),isdeterminedaccordingtoDIA  
(see AN-18 Appendix A, Table 2 for wire size information).  
CMA is then calculated from AWG.  
VOR  
NP = NS ×  
VO + VD  
Anothercriticalparameterthatmustbecheckedisthemaximum  
flux density in the core (BM ).  
where VOR is the reflected output voltage, VO is the output  
voltage and VD is the output rectifier forward voltage drop.  
Similarly, the number of bias winding turns NB can be derived  
from  
100 × IP × LP  
BM =  
NP × Ae  
VB + VDB  
NB = NS ×  
Ae is the effective cross sectional area of the core.  
VO + VD  
If BM is greater than 3000 Gauss, either the core cross sectional  
area (core size) or NP must be increased to bring it within the  
2000 to 3000 range. On the other hand, if BM is less than  
2000 Gauss, a smaller core or fewer turns on the primary can be  
used.  
where VB isthe biasvoltage andVDB isthe biasrectifierforward  
voltage drop.  
From the core/bobbin size, it is possible to determine the  
outside diameter of the primary wire OD in mm that is required  
to accommodate the primary turns in one or two full layers  
allowing for margins as appropriate.  
In addition to BM, the core gap length Lg required to generate  
inductance LP with number of primary turns NP must also be  
checked:  
BWE  
OD =  
NP2  
1000 × LP AL  
1
NP  
Lg = 40 × π × Ae ×  
−
BWE is the effective bobbin width, which takes into account  
physical bobbin width BW, margins M (all in mm), and the  
number of winding layers L:  
The core cross sectional area Ae and ungapped effective  
inductance AL can be found from the data sheets for the core. Lg  
is usually incorporated as an air gap ground into the center leg  
of the core and needs to be at least 51 µm or (2 mils) for  
manufacturability. If Lg is less than 51 µm, once again the core  
size or NP must be increased.  
BW = L × BW − (2 × M)  
[
]
E
Thecloseststandardmagnetwiregaugethatislessthanorequal  
to this diameter can be selected. Determine the bare conductor  
diameter DIA of this wire gauge using information from a wire  
table. The next step is to find out if this conductor size is  
sufficient for the maximum IRMS. The current capacity for  
magnet wire is specified in terms of “Circular mils per Amp” or  
CMA, which is the inverse of current density:  
One other parameter always required by transformer  
manufacturer is the gapped core effective inductance, ALG,  
which can be determined only after NP is fixed:  
LP  
ALG = 1000 ×  
NP2  
π
1.27 × DIA2 ×  
2
1000  
As can be seen, the transformer design is a highly iterative  
process in itself. When NP is changed, NS and NB will change  
according to ratios already established. Similarly, any change  
in core size requires a recalculation of CMA, BM and Lg to make  
sure that they are within the specified limits.  
4
CMA =  
×
IRMS  
25.4  
If the CMA is less than 200, a larger gauge wire is needed to  
handle the current. This could be accommodated by adding a  
A
6/96  
20  
AN-16  
Step 23. Determine secondary parameters ISP, ISRMS  
IRIPPLE, DIAS, ODS  
,
winding consisting of NS turns of two parallel strands of  
26 AWG will be a good choice.  
The secondary peak current ISP can be derived from the primary  
peakcurrentIP andtheturnsratiobetweenprimaryandsecondary  
NP/NS  
Note that if triple insulated wire is to be used for secondary, the  
insulatedwirediameterisactuallylargerthanDIAS bytwicethe  
thickness of the insulator. Therefore, the maximum outside  
diameter ODS (in mm) must be calculated:  
NP  
ISP = IP ×  
NS  
BW − (2 × M)  
ODS =  
NS  
The KRP of the secondary is always identical to that of the  
primary, since it is only a reflected version of the primary  
current with duty cycle (1-D). Therefore, the secondary RMS  
currentISRMS canbeexpressedinamannersimilartotheprimary  
RMS current, only with DMAX replaced by (1-DMAX).  
A triple insulated wire should be specified with a conductor  
diameter equal to or greater than DIAS and an insulated outside  
diameter equal to or less than ODS.  
Step 24. Determine maximum peak inverse voltages  
PIVS, PIVB for secondary and bias windings.  
KR2P  
ISRMS = ISP × (1− DMAX ) ×  
− KRP +1  
The peak inverse voltage across the secondary rectifier diode is  
given by:  
3
NS  
IRIPPLE istheRMSripplecurrentoftheoutputcapacitor.Because  
of current conservation, it is found that:  
PIV = VO + VMAX  
×
S
NP  
IRIPPLE = I2 − I2  
Similarly, the peak inverse voltage across the bias rectifier  
diode is given by:  
SRMS  
O
IO is the power supply output current which can be calculated,  
if not already specified, as  
NB  
PIVB = VB + VMAX  
×
NP  
P
O
IO =  
VO  
Step 25. Select clamp Zener and blocking diode for  
primary clamping based on input voltage and VCLO  
With the secondary RMS current ISRMS available, the minimum  
secondary wire diameter DIAS (in mm), can be calculated as  
follows:  
(see Step 4)  
Step 26. Select output rectifier  
4 × CMA × ISRMS 25.4  
The peak inverse voltage across the secondary diode PIVS is  
calculated in Step 24. The diodes should be chosen with a  
reverse voltage rating VR equal to or greater than 1.25 X PIVS  
to keep the PIVS at no more than 80% of the diode VR rating.  
DIAS =  
×
1.27 × π  
1000  
Note that in the AN-17 spreadsheet, a practical wire size,  
AWGS, is derived from primary current capacity CMA and  
secondary RMS current ISRMS using an empirical equation.  
DIAS is then determined from AWGS.  
The rule of thumb on the diode current rating is to choose one  
with rated DC current of at least three times the maximum  
output DC current.  
If the required secondary wire diameter turns out to be larger  
than that of the 26 AWG wire which corresponds to twice the  
skin depth at 100 KHz, a parallel configuration of windings  
using a gauge equal to or smaller than 26 AWG should be used  
to provide the same effective cross sectional area. The parallel  
windings must have identical number of turns equal to NS. For  
example, if the equation above indicates a 23 AWG wire, a  
Schottky diodes are recommended for VR less than 45V which  
would correspond to low output voltages such as 5V or 3.3V.  
ForVR requirementsthatarehigherthan45V,ultrafastrecovery  
PN diodes should be used for the lowest cost. (See Table 8 for  
recommended diodes.)  
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Step 27. Select Output capacitor  
Step 32. Select Control pin capacitor and series  
resistor  
ESR is the most important parameter for output filter capacitor  
selection. Capacitor ESR directly determines the output ripple  
voltage of the power supply and the ripple current rating of the  
capacitorwhiletheactualcapacitancevalueonlyaffectscontrol  
loop bandwidth. Below 35V, ESR is mainly determined by  
capacitorcasesize. ConsidertwoNichiconPLseriescapacitors:  
1500µF/6.3Vand390µF/35V. Bothcapacitorshaveacasesize  
of 10 mm diameter and 25 mm length, and both have the same  
ESR of 55 mΩ. To keep control loop bandwidth high, the  
smallercapacitance,highervoltageratingcapacitorispreferred.  
A 47 µF, 10V low cost standard grade electrolytic capacitor  
across the Control pin and Source pin of the TOPSwitch takes  
care of loop compensation for all types of feedback  
configurations. Low ESR capacitors should not be used for this  
purpose, as the ESR resistance of the standard grade capacitor  
(2 Ω typical) improves the loop stability by introducing a zero.  
In fact, a 6.2Ω resistor in series with this capacitor is  
recommended to improve phase margin in designs that either  
have excessive gain in the secondary (such as the TL431 circuit  
shown in Figure 6), or a KRP value of less than one (continuous  
mode).  
Ripple current is typically specified at 105oC ambient which is  
much higher than the ambient temperature required in most  
applications. Therefore, it is possible to operate the capacitor at  
higher ripple currents determined by a multiplier factor from  
the capacitor data sheet.  
Step 33. Select feedback circuit components  
• Primary feedback: Refer to RD1  
• Opto/Zener feedback: Refer to ST202A  
• Opto/TL431: Refer to ST204A  
• Select opto-coupler with CTR between 50% and 200%  
(Refer to AN-14, Table 3)  
Actual ripple current of the output capacitor can be calculated  
as follows:  
IRIPPLE = IS2RMS − IO2  
Step34. Selectbridgerectifierbasedoninputvoltage  
VACMAX and input RMS current IACRMS  
where ISRMS is the secondary winding RMS current and IO is the  
DC output current.  
Maximumoperatingcurrentfortheinputbridgerectifieroccurs  
at low line:  
Step 28 to Step 29. Select Output post filter L, C  
P
O
If the measured switching ripple voltage at the output capacitor  
is higher than the required specification, an LC post filter  
consisting of a 2.2 to 4.7µH inductor or ferrite bead (only for  
powerlevelsbelow5W)witha120uF/35V,lowESRelectrolytic  
capacitor is recommended. This will provide a lower cost  
solution compared to increasing the capacitance value and/or  
lowering the ESR of the main output filter capacitor.  
IACRMS =  
η × VACMIN × PF  
PF is the power factor of the power supply. Typically, for a  
powersupplywithacapacitorinputfilter,PFisbetween0.5and  
0.7. Use 0.5 if there is no better reference data available.  
Select the bridge rectifier such that:  
The output post filter, to a first order, is independent of output  
power except that the DC voltage drop across the inductor may  
be a concern at high currents. Inductors with larger gauge wire  
and higher current rating solve this problem.  
• ID ≥ 2 x IACRMS, where ID is the rated RMS current of the  
bridge rectifier  
• VR ≥ 1.25 x 1.414 x VACMAX; where VR is the rated reverse  
voltage of the rectifier diode  
Step 30. Select bias rectifier  
Step 35. Design complete  
Bias rectifier selection is similar to output rectifier selection  
with the exception that since the bias winding carries very little  
current (typically less than 10 mA), the considerations for  
current capability and very fast recovery no longer apply.  
Following the step-by-step procedure completes the design of  
a basic TOPSwitch flyback converter. Once built, the power  
supply should be fully functional and capable of delivering  
maximum rated output power at minimum input line voltage,  
while meeting all specifications. Minor adjustments may be  
necessary to center the output voltage.  
Step 31. Select bias capacitor  
Because of the low voltage and the minimal power required at  
the bias output, a 0.1 uF, 50V ceramic capacitor always meets  
the requirement.  
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Issues Beyond the Design Method  
Issues outside the basic converter requirements are beyond the  
scope of this application note. However, design guidelines for  
various issues are available in the following documentation:  
• Constant current/power output  
• PC board layout  
• Transformer design  
• Transformer construction  
• Efficiency  
: DN-14  
: AN-14  
: AN-17  
: AN-18  
: AN-19  
: AN-15  
: AN-20  
• EMI and safety  
• Transient  
Application specific requirements such as constant current  
and/or constant power outputs (DN-14), input under voltage  
protection, soft start etc. (refer to AN-14) are usually  
implementedbyaddingminimalcircuitrytothebasicconverter.  
General design guidelines for EMI, safety and input transient  
are provided in AN-15 and AN-20 respectively. However, the  
optimum solution for any particular design can only be found  
through experimentation.  
Transformer construction techniques are very critical in the  
successful development of a TOPSwitch flyback. AN-18  
provides practical guidelines that should be followed carefully  
tominimizeparasiticssuchasleakageinductance,inter-winding  
capacitance etc.  
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AN-16  
between primary and secondary components to satisfy the  
requirements of domestic and international safety regulations.  
Thisisolation,alongwithanynecessaryvoltagetransformation,  
requires a power transformer. Most switching power supplies  
also need an inductor as the energy storage component and also  
as part of the low pass filter required to transform the pulse  
width modulated switching waveform into a DC output. The  
flyback topology is attractive for low power isolated switching  
power supplies because the transformer is combined with the  
inductor in a single magnetic component providing energy  
storage, isolation, and voltage transformation. As compared to  
other topologies such as the forward converter, the flyback has  
the fewest magnetic components and the lowest parts count,  
resulting in the lowest cost. The flyback topology retains these  
advantages at power levels up to 100 watts, or output currents  
up to 10 amperes. Component stress levels above 100 watts or  
10 amperes output current require the use of more expensive  
components, allowing other topologies to become more cost  
effective.  
Appendix A  
TOPSwitch Flyback Fundamentals  
This appendix explains the operation of a flyback power supply  
using the TOPSwitch power integrated circuit. TOPSwitch is  
a monolithic device combining a high voltage power MOSFET  
switch with all the analog and digital control circuitry required  
toimplementisolated,regulated,andprotectedswitchingpower  
supplies. Designing the power supply is greatly simplified  
because few external components are required. The high  
switching frequency of 100 KHz reduces the size of the power  
supplybyallowingtheuseofsmallerenergystoragecomponents.  
TheTOPSwitchwasdesignedforuseinisolatedpowersupplies  
or DC to DC converters. Power levels up to 50 Watts can be  
delivered from AC voltages of 85 to 265 VAC, or 100W with  
a 195 to 265 VAC input range. Operation from lower input  
voltages is also possible with reduced levels of output power.  
The flyback power supply is described in detail. Ideal and non-  
ideal circuit operation is explained. The difference between the  
discontinuous and continuous mode of operation is discussed.  
The benefits of high frequency operation are presented. Other  
types of power supplies using both linear and switching  
techniques are examined and compared with the flyback  
topology.  
Another important advantage of the flyback topology is that a  
feedback voltage proportional to the output voltage can be  
obtained directly by adding a “feedback” winding to the power  
transformer. This means that secondary side regulation can be  
accomplished on the primary side of the power supply without  
using an optocoupler or similar isolation device between the  
primary and secondary circuitry. Single or multiple, higher or  
lower, positive or negative output voltages are primarily a  
function of the construction of the power transformer.  
The Flyback Power Supply  
The flyback topology, shown in Figure 1, is recommended for  
off-line, isolated, power supply applications. The flyback  
supply has a low parts count, wide input voltage range, inherent  
feedback voltage sensing, single or multiple output voltage  
capability, output voltages that can be higher or lower than the  
input voltage, and ability to provide both positive and negative  
voltages.  
Comparison to Other Techniques  
Alternatives to flyback power supplies for low power  
applications include linear supplies and other switching  
topologiessuchasthebuckconverterandtheforwardconverter.  
These are briefly examined below. Additional information can  
be found in some of the references listed at the end of this  
appendix.  
Almost all off-line switching power supplies require isolation  
D2  
Linear Power Supplies  
V
T1  
O
The linear power supply is characterized by the use of an AC  
line frequency (50-60 Hz) transformer, rectifier, filter, and  
linearregulatorasshowninFigure2. Thistypeofpowersupply  
is inexpensive and reliable but suffers from the following  
disadvantages:  
R
C1  
L
N
S
V
IN  
N
P
TOPSwitch  
• Largest size  
• Highest weight  
DRAIN  
SOURCE  
CONTROL  
• Poorest efficiency  
• Narrow input voltage range  
FEEDBACK  
PI-1615-021296  
Figure 1. Basic Flyback Converter Circuit.  
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Switching Power Supplies  
60 Hz  
TRANSFORMER  
LINEAR  
REGULATOR  
There are many different switching power supply topologies  
available. Thebuck,boost,andforwardconvertersaredescribed  
below. Multiswitch and resonant converters are also briefly  
discussed.  
AC  
IN  
V
O
Buck Converter - The buck converter, shown in Figure 3, is  
useful for stepping down from a higher voltage to a lower  
voltage. The key points are:  
PI-1735-021296  
Figure 2. Linear Regulator Circuit.  
• Not isolated  
• High side switch requires level shift or bootstrap circuit to  
drive  
V
V
IN  
O
• Limited to approximate 10:1 conversion range by duty  
cycle requirements  
• Provides only down converted, positive output voltages  
R
L
Boost Converter - The boost converter, shown in Figure 4, is  
useful for stepping up from a lower voltage to a higher voltage.  
The key points are:  
CONTROL  
• Not isolated  
FEEDBACK  
• Limited to approximate 10:1 conversion range by duty  
cycle requirements  
• Provides only up converted, positive output voltages  
PI-1788-021296  
Figure 3. Buck Converter Circuit.  
ForwardConverter -Theforwardconverter, showninFigure  
5,isanisolatedversionoftheBuck. Singleormultiple,positive  
or negative, higher or lower output voltages are available by  
transformer design. This topology can be useful for output  
power of 100 W to 300 W. The key points are:  
V
V
IN  
O
R
L
CONTROL  
• Inductor required for each output voltage  
• Extra diode required for each output voltage  
• Additional isolated feedback circuit required  
Multiple Switch Converters - Multiple switch converter  
topologies include the push-pull, half bridge, full bridge, two  
transistor flyback, and two transistor forward converters. All  
these circuits require at least one additional power switch and  
aremuchmorecomplexandcostly. Theyareusedtoimplement  
power supplies ranging from 200 watts to several kilowatts and  
are inappropriate for low power, low cost designs.  
FEEDBACK  
PI-1789-021296  
Figure 4. Boost Converter Circuit.  
V
R
L
IN  
Resonant and Quasi-Resonant Converters - Resonant  
converters are switching power supplies that use resonant tank  
circuits to process power with sinusoidal waveforms rather  
than the pulse width modulated quasi-square waves employed  
by conventional switching power supplies. Quasi resonant  
power supplies are switching power supplies that use resonant  
circuitstosmooththeturnonandturnoffedgesinthe switching  
waveform. In general, resonant and quasi-resonant converters  
are used at frequencies considerably higher than 100 KHz, and  
require more components than the traditional quasi-square wave  
CONTROL  
FEEDBACK  
WITH ISOLATION  
PI-1720-120595  
Figure 5. Forward Converter Circuit.  
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AN-16  
switching power supply. Peak voltage or current stress levels  
arehigherthanquasisquarewavepowerconverters, depending  
onwhetherazero-voltageswitchingorazero-currentswitching  
topology is used. The most effective resonant converters use  
both high side and low side switches, adding to circuit  
complexity. Resonant converters are not cost effective at low  
output power levels.  
into the load circuit, supplying current to the load RL and  
replenishing the charge depleted from C1 during the on time.  
The initial value of the secondary current at the instant the  
TOPSwitch turns off will be equal to IP x NS/NP, where IP is the  
peak value of IPRI at the end of TOPSwitch on time and NP is the  
number of primary turns and NS is the number of secondary  
turns. The secondary current decays from its initial value  
according to Equation (2).  
Flyback Theory  
IP × NP (VO + VD2 ) × tOFF × NP2  
Basic Flyback Operation  
ISEC  
=
−
NS  
NS2 × LP  
A basic flyback power supply circuit utilizing TOPSwitch is  
shown in Figure 1. Transformer T1 is used both for energy  
storage, output isolation, and output voltage transformation.  
When the TOPSwitch is on, secondary diode D2 is reverse  
biased,andcurrentrampsupinthetransformerprimarywinding  
according to the equation  
(ISEC ≥ 0)  
(2)  
VO istheoutputvoltageofthesupply, VD2 istheforwardvoltage  
drop of D2, and tOFF is the TOPSwitch off time. If the secondary  
current decays to zero during the off time of the primary switch,  
the output current is then supplied by the output capacitor C1.  
There are two distinct modes of flyback supply operation,  
depending on the value of ISEC at the end of the TOPSwitch off  
time. If ISECdecaystozeroatorbeforetheendofthe TOPSwitch  
offtime,thesupplyisrunninginthediscontinuousmode. If ISEC  
is greater than zero at the end of the off time, the supply is  
running in the continuous mode of operation.  
(V − VDS(ON) ) × tON  
IN  
IPRI = II +  
(1)  
LP  
IPRI is the primary current in amperes, II is the initial value of the  
primarycurrentinamperes,VIN istheDCinputvoltageafterthe  
bridge, VDS(ON) is the drain to source voltage drop across the  
TOPSwitchoutputMOSFET,tON istheontimeoftheTOPSwitch,  
and LP is the transformer primary inductance in Henries. Since  
the transformer is isolated from the output load circuit by the  
reverse biased D2, energy is supplied to RL from the output  
capacitor C1 during the TOPSwitch on time.  
Ideal Model (Discontinuous Mode)  
Therearethreedistinctintervalsofcircuitoperationforflyback  
power supplies operating in the discontinuous mode as shown  
in Figure 6.  
When the TOPSwitch turns off, the magnetic flux in the  
transformercorestartstodecay,andthepolarityofthesecondary  
winding is reversed. D2 turns on, and the energy stored in the  
transformer during the on time of the TOPSwitch is discharged  
The first interval (1) of operation occurs when the TOPSwitch  
is on. Current IPRI ramps up linearly in the transformer primary  
winding, causing a magnetic field to build in the transformer  
V
+V  
IN OR  
V
D2  
OR  
+
-
V
IN  
V
I
DRAIN  
+
PRI  
I
SEC  
V
V
R
C1  
IN  
O
L
0
-
Interval  
1
2
3
I
+
P
I
PRI  
DRAIN  
SOURCE  
V
DS  
CONTROL  
(ON)  
-
I
SEC  
PI-1616-021496  
Figure 6. Ideal Flyback Converter Waveforms - Discontinuous Mode.  
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AN-16  
core. The drain to source voltage VDS(ON) across TOPSwitch is  
nearly zero during this interval. The output diode prevents  
current flow in the secondary due to the transformer dot  
polarity. Since the transformer secondary is isolated from the  
output by the reverse biased diode D2, current is supplied to the  
output from C1.  
flows in the primary or secondary of the transformer (which  
defines the discontinuous mode of operation). Note that the  
draintosourcevoltageacrosstheTOPSwitchhasdecayedtothe  
level of the input voltage. Since the stored energy of the  
transformerhasdecayedtozero, theoutputloadcurrentisagain  
supplied by output capacitor C1.  
The second interval (2) of operation starts when TOPSwitch  
turns off. The energy stored in the magnetic field of the  
transformer causes the voltage across both the primary and  
secondary windings to reverse polarity. In an ideal circuit the  
primary current IPRI instantly stops flowing while the secondary  
current ISEC instantly starts flowing (it will be shown later how  
important it is to consider non-ideal behavior). The voltage  
across the secondary winding is equal to the sum of the output  
voltage and diode forward voltage. The secondary voltage is  
“reflected” back through the transformer turns ratio to the  
primary winding. Note that the drain to source voltage across  
the TOPSwitch during this interval of operation is equal to the  
sum of the reflected output voltage VOR and the input voltage  
VIN. This reflected voltage must be taken into account when  
selecting the transformer turns ratio to avoid excessive voltage  
stress on TOPSwitch. The reflected voltage can also be used to  
indirectly sense the output voltage of the supply from the  
primary side of the transformer through a bias or control  
winding referenced to the primary return, making primary side  
control of the supply possible.  
The energy delivered to the load each cycle by the transformer  
is given by  
1
E = × LP × IP2 ×η  
2
thus the output power is defined by  
1
P = × LP × IP2 ×η × fS  
O
2
where fS is the operating frequency of the power supply, and η  
istheefficiency. SubstitutingtheexpressionofEquation(1)for  
IP (with II = 0 and VDS(ON) = 0), and defining tON as D/fS, where  
Disthedutycycle,andfS istheTOPSwitchoperatingfrequency.  
One obtains the expression  
V2 × D2 ×η  
IN  
P =  
(3)  
O
2 × LP × fS  
The energy stored in the primary inductance of the transformer  
during the first interval of operation supplies current to the load  
circuit during the second interval of operation and replenishes  
the charge depleted from output capacitor C1 during the first  
and third intervals.  
In a power supply operating in the discontinuous mode, the  
controller will adjust the duty cycle of the primary switch to  
deliver enough power to the load to maintain the desired output  
voltage. The duty cycle is a function of both the input voltage  
and the output load.  
The third interval (3) of operation occurs when the magnetic  
field within the core has decayed to zero (ISEC = 0). No current  
Ideal Model (Continuous Mode)  
Refer to Figure 7 for the characteristic waveforms for the  
continuousmodeofoperation. Thereferencecircuitisthesame  
as in Figure 6.  
V
V
+V  
IN OR  
The secondary current ISEC does not decay completely to zero  
as in the discontinuous mode, so that the third interval of  
operation (3)doesnotexist. Theprimarycurrent IPRI startswith  
a current step equal to the final value of the secondary current  
ISEC reflected back through the transformer turns ratio. The  
drain to source voltage across TOPSwitch at the instant of turn  
on is also different since the third interval has been eliminated  
as previously discussed. The reflected output voltage state  
persists for the balance of the off cycle until TOPSwitch turns  
on again.  
IN  
0
V
DRAIN  
1
2
Interval  
I
PRI  
I
SEC  
In order to maintain a constant output voltage, the amount of  
current ramped up in the primary inductance during the on time  
must be balanced by the current ramped down during the off  
PI-1736-021496  
Figure 7. Ideal Flyback Converter Waveforms - Continuous Mode.  
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AN-16  
Leakage  
Spike  
Voltage  
V
P
V
V
+V  
IN OR  
L
I
KP  
L
D2  
KS  
IN  
+
-
V
DRAIN  
+
PRI  
I
SEC  
V
C1  
V
R
IN  
O
L
0
Interval  
1
2
3
-
I
PRI  
+
C
C
=
DRAIN  
SOURCE  
DRAIN  
+C  
Slope = di/dt  
V
DS  
CONTROL  
OSS XT  
-
I
SEC  
Crossover  
Interval  
PI-1617-021496  
Figure 8. Non-ideal Flyback Converter Waveforms - Discontinuous Mode.  
time. This means that  
continuous and discontinuous operation.  
This equation is derived by assuming that the integral of the  
output current of the power supply over the entire switching  
cycleisexactlyequaltotheintegralofthetransformer secondary  
output current over the off time period. This means that during  
the off time, the transformer delivers exactly enough energy to  
balancetheenergydeliveredtotheloadovertheentireswitching  
cycle, with no energy left over, and runs out exactly at the end  
of the off time.  
(V − VDS(ON) ) × D  
(VO + VD2 ) × (1− D)  
IN  
=
(4)  
NS  
LP × fS  
× LP × fS  
NP  
Solving for VO, one obtains the expression  
If the output current is greater than the right hand side of  
Equation (6) , the supply is operating in the continuous mode.  
If the output current is less than or equal to the right hand side  
of the equation, the supply is operating in the discontinuous  
mode. A smaller transformer primary inductance will give up  
the energy stored in the magnetic field at a faster rate and result  
indiscontinuousconductionmode. Conversely,alargerprimary  
inductancewillnotgiveupalltheenergystoredinthecoreeach  
cycle and operate in continuous mode. If the load current is  
reduced below IOB, the supply will run in the discontinuous  
mode. Also, if the input voltage is increased for a given load,  
the supply can transition to the discontinuous mode, as IOB  
increases with increasing input voltage.  
D
NS  
VO = (V − VDS(ON) ) ×  
×
− VD2 (5)  
IN  
1− D NP  
As long as the power supply is running in the continuous mode,  
it can be seen from the above expression that there is no direct  
dependence of the output voltage on the output loading. To a  
first order, the duty cycle of the supply will remain constant as  
the load is changed, and the initial value of the primary current  
waveform will change instead.  
Theprimaryinductanceofthepowertransformer,outputloading,  
and the TOPSwitch off time determine continuous or  
discontinuous operation. This dependence is shown in  
Equation(2). Theboundary ofcontinuousversusdiscontinuous  
operation is defined by the equation  
Non-ideal Model (Discontinuous and Continuous  
Mode)  
The circuit for the non-ideal flyback power supply and the  
associated waveforms for the discontinuous and continuous  
operating modes are shown in Figures 8 and 9. The non-ideal  
flyback has three additional parasitic circuit elements: two  
inductors and one capacitor. The inductor LKP is the leakage  
inductance of the primary winding on the power transformer.  
The inductor LKS is the leakage inductance of the secondary  
V2 × VO  
IN  
IOB =  
(6)  
2
NS  
NP  
2 × fS × LP ×  
× V + VO  
IN  
Where IOB is the output current at the boundary between  
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AN-16  
winding on the power transformer. The capacitor CDRAIN is the  
sumofCOSS andCXT whicharetheTOPSwitchoutputcapacitance  
and the transformer winding capacitance, respectively. These  
parasitic circuit elements are present in any real-life flyback  
power supply circuit, and greatly affect supply performance.  
interval. The decaying primary current ends up flowing into  
COSS and CXT which charge up to a peak voltage VP. This peak  
voltage, caused by leakage inductance, will be referred to as the  
“leakage spike”. In a practical TOPSwitch flyback supply, the  
leakagespikeshouldbeclampedtoavaluebelowtheTOPSwitch  
breakdown voltage rating.  
As previously shown, the discontinuous mode circuit has three  
intervals of operation per switching cycle (see Figure 8). The  
impact on circuit operation of the parasitic circuit elements in  
each of three intervals of operation is discussed below.  
During interval (3) of operation, the reflected output voltage  
goes to zero. The transformer magnetic field has given up all  
theenergystoredduringthefirstinterval. TheTOPSwitchdrain  
to source voltage makes a transition from the level equal to the  
sum of the reflected output voltage VOR and input voltage VIN  
down to a level equal to the input voltage VIN alone. This  
transition excites the resonant tank circuit formed by the stray  
capacitance and the primary inductance to create a decaying  
oscillatorywaveform, whichpersistsuntiltheTOPSwitchturns  
on again. This waveform “modulates” the voltage on (and the  
amount of energy stored in) COSS and CXT, determining the  
power loss when TOPSwitch turns on at the beginning of the  
next cycle.  
Inthefirstinterval(1)theTOPSwitchturnson,dischargingCOSS  
and CXT. The energy stored by these capacitances at the end of  
thepreviouscycleisdissipatedintheTOPSwitchatthebeginning  
of the turn on interval. This dissipated energy is proportional to  
the square of the voltage on the parasitic capacitances. Because  
of this effect, large values of parasitic capacitance can  
dramatically lower the power supply efficiency, especially at  
high input voltage. Leakage inductance has little effect during  
the turn on interval, since the transformer has no stored energy,  
and the initial value of the secondary output current is zero.  
Inthecontinuousmodeofoperation,thesameparasiticelements  
are present as in the discontinuous mode. In addition, the non-  
ideal aspects of the output rectifier characteristic become  
important. An ideal rectifier has no forward voltage drop, and  
switches infinitely fast. An actual diode has a finite forward  
voltagedrop,andtakesafinitetimetoswitchoff. APNjunction  
In interval (2) of operation, the TOPSwitch turns off. The  
energy stored in the transformer magnetic field during the  
previous interval is now transferred to the secondary circuit. A  
problemthatarisesduringthistransferisthatleakageinductances  
LKP and LKS are both trying to oppose changes in current flow.  
LKP is trying to maintain primary current flow, and LKS is trying  
to block secondary current flow. There is a “crossover region”  
duringwhichtheprimarycurrentrampsdownandthesecondary  
currentrampsup. Theprimarycurrentrampsdowntozerowith  
a slope determined by the value of leakage inductance and  
circuit voltage levels. The secondary current ramps up to the  
final value with a slope determined by the value of leakage  
inductance and circuit voltage levels. The big problem is that  
the primary current must continue to flow during this crossover  
diode has a finite reverse recovery time ( t ) due to the fact that  
rr  
the minority charge carriers must be swept from the junction by  
the applied reverse voltage before the diode junction can  
reversebiasandswitchtotheoffstate. InthecaseofaSchottky  
diode,thisfiniterecoverytimeiscausedbyjunctioncapacitance.  
This recovery time ( t ) is associated with a reverse recovery  
rr  
current spike that persists until the diode switches off. This  
current spike causes reverse power dissipation in the output  
rectifier, and loads down the TOPSwitch during its turn on  
transition. The amplitude and duration of this current spike is  
dependent on the speed of the diode. For 100 KHz power  
supplies, ultrafast diodes (trr < 50 nsec) are recommended. Use  
of slower diodes will cause a loss in efficiency due to excessive  
reverse recovery power dissipation, and can result in thermal  
runaway of the output rectifier diode.  
Leakage  
Spike  
Voltage  
V
P
V +V  
IN OR  
V
IN  
V
DRAIN  
Non-ideal operating waveforms of a continuous mode flyback  
converter are shown in Figure 9. During the interval (1) of  
operation, TOPSwitch turns on while current is still flowing in  
the transformer secondary. This means that the drain voltage at  
the instant of turn on is equal to the sum of the input voltage and  
the secondary voltage reflected back through the transformer  
turns ratio. This results in higher TOPSwitch turn-on power  
dissipation than in the discontinuous mode, due to the extra  
energy stored in the parasitic capacitances of the primary  
circuit. In addition, the current in the secondary leakage  
inductance must be discharged before the secondary output can  
be turned off. This results in a turn on current crossover while  
0
Interval  
1
2
I
PRI  
Slope = di/dt  
D1  
Reverse  
Recovery  
Current  
Spike  
I
SEC  
Crossover  
Interval  
PI-1618-021496  
Figure 9. Non-ideal Flyback Converter Waveforms - Continuous  
Mode.  
A
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29  
AN-16  
the secondary current ramps down and the primary current  
rampsup. Oncethesecondaryleakageinductanceisdischarged,  
the output rectifier D2 is reverse biased, and the charge carriers  
in the diode junction are withdrawn, resulting in a reverse  
recovery current spike that is reflected to the primary and  
appears at the leading edge of the primary current waveform.  
Dependingonthediodecharacteristics,thisinitialcurrentspike  
can be comparable in amplitude or higher than the final value  
of the primary current. This can result in spurious operation of  
a current limit protection circuit. The TOPSwitch provides  
built-inleadingedgecurrentlimitblankingtopreventtheinitial  
current spike from spuriously triggering the current limit  
protection circuitry.  
References  
1. Power Integrations, Power Integrated Circuit Data Book  
2. Ralph E. Tarter, Solid State Power Conversion Handbook,  
New York, John Wiley & Sons, Inc., 1993  
3. AbrahamI. Pressman,SwitchingPowerSupplyDesign(2nd  
ed.), New York, McGraw-Hill, Inc., 1991  
4. ApplicationInformation472, C. vanVelthooven, Properties  
of DC-to-DC converters for switched-mode power supplies,  
Philips Components, 1975 (Ordering Code 9399 324 47201)  
When TOPSwitch turns off, operation in the continuous mode  
is similar to that of the discontinuous mode. The primary and  
secondary current experience a crossover region due to the  
effectsofthetransformerleakageinductance. Thisgivesriseto  
a primary leakage spike, as in the discontinuous operating  
mode. The TOPSwitch drain to source voltage rises to the sum  
of the input supply voltage and the output voltage reflected  
back through the transformer turns ratio. Unlike the  
discontinuous mode model, this reflected voltage persists until  
TOPSwitch turns on again, so that there is no interval (3) where  
the reflected secondary voltage decays to zero.  
5. Col. William McLyman, Transformer and Inductor Design  
Handbook, New York, Marcel Dekker, Inc., 1978  
6. Col. William McLyman, Magnetic Core Selection for  
Transformers and Inductors, New York, Marcel Dekker, Inc.,  
1982  
7. Philips Components, Ferroxcube Magnetic Design Manual,  
Bulletin 550, 1971  
8. Ferdinand C. Geerlings, “SMPS Power Inductor and  
Transformer Design, Part 1”, Powerconversion International,  
November/December 1979, pp. 45-52  
9. FerdinandC. Geerlings,“SMPSPowerInductorDesignand  
Transformer Design, Part 2”, Powerconversion International,  
January/February 1980, pp. 33-40  
10. Philips Semiconductors, Power Semiconductor  
Applications, 1991, (Ordering Code 9398 651 40011)  
11. TechnicalInformation042,Usingveryfastrecoverydiodes  
on SMPS, Philips Components, 1978 (Ordering Code 9399  
450 34201)  
12. BrianHuffman,“BuildReliablePowerSuppliesbyLimiting  
Capacitor Dissipation”, EDN, March 31, 1993, pp. 93-98  
13. Jon Schleisner, “Selecting the Optimum Voltage Transient  
Suppressor”, General Instrument Data Book, 11th Edition,  
pp. 629-634  
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Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.  
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it  
convey any license under its patent rights or the rights of others.  
PILogoand TOPSwitchareregisteredtrademarksofPowerIntegrations, Inc.  
©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086  
AMERICAS  
WORLD HEADQUARTERS  
Power Integrations, Inc.  
477 N. Mathilda Avenue  
Sunnyvale, CA 94086  
USA  
EUROPE & AFRICA  
Power Integrations (Europe) Ltd.  
Mountbatten House  
Fairacres  
For Your Nearest Sales/Rep Office  
Please Contact Customer Service  
Phone: 408•523•9265  
Fax:  
408•523•9365  
Windsor SL4 4LE  
Main:  
408•523•9200  
United Kingdom  
Customer Service:  
Phone: 44•(0)•1753•622•208  
Phone: 408•523•9265  
Fax:  
44•(0)•1753•622•209  
Fax:  
408•523•9365  
APPLICATIONS HOTLINE  
World Wide 408•523•9260  
JAPAN  
ASIA & OCEANIA  
Power Integrations, K.K.  
Keihin-Tatemono 1st Bldg.  
12-20 Shin-Yokohama 2-Chome, Kohoku-ku,  
Yokohama-shi, Kanagawa 222  
Japan  
For Your Nearest Sales/Rep Office  
Please Contact Customer Service  
Phone: 408•523•9265  
APPLICATIONS FAX  
Americas  
408•523•9361  
Europe/Africa  
44•(0)•1753•622•209  
Fax:  
408•523•9365  
Phone: 81•(0)•45•471•1021  
Japan  
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Fax:  
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