AP-CF001GE3FR-NRK_技术文档

RoHS Compliant

Value Added Compact Flash Series Ⅲ

Specification for Industrial CF

Mar 8, 2011

Version 1.0

Apacer Technology Inc.

4^thFl., 75 Hsin Tai Wu Rd., Sec.1, Hsichih, New Taipei City, Taiwan 221

Tel: +886-2-2698-2888

www.apacer.com

Fax: +886-2-2698-2889

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Features:

ꢀ

Compact Flash Association

Specification Revision 3.0 Standard

Interface

ꢀ

Temperature ranges

–

Operation:

Standard: 0°C to 70°C

ET*: -40°C to 85°C

Storage: -40°C to 100°C

–

ATA command set compatible

ATA mode support for up to:

PIO Mode-6

Flash management

Multiword DMA Mode-4

Ultra DMA Mode-4

–

Intelligent endurance design

Advanced wear-leveling algorithms

S.M.A.R.T. Technology

ꢀ

Connector Type

–

50 pins female

Built-in Hardware ECC

Enhanced Data Integrity

Low power consumption (typical)

Supply voltage: 3.3V & 5V

–

Intelligent power failure recovery

–

Active mode: 80 mA/95 mA (3.3V/5.0V)

Sleep mode: 700 µA/900 µA (3.3V/5.0V)

ꢀ

RoHS compliant

ꢀ

Performance**

–

Sustained read: 30 MB/sec

Sustained write:

Standard: 5 MB/sec

High Speed: 15 MB/sec

Capacity

–

Standard:

128, 256, 512 MB

1, 2, 16 GB

High Speed:

256, 512 MB

1, 2, 4, 8 GB

ꢀ

NAND Flash Type: SLC

*Extended Temperature

**Performance varies with flash configurations

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Table of Contents

1. GENERAL DESCRIPTION ......................................................................................... 3

1.1 PERFORMANCE-OPTIMIZED

CONTROLLER ...............................................................................................3

1.1.1 Power Management Unit (PMU)...................................................................................................3

1.1.2 SRAM Buffer.................................................................................................................................3

2. FUNCTIONAL BLOCK ............................................................................................... 4

3. PIN ASSIGNMENTS................................................................................................... 5

4. CAPACITY SPECIFICATION ..................................................................................... 7

4.1 PERFORMANCE

SPECIFICATION ..............................................................................................................7

4.2 ENVIRONMENTAL

SPECIFICATIONS ..........................................................................................................8

5. FLASH MANAGEMENT ............................................................................................. 9

5.1 INTELLIGENT

ENDURANCE DESIGN..........................................................................................................9

5.1.1 Advanced wear-leveling algorithms..............................................................................................9

5.1.2 S.M.A.R.T. technology..................................................................................................................9

5.1.3 Built-in hardware ECC ..................................................................................................................9

5.1.4 Enhanced data integrity................................................................................................................9

5.2 INTELLIGENT

POWER FAILURE RECOVERY.............................................................................................10

6. SOFTWARE INTERFACE ....................................................................................... 11

6.1 COMMAND SET ....................................................................................................................................11

7. ELECTRICAL SPECIFICATION.............................................................................. 13

7.1 DC CHARACTERISTICS .........................................................................................................................14

7.2 AC CHARACTERISTICS .........................................................................................................................15

7.2.1 Attribute Memory Read Timing Specification .............................................................................16

7.2.2 Configuration Register (Attribute Memory) Write Specification..................................................17

7.2.3 Common Memory Read Timing Specification ............................................................................18

7.2.4 Common Memory Write Timing Specification ............................................................................19

7.2.5 I/O Input (Read) Timing Specification.........................................................................................20

7.2.6 I/O Output (Write) Timing Specification ......................................................................................21

7.2.7 Ultra DMA Mode Data Transfer Input/Output (Read/Write) Timing............................................22

7.2.8 Media Side Interface I/O Timing Specifications..........................................................................34

8. PHYSICAL CHARACTERISTICS............................................................................ 37

8.1 DIMENSION..........................................................................................................................................37

9. PRODUCT ORDERING INFORMATION................................................................. 38

9.1 PRODUCT

CODE DESIGNATIONS ...........................................................................................................38

9.2 VALID OMBINATIONS ..........................................................................................................................39

C

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1. General Description

Apacer’s Industrial Compact Flash Card (CFC) offers the most reliable and high performance storage

which is compatible with CF Type I and Type II devise. Unlike the ordinary consumer Compact Flash

cards, Apacer Industrial Compact Flash card provides solid traceability to ensure all products HW/SW are

the same as you qualified.

Apacer’s CFC provides complete PCMCIA - ATA functionality and compatibility. Apacer ‘s Compact Flash

technology is designed for use in Point of Sale (POS) terminals, telecom, IP-STB, medical instruments,

surveillance systems, industrial PCs and handheld applications.

Featuring technologies as Advanced Wear-leveling algorithms, S.M.A.R.T, Enhanced Data Integrity, Built-

in Hardware ECC, and Intelligent Power Failure Recovery, Apacer’s Industrial Compact Flash Card

assures users of a versatile device on data storage.

1.1 Performance-Optimized Controller

The Compact Flash Card Controller translates standard CF signals into flash media data and control

signals.

1.1.1 Power Management Unit (PMU)

The power management unit (PMU) controls the power consumption of the Compact Flash card controller.

It reduces the power consumption of the Compact Flash Card Controller by putting circuitry not in

operation into sleep mode. The PMU has zero wake-up latency.

1.1.2 SRAM Buffer

The Compact Flash Card Controller performs as an SRAM buffer to optimize the host’s data transfer to

and from the flash media.

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2. Functional Block

The Compact Flash Card (CFC) includes a controller and flash media, as well as the Compact Flash

standard interface. Figure 2-1 shows the functional block diagram.

Flash Array

Flash

Media

Flash

Media

Compact Flash

Controller

Compact Flash

Interface

Flash

Media

Flash

Media

Figure 2-1: Functional block diagram

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3. Pin Assignments

Table 3-1 lists the pin assignments with respective signal names for the 50-pin configuration. A “#” suffix

indicates the active low signal. The pin type can be input, output or input/output.

Table 3-1: Pin assignments (1 of 2)

Pin No.

Memory card mode

I/O card mode

True IDE mode

Signal name Pin I/O type

Signal name

Pin I/O type

Signal name Pin I/O type

1

2

GND

D3

-

GND

D3

-

GND

D3

-

I/O

3

D4

I/O

D4

I/O

D4

I/O

4

D5

I/O

D5

I/O

D5

I/O

5

D6

I/O

D6

I/O

D6

I/O

6

D7

I/O

D7

I/O

D7

I/O

7

8

9

#CE1

A10

#OE

A9

A8

A7

VCC

A6

A5

A4

A3

A2

A1

A0

D0

D1

D2

WP

#CD2

#CD1

D11

D12

D13

D14

D15

#CE2

#VS1

#IORD

#IOWR

#WE

RDY/-BSY

VCC

#CSEL

#VS2

RESET

I

-

I

#CE1

A10

#OE

A9

A8

A7

VCC

A6

A5

A4

A3

A2

A1

A0

D0

D1

D2

#IOIS16

#CD2

#CD1

D11

D12

D13

D14

D15

#CE2

#VS1

#IORD

#IOWR

#WE

#IREQ

VCC

#CSEL

#VS2

RESET

I

-

I

#CS0

A10¹

#ATA SEL

A9¹

I

-

I

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

A8¹

A7¹

VCC

A6¹

A5¹

A4¹

A3¹

A2

A1

A0

D0

D1

D2

I

I/O

O

I/O

I

O

I

O

-

I/O

O

I/O

I

O

I

O

-

I/O

O

I/O

I

O

I

O

-

#IOCS16

#CD2

#CD1

D11

D12

D13

D14

D15

#CS1

#VS1

#IORD

#IOWR

#WE

INTRQ

VCC

#CSEL

#VS2

#RESET

I

O

I

O

I

O

I

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Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Table 3-1: Pin assignments (2 of 2)

Pin No.

Memory card mode

I/O card mode

True IDE mode

Signal name Pin I/O type

Signal name

Pin I/O type

Signal name Pin I/O type

42

43

44

45

46

47

48

49

50

#WAIT

#INPACK

#REG

BVD2

BVD1

D8

D9

D10

GND

O

I

O

I/O

-

#WAIT

#INPACK

#REG

#SPKR

#STSCHG

D8

O

I

O

I/O

-

IORDY

DMARQ²

DMACK²

#DASP

#PDIAG

D8

D9

D10

GND

O

I

O

I/O

-

D9

D10

GND

1. The signal should be grounded by the host.

2. Connection required when UDMA is in use.

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4. Capacity Specification

Capacity specification of the Compact Flash Card series (CFC) is available as shown in Table 4-1. It lists

the specific capacity and the default numbers of heads, sectors and cylinders for each product line.

Table 4-1: Capacity specifications

Capacity

128 MB

256 MB

512 MB

1GB

Total bytes*

128,450,560

Cylinders

980

Heads

8

Sectors

32

Max LBA

250,880

256,901,120

980

16

32

501,760

512,483,328

993

16

63

1,000,944

2,001,888

4,001,760

8,027,712

16,007,040

32,014,080

1,024,966,656

2,048,901,120

4,110,188,544

8,195,604,480

16,391,208,960

1,986

3,970

7,964

15,880

16,383**

16

63

2GB

16

63

4GB

16

63

8GB

16

63

16GB

16

63

*Display of total bytes varies from file systems.

**Cylinders, heads or sectors are not applicable for these capacities. Only LBA addressing applies

4.1 Performance Specification

Performances of the Standard and High Speed ATA-Flash Disk are listed in Table 4-2 and Table 4-3.

Table 4-2: Standard Performance specifications

Capacity

128 MB / 256 MB

2 GB

16 GB

Performance

512 MB / 1 GB

15

20

5

20

5

Sustained read (MB/s)

Sustained write (MB/s)

5

Table 4-3: High Speed Performance specifications

Capacity 256 MB 512 MB

1 GB

2 GB

4 GB

8 GB

Performance

Sustained read (MB/s)

Sustained write (MB/s)

25

5

25

5

25

5

25

5

30

10

30

15

Note: Performance varies from flash configurations.

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4.2 Environmental Specifications

Environmental specification of the Compact Flash Card series (CFC) which follows the MIL-STD-810F

standards is available as shown in Table 4-4.

Table 4-4: Environmental specifications

Environment

Specification

0°C to 70 ℃ (Standard) ; -40°C to 85 ℃ (Extended Temperature)

-40℃ to 100℃

Operation

Storage

Temperature

Humidity

5% to 95% RH (Non-condensing)

Vibration (Non-Operation)

Shock (Non-Operation)

Sine wave: 10~2000Hz, 15G (X, Y, Z axes)

Half sine wave, Peak acceleration 50 G, 11 ms (X, Y, Z ; All 6 axes)

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5. Flash Management

5.1 Intelligent Endurance Design

5.1.1 Advanced wear-leveling algorithms

The NAND flash devices are limited by a certain number of write cycles. When using a file system,

frequent file table updates is mandatory. If some area on the flash wears out faster than others, it would

significantly reduce the lifetime of the whole device, even if the erase counts of others are far from the

write cycle limit. Thus, if the write cycles can be distributed evenly across the media, the lifetime of the

media can be prolonged significantly. The scheme is achieved both via buffer management and Apacer-

specific advanced wear leveling to ensure that the lifetime of the flash media can be increased, and the

disk access performance is optimized as well.

5.1.2 S.M.A.R.T. technology

S.M.A.R.T. is an acronym for Self-Monitoring, Analysis and Reporting Technology, an open standard

allowing disk drives to automatically monitor their own health and report potential problems. It protects the

user from unscheduled downtime by monitoring and storing critical drive performance and calibration

parameters. Ideally, this should allow taking proactive actions to prevent impending drive failure. Apacer

SMART feature adopts the standard SMART command B0h to read data from the drive. When the Apacer

SMART Utility running on the host, it analyzes and reports the disk status to the host before the device is

in critical condition.

5.1.3 Built-in hardware ECC

The ATA-Disk Module uses BCH Error Detection Code (EDC) and Error Correction Code (ECC)

algorithms which correct up to eight random single-bit errors for each 512-byte block of data. High

performance is fulfilled through hardware-based error detection and correction.

5.1.4 Enhanced data integrity

The properties of NAND flash memory make it ideal for applications that require high integrity while

operating in challenging environments. The integrity of data to NAND flash memory is generally

maintained through ECC algorithms and bad block management. Flash controllers can support up to 8

bits ECC capability for accuracy of data transactions, and bad block management is a preventive

mechanism from loss of data by retiring unusable media blocks and relocating the data to the other blocks,

along with the integration of advanced wear leveling algorithms, so that the lifespan of device can be

expanded.

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5.2 Intelligent Power Failure Recovery

The Low Power Detection on the controller initiates cached data saving before the power supply to the

device is too low. This feature prevents the device from crash and ensures data integrity during an

unexpected blackout. Once power was failure before cached data writing back into flash, data in the

cache will lost. The next time the power is on, the controller will check these fragmented data segment,

and, if necessary, replace them with old data kept in flash until programmed successfully.

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6. Software Interface

6.1 Command Set

Table 6-1 summarizes the command set with the paragraphs that follow describing the individual

commands and the task file for each.

Table 6-1: Command set (1 of 2)

Command

Check-Power-Mode

Code

E5H or 98H

90H

FR¹

SC²

-

SN³

-

CY⁴

-

DH⁵

D⁸

D

Y

LBA⁶

-

Execute-Drive-Diagnostic

Erase Sector(s)

Flush-Cache

Format Track

Identify-Drive

Idle

-

C0H

-

Y

-

Y

-

Y

-

Y

-

E7H

-

D

Y⁸

D

Y

50H

-

Y⁷

-

Y

-

Y

-

ECH

-

E3H or 97H

E1H or 95H

91H

-

Y

-

Idle-Immediate

Initialize-Drive-Parameters

NOP

-

Y

-

00H

-

D

Y

-

Read-Buffer

E4H

-

Read-DMA

C8H or C9H

C4H

-

Y

-

Y

-

Y

-

Y

-

Read-Multiple

Read-Sector(s)

Read-Verify-Sector(s)

Recalibrate

-

Y

20H or 21H

40H or 41H

1XH

-

Y

-

Y

-

D

Y

Request-Sense

Seek

03H

-

7XH

-

Y⁷

-

Y

-

Y

-

Y

-

Set-Features

EFH

-

D

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Table 6-1: Command set (2 of 2)

Command

Code

B0H

FR¹

SC²

Y

-

SN³

Y

-

CY⁴

Y

-

DH⁵

D

Y

LBA⁶

SMART

Y

-

Set-Multiple-Mode

Set-Sleep-Mode

Standby

C6H

-

E6H or 99H

E2H or 96H

E0H or 94H

87H

-

Standby-lmmediate

Translate-Sector

Write-Buffer

-

Y

-

Y

-

Y

-

Y

-

E8H

D

Y

Write-DMA

CAH or CBH

C5H

Y

Write-Multiple

Y

Write-Multiple-Without-Erase

Write-Sector(s)

Write-Sector-Without-Erase

Write-Verify

CDH

Y

30H or 31H

38H

Y

3CH

Y

1. FR - Features register

2. SC - Sector Count register

3. SN - Sector Number register

4. CY - Cylinder registers

5. DH - Drive/Head register

6. LBA - Logical Block Address mode supported (see command descriptions for use)

7. Y - The register contains a valid parameter for this command

8. For the Drive/Head register:

Y means both the CFC and Head parameters are used

D means only the CFC parameter is valid and not the Head parameter

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7. Electrical Specification

Caution: Absolute Maximum Stress Ratings – Applied conditions greater than those listed under

“Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these conditions or conditions greater than those defined in

the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating

conditions may affect device reliability.

Table 7-1: Operating range

Range

Ambient Temperature

0°C to +70°C

3.3V

5V

Standard

3.135-3.465V

4.75-5.25V

Extended Temperature

-40°C to +85°C

Table 7-2: Absolute maximum power pin stress ratings

Parameter

Symbol

V_DD

Conditions

Input Power

-0.3V min. to 6.5V max.

-0.5V min. to VDD + 0.5V max.

Voltage on any pin except V_DDwith respect to GND

V

Table 7-3: Recommended system power-up timing

Symbol

Parameter

Typical

200

Maximum

Units

ms

1

T_PU-READY

Power-up to Ready Operation

Power-up to Write Operation

1000

1

T_PU-WRITE

200

ms

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

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7.1 DC Characteristics

Table 7-4: DC Characteristics

Symbol

V_IH1

V_IL1

Type

Parameter

Input Voltage

Min

2.0V

Max

Units

Conditions

V_DDQ=V_DDQMax

V_DDQ=V_DDQMin

V

I1

0.8V

10

Input Leakage Current

Input Pull-Up Current

-10

A

μ

V_IN=GND to V_DDQ

V_DDQ= V_DDQMax

V_OUT=GND,

V_DDQ= V_DDQMax

V_DDQ=V_DDQMax

V_DDQ=V_DDQMin

I_IL1

I1Z

I1U

-110

-1

A

μ

I_U1

Input Voltage Schmitt Trigger

2.0

V

V_T+2

V_T-2

I2

0.8

-10

Input Leakage Current

Input Pull-Up Current

Output Voltage

10

-1

A

μ

V_IN=GND to V_DDQ

V_DDQ= V_DDQMax

V_OUT=GND,

V_DDQ= V_DDQMax

I_OH1=I_OH1Min

I_OL1=I_OL1Max

I_IL2

I_U2

I2Z

I2U

-110

2.4

A

μ

V

V_OH1

V_OL1

I_OH1

I_OL1

V_OH2

V_OL2

I_OH2

I_OL2

I_OH2

I_OL2

V_OH6

V_OL6

I_OH6

I_OL6

0.4

O1

Output Current

Output Voltage

-4

mA

V

V_DDQ=V_DDQMin

4

2.4

-6

I_OH2=I_OH2Min

I_OL2=I_OL2Max

0.4

Output Current

mA

V

V_DDQ=3.135V-3.465V

V_DDQ=4.5V-5.5V

O2

Output Current

6

Output Current

-8

Output Current

8

V_DDQ=4.5V-5.5V

Output Voltage for DASP# pin

2.4

-3

I_OH6=I_OH6Min

I_OL6=I_OL6Max

0.4

Output Current for DASP# pin

Power supply current

(T = 0°C to +70°C)

a

Power supply current

(T = -40°C to +85°C)

a

Sleep/Standby/Idle current

mA

V_DDQ=3.135V-3.465V

V_DDQ=4.5V-5.5V

O6

8

-3

I_OH6

I_OL6

12

50

V_DDQ=4.5V-5.5V

1,2

V_DD=V_DDMax

V_DDQ=V_DDQMax

V_DD=V_DDMax

V_DDQ=V_DDQMax

V_DD=V_DDMax

V_DDQ=V_DDQMax

I_DD

PWR

1,2

I_DD

75

mA

A

μ

I_SP

(T = 0°C to +70°C)

a

200

A

μ

V_DD=V_DDMax

V_DDQ=V_DDQMax

Sleep/Standby/Idle current

(T = -40°C to +85°C)

a

PWR

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7.2 AC Characteristics

Figure 7-1: AC Input/Output Reference Waveforms

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”.

Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise

and fall times (10% ↔ 90%) are <10 ns.

Note: V_IT- V_INPUTTest

V_OT- V_OUTPUTTest

V_IHT- V_{INPUT HIGH}Test

V_ILT- V_{INPUT LOW}Test

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7.2.1 Attribute Memory Read Timing Specification

The Attribute Memory access time is defined as 100 ns. Detailed timing specifications are shown in the

table below.

Table 7-5: Attribute Memory Read Timing Specification

Speed Version

Item

Read Cycle Time

100 ns

Max*

Symbol

T_C(R)

IEEE Symbol

tAVAV

Min*

100

Units

ns

Address Access Time

T_A(A)

tAVQV

tELQV

tGLQV

tEHQZ

tGHQZ

tAVGL

tELQNZ

tGLQNZ

tAXQZ

100

50

ns

Card Enable Access Time

Output Enable Access Time

Output Disable Time from CE#

Output Disable Time from OE#

Address Setup Time

Output Enable Time from CE#

Output Enable Time from OE#

Data Valid from Address Change

T_A(CE)

T_A(OE)

T_DIS(CE)

T_DIS(OE)

T_SU(A)

T_EN(CE)

T_EN(OE)

T_V(A)

10

5

0

ns

*D_OUTsignifies data provided by the Compact Flash card to the system. The CE# signal or both the OE# signal and the WE# signal

must be de-asserted between consecutive cycle operations. All AC specifications are guaranteed by design.

Figure 7-2: Attribute Memory Read Timing Diagram

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7.2.2 Configuration Register (Attribute Memory) Write Specification

The card configuration write access time is defined as 100 ns. Detailed timing specifications are shown in

the table below.

Table 7-6: Configuration Register (Attribute Memory) Write Timing

Speed Version

Item

100 ns

Max*

Symbol

T_C(W)

T_W(WE)

T_SU(A)

T_REC(WE)

T_SU(DWE#H)tDVWH

T_H(D)tWMDX

IEEE Symbol

tAVAV

tWLWH

tAVWL

tWMAX

Min*

100

60

10

15

Units

ns

Write Cycle Time

Write Pulse Width

Address Setup Time

Write Recover Time

Data Setup Time for WE

Data Hold Time

40

15

ns

*D_INsignifies data provided by the system to the Compact Flash card. All AC specifications are guaranteed by design.

Figure 7-3: Configuration Register (Attribute Memory) Write Timing Diagram

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Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

7.2.3 Common Memory Read Timing Specification

Table 7-7: Common Memory Read Timing

Item

Symbol

T_A(OE)

T_DIS(OE)

T_SU(A)

T_REC(WE)

T_SU(CE)

T_H(CE)

IEEE Symbol

tGLQV

tGHQZ

tAVGL

tGHAX

Min*

Max*

50

Units

ns

Output Enable Access Time

Output Disable Time from OE

Address Setup Time

Address Hold Time

CE Setup before OE

CE Hold following OE

10

15

0

tELGL

tGHEH

ns

15

*All AC specifications are guaranteed by design.

Figure 7-4: Common Memory Read Timing Diagram

18

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

7.2.4 Common Memory Write Timing Specification

Table 7-8: Common Memory Write Timing

Symbol IEEE Symbol

T_SU(DWE#H)tDVWH

Item

Min*

40

15

60

10

0

15

Max*

Units

ns

Data Setup before WE

Data Hold following WE

WE Pulse Width

Address Setup Time

CE Setup before WE

Write Recovery Time

Address Hold Time

CE Hold following WE

T_H(D)

tWMDX

tWLWH

tAVWL

tELWL

tWMAX

tGHAX

tGHEH

T_W(WE)

T_SU(A)

T_SU(CE)

T_REC(WE)

T_H(A)

T_H(CE)

*All AC specifications are guaranteed by design.

Figure 7-5: Common Memory Write Timing Diagram

19

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

7.2.5 I/O Input (Read) Timing Specification

Table 7-9: I/O Read Timing

Item

Symbol

T_D(IORD)

T_H(IORD)

T_W(IORD)

T_SUA(IORD)

T_HA(IORD)

T_SUCE(IORD)

T_HCE(IORD)

T_SUREG(IORD)

T_HREG(IORD)

T_{DFINPACK(IORD)}

T_{DRINPACK(IORD)}

IEEE Symbol

tlGLQV

tlGHQX

tlGLIGH

tAVIGL

Min*

Max*

100

Units

ns

Data Delay after IORD

Data Hold following IORD

IORD Width Time

0

165

70

20

5

20

5

0

Address Setup before IORD

Address Hold following IORD

CE Setup before IORD

CE Hold following IORD

REG Setup before IORD

REG Hold following IORD

INPACK Delay Falling from IORD

INPACK Delay Rising from IORD

tlGHAX

tELIGL

tlGHEH

tRGLIGL

tlGHRGH

tlGLIAL

tlGHIAH

tAVISL

0

45

35

IOIS16 Delay Falling from Address T_{DFIOIS16(ARD)}

IOIS16 Delay Rising from Address

*All AC specifications are guaranteed by design.

T_{DRIOIS16(ADR)}

tAVISH

Note: The maximum load on –INPACK and IOIS16# is 1 LSTTL with 50pF total load.

Figure 7-6: I/O Read Timing Diagram

20

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

7.2.6 I/O Output (Write) Timing Specification

Table 7-10: I/O Write Timing

Item

Symbol

T_SU(IOWR)

T_H(IOWR)

IEEE Symbol

tDVIWH

tlWHDX

tlWLIWH

tAVIWL

tlWHAX

tELIWL

tlWHEH

tRGLIWL

tlWHRGH

tAVISL

Min*

60

30

165

70

20

5

20

5

0

Max*

Units

ns

Data Setup before IOWR

Data Hold following IOWR

IOWR Width Time

Address Setup before IOWR

Address Hold following IOWR

CE Setup before IOWR

CE Hold following IOWR

REG Setup before IOWR

REG Hold following IOWR

T_W(IOWR)

T_SUA(IOWR)

T_HA(IOWR)

T_SUCE(IOWR)

T_HCE(IOWR)

T_SUREG(IOWR)

T_HREG(IOWR)

ns

IOIS16 Delay Falling from Address T_{DFIOIS16(ARD)}

IOIS16 Delay Rising from Address

*All AC specifications are guaranteed by design.

35

T_{DRIOIS16(ADR)}

tAVISH

Note: The maximum load on –INPACK and IOIS16# is 1 LSTTL with 50pF total load.

Figure 7-7: I/O Write Timing Diagram

21

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

7.2.7 Ultra DMA Mode Data Transfer Input/Output (Read/Write) Timing

Table 7-11: Ultra DMA Data Burst Timing Specifications¹

Mode 4

Measurement

Location²

Sender

Name

Descriptions

Unit

Min

60

Max

T_2CYCTYPTypical sustained average two cycle time

T _CYC

ns

Cycle time allowing for asymmetry and clock

variations (from STROBE edge to STROBE

edge)

25

Note³

T _2CYC

Two cycle time allowing for clock variations

(from rising edge to next rising edge or from

falling edge to next falling edge of STROBE)

Data setup time at recipient (from data valid until

STROBE edge)^4,5

57

ns

Sender

T _DS

5.0

6.0

ns

Recipient

Sender

T _DH

Data hold time at Recipient (from STROBE edge

until data becomes invalid)^1,2

T _DVS

T _DVH

Data valid setup time for Sender (from data valid

until STROBE edge)⁶

Data valid hold time at Sender (from STROBE

Sender

edge until data becomes invalid)³

T _CS

T _CH

T _CVS

CRC word setup time at device¹

5.0

6.7

ns

Device

Host

CRC word hold time at device¹

CRC word valid setup time at host (from CRC

valid until DMACK negation)³

T _CVH

T _ZFS

T _DZFS

T _FS

CRC word valid hold time at Sender (from

DMACK negation until CRC becomes invalid)³

Time from STROBE output released-to-driving

until the first transition of critical timing

Time from data output released-to-driving until

the first transition of critical timing

6.2

0

ns

Host

Device

Sender

Device

6.7

First STROBE time (for device to first negate

DSTROBE from STOP during a data in burst)

Limited interlock time⁷

120

100

T _LI

0

20

0

ns

Note⁸

Host

Note⁹

T _MLI

T _UI

T _AZ

Interlock time with minimum⁴

Unlimited interlock time⁴

Maximum time allowed for output drivers to

release (from asserted to negated)

Minimum delay time required for output

Drivers to assert or negate (from released)

Envelope time (from DMACK# to STOP and

HDMARDY# during data in burst initiation and

from DMACK to STOP during data our burst

initiation)

Ready-to-final STROBE time (no STROBE edge

are sent this long after negation of DMARDY)

Ready-to-pause time (Recipient waits to pause

until after negating DMARDY)

10

55

60

20

T _ZAH

T _ZAD

T _ENV

20

0

20

ns

Host

Device

Host

T _RFS

T _RP

ns

Sender

100

Recipient

T _IORDYZ

T _ZIORDY

T _ACK

Maximum time before releasing IORDY

ns

Device

Host

Minimum time before driving IORDY¹⁰

0

20

50

T _SS

Sender

22

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

1. All timing measurement switching points (low-to-high and high-to-low) are taken at 1.5V.

2. All signal transitions for a timing parameter are measured at the connector specified in the measurement location column. For

example, in the case of TRFS, both STROBE and DMARDY Transitions are measured at the Sender connector.

3. The parameter TCYC is measured at the recipient’s connector farthest from the Sender.

4. 80-Conductor cabling is required in order to meet sup (TDS, TCS) and hold (TDH, TCH) times in modes greater than two.

5. The parameters TDS and TDH for Mode 5 are defined for a Recipient at the end of the cable only in a configuration with a single

device located at the end of the cable. This could result in the minimum values for TDS and TDH for mode 5 at the middle

connector being 3.0 and 3.9 ns respectively.

6. Timing for TDVS, TDVH, TCVS, and TCVH are met for lumped capacitive loads of 15 and 50 pf at the connector where the Data

and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not

valid in a normally functioning system.

7. The parameters TUI, TMLI, and TLI indicate Sender-to-Recipient or Recipient-to-Sender interlocks. For example, one agent

(either Sender or Recipient) is waiting for the other agent to respond with a signal before proceeding; TUI is an unlimited

interlock that has no maximum time value, TMLI is a limited time-out that has a defined minimum, and TLI is a limited time-out

that has a defined maximum.

8. The parameter TLI is measured at the connector of the Sender or Recipient that is responding to an incoming transition from the

Recipient or Sender respectively. Both the incoming signal and the outgoing response are measured at the same connector.

9. The parameter TAZ is measured at the connector of the Sender or Recipient that is driving the bus but must release the bus that

allow for a bus turnaround.

10. For all modes the parameter TZIORDY may be greater than TENV because the host has a pull-on IORDY giving it a known

state when released.

23

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Table 7-12: Ultra DMA Sender and Recipient IC Timing Specifications¹

Mode 4

Name

Descriptions

Unit

Min

4.8

Max

T_DSIC

T _DHIC

Recipient IC data setup time (from data valid until STROBE edge)²

Recipient IC data hold time (from STROBE edge until data becomes

invalid)¹

ns

T _DVSIC

T _DVHIC

Sender IC data valid setup time (from data valid until STROBE edge)³

9.5

9.0

ns

1.

2.

All timing measurement switching point (low-to-high and high-to-low)

The correct data value is captured by the Recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input

STROBE with a slew rate of 0.4 V/ns rising and falling at TDSIC and TDHIC timing (as measured through 1.5 V).

The parameters TDVSIC and TDVHIC are met for lumped capacitive loads of 15 and 40 pf at the IC where all signals have the

same capacitive load value. Noise that may couple onto the output signals from external sources has not been included in

these values.

3.

Figure 7-8: Initiating an Ultra DMA Data-In Burst

Notes:

1.

The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE, and IORDY:DDRARDY-: DSTROBE signal lines are not

in effect until DMARQ and DMACK are asserted.

24

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-9: Sustained Ultra DMA Data-In Burst

Notes:

1.

DD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as

cable propagation delay will not allow the data signals to be considered stable at the host until some time after they are driven

by the device.

25

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-10: Sustained Ultra DMA Data-In Burst

Notes:

1.

2.

The host may assert STOP to request termination of the Ultra DMA burst no sooner than TRP after HDMARDY# is negated.

After negating HDMARDY#, the host may receive zero, one, two, or three more data words from the device.

26

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-11: Device Terminating and Ultra DMA Data-In Burst

Notes:

1.

The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are

negated.

27

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-12: Host Terminating and Ultra DMA Data-In Burst

Notes:

1.

The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are

negated.

28

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-13: Initiating an Ultra DMA Data-Out Burst

Notes:

1.

The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are

negated.

29

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-14: Sustained Ultra DMA Data-Out Burst

Notes:

1.

DD(15:0) and HSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as

cable propagation delay will not allow the data signals to be considered stable at the host until some time after they are driven

by the host.

30

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-15: Device Pausing and Ultra DMA Data-Out Burst

Notes:

1.

2.

The host may negate DMARQ to request termination of the Ultra DMA burst no sooner than TRP after DDMARDY# is negated.

After negating DDMARDY#, the host may receive zero, one, two, or three more data words from the host.

31

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-16: Host Terminating and Ultra DMA Data-Out Burst

Notes:

1. The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are

negated.

32

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-17: Device Terminating and Ultra DMA Data-Out Burst

Notes:

1.

The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are

negated.

33

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

7.2.8 Media Side Interface I/O Timing Specifications

Table 7-13: Timing Parameter

Symbol

T_CLS

T_CLH

T_CS

T_CH

T_CHR

T_WP

T_WH

T_WC

T_ALS

T_ALH

T_DS

T_DH

T_RP

T_RR

T_RES

T_RC

Parameter

FCLE Setup Time

FCLE Hold Time

FCE# Setup Time

FCE# Hold Time for Command/Data Write Cycle

FCE# Hold Time for Sequential Read Last Cycle

FWE# Pulse Width

FWE# High Hold Time

Write Cycle Time

FALE Setup Time

FALE Hold Time

FAD[15:0] Setup Time

FAD[15:0] Hold Time

FRE# Pulse Width

Ready to FRE# Low

FRE# Data Setup Access Time

Read Cycle Time

FRE# High Hold Time

FRE# High to Data Hi-Z

Min

20

40

-

20

40

20

40

20

40

20

40

20

5

Max

Units

ns

-

40

-

T_REH

T_RHZ

Note: All AC specifications are guaranteed by design.

34

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-18: Media Command Latch Cycle

Figure 7-19: Media Access Latch Cycle

35

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Figure 7-20: Media Data Loading Latch Cycle

Figure 7-21: Media Data Read Cycle

36

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

8. Physical Characteristics

8.1 Dimension

T

ABLE 8-1: Type I CFC physical specification

36.40 +/- 0.15mm (1.433+/- 0.06 in.)

42.80 +/- 0.10mm (1.685+/- 0.04 in.)

3.3mm+/-0.10mm (0.130+/-0.04in.)

Length:

Width:

Thickness (Including Label Area):

Unit: mm

F

IGURE 8-1: Physical dimension

37

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

9. Product Ordering Information

9.1 Product Code Designations

A P – C F x x x x E 3 X R – XXXXXXK

Specification

NR: Non-Removable Setting

NDNR: Non-DMA + Non-Removable

ETNR: Ext. Temp. + Non-Removable

ETNDNR: Ext. Temp + Non-DMA + Non-Removable

K: Value Added Ⅲ

RoHS Compliant

Configuration

E: Standard

F: High Speed

Controller Type

CFC Type

Capacity:

128M: 128MB

256M: 256MB

512M: 512MB

001G:

002G:

004G:

008G:

016G:

1GB

2GB

4GB

8GB

16GB

Model Name

Apacer Product Code

38

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

9.2 Valid Combinations

Standard Temperature

Non-Removable

Standard

High Speed

Capacity

256MB

512MB

1GB

Capacity

128MB

256MB

512MB

1GB

Model Number

AP-CF256ME3FR-NRK

AP-CF512ME3FR-NRK

AP-CF001GE3FR-NRK

AP-CF002GE3FR-NRK

AP-CF004GE3FR-NRK

AP-CF008GE3FR-NRK

AP-CF128ME3ER-NRK

AP-CF256ME3ER-NRK

AP-CF512ME3ER-NRK

AP-CF001GE3ER-NRK

AP-CF002GE3ER-NRK

AP-CF016GE3ER-NRK

2GB

4GB

16GB

8GB

Non-DMA & Non-Removable

Standard

High Speed

Capacity

256MB

512MB

1GB

Capacity

128MB

256MB

512MB

1GB

Model Number

AP-CF128ME3ER-NDNRK

AP-CF256ME3ER-NDNRK

AP-CF512ME3ER-NDNRK

AP-CF001GE3ER-NDNRK

AP-CF002GE3ER-NDNRK

AP-CF016GE3ER-NDNRK

AP-CF256ME3FR-NDNRK

AP-CF512ME3FR-NDNRK

AP-CF001GE3FR-NDNRK

AP-CF002GE3FR-NDNRK

AP-CF004GE3FR-NDNRK

AP-CF008GE3FR-NDNRK

2GB

4GB

16GB

8GB

39

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Extended Temperature

Non-Removable

Standard

High Speed

Capacity

256MB

512MB

1GB

Capacity

Model Number

128MB

256MB

512MB

1GB

AP-CF128ME3ER-ETNRK

AP-CF256ME3ER-ETNRK

AP-CF512ME3ER-ETNRK

AP-CF001GE3ER-ETNRK

AP-CF002GE3ER-ETNRK

AP-CF016GE3ER-ETNRK

AP-CF256ME3FR-ETNRK

AP-CF512ME3FR-ETNRK

AP-CF001GE3FR-ETNRK

AP-CF002GE3FR-ETNRK

AP-CF004GE3FR-ETNRK

AP-CF008GE3FR-ETNRK

2GB

4GB

16GB

8GB

Non-DMA & Non-Removable

Standard

High Speed

Capacity

256MB

512MB

1GB

Capacity

128MB

256MB

512MB

1GB

Model Number

AP-CF128ME3ER-ETNDNRK

AP-CF256ME3ER-ETNDNRK

AP-CF512ME3ER-ETNDNRK

AP-CF001GE3ER-ETNDNRK

AP-CF002GE3ER-ETNDNRK

AP-CF016GE3ER-ETNDNRK

AP-CF256ME3FR-ETNDNRK

AP-CF512ME3FR-ETNDNRK

AP-CF001GE3FR-ETNDNRK

AP-CF002GE3FR-ETNDNRK

AP-CF004GE3FR-ETNDNRK

AP-CF008GE3FR-ETNDNRK

2GB

4GB

16GB

8GB

40

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Revision History

Revision

Description

Date

1.0

Official release

Mar 8, 2011

41

Rev. 1.0

Value Added Compact Flash Ⅲ series

AP-CFxxxxE3XR-XXXXXXK

Global Presence

Apacer Technology Inc.

Taiwan (Headquarters)

4^thFl, 75 Xintai 5^thRd., Sec.1

Hsichih, New Taipei City

Taiwan 221

R.O.C.

Tel: +886-2-2698-2888

Fax: +886-2-2698-2889

amtsales@apacer.com

Apacer Memory America, Inc.

386 Fairview Way, Suite102,

Milpitas, CA 95035

Tel: 1-408-518-8699

Fax: 1-408-935-9611

U.S.A.

Japan

Europe

sa@apacerus.com

Apacer Technology Corp.

5F, Matsura Bldg., Shiba, Minato-Ku

Tokyo, 105-0014, Japan

Tel: 81-3-5419-2668

Fax: 81-3-5419-0018

jpservices@apacer.com

Apacer Technology B.V.

Aziëlaan 22,

5232 BA 's-Hertogenbosch,

The Netherlands

Tel: 31-73-645-9620

Fax: 31-73-645-9629

sales@apacer.nl

Apacer Electronic (Shanghai) Co., Ltd

1301, No.251,Xiaomuqiao Road, Shanghai,

200032, China

Tel: 86-21-5529-0222

Fax: 86-21-5206-6939

China

India

sales@apacer.com.cn

Apacer Technologies Pvt Ltd,

#1064, 1st Floor, 7th ‘A’ Main,

3rd Block Koramangala, Bangalore – 560 034

Tel: +91 80 4152 9061/62/63

Fax: +91 80 4170 0215

sales_india@apacer.com

42

Rev. 1.0

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Apacer:

AP-CF001GE3FR-ETNDNRK AP-CF001GE3FR-ETNRK AP-CF001GE3FR-NDNRK AP-CF001GE3FR-NRK AP-

CF001GH4FR-ETNDNRK AP-CF001GH4FR-ETNRK AP-CF001GH4FR-NDNRK AP-CF001GH4FR-NRK AP-

CF002GE3FR-ETNDNRK AP-CF002GE3FR-ETNRK AP-CF002GE3FR-NDNRK AP-CF002GE3FR-NRK AP-

CF002GH4FR-ETNDNRK AP-CF002GH4FR-ETNRK AP-CF002GH4FR-NDNRK AP-CF002GH4FR-NRK AP-

CF004GE3FR-ETNDNRK AP-CF004GE3FR-ETNRK AP-CF004GE3FR-NDNRK AP-CF004GE3FR-NRK AP-

CF004GH4FR-ETNDNRK AP-CF004GH4FR-ETNRK AP-CF004GH4FR-NDNRK AP-CF004GH4FR-NRK AP-

CF008GE3FR-ETNDNRK AP-CF008GE3FR-ETNRK AP-CF008GE3FR-NDNRK AP-CF008GE3FR-NRK AP-

CF008GH4FR-ETNDNRK AP-CF008GH4FR-ETNRK AP-CF008GH4FR-NDNRK AP-CF128ME3ER-ETNDNRK AP-

CF128ME3ER-ETNRK AP-CF128ME3ER-NDNRK AP-CF128ME3ER-NRK AP-CF128MH4ER-ETNDNRK AP-

CF128MH4ER-ETNRK AP-CF128MH4ER-NDNRK AP-CF128MH4ER-NRK AP-CF256ME3FR-NDNRK AP-

CF256ME3FR-NRK AP-CF256MH4FR-ETNDNRK AP-CF256MH4FR-ETNRK AP-CF256MH4FR-NDNRK AP-

CF256MH4FR-NRK AP-CF512ME3FR-ETNDNRK AP-CF512ME3FR-ETNRK AP-CF512ME3FR-NDNRK AP-

CF512ME3FR-NRK AP-CF512MH4FR-ETNDNRK AP-CF512MH4FR-ETNRK AP-CF512MH4FR-NDNRK AP-

CF512MH4FR-NRK


型号：	AP-CF001GE3FR-NRK
厂家：	ETC
描述：	Value Added Compact Flash Series â¢ Specification for Industrial CF
文件：	总44页 (文件大小：793K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AP-CF001GE3FR-NRK [ETC]

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