AP919 [ETC]

iphone音箱方案 ; iphone音箱方案
AP919
型号: AP919
厂家: ETC    ETC
描述:

iphone音箱方案
iphone音箱方案

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AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
AP919  
OTP Microcontroller with LCD Driver  
and  
Digital Tuning System for  
Docking Application  
Datasheet  
Revision 0.6  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
Table of Contents  
1. OVERVIEW................................................................................................................................................................1  
2. APPLICATIONS ........................................................................................................................................................1  
2.1.  
2.2.  
2.2.1  
2.2.2  
2.2.3  
2.2.4  
T
A
ARGET  
A
PPLICATIONS ...................................................................................................................................................... 1  
EATURES..................................................................................................................................................... 1  
EATURES....................................................................................................................................... 1  
EATURES...................................................................................................................................... 1  
EATURES ........................................................................................................................................................... 1  
EATURES............................................................................................................................................ 1  
PPLICATION F  
C
D
R
LOCK AND  
OCKING  
ADIO  
THER  
A
LARM  
F
F
C
ONTROL  
F
S
O
YSTEM  
F
3. ORDERING INFORMATION .....................................................................................................................................1  
4. PIN CONFIGURATION..............................................................................................................................................1  
5. BLOCK DIAGRAM ....................................................................................................................................................2  
6. BUILT IN PERIPHERALS .........................................................................................................................................2  
7. PIN DESCRIPTION ...................................................................................................................................................3  
8. ELECTRICAL SPECIFICATION ...............................................................................................................................5  
8.1.  
8.2.  
8.3.  
A
R
L
BSOLUTE  
ECOMMENDED  
EAKAGE URRENT AND C  
M
AXIMUM  
R
ATING............................................................................................................................................. 5  
ONDITION........................................................................................................................... 5  
APACITANCE............................................................................................................................. 5  
CHARACTERISTICS .................................................................................................................................. 5  
O
PERATING C  
C
8.4. DC ELECTRICAL  
9. BONDING AND PACKAGE INFORMATION............................................................................................................6  
9.1.  
9.2.  
R
EFERENCE COB LAYOUT  
I
NFORMATION ......................................................................................................................... 6  
PACKAGE  
INFORMATION ..................................................................................................................................................... 7  
10. SOLDERING INDICATION........................................................................................................................................8  
1.  
2.  
3.  
4.  
R
W
M
S
EFLOW  
AVE  
ANUAL  
UITABILITY OF  
S
OLDERING.......................................................................................................................................................... 8  
OLDERING .............................................................................................................................................................. 8  
OLDERING .......................................................................................................................................................... 8  
S
S
SURFACE  
MOUNT IC PACKAGES FOR  
W
AVE AND  
R
EFLOW  
SOLDERING  
METHODS ............................... 9  
Revision 0.6  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
1. OVERVIEW  
2.2.2 Docking Control Features  
The AP919 is a controller IC for docking application  
with remote control function and LCD driver. It has a  
built-in PLL controller for controlling external radio  
tuner IC to form a complete digital tuning system (DTS).  
AP919 also supports real time clock with 12/24 hour  
display format and dual alarm clock timer. Built-in with  
LCD driver and support for docking system of  
prevalent music players and mobile phones, AP919 is  
suitable for a wide range of audio applications that  
have build-in clock alarm, radio and docking features.  
Docking control through front panel buttons or  
remote controller  
PLAY, PAUSE, STOP, FAST FORWARD, FAST  
BACKWARD, RANDOM, REPEAT functions  
Device charging through docking system  
Support Apple Authentication Coprocessor  
2.2.3 Radio Features  
Auto/Manual radio station scanning  
Programmable radio station memory ( independent  
memory slots for FM and AM )  
2. APPLICATIONS  
2.1. Target Applications  
Docking System  
Clock Radio  
2.2.4 Other System Features  
Support 24 segment x 4 common or 6 common,  
1/3 bias LCD display  
2.2. Application Features  
Automatic detection of AC power  
Low standby current  
2.2.1 Clock and Alarm Features  
12/24 hour clock display mode selectable by user  
Dual alarm clocks  
User selectable alarm mode – wake-to-buzzer,  
wake-to-radio or wake-to-docked_device  
Fixed snooze feature  
3. ORDERING INFORMATION  
ORDERING NUMBER  
PINS  
PACKAGE  
Bare Dice  
LQFP  
AP919-DC-L  
100  
AP919-LQ-L  
100  
Programmable sleep timer  
4. PIN CONFIGURATION  
P90 / SPIDIO  
P91 / SPICLK  
1
2
75  
P71 / SEG18  
P72 / SEG19  
P73 / SEG20  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
50  
49  
P11  
/ BOUT1  
74 P70 / SEG17  
P10 / TONE  
3
4
5
6
7
8
9
73  
P92 / SPIDI / AST0  
P63 / SEG16  
P80  
P81  
/
/
SEG21  
SEG22  
48 P113 / I2CDAT2  
47 P112 / I2CCLK2  
46 ADCIO5  
P93 / AST1  
RSTB  
72  
71  
70  
69  
68  
P62 / SEG15  
P61 / SEG14  
P60 / SEG13  
P53 / SEG12  
P52 / SEG11  
P82 / SEG23  
P83 / SEG24  
VLCD2  
PWRDET  
AVDD  
ADCIO4  
45  
44 ADCIO3  
VLCD1  
VLCD  
ACIN  
ADCIO2  
43  
PLLFLT  
AGND  
ADCIO1  
ADCIO0  
W2  
P133  
P132 / TONE  
42  
41  
40  
39  
38  
37  
67 P51  
/
SEG10  
GND 10  
OSCI 11  
OSCO 12  
VDD 13  
VPP 14  
66  
65  
64  
63  
62  
61  
60  
P50  
GND  
/ SEG9  
P120 / TX1  
AP919  
P121  
/
RX1  
P43  
P42  
/
SEG8  
SEG7  
P122 / BOUT1  
P123  
TESTB3  
/
W3  
36 TESTB2  
35 DTSPLLFLT  
34 GND  
Dice Form  
P41 / SEG6  
P40 / SEG5  
P33 / SEG4  
PGM  
P130 15  
P131 16  
WDTEN 17  
W0 18  
ATONE  
VDD  
XOSCO  
33 IFIN  
59  
58  
57  
56  
55  
54  
53  
P32 / SEG3  
P31 / SEG2  
P30 / SEG1  
AMIN  
32  
XOSCI  
31 FMIN  
19  
GND  
W1  
30  
VDD  
29 P103  
28  
TESTB0 / EMU_SCLR  
/
/
/
/
PWMO  
BOUT0  
RX0  
P00 / I2CCLK0 20  
P01 / I2CDAT0 21  
P02 / PWMO 22  
P23 / COM1  
TESTB1 / EMU_SDI  
P102  
27 P101  
P100  
P22 / COM2  
P21 / COM3  
P20 / COM4  
EMU_SCLK 99  
EMU_SDO 100  
26  
TX0  
23  
P03 / REMO  
P110 / RCK 24  
P111 / RCD  
52  
51  
P13  
P12  
/
/
COM5  
COM6  
/
/
RX1  
TX1  
25  
Figure 1 100-Pin LQFP Package of AP919  
Figure 2 Dice Form of AP919  
Revision 0.6  
Page 1 of 10  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
5. BLOCK DIAGRAM  
The following diagram shows the system blocks embedded in AP919.  
Figure 3 Internal Block Diagram of AP919  
6. BUILT IN PERIPHERALS  
High performance 8 bit CPU  
External interrupt  
o
Support C language programming  
o
4 channels  
32 kbyte one time program ROM  
1.5 kbyte data RAM  
Interrupt Controller  
IR remote control unit  
Buzzer unit  
o
output level control available  
o
10 priority levels  
Rotary type switch counter unit  
UART interface  
Watchdog reset  
o
2 units  
Real time clock  
Embedded RC oscillator  
Programmable timer  
I2C interface  
o
SPI interface  
o
2 channels  
1 channel  
o
LCD driver  
o
2 units  
Selectable oscillator option  
24 segment x 4 common or 6  
common, 1/3 bias LCD display  
o
o
o
XOSC : low speed 32.768kHz / 75kHz crystal  
OSC : high speed 3.6864 MHz crystal  
RCOSC: medium speed 1MHz  
internal RC oscillator  
DTS PLL unit  
6-bit ADC  
o
6 channels  
AC line frequency detection unit  
Revision 0.6  
Page 2 of 10  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
7. PIN DESCRIPTION  
Pin  
Name  
Alternative  
Function  
Type  
Drive  
(mA)  
Pullup  
/down  
Reset  
State  
Descriptions  
1
2
P90  
P91  
SPIDIO  
SPICLK  
IO,S  
IO,S  
2
2
PU  
PU  
Z
Z
General purpose IO port / SPI data IO  
General purpose IO port / SPI clock IO  
General purpose IO port / SPI data input / Auto-  
strobe output 0  
General purpose IO port / Auto-strobe output 1  
Active low chip reset input  
Low-voltage detect  
Analog supply voltage  
PLL filter  
Analog ground  
3
P92  
SPIDI / AST0  
AST1  
IO,S  
2
2
PU  
Z
Z
4
5
6
7
8
9
P93  
RSTB  
PWRDET  
AVDD  
PLLFLT  
AGND  
GND  
IO,S  
I,S  
IA  
PU  
U
OA  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
Ground  
OSCI  
OSCO  
VDD  
I
O
3.6864MHz oscillator input  
3.6864MHz oscillator output  
Power supply  
Power supply  
General purpose IO port pin  
General purpose IO port pin  
Watchdog enable ( active high)  
MCU external interrupt input pin  
MCU external interrupt input pin  
General purpose IO port / I2C0 clock output  
General purpose IO port / I2C0 data IO port  
General purpose IO port / PWMO  
General purpose IO port / Remote receiver input  
General purpose IO port or rotary switch counter  
input  
VPP  
P130  
P131  
WDTEN  
W0  
W1  
P00  
P01  
P02  
P03  
IO,S  
IO,S  
I,S  
I,S  
I,S  
IO,S  
IO,S  
IO,S  
IO,S  
2
2
PU  
PU  
U
PU  
PU  
PU  
PU  
PU  
PU  
Z
Z
I2CCLK0  
I2CDAT0  
PWMO  
2
2
2
2
Z
Z
Z
Z
REMO  
24  
25  
P110  
P111  
RCK  
RCD  
IO,S  
IO,S  
2
2
PU  
PU  
Z
Z
General purpose IO port or rotary switch counter  
input  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
P100  
P101  
P102  
P103  
VDD  
FMIN  
AMIN  
IFIN  
GND  
TX0  
RX0  
BOUT0  
PWMO  
IO,S  
IO,S  
IO,S  
IO,S  
2
2
2
2
PU  
PU  
PU  
PU  
Z
Z
Z
Z
General purpose IO port or UART0 TX output  
General purpose IO port or UART0 RX input  
General purpose IO port or UART0 clock output  
General purpose IO port pin / PWM output  
Power supply  
FM input clock  
AM input clock  
IF input clock  
ground  
DTS PLL control voltage output  
Active low chip test enable  
Active low chip test enable  
General purpose IO port pin / buzzer  
General purpose IO port pin  
MCU external interrupt input pin  
ADC input channel 0 / General purpose IO port  
ADC input channel 1 / General purpose IO port  
ADC input channel 2 / General purpose IO port  
ADC input channel 3 / General purpose IO port  
ADC input channel 4 / General purpose IO port  
ADC input channel 5 / General purpose IO port  
General purpose IO port pin / I2C1 clock output  
General purpose IO port pin / I2C1 data IO  
General purpose IO port pin / buzzer output  
General purpose IO port pin / UART1 clock *Note  
General purpose IO port / LCD common 6 / UART1  
TX *Note  
IA  
IA  
IA  
DTSPLLFLT  
TESTB2  
TESTB3  
P132  
OA  
I,S  
I,S  
IO,S  
IO,S  
I,S  
IO,S  
IO,S  
IO,S  
IO,S  
IO,S  
IO,S  
IO,S  
IO,S  
IO,S  
IO,S  
U
U
PU  
PU  
PU  
TONE  
2
2
Z
Z
P133  
W2  
ADCIO0  
ADCIO1  
ADCIO2  
ADCIO3  
ADCIO4  
ADCIO5  
P112  
P113  
P10  
P11  
2
2
2
2
2
2
2
2
2
2
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
I2CCLK1  
I2CDAT1  
TONE  
PU  
PU  
PU  
PU  
BOUT1  
51  
52  
P12  
P13  
COM6 / TX1  
COM5 / RX1  
IO,S,L  
IO,S,L  
2
2
PU  
PU  
Z
Z
General purpose IO port / LCD common 5 / UART1  
RX *Note  
53  
54  
55  
56  
57  
P20  
P21  
P22  
P23  
P30  
COM4  
COM3  
COM2  
COM1  
SEG1  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
2
2
2
2
2
PU  
PU  
PU  
PU  
PU  
Z
Z
Z
Z
Z
General purpose IO port / LCD common 4  
General purpose IO port / LCD common 3  
General purpose IO port / LCD common 2  
General purpose IO port / LCD common 1  
General purpose IO port / LCD segment 1  
Revision 0.6  
Page 3 of 10  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
Pin  
Name  
Alternative  
Function  
Type  
Drive  
(mA)  
Pullup  
/down  
Reset  
State  
Descriptions  
58  
59  
60  
61  
62  
63  
64  
65  
P31  
P32  
P33  
P40  
P41  
P42  
P43  
GND  
SEG2  
SEG3  
SEG4  
SEG5  
SEG6  
SEG7  
SEG8  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
2
2
2
2
2
2
2
PU  
PU  
PU  
PU  
PU  
PU  
PU  
Z
Z
Z
Z
Z
Z
Z
General purpose IO port / LCD segment 2  
General purpose IO port / LCD segment 3  
General purpose IO port / LCD segment 4  
General purpose IO port / LCD segment 5  
General purpose IO port / LCD segment 6  
General purpose IO port / LCD segment 7  
General purpose IO port / LCD segment 8  
Ground  
General purpose IO port / LCD segment 9/ 8-bit MPU  
interface  
General purpose IO port / LCD segment 10 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 11 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 12 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 13 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 14 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 15 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 16 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 17 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 18 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 19 / 8-bit  
MPU interface  
General purpose IO port / LCD segment 20 / 8-bit  
MPU interface  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
P50  
P51  
P52  
P53  
P60  
P61  
P62  
P63  
P70  
P71  
P72  
P73  
SEG9 / LCDD0  
SEG10 / LCDD1  
SEG11 / LCDD2  
SEG12 / LCDD3  
SEG13 / LCDD4  
SEG14 / LCDD5  
SEG15 / LCDD6  
SEG16 / LCDD7  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
2
2
2
2
2
2
2
2
2
2
2
2
PU  
PU  
PU  
PU  
PU  
PU  
PU  
PU  
PU  
PU  
PU  
PU  
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
SEG17 /  
LCDWRB  
SEG18 / LCDRDB  
SEG19 / LCDA0  
SEG20 / LCDCSB  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
P80  
P81  
P82  
SEG21  
SEG22  
SEG23  
SEG24  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
2
2
2
2
PU  
PU  
PU  
PU  
Z
Z
Z
Z
General purpose IO port / LCD segment 21  
General purpose IO port / LCD segment 22  
General purpose IO port / LCD segment 23  
General purpose IO port / LCD segment 24  
1/3 x VLCD voltage  
2/3 x VLCD voltage  
LCD driver supply voltage  
AC detection input  
P83  
VLCD2  
VLCD1  
VLCD  
ACIN  
P120  
P121  
P122  
P123  
W3  
TEST4  
ATONE  
VDD  
XOSCO  
XOSCI  
GND  
TESTB0  
TESTB1  
TEST5  
TESTOUT1  
I,S  
IO,S,L  
IO,S,L  
IO,S,L  
IO,S,L  
I,S  
U
TX1  
RX1  
BOUT1  
2
2
2
2
PU  
PU  
PU  
PU  
PU  
D
Z
Z
Z
Z
General purpose IO port / UART1 TX  
*Note  
General purpose IO port / UART1 RX  
*Note  
General purpose IO port / UART1 clock output  
*Note  
General purpose IO port  
MCU external interrupt input pin  
Active high chip test enable  
Buzzer output with level control  
Power supply  
32.768kHz / 75kHz oscillator output  
32.768kHz / 75kHz oscillator input  
Ground  
Active low chip test enable  
Active low chip test enable  
Active high chip test enable  
Chip test output  
I,S  
OA  
O
I
I,S  
I,S  
I,S  
O
U
U
D
2
0
I
O
IO  
IA  
OA  
- Input pin  
- Output pin  
- Bidirectional pin  
- Analog input pin  
- Analog output pin  
S
(P)U  
(P)D  
L
- CMOS Schmitt Trigger  
- (Programmable) Pull-up  
- (Programmable) Pull-down  
- LCD Pad  
0,1,Z - Logic state 0, Logic state 1,High impedance  
*Note:  
Depending on the UART1 control register’s content, either P12[2:0] or P1[3:1] can be used as the UART1 ports.  
Revision 0.6 Page 4 of 10 May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
8. ELECTRICAL SPECIFICATION  
8.1. Absolute Maximum Rating  
Item  
Symbol  
Rating  
Unit  
Power Supply Voltage (logic)  
Power Supply Voltage (analog)  
Power Supply Voltage (LCD)  
Input Voltage  
Power Dissipation (Ta = 70°C)  
Storage Temperature  
VDD  
AVDD  
VLCD/VLCD1/VLCD2  
-0.5 to 6.0  
-0.5 to 6.0  
-0.5 to 6.0  
-0.5 to VDD+0.5  
TBD  
V
V
V
VIN  
Pd  
TSTG  
Topr  
V
mW  
°C  
°C  
-20 to 125  
0 to 70  
Operating Temperature  
8.2. Recommended Operating Condition  
Item  
Symbol  
Min.  
Typ.  
Max.  
Unit  
Power Supply Voltage (logic)  
Power Supply Voltage (analog)  
Power Supply Voltage (LCD)  
VDD  
AVDD  
VLCD  
VLCD1  
VLCD2  
VIN  
3.0  
3.0  
-
3.6  
3.6  
V
V
V
-
-
-
-
-
-
VDD  
VLCD  
VLCD1  
VDD  
VDD  
70  
VLCD2  
0
0
0
0
Input Voltage (digital)  
Input Voltage (analog)  
Operating Temperature  
V
V
°C  
VIN  
TOPR  
8.3. Leakage Current and Capacitance  
Symbol Parameter  
Condition  
Min.  
Typ. Max.  
Unit  
IIN  
IOZ  
CIN  
CIN  
CBID  
Input current  
No pull-up or pull-down  
-10  
-10  
±1  
±1  
3.0  
3.0  
3.0  
10  
10  
A  
A  
pF  
pF  
pF  
Tri-state leakage current  
Input capacitance *Note1  
Output capacitance *Note1  
Bidirectional buffer capacitance *Note1  
*Note1: capacitance value are specified without the package  
8.4. DC Electrical Characteristics  
(VDD=3.3V±10%, AVDD=3.3V±10%, operating temperature = 0°C - 70°C unless specified otherwise)  
Symbol Parameter  
Condition  
Min.  
Typ.  
Max.  
Unit  
VDD  
Supply Voltage (logic)  
Core operating mode  
Clock mode  
3.0  
2.4  
-
3.6  
3.6  
V
AVDD  
Supply Voltage (analog)  
Core operating mode  
Clock mode  
3.0  
2.4  
-
3.6  
3.6  
V
VIH  
VIL  
RPU  
RPD  
VINA  
IOL  
Input high voltage  
Input low voltage  
Pull-up resistance  
Pull-down resistance  
FMIN,AMIN,IFIN input voltage  
Output low current  
Output high current  
Core operating current  
0.7*VDD  
-
-
-
-
V
V
0.3*VDD  
75k  
VIN = 0V  
VIN = VDD  
30k  
30k  
150  
45k  
45k  
75k  
mVpp  
mA  
mA  
mA  
A  
VOL = 0.4V  
VOH = VDD-0.4V  
*Note2  
2.8  
2.5  
7
IOH  
Idd_opr  
10  
100  
Idd_idle Clock Mode current  
80  
VDD=3.3V, T=25°C *Note3  
*Note2: LCD is ON. The CPU clock source is from the 3.6864 MHz oscillator pads. No active load is being  
driven. All inputs = 0V or VDD.  
*Note3: LCD is ON. The CPU clock source is from the 75 kHz oscillator pads. No active load is being driven. All  
inputs = 0V or VDD.  
Revision 0.6  
Page 5 of 10  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
9. BONDING AND PACKAGE INFORMATION  
9.1. Reference COB Layout Information  
Libraries of reference COB PCB layout and dice connection layout are available upon request.  
Revision 0.6  
Page 6 of 10  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
9.2. Package Information  
Revision 0.6  
Page 7 of 10  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
10.SOLDERING INDICATION  
This section gives a very brief insight to a complex technology. There is no soldering method that is ideal for all  
surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for  
fine pitch SMDs. In these situations reflow soldering is recommended.  
1. Reflow Soldering  
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stenciling or pressure-syringe dispensing before package placement.  
Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven.  
Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating  
method.  
Typical reflow peak temperatures range from 215 to 250°C. The top-surface temperature of the packages should  
preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages.  
2. Wave Soldering  
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and non-wetting can present major problems.  
To overcome these problems the double-wave soldering method was specifically developed.  
If wave soldering is used, the following conditions must be observed for optimal results:  
Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth  
laminar wave.  
For packages with leads on two sides and a pitch:  
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction  
of the printed-circuit board;  
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-  
circuit board.  
The footprint must incorporate solder thieves at the downstream end.  
For packages with leads on four sides, the footprint must be placed at a 45angle to the transport direction of the  
printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.  
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.  
Typical dwell time is 4 seconds at 250°C.  
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.  
3. Manual Soldering  
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron  
applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.  
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and  
320 °C.  
Revision 0.6  
Page 8 of 10  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
4. Suitability of Surface Mount IC Packages for Wave and Reflow Soldering Methods  
Soldering Method  
Wave  
Not suitable (2)  
Package  
Reflow (1)  
Suitable  
BGA, HBGA, LFBGA, SQFP, TFBGA  
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS  
PLCC (3), SO, SOJ  
Not suitable  
Suitable  
Suitable  
Suitable  
Suitable  
Suitable  
LQFP, QFP, TQFP  
SSOP, TSSOP, VSO  
Not recommended (3)(4)  
Not recommended (5)  
Notes  
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks  
may occur due to vaporization of the moisture in them (the so called popcorn effect).  
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at  
bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).  
3. If wave soldering is considered, the package must be placed at a 45angle to the solder wave direction. The package  
footprint must incorporate solder thieves downstream and at the side corners.  
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch equal to or larger than 0.8 mm; it is  
definitely not suitable for packages with a pitch equal to or smaller than 0.65 mm.  
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch equal to or smaller than 0.5 mm.  
Revision 0.6  
Page 9 of 10  
May 15, 2008  
AP919  
OTP Microcontroller with LCD Driver and  
Digital Tuning System for Docking Application  
Valence Semiconductor Design Limited  
Unit 2001, 20/F, APEC Plaza,  
49 Hoi Yuen Road, Kwun Tong, Hong Kong  
Tel: (852) 2797 3288  
Fax: (852) 2776 7770  
Email: inquiry@valencetech.com  
Website: http://www.valencetech.com  
IMPORTANT NOTICE  
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. ValenceTech Ltd. and its affiliates (“Valence”) believe that the  
information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).  
Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the  
terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by  
Valence for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document  
is the property of Valence and by furnishing this information, Valence grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other  
intellectual property rights. Valence owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your  
organization with respect to Valence integrated circuits or other products of Valence. This consent does not extend to other copying such as copying for general distribution, advertising or  
promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies  
described in this material and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and /or quota needs to be obtained from the  
competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the  
PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR  
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). VALENCE PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY  
APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT  
SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF VALENCE PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD  
TO BE FULLY AT THE CUSTOMER’S RISK AND VALENCE DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF  
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY VALENCE PRODUCT THAT IS USED IN SUCH  
A MANNER. IF THE CUSTOMER OR  
CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF VALENCE PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY VALENCE,  
ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT  
FROM OR ARISE IN CONNECTION WITH THESE USES.  
Revision 0.6  
Page 10 of 10  
May 15, 2008  

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