APL4500 [ETC]
PLL Module; PLL模块
ETC 
Plerow APL4500
PLL Module
Features
· -4 dBm Output Level at 4500 MHz
· Channel Step Size : 1000 kHz
· 2nd Harmonic : < 0 dBc
· Spurious Level : < -70 dBc
· Lock Time : < 10 ms
· 25 mA Current Consumption
Description
The plerowTM PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB’s PLL provides
exceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are
available in a surface-mount type package.
Specifications
Max.
Parameter
Frequency Range
Output Power
Unit
MHz
dBm
V
Min.
Typical
4500
-4
More Information
Website: www.asb.co.kr
E-mail: sales@asb.co.kr
-5
-3
5.3
35
Supply Voltage
4.7
5.0
25
Current Consumption
Channel Step Size
2nd Harmonics
mA
Tel: (82) 42-528-7220
Fax: (82) 42-528-7222
ASB, Inc., 4th Fl. Venture Town
Bldg, KT HRDC, 367-17
Goijeong-Dong, Seo-Gu,
Daejeon, 302-716, Korea
kHz
dBc
dBc
ms
1000
-4
0
Spurious Level
-78
3
-70
10
Lock Time
Reference Frequency
Reference Input Level
Phase Noise (C / N)
MHz
dBm
10
-5
0
5
@ 10 kHz
@ 100 kHz
dBc/Hz
dBc/Hz
Ω
-96
-93
-90
-123
-120
-117
Output Impedance
Operating Temp. Range
Package Type & Size
50
-40
25
85
°C
Mm
SMT, 19.0W×19.0L×5.8H
1) Measurement conditions are as follows: T = 25°C, VCC = 5 V, Freq. = 4500 MHz, 50 ohm system.
Outline Drawing
Top View
Bottom View
Dimension (mm)
Pin Configuration
CLOCK
A
B
C
D
E
F
G
H
I
19.0
19.0
5.8
1.5
0.5
1.75
1.35
15.0
0.9
1
2
3
4
9
D
E
F
DATA
ENABLE
OSC IN
A
VCC (VCO)
13
15
16
RF OUT
VCP (PLL)
LOCK DETECT
Ground
I
H
G
Others
Tolerance: ± 0.2
C
B
Side View
1/1
www.asb.co.kr
March 2004
相关型号：
APL502B2G
Power Field-Effect Transistor, 58A I(D), 500V, 0.09ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, ROHS COMPLIANT, TMAX-3
MICROSEMI
©2020 ICPDF网 联系我们和版权申明