AS29P200_技术文档

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• Organization: 256K×8 or 128K×16

• Sector architecture

• Low power consumption

- 20 mA typical read current

- One 16K; two 8K; one 32K; and three 64K byte sectors

- Boot code sector architecture—T (top) or B (bottom)

- Erase any combination of sectors or full chip

• Single 5.0±0.5V power supply for read/ write operations

• Sector protection

• High speed 55/ 70/ 90/ 120 ns address access time

• Automated on-chip programming algorithm

- Automatically programs/ verifies data at specified ad-

dress

• Automated on-chip erase algorith

- Automatically preprograms/ erases chip or specified sec-

tors

• 10,000 write/ erase cycle endurance

• Hardware RESET pin

- 30 mA typical program current

- 300 µA typical standby current

- 1 µA typical standby current (RESET = 0)

• JEDEC standard software, packages and pinouts

- 48-pin TSOP

- 44-pin SO

• Detection of program/ erase cycle completion

- DQ7 DATApolling

- DQ6 toggle bit

- RY/ BY output

• Erase suspend/ resume

- Supports reading data from a sector not being erased

• Low V write lock-out below 2.8V

CC

- Resets internal state machine to read mode

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48-pin TSOP

44-pin SO

Sector protect

switches

RY/ BY

DQ0–DQ15

V

CC

V

SS

NC

RY/ BY

NC

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

RESET

WE

A8

Erase voltage

generator

Input/ output

buffers

2

RESET

3

A7

4

A9

Program/ erase

control

WE

BYTE

A6

5

A10

A11

A12

A13

A14

A15

A16

BYTE

A5

6

A4

7

Program voltage

generator

AS29F200

Command

register

A3

8

A2

A1

A0

CE

9

10

11

12

13

14

15

16

17

18

19

20

21

22

STB

Chip enable

Output enable

Logic

Data latch

CE

OE

A-1

V

SS

OE

DQ0

DQ15/ A-1

DQ7

Y decoder

Y gating

STB

DQ8

DQ14

DQ6

DQ1

DQ9

DQ13

DQ5

V

detector

Timer

CC

DQ2

X decoder

Cell matrix

DQ10

DQ3

DQ12

DQ4

A0–A16

DQ11

V

CC

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29F200-55 29F200-70 29F200-90 29F200-120 Unit

Maximum access time

t_AA

t_CE

t_OE

55

25

70

30

90

35

120

50

ns

Maximum chip enable access time

Maximum output enable access time

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The AS29F200 is a 2 megabit, 5 volt only Flash memory organized as 256K bytes of 8 bits each or 128K words of 16 bits each. For flexible

erase and program capability, the 2 megabits of data is divided into 7 sectors: one 16K byte, two 8K byte, one 32K byte, and three 64K bytes.

The ×8 data appears on DQ0–DQ7; the ×16 data appears on DQ0–DQ15. The AS29F200 is offered in JEDEC standard 44-pin SO and 48-pin

TSOP packages. This device is designed to be programmed and erased in-system with a single 5.0V V_CCsupply. The device can also be

reprogrammed in standard EPROM programmers.

The AS29F200 offers access times of 55/ 70/ 90/ 120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus

contention the device has separate chip enable ( CE), write enable ( WE), and output enable ( OE) controls. Word mode (×16 output) is

selected by BYTE = High.

The AS29F200 is fully compatible with the JEDEC single power supply Flash standard. Write commands to the command register using

standard microprocessor write timings. An internal state-machine uses register contents to control the erase and programming circuitry.

Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data from the device in the same

manner as other Flash or EPROM devices. Use the program command sequence to invoke the automated on-chip programming algorithm

that automatically times the program pulse widths and verifies proper cell margin. Use the erase command sequence to invoke theautomated

on-chip erase algorithm that preprograms the sector if it is not already programmed before executing the erase operation, times the erase

pulse widths, and verifies proper cell margin.

Boot sector architecture enables the device to boot from either the top (AS29F200T) or bottom (AS29F200B) sector. Sector erase architecture

allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically erases and

verifies within 1.6 seconds. Hardware sector protection disables both program and erase operations in all or any combination of the seven

sectors. The device provides background erase with Erase Suspend, which puts erase operations on hold to read data from a sector that is not

being erased. The chip erase command will automatically erase all unprotected sectors.

A factory shipped AS29F200 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one

byte/ word at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes/

words in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors.

The device features single 5.0V power supply operation for both read and write functions. Internally generated and regulated voltages are

provided for the program and erase operations. A low V_CCdetector automatically inhibits write operations during power transtitions. The

RY/ BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase operations. The device automatically

resets to the read mode after program/ erase operations are completed.

The AS29F200 resists accidental erasure or spurious programming signals resulting from power transitions. Control register architecture

permits alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set

to read mode with all program/ erase commands disabled when V_CCis less than V_LKO(lockout voltage). The command registers are not

affected by noise pulses of less than 5 ns on OE, CE, or WE. CE and WE must be logical zero and OE a logical one to initiate write commands.

When the device’s hardware RESET pin is driven low, any program/ erase operation in progress will be terminated and the internal state

machine will be reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated on-

chip program/ erase algorithm, data in address locations being operated on will become corrupted and require rewriting. Resetting the

device enables the system’s microprocessor to read boot-up firmware from the Flash memory.

The AS29F200 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes/ words are programmed

one at a time using EPROM programming mechanism of hot electron injection.

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Bottom boot sector architecture (AS29F200B)

Top boot sector architecture (AS29F200T)

Size

Sector

×8

×16

(Kbytes)

×8

×16

(Kbytes)

0

1

2

3

4

5

6

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

16

8

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–37FFFh

38000h–39FFFh

3A000h–3BFFFh

3C000h–3FFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1BFFFh

1C000h–1CFFFh

1D000h–1DFFFh

1E000h–1FFFFh

64

32

8

32

64

8

16

In word mode, there are one 8K word, two 4K word, one 16K word, and three 32K word sectors. Address range is A16–A-1 if BYTE = V ; address range is

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A16–A0 if BYTE = V .

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Bottom boot sector address (AS29F200B)

Top boot sector address (AS29F200T)

Sector

A16

0

A15

0

A14

0

A13

0

A12

X

0

A16

0

A15

0

A14

X

0

A13

X

0

A12

X

0

1

2

3

4

5

6

0

1

0

1

0

1

0

1

X

1

0

1

X

1

0

1

0

1

X

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Mode

CE

L

OE

L

WE

A0

A1

L

A6

L

A9

RESET

H

DQ

ID read MFR code

ID read device code

Read

H

L

V

Code

ID

L

H

A0

X

A0

L

V

H

Code

ID

L

H

A1

X

A6

X

A6

L

A9

X

H

D_OUT

High Z

Standby

H

L

X

H

X

H

Output disable

Write

H

X

H

L

A1

H

A9

H

D

IN

Enable sector protect

Sector unprotect

Verify sector protect

L

V

Pulse/ L

H

V

H

X

ID

L

V

L

H

L

V

H

X

ID

L

H

V

H

Code

ID

Temporary sector

unprotect

X

V

X

ID

Hardware Reset

X

L

High Z

L = Low (<V ); H = High (>V ); V = 12.0 ± 0.5V; X = don’t care; In ×16 mode, BYTE = V . In ×8 mode, BYTE = V and DQ8–14 is High Z with

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ID

IH

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DQ15 = A-1(X).

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Item

Description

Selected by A9 = V (11.5–12.5V), CE = OE = A1 = A6 = L, enabling outputs.

ID

ID MFR code,

device code

When A0 is low (V ) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.

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When A0 is high (V ), D_OUTrepresents the device code for the AS29F200.

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Selected with CE = OE = L, WE = H. Data is valid in t_ACCtime after addresses are stable, t_CEafter CE is low

and t_OEafter OE is low.

Read mode

Standby

Selected with CE = H. Part is powered down, and I_CCreduced to <2.0 mA for TTL input levels. If activated

during an automated on-chip algorithm, the device completes the operation before entering standby.

Output disable Part remains powered up; but outputs disabled with OE pulled high.

Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command

register. Contents of command register serve as inputs to the internal state machine. Address latching occurs

on the falling edge of WE or CE, whichever occurs late . Data latching occurs on the rising edge WE or CE,

Write

whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.

Enable

Hardware protection circuitry implemented with external programming equipment causes the device to

sector protect disable program and erase operations for specified sectors.

Sector

unprotect

Disables sector protection for all sectors using external programming equipment. All sectors must be

protected prior to sector unprotection.

Verifies write protection for sector. Sectors are protected from program/ erase operations on commercial

programming equipment. Determine if sector protection exists in a system by writing the ID read command

Verify

sector protect sequence and reading location XXX02h, where address bits A12–16 select the defined sector addresses. A

logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.

Temporarily disables sector protection for in-system data changes to protected sectors. Apply +12V to RESET

to activate sector unprotect mode. During temporary sector unprotect mode, program protected sectors by

selecting the appropriate sector address. All protected sectors revert to protected state on removal of +12V

from RESET.

Temporary

sector

unprotect

Resets the write and erase state machine to read mode. If device is programming or erasing when

RESET = L, data may be corrupted.

RESET

Deep

Hold RESET low to enter deep power down mode (<10 µA CMOS). Recovery time to active mode is 1.5 µs.

power down

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Mode

A16–A12

A6

L

A1

L

A0

L

Code

52h

MFR code (Alliance Semiconductor)

X

×8 T boot

×8 Bboot

×16 T boot

×16 B boot

L

H

51h

L

57h

Device code

L

2251h

2257h

L

01h protected

00h unprotected

Sector protection

Sector address

L

H

L

Key: L =Low (<V ); H = High (>V ); X =Don’t care; T = top; B = botto

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Status

DQ7

DQ6

DQ5

DQ3

DQ2

RY/ BY

Auto programming (byte/ word) DQ7

Toggle

No toggle

0

1

0

No toggle

Toggle^†

Toggle

0

1

Program/ erase in auto erase

Read erasing sector

0

1

In progress

Erase

suspend

mode

Read non-erasing

sector

Data

DQ7

Data

0

Data

0

Data

1

0

Program in erase

suspend

Toggle

Toggle^†

Auto programming (byte/ word) DQ7

Toggle

1

NA

1

No toggle

Toggle^‡

No toggle^‡

1

Exceeded time limits

Program/ erase in auto erase

Program in erase suspend

0

DQ7

NA

†

Toggles with OE or CE only for erasing or erase suspended sector addresses.

‡

Toggles only if DQ5 = 1 and address applied is within sector that exceeded timing limits.

DQ8–DQ15 = Don’t care in ×16 mode.

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Item

Description

Initiate read or reset operations by writing the Read/ Reset command sequence into the command

register. This allows the microprocessor to retrieve data from the memory. Device remains in read

mode until command register contents are altered.

Reset/ Read

Device automatically powers up in read/ reset state. This feature allows only reads, therefore

ensuring no spurious memory content alterations during power up.

AS29F200 provides manufacturer and device codes in two ways. External PROM programmers

typically access the device codes by driving +12V on A9. AS29F200 also contains an ID read

command to read the device code with only +5V, since multiplexing +12V on address lines is

generally undesirable.

Initiate device ID read by writing the ID Read command sequence into the command register.

Follow with a read sequence from address XX00h to return MFG code. Follow ID read command

sequence with a read sequence from address XX01h to return device code.

ID Read

To verify write protect status on sectors, read address XX02h. Sector addresses A16–A12 produce a

1 on DQ0 for protected sector and a 0 for unprotected sector.

Exit from ID read mode with Read/ Reset command sequence.

Holding RESET low for 500 ns resets the device, terminating any operation in progress; data

handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven

low. RY/ BY remains low until the RESET operation is completed. After RESET is set high, there is a

delay of 1.5 µs for the device to permit read operations.

Hardware Reset

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Item

Description

Programming the AS29F200 is a four bus cycle operation performed on a byte-by-byte or word-

by-word basis.Two unlock write cycles precede the Program Setup command and program data

write cycle. Upon execution of the program command, no additional CPU controls or timings are

necessary. Addresses are latched on the falling edge of CE or WE (whichever is last); data is latched

on the rising edge of CE or WE, (whichever is first). The AS29F200’s automated on-chip program

algorithm provides adequate internally-generated programming pulses and verifies the

programmed cell margin.

Check programming status by sampling data on the DATA polling (DQ7), toggle bit (DQ6), orRY/

BY pin. The AS29F200 returns the equivalent data that was written to it (as opposed to

complemented data), to complete the programming operation.

Byte/ word

Programming

The AS29F200 ignores commands written during programming. A hardware reset occurring

during programming may corrupt the data at the programmed location.

AS29F200 allows programming in any sequence, across any sector boundary. Changing data from 0

to 1 requires an erase operation. Attempting to program data 0 to 1 results in DQ5 = 1 (exceeded

programming time limits); reading this data after a Read/ reset operation returns a 0. When

programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a

reset command returns the device to read mode.

Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional

unlock write cycles; and finally the Chip Erase command.

Chip erase does not require logical 0s written prior to erasure. When the automated on-chip erase

algorithm is invoked with the Chip Erase command sequence, AS29F200 automatically programs

and verifies the entire memory array for an all-zero pattern prior to erase. The AS29F200 returns to

read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time

limit.

Chip Erase

Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional

unlock write cycles, and finally the Sector Erase command. Determine the sector to be erased by

addressing any location in the sector. This address is latched on the falling edge of WE; the

command, 30H is latched on the rising edge of WE. The sector erase operation begins after a 80 µs

time-out.

To erase multiple sectors, write the sector erase command to each of the addresses of sectors to

erase after following the six bus cycle operation above. Timing between writes of additional sectors

must be <80 µs, or the AS29F200 ignores the command and erasure begins. During the

time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase

or Erase Suspend) during time-out resets the AS29F200 to read mode, and the device ignores the

sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on

the ignored sectors.

Sector Erase

The entire array need not be written with 0s prior to erasure. AS29F200 writes 0s to the entire

sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected

sectors unaffected. AS29F200 requires no CPU control or timing signals during sector erase

operations.

Automatic sector erase begins after erase time-out from the last rising edge of WE from the sector

erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address

must be performed on addresses that fall within the sectors being erased. AS29F200 returns to read

mode after sector erase unless DQ5 is set high by exceeding the time limit.

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Item

Description

Erase suspend allows interruption of sector erase operations to perform data reads from a sector not

being erased. Erase suspend applies only during sector erase operations, including the time-out

period. Writing an Erase Suspend command during sector erase time-out results in immediate

termination of time-out period and suspension of erase operation.

AS29F200 ignores any commands during erase suspend other than the Reset or Erase Resume

commands. Writing erase resume continues erase operations. Addresses are DON’T CARE when

writing Erase Suspend or Erase Resume commands.

AS29F200 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command.

Check completion of erase suspend by polling RY/ BY. Check DQ2 in conjunction with DQ6 to

determine if a sector is being erased. AS29F200 ignores redundant writes of erase suspend.

Erase Suspend

AS29F200 defaults to erase-suspend-read mode while an erase operation has been suspended.

While in erase-suspend-read mode AS29F200 allows reading data from or programming data to

any sector not undergoing sector erase.

Write the Resume command 30h to continue operation of sector erase. AS29F200 ignores

redundant writes of the Resume command. AS29F200 permits multiple suspend/ resume

operations during sector erase.

When attempting to write to a protected sector, DATA polling andToggle Bit 1 (DQ6) are activated

for about <1 µs. When attempting to erase a protected sector, DATA polling and

Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode

without altering the specified sectors.

Sector Protect

Ready/ Busy

RY/ BY indicates whether an automated on-chip algorithm is in progress (RY/ BY = low) or

completed (RY/ BY = high). The device does not accept program/ erase commands when

RY/ BY = low. RY/ BY= high when device is in erase suspend mode. RY/ BY is an open drain output,

enabling multiple RY/ BY pins to be tied in parallel with a pull up resistor to V_CC.

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Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects

complement of data last written when read during the automated on-chip algorithm (0 during

erase algorithm); reflects true data when read after completion of an automated on-chip algorithm

(1 after completion of erase agorithm).

DATA polling (DQ7)

Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE or OE

toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth

pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase;

after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6

toggles for only <1 µs during writes, and <5 µs during erase (if all selected sectors are protected).

Toggle bit (DQ6)

Indicates unsuccessful completion of program/ erase operation (DQ5 = 1). DATA polling remains

active; CE powers the device down to 2 mA. If DQ5 = 1 during chip erase, all or some sectors are

defective; during byte programming, the entire sector is defective; during sector erase, the sector is

defective (in this case, reset the device and execute a program or erase command sequence to

continue working with functional sectors). Attempting to program 0 to 1 will set DQ5 = 1.

Exceeding time limit

(DQ5)

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Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands

will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and

after each sector erase command to verify that the command was accepted.

Sector erase timer

(DQ3)

During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being

erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles

only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use

DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend

mode.

Toggle bit 2 (DQ2)

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2nd bus

3rd bus

4th bus

5th bus

6th bus

1st bus write cycle

write cycle

read/ write cycle

write cycle

Required

Command sequence bus cycles Address Data Address Data Address Data Address

Data Address Data Address Data

Read

Reset/ Read

1

XXXXh

F0h

Read Data

Address

2AAAh

5555h

×16

×8

5555h

AAAAh

5555h

AAAAh

Read

Address

Read

Data

Reset/ Read

4

AAh

55h

F0h

90h

2251h(T)

2257h (B)

×16

5555h

AAAAh

2AAAh

5555h

AAAAh

01h

02h

51h (T)

57h (B)

×8

Autoselect

ID Read

4

AAh

55h

00h

MFR code

×16/ ×8

52h

×16

×8

XXX02h

XXX04h

01 = protected

00 = unprotected

×16

×8

5555h

AAAAh

5555h

AAAAh

5555h

AAAAh

XXXXh

2AAAh

5555h

2AAAh

5555h

2AAAh

5555h

AAAAh

5555h

AAAAh

5555h

AAAAh

Program

Address

Program

Data

Program

4

6

AAh

55h

A0h

80h

×16

×8

5555h

AAAAh

5555h

AAAAh

2AAAh

5555h

AAAAh

Chip Erase

Sector Erase

AAh

55h

10h

30h

5555h

2AAAh

5555h

×16

×8

Sector

Address

Sector Erase Suspend

Sector Erase Resume

1

B0h

30h

1

2

3

4

5

6

Bus operations defined in "Mode definitions," on page 4.

Reading data from or programming data to non-erasing sectors allowed in Erase Suspend mode.

Address bit A15 = X = Don’t care for all address commands except Program Address and Sector Address.

Address bit A16 = X = Don’t care for all address commands except Program Address and Sector Address.

System should generate address patterns: ×16 mode - 5555h or 2AAAh to address A0–A14; ×8 mode - AAAAh or 5555h to address A-1–A14.

A = 0, A = 1, A = 0 for sector protect verify; sector selected on A16-A12.

0

1

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Write erase command sequence

(see below)

Write program command sequence

(see below)

DATA polling or toggle bit

successfully completed

DATA poll device

Erase complete

Chip erase command sequence

×16 mode (address/ command):

Sector erase command sequence

×16 mode (address/ command):

NO

Verify byte?

5555h/ AAh

2AAAh/ 55h

5555h/ 80h

5555h/ AAh

2AAAh/ 55h

5555h/ 10h

5555h/ AAh

YES

2AAAh/ 55h

Programming completed

5555h/ 80h

Program command sequence

×16 mode (address/ command):

5555h/ AAh

2AAAh/ 55h

5555h/ A0h

Sector address/ 30h

Program address/ program data

Optional multiple

sector erase commands

†

The system software should check the status of DQ3 prior to and

following each subsequent sector erase command to ensure command

completion. The device may not have accepted the command if DQ3 is

high on second status check.

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Read byte (DQ0–DQ7)

Address = don’t care

†

Address = VA

DQ7

=

DQ6

YES

NO

=

DONE

data

toggle

?

NO

YES

DQ5

=

DQ5

=

NO

1

?

YES

Read byte (DQ0–DQ7)

Address = VA

Read byte (DQ0–DQ7)

Address = don’t care

DQ7

data^‡

?

DQ6

†

YES

NO

=

DONE

†

toggle

?

†

NO

FAIL

YES

FAIL

†

‡

VA = Byte address for programming. VA = any of the sector

addresses within the sector being erased during Sector Erase. VA

= valid address equals any non-protected sector group address

during Chip Erase.

^†DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling

when DQ5 changes to 1.

DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not

change simultaneously.

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Parameter

Symbol

t_VIDR

t_RSP

All speeds

500 (min)

4 (min)

Unit

ns

V_IDrise and fall time

RESET# setup time for temporary sector unprotect

µs

7HPSRUDU\#VHFWRU#XQSURWHFW#ZDYHIRUP#

10V

0 or 1.8V

RESET

Program/ erase command sequence

t_VIDR

CE

WE

t_RSP

RY/ BY

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Parameter

9_&&# #813±3189

Symbol Test conditions

Min

-

Max

Unit

µA

mA

µA

V

Input load current

I_LI

V

_IN= V_SSto V_CC, V_CC= V_CCMAX

V_CC= V_CCMAX, A9 = 12.5V

_OUT= V to V_CC, V_CC= V_CCMAX

±1

A9 Input load current

Output leakage current

Output short circuit current¹

Active current, read @ 6MHz²

Active current, program/ erase³

Standby current (TTL compatible)

Deep power down

I_LIT

I_LO

I_OS

I_CC

I_CC2

I_SB1

I_SB2

90

V

-

±1

SS

V_OUT= 0.5V

-

200

40

CE = V , OE = V

-

IL

IH

CE = V , OE = V

-

60

IL

IH

CE = OE = V , V_CC= V

-

400

1

IH

CCMAX

RP = 0V

-

Input low voltage

V

-0.5

2.0

0.8

V_CC+ 0.3

0.45

-

IL

Input high voltage

V

IH

Output low voltage

V

I_OL= 5.8mA, V_CC= V_{CC MIN}

I_OH= -2.5 mA, V_CC= V_{CC MIN}

-

V

OL

V

2.4

V

OH1

Output high level

V

I_OH= -100 µA, V_CC= V

V_CC- 0.4

2.8

-

V

OH2

CC MIN

Low V_CClock out voltage

Input HV select voltage

V_LKO

4.2

12.5

V

11.5

V

h

1

2

3

Not more than one output tested simultaneously. Duration of the short circuit must not be >1 second.

= 0.5V was selected to avoid test problems

OUT

caused by tester ground degradation. (This parameter is sampled and not 100% tested, but guaranteed by characterization.)

The I current listed includes both the DC operating current and the frequency dependent component (@ 6 MHz). The frequency componenttypically

CC

is less than 2 mA/ MHz with OE at V .

IH

I

active while program or erase operations are in progress.

CC

.H\#WR#VZLWFKLQJ#ZDYHIRUPV

Rising input

Falling input

Undefined output/ don’t care

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20 ns 20 ns 20 ns

+0.8V

-0.5V

-2.0V

0D[LPXP#SRVLWLYH#RYHUVKRRW#ZDYHIRUP

V +2.0V

CC

V +0.5V

CC

+2.0V

20 ns 20 ns 20 ns

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-55

-70

-90

-120

JEDEC Std

Symbol Symbol

Parameter

Min Max Min Max Min Max Min Max Unit

t_AVAVt_RC

Read cycle time

55

-

70

-

90

-

120

-

ns

t_AVQVt_ACC

t_ELQVt_CE

t_GLQVt_OE

t_EHQZt_DF

t_GHQZt_DF

Address to output delay

Chip enable to output

Output enable to output

Chip enable to output High Z

Output enable to output High Z

55

25

15

70

30

20

90

35

20

-

120

50

-

30

-

30

Output hold time from addresses,

first occurrence of CE or OE

t_AXQXt_OH

0

-

0

-

0

-

0

-

ns

t_{ELFL/ ELFH}CE to BYTE transition low/ high

-

5

1.5

55

-

5

1.5

70

-

5

1.5

90

-

5

1.5

120

-

ns

µs

ns

t_PHQVt_PWH

t_BDEL

t_FLQZ

RESET high to output delay

BYTE switching to valid data

BYTE low to DQ8–DQ15 tri-state

-

30

35

50

5HDG#ZDYHIRUP

t_RC

Addresses stable

t_ACC

Addresses

CE

t_DF

t_OE

OE

t_OEH

WE

t_OH

Output valid

t_CE

High Z

Outputs

BYTE

t_{ELFL/ ELFH}

t_BDEL

t_PWH

RESET

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-70

-90

-120

JEDEC

Std

Symbol Symbol

Parameter

Min Max Min Max Min Max Min Max

Unit

ns

t_AVAV

t_WC

t_AS

t_AH

t_DS

t_DH

t_OES

Write cycle time

55

0

-

70

0

-

90

0

-

120

0

-

t_AVWL

t_WLAX

t_DVWH

t_WHDX

Address setup time

Address hold time

Data setup time

ns

40

25

0

45

30

0

45

0

50

0

ns

Data hold time

ns

Output enable setup time

Output enable hold time: Read

0

ns

0

ns

t_OEH

Output enable hold time:

Toggle and DATA polling

10

-

10

-

10

-

10

-

ns

t_READY

t_RP

t_GHWL

t_CS

RESET pin low to read mode

RESET

20

500

0

-

20

500

0

-

20

500

0

-

20

500

0

-

µs

ns

µs

sec

t_GHWL

t_ELWL

Read recover time before write

CE setup time

0

t_WHEH

t_WLWH

t_WHWL

t_CH

CE hold time

0

t_WP

Write pulse width

Write pulse width high

35

20

50

0.3

35

20

50

0.3

45

20

50

0.3

50

20

50

0.3

t_WPH

t_WHWH1t_WHWH1Programming pulse time

t_WHWH2t_WHWH2Erase pulse time

:ULWH#ZDYHIRUP

:(#FRQWUROOHG

3rd bus cycle

t_AS

DATA polling

t_WC

5555h

Program address

t_AH

Program address

Addresses

CE

t_CH

t_GHWL; t_OES

OE

t_WP

t_{WHWH1 or 2}

WE

t_CS

t_WPH

t_DH

Program

data

A0h

DQ7

D

OUT

DATA

t_DS

V

SS

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-70

-90

-120

JEDEC

Std

Symbol Symbol

Parameter

Min Max Min Max Min Max Min Max

Unit

ns

t_AVAV

t_AVEL

t_ELAX

t_DVEH

t_EHDX

t_WC

t_AS

t_AH

t_DS

t_DH

t_OES

Write cycle time

55

0

-

70

0

-

90

0

-

120

0

-

Address setup time

Address hold time

Data setup time

ns

40

30

0

45

30

0

45

0

50

0

ns

Data hold time

ns

Output enable setup time

Output enable hold time: Read

0

ns

0

ns

t_OEH

Output enable hold time:

Toggle and DATA polling

10

-

10

-

10

-

10

-

ns

t_GHEL

t_WLEL

t_EHWH

t_ELEH

t_GHEL

t_WS

t_WH

t_CP

Read recover time before write

WE setup time

0

-

0

-

0

-

0

-

ns

µs

sec

WE hold time

0

CE pulse width

35

20

50

0.3

35

20

50

0.3

45

20

50

0.3

50

20

50

0.3

t_EHEL

t_CPH

CE pulse width high

t_WHWH1t_WHWH1Programming pulse time

t_WHWH2t_WHWH2Erase pulse time

:ULWH#ZDYHIRUP#5

&(#FRQWUROOHG

DATA polling

Addresses

WE

5555h

t_WC

Program address

t_AH

t_AS

t_GHEL, t_OES

OE

t_WH

t_CP

t_{WHWH1 or 2}

CE

t_CPH

t_WS

t_DH

Program

DATA

A0h

t_DS

DQ7

D

OUT

data

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t_WC

t_AS

Addresses

CE

5555h

2Ah

5555h

2Ah

Sector address

t_AH

t_GHWL

OE

t_WP

t_WC

WE

t_WPH

t_CS

10h for Chip Erase

t_DH

Data

AAh

55h

80h

AAh

55h

30h

t_DS

5(6(7#ZDYHIRUP

CE

RY/ BY

RESET

t_RP

t_READY

5<2%<#ZDYHIRUP

CE

Rising edge of last WE signal

WE

Program/ erase

operation

RY/ BY

tri-stated open-drain

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t_CH

CE

t_DF

t_OE

OE

t_OEH

WE

t_CE

t_OH

Output

High Z

DQ7

Input DQ7

Output DQ7

t_{WHWH1 or 2}

7RJJOH#ELW#ZDYHIRUP

CE

t_OEH

WE

OE

DQ6

t_DH

t_OE

(UDVH#DQG#SURJUDPPLQJ#SHUIRUPDQFH

Limits

Parameter

Min

Typical

1.6

60

Max

Unit

sec

Sector erase and verify-1 time (excludes 00h programming prior to erase)

Word programming time

-

µs

Byte program time

-

60

-

µs

Chip programming time

7.5

-

sec

Erase/ program cycles

10,000

cycles

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Device underTest

®

Test condition

-170

-200

1 TTL gate

5

Unit

100 pF*

Output load

Input rise and fall times

Input pulse levels

ns

V

V_SS

0.0-2.0

*including scope

and jig capacitance

Input timing measurement reference levels

Output timing measurement reference levels

1.0

5HFRPPHQGHG#RSHUDWLQJ#FRQGLWLRQV

Parameter

Symbol

V_CC

Min

+4.5

0

Typical

Max

+5.5

0

Unit

V

5.0

0

Supply voltage

Input voltage

V_SS

V

2.0

-

V_CC+ 0.5

0.8

V

IH

V

–0.5

-

IL

$EVROXWH#PD[LPXP#UDWLQJV

Parameter

Symbol

Min

–2.0

-0.5

–55

–65

-

Max

Unit

V

Input voltage (Input or DQ pin)

Input Voltage (A9 pin, OE, RESET)

Power supply voltage

V

+7.0

+13.0

+5.5

+125

+150

200

IN

V

IN

V_CC

V

Operating temperature

T_OPR

T_STG

I_OUT

°C

mA

Storage temperature (Plastic)

Short circuit output current

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions outside those indicated in the operational sections of this specification is notimplied. Exposure to absolute max-

imum rating conditions for extended periodsmay affect reliability.

/DWFKXS#WROHUDQFH#

Parameter

Min

-1.0

-100

Max

Unit

V

Input voltage with respect to V on A9, OE, and RESET pin

+13.0

V_CC+1.0

+100

SS

Input voltage with respect to V on all DQ, address and control pins

V

SS

Current

mA

Includes all pins except V . Test conditions: V = 5.0V, one pin at a time.

CC

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Symbol

Parameter

Test setup

Typ

6

Max

7.5

12

Unit

pF

C

Input capacitance

V

_IN= 0

_OUT= 0

_IN= 0

IN

C_OUT

Output capacitance

Control pin capacitance

V

8.5

8

pF

C

V

10

µF

IN2

62#SLQ#FDSDFLWDQFH

Symbol

Parameter

Test setup

_IN= 0

_OUT= 0

_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C

Input capacitance

V

IN

C_OUT

Output capacitance

Control pin capacitance

V

8.5

8

pF

C

V

10

µF

IN2

'DWD#UHWHQWLRQ

Temp.

(°C)

Parameter

Min

10

Unit

years

150°

125°

Minimum pattern data retention time

20

4;

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h

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

48-pin TSOP

min

max

(mm)

9

10

11

a

b

c

d

e

f

1.20

0.25

j

48-pin TSOP

12

13

14

15

16

17

18

19

20

21

22

23

24

g

0.50

0.1

0.70

0.21

18.30

19.80

11.90

0.95

18.50

20.20

12.10

1.05

g

h

i

e

f

i

0.05

0.15

d

j

0.50

a

0–5°

c

b

w

44-pin SO

0–8°

min

max

u

(mm)

m

n

o

p

q

r

28.00

0.35

0.10

2.17

28.40

0.50

0.35

2.45

2.80

22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3 2 1

44-pin SO

s

t

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

r

1.27

13.10

15.70

0.06

s

13.50

16.30

1.00

p

q

t

u

w

n

o

0.10

0.21

m

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55 ns

70 ns

90 ns

120 ns

Package \ Access Time

(commercial/ industrial)

AS29F200B-55TC

AS29F200B-55TI

AS29F200B-70TC

AS29F200B-70TI

AS29F200B-90TC

AS29F200B-90TI

AS29F200B-120TC

AS29F200B-120TI

TSOP, 12×20 mm, 48-pin

SO, 600 mil wide, 44-pin

AS29F200T-55TC

AS29F200T-55TI

AS29F200T-70TC

AS29F200T-70TI

AS29F200T-90TC

AS29F200T-90TI

AS29F200T-120TC

AS29F200T-120TI

AS29F200B-55SC

AS29F200B-55SI

AS29F200B-70SC

AS29F200B-70SI

AS29F200B-90SC

AS29F200B-90SI

AS29F200B-120SC

AS29F200B-120SI

AS29F200T-55SC

AS29F200T-55SI

AS29F200T-70SC

AS29F200T-70SI

AS29F200T-90SC

AS29F200T-90SI

AS29F200T-120SC

AS29F200T-120SI

3DUW#QXPEHULQJ#V\VWHP

AS29

X

200

X

–XXX

X

C

F = 5V

LV = 3V

LL = 2.5V

Temperature range

Device

number

B (bottom) or

T (top) boot block

Package:

S= SO

T= TSOP

Flash EEPROM prefix

Address access time

C = Commercial, 0°C to 70 °C

I = Industrial, -40°C to 85°C

53

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型号：	AS29P200
厂家：	ETC
描述：	5V 256K x 8 / 128K x 16 CMOS Flash EEPROM 5V 256K ×8 / 128K ×16的CMOS闪存EEPROM\n 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总20页 (文件大小：357K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AS29P200 [ETC]

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