ASX340CS2C00SPEA0-E [ETC]
1/4-Inch Color NTSC/PAL Digital Image SOC with Overlay Processor;型号: | ASX340CS2C00SPEA0-E |
厂家: | ETC |
描述: | 1/4-Inch Color NTSC/PAL Digital Image SOC with Overlay Processor |
文件: | 总78页 (文件大小:2762K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Aptina Confidential and Proprietary
Preliminary‡
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Features
1/4-Inch Color NTSC/PAL Digital Image SOC with
Overlay Processor
ASX340/MT9V139 Data Sheet
For the latest data sheet, refer to Aptina’s Web site: www.aptina.com
Features
Table 1:
Key Parameters
Typical Value
• Low-power image sensor with integrated image flow
processor (IFP) and video encoder
• 1/4-inch optical format, VGA resolution (640H x
480V)
Parameter
Pixel size
and type
5.6μm x 5.6μm active pinned-photodiode
with high-sensitivity mode for low-light
conditions
• 2x upscaling zoom and pan control
•
40 additional columns and 36 additional rows to
compensate for lens alignment tolerances
Sensor format
728H x 560V (includes 36 rows and 40
columns for lens alignment)
• Option to use single 2.8V power supply with off-chip
bypass transistor
• Overlay generator for dynamic bitmap overlay
• Integrated video encoder for NTSC/PAL with overlay
capability and 10-bit I-DAC
• Integrated microcontroller for flexibility
• On-chip image flow processor performs
sophisticated processing, such as color recovery and
correction, sharpening, gamma, lens shading
correction, on-the-fly defect correction, auto white
balancing, and auto exposure
NTSC output
PAL output
720H x 480V
720H x 576V
Imaging area
Optical format
Frame rate
Total array size: 3.584mm x 2.688mm
¼-inch
50/60 fields/sec
Sensor scan mode
Color filter array
Shutter type
Progressive scan
RGB standard Bayer
Electronic rolling shutter (ERS)
Automatic Functions Exposure, white balance, black level
offset correction, flicker detection and
avoidance, color saturation control, on-
the-fly defect correction, aperture
correction
• Auto black level calibration
• 10-bit, on-chip analog-to-digital converter (ADC)
• Internal master clock generated by on-chip phase-
locked loop (PLL)
• Two-wire serial programming interface
• Interface to low-cost EEPROM and Flash through SPI
bus
Programmable
Controls
Exposure, white balance, horizontal and
vertical blanking, color, sharpness,
gamma correction, lens shading
correction, horizontal and vertical image
flip, zoom, windowing, sampling rates,
GPIO control
• High-level host command interface
• Stand-alone operation support
• Comprehensive tool support for overlay generation
and lens correction setup
• Development system with DevWare
Key parameters are continued on next page.
Applications
• Analog surveillance CCTV
• Surveillance network IP camera
See “Ordering Information” on page 3.
See details of new features on page 3.
PDF: 171981479/Source: 8304342517Source:8304342517
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
Aptina reserves the right to change products or specifications without notice.
© 2010 Aptina Imaging Corporation All rights reserved.
1
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Aptina without
notice. Products are only warranted by Aptina to meet Aptina’s production data sheet specifications.
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Applications
Table 2:
Key Parameters (continued)
Parameter
Typical Value
Overlay Support
Utilizes SPI interface to load overlay data from external flash/EEPROM memory with the
following features:
•Available in Analog output and BT656 Digital output
•Overlay Size 360 x 480 pixel rendered into 720 x 480 (NTSC) or 720 x 576 (PAL)
•Up to four (4) overlays may be blended simultaneously
•Selectable readout: Rotating order user selected
•Dynamic scenes by loading pre-rendered frames from external memory
•Palette of 32 colors out of 64,000
•8 colors per bitmap
•Blend factor dynamically programmable for smooth transitions
•Fast Update rate of up to 30 fps
•Every bitmap object has independent x/y position
•Statistic Engine to calibrate optical alignment
•Number Generator
Windowing
Programmable to any size
Analog gain range
ADC
0.5–80x
10-bit, on-chip
Output interface
Output data formats1
Analog composite video out, single-ended or differential; 8-, 10-bit parallel digital output
Digital: Raw Bayer 8-,10-bit, CCIR656, 565RGB, 555RGB, 444RGB
Parallel: 27 MB/s
NTSC: 60 fields/sec
PAL: 50 fields/sec
Data rate
Control interface
Two-wire I/F for register interface plus high-level command exchange. SPI port to interface
to external memory to load overlay data, register settings, or firmware extensions.
Input clock for PLL
27 MHz
SPI Clock Frequencies
1.6875 – 18 MHz, programmable
Analog: 2.8V 5%
Supply voltage
Core: 1.8V 5%
IO: 2.8V 5%
Power
consumption
Analog output only
Digital output only
Full resolution at 60 fps: 236 mW
Full resolution at 60 fps: 234 mW
Package
63-cBGA, 7 mm x 7 mm 0.65mm pin pitch
63- CSP, 6.198 x 6.178 mm, 0.65mm pin pitch
Ambient temperature
Operating: -30°C to 70°C
Storage: –50°C to +150°C
Dark Current
< 200e/s at 60°C with a gain of 1
Fixed pattern Column
< 2%
noise
Row
< 2%
Responsivity
16.5 V/lux-s at 550nm
46 dB
Signal to noise ratio (S/N)
Pixel dynamic range
74.8 dB
PDF: 171981479/Source: 8304342517
Aptina reserves the right to change products or specifications without notice.
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
2
© 2010 Aptina Imaging Corporation All rights reserved.
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Ordering Information
Ordering Information
Table 3:
Available Part Numbers
Part Number Description
ASX340CS2C00SPEA0-E
ASX340CS2C00SPEA0
ASX340CS2C00SPEAH-E
ASX340CS2C00SPEAD-E
MT9V139I83STC ES
63-ball cBGA, AS/ES
63-ball cBGA, MP
63-ball cBGA, Headboard
63-ball cBGA, Demo
CSP ES part number
Demo kit
MT9V139I83STCD ES
MT9V139I83STCH ES
Head Board
New Features
•
•
•
•
•
•
Automatic 50hz/60hz flicker detection
2x upscaling zoom and pan/tilt control
Independent control of colorburst parameters in the NTSC/PAL encoder
Horizontal field of view adjustment between 700 and 720 pixels on the analog output
Option to use single 2.8V power supply with off-chip bypass transistor
SPI EEPROM support for lower cost system design.
PDF: 171981479/Source: 8304342517
Aptina reserves the right to change products or specifications without notice.
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
3
© 2010 Aptina Imaging Corporation All rights reserved.
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Table of Contents
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Internal Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Crystal Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Pin Descriptions and Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
SOC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Detailed Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Sensor Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Sensor Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Image Flow Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
NTSC/PAL Test Pattern Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CCIR-656 Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Black Level Subtraction and Digital Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Positional Gain Adjustments (PGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
The Correction Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Color Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Color Correction and Aperture Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RGB to YUV Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Color Kill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
YUV Color Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
YUV-to-RGB/YUV Conversion and Output Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Output Format and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
YUV/RGB Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Uncompressed 10-Bit Bypass Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Readout Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Zoom Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
FOV Stretch Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Usage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Multicamera Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
External Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Supported SPI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Supported SPI Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Host Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Host Command Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Command Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Issue the SYSMGR_SET_STATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Summary of Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Slave Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
PDF: 171981479/Source: 8304342517
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
Aptina reserves the right to change products or specifications without notice.
© 2010 Aptina Imaging Corporation All rights reserved.
4
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Table of Contents
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Slave Address/Data Direction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Message Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Typical Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Single READ from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Sequential READ, Start from Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Single Write to Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Overlay Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Serial Memory Partition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
External Memory Speed Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Overlay Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Overlay Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Character Generator Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Full Character Set for Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Composite Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Single-Ended and Differential Composite Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Parallel Output (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Reset and Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Floating Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Output Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Power Consumption, Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
NTSC Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Two-Wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
PDF: 171981479/Source: 8304342517
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
Aptina reserves the right to change products or specifications without notice.
© 2010 Aptina Imaging Corporation All rights reserved.
5
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Using a Crystal Instead of an External Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Image Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Pixel Color Pattern Detail (top right corner). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Color Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Gamma Correction Curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Auto-Config Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Flash Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Usage Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Host Mode with Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Host Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Multicamera System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
External Signal Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Power-Up Sequence – Configuration Options Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Interface Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Single Read from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Overlay Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Memory Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Overlay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Internal Block Diagram Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Example of Character Descriptor 0 Stored in ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Full Character Set for Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Single-Ended Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Differential Connection—Grounded Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems . . . . . . . . . . . . . . . . . . . .52
Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .53
Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .54
Primary Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Typical I/O Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
NTSC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Slew Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
FRAME_SYNC to FRAME_VALID/LINE_VALID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Reset to SPI Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Reset to Serial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Reset to AE/AWB Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SPI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Equivalent Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
V Pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
63-Ball cBGA Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 9:
Figure 10:
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Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
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Figure 25:
Figure 26:
Figure 27:
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Figure 32:
Figure 33:
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Figure 52:
Figure 53:
Figure 54:
Figure 55:
Figure 56:
PDF: 171981479/Source: 8304342517
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
Aptina reserves the right to change products or specifications without notice.
© 2010 Aptina Imaging Corporation All rights reserved.
6
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Figures
Figure 57:
63-Ball CSP Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PDF: 171981479/Source: 8304342517
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
Aptina reserves the right to change products or specifications without notice.
© 2010 Aptina Imaging Corporation All rights reserved.
7
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Parameters (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Reset/Default State of Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
EIA Color Bars (NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
EBU Color Bars (PAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
YCbCr Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
RGB Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2-Byte Bayer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
SPI Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
SPI Commands Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
GPIO Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
System Manager Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Overlay Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
GPIO Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Flash Manager Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Sequencer Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Patch Loader Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Miscellaneous Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Calibration Stats Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Two-Wire Interface ID Address Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Transfer Time Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Character Generator Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Field, Vertical Blanking, EAV, and SAV States 525/60 Video System . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System . . . . . . . . . . . . . . . . . . . . . . . . .54
Output Data Ordering in DOUT RGB Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Output Data Ordering in Sensor Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Parallel Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Slew Rate for PIXCLK and DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
RESET_BAR Delay Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SPI Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Video DAC Electrical Characteristics–Single-Ended Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Video DAC Electrical Characteristics–Differential Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Digital I/O Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Power Consumption – Condition 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Power Consumption – Condition 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
NTSC Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Equivalent Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
V Pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Table 25:
Table 26:
Table 27:
Table 28:
Table 29:
Table 30:
Table 31:
Table 32:
Table 33:
Table 34:
Table 35:
Table 36:
Table 37:
Table 38:
Table 39:
Table 40:
Table 41:
Table 42:
Table 43:
Table 44:
Table 45:
Table 46:
Table 47:
Table 48:
Table 49:
Table 50:
Table 51:
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8
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
General Description
General Description
The Aptina® ASX340/MT9V139 is a VGA-format, single-chip active-pixel digital image
sensor for surveillance applications. It captures high-quality color images at VGA resolu-
tion and outputs NTSC or PAL interlaced composite video.
The VGA image sensor features Aptina’s breakthrough low-noise imaging technology
that achieves superior image quality (based on signal-to-noise ratio and low-light sensi-
tivity) while maintaining the inherent size, cost, low power, and integration advantages
of Aptina's advanced active pixel process technology.
The ASX340/MT9V139 is a complete camera-on-a-chip. It incorporates sophisticated
camera functions on-chip and is programmable through a simple two-wire serial inter-
face or by an attached SPI EEPROM or Flash memory that contains setup information
that may be loaded automatically at startup.
The ASX340/MT9V139 performs sophisticated processing functions including color
recovery, color correction, sharpening, programmable gamma correction, auto black
reference clamping, auto exposure, 50Hz/60Hz flicker detection and avoidance, lens
shading correction, auto white balance (AWB), and on-the-fly defect identification and
correction.
The ASX340/MT9V139 outputs interlaced-scan images at 60 or 50 Fields per Second,
supporting both NTSC and PAL video formats. The image data can be output on one or
two output ports:
•
•
Composite analog video (single-ended and differential output support)
Parallel 8-, 10-bit digital
Architecture
Internal Block Diagram
Figure 1:
Internal Block Diagram
SPI
2. 8V
1 .8 V
Two-Wire I/F
2
4
Camera Control
SPI & 2W I/F
Interface
AWB
AE
640 x 480 Active Array
Image Flow Processor
Overlay
Graphics
Generation
8
10
Color & Gamma Correction
Color Space Conversion
Edge Enhancement
¼” VGA ROI
BT -656
@ 60 frames per sec.
NTSC /
PAL
VideoEncoder
DAC
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Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Architecture
System Block Diagram
The system block diagram will depend on the application. The system block diagram in
Figure 2 shows all components; optional peripheral components are highlighted. The
optional microcontroller controls the ASX340/MT9V139 sensor using the two-wire serial
bus. Optional components will vary by application. For further details, see the ASX340/
MT9V139 Register and Variable Reference.
Figure 2:
System Block Diagram
27 MHz
EXTCLK
XTAL
RESET_BAR
FRAME _SYNC
Serial Data
EEPROM/Flash
1KB - 16MB
System Bus
SPI
μC
2WIRE I/F
DAC_REF
LP Filter
Composite
Video
PAL /NTSC
DAC _POS
DAC _NEG
4.7kΩ
75Ω
V
DD_DAC (2.8V)
DD_PLL (2.8.V)
DD_IO (2.8V)
V
V
2.8V
.
Optional
V
AA _PIX (2.8V)
V
AA (2.8V)
V
DD (1.8V)
V
REG_BASE
]
D
OUT
[7:0
CCIR 656/
GPO
D
OUT_
LSB0, 1
PIXCLK
FRAME_VALID
LINE_VALID
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Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Architecture
Crystal Usage
As an alternative to using an external oscillator, a fundamental 27 MHz crystal may be
connected between EXTCLK and XTAL. Two small loading capacitors of 10–22 pF of NPO
dielectric should be added as shown in Figure 3.
Aptina does not recommend using the crystal option for applications above 85°C. A
crystal oscillator with temperature compensation is recommended.
Figure 3:
Using a Crystal Instead of an External Oscillator
Sensor
18pF -NPO
EXTCLK
XTAL
27.000 MHz
18pF -NPO
Note:
Value of load cap is Xtal dependent. Xtal with small load cap is recommended.
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11
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Pin Descriptions and Assignments
Table 4:
Pin Descriptions
Pin Name
Pin Number
Type
Description
Clock and Reset
A2
EXTCLK
Input
Master input clock (27MHz): This can either be a square-wave generated from an
oscillator (in which case the XTAL input must be left unconnected) or connected
directly to a crystal.
B1
D2
XTAL
Output
Input
If EXTCLK is connected to one pin of a crystal, this signal is connected to the other pin;
otherwise this signal must be left unconnected.
RESET_BAR
Asynchronous active-low reset: When asserted, the device will return all interfaces to
their reset state. When released, the device will initiate the boot sequence. This signal
has an internal pull-up resistor.
E1
FRAME_SYNC
Input
This input can be used to set the output timing of the ASX340/MT9V139 to a fixed
point in the frame.
The input buffer associated with this input is permanently enabled. This signal must
be connected to GND if not used.
Register Interface
F1
F2
E2
SCLK
SDATA
SADDR
Input
Input/Output
Input
These two signals implement serial communications protocol for access to the internal
registers and variables.
This signal controls the device ID that will respond to serial communication
commands.
Two-wire serial interface device ID selection:
0: 0x90
1: 0xBA
SPI Interface
D4
SPI_SCLK
Output
Clock output for interfacing to an external SPI memory such as Flash/EEPROM. Tristate
when RESET_BAR is asserted.
E4
H3
H2
SPI_SDI
SPI_SDO
SPI_CS_N
Input
Output
Output
Data in from SPI device. This signal has an internal pull-up resistor.
Data out to SPI device. Tristate when RESET_BAR is asserted.
Chip selects to SPI device. Tristate when RESET_BAR is asserted.
(Parallel) Pixel Data Output
F7
G7
E6
FRAME_VALID
LINE_VALID
PIXCLK
Input/Output Pixel data from the ASX340/MT9V139 can be routed out on this interface and
processed externally.
Input/Output
Output
To save power, these signals are driven to a constant logic level unless the parallel pixel
data output or alternate (GPIO) function is enabled for these pins. For more
information see Table 16 on page 33.
F8, D6, D7,
C6, C7, B6,
B7, A6
DOUT[7:0]
Output
This interface is disabled by default.
The slew rate of these outputs is programmable.
These signals can also be used as general purpose input/outputs.
B3
C2
DOUT_LSB1
DOUT_LSB0
Input/Output When the sensor core is running in bypass mode, it will generate 10 bits of output data
per pixel. These two pins make the two LSB of pixel data available externally. Leave
DOUT_LSB1 unconnected if not used. To save power, these signals are driven to a
constant logic level unless the sensor core is running in bypass mode or the alternate
function is enabled for these pins. For more information see Table 16,
Input/Output
“GPIO Bit Descriptions,” on page 38. The slew rate of these outputs is programmable.
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Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Table 4:
Pin Descriptions (continued)
Pin Number
Pin Name
Type
Description
Composite Video Output
F5
DAC_POS
Output
Positive video DAC output in differential mode.
Video DAC output in single-ended mode. This interface is enabled by default using
NTSC/PAL signalling. For applications where composite video output is not required,
the video DAC can be placed in a power-down state under software control.
G5
A4
DAC_NEG
DAC_REF
Output
Output
Negative video DAC output in differential mode.
External reference resistor for the video DAC.
Manufacturing Test Interface
D3
G2
F3
TDI
TDO
Input
Output
Input
Input
Input
Input
Input
JTAG Test pin (Reserved for Test Mode)
JTAG Test pin (Reserved for Test Mode)
JTAG Test pin (Reserved for Test Mode)
JTAG Test pin (Reserved for Test Mode)
Connect to GND.
TMS
C3
C4
G6
F6
TCK
TRST_N
ATEST1
ATEST2
Analog test input. Connect to GND in normal operation.
Analog test input. Connect to GND in normal operation.
GPIO
C1
A3
GPIO12
GPIO13
Input/Output Dedicated general-purpose input/output pin.
Input/Output Dedicated general-purpose input/output pin.
Power
G4
VREG_BASE
VDD
Supply
Supply
Voltage regulator control. Leave floating if not used.
A5, A7, D8,
E7, G1, G3
Supply for VDD core: 1.8V nominal. Can be connected to the output of the transistor of
the off-chip bypass transistor or a external 1.8V power supply.
B2, B8, C8,
E3, E8, G8,
H8
VDD_IO
Supply
Supply for digital IOs: 2.8V nominal.
H5
A8
VDD_DAC
VDD_PLL
VAA
Supply
Supply
Supply
Supply
Supply for video DAC: 2.8V nominal.
Supply for PLL: 2.8V nominal.
B4, H6
H7
Analog power: 2.8V nominal.
VAA_PIX
Reserved
DGND
Analog pixel array power: 2.8V nominal. Must be at same voltage potential as VAA.
H4
B5, C5, D1,
D5, H1
Supply
Supply
Digital ground.
Analog ground.
E5, F4
AGND
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Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Pin Assignments
Pin 1 is not populated with a ball. That allows the device to be identified by an additional
marking.
Table 5:
Pin Assignments
1
2
3
4
5
6
7
8
A
B
C
D
EXTCLK
VDD_IO
DOUT_LSB0
RESET_BAR
SADDR
GPIO13
DOUT_LSB1
TCK
DAC_REF
VAA
VDD
DOUT0
DOUT2
DOUT4
DOUT6
PIXCLK
VDD
VDD_PLL
VDD_IO
VDD_IO
VDD
XTAL
GPIO12
GND
GND
GND
GND
AGND
DOUT1
DOUT3
DOUT5
VDD
TRST_N
SPI_SCLK
SPI_SDI
AGND
TDI
E
F
FRAME_SYNC
SCLK
VDD_IO
TMS
VDD_IO
DOUT7
VDD_IO
VDD_IO
SDATA
DAC_POS
DAC_NEG
VDD_DAC
ATEST2
ATEST1
VAA
FRAME_VALID
LINE_VALID
VAA_PIX
G
H
VDD
TDO
VDD
VREG_BASE
Reserved
GND
SPI_CS_N
SPI_SDO
Table 6:
Reset/Default State of Interfaces
Reset State
Name
Default State
Notes
EXTCLK
XTAL
Clock running or stopped
Clock running
N/A
Input
Input
Input
N/A
Asserted
N/A
RESET_BAR
SCLK
De-asserted
N/A
Input. Must always be driven to a valid logic
level.
SDATA
SADDR
High impedance
N/A
High impedance
N/A
Input/Output. A valid logic level should be
established by pull-up resistor.
Input. Must always be driven to a valid logic
level. Must be permanently tied to VDD_IO or
GND.
SPI_SCLK
SPI_SDI
High impedance.
Internal pull-up enabled.
High impedance
Driven, logic 0
Internal pull-up enabled
Driven, logic 0
Output. Output enable is R0x0032[13].
Input. Internal pull-up is permanently enabled.
Output enable is R0x0032[13].
SPI_SDO
SPI_CS_N
FRAME_VALID
LINE_VALID
High impedance
Driven, logic 1
Output enable is R0x0032[13].
High impedance
High impedance
Input/Output. This interface disabled by default.
Input buffers (used for GPIO function) powered
down by default, so these pins can be left
unconnected (floating). After reset, these pins
are powered up, sampled, then powered down
again as part of the auto-configuration
mechanism. See Note 2.
PIXCLK
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
High impedance
Driven, logic 0
Output. This interface disabled by default.
See Note 1.
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14
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Table 6:
Name
Reset/Default State of Interfaces (continued)
Reset State
Default State
Notes
DOUT_LSB1
DOUT_LSB0
High impedance
High impedance
High impedance
HIgh impedance
Input/Output. This interface disabled by default.
Input buffers (used for GPIO function) powered
down by default, so these pins can be left
unconnected (floating). After reset, these pins
are powered-up, sampled, then powered down
again as part of the auto-configuration
mechanism.
DAC_POS
DAC_NEG
DAC_REF
TDI
High impedance
Driven
Output. Interface disabled by hardware reset
and enabled by default when the device starts
streaming.
Internal pull-up enabled
High impedance
Internal pull-up enabled
High impedance
Input. Internal pull-up means that this pin can
be left unconnected (floating).
TDO
TMS
Output. Driven only during appropriate parts of
the JTAG shifter sequence.
Internal pull-up enabled
Internal pull-up enabled
N/A
Internal pull-up enabled
Internal pull-up enabled
N/A
Input. Internal pull-up means that this pin can
be left unconnected (floating).
TCK
Input. Internal pull-up means that this pin can
be left unconnected (floating).
TRST_N
Input. Must always be driven to a valid logic
level. Must be driven to GND for normal
operation.
FRAME_SYNC
GPIO12
N/A
N/A
Input. Must always be driven to a valid logic
level. Must be driven to GND for normal
operation.
High impedance
High impedance
Input/Output. This interface disabled by default.
Input buffers (used for GPIO function) powered
down by default, so these pins can be left
unconnected (floating). After reset, these pins
are powered-up, sampled, then powered down
again as part of the auto-configuration
mechanism.
GPIO13
High impedance
High impedance
Input/Output. This interface disabled by default.
Input buffers (used for GPIO function) powered
down by default, so these pins can be left
unconnected (floating). After reset, these pins
are powered-up, sampled, then powered down
again as part of the auto-configuration
mechanism.
ATEST1
ATEST2
N/A
N/A
N/A
N/A
Must be driven to GND for normal operation.
Must be driven to GND for normal operation.
Notes: 1. The reason for defining the default state as logic 0 rather than high impedance is this: when wired in a
system (for example, on our demo boards), these outputs will be connected, and the inputs to which
they are connected will want to see a valid logic level. No current drain should result from driving these
to a valid logic level (unless there is a pull-up at the system level).
2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore, they
can be left floating but they will not drive a valid logic level to an attached device.
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© 2010 Aptina Imaging Corporation All rights reserved.
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
SOC Description
SOC Description
Detailed Architecture Overview
Sensor Core
The sensor consists of a pixel array, an analog readout chain, a 10-bit ADC with programmable
gain and black offset, and timing and control as illustrated in Figure 4.
Figure 4:
Sensor Core Block Diagram
Control Register
Communication
Bus
Active Pixel
to IFP
Sensor (APS)
Array
Timing and Control
Clock
Sync
Signals
10-Bit Data
to IFP
Analog Processing
ADC
Pixel Array Structure
The sensor core pixel array is configured as 792 columns by 560 rows, as shown in
Figure 5.
Figure 5:
Pixel Array Description
(64, 0)
(104, 36)
lens alignment rows
demosaic rows
Pixel logical address = (0, 0)
Active pixel array
640 x 480
Pixel logical address = (791, 559)
demosaic rows
lens alignment rows
(751, 523)
(not to scale)
Black rows used internally for automatic black level adjustment are not addressed by
default, but can be read out in raw output mode via a register setting.
There are 792 columns by 560 rows of optically-active pixels that include a pixel
boundary around the VGA (640 x 480) image to avoid boundary effects during color
interpolation and correction.
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Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
SOC Description
Figure 6 illustrates the process of capturing the image. The original scene is flipped and
mirrored by the sensor optics. Sensor readout starts at the lower right corner. The image
is presented in true orientation by the output display.
Figure 6:
Image Capture Example
SCENE
(Front view)
OPTICS
IMAGE SENSOR
(Rear view)
IMAGE CAPTURE
Row by Row
Start Rasterization
Start Readout
IMAGE RENDERING
DISPLAY
(Front view)
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Sensor Pixel Array
The active pixel array is 640 x 480 pixels. In addition, there are 72 rows and 80 columns
for lens alignment and 8 rows and 8 columns for demosaic.
Figure 7:
Pixel Color Pattern Detail (top right corner)
Column Readout Direction
.
.
Black Pixels
First Lens Alignment
.
Pixel
(64, 0)
G
B
G
B
G
B
R
G
R
G
B
G
B
G
B
R
G
R
G
B
G
B
G
B
R
G
R
G
B
G
B
G
B
Row
Readout
Direction
...
G
R
G
R
G
R
G
G
G
Output Data Format
The sensor core image data are read out in progressive scan order. Valid image data are
surrounded by horizontal and vertical blanking, shown in Figure 8.
For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size
is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of
the image field.
For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical
size is 288 pixels per field.
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Figure 8:
Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n
P2,0 P2,1 P2,2.....................................P2,n-1 P2,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Horizontal
Blanking
Valid Image Odd Field
Pm-2,0 Pm-2,1.....................................Pm-2,n-1 Pm-2,n 00 00 00 .................. 00 00 00
Pm,0 Pm,1.....................................Pm,n-1 Pm,n
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Vertical/Horizontal
Blanking
Vertical Even Blanking
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n
P3,0 P3,1 P3,2.....................................P3,n-1 P3,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Horizontal
Blanking
Valid Image Even Field
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00
Pm+1,0 Pm+1,1..................................Pm+1,n-1 Pm+1,n 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Vertical/Horizontal
Blanking
Vertical Odd Blanking
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
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Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Image Flow Processor
Image and color processing in the ASX340/MT9V139 are implemented as an image flow
processor (IFP) coded in hardware logic. During normal operation, the embedded
microcontroller will automatically adjust the operation parameters. The IFP is broken
down into different sections, as outlined in Figure 9.
Figure 9:
Color Pipeline
RAW 10
Pixel Array
ADC
Raw Data
IFP
Test Pattern
Generator
MUX
Black
Level
Digital Gain Control
Lens Shading
Subtraction
Correction
Defect Correction,
Noise Reduction,
Color Interpolation
Statistics
Engine
8-bit
RGB
RGB to YUV
10/12-Bit
RGB
8-bit
YUV
Color Correction
Color Kill
Aperture
Correction
Output
Gamma
Correction
Formatting
YUV to RGB
(12-to-8 Lookup)
Overlay Control
Output
Interface
Parallel Output Mux
Analog Output Mux
Parallel
Output
NTSC/PAL
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Test Patterns
During normal operation of the ASX340/MT9V139, a stream of raw image data from the
sensor core is continuously fed into the color pipeline. For test purposes, this stream can
be replaced with a fixed image generated by a special test module in the pipeline. The
module provides a selection of test patterns sufficient for basic testing of the pipeline.
NTSC/PAL Test Pattern Generation
There is a built-in standard EIA (NTSC) and EBU (PAL) color bars to support hue and
color saturation characterization. Each pattern consists of seven color bars (white,
yellow, cyan, green, magenta, red, and blue). The Y, Cb and Cr values for each bar are
detailed in Tables 7 and 8.
Figure 10:
Color Bars
Table 7:
EIA Color Bars (NTSC)
Nominal Range White
Yellow
Cyan
Green
Magenta
Red
Blue
Y
16 to 235
16 to 240
16 to 240
180
128
128
162
44
131
156
44
112
72
84
65
35
Cb
Cr
184
198
100
212
212
114
142
58
Table 8:
EBU Color Bars (PAL)
Nominal Range
White
Yellow
Cyan
Green
Magenta
Red
Blue
Y
16 to 235
16 to 240
16 to 240
235
128
128
162
44
131
156
44
112
72
84
65
35
Cb
Cr
184
198
100
212
212
114
142
58
CCIR-656 Format
The color bar data is encoded in 656 data streams. The duration of the blanking and
active video periods of the generated 656 data are summarized in the following tables.
Table 9:
NTSC
Line Numbers
Field
Description
1-3
4-19
2
1
1
Blanking
Blanking
20-263
Active video
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Table 9:
NTSC
Line Numbers
Field
Description
264-265
266-282
283-525
1
2
2
Blanking
Blanking
Active Video
Table 10:
PAL
Line Numbers
Field
Description
1-22
1
1
1
2
2
2
Blanking
23-310
Active video
Blanking
311-312
313-335
336-623
624-625
Blanking
Active video
Blanking
Black Level Subtraction and Digital Gain
Image stream processing starts with black level subtraction and multiplication of all
pixel values by a programmable digital gain. Both operations can be independently set
to separate values for each color channel (R, Gr., Gb, B). Independent color channel
digital gain can be adjusted with registers. Independent color channel black level adjust-
ments can also be made. If the black level subtraction produces a negative result for a
particular pixel, the value of this pixel is set to 0.
Positional Gain Adjustments (PGA)
Lenses tend to produce images whose brightness is significantly attenuated near the
edges. There are also other factors causing fixed pattern signal gradients in images
captured by image sensors. The cumulative result of all these factors is known as image
shading. The ASX340/MT9V139 has an embedded shading correction module that can
be programmed to counter the shading effects on each individual R, Gb, Gr., and B color
signal.
The Correction Function
The correction functions can then be applied to each pixel value to equalize the
response across the image as follows:
P
(row,col)=P
(row,col)*f(row,col)
(EQ 1)
corrected
sensor
where P are the pixel values and f is the color dependent correction functions for each
color channel.
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Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Color Interpolation
In the raw data stream fed by the sensor core to the IFP, each pixel is represented by a
10-bit integer number, which can be considered proportional to the pixel's response to a
one-color light stimulus, red, green, or blue, depending on the pixel's position under the
color filter array. Initial data processing steps, up to and including the defect correction,
preserve the one-color-per-pixel nature of the data stream, but after the defect correc-
tion it must be converted to a three-colors-per-pixel stream appropriate for standard
color processing. The conversion is done by an edge-sensitive color interpolation
module. The module pads the incomplete color information available for each pixel
with information extracted from an appropriate set of neighboring pixels. The algorithm
used to select this set and extract the information seeks the best compromise between
preserving edges and filtering out high frequency noise in flat field areas. The edge
threshold can be set through register settings.
Color Correction and Aperture Correction
To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are
subjected to color correction. The IFP multiplies each vector of three pixel colors by a
3 x 3 color correction matrix. The three components of the resulting color vector are all
sums of three 10-bit numbers. Since such sums can have up to 12 significant bits, the bit
width of the image data stream is widened to 12 bits per color (36 bits per pixel). The
color correction matrix can be either programmed by the user or automatically selected
by the auto white balance (AWB) algorithm implemented in the IFP. Color correction
should ideally produce output colors that are corrected for the spectral sensitivity and
color crosstalk characteristics of the image sensor. The optimal values of the color
correction matrix elements depend on those sensor characteristics and on the spectrum
of light incident on the sensor. The color correction variables can be adjusted through
register settings.
To increase image sharpness, a programmable 2D aperture correction (sharpening filter)
is applied to color-corrected image data. The gain and threshold for 2D correction can
be defined through register settings.
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Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Gamma Correction
The ASX340/MT9V139 includes a block for gamma correction that can adjust its shape
based on brightness to enhance the performance under certain lighting conditions. Two
custom gamma correction tables may be uploaded corresponding to a brighter lighting
condition and a darker lighting condition. At power-up, the IFP loads the two tables with
default values. The final gamma correction table used depends on the brightness of the
scene and takes the form of an interpolated version of the two tables.
The gamma correction curve (as shown in Figure 11) is implemented as a piecewise
linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit
output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280,
1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit ordinates
are programmable through registers.
Figure 11:
Gamma Correction Curve
RGB to YUV Conversion
Color Kill
For further processing, the data is converted from RGB color space to YUV color space.
To remove high-or low-light color artifacts, a color kill circuit is included. It affects only
pixels whose luminance exceeds a certain preprogrammed threshold. The U and V
values of those pixels are attenuated proportionally to the difference between their lumi-
nance and the threshold.
YUV Color Filter
As an optional processing step, noise suppression by one-dimensional low-pass filtering
of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.
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Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
YUV-to-RGB/YUV Conversion and Output Formatting
The YUV data stream emerging from the colorpipe can either exit the color pipeline as-is
or be converted before exit to an alternative YUV or RGB data format.
Output Format and Timing
YUV/RGB Data Ordering
The ASX340/MT9V139 supports swapping YCbCr mode, as illustrated in Table 11.
Table 11:
YCbCr Output Data Ordering
Mode
Data Sequence
Default (no swap)
Swapped CbCr
Swapped YC
Cbi
Cri
Yi
Yi
Yi
Cri
Yi+1
Yi+1
Cri
Cbi
Yi+1
Yi+1
Cbi
Cri
Swapped CbCr, YC
Yi
Cbi
The RGB output data ordering in default mode is shown in Table 12. The odd and even
bytes are swapped when luma/chroma swap is enabled. R and B channels are bit-wise
swapped when chroma swap is enabled.
Table 12:
RGB Ordering in Default Mode
Mode (Swap Disabled)
Byte
D7D6D5D4D3D2D1D0
565RGB
555RGB
444xRGB
x444RGB
Odd
Even
Odd
Even
Odd
Even
Odd
Even
R7R6R5R4R3G7G6G5
G4G3G2B7B6B5B4B3
0 R7R6R5R4R3G7G6
G5G4G3B7B6B5B4B3
R7R6R5R4G7G6G5G4
B7B6B5B4 0 0 0 0
0 0 0 0 R7R6R5R4
G7G6G5G4B7B6B5B4
Uncompressed 10-Bit Bypass Output
Raw 10-bit Bayer data from the sensor core can be output in bypass mode in two ways:
•
Using 8 data output signals (DOUT[7:0]) and GPIO[1:0]. The GPIO signals are the least
significant 2 bits of data.
•
Using only 8 signals (DOUT[7:0]) and a special 8 + 2 data format, shown in Table 13.
Table 13:
2-Byte Bayer Format
Byte
Bits Used
Bit Sequence
Odd bytes
Even bytes
8 data bits
D9D8D7D6D5D4D3D2
0 0 0 0 0 0 D1D0
2 data bits + 6 unused bits
Readout Formats
Progressive format is used for raw Bayer output.
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Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Output Formats
ITU-R BT.656 and RGB Output
TheASX340/MT9V139 can output processed video as a standard ITU-R BT.656
(CCIR656) stream, an RGB stream, or as unprocessed Bayer data. The ITU-R BT.656
stream contains YCbCr 4:2:2 data with embedded synchronization codes. This output is
typically suitable for subsequent display by standard video equipment or JPEG/MPEG
compression.
Colorpipe data (pre-lens correction and overlay) can also be output in YCbCr 4:2:2 and a
variety of RGB formats in 640 by 480 progressive format in conjunction with
LINE_VALID and FRAME_VALID.
The ASX340/MT9V139 can be configured to output 16-bit RGB (565RGB), 15-bit RGB
(555RGB), and two types of 12-bit RGB (444RGB). Refer to Table 30 and Table 31 on
page 56 for details.
Bayer Output
Unprocessed Bayer data are generated when bypassing the IFP completely—that is, by
simply outputting the sensor Bayer stream as usual, using FRAME_VALID, LINE_VALID,
and PIXCLK to time the data. This mode is called sensor bypass mode.
Output Ports
Composite Video Output
The composite video output DAC is external-resistor-programmable and supports both
single-ended and differential output. The DAC is driven by the on-chip video encoder
output.
Parallel Output
Parallel output uses either 8-bit or 10-bit output. Eight-bit output is used for ITU-R
BT.656 and RGB output. Ten-bit output is used for raw Bayer output.
Zoom Support
The ASX340/MT9V139 supports zoom x1 and x2 modes, in interlaced and progressive
scan modes. The progressive support is limited to the VGA at either 60 fps or 50 fps.
In the zoom x2 modes, the sensor is configured for QVGA (320 x 240), and the zoom x2
window can be configured to pan around the VGA window.
FOV Stretch Support
The ASX340/MT9V139 supports the ability to control the active 'width' of the TV output
line, between 720 and 700 pixels. The hardware supports two margins, each a maximum
of 10 pixels width, and has to be an even number of pixels.
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Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Usage Modes
Usage Modes
How a camera based on the ASX340/MT9V139 will be configured depends on what
features are used. In the simplest case, an ASX340/MT9V139 operating in Auto-Config
Mode with no customized settings might be sufficient. Flash sizes vary depending on
the data for registers, firmware, and overlay data—somewhere between 1KB to 16MB.
The two-wire bus is adequate since only high-level commands are used to invoke over-
lays, load registers from memory, or set up lens correction parameters. Overlay data can
alternatively be issued by the external µC if the rate of refreshing data is deemed
adequate. If there are no commands in the EEPROM or Flash image the device can be in
auto configuration mode by which the sensor is set up according to the status of pins
FRAME_VALID, LINE_VALID, DOUT_LSB1, and DOUT_LSB0.
In the simplest case no EEPROM or Flash memory or µC is required, as shown in
Figure 12. This is truly a single chip operation.
Figure 12:
Auto-Config Mode
ASX340/MT9V139
Auto-Config Mode
Analog Out
Digital Out
The ASX340/MT9V139 can be configured by a serial EEPROM or Flash through the SPI
Interface.
Figure 13:
Flash Mode
Serial
EEPROM/Flash
ASX340/MT9V139
SPI
Functions such as overlay or 2x zoom can also be assigned to general purpose inputs.
That capability can be employed on all configurations with external EEPROM or Flash
memory by mapping overlay images to an input. Alternatively, the µC may poll these
inputs to create an action such as a new overlay as shown in Figure 14.
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Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Usage Modes
Figure 14:
Usage Mode 3
Serial
EEPROM/Flash
ASX340/MT9V139
SPI
GPI[7:0]
External device
In some applications, button or user interface keypad can trigger overlay images being
called by the μC as shown in Figure 15.
Figure 15:
Host Mode with Flash
Serial
EEPROM/Flash
ASX340/MT9V139
SPI
8/16bit μC
Button or
user interface
keypad
two-wire
Overlay information may also be passed by the µC without a need for an EEPROM or
Flash memory. However, because the data transfer rate is limited over the two-wire serial
bus, the update rate may be slower. However, if overlay images are preloaded into the
four on-chip buffers, they may be turned on and off or move location at the frame rate as
shown in Figure 16.
Figure 16:
Host Mode
8/16bit μC
ASX340/MT9V139
Button or
user interface
keypad
two-wire
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Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Multicamera Support
Multicamera Support
Two or more ASX340/MT9V139 sensors may be synchronized to a frame by asserting the
FRAME_SYNC signal. At that point, the sensor and video encoder will reset without
affecting any register settings. The ASX340/MT9V139 may be triggered to be synchro-
nized with another ASX340/MT9V139 or an external event.
Figure 17:
Multicamera System Block Diagram
Decoder/DSP
Dual Camera
ASX340/
MT9V139
CVBS
CVBS
Camera 1
Camera 2
OSC
F_SYNC
ASX340/
MT9V139
F_SYNC
1
System Bus
μC
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
External Signal Processing
An external signal processor can take data from ITU656 or raw Bayer output format and
post-process or compress the data in various formats.
Figure 18:
External Signal Processing Block Diagram
27 MHz
Serial
EXTCLK
SPI
EEPROM/Flash
1KB to 16MB
VIDEO_P
VIDEO_N
CVBS
PAL/NTSC
Signal processor
DOUT [7:0]
PIXCLK
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Device Configuration
After power is applied and the device is out of reset by de-asserting the RESET_BAR pin,
it will enter a boot sequence to configure its operating mode. There are essentially three
configuration modes: Flash/EEPROM Config, Auto Config, and Host Config. Figure 19:
“Power-Up Sequence – Configuration Options Flow Chart,” on page 32 contains more
details on the configuration options.
The SOC firmware supports a System Configuration phase at start-up. This consists of
five modes of execution:
1. Flash Detection
2. Flash-Config
3. Auto-Config
4. Host-Config
5. Change-Config (commences streaming - completes the System Configuration mode).
The System Configuration phase is entered immediately after the firmware initializes
following SOC power-up or reset. By default, the firmware first enters the Flash Detec-
tion mode
The Flash Detection mode attempts to detect the presence of an SPI Flash or EEPROM
device:
•
If no device is detected, the firmware then samples the SPI_SDI pin state to determine
the next mode:
– If SPI_SDI == 0 then it enters the Host-Config mode.
– If SPI_SDI == 1 then it enters the Auto-Config mode.
•
If a device is detected, the firmware switches to the Flash-Config mode.
In the Flash-Config phase, the firmware interrogates the device to determine if it
contains valid configuration records:
•
•
If no records are detected, then the firmware enters the Auto-Config mode.
If records are detected, the firmware processes them. By default, when all Flash
records are processed the firmware switches to the Host-Config mode. However, the
records encoded into the Flash can optionally be used to instruct the firmware to
proceed to one of the other mode (auto-config/change-config).
The Auto-Config mode uses the FRAME_VALID, LINE_VALUE, DOUT_LSB0 and
DOUT_LSB1 pins to configure the operation of the device, such as video format and
pedestal (see Table 16, “GPIO Bit Descriptions,” on page 33). After Auto-Config
completes the firmware switches to the Change-Config mode.
In the Host-Config mode, the firmware performs no configuration, and remains idle
waiting for configuration and commands from the host. The System Configuration
phase is effectively complete and the SOC will take no actions until the host issues
commands.
In the Change-Config mode, the firmware performs a 'Change-Config' operation. This
applies the current configuration settings to the SOC, and commences streaming. This
completes the System Configuration phase.
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Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Power Sequence
In power-up, the core voltage (1.8V) must trail the IO (2.8V) by a positive number. All
2.8V rails can be turned on at the same time or follow the power-up sequence in Figure
45: “Power Up Sequence,” on page 62.
In power down, the sequence is reversed. The core voltage (1.8V) must be turned off
before any 2.8V. Refer to Figure 46: “Power Down Sequence,” on page 63 for details.
Figure 19:
Power-Up Sequence – Configuration Options Flow Chart
Power Up/ RESET
EEPROM/Flash
Exists?
yes
no
EEPROM/Flash
Header?
no
yes
SPI _SDI = 0?
no
Parse
EEPROM/Flash
Content
(optional)
:
Auto-Config
Change-Config
Disable Auto-Config
(default)
Auto Configuration:
Auto-Config
_
FRAME VALID
Wait for Host
Command
LINE_VALID
DOUT_LSB 0
DOUT_LSB 1
Host Config
Wait for Host
Command
Change-Config
Change Config
Wait for Host
Command
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External Signal Processing
Supported SPI Devices
Table 14 lists supported EEPROM/Flash devices. Devices not compatible will require a
firmware patch. Contact Aptina for additional support.
Table 14:
Type
SPI Flash Devices
Speed
(MHz)
Temp Range
(°C)
Density
Manufacturer
Device
Standard
Supported
Flash
Flash
1 MB
8 MB
1MB
8KB
ST
Atmel
ST
M25P10-AVMB3
AT26DF081A
M95M01-R
50
70
5
–40 to +125
–20 to +85
–40 to +130
–40 to +125
Yes
Yes
Yes
Yes
JEDEC/Device ID
EEPROM
EEPROM
Microchip
25LC080
2
Supported SPI Commands
The SPI commands shown in Table 15 are supported by the ASX340/MT9V139.
SPI Commands Supported
Table 15:
Command
Value
Read Array
Block Erase
Chip Erase
Read Status
0x03
0xD8
0xC7
0x05
0x01
0x02
0x06
0x04
0x9F
0x0B
Write status
Byte Page Program
Write Enable
Write Disable
Read Manufacturer and Device ID
(Fast) Read Array
Table 16:
GPIO Bit Descriptions
GPIO[11] (DOUT_LSB1)
GPIO[10] (DOUT_LSB0)
GPIO[9] (FRAME_VALID) GPI[8] (LINE_VALID)
Low (“0”)
High (“1”)
Normal
NTSC
PAL
Normal
Horizontal mirror
No pedestal
Pedestal
Vertical Flip
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Host Command Interface
Aptina’s sensors and SOCs contain numerous registers that are accessed through a
two-wire interface with speeds up to 400 kHz.
The ASX340/MT9V139 in addition to writing or reading straight to/from registers or
firmware variables, has a mechanism to write higher level commands, the Host
Command Interface (HCI). Once a command has been written through the HCI, it will
be executed by on chip firmware and the results are reported back. In general, registers
shall not be accessed with the exception of registers that are marked for “User Access.”
EEPROM or Flash memory is also available to store commands for later execution.
Under DMA control, a command is written into the SOC and executed.
For a complete spec on host commands, refer to the ASX340/MT9V139 Host Command
Interface Specification.
Figure 20:
Interface Structure
14
bit
15
0
1
0
Host Command to FW
Response from FW
Addr 0x40
command register
door bell
bit
15
0
Addr 0xFC00
Parameter 0
cmd_handler_params_pool_0
cmd_handler_params_pool_1
cmd_handler_params_pool_2
Addr 0xFC02
Addr 0xFC04
Addr 0xFC06
Addr 0xFC08
Addr 0xFC0A
Addr 0xFC0C
cmd_handler_params_pool_3
cmd_handler_params_pool_4
cmd_handler_params_pool_5
cmd_handler_params_pool_6
cmd_handler_params_pool_7
Addr 0xFC0E
Parameter 7
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External Signal Processing
Host Command Process Flow
Issue
Command
Wait for a
response?
No
Host could insert an
optional delay here
Yes
Read Command
register
Host could insert an
optional delay here
Read Command
register
No
No
Doorbell
bit clear ?
Doorbell bit
clear?
Yes
At this point
Command Register
Yes
contains response code
Command has
parameters
?
Command
has response
parameters ?
No
Yes
Write parameters
Yes
No
to
Parameter Pool
Read response
parameters from
Parameter Pool
Write command
to
Command register
Done
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External Signal Processing
Command Flow
The host issues a command by writing (through a two-wire interface bus) to the
command register. All commands are encoded with bit 15 set, which automatically
generates the host command (doorbell) interrupt to the microprocessor.
Assuming initial conditions, the host first writes the command parameters (if any) to the
parameters pool (in the command handler's logical page), then writes the command to
command register. The SOC firmware interrupt handler then signals the Command
Handler task to process the command.
If the host wishes to determine the outcome of the command, it must poll the command
register waiting for the doorbell bit to be cleared. This indicates that the firmware
completed processing the command. When the doorbell bit is cleared, the contents of
the command register indicate the command's result status. If the command generated
response parameters, the host can now retrieve these from the parameters pool.
Note:
The host must not write to the parameters pool, nor issue another command, until
the previous command completes. This is true even if the host does not care about the
result of the previous command. Therefore, the host must always poll the command
register to determine the state of the doorbell bit, and ensure the bit is cleared before
issuing a command.
For a complete command list and further information consult the Host Command Inter-
face Specification.
An example of how (using DevWare) a command may be initiated in the form of a
“Preset” follows.
Issue the SYSMGR_SET_STATE Command
All DevWare presets supplied by Aptina poll and test the doorbell bit after issuing the
command. Therefore there is no need to check if the doorbell bit is clear before issuing
the next command.
# Set the desired next state in the parameters
pool(SYS_STATE_ENTER_CONFIG_CHANGE)
REG= 0xFC00, 0x2800 // CMD_HANDLER_PARAMS_POOL_0
# Issue the HC_SYSMGR_SET_STATE command
REG= 0x0040, 0x8100 // COMMAND_REGISTER
# Wait for the FW to complete the command (clear the Doorbell bit)
POLL_FIELD= COMMAND_REGISTER, DOORBELL, !=0, DELAY=10, TIMEOUT=100
# Check the command was successful
ERROR_IF= COMMAND_REGISTER, HOST_COMMAND, !=0, "Set State command
failed",
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Summary of Host Commands
Table 17 on page 37 through Table 24 on page 39 show summaries of the host
commands. The commands are divided into the following sections:
•
•
•
•
•
•
•
•
System Manager
Overlay
GPIO
Flash Manager
Sequencer
Patch Loader
Miscellaneous
Calibration Stats
Following is a summary of the Host Interface commands. The description gives a quick
orientation. The “Type” column shows if it is an asynchronous or synchronous
command. For a complete list of all commands including parameters, consult the Host
Command Interface Specification document.
Table 17:
System Manager Commands
System Manager
Host Command
Value
Type
Description
Set State
Get State
0x8100
0x8101
Synchronous
Synchronous
Request the system enter a new state
Get the current state of the system
Table 18:
Overlay Host Commands
Overlay Host Command
Value
Type
Description
Enable Overlay
Get Overlay State
Set Calibration
Set Bitmap Property
Get Bitmap Property
Set String Property
Load Buffer
0x8200
0x8201
0x8202
0x8203
0x8204
0x8205
0x8206
0x8207
0x8208
0x8209
0x820A
0x820B
0x820C
0x820D
0x820E
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Enable or disable the overlay subsystem
Retrieve the state of the overlay subsystem
Set the calibration offset
Set a property of a bitmap
Get a property of a bitmap
Set a property of a character string
Load an overlay buffer with a bitmap (from Flash)
Retrieve status of an active load buffer operation
Write directly to an overlay buffer
Read directly from an overlay buffer
Enable or disable an overlay layer
Retrieve the status of an overlay layer
Set the character string
Load Status
Write Buffer
Read Buffer
Enable Layer
Get Layer Status
Set String
Get String
Get the current character string
Load String
Load a character string (from Flash)
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Table 19:
GPIO Host Commands
GPIO Host Command
Value
Type
Description
Set GPIO Property
Get GPIO Property
Set GPO State
0x8400
0x8401
0x8402
0x8403
0x8404
0x8405
Synchronous Set a property of one or more GPIO pins
Synchronous Retrieve a property of a GPIO pin
Synchronous Set the state of a GPO pin or pins
Get GPIO State
Synchronous Get the state of a GPI pin or pins
Set GPI Association
Get GPI Association
Synchronous Associate a GPI pin state with a Command Sequence stored in SPI Flash
Synchronous Retrieve an GPIO pin association
Table 20:
Flash Manager Host Commands
Flash Manager
Host Command
Value
Type
Description
Get Lock
0x8500
0x8501
0x8502
0x8503
0x8504
0x8505
0x8506
0x8507
0x8508
0x8509
0x850A
Asynchronous Request the Flash Manager access lock
Synchronous Retrieve the status of the access lock request
Synchronous Release the Flash Manager access lock
Synchronous Configure the Flash Manager and underlying SPI Flash subsystem
Asynchronous Read data from the SPI Flash
Lock Status
Release Lock
Config
Read
Write
Asynchronous Write data to the SPI Flash
Erase Block
Erase Device
Query Device
Status
Asynchronous Erase a block of data from the SPI Flash
Asynchronous Erase the SPI Flash device
Asynchronous Query device-specific information
Synchronous Obtain status of current asynchronous operation
Synchronous Configure the attached SPI NVM device
Config Device
Table 21:
Sequencer Host Commands
Value
Sequencer Host
Command
Type
Description
Refresh
0x8606
0x8607
Synchronous
Synchronous
Refresh the automatic image processing algorithm configuration
Retrieve the status of the last Refresh operation
Refresh Status
Table 22:
Patch Loader Host Commands
Patch Loader Host
Command
Value
Type
Asynchronous
Description
Load Patch
Status
0x8700
0x8701
0x8702
0x8706
Load a patch from SPI Flash and automatically apply
Get status of an active Load Patch or Apply Patch request
Apply a patch (already located in Patch RAM)
Reserve RAM to contain a patch
Synchronous
Asynchronous
Synchronous
Apply Patch
Reserve RAM
Table 23:
Miscellaneous Host Commands
Miscellaneous Host Command
Value
Type
Synchronous
Synchronous
Synchronous
Description
Invoke Command Seq
Config Command Seq Processor
Wait For Event
0x8900
0x8901
0x8902
Invoke a sequence of commands stored in NVM
Configures the Command Sequencer processor
Wait for a system event to be signalled
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External Signal Processing
Table 24:
Calibration Stats Host Commands
Calibration Stats Host
Command
Value
Type
Asynchronous
Synchronous
Description
Control
Read
0x8B00
0x8B01
Start statistics gathering
Read the results back
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Slave Two-Wire Serial Interface
The two-wire serial interface bus enables read/write access to control and status regis-
ters within the ASX340/MT9V139. This interface is designed to be compatible with the
MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the elec-
trical characteristics and transfer protocols of the two-wire serial interface specification.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The sensor acts as a slave device. The master generates a clock
(SCLK) that is an input to the sensor and used to synchronize transfers.
Data is transferred between the master and the slave on a bidirectional signal (SDATA).
SDATA is pulled up to VDD_IO off-chip by a pull-up resistor in the range of 1.5 to 4.7kΩ
resistor.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of low-
level protocol elements, as follows:
•
•
•
•
•
•
a start or restart condition
a slave address/data direction byte
a 16-bit register address
an acknowledge or a no-acknowledge bit
data bytes
a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with
a start condition, and the bus is released with a stop condition. Only the master can gen-
erate the start and stop conditions.
The SADDR pin is used to select between two different addresses in case of conflict with
another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave
address is 0xBA. See Table 25 below.
Table 25:
Two-Wire Interface ID Address Switching
SADDR
Two-Wire Interface Address ID
0
1
0x90
0xBA
Start Condition
Data Transfer
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is low and must be stable while SCLK is HIGH.
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Slave Two-Wire Serial Interface
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default
slave addresses used by the ASX340/MT9V139 are 0x90 (write address) and 0x91 (read
address). Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can
be selected by asserting the SADDR input signal.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data. The protocol used is outside the scope of the
two-wire serial interface specification.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-
edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
Stop Condition
The no-acknowledge bit is generated when the receiver does not drive SDATA low during
the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi-
nate a read sequence.
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
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Slave Two-Wire Serial Interface
Typical Operation
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”
indicates a WRITE and a “1” indicates a READ. If the address matches the address of the
slave device, the slave device acknowledges receipt of the address by generating an
acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master will then transfer the 16-bit data, as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master stops writing by generating a (re)start or stop condition. If the
request was a READ, the master sends the 8-bit write slave address/data direction byte
and 16-bit register address, just as in the write request. The master then generates a
(re)start condition and the 8-bit read slave address/data direction byte, and clocks out
the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-
bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.
Single READ from Random Location
Figure 21 shows the typical READ cycle of the host to the ASX340/MT9V139. The first two
bytes sent by the host are an internal 16-bit register address. The following 2-byte READ
cycle sends the contents of the registers to host.
Figure 21:
Single READ from Random Location
M+1
P
Previous RegAddress, N
Reg Address, M
Read Data
Read Data
[7:0]
S
Slave Address
0
A
Reg Address[15:8]
A
Reg Address[7:0]
A
Sr Slave Address
1
A
A
A
[15:8]
S = start condition
P = stop condition
Sr =restart condition
A = acknowledge
slave to master
master toslave
A = no-acknowledge
Single READ from Current Location
Figure 22 shows the single READ cycle without writing the address. The internal address
will use the previous address value written to the register.
Figure 22:
Single Read from Current Location
Previous Reg Address, N
Reg Address, N+1
Slave Address
N+2
Read Data
[7:0]
Read Data
[15:8]
Read Data
[15:8]
Read Data
[7:0]
A
S
Slave Address
1
A
A
P
S
1 A
A
A P
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Slave Two-Wire Serial Interface
Sequential READ, Start from Random Location
This sequence (Figure 23) starts in the same way as the single READ from random loca-
tion (Figure 21 on page 42). Instead of generating a no-acknowledge bit after the first
byte of data has been transferred, the master generates an acknowledge bit and
continues to perform byte READs until “L” bytes have been read.
Figure 23:
Sequential READ, Start from Random Location
Previous Reg Address, N
Reg Address, M
M+1
A
Read Data
A
S
Slave Address
0
Reg Address[15:8]
A
Reg Address[7:0]
Sr
A
Slave Address
1
A
M+1
M+2
M+L-2
M+L-1
M+3
M+L
Read Data
(15:8)
Read Data
(15:8)
Read Data
(7:0)
Read Data
(15:8)
Read Data
(7:0)
Read Data
(7:0)
Read Data
(15:8)
Read Data
(7:0)
A
A
A
A
A
A
A
A
P
Sequential READ, Start from Current Location
This sequence (Figure 24) starts in the same way as the single READ from current loca-
tion (Figure 22). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte reads until “L” bytes have been read.
Figure 24:
Sequential READ, Start from Current Location
Previous Reg Address, N
N+1
A
N+2
A
N+L-1
N+L
P
Read Data
Read Data
Read Data
Read Data
(15:8)
Read Data
Read Data
(15:8)
Read Data
Read Data
A
A
A
A
A
S
Slave Address 1 A
(7:0)
(7:0)
(7:0)
A
(15:8)
(15:8)
(7:0)
Single Write to Random Location
Figure 25 shows the typical WRITE cycle from the host to the ASX340/MT9V139.The first
2 bytes indicate a 16-bit address of the internal registers with most-significant byte first.
The following 2 bytes indicate the 16-bit data.
Figure 25:
Single WRITE to Random Location
Previous Reg Address, N
Reg Address, M
Write Data
M+1
P
A
A
S
Slave Address
0
Reg Address[15:8]
Reg Address[7:0]
A
A
A
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Slave Two-Wire Serial Interface
Sequential WRITE, Start at Random Location
This sequence (Figure 26) starts in the same way as the single WRITE to random location
(Figure 25). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte writes until “L” bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 26:
Sequential WRITE, Start at Random Location
Previous Reg Address, N
Reg Address, M
Write Data
M+1
S
Slave Address
0
Reg Address[15:8]
A
Reg Address[7:0]
A
A
A
A
M+1
M+2
M+L-2
M+L-1
M+3
M+L
P
Write Data
Write Data
Write Data
(15:8)
Write Data
(7:0)
Write Data
Write Data
Write Data
Write Data
A
A
A
A
A
(15:8) (7:0)
A
A
(15:8) (7:0)
A
A
(15:8) (7:0)
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Capability
Overlay Capability
Figure 27 highlights the graphical overlay data flow of theASX340/MT9V139. The images
are separated to fit into 2KB blocks of memory after compression.
•
•
Up to four overlays may be blended simultaneously
Overlay size 360 x 480 pixels rendered into a display area of 720 x 480 pixels (NTSC) or
720 x 576 (PAL)
•
•
•
•
Selectable readout: rotating order is user programmable
Dynamic movement through predefined overlay images
Palette of 32 colors out of 64,000 with eight colors per bitmap
Blend factors may be changed dynamically to achieve smooth transitions
The host commands allow a bitmap to be written piecemeal to a memory buffer through
2
the I C, and also through DMA direct from SPI Flash memory. Multiple encoding passes
may be required to fit an image into a 2KB block of memory; alternatively, the image can
be divided into two or more blocks to make the image fit. Every graphic image may be
positioned in an x/y direction and overlap with other graphic images.
The host may load an image at any time. Under control of DMA assist, data are trans-
ferred to the off-screen buffer in compressed form. This assures that no display data are
corrupted during the replenishment of the four active overlay buffers.
Figure 27:
Overlay Data Flow
Overlay buffers: 2KB each
Flash
Decompress
Blend and Overlay
Bitmaps - compressed
Off-screen
buffer
Note:
These images are not actually rendered, but show conceptual objects and object blending.
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Serial Memory Partition
Serial Memory Partition
The contents of the Flash/EEPROM memory partition logically into three blocks (see
Figure 28):
•
•
•
Memory for overlay data and descriptors
Memory for register settings, which may be loaded at boot-up
Firmware extensions or software patches; in addition to the on-chip firmware, exten-
sions reside in this block of memory
These blocks are not necessarily contiguous.
Figure 28:
Memory Partitioning
Fixed-size
Fixed-size
Overlays – RLE
Flash
Overlays – RLE
Partitioning
12-byte Header
Overlay
Data
RLE Encoded
Data
2KB
Lens Shading
Correction
Parameter
Alternate
RegisterSetting
External Memory Speed Requirement
For a 2KB block of overlay to be transferred within a frame time to achieve maximum
update rate, the serial memory has to be a certain speed.
Table 26:
Transfer Time Estimate
Frame Time
SPI Clock
Transfer Time to 2KB
33.3ms
4.5 MHz
1ms
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Adjustment
Overlay Adjustment
To ensure a correct position of the overlay to compensate for assembly deviation, the
overlay can be adjusted with assistance from the overlay statistics engine:
•
•
•
•
The overlay statistics engine supports a windowed 8-bin luma histogram, either row-
wise (vertical) or column-wise (horizontal).
The example calibration statistics can be used to perform an automatic successive-
approximation search of a cross-hair target within the scene.
On the first frame, the firmware performs a coarse horizontal search, followed by a
coarse vertical search in the second frame.
In subsequent frames, the firmware reduces the region-of-interest of the search to the
histogram bins containing the greatest accumulator values, thereby refining the
search.
•
•
The resultant X, Y location of the cross-hair target can be used to assign a calibration
value of offset selected overlay graphic image positions within the output image.
The calibration statistics patch also supports a manual mode, which allows the host
to access the raw accumulator values directly.
Figure 29:
Overlay Calibration
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Overlay Character Generator
The position of the target will be used to determine the calibration value that shifts the
X,Y position of adjustable overlay graphics.
The overlay calibration is intended to be applied on a device by device basis “in system,”
which means after the camera has been installed. Aptina provides basic programming
scripts that may reside in the SPI Flash memory to assist in this effort.
Overlay Character Generator
In addition to the four overlay layers, a fifth layer exists for a character generator overlay
string.
There are a total of:
•
•
•
16 alphanumeric characters available
22 characters maximum per line
16 x 32 pixels with 1-bit color depth
Any update to the character generator string requires the string to be passed in its
entirety with the Host Command. Character strings have their own control properties
aside from the Overlay bitmap properties.
Figure 30:
Internal Block Diagram Overlay
BT656
Overlay
Layer3
Layer2
Layer1
Layer0
Register Bus
User Registers
Data Bus
DMA/CPU
Timing control
Number
Generator
ROM
BT656
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Overlay Character Generator
Character Generator
The character generator can be seen as the fifth top layer, but instead of getting the
source from RLE data in the memory buffers, it has a predefined 16 characters stored in
ROM.
All the characters are 1-bit depth color and are sharing the same YCbCr look up table.
Figure 31:
Example of Character Descriptor 0 Stored in ROM
ROM 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x00
0x02
0x04
0x06
0x08
0x0a
0x0c
0x0e
0x10
0x12
0x14
0x16
0x18
0x1a
0x1c
0x1e
0x20
0x22
0x24
0x26
0x28
0x2a
0x2c
0x2e
0x30
0x32
0x34
0x36
0x38
0x3a
0x3c
0x3e
…
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
It can show a row of up to 22 characters of 16 x 32 pixels resolution (32 x 32 pixels when
blended with the BT 656 data).
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Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Character Generator Details
Table 27 shows the characters that can be generated.
Table 27:
Item
Character Generator Details
Quantity
Description
16-bit character
1 bpp color
22
1
Coder for one of these characters: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /, (space), :, –, (comma), (period)
Depth of the bit map is 1 bpp
It is the responsibility of the user to set up proper values in the character positioning to
fit them in the same row (that is one of the reasons that 22 is the maximum number of
characters).
Note:
No error is generated if the character row overruns the horizontal or vertical limits of
the frame.
Full Character Set for Overlay
Figure 32 shows all of the characters that can be generated by theASX340/MT9V139.
Figure 32:
Full Character Set for Overlay
0x0 0x4 0x8 0xC
0x1 0x5 0x9 0xD
0x2 0x6 0xA 0xE
0x3 0x7 0xB 0xF
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Modes and Timing
This section provides an overview of the typical usage modes and related timing infor-
mation for theASX340/MT9V139.
Composite Video Output
The external pin DOUT_LSB0 can be used to configure the device for default NTSC or PAL
operation (auto-config mode). This and other video configuration settings are available
as register settings accessible through the serial interface.
NTSC
Both differential and single-ended connections of the full NTSC format are supported.
The differential connection that uses two output lines is used for low noise or long
distance applications. The single-ended connection is used for PCB tracks and screened
cable where noise is not a concern. The NTSC format has three black lines at the bottom
of each image for padding (which most LCDs do not display).
PAL
The PAL format is supported with 576 active image rows.
Single-Ended and Differential Composite Output
The composite output can be operated in a single-ended or differential mode by simply
changing the external resistor configuration. For single-ended termination, see
Figure 33 on page 51. The differential schematic is shown in Figure 34 on page 52.
Figure 33: Single-Ended Termination
V
DD
75Ω Terminated Receiver
Single-ended
e.g. PCB Track
e.g. 75Ω COAX
Chip
i = IMINUS
i = IPLUS
Boundary
75Ω
Single-Ended
75Ω
Single-ended
L 0
L2
L1
=
L
1uH
= 1uH
L
L = 2.2μH
C 0
C1
pF
pF
C = 330
C = 330
Typical Values for LC
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Modes and Timing
Figure 34:
Differential Connection—Grounded Termination
Parallel Output (DOUT)
The DOUT[7:0] port supports both progressive and Interlaced mode. Progressive mode
(with FV and LV signal) include raw bayer(8 or 10 bit), YCbCr, RGB. Interlaced mode is
CCIR656 compliant.
Figure 35 shows the data that is output on the parallel port for CCIR656. Both NTSC and
PAL formats are displayed. The blue values in Figure 35 represent NTSC (525/60). The
red values represent PAL (625/50).
Figure 35:
CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems
Start of digital line
Start of digital active line
Next line
EAV CODE
BLANKING
SAV CODE
CO-SITED
_
CO-SITED _
Digital
video
stream
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
B
C
R
C
B
C
R
C
R
F
F
Y
Y
Y
Y
Y
4
4
268
280
4
4
1440
1440
1716
1728
Figure 36 on page 53 shows detailed vertical blanking information for NTSC timing. See
Table 28 on page 53 for data on field, vertical blanking, EAV, and SAV states.
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 36:
Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System
Line 4
Line 1 (V = 1)
Line 20 (V = 0)
Line 264 (V = 1)
Blanking
Field 1 Active Video
Blanking
Field 1
(F = 0)
Odd
266
Field 2
(F = 1)
Even
Line 283 (V = 0)
Line 525 (V = 0)
Field 2 Active Video
H = 1
EAV
H = 0
SAV
Table 28:
Field, Vertical Blanking, EAV, and SAV States 525/60 Video System
H
(EAV)
H
(SAV)
Line Number
F
V
1–3
1
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
4–9
20–263
264–265
266–282
283–525
Figure 37 shows detailed vertical blanking information for PAL timing. See Table 29 on
page 54 for data on field, vertical blanking, EAV, and SAV states.
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 37:
Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System
Line 1 (V = 1)
Line 23 (V = 0)
Blanking
Field 1 Active Video
Blanking
Field 1
(F = 0)
Odd
Line 311 (V = 1)
Line 336 (V = 0)
Field 2
(F = 1)
Even
Field 2 Active Video
Blanking
Line 624 (V = 1)
Line 625 (V = 1)
H =1
EAV
H = 0
SAV
Table 29:
Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System
H
(EAV)
H
(SAV)
Line Number
F
V
1–22
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
23–310
311–312
313–335
336–623
624–625
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Reset and Clocks
Reset
Power-up reset is asserted or de-asserted with the RESET_BAR pin, which is active LOW.
In the reset state, all control registers are set to default values. See “Device Configura-
tion” on page 31 for more details on Auto, Host, and Flash configurations.
Soft reset is asserted or de-asserted by the two-wire serial interface program. In soft-
reset mode, the two-wire serial interface and the register bus are still running. All control
registers are reset using default values.
Clocks
The ASX340/MT9V139 has two primary clocks:
•
•
A master clock coming from the EXTCLK signal.
In default mode, a pixel clock (PIXCLK) running at 2 * EXTCLK. In raw Bayer bypass
mode, PIXCLK runs at the same frequency as EXTCLK.
When the ASX340/MT9V139 operates in sensor stand-alone mode, the image flow pipe-
line clocks can be shut off to conserve power.
The sensor core is a master in the system. The sensor core frame rate defines the overall
image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced
by the sensor configuration, and are also a function of certain image flow pipeline func-
tions. The relationship of the primary clocks is depicted in Figure 38.
The image flow pipeline typically generates up to 16 bits per pixel—for example, YCbCr
or 565RGB—but has only an 8-bit port through which to communicate this pixel data.
To generate NTSC or PAL format images, the sensor core requires a 27 MHz clock.
Figure 38:
Primary Clock Relationships
Sensor
Master Clock
EXTCLK
Sensor Core
Sensor
Pixel Clock
10 bits/pixel
1 pixel/clock
Colorpipe
16 bits/pixel
1 pixel/clock
Output Interface
16 bits/pixel (TYP)
0.5 pixel/clock
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Floating Inputs
The following ASX340/MT9V139 pins cannot be floated:
•
•
•
•
•
•
•
SDATA–This pin is bidirectional and should not be floated
FRAME_SYNC
TRST_N
SCLK
SADDR
ATEST1
ATEST2
Output Data Ordering
Table 30:
Output Data Ordering in DOUT RGB Mode
Mode
(Swap Disabled)
Byte
D7
D6
D5
D4
D3
D2
D1
D0
565RGB
First
Second
First
R7
G4
0
R6
G3
R7
G4
R6
B6
0
R5
G2
R6
G3
R5
B5
0
R4
B7
R5
B7
R4
B4
0
R3
B6
R4
B6
G7
0
G7
B5
R3
B5
G6
0
G6
B4
G7
B4
G5
0
G5
B3
G6
B3
G4
0
555RGB
444xRGB
x444RGB
Second
First
G5
R7
B7
0
Second
First
R7
B7
R6
B6
R5
B5
R4
B4
Second
G7
G6
G5
G4
Note:
PIXCLK is 54 MHz when EXTCLK is 27 MHz.
Table 31:
Output Data Ordering in Sensor Stand-Alone Mode
Mode
D7
D6
D5
D4
D3
D2
D1
D0
B2
DOUT_LSB1
DOUT_LSB0
B9
B8
B7
B6
B5
B4
B3
B1
B0
10-bit Output
Note:
PIXCLK is 27 MHz when EXTCLK is 27 MHz.
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
I/O Circuitry
Figure 39:
Figure 39 illustrates typical circuitry used for each input, output, or I/O pad.
Typical I/O Equivalent Circuits
V
DD_IO
Input Pad
Pad
Receiver
GND
DD_IO
V
SPI_SDI and RESET_BAR
Input Pad
Pad
Receiver
GND
VDD_IO
Receiver
I/O Pad
Pad
Slew
Rate
Control
GND
V
DD_IO
SCLK and XTAL_IN
Input Pad
Pad
Receiver
GND
XTAL
Pad
Output Pad
VDD_IO
GND
Note:
All I/O circuitry shown above is for reference only. The actual implementation may be different.
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 40:
NTSC Block
NTSC Block
VDD_DAC
Pad
DAC_REF
Pad
Pad
DAC_POS
DAC_NEG
ESD
ESD
ESD
Resistor
4.7kΩ/2.35kΩ
GND
Note:
All I/O circuitry shown above is for reference only. The actual implementation may be different.
Figure 41:
Serial Interface
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
I/O Timing
Digital Output
By default, the ASX340/MT9V139 launches pixel data, FV, and LV synchronously with the
falling edge of PIXCLK. The expectation is that the user captures data, FV, and LV using
the rising edge of PIXCLK. The timing diagram is shown in Figure 42.
As an option, the polarity of the PIXCLK can be inverted from the default by program-
ming R0x0016[14].
Figure 42:
Digital Output I/O Timing
t
extclk_period
Input
EXTC LK
PIXC LK
Output
t
t
pixclkf_dout
dout_ho
Output
Output
D
OUT [7 :0]
t
dout_su
t
fvlv_ho
t
pixclkf_fvlv
FR AM E_VALID
LIN E _VALID
t
fvlv_su
Table 32:
Parallel Digital Output I/O Timing
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate
Signal
Parameter
Conditions
Min
Typ
Max
Unit
EXTCLK
fextclk
max ±100 ppm
6
27
37
50
27
37.04
50
–
54
166.67
55
MHz
ns
textclk_period
Duty cycle
fpixclk
18.52
45
%
PIXCLK1
DATA[7:0]
FV/LV
6
54
MHz
ns
tpixclk_period
Duty cycle
tpixclkf_dout
tdout_su
18.52
45
166.67
55
%
0.97
6.83
2.74
1.15
6.72
5.74
2.42
8.28
6.32
2.53
8.1
ns
–
ns
tdout_ho
tpixclkf_fvlv
tfvlv_su
–
ns
–
ns
–
ns
tfvlv_ho
–
7.62
ns
Note:
PIXCLK can be inverted from the default by programming R0x0016[14].
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Modes and Timing
Slew Rate
Table 33:
Slew Rate for PIXCLK and DOUT
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VΑΑ_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; T = 25°C; CLOAD = 40 pF
PIXCLK
DOUT[7:0]
Typical
Rise Time
Typical
Fall Time
Typical
Rise Time
Typical
Fall Time
R0x30 [10:8]
R0x30 [2:0]
Unit
000
001
010
011
100
101
110
111
6.5
4.8
3.9
3.7
3.6
3.5
3.4
3.3
6.3
4.6
3.8
3.7
3.6
3.5
3.4
3.3
000
001
010
011
100
101
110
111
6.5
4.8
3.9
3.7
3.6
3.5
3.4
3.3
6.3
4.6
3.8
3.7
3.6
3.5
3.4
3.3
ns
ns
ns
ns
ns
ns
ns
ns
Figure 43:
Slew Rate Timing
90%
10%
PIXCLK
t
ris e
tfa ll
90%
10%
D
OUT
tris e
t
fa ll
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Modes and Timing
Configuration Timing
During start-up, the Dout_LSB0, LV and FV are sampled. Setup and hold timing for the
RESET_BAR signal with respect to DOUT_LSB0, LV, and FV are shown in Figure 44 and
Table 34. These signals are sampled once by the on-chip firmware, which yields a long
t
Hold time.
Figure 44:
Configuration Timing
RESET_BAR
t
t
SETUP
HOLD
DOUT_LSB0
FRAME_VALID
LINE_VALID
Valid Data
Table 34:
Configuration Timing
Signal
Parameter
Min
Typ
Max
Unit
t
DOUT_LSB0, FRAME_VALID, LINE_VALID
SETUP
0
μs
μs
t
HOLD
50
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Modes and Timing
Figure 45:
Power Up Sequence
VDD_PLL
VDD_DAC (2.8)
t0
VAA_PIX
VAA (2.8)
t1
VDD_IO (2.8)
t2
VDD (1.8)
tx
EXTCLK
RESET_BAR
t4
t5
t3
Internal
(NTSC/PAL)
Initialization
Hard Reset
Patch Config
SPI or Host
Streaming
Notes: 1. RESET_BAR may not exceed VDD_IO + 0.3V.
2. The 2.8V plane (VAA, VAA_PIX, VDD_PLL, VDD_DAC, VDD_IO) must remain at a higher voltage than the
1.8V core voltage at all times.
Table 35:
Power Up Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD_PLL to VAA/VAA_PIX
VAA/VAA_PIX to VDD_IO
VDD_IO to VDD
t0
t1
t2
tx
t3
t4
t5
0
0
–
–
–
–
–
–
–
–
–
μS
μS
μS
0
–
301
Xtal settle time
–
mS
Hard Reset
102
50
–
–
Clock cycle
mS
Internal Initialization
Patch Load (SPI or I2C)
–
4003
mS
Notes: 1. Xtal settling time is component-dependent (Xtal, Oscillator, and so on) and usually takes about 10mS
~100mS.
2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are required
for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is performed by
the RC circuit, then the RC time must include the all power rail settle time and Xtal
3. This is required to load necessary patches using Flash mode (SPI) or Host mode (two-wire serial inter-
face). Loading time varies depending on the number of patches and bus speed.
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 46:
Power Down Sequence
V
DD (1.8)
t0
V
DD_IO (2.8)
t1
VAA_PIX
VAA (2.8)
t2
VDD_PLL
V
DD_DAC (2.8)
EXTCLK
t3
Power Down until next Power Up Cycle
Table 36:
Power Down Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD to VDD_IO
t0
t1
t2
t3
0
0
–
–
–
–
–
–
–
–
μS
μS
μS
ms
VDD_IO to VAA/VAA_PIX
VAA/VAA_PIX to VDD_PLL/DAC
0
1001
Power Down until Next Power Up Time
(1) t3 is required between power down and next power up time, all decoupling caps from
regulators must completely discharged before next power up.
Figure 47:
FRAME_SYNC to FRAME_VALID/LINE_VALID
tFRAME_SYNC
FRAME_SYNC
tFRMSYNH_FVH
FRAME_VALID
LINE_VALID
Table 37:
FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters
Parameter
Name
Conditions
Min
Typ
Max
Unit
FRAME_SYNC to FV/LV
tFRAME_SYNC
tFRMSYNC_FVH
tFRAMESYNC
Auto Config mode
4
–
–
ms
ms
30
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Modes and Timing
Figure 48:
Reset to SPI Access Delay
R ESET_BAR
tRSTH_CSL
SPI_CS_N
Figure 49:
Reset to Serial Access Delay
RESET_BAR
tRSTH_SDATAL
SDATA
Figure 50:
Reset to AE/AWB Image
RESET_BAR
VIDEO
First Frame
Overlay from
Flash
AE/AWB settled
tRSTH_FVL
tRSTH_OVL
tRSTH_AEAWB
Table 38:
RESET_BAR Delay Parameters
Parameter
Name
Condition
Min
Typ
Max
Unit
Power up delay 2.8V to 1.8V
0.1
18
–
–
–
–
–
–
–
–
ms
ms
ms
ms
ms
ms
RESET_BAR HIGH to SPI_CS_N LOW
RESET_BAR HIGH to SDATA LOW
RESET_BAR HIGH to FRAME_VALID
RESET_BAR HIGH to first Overlay
RESET_BAR HIGH to AE/AWB settled
tRSTH_CSL
tRSTH_SDATAL
tRSTH_FVL
1.8
235
235
–
–
–
tRSTH_OVL
–
tRSTH_AEAWB
400
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Electrical Specifications
Electrical Specifications
Figure 51:
SPI Output Timing
tCS_SCLK
SPI_CS_N
SPI_SCLK
SPI_SDI
tSCLK_SDO
ts u
SPI_SDO
Table 39:
SPI Data Setup and Hold Timing
Parameter
Description
Min
Typ
Max
Units
fSPI_SCLK
tsu
tSCLK_SDO
tCS_SCLK
SPI_SCLK Frequency
1.6875
–
4.5
–
18
110
110
–
MHz
ns
Setup time
Hold time
ns
Delay from falling edge of SPI_CS_N to rising edge of SPI_SCLK
–
230
ns
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Caution Stresses greater than those listed in Table 40 may cause permanent damage to the device. This is
a stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Table 40:
Absolute Maximum Ratings
Rating
Symbol
Parameter
Min
Max
Unit
Digital power (1.8V)
I/O power (2.8v)
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-50
2.4
V
V
V
V
V
V
V
V
°C
VDD
4
VDD_IO
VAA
VAA Analog power (2.8V)
Pixel array power (2.8v)
PLL power (2.8V)
4
4
VAA_PIX
VDD_PLL
VDD_DAC
VIN
4
4
DAC power (2.8V)
DC Input Voltage
VDD_IO+0.3
VDD_IO+0.3
150
DC Output Voltage
Storage temperature
VOUT
TSTG
Table 41:
Electrical Characteristics and Operating Conditions
Condition
Parameter1
Min
Typ
Max
Unit
Core digital voltage (VDD)
IO digital voltage (VDD_IO)
Video DAC voltage (VDD_DAC)
PLL Voltage (VDD_PLL)
–
1.7
1.8
2.8
2.8
2.8
2.8
2.8
1.9
2.94
2.94
2.94
2.94
2.94
10
V
V
–
2.66
2.66
2.66
2.66
2.66
–
V
–
V
Analog voltage (VAA)
–
V
Pixel supply voltage (VAA_PIX)
Leakage current
–
V
EXTCLK: HIGH or LOW
μA
°C
°C
Imager operating temperature
Storage temperature
–
–
–30
–50
+70
+150
Notes: 1. VAA and VAA_PIX must all be at the same potential to avoid excessive current draw. Care must be taken
to avoid excessive noise injection in the analog supplies if all three supplies are tied together.
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Electrical Specifications
Table 42:
Video DAC Electrical Characteristics–Single-Ended Mode
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter
Condition
Min
Typ
Max
Unit
Resolution
DNL
–
–
–
–
–
–
–
–
–
–
–
–
10
0.2
-
bits
bits
bits
Ω
Ω
V
0.4
INL
0.7
3.5
Output local load
Output pad (DAC_POS)
Unused output (DAC_NEG)
Single-ended mode, code 000h
Single-ended mode, code 3FFh
Single-ended mode, code 000h
Single-ended mode, code 3FFh
Estimate
75
-
0
-
Output voltage
Output current
.02
-
1.30
0.26
17.33
-
-
V
-
mA
mA
mA
V
-
Supply current
DAC_REF
25.0
DAC Reference
1.15 +/-0.2
4.7
-
-
R DAC_REF
DAC Reference
KΩ
Table 43:
Video DAC Electrical Characteristics–Differential Mode
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter
Condition
Min
Typ
Max
Unit
DNL
INL
–
–
–
0.2
0.8
0.25
2.5
–
Bits
Bits
Ω
Output local load
Differential mode per pad
(DAC_POS and DAC_NEG)
37.5
Output voltage
Differential mode, code 000h, pad dacp
Differential mode, code 000h, pad dacn
Differential mode, code 3FFh, pad dacp
Differential mode, code 3FFH, pad dacn
Differential mode, code 000h, pad dacp
Differential mode, code 000h, pad dacn
Differential mode, code 3FFh, pad dacp
Differential mode, code 3FFH, pad dacn
–
–
–
–
–
–
–
–
–
.02
1.30
1.30
.02
–
–
–
–
–
–
–
–
–
V
V
V
V
Output current
.53
mA
mA
mA
mA
V
34.7
34.7
.53
Differential output,
midlevel
0.65
Supply current
DAC_REF
Estimate
–
–
–
50
mA
V
DAC Reference
DAC Reference
1.15 +/-0.2
2.35
R DAC_REF
KΩ
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Table 44:
Signal
Digital I/O Parameters
TA = Ambient = 25°C; All supplies at 2.8V
Parameter Definitions
Condition
Min
Typ
Max
Unit
All
Outputs
Load capacitance
5
–
–
30
–
pF
V/ns
V/ns
V
Output signal slew
2.8V, 30pF load
2.8V, 5pF load
–
–
–
–
VOH
VOL
IOH
Output high voltage
Output low voltage
Output high current
–
VDD_IO
–
–0.3
–
–
–
–
V
VDD = 2.8V, VOH
= 2.4V
8
mA
IOL
Output low current
VDD = 2.8V, VOL =
0.4V
–
–
8
mA
All Inputs
VIH
VIL
IIN
Input high voltage
Input low voltage
Input leakage current
VDD = 2.8V
VDD = 2.8V
0.7 * VDD_IO
–
–
VDD_IO + 0.3
V
V
–0.3
–2
–
0.3 * VDD_IO
–
2
–
μA
pF
Signal CAP Input signal
capacitance
3.5
Notes: 1. All inputs are protected and may be active when All supplies (2.8V and 1.8V) are turned off.
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ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Power Consumption, Operating Mode
Table 45:
Power Consumption – Condition 1
fEXTCLK = 27 MHz; VDD = 1.8V; VDD _IO = 2.8V; VAA =2.8V;VAA_PIX=2.8V;
VDD _PLL = 2.8V; VDD _DAC = 2.8V
Power Plane
Supply
Condition 1
Typ Power
Max Power
Unit
VDD
1.8
2.8
2.8
2.8
2.8
2.8
55
5
65
10
mW
mW
mW
mW
mW
mW
mW
VDD_IO
VAA
Parallel off
95
112
5
VAA_PIX
VDD_DAC
VDD_PLL
2.5
65
Single 75Ω
70
20
25
Total
242.5
287
Analog output uses single-ended mode: DAC_Pos = 75Ω, DAC_Neg = open, parallel
output is disabled.
Table 46:
Power Consumption – Condition 2
fEXTCLK = 27 MHz; VDD = 1.8V; VDD _IO = 2.8V; VAA =2.8V;VAA_PIX=2.8V;
VDD _PLL = 2.8V; VDD _DAC = 2.8V
Power Plane
Supply
Condition 2
Typ Power
Max Power
Unit
VDD
1.8
2.8
2.8
2.8
2.8
2.8
55
30
65
50
112
5
mW
mW
mW
mW
mW
mW
mW
VDD_IO
VAA
Parallel on
95
VAA_PIX
VDD_DAC
VDD_PLL
2.5
2
VDAC off
Total
5
20
25
262
204.5
Analog output is disabled; parallel output is enabled.
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Electrical Specifications
NTSC Signal Parameters
Table 47:
NTSC Signal Parameters
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter
Conditions
Min
Typ
Max
Units
Notes
Line Frequency
Field Frequency
Sync Rise Time
Sync Fall Time
Sync Width
15734.25
59.94
148
15734.27
59.94
148
15734.28
59.94
148
Hz
Hz
ns
148
148
148
ns
4.74
38
4.74
4.74
42
μs
IRE
IRE
μs
Sync Level
39.9
2, 4
2, 4
Burst Level
38
39.7
42
Sync to Setup
9.44
9.44
9.44
(with pedestal off)
Sync to Burst Start
Front Porch
5.33
1.33
6.5
5.33
1.33
7.5
5.33
1.33
8.5
μs
μs
IRE
IRE
Black Level
1, 2, 4
White Level
90
100
110
1, 2, 3, 4
Notes: 1. Black and white levels are referenced to the blanking level.
2. NTSC convention standardized by the IRE (1 IRE = 7.14mV).
3. Encoder contrast setting R0x011 = R0x001 = 0.
4. DAC ref = 2.8kΩ, load = 37.5Ω.
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Electrical Specifications
Figure 52:
Video Timing
A
D
E
C
B
J
F
K
H
G
H
Table 48:
Video Timing
NTSC
27 MHz
PAL
27 MHz
Signal
Units
A
B
C
D
E
H Period
1716
144
63
1728
153
66
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
Clocks
Hsync to burst
burst
Hsync to Signal
Video Signal
Front
255
1423
36
279
1413
39
F
G
H
J
Hsync Period
128
4
128
4
Sync rising/falling edge
Back overscan (BOS)
Front overscan (FOS)
9
14
K
8
13
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Electrical Specifications
Figure 53:
Equivalent Pulse
L
I
J
K
K
Table 49:
Equivalent Pulse
NTSC
27 MHz
PAL
27 MHz
Signal
Units
I
J
H/2 Period
Pulse width
858
64
4
864
64
4
Clocks
Clocks
Clocks
Clocks
K
L
Pulse rising/falling edge
Signal to pulse
38
41
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Electrical Specifications
Figure 54:
V Pulse
M
O
N
P
P
Table 50:
V Pulse
NTSC
27 MHz
PAL
27 MHz
Signal
Units
M
N
O
P
H/2 Period
Pulse width
858
730
128
4
864
736
128
4
Clocks
Clocks
Clocks
Clocks
V pulse interval
Pulse rising/falling edge
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Electrical Specifications
Two-Wire Serial Bus Timing
Figure 55 and Table 51 describe the timing for the two-wire serial interface.
Figure 55:
Two-Wire Serial Bus Timing Parameters
Write Sequence
tSTPH
tSDS
tSRTH
tAHSW
tSHAW
tSTPS
tSCLK
tSDH
SCLK
SDATA
Write
Address
Bit 7
Write
Address
Bit 0
Register
Value
Bit 7
Register
Value
Bit 0
Stop
Write Start
Ack
tSDSR
Read Sequence
SCLK
tSDHR
tSHAR
tAHSR
SDATA
Read
Address
Bit 7
Read
Address
Bit 0
Register
Value
Bit 7
Register
Value
Bit 0
Ack
Read Start
Table 51:
Parameter
Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Standard-Mode
Fast-Mode
Symbol
Min
Max
Min
Max
Unit
SCLK Clock Frequency
fSCL
0
100
0
400
KHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD;STA
4.0
-
0.6
-
μS
LOW period of the SCLK clock
HIGH period of the SCLK clock
tLOW
tHIGH
4.7
4.0
4.7
-
-
-
1.3
0.6
0.6
-
-
-
μS
μS
μS
Set-up time for a repeated START
condition
tSU;STA
Data hold time:
tHD;DAT
tSU;DAT
tr
04
250
-
3.455
-
06
1006
20 + 0.1Cb7
20 + 0.1Cb7
0.6
0.95
-
μS
nS
nS
nS
μS
Data set-up time
Rise time of both SDATA and SCLK signals
Fall time of both SDATA and SCLK signals
Set-up time for STOP condition
1000
300
-
300
300
-
tf
-
tSU;STO
4.0
PDF: 171981479/Source: 8304342517
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
Aptina reserves the right to change products or specifications without notice.
© 2010 Aptina Imaging Corporation All rights reserved.
74
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Table 51:
Parameter
Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Standard-Mode
Fast-Mode
Symbol
Min
Max
Min
Max
Unit
Bus free time between a STOP and START
condition
tBUF
4.7
-
1.3
-
μS
Capacitive load for each bus line
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull-up resistor
Cb
CIN_SI
CLOAD_SD
RSD
-
-
400
3.3
30
-
-
400
3.3
30
pF
pF
-
-
pF
1.5
4.7
1.5
4.7
KΩ
Notes: 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I2C-compatible.
3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the unde-
fined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must out-
put the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Stan-
dard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
PDF: 171981479/Source: 8304342517
Aptina reserves the right to change products or specifications without notice.
ASX340/MT9V139_DS Rev. C Pub. 3/11 EN
75
© 2010 Aptina Imaging Corporation All rights reserved.
Package and Die Dimensions
Figure 56:
63-Ball cBGA Package Outline Drawing
Figure 57:
63-Ball CSP Package Outline Drawing
Aptina Confidential and Proprietary
Preliminary
ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Revision History
Revision History
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/14/11
•
•
•
•
•
•
•
•
•
Changed Part number to ASX340
Updated “Features” on page 1
Updated Table 1, “Key Parameters,” on page 1
Updated Table 3, “Available Part Numbers,” on page 3
Updated “New Features” on page 3
Updated Table 4, “Pin Descriptions,” on page 12
Updated Table 5, “Pin Assignments,” on page 14
Updated “Device Configuration” on page 31
Updated Figure 19: “Power-Up Sequence – Configuration Options Flow Chart,” on
page 32
•
Added Figure 56: “63-Ball cBGA Package Outline Drawing,” on page 76
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/11/10
•
•
•
Remove note from Table 2, “Key Parameters (continued),” on page 2
Updated Table 4, “Pin Descriptions,” on page 12
Updated Table 35, “Power Up Sequence,” on page 62 and Table 36, “Power Down
Sequence,” on page 63
•
Updated Table 45, “Power Consumption – Condition 1,” on page 69, Table 46, “Power
Consumption – Condition 2,” on page 69 on, and Table 47, “NTSC Signal Parameters,”
on page 70
•
•
•
•
Changed 15–33 pF to 15-22 pF in“Crystal Usage” on page 11
UpdatedTable 20, “Interface Structure,” on page 34
UpdatedTable 38, “RESET_BAR Delay Parameters,” on page 64
UpdatedTable 41, “Electrical Characteristics and Operating Conditions,” on page 66
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/6/10
Initial release
•
10 Eunos Road 8 13-40, Singapore Post Center, Singapore 408600 prodmktg@aptina.com www.aptina.com
Aptina, Aptina Imaging, and the Aptina logo are the property of Aptina Imaging Corporation
All other trademarks are the property of their respective owners.
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
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-ASX340/MT9V139_DS Rev. B Pub. 3/11 EN
AAptina reserves the right to change products or specifications without notice.
© 2010 Aptina Imaging Corporation All rights reserved.
78
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