AT24C64AY1-10Y1-2.7 [ETC]
EEPROM ; EEPROM\n
| 型号： | AT24C64AY1-10Y1-2.7 |
| 厂家： | 
ETC |
| 描述： | EEPROM
|
| 文件： | 总20页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-Voltage and Standard-Voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• Low-Power Devices (ISB = 2 µA @ 5.5V) Available
• Internally Organized 4096 x 8, 8192 x 8
• 2-Wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 100 kHz (1.8V) and 400 kHz (2.5V) Clock Rate for AT24C32A
• 400 kHz (1.8V) Clock Rate for AT24C64A
• Write Protect Pin for Hardware Data Protection
• 32-Byte Page Write Mode (Partial Page Writes Allowed)
• Self-Timed Write Cycle (10 ms max)
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8132 x 8)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP Packages
Description
AT24C32A
AT24C64A
The AT24C32A/64A provides 32,768/65,536 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2-
wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT24C32A/64A is
available in space saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead MAP and
8-lead TSSOP packages and is accessed via a 2-wire serial interface. In addition, the
entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Pin Configurations
8-lead SOIC
Pin Name
A0 - A2
SDA
Function
8-lead MAP
Address Inputs
Serial Data
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
1
2
3
4
VCC
WP
8
7
6
5
A0
A1
A2
SCL
SDA
SCL
SDA
A2
GND
SCL
Serial Clock Input
Write Protect
GND
WP
Bottom View
8-lead PDIP
8-lead TSSOP
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
A0
A1
A2
1
2
3
4
8
7
6
5
VCC
WP
A2
SCL
SDA
SCL
SDA
GND
GND
Rev. 3054E–SEEPR–10/02
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
2
AT24C32A/64A
3054E–SEEPR–10/02
AT24C32A/64A
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address
inputs that are hard wired or left not connected for hardware compatibility with
AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be
addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hardwired, the default A2, A1, and A0
are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write
operations. When WP is tied high to VCC, all write operations to the memory are inhib-
ited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior
to a write operation creates a software write protect function.
Memory Organization AT24C32A/64A, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as
128/256 pages of 32 bytes each. Random word addressing requires a 12/13-bit data
word address.
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3054E–SEEPR–10/02
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
CC = +1.8V to +5.5V (unless otherwise noted).
V
Symbol
Parameter
Test Condition
Min
1.8
2.5
2.7
4.5
Typ
Max
5.5
5.5
5.5
5.5
1.0
3.0
0.1
2.0
0.5
2.0
0.5
2.0
Units
V
VCC1
VCC2
VCC3
VCC4
ICC1
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
V
V
V
VCC = 5.0V
VCC = 5.0V
READ at 100 kHz
WRITE at 100 kHz
0.4
2.0
mA
mA
µA
ICC2
V
V
V
V
V
V
CC = 1.8V
CC = 5.5V
CC = 2.5V
CC = 5.5V
CC = 2.7V
CC = 5.5V
Standby Current
ISB1
ISB2
ISB3
VIN = VCC or VSS
(1.8V option)
µA
µA
Standby Current
(2.5V option)
V
V
IN = VCC or VSS
Standby Current
(2.7V option)
IN = VCC or VSS
Standby Current
(5V option)
ISB4
V
CC = 4.5 - 5.5V
VIN = VCC or VSS
20
35
3.0
3.0
µA
µA
µA
Input Leakage
Current
ILI
VIN = VCC or VSS
0.10
0.05
Output Leakage
Current
ILO
VOUT = VCC or VSS
VIL
VIH
Input Low Level(1)
Input High Level(1)
Output Low Level
Output Low Level
-0.6
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
VCC x 0.7
VOL2
VOL1
Note:
VCC = 3.0V
VCC = 1.8V
IOL = 2.1 mA
IOL = 0.15 mA
0.2
1. VIL min and VIH max are reference only and are not tested.
4
AT24C32A/64A
3054E–SEEPR–10/02
AT24C32A/64A
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
AT24C32A
2.5V – 5.0V
AT24C64A
1.8V – 3.6V
1.8V
5.0V
Symbol
fSCL
tLOW
tHIGH
tI
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
100
400
400
400
4.7
4.0
1.3
0.6
1.3
0.6
1.2
0.6
µs
100
4.5
50
100
0.9
50
ns
tAA
0.1
4.7
0.1
1.3
0.9
0.2
1.3
0.1
1.2
0.9
µs
Time the bus must be free
before a new transmission can
start(2)
tBUF
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
4.0
4.7
0
0.6
0.6
0
0.6
0.6
0
0.6
0.6
0
µs
µs
µs
ns
µs
ns
µs
ns
ms
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(2)
Inputs Fall Time(2)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
200
100
100
100
1.0
0.3
0.3
0.3
tF
300
300
300
300
tSU.STO
tDH
4.7
0.6
50
0.6
0.6
50
100
200
tWR
20
10
20
10
Write
Cycles
Endurance(1) 5.0V, 25°C, Page Mode
1M
1M
1M
1M
Notes: 1. This parameter is characterized and is not 100% tested (TA = 25°C).
2. This parameter is characterized and is not 100% tested.
5
3054E–SEEPR–10/02
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32A/64A features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6
AT24C32A/64A
3054E–SEEPR–10/02
AT24C32A/64A
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
(1)
tWR
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
3054E–SEEPR–10/02
Data Validity
Start and Stop Definition
Output Acknowledge
8
AT24C32A/64A
3054E–SEEPR–10/02
AT24C32A/64A
Device Addressing
The 32K/64K EEPROM requires an 8-bit device address word following a start condition
to enable the chip for a read or write operation (refer to Figure 1). The device address
word consists of a mandatory one, zero sequence for the first four most significant bits
as shown. This is common to all 2-wire EEPROM devices.
The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare to their corresponding hardwired
input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them
to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the device will return to standby state.
DATA SECURITY: The AT24C32A/64A has a hardware data protection scheme that
allows the user to write protect the entire memory when the WP pin is at VCC
.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condi-
tion. At this time the EEPROM enters an internally-timed write cycle, tWR, to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (refer to Figure 2).
PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 31
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (refer
to Figure 3).
The data word address lower 5 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 32 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.
9
3054E–SEEPR–10/02
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page, to the first
byte of the first page. The address “roll over” during write is from the last byte of the cur-
rent page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 5).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condi-
tion (refer to Figure 6).
10
AT24C32A/64A
3054E–SEEPR–10/02
AT24C32A/64A
Figure 1. Device Address
Figure 2. Byte Write
Figure 3. Page Write
Notes: 1. * = DON’T CARE bits
2. † = DON’T CARE bits for the 32K
Figure 4. Current Address Read
11
3054E–SEEPR–10/02
Figure 5. Random Read
Note:
1. * = DON’T CARE bits
Figure 6. Sequential Read
12
AT24C32A/64A
3054E–SEEPR–10/02
AT24C32A/64A
AT24C32A Ordering Information
Ordering Code
Package
Operation Range
AT24C32A-10PI-2.7
AT24C32AN-10SI-2.7
AT24C32A-10TI-2.7
AT24C32AY1-10YI-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C32A-10PI-1.8
AT24C32AN-10SI-1.8
AT24C32A-10TI-1.8
AT24C32AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
High Grade/Extended Temperature
AT24C32AN-10SE-2.7
8S1
(-40°C to 125°C)
Note:
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
8P3
8S1
8A2
8Y1
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
13
3054E–SEEPR–10/02
AT24C64A Ordering Information
Ordering Code
Package
Operation Range
AT24C64A-10PI-2.7
AT24C64AN-10SI-2.7
AT24C64A-10TI-2.7
AT24C64AY1-10Y1-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
AT24C64A-10PI-1.8
AT24C64AN-10SI-1.8
AT24C64A-10TI-1.8
AT24C64AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85°C)
High Grade/Extended Temperature
AT24C64AN-10SE-2.7
8S1
(-40°C to 125°C)
Note:
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8P3
8S1
8A2
8Y1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
14
AT24C32A/64A
3054E–SEEPR–10/02
AT24C32A/64A
Package Type
Options
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
15
3054E–SEEPR–10/02
Package Drawings
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
16
AT24C32A/64A
3054E–SEEPR–10/02
AT24C32A/64A
8S1 – JEDEC SOIC
1
3
2
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.75
0.51
0.25
5.00
4.00
NOM
NOTE
SYMBOL
A
B
C
D
E
e
–
A2
L
–
–
–
–
–
–
–
–
1.27 BSC
E
H
L
–
–
–
–
6.20
1.27
End View
Note:
This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
A
R
Small Outline (JEDEC SOIC)
17
3054E–SEEPR–10/02
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
18
AT24C32A/64A
3054E–SEEPR–10/02
AT24C32A/64A
8Y1 – MAP
PIN 1 INDEX AREA
A
1
3
4
2
PIN 1 INDEX AREA
E1
D1
D
L
8
6
5
7
b
e
A1
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
–
MAX
0.90
0.05
5.10
3.20
1.15
1.15
0.35
NOM
–
NOTE
A
A1
D
0.00
4.70
2.80
0.85
0.85
0.25
–
4.90
3.00
1.00
1.00
0.30
0.65 TYP
0.60
E
D1
E1
b
e
L
0.50
0.70
7/25/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
8Y1
B
R
19
3054E–SEEPR–10/02
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Printed on recycled paper.
3054E–SEEPR–10/02
xM
相关型号：
AT24C64B-10PU-1.8
EEPROM, 8KX8, Serial, CMOS, PDIP8, 0.300 INCH, GREEN, PLASTIC, MS-001BA, DIP-8
ATMEL
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